unknown changes from android-tegra-nv-3.4
[linux-3.10.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *  This program is free software; you can redistribute it and/or modify it
12  *  under the terms of the GNU General Public License as published by the Free
13  *  Software Foundation; either version 2 of the License, or (at your option)
14  *  any later version.
15  *
16  *  This program is distributed in the hope that it will be useful, but WITHOUT
17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
19  *  more details.
20  *
21  *  You should have received a copy of the GNU General Public License along with
22  *  this program; if not, write to the Free Software Foundation, Inc., 59
23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
24  *
25  *  CONTACTS:
26  *
27  *  Matt Jared          matt.jared@intel.com
28  *  Andy Kopp           andy.kopp@intel.com
29  *  Dan Kogan           dan.d.kogan@intel.com
30  *
31  *  CHANGES:
32  *
33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
34  *
35  */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53 #include <linux/clk.h>
54
55 #ifdef CONFIG_X86
56 /* for snoop control */
57 #include <asm/pgtable.h>
58 #include <asm/cacheflush.h>
59 #endif
60 #include <sound/core.h>
61 #include <sound/initval.h>
62 #include <linux/vgaarb.h>
63 #include <linux/vga_switcheroo.h>
64 #include <linux/firmware.h>
65 #include "hda_codec.h"
66
67
68 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
69 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
70 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
71 static char *model[SNDRV_CARDS];
72 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
73 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
74 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int probe_only[SNDRV_CARDS];
76 static int jackpoll_ms[SNDRV_CARDS];
77 static bool single_cmd;
78 static int enable_msi = -1;
79 #ifdef CONFIG_SND_HDA_PATCH_LOADER
80 static char *patch[SNDRV_CARDS];
81 #endif
82 #ifdef CONFIG_SND_HDA_INPUT_BEEP
83 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
84                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
85 #endif
86
87 module_param_array(index, int, NULL, 0444);
88 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
89 module_param_array(id, charp, NULL, 0444);
90 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
91 module_param_array(enable, bool, NULL, 0444);
92 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
93 module_param_array(model, charp, NULL, 0444);
94 MODULE_PARM_DESC(model, "Use the given board model.");
95 module_param_array(position_fix, int, NULL, 0444);
96 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
97                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
98 module_param_array(bdl_pos_adj, int, NULL, 0644);
99 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
100 module_param_array(probe_mask, int, NULL, 0444);
101 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
102 module_param_array(probe_only, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
104 module_param_array(jackpoll_ms, int, NULL, 0444);
105 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
106 module_param(single_cmd, bool, 0444);
107 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
108                  "(for debugging only).");
109 module_param(enable_msi, bint, 0444);
110 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
111 #ifdef CONFIG_SND_HDA_PATCH_LOADER
112 module_param_array(patch, charp, NULL, 0444);
113 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
114 #endif
115 #ifdef CONFIG_SND_HDA_INPUT_BEEP
116 module_param_array(beep_mode, bool, NULL, 0444);
117 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
118                             "(0=off, 1=on) (default=1).");
119 #endif
120
121 #ifdef CONFIG_PM
122 static int param_set_xint(const char *val, const struct kernel_param *kp);
123 static struct kernel_param_ops param_ops_xint = {
124         .set = param_set_xint,
125         .get = param_get_int,
126 };
127 #define param_check_xint param_check_int
128
129 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
130 module_param(power_save, xint, 0644);
131 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
132                  "(in second, 0 = disable).");
133
134 /* reset the HD-audio controller in power save mode.
135  * this may give more power-saving, but will take longer time to
136  * wake up.
137  */
138 static bool power_save_controller = 1;
139 module_param(power_save_controller, bool, 0644);
140 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
141 #endif /* CONFIG_PM */
142
143 static int align_buffer_size = -1;
144 module_param(align_buffer_size, bint, 0644);
145 MODULE_PARM_DESC(align_buffer_size,
146                 "Force buffer and period sizes to be multiple of 128 bytes.");
147
148 #ifdef CONFIG_X86
149 static bool hda_snoop = true;
150 module_param_named(snoop, hda_snoop, bool, 0444);
151 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
152 #define azx_snoop(chip)         (chip)->snoop
153 #else
154 #define hda_snoop               true
155 #define azx_snoop(chip)         true
156 #endif
157
158
159 MODULE_LICENSE("GPL");
160 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
161                          "{Intel, ICH6M},"
162                          "{Intel, ICH7},"
163                          "{Intel, ESB2},"
164                          "{Intel, ICH8},"
165                          "{Intel, ICH9},"
166                          "{Intel, ICH10},"
167                          "{Intel, PCH},"
168                          "{Intel, CPT},"
169                          "{Intel, PPT},"
170                          "{Intel, LPT},"
171                          "{Intel, LPT_LP},"
172                          "{Intel, HPT},"
173                          "{Intel, PBG},"
174                          "{Intel, SCH},"
175                          "{ATI, SB450},"
176                          "{ATI, SB600},"
177                          "{ATI, RS600},"
178                          "{ATI, RS690},"
179                          "{ATI, RS780},"
180                          "{ATI, R600},"
181                          "{ATI, RV630},"
182                          "{ATI, RV610},"
183                          "{ATI, RV670},"
184                          "{ATI, RV635},"
185                          "{ATI, RV620},"
186                          "{ATI, RV770},"
187                          "{VIA, VT8251},"
188                          "{VIA, VT8237A},"
189                          "{SiS, SIS966},"
190                          "{ULI, M5461}}");
191 MODULE_DESCRIPTION("Intel HDA driver");
192
193 #ifdef CONFIG_SND_VERBOSE_PRINTK
194 #define SFX     /* nop */
195 #else
196 #define SFX     "hda-intel "
197 #endif
198
199 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
200 #ifdef CONFIG_SND_HDA_CODEC_HDMI
201 #define SUPPORT_VGA_SWITCHEROO
202 #endif
203 #endif
204
205
206 /*
207  * registers
208  */
209 #define ICH6_REG_GCAP                   0x00
210 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
211 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
212 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
213 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
214 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
215 #define ICH6_REG_VMIN                   0x02
216 #define ICH6_REG_VMAJ                   0x03
217 #define ICH6_REG_OUTPAY                 0x04
218 #define ICH6_REG_INPAY                  0x06
219 #define ICH6_REG_GCTL                   0x08
220 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
221 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
222 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
223 #define ICH6_REG_WAKEEN                 0x0c
224 #define ICH6_REG_STATESTS               0x0e
225 #define ICH6_REG_GSTS                   0x10
226 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
227 #define ICH6_REG_INTCTL                 0x20
228 #define ICH6_REG_INTSTS                 0x24
229 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
230 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
231 #define ICH6_REG_SSYNC                  0x38
232 #define ICH6_REG_CORBLBASE              0x40
233 #define ICH6_REG_CORBUBASE              0x44
234 #define ICH6_REG_CORBWP                 0x48
235 #define ICH6_REG_CORBRP                 0x4a
236 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
237 #define ICH6_REG_CORBCTL                0x4c
238 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
239 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
240 #define ICH6_REG_CORBSTS                0x4d
241 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
242 #define ICH6_REG_CORBSIZE               0x4e
243
244 #define ICH6_REG_RIRBLBASE              0x50
245 #define ICH6_REG_RIRBUBASE              0x54
246 #define ICH6_REG_RIRBWP                 0x58
247 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
248 #define ICH6_REG_RINTCNT                0x5a
249 #define ICH6_REG_RIRBCTL                0x5c
250 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
251 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
252 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
253 #define ICH6_REG_RIRBSTS                0x5d
254 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
255 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
256 #define ICH6_REG_RIRBSIZE               0x5e
257
258 #define ICH6_REG_IC                     0x60
259 #define ICH6_REG_IR                     0x64
260 #define ICH6_REG_IRS                    0x68
261 #define   ICH6_IRS_VALID        (1<<1)
262 #define   ICH6_IRS_BUSY         (1<<0)
263
264 #define ICH6_REG_DPLBASE                0x70
265 #define ICH6_REG_DPUBASE                0x74
266 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
267
268 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
269 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
270
271 /* stream register offsets from stream base */
272 #define ICH6_REG_SD_CTL                 0x00
273 #define ICH6_REG_SD_STS                 0x03
274 #define ICH6_REG_SD_LPIB                0x04
275 #define ICH6_REG_SD_CBL                 0x08
276 #define ICH6_REG_SD_LVI                 0x0c
277 #define ICH6_REG_SD_FIFOW               0x0e
278 #define ICH6_REG_SD_FIFOSIZE            0x10
279 #define ICH6_REG_SD_FORMAT              0x12
280 #define ICH6_REG_SD_BDLPL               0x18
281 #define ICH6_REG_SD_BDLPU               0x1c
282
283 /* PCI space */
284 #define ICH6_PCIREG_TCSEL       0x44
285
286 /*
287  * other constants
288  */
289
290 /* max number of SDs */
291 /* ICH, ATI and VIA have 4 playback and 4 capture */
292 #define ICH6_NUM_CAPTURE        4
293 #define ICH6_NUM_PLAYBACK       4
294
295 /* ULI has 6 playback and 5 capture */
296 #define ULI_NUM_CAPTURE         5
297 #define ULI_NUM_PLAYBACK        6
298
299 /* ATI HDMI has 1 playback and 0 capture */
300 #define ATIHDMI_NUM_CAPTURE     0
301 #define ATIHDMI_NUM_PLAYBACK    1
302
303 /* TERA has 4 playback and 3 capture */
304 #define TERA_NUM_CAPTURE        3
305 #define TERA_NUM_PLAYBACK       4
306
307 /* this number is statically defined for simplicity */
308 #define MAX_AZX_DEV             16
309
310 /* max number of fragments - we may use more if allocating more pages for BDL */
311 #define BDL_SIZE                4096
312 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
313 #define AZX_MAX_FRAG            32
314 /* max buffer size - no h/w limit, you can increase as you like */
315 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
316
317 /* RIRB int mask: overrun[2], response[0] */
318 #define RIRB_INT_RESPONSE       0x01
319 #define RIRB_INT_OVERRUN        0x04
320 #define RIRB_INT_MASK           0x05
321
322 /* STATESTS int mask: S3,SD2,SD1,SD0 */
323 #define AZX_MAX_CODECS          8
324 #define AZX_DEFAULT_CODECS      4
325 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
326
327 /* SD_CTL bits */
328 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
329 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
330 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
331 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
332 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
333 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
334 #define SD_CTL_STREAM_TAG_SHIFT 20
335
336 /* SD_CTL and SD_STS */
337 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
338 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
339 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
340 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
341                                  SD_INT_COMPLETE)
342
343 /* SD_STS */
344 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
345
346 /* INTCTL and INTSTS */
347 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
348 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
349 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
350
351 /* below are so far hardcoded - should read registers in future */
352 #define ICH6_MAX_CORB_ENTRIES   256
353 #define ICH6_MAX_RIRB_ENTRIES   256
354
355 /* position fix mode */
356 enum {
357         POS_FIX_AUTO,
358         POS_FIX_LPIB,
359         POS_FIX_POSBUF,
360         POS_FIX_VIACOMBO,
361         POS_FIX_COMBO,
362 };
363
364 /* Defines for ATI HD Audio support in SB450 south bridge */
365 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
366 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
367
368 /* Defines for Nvidia HDA support */
369 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
370 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
371 #define NVIDIA_HDA_ISTRM_COH          0x4d
372 #define NVIDIA_HDA_OSTRM_COH          0x4c
373 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
374
375 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
376 /* Defines for Nvidia Tegra HDA support */
377 #define NVIDIA_TEGRA_HDA_BAR0_OFFSET           0x8000
378
379 #define NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET        0x1004
380 #define NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET       0x1010
381
382 #define NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE       (1 << 0)
383 #define NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE      (1 << 1)
384 #define NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER     (1 << 2)
385 #define NVIDIA_TEGRA_HDA_ENABLE_SERR           (1 << 8)
386 #define NVIDIA_TEGRA_HDA_DISABLE_INTR          (1 << 10)
387 #define NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
388 #define NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM    (1 << 14)
389
390 /* IPFS */
391 #define NVIDIA_TEGRA_HDA_IPFS_CONFIG           0x180
392 #define NVIDIA_TEGRA_HDA_IPFS_EN_FPCI          0x1
393
394 #define NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0        0x80
395 #define NVIDIA_TEGRA_HDA_FPCI_BAR0_START       0x40
396
397 #define NVIDIA_TEGRA_HDA_IPFS_INTR_MASK        0x188
398 #define NVIDIA_TEGRA_HDA_IPFS_EN_INTR          (1 << 16)
399 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
400
401 /* Defines for Intel SCH HDA snoop control */
402 #define INTEL_SCH_HDA_DEVC      0x78
403 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
404
405 /* Define IN stream 0 FIFO size offset in VIA controller */
406 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
407 /* Define VIA HD Audio Device ID*/
408 #define VIA_HDAC_DEVICE_ID              0x3288
409
410 /* HD Audio class code */
411 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
412
413 /*
414  */
415
416 struct azx_dev {
417         struct snd_dma_buffer bdl; /* BDL buffer */
418         u32 *posbuf;            /* position buffer pointer */
419
420         unsigned int bufsize;   /* size of the play buffer in bytes */
421         unsigned int period_bytes; /* size of the period in bytes */
422         unsigned int frags;     /* number for period in the play buffer */
423         unsigned int fifo_size; /* FIFO size */
424         unsigned long start_wallclk;    /* start + minimum wallclk */
425         unsigned long period_wallclk;   /* wallclk for period */
426
427         void __iomem *sd_addr;  /* stream descriptor pointer */
428
429         u32 sd_int_sta_mask;    /* stream int status mask */
430
431         /* pcm support */
432         struct snd_pcm_substream *substream;    /* assigned substream,
433                                                  * set in PCM open
434                                                  */
435         unsigned int format_val;        /* format value to be set in the
436                                          * controller and the codec
437                                          */
438         unsigned char stream_tag;       /* assigned stream */
439         unsigned char index;            /* stream index */
440         int assigned_key;               /* last device# key assigned to */
441
442         unsigned int opened :1;
443         unsigned int running :1;
444         unsigned int irq_pending :1;
445         unsigned int prepared:1;
446         unsigned int locked:1;
447         /*
448          * For VIA:
449          *  A flag to ensure DMA position is 0
450          *  when link position is not greater than FIFO size
451          */
452         unsigned int insufficient :1;
453         unsigned int wc_marked:1;
454         unsigned int no_period_wakeup:1;
455
456         struct timecounter  azx_tc;
457         struct cyclecounter azx_cc;
458
459 #ifdef CONFIG_SND_HDA_DSP_LOADER
460         struct mutex dsp_mutex;
461 #endif
462 };
463
464 /* DSP lock helpers */
465 #ifdef CONFIG_SND_HDA_DSP_LOADER
466 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
467 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
468 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
469 #define dsp_is_locked(dev)      ((dev)->locked)
470 #else
471 #define dsp_lock_init(dev)      do {} while (0)
472 #define dsp_lock(dev)           do {} while (0)
473 #define dsp_unlock(dev)         do {} while (0)
474 #define dsp_is_locked(dev)      0
475 #endif
476
477 /* CORB/RIRB */
478 struct azx_rb {
479         u32 *buf;               /* CORB/RIRB buffer
480                                  * Each CORB entry is 4byte, RIRB is 8byte
481                                  */
482         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
483         /* for RIRB */
484         unsigned short rp, wp;  /* read/write pointers */
485         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
486         u32 res[AZX_MAX_CODECS];        /* last read value */
487 };
488
489 struct azx_pcm {
490         struct azx *chip;
491         struct snd_pcm *pcm;
492         struct hda_codec *codec;
493         struct hda_pcm_stream *hinfo[2];
494         struct list_head list;
495 };
496
497 struct azx {
498         struct snd_card *card;
499         struct pci_dev *pci;
500         struct platform_device *pdev;
501         struct device *dev;
502         int irq_id;
503         int dev_index;
504
505         /* chip type specific */
506         int driver_type;
507         unsigned int driver_caps;
508         int playback_streams;
509         int playback_index_offset;
510         int capture_streams;
511         int capture_index_offset;
512         int num_streams;
513
514         /* pci resources */
515         unsigned long addr;
516         void __iomem *remap_addr;
517 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
518         void __iomem *remap_config_addr;
519 #endif
520         int irq;
521
522 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
523         /* platform driver clocks */
524         struct clk **platform_clks;
525         int platform_clk_count;
526         int platform_clk_enable;
527 #endif
528
529         /* locks */
530         spinlock_t reg_lock;
531         struct mutex open_mutex;
532         struct completion probe_wait;
533
534         /* streams (x num_streams) */
535         struct azx_dev *azx_dev;
536
537         /* PCM */
538         struct list_head pcm_list; /* azx_pcm list */
539
540         /* HD codec */
541         unsigned short codec_mask;
542         int  codec_probe_mask; /* copied from probe_mask option */
543         struct hda_bus *bus;
544         unsigned int beep_mode;
545
546         /* CORB/RIRB */
547         struct azx_rb corb;
548         struct azx_rb rirb;
549
550         /* CORB/RIRB and position buffers */
551         struct snd_dma_buffer rb;
552         struct snd_dma_buffer posbuf;
553
554 #ifdef CONFIG_SND_HDA_PATCH_LOADER
555         const struct firmware *fw;
556 #endif
557
558         /* flags */
559         int position_fix[2]; /* for both playback/capture streams */
560         int poll_count;
561         unsigned int running :1;
562         unsigned int initialized :1;
563         unsigned int single_cmd :1;
564         unsigned int polling_mode :1;
565         unsigned int msi :1;
566         unsigned int irq_pending_warned :1;
567         unsigned int probing :1; /* codec probing phase */
568         unsigned int snoop:1;
569         unsigned int align_buffer_size:1;
570         unsigned int region_requested:1;
571
572         /* VGA-switcheroo setup */
573         unsigned int use_vga_switcheroo:1;
574         unsigned int vga_switcheroo_registered:1;
575         unsigned int init_failed:1; /* delayed init failed */
576         unsigned int disabled:1; /* disabled by VGA-switcher */
577
578         /* for debugging */
579         unsigned int last_cmd[AZX_MAX_CODECS];
580
581         /* for pending irqs */
582         struct work_struct irq_pending_work;
583
584         /* reboot notifier (for mysterious hangup problem at power-down) */
585         struct notifier_block reboot_notifier;
586
587         /* card list (for power_save trigger) */
588         struct list_head list;
589
590 #ifdef CONFIG_SND_HDA_DSP_LOADER
591         struct azx_dev saved_azx_dev;
592 #endif
593 };
594
595 #define CREATE_TRACE_POINTS
596 #include "hda_intel_trace.h"
597
598 /* driver types */
599 enum {
600         AZX_DRIVER_ICH,
601         AZX_DRIVER_PCH,
602         AZX_DRIVER_SCH,
603         AZX_DRIVER_ATI,
604         AZX_DRIVER_ATIHDMI,
605         AZX_DRIVER_ATIHDMI_NS,
606         AZX_DRIVER_VIA,
607         AZX_DRIVER_SIS,
608         AZX_DRIVER_ULI,
609         AZX_DRIVER_NVIDIA,
610         AZX_DRIVER_NVIDIA_TEGRA,
611         AZX_DRIVER_TERA,
612         AZX_DRIVER_CTX,
613         AZX_DRIVER_CTHDA,
614         AZX_DRIVER_GENERIC,
615         AZX_NUM_DRIVERS, /* keep this as last entry */
616 };
617
618 /* driver quirks (capabilities) */
619 /* bits 0-7 are used for indicating driver type */
620 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
621 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
622 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
623 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
624 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
625 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
626 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
627 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
628 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
629 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
630 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
631 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
632 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
633 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
634 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
635 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
636 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
637 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
638
639 /* quirks for Intel PCH */
640 #define AZX_DCAPS_INTEL_PCH_NOPM \
641         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
642          AZX_DCAPS_COUNT_LPIB_DELAY)
643
644 #define AZX_DCAPS_INTEL_PCH \
645         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
646
647 /* quirks for ATI SB / AMD Hudson */
648 #define AZX_DCAPS_PRESET_ATI_SB \
649         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
650          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
651
652 /* quirks for ATI/AMD HDMI */
653 #define AZX_DCAPS_PRESET_ATI_HDMI \
654         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
655
656 /* quirks for Nvidia */
657 #define AZX_DCAPS_PRESET_NVIDIA \
658         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
659          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
660
661 #define AZX_DCAPS_PRESET_CTHDA \
662         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
663
664 /*
665  * VGA-switcher support
666  */
667 #ifdef SUPPORT_VGA_SWITCHEROO
668 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
669 #else
670 #define use_vga_switcheroo(chip)        0
671 #endif
672
673 static char *driver_short_names[] = {
674         [AZX_DRIVER_ICH] = "HDA Intel",
675         [AZX_DRIVER_PCH] = "HDA Intel PCH",
676         [AZX_DRIVER_SCH] = "HDA Intel MID",
677         [AZX_DRIVER_ATI] = "HDA ATI SB",
678         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
679         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
680         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
681         [AZX_DRIVER_SIS] = "HDA SIS966",
682         [AZX_DRIVER_ULI] = "HDA ULI M5461",
683         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
684         [AZX_DRIVER_NVIDIA_TEGRA] = "HDA NVIDIA Tegra",
685         [AZX_DRIVER_TERA] = "HDA Teradici", 
686         [AZX_DRIVER_CTX] = "HDA Creative", 
687         [AZX_DRIVER_CTHDA] = "HDA Creative",
688         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
689 };
690
691 /*
692  * macros for easy use
693  */
694 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
695 #define MASK_LONG_ALIGN         0x3UL
696 #define SHIFT_BYTE              3
697 #define SHIFT_BITS(reg)         ((reg & MASK_LONG_ALIGN) << SHIFT_BYTE)
698 #define ADDR_ALIGN_L(base, reg) (base + (reg & ~MASK_LONG_ALIGN))
699 #define MASK(bits)              (BIT(bits) - 1)
700 #define MASK_REG(reg, bits)     (MASK(bits) << SHIFT_BITS(reg))
701
702 #define tegra_write(base, reg, val, bits) \
703         writel((readl(ADDR_ALIGN_L(base, reg)) & ~MASK_REG(reg, bits)) | \
704                ((val) << SHIFT_BITS(reg)), ADDR_ALIGN_L(base, reg))
705
706 #define tegra_read(base, reg, bits) \
707         ((readl(ADDR_ALIGN_L(base, reg)) >> SHIFT_BITS(reg)) & MASK(bits))
708
709 #define azx_writel(chip, reg, value) \
710         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
711 #define azx_readl(chip, reg) \
712         readl((chip)->remap_addr + ICH6_REG_##reg)
713 #define azx_writew(chip, reg, value) \
714         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 16)
715 #define azx_readw(chip, reg) \
716         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 16)
717 #define azx_writeb(chip, reg, value) \
718         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 8)
719 #define azx_readb(chip, reg) \
720         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 8)
721
722 #define azx_sd_writel(dev, reg, value) \
723         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
724 #define azx_sd_readl(dev, reg) \
725         readl((dev)->sd_addr + ICH6_REG_##reg)
726 #define azx_sd_writew(dev, reg, value) \
727         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 16)
728 #define azx_sd_readw(dev, reg) \
729         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 16)
730 #define azx_sd_writeb(dev, reg, value) \
731         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 8)
732 #define azx_sd_readb(dev, reg) \
733         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 8)
734
735 #else /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
736 #define azx_writel(chip,reg,value) \
737         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
738 #define azx_readl(chip,reg) \
739         readl((chip)->remap_addr + ICH6_REG_##reg)
740 #define azx_writew(chip,reg,value) \
741         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
742 #define azx_readw(chip,reg) \
743         readw((chip)->remap_addr + ICH6_REG_##reg)
744 #define azx_writeb(chip,reg,value) \
745         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
746 #define azx_readb(chip,reg) \
747         readb((chip)->remap_addr + ICH6_REG_##reg)
748
749 #define azx_sd_writel(dev,reg,value) \
750         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
751 #define azx_sd_readl(dev,reg) \
752         readl((dev)->sd_addr + ICH6_REG_##reg)
753 #define azx_sd_writew(dev,reg,value) \
754         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
755 #define azx_sd_readw(dev,reg) \
756         readw((dev)->sd_addr + ICH6_REG_##reg)
757 #define azx_sd_writeb(dev,reg,value) \
758         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
759 #define azx_sd_readb(dev,reg) \
760         readb((dev)->sd_addr + ICH6_REG_##reg)
761
762 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
763
764 /* for pcm support */
765 #define get_azx_dev(substream) (substream->runtime->private_data)
766
767 #ifdef CONFIG_X86
768 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
769 {
770         int pages;
771
772         if (azx_snoop(chip))
773                 return;
774         if (!dmab || !dmab->area || !dmab->bytes)
775                 return;
776
777 #ifdef CONFIG_SND_DMA_SGBUF
778         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
779                 struct snd_sg_buf *sgbuf = dmab->private_data;
780                 if (on)
781                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
782                 else
783                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
784                 return;
785         }
786 #endif
787
788         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
789         if (on)
790                 set_memory_wc((unsigned long)dmab->area, pages);
791         else
792                 set_memory_wb((unsigned long)dmab->area, pages);
793 }
794
795 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
796                                  bool on)
797 {
798         __mark_pages_wc(chip, buf, on);
799 }
800 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
801                                    struct snd_pcm_substream *substream, bool on)
802 {
803         if (azx_dev->wc_marked != on) {
804                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
805                 azx_dev->wc_marked = on;
806         }
807 }
808 #else
809 /* NOP for other archs */
810 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
811                                  bool on)
812 {
813 }
814 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
815                                    struct snd_pcm_substream *substream, bool on)
816 {
817 }
818 #endif
819
820 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
821 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
822 /*
823  * Interface for HD codec
824  */
825
826 /*
827  * CORB / RIRB interface
828  */
829 static int azx_alloc_cmd_io(struct azx *chip)
830 {
831         int err;
832
833         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
834         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
835                                   chip->dev,
836                                   PAGE_SIZE, &chip->rb);
837         if (err < 0) {
838                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", pci_name(chip->pci));
839                 return err;
840         }
841         mark_pages_wc(chip, &chip->rb, true);
842         return 0;
843 }
844
845 static void azx_init_cmd_io(struct azx *chip)
846 {
847         spin_lock_irq(&chip->reg_lock);
848         /* CORB set up */
849         chip->corb.addr = chip->rb.addr;
850         chip->corb.buf = (u32 *)chip->rb.area;
851         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
852         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
853
854         /* set the corb size to 256 entries (ULI requires explicitly) */
855         azx_writeb(chip, CORBSIZE, 0x02);
856         /* set the corb write pointer to 0 */
857         azx_writew(chip, CORBWP, 0);
858         /* reset the corb hw read pointer */
859         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
860         /* enable corb dma */
861         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
862
863         /* RIRB set up */
864         chip->rirb.addr = chip->rb.addr + 2048;
865         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
866         chip->rirb.wp = chip->rirb.rp = 0;
867         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
868         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
869         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
870
871         /* set the rirb size to 256 entries (ULI requires explicitly) */
872         azx_writeb(chip, RIRBSIZE, 0x02);
873         /* reset the rirb hw write pointer */
874         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
875         /* set N=1, get RIRB response interrupt for new entry */
876         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
877                 azx_writew(chip, RINTCNT, 0xc0);
878         else
879                 azx_writew(chip, RINTCNT, 1);
880         /* enable rirb dma and response irq */
881         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
882         spin_unlock_irq(&chip->reg_lock);
883 }
884
885 static void azx_free_cmd_io(struct azx *chip)
886 {
887         spin_lock_irq(&chip->reg_lock);
888         /* disable ringbuffer DMAs */
889         azx_writeb(chip, RIRBCTL, 0);
890         azx_writeb(chip, CORBCTL, 0);
891         spin_unlock_irq(&chip->reg_lock);
892 }
893
894 static unsigned int azx_command_addr(u32 cmd)
895 {
896         unsigned int addr = cmd >> 28;
897
898         if (addr >= AZX_MAX_CODECS) {
899                 snd_BUG();
900                 addr = 0;
901         }
902
903         return addr;
904 }
905
906 static unsigned int azx_response_addr(u32 res)
907 {
908         unsigned int addr = res & 0xf;
909
910         if (addr >= AZX_MAX_CODECS) {
911                 snd_BUG();
912                 addr = 0;
913         }
914
915         return addr;
916 }
917
918 /* send a command */
919 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
920 {
921         struct azx *chip = bus->private_data;
922         unsigned int addr = azx_command_addr(val);
923         unsigned int wp, rp;
924
925         spin_lock_irq(&chip->reg_lock);
926
927         /* add command to corb */
928         wp = azx_readw(chip, CORBWP);
929         if (wp == 0xffff) {
930                 /* something wrong, controller likely turned to D3 */
931                 spin_unlock_irq(&chip->reg_lock);
932                 return -EIO;
933         }
934         wp++;
935         wp %= ICH6_MAX_CORB_ENTRIES;
936
937         rp = azx_readw(chip, CORBRP);
938         if (wp == rp) {
939                 /* oops, it's full */
940                 spin_unlock_irq(&chip->reg_lock);
941                 return -EAGAIN;
942         }
943
944         chip->rirb.cmds[addr]++;
945         chip->corb.buf[wp] = cpu_to_le32(val);
946         azx_writel(chip, CORBWP, wp);
947
948         spin_unlock_irq(&chip->reg_lock);
949
950         return 0;
951 }
952
953 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
954
955 /* retrieve RIRB entry - called from interrupt handler */
956 static void azx_update_rirb(struct azx *chip)
957 {
958         unsigned int rp, wp;
959         unsigned int addr;
960         u32 res, res_ex;
961
962         wp = azx_readw(chip, RIRBWP);
963         if (wp == 0xffff) {
964                 /* something wrong, controller likely turned to D3 */
965                 return;
966         }
967
968         if (wp == chip->rirb.wp)
969                 return;
970         chip->rirb.wp = wp;
971
972         while (chip->rirb.rp != wp) {
973                 chip->rirb.rp++;
974                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
975
976                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
977                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
978                 res = le32_to_cpu(chip->rirb.buf[rp]);
979                 addr = azx_response_addr(res_ex);
980                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
981                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
982                 else if (chip->rirb.cmds[addr]) {
983                         chip->rirb.res[addr] = res;
984                         smp_wmb();
985                         chip->rirb.cmds[addr]--;
986                 } else
987                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
988                                    "last cmd=%#08x\n",
989                                    pci_name(chip->pci),
990                                    res, res_ex,
991                                    chip->last_cmd[addr]);
992         }
993 }
994
995 /* receive a response */
996 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
997                                           unsigned int addr)
998 {
999         struct azx *chip = bus->private_data;
1000         unsigned long timeout;
1001         unsigned long loopcounter;
1002         int do_poll = 0;
1003
1004  again:
1005         timeout = jiffies + msecs_to_jiffies(1000);
1006
1007         for (loopcounter = 0;; loopcounter++) {
1008                 if (chip->polling_mode || do_poll) {
1009                         spin_lock_irq(&chip->reg_lock);
1010                         azx_update_rirb(chip);
1011                         spin_unlock_irq(&chip->reg_lock);
1012                 }
1013                 if (!chip->rirb.cmds[addr]) {
1014                         smp_rmb();
1015                         bus->rirb_error = 0;
1016
1017                         if (!do_poll)
1018                                 chip->poll_count = 0;
1019                         return chip->rirb.res[addr]; /* the last value */
1020                 }
1021                 if (time_after(jiffies, timeout))
1022                         break;
1023                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1024                         msleep(2); /* temporary workaround */
1025                 else {
1026                         udelay(10);
1027                         cond_resched();
1028                 }
1029         }
1030
1031         if (!chip->polling_mode && chip->poll_count < 2) {
1032                 snd_printdd(SFX "%s: azx_get_response timeout, "
1033                            "polling the codec once: last cmd=0x%08x\n",
1034                            pci_name(chip->pci), chip->last_cmd[addr]);
1035                 do_poll = 1;
1036                 chip->poll_count++;
1037                 goto again;
1038         }
1039
1040
1041         if (!chip->polling_mode) {
1042                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
1043                            "switching to polling mode: last cmd=0x%08x\n",
1044                            pci_name(chip->pci), chip->last_cmd[addr]);
1045                 chip->polling_mode = 1;
1046                 goto again;
1047         }
1048
1049         if (chip->msi) {
1050                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
1051                            "disabling MSI: last cmd=0x%08x\n",
1052                            pci_name(chip->pci), chip->last_cmd[addr]);
1053                 free_irq(chip->irq, chip);
1054                 chip->irq = -1;
1055                 pci_disable_msi(chip->pci);
1056                 chip->msi = 0;
1057                 if (azx_acquire_irq(chip, 1) < 0) {
1058                         bus->rirb_error = 1;
1059                         return -1;
1060                 }
1061                 goto again;
1062         }
1063
1064         if (chip->probing) {
1065                 /* If this critical timeout happens during the codec probing
1066                  * phase, this is likely an access to a non-existing codec
1067                  * slot.  Better to return an error and reset the system.
1068                  */
1069                 return -1;
1070         }
1071
1072         /* a fatal communication error; need either to reset or to fallback
1073          * to the single_cmd mode
1074          */
1075         bus->rirb_error = 1;
1076         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1077                 bus->response_reset = 1;
1078                 return -1; /* give a chance to retry */
1079         }
1080
1081         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1082                    "switching to single_cmd mode: last cmd=0x%08x\n",
1083                    chip->last_cmd[addr]);
1084         chip->single_cmd = 1;
1085         bus->response_reset = 0;
1086         /* release CORB/RIRB */
1087         azx_free_cmd_io(chip);
1088         /* disable unsolicited responses */
1089         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1090         return -1;
1091 }
1092
1093 /*
1094  * Use the single immediate command instead of CORB/RIRB for simplicity
1095  *
1096  * Note: according to Intel, this is not preferred use.  The command was
1097  *       intended for the BIOS only, and may get confused with unsolicited
1098  *       responses.  So, we shouldn't use it for normal operation from the
1099  *       driver.
1100  *       I left the codes, however, for debugging/testing purposes.
1101  */
1102
1103 /* receive a response */
1104 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1105 {
1106         int timeout = 50;
1107
1108         while (timeout--) {
1109                 /* check IRV busy bit */
1110                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1111                         /* reuse rirb.res as the response return value */
1112                         chip->rirb.res[addr] = azx_readl(chip, IR);
1113                         return 0;
1114                 }
1115                 udelay(1);
1116         }
1117         if (printk_ratelimit())
1118                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1119                            pci_name(chip->pci), azx_readw(chip, IRS));
1120         chip->rirb.res[addr] = -1;
1121         return -EIO;
1122 }
1123
1124 /* send a command */
1125 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1126 {
1127         struct azx *chip = bus->private_data;
1128         unsigned int addr = azx_command_addr(val);
1129         int timeout = 50;
1130
1131         bus->rirb_error = 0;
1132         while (timeout--) {
1133                 /* check ICB busy bit */
1134                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1135                         /* Clear IRV valid bit */
1136                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1137                                    ICH6_IRS_VALID);
1138                         azx_writel(chip, IC, val);
1139                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1140                                    ICH6_IRS_BUSY);
1141                         return azx_single_wait_for_response(chip, addr);
1142                 }
1143                 udelay(1);
1144         }
1145         if (printk_ratelimit())
1146                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1147                            pci_name(chip->pci), azx_readw(chip, IRS), val);
1148         return -EIO;
1149 }
1150
1151 /* receive a response */
1152 static unsigned int azx_single_get_response(struct hda_bus *bus,
1153                                             unsigned int addr)
1154 {
1155         struct azx *chip = bus->private_data;
1156         return chip->rirb.res[addr];
1157 }
1158
1159 /*
1160  * The below are the main callbacks from hda_codec.
1161  *
1162  * They are just the skeleton to call sub-callbacks according to the
1163  * current setting of chip->single_cmd.
1164  */
1165
1166 /* send a command */
1167 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1168 {
1169         struct azx *chip = bus->private_data;
1170
1171         if (chip->disabled)
1172                 return 0;
1173         chip->last_cmd[azx_command_addr(val)] = val;
1174         if (chip->single_cmd)
1175                 return azx_single_send_cmd(bus, val);
1176         else
1177                 return azx_corb_send_cmd(bus, val);
1178 }
1179
1180 /* get a response */
1181 static unsigned int azx_get_response(struct hda_bus *bus,
1182                                      unsigned int addr)
1183 {
1184         struct azx *chip = bus->private_data;
1185         if (chip->disabled)
1186                 return 0;
1187         if (chip->single_cmd)
1188                 return azx_single_get_response(bus, addr);
1189         else
1190                 return azx_rirb_get_response(bus, addr);
1191 }
1192
1193 #ifdef CONFIG_PM
1194 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1195 #endif
1196
1197 #ifdef CONFIG_SND_HDA_DSP_LOADER
1198 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1199                                 unsigned int byte_size,
1200                                 struct snd_dma_buffer *bufp);
1201 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1202 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1203                                  struct snd_dma_buffer *dmab);
1204 #endif
1205
1206 /* reset codec link */
1207 static int azx_reset(struct azx *chip, int full_reset)
1208 {
1209         unsigned long timeout;
1210
1211         if (!full_reset)
1212                 goto __skip;
1213
1214         /* clear STATESTS */
1215         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1216
1217         /* reset controller */
1218         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1219
1220         timeout = jiffies + msecs_to_jiffies(100);
1221         while (azx_readb(chip, GCTL) &&
1222                         time_before(jiffies, timeout))
1223                 usleep_range(500, 1000);
1224
1225         /* delay for >= 100us for codec PLL to settle per spec
1226          * Rev 0.9 section 5.5.1
1227          */
1228         usleep_range(500, 1000);
1229
1230         /* Bring controller out of reset */
1231         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1232
1233         timeout = jiffies + msecs_to_jiffies(100);
1234         while (!azx_readb(chip, GCTL) &&
1235                         time_before(jiffies, timeout))
1236                 usleep_range(500, 1000);
1237
1238         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1239         usleep_range(1000, 1200);
1240
1241       __skip:
1242         /* check to see if controller is ready */
1243         if (!azx_readb(chip, GCTL)) {
1244                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", pci_name(chip->pci));
1245                 return -EBUSY;
1246         }
1247
1248         /* Accept unsolicited responses */
1249         if (!chip->single_cmd)
1250                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1251                            ICH6_GCTL_UNSOL);
1252
1253         /* detect codecs */
1254         if (!chip->codec_mask) {
1255                 chip->codec_mask = azx_readw(chip, STATESTS);
1256                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", pci_name(chip->pci), chip->codec_mask);
1257         }
1258
1259         return 0;
1260 }
1261
1262
1263 /*
1264  * Lowlevel interface
1265  */
1266
1267 /* enable interrupts */
1268 static void azx_int_enable(struct azx *chip)
1269 {
1270         /* enable controller CIE and GIE */
1271         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1272                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1273 }
1274
1275 /* disable interrupts */
1276 static void azx_int_disable(struct azx *chip)
1277 {
1278         int i;
1279
1280         /* disable interrupts in stream descriptor */
1281         for (i = 0; i < chip->num_streams; i++) {
1282                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1283                 azx_sd_writeb(azx_dev, SD_CTL,
1284                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1285         }
1286
1287         /* disable SIE for all streams */
1288         azx_writeb(chip, INTCTL, 0);
1289
1290         /* disable controller CIE and GIE */
1291         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1292                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1293 }
1294
1295 /* clear interrupts */
1296 static void azx_int_clear(struct azx *chip)
1297 {
1298         int i;
1299
1300         /* clear stream status */
1301         for (i = 0; i < chip->num_streams; i++) {
1302                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1303                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1304         }
1305
1306         /* clear STATESTS */
1307         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1308
1309         /* clear rirb status */
1310         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1311
1312         /* clear int status */
1313         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1314 }
1315
1316 /* start a stream */
1317 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1318 {
1319         /*
1320          * Before stream start, initialize parameter
1321          */
1322         azx_dev->insufficient = 1;
1323
1324         /* enable SIE */
1325         azx_writel(chip, INTCTL,
1326                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1327         /* set DMA start and interrupt mask */
1328         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1329                       SD_CTL_DMA_START | SD_INT_MASK);
1330 }
1331
1332 /* stop DMA */
1333 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1334 {
1335         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1336                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1337         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1338 }
1339
1340 /* stop a stream */
1341 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1342 {
1343         azx_stream_clear(chip, azx_dev);
1344         /* disable SIE */
1345         azx_writel(chip, INTCTL,
1346                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1347 }
1348
1349
1350 /*
1351  * reset and start the controller registers
1352  */
1353 static void azx_init_chip(struct azx *chip, int full_reset)
1354 {
1355         if (chip->initialized)
1356                 return;
1357
1358         /* reset controller */
1359         azx_reset(chip, full_reset);
1360
1361         /* initialize interrupts */
1362         azx_int_clear(chip);
1363         azx_int_enable(chip);
1364
1365         /* initialize the codec command I/O */
1366         if (!chip->single_cmd)
1367                 azx_init_cmd_io(chip);
1368
1369         /* program the position buffer */
1370         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1371         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1372
1373         chip->initialized = 1;
1374 }
1375
1376 /*
1377  * initialize the PCI registers
1378  */
1379 /* update bits in a PCI register byte */
1380 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1381                             unsigned char mask, unsigned char val)
1382 {
1383         unsigned char data;
1384
1385         pci_read_config_byte(pci, reg, &data);
1386         data &= ~mask;
1387         data |= (val & mask);
1388         pci_write_config_byte(pci, reg, data);
1389 }
1390
1391 static void azx_init_pci(struct azx *chip)
1392 {
1393         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1394          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1395          * Ensuring these bits are 0 clears playback static on some HD Audio
1396          * codecs.
1397          * The PCI register TCSEL is defined in the Intel manuals.
1398          */
1399         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1400                 snd_printdd(SFX "%s: Clearing TCSEL\n", pci_name(chip->pci));
1401                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1402         }
1403
1404         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1405          * we need to enable snoop.
1406          */
1407         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1408                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1409                 update_pci_byte(chip->pci,
1410                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1411                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1412         }
1413
1414         /* For NVIDIA HDA, enable snoop */
1415         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1416                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", pci_name(chip->pci), azx_snoop(chip));
1417                 update_pci_byte(chip->pci,
1418                                 NVIDIA_HDA_TRANSREG_ADDR,
1419                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1420                 update_pci_byte(chip->pci,
1421                                 NVIDIA_HDA_ISTRM_COH,
1422                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1423                 update_pci_byte(chip->pci,
1424                                 NVIDIA_HDA_OSTRM_COH,
1425                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1426         }
1427
1428         /* Enable SCH/PCH snoop if needed */
1429         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1430                 unsigned short snoop;
1431                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1432                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1433                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1434                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1435                         if (!azx_snoop(chip))
1436                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1437                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1438                         pci_read_config_word(chip->pci,
1439                                 INTEL_SCH_HDA_DEVC, &snoop);
1440                 }
1441                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1442                                 pci_name(chip->pci), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1443                                 ? "Disabled" : "Enabled");
1444         }
1445 }
1446
1447 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
1448 /*
1449  * initialize the platform specific registers
1450  */
1451 static void reg_update_bits(void __iomem *base, unsigned int reg,
1452                             unsigned int mask, unsigned int val)
1453 {
1454         unsigned int data;
1455
1456         data = readl(base + reg);
1457         data &= ~mask;
1458         data |= (val & mask);
1459         writel(data, base + reg);
1460 }
1461
1462 static void azx_init_platform(struct azx *chip)
1463 {
1464         switch (chip->driver_type) {
1465 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1466         case AZX_DRIVER_NVIDIA_TEGRA:
1467                 /*Enable the PCI access */
1468                 reg_update_bits(chip->remap_config_addr,
1469                                 NVIDIA_TEGRA_HDA_IPFS_CONFIG,
1470                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI,
1471                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI);
1472                 /* Enable MEM/IO space and bus master */
1473                 reg_update_bits(chip->remap_config_addr,
1474                                 NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET, 0x507,
1475                                 NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE |
1476                                 NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE |
1477                                 NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER |
1478                                 NVIDIA_TEGRA_HDA_ENABLE_SERR);
1479                 reg_update_bits(chip->remap_config_addr,
1480                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1481                                 NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM);
1482                 reg_update_bits(chip->remap_config_addr,
1483                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1484                                 NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM);
1485                 reg_update_bits(chip->remap_config_addr,
1486                                 NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0, 0xFFFFFFFF,
1487                                 NVIDIA_TEGRA_HDA_FPCI_BAR0_START);
1488                 reg_update_bits(chip->remap_config_addr,
1489                                 NVIDIA_TEGRA_HDA_IPFS_INTR_MASK,
1490                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR,
1491                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR);
1492                 break;
1493 #endif
1494         default:
1495                 break;
1496         }
1497
1498         return;
1499 }
1500
1501 static void azx_platform_enable_clocks(struct azx *chip)
1502 {
1503         int i;
1504
1505         for (i = 0; i < chip->platform_clk_count; i++)
1506                 clk_enable(chip->platform_clks[i]);
1507
1508         chip->platform_clk_enable++;
1509 }
1510
1511 static void azx_platform_disable_clocks(struct azx *chip)
1512 {
1513         int i;
1514
1515         if (!chip->platform_clk_enable)
1516                 return;
1517
1518         for (i = 0; i < chip->platform_clk_count; i++)
1519                 clk_disable(chip->platform_clks[i]);
1520
1521         chip->platform_clk_enable--;
1522 }
1523 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
1524
1525 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1526
1527 /*
1528  * interrupt handler
1529  */
1530 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1531 {
1532         struct azx *chip = dev_id;
1533         struct azx_dev *azx_dev;
1534         u32 status;
1535         u8 sd_status;
1536         int i, ok;
1537
1538 #ifdef CONFIG_PM_RUNTIME
1539         if (chip->pci->dev.power.runtime_status != RPM_ACTIVE)
1540                 return IRQ_NONE;
1541 #endif
1542
1543         spin_lock(&chip->reg_lock);
1544
1545         if (chip->disabled) {
1546                 spin_unlock(&chip->reg_lock);
1547                 return IRQ_NONE;
1548         }
1549
1550         status = azx_readl(chip, INTSTS);
1551         if (status == 0) {
1552                 spin_unlock(&chip->reg_lock);
1553                 return IRQ_NONE;
1554         }
1555
1556         for (i = 0; i < chip->num_streams; i++) {
1557                 azx_dev = &chip->azx_dev[i];
1558                 if (status & azx_dev->sd_int_sta_mask) {
1559                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1560                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1561                         if (!azx_dev->substream || !azx_dev->running ||
1562                             !(sd_status & SD_INT_COMPLETE))
1563                                 continue;
1564                         /* check whether this IRQ is really acceptable */
1565                         ok = azx_position_ok(chip, azx_dev);
1566                         if (ok == 1) {
1567                                 azx_dev->irq_pending = 0;
1568                                 spin_unlock(&chip->reg_lock);
1569                                 snd_pcm_period_elapsed(azx_dev->substream);
1570                                 spin_lock(&chip->reg_lock);
1571                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1572                                 /* bogus IRQ, process it later */
1573                                 azx_dev->irq_pending = 1;
1574                                 queue_work(chip->bus->workq,
1575                                            &chip->irq_pending_work);
1576                         }
1577                 }
1578         }
1579
1580         /* clear rirb int */
1581         status = azx_readb(chip, RIRBSTS);
1582         if (status & RIRB_INT_MASK) {
1583                 if (status & RIRB_INT_RESPONSE) {
1584                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1585                                 udelay(80);
1586                         azx_update_rirb(chip);
1587                 }
1588                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1589         }
1590
1591 #if 0
1592         /* clear state status int */
1593         if (azx_readb(chip, STATESTS) & 0x04)
1594                 azx_writeb(chip, STATESTS, 0x04);
1595 #endif
1596         spin_unlock(&chip->reg_lock);
1597
1598         return IRQ_HANDLED;
1599 }
1600
1601
1602 /*
1603  * set up a BDL entry
1604  */
1605 static int setup_bdle(struct azx *chip,
1606                       struct snd_dma_buffer *dmab,
1607                       struct azx_dev *azx_dev, u32 **bdlp,
1608                       int ofs, int size, int with_ioc)
1609 {
1610         u32 *bdl = *bdlp;
1611
1612         while (size > 0) {
1613                 dma_addr_t addr;
1614                 int chunk;
1615
1616                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1617                         return -EINVAL;
1618
1619                 addr = snd_sgbuf_get_addr(dmab, ofs);
1620                 /* program the address field of the BDL entry */
1621                 bdl[0] = cpu_to_le32((u32)addr);
1622                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1623                 /* program the size field of the BDL entry */
1624                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1625                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1626                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1627                         u32 remain = 0x1000 - (ofs & 0xfff);
1628                         if (chunk > remain)
1629                                 chunk = remain;
1630                 }
1631                 bdl[2] = cpu_to_le32(chunk);
1632                 /* program the IOC to enable interrupt
1633                  * only when the whole fragment is processed
1634                  */
1635                 size -= chunk;
1636                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1637                 bdl += 4;
1638                 azx_dev->frags++;
1639                 ofs += chunk;
1640         }
1641         *bdlp = bdl;
1642         return ofs;
1643 }
1644
1645 /*
1646  * set up BDL entries
1647  */
1648 static int azx_setup_periods(struct azx *chip,
1649                              struct snd_pcm_substream *substream,
1650                              struct azx_dev *azx_dev)
1651 {
1652         u32 *bdl;
1653         int i, ofs, periods, period_bytes;
1654         int pos_adj;
1655
1656         /* reset BDL address */
1657         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1658         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1659
1660         period_bytes = azx_dev->period_bytes;
1661         periods = azx_dev->bufsize / period_bytes;
1662
1663         /* program the initial BDL entries */
1664         bdl = (u32 *)azx_dev->bdl.area;
1665         ofs = 0;
1666         azx_dev->frags = 0;
1667         pos_adj = bdl_pos_adj[chip->dev_index];
1668         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1669                 struct snd_pcm_runtime *runtime = substream->runtime;
1670                 int pos_align = pos_adj;
1671                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1672                 if (!pos_adj)
1673                         pos_adj = pos_align;
1674                 else
1675                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1676                                 pos_align;
1677                 pos_adj = frames_to_bytes(runtime, pos_adj);
1678                 if (pos_adj >= period_bytes) {
1679                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1680                                    pci_name(chip->pci), bdl_pos_adj[chip->dev_index]);
1681                         pos_adj = 0;
1682                 } else {
1683                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1684                                          azx_dev,
1685                                          &bdl, ofs, pos_adj, true);
1686                         if (ofs < 0)
1687                                 goto error;
1688                 }
1689         } else
1690                 pos_adj = 0;
1691         for (i = 0; i < periods; i++) {
1692                 if (i == periods - 1 && pos_adj)
1693                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1694                                          azx_dev, &bdl, ofs,
1695                                          period_bytes - pos_adj, 0);
1696                 else
1697                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1698                                          azx_dev, &bdl, ofs,
1699                                          period_bytes,
1700                                          !azx_dev->no_period_wakeup);
1701                 if (ofs < 0)
1702                         goto error;
1703         }
1704         return 0;
1705
1706  error:
1707         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1708                    pci_name(chip->pci), azx_dev->bufsize, period_bytes);
1709         return -EINVAL;
1710 }
1711
1712 /* reset stream */
1713 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1714 {
1715         unsigned char val;
1716         int timeout;
1717
1718         azx_stream_clear(chip, azx_dev);
1719
1720         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1721                       SD_CTL_STREAM_RESET);
1722         udelay(3);
1723         timeout = 300;
1724         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1725                --timeout)
1726                 ;
1727         val &= ~SD_CTL_STREAM_RESET;
1728         azx_sd_writeb(azx_dev, SD_CTL, val);
1729         udelay(3);
1730
1731         timeout = 300;
1732         /* waiting for hardware to report that the stream is out of reset */
1733         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1734                --timeout)
1735                 ;
1736
1737         /* reset first position - may not be synced with hw at this time */
1738         *azx_dev->posbuf = 0;
1739 }
1740
1741 /*
1742  * set up the SD for streaming
1743  */
1744 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1745 {
1746         unsigned int val;
1747         /* make sure the run bit is zero for SD */
1748         azx_stream_clear(chip, azx_dev);
1749         /* program the stream_tag */
1750         val = azx_sd_readl(azx_dev, SD_CTL);
1751         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1752                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1753         if (!azx_snoop(chip))
1754                 val |= SD_CTL_TRAFFIC_PRIO;
1755         azx_sd_writel(azx_dev, SD_CTL, val);
1756
1757         /* program the length of samples in cyclic buffer */
1758         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1759
1760         /* program the stream format */
1761         /* this value needs to be the same as the one programmed */
1762         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1763
1764         /* program the stream LVI (last valid index) of the BDL */
1765         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1766
1767         /* program the BDL address */
1768         /* lower BDL address */
1769         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1770         /* upper BDL address */
1771         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1772
1773         /* enable the position buffer */
1774         if (chip->position_fix[0] != POS_FIX_LPIB ||
1775             chip->position_fix[1] != POS_FIX_LPIB) {
1776                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1777                         azx_writel(chip, DPLBASE,
1778                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1779         }
1780
1781         /* set the interrupt enable bits in the descriptor control register */
1782         azx_sd_writel(azx_dev, SD_CTL,
1783                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1784
1785         return 0;
1786 }
1787
1788 /*
1789  * Probe the given codec address
1790  */
1791 static int probe_codec(struct azx *chip, int addr)
1792 {
1793         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1794                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1795         unsigned int res;
1796
1797         mutex_lock(&chip->bus->cmd_mutex);
1798         chip->probing = 1;
1799         azx_send_cmd(chip->bus, cmd);
1800         res = azx_get_response(chip->bus, addr);
1801         chip->probing = 0;
1802         mutex_unlock(&chip->bus->cmd_mutex);
1803         if (res == -1)
1804                 return -EIO;
1805         snd_printdd(SFX "%s: codec #%d probed OK\n", pci_name(chip->pci), addr);
1806         return 0;
1807 }
1808
1809 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1810                                  struct hda_pcm *cpcm);
1811 static void azx_stop_chip(struct azx *chip);
1812
1813 static void azx_bus_reset(struct hda_bus *bus)
1814 {
1815         struct azx *chip = bus->private_data;
1816
1817         bus->in_reset = 1;
1818         azx_stop_chip(chip);
1819         azx_init_chip(chip, 1);
1820 #ifdef CONFIG_PM
1821         if (chip->initialized) {
1822                 struct azx_pcm *p;
1823                 list_for_each_entry(p, &chip->pcm_list, list)
1824                         snd_pcm_suspend_all(p->pcm);
1825                 snd_hda_suspend(chip->bus);
1826                 snd_hda_resume(chip->bus);
1827         }
1828 #endif
1829         bus->in_reset = 0;
1830 }
1831
1832 static int get_jackpoll_interval(struct azx *chip)
1833 {
1834         int i = jackpoll_ms[chip->dev_index];
1835         unsigned int j;
1836         if (i == 0)
1837                 return 0;
1838         if (i < 50 || i > 60000)
1839                 j = 0;
1840         else
1841                 j = msecs_to_jiffies(i);
1842         if (j == 0)
1843                 snd_printk(KERN_WARNING SFX
1844                            "jackpoll_ms value out of range: %d\n", i);
1845         return j;
1846 }
1847
1848 /*
1849  * Codec initialization
1850  */
1851
1852 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1853 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1854         [AZX_DRIVER_NVIDIA] = 8,
1855         [AZX_DRIVER_TERA] = 1,
1856 };
1857
1858 static int azx_codec_create(struct azx *chip, const char *model)
1859 {
1860         struct hda_bus_template bus_temp;
1861         int c, codecs, err;
1862         int max_slots;
1863
1864         memset(&bus_temp, 0, sizeof(bus_temp));
1865         bus_temp.private_data = chip;
1866         bus_temp.modelname = model;
1867         bus_temp.pci = chip->pci;
1868         bus_temp.pdev = chip->pdev;
1869         bus_temp.ops.command = azx_send_cmd;
1870         bus_temp.ops.get_response = azx_get_response;
1871         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1872         bus_temp.ops.bus_reset = azx_bus_reset;
1873 #ifdef CONFIG_PM
1874         bus_temp.power_save = &power_save;
1875         bus_temp.ops.pm_notify = azx_power_notify;
1876 #endif
1877 #ifdef CONFIG_SND_HDA_DSP_LOADER
1878         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1879         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1880         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1881 #endif
1882
1883         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1884         if (err < 0)
1885                 return err;
1886
1887         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1888                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", pci_name(chip->pci));
1889                 chip->bus->needs_damn_long_delay = 1;
1890         }
1891
1892         codecs = 0;
1893         max_slots = azx_max_codecs[chip->driver_type];
1894         if (!max_slots)
1895                 max_slots = AZX_DEFAULT_CODECS;
1896
1897         /* First try to probe all given codec slots */
1898         for (c = 0; c < max_slots; c++) {
1899                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1900                         if (probe_codec(chip, c) < 0) {
1901                                 /* Some BIOSen give you wrong codec addresses
1902                                  * that don't exist
1903                                  */
1904                                 snd_printk(KERN_WARNING SFX
1905                                            "%s: Codec #%d probe error; "
1906                                            "disabling it...\n", pci_name(chip->pci), c);
1907                                 chip->codec_mask &= ~(1 << c);
1908                                 /* More badly, accessing to a non-existing
1909                                  * codec often screws up the controller chip,
1910                                  * and disturbs the further communications.
1911                                  * Thus if an error occurs during probing,
1912                                  * better to reset the controller chip to
1913                                  * get back to the sanity state.
1914                                  */
1915                                 azx_stop_chip(chip);
1916                                 azx_init_chip(chip, 1);
1917                         }
1918                 }
1919         }
1920
1921         /* AMD chipsets often cause the communication stalls upon certain
1922          * sequence like the pin-detection.  It seems that forcing the synced
1923          * access works around the stall.  Grrr...
1924          */
1925         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1926                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
1927                         pci_name(chip->pci));
1928                 chip->bus->sync_write = 1;
1929                 chip->bus->allow_bus_reset = 1;
1930         }
1931
1932         /* Then create codec instances */
1933         for (c = 0; c < max_slots; c++) {
1934                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1935                         struct hda_codec *codec;
1936                         err = snd_hda_codec_new(chip->bus, c, &codec);
1937                         if (err < 0)
1938                                 continue;
1939                         codec->jackpoll_interval = get_jackpoll_interval(chip);
1940                         codec->beep_mode = chip->beep_mode;
1941                         codecs++;
1942                 }
1943         }
1944         if (!codecs) {
1945                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", pci_name(chip->pci));
1946                 return -ENXIO;
1947         }
1948         return 0;
1949 }
1950
1951 /* configure each codec instance */
1952 static int azx_codec_configure(struct azx *chip)
1953 {
1954         struct hda_codec *codec;
1955         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1956                 snd_hda_codec_configure(codec);
1957         }
1958         return 0;
1959 }
1960
1961
1962 /*
1963  * PCM support
1964  */
1965
1966 /* assign a stream for the PCM */
1967 static inline struct azx_dev *
1968 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1969 {
1970         int dev, i, nums;
1971         struct azx_dev *res = NULL;
1972         /* make a non-zero unique key for the substream */
1973         int key = (substream->pcm->device << 16) | (substream->number << 2) |
1974                 (substream->stream + 1);
1975
1976         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1977                 dev = chip->playback_index_offset;
1978                 nums = chip->playback_streams;
1979         } else {
1980                 dev = chip->capture_index_offset;
1981                 nums = chip->capture_streams;
1982         }
1983         for (i = 0; i < nums; i++, dev++) {
1984                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
1985                 dsp_lock(azx_dev);
1986                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
1987                         res = azx_dev;
1988                         if (res->assigned_key == key) {
1989                                 res->opened = 1;
1990                                 res->assigned_key = key;
1991                                 dsp_unlock(azx_dev);
1992                                 return azx_dev;
1993                         }
1994                 }
1995                 dsp_unlock(azx_dev);
1996         }
1997         if (res) {
1998                 dsp_lock(res);
1999                 res->opened = 1;
2000                 res->assigned_key = key;
2001                 dsp_unlock(res);
2002         }
2003         return res;
2004 }
2005
2006 /* release the assigned stream */
2007 static inline void azx_release_device(struct azx_dev *azx_dev)
2008 {
2009         azx_dev->opened = 0;
2010 }
2011
2012 static cycle_t azx_cc_read(const struct cyclecounter *cc)
2013 {
2014         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
2015         struct snd_pcm_substream *substream = azx_dev->substream;
2016         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2017         struct azx *chip = apcm->chip;
2018
2019         return azx_readl(chip, WALLCLK);
2020 }
2021
2022 static void azx_timecounter_init(struct snd_pcm_substream *substream,
2023                                 bool force, cycle_t last)
2024 {
2025         struct azx_dev *azx_dev = get_azx_dev(substream);
2026         struct timecounter *tc = &azx_dev->azx_tc;
2027         struct cyclecounter *cc = &azx_dev->azx_cc;
2028         u64 nsec;
2029
2030         cc->read = azx_cc_read;
2031         cc->mask = CLOCKSOURCE_MASK(32);
2032
2033         /*
2034          * Converting from 24 MHz to ns means applying a 125/3 factor.
2035          * To avoid any saturation issues in intermediate operations,
2036          * the 125 factor is applied first. The division is applied
2037          * last after reading the timecounter value.
2038          * Applying the 1/3 factor as part of the multiplication
2039          * requires at least 20 bits for a decent precision, however
2040          * overflows occur after about 4 hours or less, not a option.
2041          */
2042
2043         cc->mult = 125; /* saturation after 195 years */
2044         cc->shift = 0;
2045
2046         nsec = 0; /* audio time is elapsed time since trigger */
2047         timecounter_init(tc, cc, nsec);
2048         if (force)
2049                 /*
2050                  * force timecounter to use predefined value,
2051                  * used for synchronized starts
2052                  */
2053                 tc->cycle_last = last;
2054 }
2055
2056 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
2057                                 u64 nsec)
2058 {
2059         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2060         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2061         u64 codec_frames, codec_nsecs;
2062
2063         if (!hinfo->ops.get_delay)
2064                 return nsec;
2065
2066         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
2067         codec_nsecs = div_u64(codec_frames * 1000000000LL,
2068                               substream->runtime->rate);
2069
2070         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2071                 return nsec + codec_nsecs;
2072
2073         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
2074 }
2075
2076 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
2077                                 struct timespec *ts)
2078 {
2079         struct azx_dev *azx_dev = get_azx_dev(substream);
2080         u64 nsec;
2081
2082         nsec = timecounter_read(&azx_dev->azx_tc);
2083         nsec = div_u64(nsec, 3); /* can be optimized */
2084         nsec = azx_adjust_codec_delay(substream, nsec);
2085
2086         *ts = ns_to_timespec(nsec);
2087
2088         return 0;
2089 }
2090
2091 static struct snd_pcm_hardware azx_pcm_hw = {
2092         .info =                 (SNDRV_PCM_INFO_MMAP |
2093                                  SNDRV_PCM_INFO_INTERLEAVED |
2094                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
2095                                  SNDRV_PCM_INFO_MMAP_VALID |
2096                                  /* No full-resume yet implemented */
2097                                  /* SNDRV_PCM_INFO_RESUME |*/
2098                                  SNDRV_PCM_INFO_PAUSE |
2099                                  SNDRV_PCM_INFO_SYNC_START |
2100                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
2101                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
2102         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
2103         .rates =                SNDRV_PCM_RATE_48000,
2104         .rate_min =             48000,
2105         .rate_max =             48000,
2106         .channels_min =         2,
2107         .channels_max =         2,
2108         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
2109         .period_bytes_min =     128,
2110         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
2111         .periods_min =          2,
2112         .periods_max =          AZX_MAX_FRAG,
2113         .fifo_size =            0,
2114 };
2115
2116 static int azx_pcm_open(struct snd_pcm_substream *substream)
2117 {
2118         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2119         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2120         struct azx *chip = apcm->chip;
2121         struct azx_dev *azx_dev;
2122         struct snd_pcm_runtime *runtime = substream->runtime;
2123         unsigned long flags;
2124         int err;
2125         int buff_step;
2126
2127         mutex_lock(&chip->open_mutex);
2128         azx_dev = azx_assign_device(chip, substream);
2129         if (azx_dev == NULL) {
2130                 mutex_unlock(&chip->open_mutex);
2131                 return -EBUSY;
2132         }
2133         runtime->hw = azx_pcm_hw;
2134         runtime->hw.channels_min = hinfo->channels_min;
2135         runtime->hw.channels_max = hinfo->channels_max;
2136         runtime->hw.formats = hinfo->formats;
2137         runtime->hw.rates = hinfo->rates;
2138         snd_pcm_limit_hw_rates(runtime);
2139         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2140
2141         /* avoid wrap-around with wall-clock */
2142         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2143                                 20,
2144                                 178000000);
2145
2146         if (chip->align_buffer_size)
2147                 /* constrain buffer sizes to be multiple of 128
2148                    bytes. This is more efficient in terms of memory
2149                    access but isn't required by the HDA spec and
2150                    prevents users from specifying exact period/buffer
2151                    sizes. For example for 44.1kHz, a period size set
2152                    to 20ms will be rounded to 19.59ms. */
2153                 buff_step = 128;
2154         else
2155                 /* Don't enforce steps on buffer sizes, still need to
2156                    be multiple of 4 bytes (HDA spec). Tested on Intel
2157                    HDA controllers, may not work on all devices where
2158                    option needs to be disabled */
2159                 buff_step = 4;
2160
2161         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2162                                    buff_step);
2163         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2164                                    buff_step);
2165         snd_hda_power_up_d3wait(apcm->codec);
2166         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2167         if (err < 0) {
2168                 azx_release_device(azx_dev);
2169                 snd_hda_power_down(apcm->codec);
2170                 mutex_unlock(&chip->open_mutex);
2171                 return err;
2172         }
2173         snd_pcm_limit_hw_rates(runtime);
2174         /* sanity check */
2175         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2176             snd_BUG_ON(!runtime->hw.channels_max) ||
2177             snd_BUG_ON(!runtime->hw.formats) ||
2178             snd_BUG_ON(!runtime->hw.rates)) {
2179                 azx_release_device(azx_dev);
2180                 hinfo->ops.close(hinfo, apcm->codec, substream);
2181                 snd_hda_power_down(apcm->codec);
2182                 mutex_unlock(&chip->open_mutex);
2183                 return -EINVAL;
2184         }
2185
2186         /* disable WALLCLOCK timestamps for capture streams
2187            until we figure out how to handle digital inputs */
2188         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2189                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2190
2191         spin_lock_irqsave(&chip->reg_lock, flags);
2192         azx_dev->substream = substream;
2193         azx_dev->running = 0;
2194         spin_unlock_irqrestore(&chip->reg_lock, flags);
2195
2196         runtime->private_data = azx_dev;
2197         snd_pcm_set_sync(substream);
2198         mutex_unlock(&chip->open_mutex);
2199         return 0;
2200 }
2201
2202 static int azx_pcm_close(struct snd_pcm_substream *substream)
2203 {
2204         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2205         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2206         struct azx *chip = apcm->chip;
2207         struct azx_dev *azx_dev = get_azx_dev(substream);
2208         unsigned long flags;
2209
2210         mutex_lock(&chip->open_mutex);
2211         spin_lock_irqsave(&chip->reg_lock, flags);
2212         azx_dev->substream = NULL;
2213         azx_dev->running = 0;
2214         spin_unlock_irqrestore(&chip->reg_lock, flags);
2215         azx_release_device(azx_dev);
2216         hinfo->ops.close(hinfo, apcm->codec, substream);
2217         snd_hda_power_down(apcm->codec);
2218         mutex_unlock(&chip->open_mutex);
2219         return 0;
2220 }
2221
2222 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2223                              struct snd_pcm_hw_params *hw_params)
2224 {
2225         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2226         struct azx *chip = apcm->chip;
2227         struct azx_dev *azx_dev = get_azx_dev(substream);
2228         int ret;
2229
2230         dsp_lock(azx_dev);
2231         if (dsp_is_locked(azx_dev)) {
2232                 ret = -EBUSY;
2233                 goto unlock;
2234         }
2235
2236         mark_runtime_wc(chip, azx_dev, substream, false);
2237         azx_dev->bufsize = 0;
2238         azx_dev->period_bytes = 0;
2239         azx_dev->format_val = 0;
2240         ret = snd_pcm_lib_malloc_pages(substream,
2241                                         params_buffer_bytes(hw_params));
2242         if (ret < 0)
2243                 goto unlock;
2244         mark_runtime_wc(chip, azx_dev, substream, true);
2245  unlock:
2246         dsp_unlock(azx_dev);
2247         return ret;
2248 }
2249
2250 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2251 {
2252         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2253         struct azx_dev *azx_dev = get_azx_dev(substream);
2254         struct azx *chip = apcm->chip;
2255         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2256
2257         /* reset BDL address */
2258         dsp_lock(azx_dev);
2259         if (!dsp_is_locked(azx_dev)) {
2260                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2261                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2262                 azx_sd_writel(azx_dev, SD_CTL, 0);
2263                 azx_dev->bufsize = 0;
2264                 azx_dev->period_bytes = 0;
2265                 azx_dev->format_val = 0;
2266         }
2267
2268         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2269
2270         mark_runtime_wc(chip, azx_dev, substream, false);
2271         azx_dev->prepared = 0;
2272         dsp_unlock(azx_dev);
2273         return snd_pcm_lib_free_pages(substream);
2274 }
2275
2276 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2277 {
2278         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2279         struct azx *chip = apcm->chip;
2280         struct azx_dev *azx_dev = get_azx_dev(substream);
2281         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2282         struct snd_pcm_runtime *runtime = substream->runtime;
2283         unsigned int bufsize, period_bytes, format_val, stream_tag;
2284         int err;
2285         struct hda_spdif_out *spdif =
2286                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2287         unsigned short ctls = spdif ? spdif->ctls : 0;
2288
2289         dsp_lock(azx_dev);
2290         if (dsp_is_locked(azx_dev)) {
2291                 err = -EBUSY;
2292                 goto unlock;
2293         }
2294
2295         azx_stream_reset(chip, azx_dev);
2296         format_val = snd_hda_calc_stream_format(runtime->rate,
2297                                                 runtime->channels,
2298                                                 runtime->format,
2299                                                 hinfo->maxbps,
2300                                                 ctls);
2301         if (!format_val) {
2302                 snd_printk(KERN_ERR SFX
2303                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2304                            pci_name(chip->pci), runtime->rate, runtime->channels, runtime->format);
2305                 err = -EINVAL;
2306                 goto unlock;
2307         }
2308
2309         bufsize = snd_pcm_lib_buffer_bytes(substream);
2310         period_bytes = snd_pcm_lib_period_bytes(substream);
2311
2312         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2313                     pci_name(chip->pci), bufsize, format_val);
2314
2315         if (bufsize != azx_dev->bufsize ||
2316             period_bytes != azx_dev->period_bytes ||
2317             format_val != azx_dev->format_val ||
2318             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2319                 azx_dev->bufsize = bufsize;
2320                 azx_dev->period_bytes = period_bytes;
2321                 azx_dev->format_val = format_val;
2322                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2323                 err = azx_setup_periods(chip, substream, azx_dev);
2324                 if (err < 0)
2325                         goto unlock;
2326         }
2327
2328         /* wallclk has 24Mhz clock source */
2329         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2330                                                 runtime->rate) * 1000);
2331         azx_setup_controller(chip, azx_dev);
2332         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2333                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2334         else
2335                 azx_dev->fifo_size = 0;
2336
2337         stream_tag = azx_dev->stream_tag;
2338         /* CA-IBG chips need the playback stream starting from 1 */
2339         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2340             stream_tag > chip->capture_streams)
2341                 stream_tag -= chip->capture_streams;
2342         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2343                                      azx_dev->format_val, substream);
2344
2345  unlock:
2346         if (!err)
2347                 azx_dev->prepared = 1;
2348         dsp_unlock(azx_dev);
2349         return err;
2350 }
2351
2352 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2353 {
2354         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2355         struct azx *chip = apcm->chip;
2356         struct azx_dev *azx_dev;
2357         struct snd_pcm_substream *s;
2358         int rstart = 0, start, nsync = 0, sbits = 0;
2359         int nwait, timeout;
2360
2361         azx_dev = get_azx_dev(substream);
2362         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2363
2364         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2365                 return -EPIPE;
2366
2367         switch (cmd) {
2368         case SNDRV_PCM_TRIGGER_START:
2369                 rstart = 1;
2370         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2371         case SNDRV_PCM_TRIGGER_RESUME:
2372                 start = 1;
2373                 break;
2374         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2375         case SNDRV_PCM_TRIGGER_SUSPEND:
2376         case SNDRV_PCM_TRIGGER_STOP:
2377                 start = 0;
2378                 break;
2379         default:
2380                 return -EINVAL;
2381         }
2382
2383         snd_pcm_group_for_each_entry(s, substream) {
2384                 if (s->pcm->card != substream->pcm->card)
2385                         continue;
2386                 azx_dev = get_azx_dev(s);
2387                 sbits |= 1 << azx_dev->index;
2388                 nsync++;
2389                 snd_pcm_trigger_done(s, substream);
2390         }
2391
2392         spin_lock(&chip->reg_lock);
2393
2394         /* first, set SYNC bits of corresponding streams */
2395         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2396                 azx_writel(chip, OLD_SSYNC,
2397                         azx_readl(chip, OLD_SSYNC) | sbits);
2398         else
2399                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2400
2401         snd_pcm_group_for_each_entry(s, substream) {
2402                 if (s->pcm->card != substream->pcm->card)
2403                         continue;
2404                 azx_dev = get_azx_dev(s);
2405                 if (start) {
2406                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2407                         if (!rstart)
2408                                 azx_dev->start_wallclk -=
2409                                                 azx_dev->period_wallclk;
2410                         azx_stream_start(chip, azx_dev);
2411                 } else {
2412                         azx_stream_stop(chip, azx_dev);
2413                 }
2414                 azx_dev->running = start;
2415         }
2416         spin_unlock(&chip->reg_lock);
2417         if (start) {
2418                 /* wait until all FIFOs get ready */
2419                 for (timeout = 5000; timeout; timeout--) {
2420                         nwait = 0;
2421                         snd_pcm_group_for_each_entry(s, substream) {
2422                                 if (s->pcm->card != substream->pcm->card)
2423                                         continue;
2424                                 azx_dev = get_azx_dev(s);
2425                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2426                                       SD_STS_FIFO_READY))
2427                                         nwait++;
2428                         }
2429                         if (!nwait)
2430                                 break;
2431                         cpu_relax();
2432                 }
2433         } else {
2434                 /* wait until all RUN bits are cleared */
2435                 for (timeout = 5000; timeout; timeout--) {
2436                         nwait = 0;
2437                         snd_pcm_group_for_each_entry(s, substream) {
2438                                 if (s->pcm->card != substream->pcm->card)
2439                                         continue;
2440                                 azx_dev = get_azx_dev(s);
2441                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2442                                     SD_CTL_DMA_START)
2443                                         nwait++;
2444                         }
2445                         if (!nwait)
2446                                 break;
2447                         cpu_relax();
2448                 }
2449         }
2450         spin_lock(&chip->reg_lock);
2451         /* reset SYNC bits */
2452         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2453                 azx_writel(chip, OLD_SSYNC,
2454                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2455         else
2456                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2457         if (start) {
2458                 azx_timecounter_init(substream, 0, 0);
2459                 if (nsync > 1) {
2460                         cycle_t cycle_last;
2461
2462                         /* same start cycle for master and group */
2463                         azx_dev = get_azx_dev(substream);
2464                         cycle_last = azx_dev->azx_tc.cycle_last;
2465
2466                         snd_pcm_group_for_each_entry(s, substream) {
2467                                 if (s->pcm->card != substream->pcm->card)
2468                                         continue;
2469                                 azx_timecounter_init(s, 1, cycle_last);
2470                         }
2471                 }
2472         }
2473         spin_unlock(&chip->reg_lock);
2474         return 0;
2475 }
2476
2477 /* get the current DMA position with correction on VIA chips */
2478 static unsigned int azx_via_get_position(struct azx *chip,
2479                                          struct azx_dev *azx_dev)
2480 {
2481         unsigned int link_pos, mini_pos, bound_pos;
2482         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2483         unsigned int fifo_size;
2484
2485         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2486         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2487                 /* Playback, no problem using link position */
2488                 return link_pos;
2489         }
2490
2491         /* Capture */
2492         /* For new chipset,
2493          * use mod to get the DMA position just like old chipset
2494          */
2495         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2496         mod_dma_pos %= azx_dev->period_bytes;
2497
2498         /* azx_dev->fifo_size can't get FIFO size of in stream.
2499          * Get from base address + offset.
2500          */
2501         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2502
2503         if (azx_dev->insufficient) {
2504                 /* Link position never gather than FIFO size */
2505                 if (link_pos <= fifo_size)
2506                         return 0;
2507
2508                 azx_dev->insufficient = 0;
2509         }
2510
2511         if (link_pos <= fifo_size)
2512                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2513         else
2514                 mini_pos = link_pos - fifo_size;
2515
2516         /* Find nearest previous boudary */
2517         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2518         mod_link_pos = link_pos % azx_dev->period_bytes;
2519         if (mod_link_pos >= fifo_size)
2520                 bound_pos = link_pos - mod_link_pos;
2521         else if (mod_dma_pos >= mod_mini_pos)
2522                 bound_pos = mini_pos - mod_mini_pos;
2523         else {
2524                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2525                 if (bound_pos >= azx_dev->bufsize)
2526                         bound_pos = 0;
2527         }
2528
2529         /* Calculate real DMA position we want */
2530         return bound_pos + mod_dma_pos;
2531 }
2532
2533 static unsigned int azx_get_position(struct azx *chip,
2534                                      struct azx_dev *azx_dev,
2535                                      bool with_check)
2536 {
2537         struct snd_pcm_substream *substream = azx_dev->substream;
2538         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2539         unsigned int pos;
2540         int stream = substream->stream;
2541         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2542         int delay = 0;
2543
2544         switch (chip->position_fix[stream]) {
2545         case POS_FIX_LPIB:
2546                 /* read LPIB */
2547                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2548                 break;
2549         case POS_FIX_VIACOMBO:
2550                 pos = azx_via_get_position(chip, azx_dev);
2551                 break;
2552         default:
2553                 /* use the position buffer */
2554                 pos = le32_to_cpu(*azx_dev->posbuf);
2555                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2556                         if (!pos || pos == (u32)-1) {
2557                                 printk(KERN_WARNING
2558                                        "hda-intel: Invalid position buffer, "
2559                                        "using LPIB read method instead.\n");
2560                                 chip->position_fix[stream] = POS_FIX_LPIB;
2561                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2562                         } else
2563                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2564                 }
2565                 break;
2566         }
2567
2568         if (pos >= azx_dev->bufsize)
2569                 pos = 0;
2570
2571         /* calculate runtime delay from LPIB */
2572         if (substream->runtime &&
2573             chip->position_fix[stream] == POS_FIX_POSBUF &&
2574             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2575                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2576                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2577                         delay = pos - lpib_pos;
2578                 else
2579                         delay = lpib_pos - pos;
2580                 if (delay < 0)
2581                         delay += azx_dev->bufsize;
2582                 if (delay >= azx_dev->period_bytes) {
2583                         snd_printk(KERN_WARNING SFX
2584                                    "%s: Unstable LPIB (%d >= %d); "
2585                                    "disabling LPIB delay counting\n",
2586                                    pci_name(chip->pci), delay, azx_dev->period_bytes);
2587                         delay = 0;
2588                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2589                 }
2590                 delay = bytes_to_frames(substream->runtime, delay);
2591         }
2592
2593         if (substream->runtime) {
2594                 if (hinfo->ops.get_delay)
2595                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2596                                                       substream);
2597                 substream->runtime->delay = delay;
2598         }
2599
2600         trace_azx_get_position(chip, azx_dev, pos, delay);
2601         return pos;
2602 }
2603
2604 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2605 {
2606         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2607         struct azx *chip = apcm->chip;
2608         struct azx_dev *azx_dev = get_azx_dev(substream);
2609         return bytes_to_frames(substream->runtime,
2610                                azx_get_position(chip, azx_dev, false));
2611 }
2612
2613 /*
2614  * Check whether the current DMA position is acceptable for updating
2615  * periods.  Returns non-zero if it's OK.
2616  *
2617  * Many HD-audio controllers appear pretty inaccurate about
2618  * the update-IRQ timing.  The IRQ is issued before actually the
2619  * data is processed.  So, we need to process it afterwords in a
2620  * workqueue.
2621  */
2622 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2623 {
2624         u32 wallclk;
2625         unsigned int pos;
2626
2627         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2628         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2629                 return -1;      /* bogus (too early) interrupt */
2630
2631         pos = azx_get_position(chip, azx_dev, true);
2632
2633         if (WARN_ONCE(!azx_dev->period_bytes,
2634                       "hda-intel: zero azx_dev->period_bytes"))
2635                 return -1; /* this shouldn't happen! */
2636         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2637             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2638                 /* NG - it's below the first next period boundary */
2639                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2640         azx_dev->start_wallclk += wallclk;
2641         return 1; /* OK, it's fine */
2642 }
2643
2644 /*
2645  * The work for pending PCM period updates.
2646  */
2647 static void azx_irq_pending_work(struct work_struct *work)
2648 {
2649         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2650         int i, pending, ok;
2651
2652         if (!chip->irq_pending_warned) {
2653                 printk(KERN_WARNING
2654                        "hda-intel: IRQ timing workaround is activated "
2655                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2656                        chip->card->number);
2657                 chip->irq_pending_warned = 1;
2658         }
2659
2660         for (;;) {
2661                 pending = 0;
2662                 spin_lock_irq(&chip->reg_lock);
2663                 for (i = 0; i < chip->num_streams; i++) {
2664                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2665                         if (!azx_dev->irq_pending ||
2666                             !azx_dev->substream ||
2667                             !azx_dev->running)
2668                                 continue;
2669                         ok = azx_position_ok(chip, azx_dev);
2670                         if (ok > 0) {
2671                                 azx_dev->irq_pending = 0;
2672                                 spin_unlock(&chip->reg_lock);
2673                                 snd_pcm_period_elapsed(azx_dev->substream);
2674                                 spin_lock(&chip->reg_lock);
2675                         } else if (ok < 0) {
2676                                 pending = 0;    /* too early */
2677                         } else
2678                                 pending++;
2679                 }
2680                 spin_unlock_irq(&chip->reg_lock);
2681                 if (!pending)
2682                         return;
2683                 msleep(1);
2684         }
2685 }
2686
2687 /* clear irq_pending flags and assure no on-going workq */
2688 static void azx_clear_irq_pending(struct azx *chip)
2689 {
2690         int i;
2691
2692         spin_lock_irq(&chip->reg_lock);
2693         for (i = 0; i < chip->num_streams; i++)
2694                 chip->azx_dev[i].irq_pending = 0;
2695         spin_unlock_irq(&chip->reg_lock);
2696 }
2697
2698 #ifdef CONFIG_X86
2699 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2700                         struct vm_area_struct *area)
2701 {
2702         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2703         struct azx *chip = apcm->chip;
2704         if (!azx_snoop(chip))
2705                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2706         return snd_pcm_lib_default_mmap(substream, area);
2707 }
2708 #else
2709 #define azx_pcm_mmap    NULL
2710 #endif
2711
2712 static struct snd_pcm_ops azx_pcm_ops = {
2713         .open = azx_pcm_open,
2714         .close = azx_pcm_close,
2715         .ioctl = snd_pcm_lib_ioctl,
2716         .hw_params = azx_pcm_hw_params,
2717         .hw_free = azx_pcm_hw_free,
2718         .prepare = azx_pcm_prepare,
2719         .trigger = azx_pcm_trigger,
2720         .pointer = azx_pcm_pointer,
2721         .wall_clock =  azx_get_wallclock_tstamp,
2722         .mmap = azx_pcm_mmap,
2723         .page = snd_pcm_sgbuf_ops_page,
2724 };
2725
2726 static void azx_pcm_free(struct snd_pcm *pcm)
2727 {
2728         struct azx_pcm *apcm = pcm->private_data;
2729         if (apcm) {
2730                 list_del(&apcm->list);
2731                 kfree(apcm);
2732         }
2733 }
2734
2735 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2736
2737 static int
2738 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2739                       struct hda_pcm *cpcm)
2740 {
2741         struct azx *chip = bus->private_data;
2742         struct snd_pcm *pcm;
2743         struct azx_pcm *apcm;
2744         int pcm_dev = cpcm->device;
2745         unsigned int size;
2746         int s, err;
2747
2748         list_for_each_entry(apcm, &chip->pcm_list, list) {
2749                 if (apcm->pcm->device == pcm_dev) {
2750                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2751                                    pci_name(chip->pci), pcm_dev);
2752                         return -EBUSY;
2753                 }
2754         }
2755         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2756                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2757                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2758                           &pcm);
2759         if (err < 0)
2760                 return err;
2761         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2762         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2763         if (apcm == NULL)
2764                 return -ENOMEM;
2765         apcm->chip = chip;
2766         apcm->pcm = pcm;
2767         apcm->codec = codec;
2768         pcm->private_data = apcm;
2769         pcm->private_free = azx_pcm_free;
2770         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2771                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2772         list_add_tail(&apcm->list, &chip->pcm_list);
2773         cpcm->pcm = pcm;
2774         for (s = 0; s < 2; s++) {
2775                 apcm->hinfo[s] = &cpcm->stream[s];
2776                 if (cpcm->stream[s].substreams)
2777                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2778         }
2779         /* buffer pre-allocation */
2780         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2781         if (size > MAX_PREALLOC_SIZE)
2782                 size = MAX_PREALLOC_SIZE;
2783         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2784                                               chip->dev,
2785                                               size, MAX_PREALLOC_SIZE);
2786         return 0;
2787 }
2788
2789 /*
2790  * mixer creation - all stuff is implemented in hda module
2791  */
2792 static int azx_mixer_create(struct azx *chip)
2793 {
2794         return snd_hda_build_controls(chip->bus);
2795 }
2796
2797
2798 /*
2799  * initialize SD streams
2800  */
2801 static int azx_init_stream(struct azx *chip)
2802 {
2803         int i;
2804
2805         /* initialize each stream (aka device)
2806          * assign the starting bdl address to each stream (device)
2807          * and initialize
2808          */
2809         for (i = 0; i < chip->num_streams; i++) {
2810                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2811                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2812                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2813                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2814                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2815                 azx_dev->sd_int_sta_mask = 1 << i;
2816                 /* stream tag: must be non-zero and unique */
2817                 azx_dev->index = i;
2818                 azx_dev->stream_tag = i + 1;
2819         }
2820
2821         return 0;
2822 }
2823
2824 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2825 {
2826         if (request_irq(chip->irq_id, azx_interrupt,
2827                         chip->msi ? 0 : IRQF_SHARED,
2828                         KBUILD_MODNAME, chip)) {
2829                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2830                        "disabling device\n", chip->irq_id);
2831                 if (do_disconnect)
2832                         snd_card_disconnect(chip->card);
2833                 return -1;
2834         }
2835         chip->irq = chip->irq_id;
2836         if (chip->pci)
2837                 pci_intx(chip->pci, !chip->msi);
2838
2839         return 0;
2840 }
2841
2842
2843 static void azx_stop_chip(struct azx *chip)
2844 {
2845         if (!chip->initialized)
2846                 return;
2847
2848         /* disable interrupts */
2849         azx_int_disable(chip);
2850         azx_int_clear(chip);
2851
2852         /* disable CORB/RIRB */
2853         azx_free_cmd_io(chip);
2854
2855         /* disable position buffer */
2856         azx_writel(chip, DPLBASE, 0);
2857         azx_writel(chip, DPUBASE, 0);
2858
2859         chip->initialized = 0;
2860 }
2861
2862 #ifdef CONFIG_SND_HDA_DSP_LOADER
2863 /*
2864  * DSP loading code (e.g. for CA0132)
2865  */
2866
2867 /* use the first stream for loading DSP */
2868 static struct azx_dev *
2869 azx_get_dsp_loader_dev(struct azx *chip)
2870 {
2871         return &chip->azx_dev[chip->playback_index_offset];
2872 }
2873
2874 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
2875                                 unsigned int byte_size,
2876                                 struct snd_dma_buffer *bufp)
2877 {
2878         u32 *bdl;
2879         struct azx *chip = bus->private_data;
2880         struct azx_dev *azx_dev;
2881         int err;
2882
2883         azx_dev = azx_get_dsp_loader_dev(chip);
2884
2885         dsp_lock(azx_dev);
2886         spin_lock_irq(&chip->reg_lock);
2887         if (azx_dev->running || azx_dev->locked) {
2888                 spin_unlock_irq(&chip->reg_lock);
2889                 err = -EBUSY;
2890                 goto unlock;
2891         }
2892         azx_dev->prepared = 0;
2893         chip->saved_azx_dev = *azx_dev;
2894         azx_dev->locked = 1;
2895         spin_unlock_irq(&chip->reg_lock);
2896
2897         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
2898                                   snd_dma_pci_data(chip->pci),
2899                                   byte_size, bufp);
2900         if (err < 0)
2901                 goto err_alloc;
2902
2903         mark_pages_wc(chip, bufp, true);
2904         azx_dev->bufsize = byte_size;
2905         azx_dev->period_bytes = byte_size;
2906         azx_dev->format_val = format;
2907
2908         azx_stream_reset(chip, azx_dev);
2909
2910         /* reset BDL address */
2911         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2912         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2913
2914         azx_dev->frags = 0;
2915         bdl = (u32 *)azx_dev->bdl.area;
2916         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
2917         if (err < 0)
2918                 goto error;
2919
2920         azx_setup_controller(chip, azx_dev);
2921         dsp_unlock(azx_dev);
2922         return azx_dev->stream_tag;
2923
2924  error:
2925         mark_pages_wc(chip, bufp, false);
2926         snd_dma_free_pages(bufp);
2927  err_alloc:
2928         spin_lock_irq(&chip->reg_lock);
2929         if (azx_dev->opened)
2930                 *azx_dev = chip->saved_azx_dev;
2931         azx_dev->locked = 0;
2932         spin_unlock_irq(&chip->reg_lock);
2933  unlock:
2934         dsp_unlock(azx_dev);
2935         return err;
2936 }
2937
2938 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
2939 {
2940         struct azx *chip = bus->private_data;
2941         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2942
2943         if (start)
2944                 azx_stream_start(chip, azx_dev);
2945         else
2946                 azx_stream_stop(chip, azx_dev);
2947         azx_dev->running = start;
2948 }
2949
2950 static void azx_load_dsp_cleanup(struct hda_bus *bus,
2951                                  struct snd_dma_buffer *dmab)
2952 {
2953         struct azx *chip = bus->private_data;
2954         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
2955
2956         if (!dmab->area || !azx_dev->locked)
2957                 return;
2958
2959         dsp_lock(azx_dev);
2960         /* reset BDL address */
2961         azx_sd_writel(azx_dev, SD_BDLPL, 0);
2962         azx_sd_writel(azx_dev, SD_BDLPU, 0);
2963         azx_sd_writel(azx_dev, SD_CTL, 0);
2964         azx_dev->bufsize = 0;
2965         azx_dev->period_bytes = 0;
2966         azx_dev->format_val = 0;
2967
2968         mark_pages_wc(chip, dmab, false);
2969         snd_dma_free_pages(dmab);
2970         dmab->area = NULL;
2971
2972         spin_lock_irq(&chip->reg_lock);
2973         if (azx_dev->opened)
2974                 *azx_dev = chip->saved_azx_dev;
2975         azx_dev->locked = 0;
2976         spin_unlock_irq(&chip->reg_lock);
2977         dsp_unlock(azx_dev);
2978 }
2979 #endif /* CONFIG_SND_HDA_DSP_LOADER */
2980
2981 #ifdef CONFIG_PM
2982 /* power-up/down the controller */
2983 static void azx_power_notify(struct hda_bus *bus, bool power_up)
2984 {
2985         struct azx *chip = bus->private_data;
2986
2987         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
2988                 return;
2989
2990         if (power_up)
2991                 pm_runtime_get_sync(&chip->pci->dev);
2992         else
2993                 pm_runtime_put_sync(&chip->pci->dev);
2994 }
2995
2996 static DEFINE_MUTEX(card_list_lock);
2997 static LIST_HEAD(card_list);
2998
2999 static void azx_add_card_list(struct azx *chip)
3000 {
3001         mutex_lock(&card_list_lock);
3002         list_add(&chip->list, &card_list);
3003         mutex_unlock(&card_list_lock);
3004 }
3005
3006 static void azx_del_card_list(struct azx *chip)
3007 {
3008         mutex_lock(&card_list_lock);
3009         list_del_init(&chip->list);
3010         mutex_unlock(&card_list_lock);
3011 }
3012
3013 /* trigger power-save check at writing parameter */
3014 static int param_set_xint(const char *val, const struct kernel_param *kp)
3015 {
3016         struct azx *chip;
3017         struct hda_codec *c;
3018         int prev = power_save;
3019         int ret = param_set_int(val, kp);
3020
3021         if (ret || prev == power_save)
3022                 return ret;
3023
3024         mutex_lock(&card_list_lock);
3025         list_for_each_entry(chip, &card_list, list) {
3026                 if (!chip->bus || chip->disabled)
3027                         continue;
3028                 list_for_each_entry(c, &chip->bus->codec_list, list)
3029                         snd_hda_power_sync(c);
3030         }
3031         mutex_unlock(&card_list_lock);
3032         return 0;
3033 }
3034 #else
3035 #define azx_add_card_list(chip) /* NOP */
3036 #define azx_del_card_list(chip) /* NOP */
3037 #endif /* CONFIG_PM */
3038
3039 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
3040 /*
3041  * power management
3042  */
3043 static int azx_suspend(struct device *dev)
3044 {
3045         struct snd_card *card = dev_get_drvdata(dev);
3046         struct azx *chip = card->private_data;
3047         struct azx_pcm *p;
3048
3049         if (chip->disabled)
3050                 return 0;
3051
3052 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3053         defined(CONFIG_SND_HDA_POWER_SAVE)
3054         if (chip->pdev)
3055                 azx_platform_enable_clocks(chip);
3056 #endif
3057
3058         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3059         azx_clear_irq_pending(chip);
3060         list_for_each_entry(p, &chip->pcm_list, list)
3061                 snd_pcm_suspend_all(p->pcm);
3062         if (chip->initialized)
3063                 snd_hda_suspend(chip->bus);
3064         azx_stop_chip(chip);
3065         if (chip->irq >= 0) {
3066                 free_irq(chip->irq, chip);
3067                 chip->irq = -1;
3068         }
3069
3070         if (chip->pci) {
3071                 if (chip->msi)
3072                         pci_disable_msi(chip->pci);
3073                 pci_disable_device(chip->pci);
3074                 pci_save_state(chip->pci);
3075                 pci_set_power_state(pci, PCI_D3hot);
3076         }
3077
3078 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3079         if (chip->pdev) {
3080                 /* Disable all clk references */
3081                 while (chip->platform_clk_enable)
3082                         azx_platform_disable_clocks(chip);
3083         }
3084 #endif
3085
3086         return 0;
3087 }
3088
3089 static int azx_resume(struct device *dev)
3090 {
3091         struct snd_card *card = dev_get_drvdata(dev);
3092         struct azx *chip = card->private_data;
3093
3094         if (chip->disabled)
3095                 return 0;
3096
3097 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3098         if (chip->pdev)
3099                 azx_platform_enable_clocks(chip);
3100 #endif
3101
3102         if (chip->pci) {
3103                 pci_set_power_state(chip->pci, PCI_D0);
3104                 pci_restore_state(chip->pci);
3105                 if (pci_enable_device(chip->pci) < 0) {
3106                         printk(KERN_ERR "hda-intel: pci_enable_device failed, "
3107                                "disabling device\n");
3108                         snd_card_disconnect(card);
3109                         return -EIO;
3110                 }
3111                 pci_set_master(chip->pci);
3112                 if (chip->msi)
3113                         if (pci_enable_msi(chip->pci) < 0)
3114                                 chip->msi = 0;
3115         }
3116
3117         if (azx_acquire_irq(chip, 1) < 0)
3118                 return -EIO;
3119
3120         if (chip->pci)
3121                 azx_init_pci(chip);
3122
3123 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3124         if (chip->pdev)
3125                 azx_init_platform(chip);
3126 #endif
3127
3128         if (snd_hda_codecs_inuse(chip->bus))
3129                 azx_init_chip(chip, 1);
3130
3131         snd_hda_resume(chip->bus);
3132         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3133
3134 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3135         defined(CONFIG_SND_HDA_POWER_SAVE)
3136         if (chip->pdev)
3137                 azx_platform_disable_clocks(chip);
3138 #endif
3139
3140         return 0;
3141 }
3142 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
3143
3144 #ifdef CONFIG_PM_RUNTIME
3145 static int azx_runtime_suspend(struct device *dev)
3146 {
3147         struct snd_card *card = dev_get_drvdata(dev);
3148         struct azx *chip = card->private_data;
3149
3150         azx_stop_chip(chip);
3151 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3152         azx_platform_disable_clocks(chip);
3153 #endif
3154         azx_clear_irq_pending(chip);
3155         return 0;
3156 }
3157
3158 static int azx_runtime_resume(struct device *dev)
3159 {
3160         struct snd_card *card = dev_get_drvdata(dev);
3161         struct azx *chip = card->private_data;
3162
3163         azx_init_pci(chip);
3164 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3165         azx_platform_enable_clocks(chip);
3166 #endif
3167         azx_init_chip(chip, 1);
3168         return 0;
3169 }
3170
3171 static int azx_runtime_idle(struct device *dev)
3172 {
3173         struct snd_card *card = dev_get_drvdata(dev);
3174         struct azx *chip = card->private_data;
3175
3176         if (!power_save_controller ||
3177             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3178                 return -EBUSY;
3179
3180         return 0;
3181 }
3182
3183 #endif /* CONFIG_PM_RUNTIME */
3184
3185 #ifdef CONFIG_PM
3186 static const struct dev_pm_ops azx_pm = {
3187         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3188         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3189 };
3190
3191 #define AZX_PM_OPS      &azx_pm
3192 #else
3193 #define AZX_PM_OPS      NULL
3194 #endif /* CONFIG_PM */
3195
3196
3197 /*
3198  * reboot notifier for hang-up problem at power-down
3199  */
3200 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3201 {
3202         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3203
3204 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3205         defined(CONFIG_SND_HDA_POWER_SAVE)
3206         if (chip->pdev)
3207                 azx_platform_enable_clocks(chip);
3208 #endif
3209
3210         snd_hda_bus_reboot_notify(chip->bus);
3211         azx_stop_chip(chip);
3212
3213 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER) && \
3214         defined(CONFIG_SND_HDA_POWER_SAVE)
3215         if (chip->pdev)
3216                 azx_platform_disable_clocks(chip);
3217 #endif
3218
3219         return NOTIFY_OK;
3220 }
3221
3222 static void azx_notifier_register(struct azx *chip)
3223 {
3224         chip->reboot_notifier.notifier_call = azx_halt;
3225         register_reboot_notifier(&chip->reboot_notifier);
3226 }
3227
3228 static void azx_notifier_unregister(struct azx *chip)
3229 {
3230         if (chip->reboot_notifier.notifier_call)
3231                 unregister_reboot_notifier(&chip->reboot_notifier);
3232 }
3233
3234 static int azx_first_init(struct azx *chip);
3235 static int azx_probe_continue(struct azx *chip);
3236
3237 #ifdef SUPPORT_VGA_SWITCHEROO
3238 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3239
3240 static void azx_vs_set_state(struct pci_dev *pci,
3241                              enum vga_switcheroo_state state)
3242 {
3243         struct snd_card *card = pci_get_drvdata(pci);
3244         struct azx *chip = card->private_data;
3245         bool disabled;
3246
3247         wait_for_completion(&chip->probe_wait);
3248         if (chip->init_failed)
3249                 return;
3250
3251         disabled = (state == VGA_SWITCHEROO_OFF);
3252         if (chip->disabled == disabled)
3253                 return;
3254
3255         if (!chip->bus) {
3256                 chip->disabled = disabled;
3257                 if (!disabled) {
3258                         snd_printk(KERN_INFO SFX
3259                                    "%s: Start delayed initialization\n",
3260                                    pci_name(chip->pci));
3261                         if (azx_first_init(chip) < 0 ||
3262                             azx_probe_continue(chip) < 0) {
3263                                 snd_printk(KERN_ERR SFX
3264                                            "%s: initialization error\n",
3265                                            pci_name(chip->pci));
3266                                 chip->init_failed = true;
3267                         }
3268                 }
3269         } else {
3270                 snd_printk(KERN_INFO SFX
3271                            "%s: %s via VGA-switcheroo\n", pci_name(chip->pci),
3272                            disabled ? "Disabling" : "Enabling");
3273                 if (disabled) {
3274                         azx_suspend(&pci->dev);
3275                         chip->disabled = true;
3276                         if (snd_hda_lock_devices(chip->bus))
3277                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3278                                            pci_name(chip->pci));
3279                 } else {
3280                         snd_hda_unlock_devices(chip->bus);
3281                         chip->disabled = false;
3282                         azx_resume(&pci->dev);
3283                 }
3284         }
3285 }
3286
3287 static bool azx_vs_can_switch(struct pci_dev *pci)
3288 {
3289         struct snd_card *card = pci_get_drvdata(pci);
3290         struct azx *chip = card->private_data;
3291
3292         wait_for_completion(&chip->probe_wait);
3293         if (chip->init_failed)
3294                 return false;
3295         if (chip->disabled || !chip->bus)
3296                 return true;
3297         if (snd_hda_lock_devices(chip->bus))
3298                 return false;
3299         snd_hda_unlock_devices(chip->bus);
3300         return true;
3301 }
3302
3303 static void init_vga_switcheroo(struct azx *chip)
3304 {
3305         struct pci_dev *p = get_bound_vga(chip->pci);
3306         if (p) {
3307                 snd_printk(KERN_INFO SFX
3308                            "%s: Handle VGA-switcheroo audio client\n",
3309                            pci_name(chip->pci));
3310                 chip->use_vga_switcheroo = 1;
3311                 pci_dev_put(p);
3312         }
3313 }
3314
3315 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3316         .set_gpu_state = azx_vs_set_state,
3317         .can_switch = azx_vs_can_switch,
3318 };
3319
3320 static int register_vga_switcheroo(struct azx *chip)
3321 {
3322         int err;
3323
3324         if (!chip->use_vga_switcheroo)
3325                 return 0;
3326         /* FIXME: currently only handling DIS controller
3327          * is there any machine with two switchable HDMI audio controllers?
3328          */
3329         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3330                                                     VGA_SWITCHEROO_DIS,
3331                                                     chip->bus != NULL);
3332         if (err < 0)
3333                 return err;
3334         chip->vga_switcheroo_registered = 1;
3335         return 0;
3336 }
3337 #else
3338 #define init_vga_switcheroo(chip)               /* NOP */
3339 #define register_vga_switcheroo(chip)           0
3340 #define check_hdmi_disabled(pci)        false
3341 #endif /* SUPPORT_VGA_SWITCHER */
3342
3343 /*
3344  * destructor
3345  */
3346 static int azx_free(struct azx *chip)
3347 {
3348         int i;
3349
3350         azx_del_card_list(chip);
3351
3352         azx_notifier_unregister(chip);
3353
3354         chip->init_failed = 1; /* to be sure */
3355         complete_all(&chip->probe_wait);
3356
3357         if (use_vga_switcheroo(chip)) {
3358                 if (chip->disabled && chip->bus)
3359                         snd_hda_unlock_devices(chip->bus);
3360                 if (chip->vga_switcheroo_registered)
3361                         vga_switcheroo_unregister_client(chip->pci);
3362         }
3363
3364         if (chip->initialized) {
3365                 azx_clear_irq_pending(chip);
3366                 for (i = 0; i < chip->num_streams; i++)
3367                         azx_stream_stop(chip, &chip->azx_dev[i]);
3368                 azx_stop_chip(chip);
3369         }
3370
3371 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3372         azx_platform_disable_clocks(chip);
3373         for (i = 0; i < chip->platform_clk_count; i++)
3374                 clk_put(chip->platform_clks[i]);
3375 #endif
3376
3377         if (chip->irq >= 0)
3378                 free_irq(chip->irq, (void*)chip);
3379         if (chip->pci && chip->msi)
3380                 pci_disable_msi(chip->pci);
3381         if (chip->remap_addr)
3382                 iounmap(chip->remap_addr);
3383
3384         if (chip->azx_dev) {
3385                 for (i = 0; i < chip->num_streams; i++)
3386                         if (chip->azx_dev[i].bdl.area) {
3387                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3388                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3389                         }
3390         }
3391         if (chip->rb.area) {
3392                 mark_pages_wc(chip, &chip->rb, false);
3393                 snd_dma_free_pages(&chip->rb);
3394         }
3395         if (chip->posbuf.area) {
3396                 mark_pages_wc(chip, &chip->posbuf, false);
3397                 snd_dma_free_pages(&chip->posbuf);
3398         }
3399         if (chip->pci) {
3400                 if (chip->region_requested)
3401                         pci_release_regions(chip->pci);
3402                 pci_disable_device(chip->pci);
3403         }
3404         kfree(chip->azx_dev);
3405 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3406         if (chip->fw)
3407                 release_firmware(chip->fw);
3408 #endif
3409         kfree(chip);
3410
3411         return 0;
3412 }
3413
3414 static int azx_dev_free(struct snd_device *device)
3415 {
3416         return azx_free(device->device_data);
3417 }
3418
3419 #ifdef SUPPORT_VGA_SWITCHEROO
3420 /*
3421  * Check of disabled HDMI controller by vga-switcheroo
3422  */
3423 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3424 {
3425         struct pci_dev *p;
3426
3427         /* check only discrete GPU */
3428         switch (pci->vendor) {
3429         case PCI_VENDOR_ID_ATI:
3430         case PCI_VENDOR_ID_AMD:
3431         case PCI_VENDOR_ID_NVIDIA:
3432                 if (pci->devfn == 1) {
3433                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3434                                                         pci->bus->number, 0);
3435                         if (p) {
3436                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3437                                         return p;
3438                                 pci_dev_put(p);
3439                         }
3440                 }
3441                 break;
3442         }
3443         return NULL;
3444 }
3445
3446 static bool check_hdmi_disabled(struct pci_dev *pci)
3447 {
3448         bool vga_inactive = false;
3449         struct pci_dev *p = get_bound_vga(pci);
3450
3451         if (p) {
3452                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3453                         vga_inactive = true;
3454                 pci_dev_put(p);
3455         }
3456         return vga_inactive;
3457 }
3458 #endif /* SUPPORT_VGA_SWITCHEROO */
3459
3460 /*
3461  * white/black-listing for position_fix
3462  */
3463 static struct snd_pci_quirk position_fix_list[] = {
3464         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3465         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3466         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3467         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3468         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3469         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3470         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3471         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3472         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3473         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3474         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3475         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3476         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3477         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3478         {}
3479 };
3480
3481 static int check_position_fix(struct azx *chip, int fix)
3482 {
3483         const struct snd_pci_quirk *q;
3484
3485         switch (fix) {
3486         case POS_FIX_AUTO:
3487         case POS_FIX_LPIB:
3488         case POS_FIX_POSBUF:
3489         case POS_FIX_VIACOMBO:
3490         case POS_FIX_COMBO:
3491                 return fix;
3492         }
3493
3494         if (chip->pci) {
3495                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3496                 if (q) {
3497                         printk(KERN_INFO
3498                                "hda_intel: position_fix set to %d "
3499                                "for device %04x:%04x\n",
3500                                q->value, q->subvendor, q->subdevice);
3501                         return q->value;
3502                 }
3503         }
3504
3505         /* Check VIA/ATI HD Audio Controller exist */
3506         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3507                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", pci_name(chip->pci));
3508                 return POS_FIX_VIACOMBO;
3509         }
3510         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3511                 snd_printd(SFX "%s: Using LPIB position fix\n", pci_name(chip->pci));
3512                 return POS_FIX_LPIB;
3513         }
3514         return POS_FIX_AUTO;
3515 }
3516
3517 /*
3518  * black-lists for probe_mask
3519  */
3520 static struct snd_pci_quirk probe_mask_list[] = {
3521         /* Thinkpad often breaks the controller communication when accessing
3522          * to the non-working (or non-existing) modem codec slot.
3523          */
3524         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3525         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3526         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3527         /* broken BIOS */
3528         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3529         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3530         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3531         /* forced codec slots */
3532         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3533         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3534         /* WinFast VP200 H (Teradici) user reported broken communication */
3535         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3536         {}
3537 };
3538
3539 #define AZX_FORCE_CODEC_MASK    0x100
3540
3541 static void check_probe_mask(struct azx *chip, int dev)
3542 {
3543         const struct snd_pci_quirk *q;
3544
3545         chip->codec_probe_mask = probe_mask[dev];
3546         if (chip->pci && (chip->codec_probe_mask == -1)) {
3547                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3548                 if (q) {
3549                         printk(KERN_INFO
3550                                "hda_intel: probe_mask set to 0x%x "
3551                                "for device %04x:%04x\n",
3552                                q->value, q->subvendor, q->subdevice);
3553                         chip->codec_probe_mask = q->value;
3554                 }
3555         }
3556
3557         /* check forced option */
3558         if (chip->codec_probe_mask != -1 &&
3559             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3560                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3561                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3562                        chip->codec_mask);
3563         }
3564 }
3565
3566 /*
3567  * white/black-list for enable_msi
3568  */
3569 static struct snd_pci_quirk msi_black_list[] = {
3570         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3571         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3572         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3573         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3574         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3575         {}
3576 };
3577
3578 static void check_msi(struct azx *chip)
3579 {
3580         const struct snd_pci_quirk *q;
3581
3582         /* Disable MSI if chip is not a pci device */
3583         if (!chip->pci) {
3584                 chip->msi = 0;
3585                 return;
3586         }
3587
3588         if (enable_msi >= 0) {
3589                 chip->msi = !!enable_msi;
3590                 return;
3591         }
3592         chip->msi = 1;  /* enable MSI as default */
3593         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3594         if (q) {
3595                 printk(KERN_INFO
3596                        "hda_intel: msi for device %04x:%04x set to %d\n",
3597                        q->subvendor, q->subdevice, q->value);
3598                 chip->msi = q->value;
3599                 return;
3600         }
3601
3602         /* NVidia chipsets seem to cause troubles with MSI */
3603         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3604                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3605                 chip->msi = 0;
3606         }
3607 }
3608
3609 /* check the snoop mode availability */
3610 static void azx_check_snoop_available(struct azx *chip)
3611 {
3612         bool snoop = chip->snoop;
3613
3614         switch (chip->driver_type) {
3615         case AZX_DRIVER_VIA:
3616                 /* force to non-snoop mode for a new VIA controller
3617                  * when BIOS is set
3618                  */
3619                 if (snoop) {
3620                         u8 val;
3621                         pci_read_config_byte(chip->pci, 0x42, &val);
3622                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3623                                 snoop = false;
3624                 }
3625                 break;
3626         case AZX_DRIVER_ATIHDMI_NS:
3627                 /* new ATI HDMI requires non-snoop */
3628                 snoop = false;
3629                 break;
3630         case AZX_DRIVER_CTHDA:
3631                 snoop = false;
3632                 break;
3633         }
3634
3635         if (snoop != chip->snoop) {
3636                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3637                            pci_name(chip->pci), snoop ? "snoop" : "non-snoop");
3638                 chip->snoop = snoop;
3639         }
3640 }
3641
3642 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3643 static const char *tegra_clk_names[] = {
3644         "hda",
3645         "hda2codec",
3646         "hda2hdmi",
3647 };
3648 static struct clk *tegra_clks[ARRAY_SIZE(tegra_clk_names)];
3649 #endif
3650
3651 /*
3652  * constructor
3653  */
3654 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3655                                 struct platform_device *pdev,
3656                                 int dev, unsigned int driver_caps,
3657                                 struct azx **rchip)
3658 {
3659         static struct snd_device_ops ops = {
3660                 .dev_free = azx_dev_free,
3661         };
3662         struct azx *chip;
3663         int err;
3664
3665         *rchip = NULL;
3666
3667         if (pci) {
3668                 err = pci_enable_device(pci);
3669                 if (err < 0)
3670                         return err;
3671         }
3672
3673         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3674         if (!chip) {
3675                 snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3676                 if (pci)
3677                         pci_disable_device(pci);
3678                 return -ENOMEM;
3679         }
3680
3681         spin_lock_init(&chip->reg_lock);
3682         mutex_init(&chip->open_mutex);
3683         chip->card = card;
3684         chip->pci = pci;
3685         chip->pdev = pdev;
3686         chip->dev = pci ? snd_dma_pci_data(pci) : &pdev->dev;
3687         chip->irq_id = pci ? pci->irq : platform_get_irq(pdev, 0);
3688         chip->irq = -1;
3689         chip->driver_caps = driver_caps;
3690         chip->driver_type = driver_caps & 0xff;
3691         check_msi(chip);
3692         chip->dev_index = dev;
3693         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3694         INIT_LIST_HEAD(&chip->pcm_list);
3695         INIT_LIST_HEAD(&chip->list);
3696         init_vga_switcheroo(chip);
3697         init_completion(&chip->probe_wait);
3698
3699         chip->position_fix[0] = chip->position_fix[1] =
3700                 check_position_fix(chip, position_fix[dev]);
3701         /* combo mode uses LPIB for playback */
3702         if (chip->position_fix[0] == POS_FIX_COMBO) {
3703                 chip->position_fix[0] = POS_FIX_LPIB;
3704                 chip->position_fix[1] = POS_FIX_AUTO;
3705         }
3706
3707         check_probe_mask(chip, dev);
3708
3709         chip->single_cmd = single_cmd;
3710         chip->snoop = hda_snoop;
3711         azx_check_snoop_available(chip);
3712
3713         if (bdl_pos_adj[dev] < 0) {
3714                 switch (chip->driver_type) {
3715                 case AZX_DRIVER_ICH:
3716                 case AZX_DRIVER_PCH:
3717                         bdl_pos_adj[dev] = 1;
3718                         break;
3719                 default:
3720                         bdl_pos_adj[dev] = 32;
3721                         break;
3722                 }
3723         }
3724
3725         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3726         if (err < 0) {
3727                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3728                    pci_name(chip->pci));
3729                 azx_free(chip);
3730                 return err;
3731         }
3732
3733         *rchip = chip;
3734         return 0;
3735 }
3736
3737 static int azx_first_init(struct azx *chip)
3738 {
3739         int dev = chip->dev_index;
3740         struct pci_dev *pci = chip->pci;
3741         struct snd_card *card = chip->card;
3742         int i, err = 0;
3743         unsigned short gcap;
3744
3745 #if BITS_PER_LONG != 64
3746         /* Fix up base address on ULI M5461 */
3747         if (chip->driver_type == AZX_DRIVER_ULI) {
3748                 u16 tmp3;
3749                 pci_read_config_word(pci, 0x40, &tmp3);
3750                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3751                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3752         }
3753 #endif
3754
3755         if (chip->pci) {
3756                 err = pci_request_regions(pci, "ICH HD audio");
3757                 if (err < 0)
3758                         return err;
3759                 chip->region_requested = 1;
3760
3761                 chip->addr = pci_resource_start(pci, 0);
3762                 chip->remap_addr = pci_ioremap_bar(pci, 0);
3763                 if (chip->remap_addr == NULL) {
3764                         snd_printk(KERN_ERR SFX "%s: ioremap error\n", pci_name(chip->pci));
3765                         return -ENXIO;
3766                 }
3767         }
3768
3769 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3770         if (chip->pdev) {
3771                 struct resource *res, *region;
3772
3773                 /* Do platform specific initialization */
3774                 switch (chip->driver_type) {
3775 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3776                 case AZX_DRIVER_NVIDIA_TEGRA:
3777                         chip->platform_clk_count = ARRAY_SIZE(tegra_clk_names);
3778                         for (i = 0; i < chip->platform_clk_count; i++) {
3779                                 tegra_clks[i] = clk_get(&pdev->dev,
3780                                                         tegra_clk_names[i]);
3781                                 if (IS_ERR_OR_NULL(tegra_clks[i])) {
3782                                         err = PTR_ERR(tegra_clks[i]);
3783                                         goto errout;
3784                                 }
3785                         }
3786                         chip->platform_clks = tegra_clks;
3787                         break;
3788 #endif
3789                 default:
3790                         break;
3791                 }
3792
3793                 azx_platform_enable_clocks(chip);
3794
3795                 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3796                 if (res == NULL) {
3797                         err = EINVAL;
3798                         goto errout;
3799                 }
3800
3801                 region = devm_request_mem_region(chip->dev, res->start,
3802                                                  resource_size(res),
3803                                                  pdev->name);
3804                 if (!region) {
3805                         snd_printk(KERN_ERR SFX "Mem region already claimed\n");
3806                         err = -EINVAL;
3807                         goto errout;
3808                 }
3809
3810                 chip->addr = res->start;
3811                 chip->remap_addr = devm_ioremap(chip->dev,
3812                                                 res->start,
3813                                                 resource_size(res));
3814                 if (chip->remap_addr == NULL) {
3815                         snd_printk(KERN_ERR SFX "ioremap error\n");
3816                         err = -ENXIO;
3817                         goto errout;
3818                 }
3819
3820 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3821                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
3822                         chip->remap_config_addr = chip->remap_addr;
3823                         chip->remap_addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3824                         chip->addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3825                 }
3826 #endif
3827
3828                 azx_init_platform(chip);
3829         }
3830 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3831
3832         if (azx_acquire_irq(chip, 0) < 0)
3833                 return -EBUSY;
3834
3835         if (chip->pci)
3836                 pci_set_master(pci);
3837
3838         synchronize_irq(chip->irq);
3839
3840         gcap = azx_readw(chip, GCAP);
3841         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", pci_name(chip->pci), gcap);
3842
3843         /* disable SB600 64bit support for safety */
3844         if (chip->pci && chip->pci->vendor == PCI_VENDOR_ID_ATI) {
3845                 struct pci_dev *p_smbus;
3846                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
3847                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
3848                                          NULL);
3849                 if (p_smbus) {
3850                         if (p_smbus->revision < 0x30)
3851                                 gcap &= ~ICH6_GCAP_64OK;
3852                         pci_dev_put(p_smbus);
3853                 }
3854         }
3855
3856         /* disable 64bit DMA address on some devices */
3857         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
3858                 snd_printd(SFX "%s: Disabling 64bit DMA\n", pci_name(chip->pci));
3859                 gcap &= ~ICH6_GCAP_64OK;
3860         }
3861
3862         /* disable buffer size rounding to 128-byte multiples if supported */
3863         if (align_buffer_size >= 0)
3864                 chip->align_buffer_size = !!align_buffer_size;
3865         else {
3866                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
3867                         chip->align_buffer_size = 0;
3868                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
3869                         chip->align_buffer_size = 1;
3870                 else
3871                         chip->align_buffer_size = 1;
3872         }
3873
3874         if (chip->pci) {
3875                 /* allow 64bit DMA address if supported by H/W */
3876                 if ((gcap & ICH6_GCAP_64OK) &&
3877                     !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
3878                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
3879                 else {
3880                         pci_set_dma_mask(pci, DMA_BIT_MASK(32));
3881                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
3882                 }
3883         }
3884
3885         /* read number of streams from GCAP register instead of using
3886          * hardcoded value
3887          */
3888         chip->capture_streams = (gcap >> 8) & 0x0f;
3889         chip->playback_streams = (gcap >> 12) & 0x0f;
3890         if (!chip->playback_streams && !chip->capture_streams) {
3891                 /* gcap didn't give any info, switching to old method */
3892
3893                 switch (chip->driver_type) {
3894                 case AZX_DRIVER_ULI:
3895                         chip->playback_streams = ULI_NUM_PLAYBACK;
3896                         chip->capture_streams = ULI_NUM_CAPTURE;
3897                         break;
3898                 case AZX_DRIVER_ATIHDMI:
3899                 case AZX_DRIVER_ATIHDMI_NS:
3900                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
3901                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
3902                         break;
3903                 case AZX_DRIVER_GENERIC:
3904                 default:
3905                         chip->playback_streams = ICH6_NUM_PLAYBACK;
3906                         chip->capture_streams = ICH6_NUM_CAPTURE;
3907                         break;
3908                 }
3909         }
3910         chip->capture_index_offset = 0;
3911         chip->playback_index_offset = chip->capture_streams;
3912         chip->num_streams = chip->playback_streams + chip->capture_streams;
3913         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
3914                                 GFP_KERNEL);
3915         if (!chip->azx_dev) {
3916                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", pci_name(chip->pci));
3917                 return -ENOMEM;
3918         }
3919
3920         for (i = 0; i < chip->num_streams; i++) {
3921                 dsp_lock_init(&chip->azx_dev[i]);
3922                 /* allocate memory for the BDL for each stream */
3923                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3924                                           chip->dev,
3925                                           BDL_SIZE, &chip->azx_dev[i].bdl);
3926                 if (err < 0) {
3927                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", pci_name(chip->pci));
3928                         return -ENOMEM;
3929                 }
3930                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
3931         }
3932         /* allocate memory for the position buffer */
3933         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
3934                                   chip->dev,
3935                                   chip->num_streams * 8, &chip->posbuf);
3936         if (err < 0) {
3937                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", pci_name(chip->pci));
3938                 return -ENOMEM;
3939         }
3940         mark_pages_wc(chip, &chip->posbuf, true);
3941         /* allocate CORB/RIRB */
3942         err = azx_alloc_cmd_io(chip);
3943         if (err < 0)
3944                 return err;
3945
3946         /* initialize streams */
3947         azx_init_stream(chip);
3948
3949         /* initialize chip */
3950         if (chip->pci)
3951                 azx_init_pci(chip);
3952         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
3953
3954         /* codec detection */
3955         if (!chip->codec_mask) {
3956                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", pci_name(chip->pci));
3957                 return -ENODEV;
3958         }
3959
3960         strcpy(card->driver, "HDA-Intel");
3961         strlcpy(card->shortname, driver_short_names[chip->driver_type],
3962                 sizeof(card->shortname));
3963         snprintf(card->longname, sizeof(card->longname),
3964                  "%s at 0x%lx irq %i",
3965                  card->shortname, chip->addr, chip->irq);
3966
3967         return 0;
3968 }
3969
3970 static void power_down_all_codecs(struct azx *chip)
3971 {
3972 #ifdef CONFIG_PM
3973         /* The codecs were powered up in snd_hda_codec_new().
3974          * Now all initialization done, so turn them down if possible
3975          */
3976         struct hda_codec *codec;
3977         list_for_each_entry(codec, &chip->bus->codec_list, list) {
3978                 snd_hda_power_down(codec);
3979         }
3980 #endif
3981 }
3982
3983 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3984 /* callback from request_firmware_nowait() */
3985 static void azx_firmware_cb(const struct firmware *fw, void *context)
3986 {
3987         struct snd_card *card = context;
3988         struct azx *chip = card->private_data;
3989         struct pci_dev *pci = chip->pci;
3990
3991         if (!fw) {
3992                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
3993                            pci_name(chip->pci));
3994                 goto error;
3995         }
3996
3997         chip->fw = fw;
3998         if (!chip->disabled) {
3999                 /* continue probing */
4000                 if (azx_probe_continue(chip))
4001                         goto error;
4002         }
4003         return; /* OK */
4004
4005  error:
4006         snd_card_free(card);
4007         pci_set_drvdata(pci, NULL);
4008 }
4009 #endif
4010
4011 static int azx_probe(struct pci_dev *pci,
4012                                struct platform_device *pdev,
4013                                int driver_data)
4014 {
4015         static int dev;
4016         struct snd_card *card;
4017         struct azx *chip;
4018         bool probe_now;
4019         struct device *azx_dev = pci ? &pci->dev : &pdev->dev;
4020         int err;
4021
4022         if (dev >= SNDRV_CARDS)
4023                 return -ENODEV;
4024         if (!enable[dev]) {
4025                 dev++;
4026                 return -ENOENT;
4027         }
4028
4029         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
4030         if (err < 0) {
4031                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
4032                 return err;
4033         }
4034
4035         snd_card_set_dev(card, azx_dev);
4036
4037         err = azx_create(card, pci, pdev, dev, driver_data, &chip);
4038         if (err < 0)
4039                 goto out_free;
4040         card->private_data = chip;
4041
4042         if (pci)
4043                 pci_set_drvdata(pci, card);
4044         else
4045                 dev_set_drvdata(&pdev->dev, card);
4046
4047         err = register_vga_switcheroo(chip);
4048         if (err < 0) {
4049                 snd_printk(KERN_ERR SFX
4050                            "%s: Error registering VGA-switcheroo client\n", pci_name(pci));
4051                 goto out_free;
4052         }
4053
4054         if (check_hdmi_disabled(pci)) {
4055                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
4056                            pci_name(pci));
4057                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", pci_name(pci));
4058                 chip->disabled = true;
4059         }
4060
4061         probe_now = !chip->disabled;
4062         if (probe_now) {
4063                 err = azx_first_init(chip);
4064                 if (err < 0)
4065                         goto out_free;
4066         }
4067
4068 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4069         if (patch[dev] && *patch[dev]) {
4070                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
4071                            pci_name(pci), patch[dev]);
4072                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
4073                                               &pci->dev, GFP_KERNEL, card,
4074                                               azx_firmware_cb);
4075                 if (err < 0)
4076                         goto out_free;
4077                 probe_now = false; /* continued in azx_firmware_cb() */
4078         }
4079 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
4080
4081         if (probe_now) {
4082                 err = azx_probe_continue(chip);
4083                 if (err < 0)
4084                         goto out_free;
4085         }
4086
4087         if (pci_dev_run_wake(pci))
4088                 pm_runtime_put_noidle(&pci->dev);
4089
4090         dev++;
4091         complete_all(&chip->probe_wait);
4092         return 0;
4093
4094 out_free:
4095         snd_card_free(card);
4096         pci_set_drvdata(pci, NULL);
4097         return err;
4098 }
4099
4100 static int azx_probe_continue(struct azx *chip)
4101 {
4102         int dev = chip->dev_index;
4103         int err;
4104
4105 #ifdef CONFIG_SND_HDA_INPUT_BEEP
4106         chip->beep_mode = beep_mode[dev];
4107 #endif
4108
4109         /* create codec instances */
4110         err = azx_codec_create(chip, model[dev]);
4111         if (err < 0)
4112                 goto out_free;
4113 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4114         if (chip->fw) {
4115                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
4116                                          chip->fw->data);
4117                 if (err < 0)
4118                         goto out_free;
4119 #ifndef CONFIG_PM
4120                 release_firmware(chip->fw); /* no longer needed */
4121                 chip->fw = NULL;
4122 #endif
4123         }
4124 #endif
4125         if ((probe_only[dev] & 1) == 0) {
4126                 err = azx_codec_configure(chip);
4127                 if (err < 0)
4128                         goto out_free;
4129         }
4130
4131         /* create PCM streams */
4132         err = snd_hda_build_pcms(chip->bus);
4133         if (err < 0)
4134                 goto out_free;
4135
4136         /* create mixer controls */
4137         err = azx_mixer_create(chip);
4138         if (err < 0)
4139                 goto out_free;
4140
4141         err = snd_card_register(chip->card);
4142         if (err < 0)
4143                 goto out_free;
4144
4145         chip->running = 1;
4146         power_down_all_codecs(chip);
4147         azx_notifier_register(chip);
4148         azx_add_card_list(chip);
4149
4150         return 0;
4151
4152 out_free:
4153         chip->init_failed = 1;
4154         return err;
4155 }
4156
4157 static int azx_probe_pci(struct pci_dev *pci,
4158                                    const struct pci_device_id *pci_id)
4159 {
4160         return azx_probe(pci, NULL, pci_id->driver_data);
4161 }
4162
4163 static void azx_remove_pci(struct pci_dev *pci)
4164 {
4165         struct snd_card *card = pci_get_drvdata(pci);
4166
4167         if (pci_dev_run_wake(pci))
4168                 pm_runtime_get_noresume(&pci->dev);
4169
4170         if (card)
4171                 snd_card_free(card);
4172         pci_set_drvdata(pci, NULL);
4173 }
4174
4175 /* PCI IDs */
4176 static DEFINE_PCI_DEVICE_TABLE(azx_pci_ids) = {
4177         /* CPT */
4178         { PCI_DEVICE(0x8086, 0x1c20),
4179           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4180         /* PBG */
4181         { PCI_DEVICE(0x8086, 0x1d20),
4182           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4183         /* Panther Point */
4184         { PCI_DEVICE(0x8086, 0x1e20),
4185           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4186         /* Lynx Point */
4187         { PCI_DEVICE(0x8086, 0x8c20),
4188           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4189         /* Wellsburg */
4190         { PCI_DEVICE(0x8086, 0x8d20),
4191           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4192         { PCI_DEVICE(0x8086, 0x8d21),
4193           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4194         /* Lynx Point-LP */
4195         { PCI_DEVICE(0x8086, 0x9c20),
4196           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4197         /* Lynx Point-LP */
4198         { PCI_DEVICE(0x8086, 0x9c21),
4199           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4200         /* Haswell */
4201         { PCI_DEVICE(0x8086, 0x0a0c),
4202           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4203         { PCI_DEVICE(0x8086, 0x0c0c),
4204           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4205         { PCI_DEVICE(0x8086, 0x0d0c),
4206           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4207         /* 5 Series/3400 */
4208         { PCI_DEVICE(0x8086, 0x3b56),
4209           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4210         /* Poulsbo */
4211         { PCI_DEVICE(0x8086, 0x811b),
4212           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4213         /* Oaktrail */
4214         { PCI_DEVICE(0x8086, 0x080a),
4215           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4216         /* ICH */
4217         { PCI_DEVICE(0x8086, 0x2668),
4218           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4219           AZX_DCAPS_BUFSIZE },  /* ICH6 */
4220         { PCI_DEVICE(0x8086, 0x27d8),
4221           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4222           AZX_DCAPS_BUFSIZE },  /* ICH7 */
4223         { PCI_DEVICE(0x8086, 0x269a),
4224           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4225           AZX_DCAPS_BUFSIZE },  /* ESB2 */
4226         { PCI_DEVICE(0x8086, 0x284b),
4227           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4228           AZX_DCAPS_BUFSIZE },  /* ICH8 */
4229         { PCI_DEVICE(0x8086, 0x293e),
4230           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4231           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4232         { PCI_DEVICE(0x8086, 0x293f),
4233           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4234           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4235         { PCI_DEVICE(0x8086, 0x3a3e),
4236           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4237           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4238         { PCI_DEVICE(0x8086, 0x3a6e),
4239           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4240           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4241         /* Generic Intel */
4242         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4243           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4244           .class_mask = 0xffffff,
4245           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4246         /* ATI SB 450/600/700/800/900 */
4247         { PCI_DEVICE(0x1002, 0x437b),
4248           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4249         { PCI_DEVICE(0x1002, 0x4383),
4250           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4251         /* AMD Hudson */
4252         { PCI_DEVICE(0x1022, 0x780d),
4253           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4254         /* ATI HDMI */
4255         { PCI_DEVICE(0x1002, 0x793b),
4256           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4257         { PCI_DEVICE(0x1002, 0x7919),
4258           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4259         { PCI_DEVICE(0x1002, 0x960f),
4260           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4261         { PCI_DEVICE(0x1002, 0x970f),
4262           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4263         { PCI_DEVICE(0x1002, 0xaa00),
4264           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4265         { PCI_DEVICE(0x1002, 0xaa08),
4266           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4267         { PCI_DEVICE(0x1002, 0xaa10),
4268           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4269         { PCI_DEVICE(0x1002, 0xaa18),
4270           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4271         { PCI_DEVICE(0x1002, 0xaa20),
4272           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4273         { PCI_DEVICE(0x1002, 0xaa28),
4274           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4275         { PCI_DEVICE(0x1002, 0xaa30),
4276           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4277         { PCI_DEVICE(0x1002, 0xaa38),
4278           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4279         { PCI_DEVICE(0x1002, 0xaa40),
4280           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4281         { PCI_DEVICE(0x1002, 0xaa48),
4282           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4283         { PCI_DEVICE(0x1002, 0x9902),
4284           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4285         { PCI_DEVICE(0x1002, 0xaaa0),
4286           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4287         { PCI_DEVICE(0x1002, 0xaaa8),
4288           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4289         { PCI_DEVICE(0x1002, 0xaab0),
4290           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4291         /* VIA VT8251/VT8237A */
4292         { PCI_DEVICE(0x1106, 0x3288),
4293           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4294         /* VIA GFX VT7122/VX900 */
4295         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4296         /* VIA GFX VT6122/VX11 */
4297         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4298         /* SIS966 */
4299         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4300         /* ULI M5461 */
4301         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4302         /* NVIDIA MCP */
4303         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4304           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4305           .class_mask = 0xffffff,
4306           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4307         /* Teradici */
4308         { PCI_DEVICE(0x6549, 0x1200),
4309           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4310         { PCI_DEVICE(0x6549, 0x2200),
4311           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4312         /* Creative X-Fi (CA0110-IBG) */
4313         /* CTHDA chips */
4314         { PCI_DEVICE(0x1102, 0x0010),
4315           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4316         { PCI_DEVICE(0x1102, 0x0012),
4317           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4318 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4319         /* the following entry conflicts with snd-ctxfi driver,
4320          * as ctxfi driver mutates from HD-audio to native mode with
4321          * a special command sequence.
4322          */
4323         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4324           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4325           .class_mask = 0xffffff,
4326           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4327           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4328 #else
4329         /* this entry seems still valid -- i.e. without emu20kx chip */
4330         { PCI_DEVICE(0x1102, 0x0009),
4331           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4332           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4333 #endif
4334         /* Vortex86MX */
4335         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4336         /* VMware HDAudio */
4337         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4338         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4339         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4340           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4341           .class_mask = 0xffffff,
4342           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4343         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4344           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4345           .class_mask = 0xffffff,
4346           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4347         { 0, }
4348 };
4349 MODULE_DEVICE_TABLE(pci, azx_pci_ids);
4350
4351 /* pci_driver definition */
4352 static struct pci_driver azx_driver = {
4353         .name = KBUILD_MODNAME,
4354         .id_table = azx_ids,
4355         .probe = azx_probe,
4356         .remove = azx_remove,
4357         .driver = {
4358                 .pm = AZX_PM_OPS,
4359         },
4360 };
4361
4362 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4363 static int azx_probe_platform(struct platform_device *pdev)
4364 {
4365         const struct platform_device_id *pdev_id = platform_get_device_id(pdev);
4366
4367         return azx_probe(NULL, pdev, pdev_id->driver_data);
4368 }
4369
4370 static int azx_remove_platform(struct platform_device *pdev)
4371 {
4372         return snd_card_free(dev_get_drvdata(&pdev->dev));
4373 }
4374
4375 static const struct platform_device_id azx_platform_ids[] = {
4376 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
4377         { "tegra30-hda",
4378           .driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_RIRB_DELAY },
4379 #endif
4380         { },
4381 };
4382 MODULE_DEVICE_TABLE(platform, azx_platform_ids);
4383
4384 /* platform_driver definition */
4385 static struct platform_driver hda_platform_driver = {
4386         .driver = {
4387                 .name = "hda-platform"
4388                 .pm = AZX_PM_OPS,
4389         },
4390         .probe = azx_probe_platform,
4391         .remove = azx_remove_platform,
4392         .id_table = azx_platform_ids,
4393 };
4394 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
4395
4396 module_pci_driver(azx_driver);
4397 module_platform_driver(hda_platform_driver);