alsa: hda: Read pwrgate partition-id from DT
[linux-3.10.git] / sound / pci / hda / hda_intel.c
1 /*
2  *
3  *  hda_intel.c - Implementation of primary alsa driver code base
4  *                for Intel HD Audio.
5  *
6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
7  *
8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9  *                     PeiSen Hou <pshou@realtek.com.tw>
10  *
11  *   Copyright (C) 2013-2015 NVIDIA Corporation. All rights reserved.
12  *
13  *  This program is free software; you can redistribute it and/or modify it
14  *  under the terms of the GNU General Public License as published by the Free
15  *  Software Foundation; either version 2 of the License, or (at your option)
16  *  any later version.
17  *
18  *  This program is distributed in the hope that it will be useful, but WITHOUT
19  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
21  *  more details.
22  *
23  *  You should have received a copy of the GNU General Public License along with
24  *  this program; if not, write to the Free Software Foundation, Inc., 59
25  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
26  *
27  *  CONTACTS:
28  *
29  *  Matt Jared          matt.jared@intel.com
30  *  Andy Kopp           andy.kopp@intel.com
31  *  Dan Kogan           dan.d.kogan@intel.com
32  *
33  *  CHANGES:
34  *
35  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
36  *
37  */
38
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include <linux/kernel.h>
42 #include <linux/module.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/moduleparam.h>
45 #include <linux/init.h>
46 #include <linux/slab.h>
47 #include <linux/pci.h>
48 #include <linux/mutex.h>
49 #include <linux/reboot.h>
50 #include <linux/io.h>
51 #include <linux/pm_runtime.h>
52 #include <linux/clocksource.h>
53 #include <linux/time.h>
54 #include <linux/completion.h>
55 #include <linux/clk.h>
56 #include <linux/of_device.h>
57 #include <linux/dma-mapping.h>
58
59 #ifdef CONFIG_X86
60 /* for snoop control */
61 #include <asm/pgtable.h>
62 #include <asm/cacheflush.h>
63 #endif
64 #include <sound/core.h>
65 #include <sound/initval.h>
66 #include <linux/vgaarb.h>
67 #include <linux/vga_switcheroo.h>
68 #include <linux/firmware.h>
69 #include "hda_codec.h"
70 #include "hda_local.h"
71
72 #ifdef CONFIG_SND_HDA_VPR
73 #include <linux/nvmap.h>
74 #endif
75 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
76 #include <linux/tegra-powergate.h>
77 #include <linux/tegra_pm_domains.h>
78 #endif
79
80 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
81 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
82 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
83 static char *model[SNDRV_CARDS];
84 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
85 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
86 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
87 static int probe_only[SNDRV_CARDS];
88 static int jackpoll_ms[SNDRV_CARDS];
89 static bool single_cmd;
90 static int enable_msi = -1;
91 #ifdef CONFIG_SND_HDA_PATCH_LOADER
92 static char *patch[SNDRV_CARDS];
93 #endif
94 #ifdef CONFIG_SND_HDA_INPUT_BEEP
95 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
96                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
97 #endif
98
99 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
100 static struct of_device_id tegra_disb_pd[] = {
101         { .compatible = "nvidia, tegra210-disb-pd", },
102         {},
103 };
104 #endif
105
106 module_param_array(index, int, NULL, 0444);
107 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
108 module_param_array(id, charp, NULL, 0444);
109 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
110 module_param_array(enable, bool, NULL, 0444);
111 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
112 module_param_array(model, charp, NULL, 0444);
113 MODULE_PARM_DESC(model, "Use the given board model.");
114 module_param_array(position_fix, int, NULL, 0444);
115 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
116                  "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
117 module_param_array(bdl_pos_adj, int, NULL, 0644);
118 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
119 module_param_array(probe_mask, int, NULL, 0444);
120 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
121 module_param_array(probe_only, int, NULL, 0444);
122 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
123 module_param_array(jackpoll_ms, int, NULL, 0444);
124 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
125 module_param(single_cmd, bool, 0444);
126 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
127                  "(for debugging only).");
128 module_param(enable_msi, bint, 0444);
129 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
130 #ifdef CONFIG_SND_HDA_PATCH_LOADER
131 module_param_array(patch, charp, NULL, 0444);
132 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
133 #endif
134 #ifdef CONFIG_SND_HDA_INPUT_BEEP
135 module_param_array(beep_mode, bool, NULL, 0444);
136 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
137                             "(0=off, 1=on) (default=1).");
138 #endif
139
140 #ifdef CONFIG_PM
141 static int param_set_xint(const char *val, const struct kernel_param *kp);
142 static struct kernel_param_ops param_ops_xint = {
143         .set = param_set_xint,
144         .get = param_get_int,
145 };
146 #define param_check_xint param_check_int
147
148 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
149 module_param(power_save, xint, 0644);
150 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
151                  "(in second, 0 = disable).");
152
153 /* reset the HD-audio controller in power save mode.
154  * this may give more power-saving, but will take longer time to
155  * wake up.
156  */
157 static bool power_save_controller = 1;
158 module_param(power_save_controller, bool, 0644);
159 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
160 #endif /* CONFIG_PM */
161
162 static int align_buffer_size = -1;
163 module_param(align_buffer_size, bint, 0644);
164 MODULE_PARM_DESC(align_buffer_size,
165                 "Force buffer and period sizes to be multiple of 128 bytes.");
166
167 #ifdef CONFIG_X86
168 static bool hda_snoop = true;
169 module_param_named(snoop, hda_snoop, bool, 0444);
170 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
171 #define azx_snoop(chip)         (chip)->snoop
172 #else
173 #define hda_snoop               true
174 #define azx_snoop(chip)         true
175 #endif
176
177
178 MODULE_LICENSE("GPL");
179 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
180                          "{Intel, ICH6M},"
181                          "{Intel, ICH7},"
182                          "{Intel, ESB2},"
183                          "{Intel, ICH8},"
184                          "{Intel, ICH9},"
185                          "{Intel, ICH10},"
186                          "{Intel, PCH},"
187                          "{Intel, CPT},"
188                          "{Intel, PPT},"
189                          "{Intel, LPT},"
190                          "{Intel, LPT_LP},"
191                          "{Intel, HPT},"
192                          "{Intel, PBG},"
193                          "{Intel, SCH},"
194                          "{ATI, SB450},"
195                          "{ATI, SB600},"
196                          "{ATI, RS600},"
197                          "{ATI, RS690},"
198                          "{ATI, RS780},"
199                          "{ATI, R600},"
200                          "{ATI, RV630},"
201                          "{ATI, RV610},"
202                          "{ATI, RV670},"
203                          "{ATI, RV635},"
204                          "{ATI, RV620},"
205                          "{ATI, RV770},"
206                          "{VIA, VT8251},"
207                          "{VIA, VT8237A},"
208                          "{SiS, SIS966},"
209                          "{ULI, M5461}}");
210 MODULE_DESCRIPTION("Intel HDA driver");
211
212 #ifdef CONFIG_SND_VERBOSE_PRINTK
213 #define SFX     /* nop */
214 #else
215 #define SFX     "hda-intel "
216 #endif
217
218 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO) && \
219         !defined(CONFIG_SND_HDA_PLATFORM_DRIVER)
220 #ifdef CONFIG_SND_HDA_CODEC_HDMI
221 #define SUPPORT_VGA_SWITCHEROO
222 #endif
223 #endif
224
225
226 /*
227  * registers
228  */
229 #define ICH6_REG_GCAP                   0x00
230 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
231 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
232 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
233 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
234 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
235 #define ICH6_REG_VMIN                   0x02
236 #define ICH6_REG_VMAJ                   0x03
237 #define ICH6_REG_OUTPAY                 0x04
238 #define ICH6_REG_INPAY                  0x06
239 #define ICH6_REG_GCTL                   0x08
240 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
241 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
242 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
243 #define ICH6_REG_WAKEEN                 0x0c
244 #define ICH6_REG_STATESTS               0x0e
245 #define ICH6_REG_GSTS                   0x10
246 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
247 #define ICH6_REG_INTCTL                 0x20
248 #define ICH6_REG_INTSTS                 0x24
249 #define ICH6_REG_WALLCLK                0x30    /* 24Mhz source */
250 #define ICH6_REG_OLD_SSYNC              0x34    /* SSYNC for old ICH */
251 #define ICH6_REG_SSYNC                  0x38
252 #define ICH6_REG_CORBLBASE              0x40
253 #define ICH6_REG_CORBUBASE              0x44
254 #define ICH6_REG_CORBWP                 0x48
255 #define ICH6_REG_CORBRP                 0x4a
256 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
257 #define ICH6_REG_CORBCTL                0x4c
258 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
259 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
260 #define ICH6_REG_CORBSTS                0x4d
261 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
262 #define ICH6_REG_CORBSIZE               0x4e
263
264 #define ICH6_REG_RIRBLBASE              0x50
265 #define ICH6_REG_RIRBUBASE              0x54
266 #define ICH6_REG_RIRBWP                 0x58
267 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
268 #define ICH6_REG_RINTCNT                0x5a
269 #define ICH6_REG_RIRBCTL                0x5c
270 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
271 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
272 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
273 #define ICH6_REG_RIRBSTS                0x5d
274 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
275 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
276 #define ICH6_REG_RIRBSIZE               0x5e
277
278 #define ICH6_REG_IC                     0x60
279 #define ICH6_REG_IR                     0x64
280 #define ICH6_REG_IRS                    0x68
281 #define   ICH6_IRS_VALID        (1<<1)
282 #define   ICH6_IRS_BUSY         (1<<0)
283
284 #define ICH6_REG_DPLBASE                0x70
285 #define ICH6_REG_DPUBASE                0x74
286 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
287
288 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
289 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
290
291 /* stream register offsets from stream base */
292 #define ICH6_REG_SD_CTL                 0x00
293 #define ICH6_REG_SD_STS                 0x03
294 #define ICH6_REG_SD_LPIB                0x04
295 #define ICH6_REG_SD_CBL                 0x08
296 #define ICH6_REG_SD_LVI                 0x0c
297 #define ICH6_REG_SD_FIFOW               0x0e
298 #define ICH6_REG_SD_FIFOSIZE            0x10
299 #define ICH6_REG_SD_FORMAT              0x12
300 #define ICH6_REG_SD_BDLPL               0x18
301 #define ICH6_REG_SD_BDLPU               0x1c
302
303 /* PCI space */
304 #define ICH6_PCIREG_TCSEL       0x44
305
306 /*
307  * other constants
308  */
309
310 /* max number of SDs */
311 /* ICH, ATI and VIA have 4 playback and 4 capture */
312 #define ICH6_NUM_CAPTURE        4
313 #define ICH6_NUM_PLAYBACK       4
314
315 /* ULI has 6 playback and 5 capture */
316 #define ULI_NUM_CAPTURE         5
317 #define ULI_NUM_PLAYBACK        6
318
319 /* ATI HDMI has 1 playback and 0 capture */
320 #define ATIHDMI_NUM_CAPTURE     0
321 #define ATIHDMI_NUM_PLAYBACK    1
322
323 /* TERA has 4 playback and 3 capture */
324 #define TERA_NUM_CAPTURE        3
325 #define TERA_NUM_PLAYBACK       4
326
327 /* this number is statically defined for simplicity */
328 #define MAX_AZX_DEV             16
329
330 /* max number of fragments - we may use more if allocating more pages for BDL */
331 #define BDL_SIZE                4096
332 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
333 #define AZX_MAX_FRAG            32
334 /* max buffer size - no h/w limit, you can increase as you like */
335 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
336
337 /* RIRB int mask: overrun[2], response[0] */
338 #define RIRB_INT_RESPONSE       0x01
339 #define RIRB_INT_OVERRUN        0x04
340 #define RIRB_INT_MASK           0x05
341
342 /* STATESTS int mask: S3,SD2,SD1,SD0 */
343 #define AZX_MAX_CODECS          8
344 #define AZX_DEFAULT_CODECS      4
345 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
346
347 /* SD_CTL bits */
348 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
349 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
350 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
351 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
352 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
353 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
354 #define SD_CTL_STREAM_TAG_SHIFT 20
355
356 /* SD_CTL and SD_STS */
357 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
358 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
359 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
360 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
361                                  SD_INT_COMPLETE)
362
363 /* SD_STS */
364 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
365
366 /* INTCTL and INTSTS */
367 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
368 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
369 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
370
371 /* below are so far hardcoded - should read registers in future */
372 #define ICH6_MAX_CORB_ENTRIES   256
373 #define ICH6_MAX_RIRB_ENTRIES   256
374
375 /* position fix mode */
376 enum {
377         POS_FIX_AUTO,
378         POS_FIX_LPIB,
379         POS_FIX_POSBUF,
380         POS_FIX_VIACOMBO,
381         POS_FIX_COMBO,
382 };
383
384 /* Defines for ATI HD Audio support in SB450 south bridge */
385 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
386 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
387
388 /* Defines for Nvidia HDA support */
389 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
390 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
391 #define NVIDIA_HDA_ISTRM_COH          0x4d
392 #define NVIDIA_HDA_OSTRM_COH          0x4c
393 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
394
395 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
396 /* Defines for Nvidia Tegra HDA support */
397 #define NVIDIA_TEGRA_HDA_BAR0_OFFSET           0x8000
398
399 #define NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET        0x1004
400 #define NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET       0x1010
401
402 #define NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE       (1 << 0)
403 #define NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE      (1 << 1)
404 #define NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER     (1 << 2)
405 #define NVIDIA_TEGRA_HDA_ENABLE_SERR           (1 << 8)
406 #define NVIDIA_TEGRA_HDA_DISABLE_INTR          (1 << 10)
407 #define NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM     0xFFFFFFFF
408 #define NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM    (1 << 14)
409
410 /* IPFS */
411 #define NVIDIA_TEGRA_HDA_IPFS_CONFIG           0x180
412 #define NVIDIA_TEGRA_HDA_IPFS_EN_FPCI          0x1
413
414 #define NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0        0x80
415 #define NVIDIA_TEGRA_HDA_FPCI_BAR0_START       0x40
416
417 #define NVIDIA_TEGRA_HDA_IPFS_INTR_MASK        0x188
418 #define NVIDIA_TEGRA_HDA_IPFS_EN_INTR          (1 << 16)
419 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
420
421 /* Defines for Intel SCH HDA snoop control */
422 #define INTEL_SCH_HDA_DEVC      0x78
423 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
424
425 /* Define IN stream 0 FIFO size offset in VIA controller */
426 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
427 /* Define VIA HD Audio Device ID*/
428 #define VIA_HDAC_DEVICE_ID              0x3288
429
430 /* HD Audio class code */
431 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
432
433 /*
434  */
435
436 struct azx_dev {
437         struct snd_dma_buffer bdl; /* BDL buffer */
438         u32 *posbuf;            /* position buffer pointer */
439
440         unsigned int bufsize;   /* size of the play buffer in bytes */
441         unsigned int period_bytes; /* size of the period in bytes */
442         unsigned int frags;     /* number for period in the play buffer */
443         unsigned int fifo_size; /* FIFO size */
444         unsigned long start_wallclk;    /* start + minimum wallclk */
445         unsigned long period_wallclk;   /* wallclk for period */
446
447         void __iomem *sd_addr;  /* stream descriptor pointer */
448
449         u32 sd_int_sta_mask;    /* stream int status mask */
450
451         /* pcm support */
452         struct snd_pcm_substream *substream;    /* assigned substream,
453                                                  * set in PCM open
454                                                  */
455         unsigned int format_val;        /* format value to be set in the
456                                          * controller and the codec
457                                          */
458         unsigned char stream_tag;       /* assigned stream */
459         unsigned char index;            /* stream index */
460         int assigned_key;               /* last device# key assigned to */
461
462         unsigned int opened :1;
463         unsigned int running :1;
464         unsigned int irq_pending :1;
465         unsigned int prepared:1;
466         unsigned int locked:1;
467         /*
468          * For VIA:
469          *  A flag to ensure DMA position is 0
470          *  when link position is not greater than FIFO size
471          */
472         unsigned int insufficient :1;
473         unsigned int wc_marked:1;
474         unsigned int no_period_wakeup:1;
475
476         struct timecounter  azx_tc;
477         struct cyclecounter azx_cc;
478
479 #ifdef CONFIG_SND_HDA_DSP_LOADER
480         struct mutex dsp_mutex;
481 #endif
482 };
483
484 /* DSP lock helpers */
485 #ifdef CONFIG_SND_HDA_DSP_LOADER
486 #define dsp_lock_init(dev)      mutex_init(&(dev)->dsp_mutex)
487 #define dsp_lock(dev)           mutex_lock(&(dev)->dsp_mutex)
488 #define dsp_unlock(dev)         mutex_unlock(&(dev)->dsp_mutex)
489 #define dsp_is_locked(dev)      ((dev)->locked)
490 #else
491 #define dsp_lock_init(dev)      do {} while (0)
492 #define dsp_lock(dev)           do {} while (0)
493 #define dsp_unlock(dev)         do {} while (0)
494 #define dsp_is_locked(dev)      0
495 #endif
496
497 /* CORB/RIRB */
498 struct azx_rb {
499         u32 *buf;               /* CORB/RIRB buffer
500                                  * Each CORB entry is 4byte, RIRB is 8byte
501                                  */
502         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
503         /* for RIRB */
504         unsigned short rp, wp;  /* read/write pointers */
505         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
506         u32 res[AZX_MAX_CODECS];        /* last read value */
507 };
508
509 struct azx_pcm {
510         struct azx *chip;
511         struct snd_pcm *pcm;
512         struct hda_codec *codec;
513         struct hda_pcm_stream *hinfo[2];
514         struct list_head list;
515 };
516
517 struct azx {
518         struct snd_card *card;
519         struct pci_dev *pci;
520         struct platform_device *pdev;
521         struct device *dev;
522         int irq_id;
523         int dev_index;
524
525         /* chip type specific */
526         int driver_type;
527         unsigned int driver_caps;
528         int playback_streams;
529         int playback_index_offset;
530         int capture_streams;
531         int capture_index_offset;
532         int num_streams;
533
534         /* pci resources */
535         unsigned long addr;
536         void __iomem *remap_addr;
537 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
538         void __iomem *remap_config_addr;
539 #endif
540         int irq;
541
542 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
543         /* platform driver clocks */
544         struct clk **platform_clks;
545         int platform_clk_count;
546         int platform_clk_enable;
547 #endif
548
549 #ifdef CONFIG_SND_HDA_VPR
550         struct dma_buf_attachment *attach;
551         struct sg_table *sgt;
552         dma_addr_t iova_addr;
553         struct dma_attrs dmaattrs;
554         unsigned int buf_size;
555 #endif
556
557         /* locks */
558         spinlock_t reg_lock;
559         struct mutex open_mutex;
560         struct completion probe_wait;
561
562         /* streams (x num_streams) */
563         struct azx_dev *azx_dev;
564
565         /* PCM */
566         struct list_head pcm_list; /* azx_pcm list */
567
568         /* HD codec */
569         unsigned short codec_mask;
570         int  codec_probe_mask; /* copied from probe_mask option */
571         struct hda_bus *bus;
572         unsigned int beep_mode;
573
574         /* CORB/RIRB */
575         struct azx_rb corb;
576         struct azx_rb rirb;
577
578         /* CORB/RIRB and position buffers */
579         struct snd_dma_buffer rb;
580         struct snd_dma_buffer posbuf;
581
582 #ifdef CONFIG_SND_HDA_PATCH_LOADER
583         const struct firmware *fw;
584 #endif
585
586         /* flags */
587         int position_fix[2]; /* for both playback/capture streams */
588         int poll_count;
589         unsigned int running :1;
590         unsigned int initialized :1;
591         unsigned int single_cmd :1;
592         unsigned int polling_mode :1;
593         unsigned int msi :1;
594         unsigned int irq_pending_warned :1;
595         unsigned int probing :1; /* codec probing phase */
596         unsigned int snoop:1;
597         unsigned int align_buffer_size:1;
598         unsigned int region_requested:1;
599
600         /* VGA-switcheroo setup */
601         unsigned int use_vga_switcheroo:1;
602         unsigned int vga_switcheroo_registered:1;
603         unsigned int init_failed:1; /* delayed init failed */
604         unsigned int disabled:1; /* disabled by VGA-switcher */
605
606         /* for debugging */
607         unsigned int last_cmd[AZX_MAX_CODECS];
608
609         /* for pending irqs */
610         struct work_struct irq_pending_work;
611
612         /* reboot notifier (for mysterious hangup problem at power-down) */
613         struct notifier_block reboot_notifier;
614
615         /* card list (for power_save trigger) */
616         struct list_head list;
617
618 #ifdef CONFIG_SND_HDA_DSP_LOADER
619         struct azx_dev saved_azx_dev;
620 #endif
621 };
622
623 #define CREATE_TRACE_POINTS
624 #include "hda_intel_trace.h"
625
626 /* driver types */
627 enum {
628         AZX_DRIVER_ICH,
629         AZX_DRIVER_PCH,
630         AZX_DRIVER_SCH,
631         AZX_DRIVER_ATI,
632         AZX_DRIVER_ATIHDMI,
633         AZX_DRIVER_ATIHDMI_NS,
634         AZX_DRIVER_VIA,
635         AZX_DRIVER_SIS,
636         AZX_DRIVER_ULI,
637         AZX_DRIVER_NVIDIA,
638         AZX_DRIVER_NVIDIA_TEGRA,
639         AZX_DRIVER_TERA,
640         AZX_DRIVER_CTX,
641         AZX_DRIVER_CTHDA,
642         AZX_DRIVER_GENERIC,
643         AZX_NUM_DRIVERS, /* keep this as last entry */
644 };
645
646 /* driver quirks (capabilities) */
647 /* bits 0-7 are used for indicating driver type */
648 #define AZX_DCAPS_NO_TCSEL      (1 << 8)        /* No Intel TCSEL bit */
649 #define AZX_DCAPS_NO_MSI        (1 << 9)        /* No MSI support */
650 #define AZX_DCAPS_ATI_SNOOP     (1 << 10)       /* ATI snoop enable */
651 #define AZX_DCAPS_NVIDIA_SNOOP  (1 << 11)       /* Nvidia snoop enable */
652 #define AZX_DCAPS_SCH_SNOOP     (1 << 12)       /* SCH/PCH snoop enable */
653 #define AZX_DCAPS_RIRB_DELAY    (1 << 13)       /* Long delay in read loop */
654 #define AZX_DCAPS_RIRB_PRE_DELAY (1 << 14)      /* Put a delay before read */
655 #define AZX_DCAPS_CTX_WORKAROUND (1 << 15)      /* X-Fi workaround */
656 #define AZX_DCAPS_POSFIX_LPIB   (1 << 16)       /* Use LPIB as default */
657 #define AZX_DCAPS_POSFIX_VIA    (1 << 17)       /* Use VIACOMBO as default */
658 #define AZX_DCAPS_NO_64BIT      (1 << 18)       /* No 64bit address */
659 #define AZX_DCAPS_SYNC_WRITE    (1 << 19)       /* sync each cmd write */
660 #define AZX_DCAPS_OLD_SSYNC     (1 << 20)       /* Old SSYNC reg for ICH */
661 #define AZX_DCAPS_BUFSIZE       (1 << 21)       /* no buffer size alignment */
662 #define AZX_DCAPS_ALIGN_BUFSIZE (1 << 22)       /* buffer size alignment */
663 #define AZX_DCAPS_4K_BDLE_BOUNDARY (1 << 23)    /* BDLE in 4k boundary */
664 #define AZX_DCAPS_COUNT_LPIB_DELAY  (1 << 25)   /* Take LPIB as delay */
665 #define AZX_DCAPS_PM_RUNTIME    (1 << 26)       /* runtime PM support */
666
667 /* quirks for Intel PCH */
668 #define AZX_DCAPS_INTEL_PCH_NOPM \
669         (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
670          AZX_DCAPS_COUNT_LPIB_DELAY)
671
672 #define AZX_DCAPS_INTEL_PCH \
673         (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
674
675 /* quirks for ATI SB / AMD Hudson */
676 #define AZX_DCAPS_PRESET_ATI_SB \
677         (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
678          AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
679
680 /* quirks for ATI/AMD HDMI */
681 #define AZX_DCAPS_PRESET_ATI_HDMI \
682         (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
683
684 /* quirks for Nvidia */
685 #define AZX_DCAPS_PRESET_NVIDIA \
686         (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
687          AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT  | AZX_DCAPS_PM_RUNTIME)
688
689 #define AZX_DCAPS_PRESET_CTHDA \
690         (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
691
692 /*
693  * VGA-switcher support
694  */
695 #ifdef SUPPORT_VGA_SWITCHEROO
696 #define use_vga_switcheroo(chip)        ((chip)->use_vga_switcheroo)
697 #else
698 #define use_vga_switcheroo(chip)        0
699 #endif
700
701 static char *driver_short_names[] = {
702         [AZX_DRIVER_ICH] = "HDA Intel",
703         [AZX_DRIVER_PCH] = "HDA Intel PCH",
704         [AZX_DRIVER_SCH] = "HDA Intel MID",
705         [AZX_DRIVER_ATI] = "HDA ATI SB",
706         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
707         [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
708         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
709         [AZX_DRIVER_SIS] = "HDA SIS966",
710         [AZX_DRIVER_ULI] = "HDA ULI M5461",
711         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
712         [AZX_DRIVER_NVIDIA_TEGRA] = "HDA NVIDIA Tegra",
713         [AZX_DRIVER_TERA] = "HDA Teradici",
714         [AZX_DRIVER_CTX] = "HDA Creative",
715         [AZX_DRIVER_CTHDA] = "HDA Creative",
716         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
717 };
718
719 /*
720  * macros for easy use
721  */
722 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
723 #define MASK_LONG_ALIGN         0x3UL
724 #define SHIFT_BYTE              3
725 #define SHIFT_BITS(reg)         ((reg & MASK_LONG_ALIGN) << SHIFT_BYTE)
726 #define ADDR_ALIGN_L(base, reg) (base + (reg & ~MASK_LONG_ALIGN))
727 #define MASK(bits)              (BIT(bits) - 1)
728 #define MASK_REG(reg, bits)     (MASK(bits) << SHIFT_BITS(reg))
729
730 #define tegra_write(base, reg, val, bits) \
731         writel((readl(ADDR_ALIGN_L(base, reg)) & ~MASK_REG(reg, bits)) | \
732                ((val) << SHIFT_BITS(reg)), ADDR_ALIGN_L(base, reg))
733
734 #define tegra_read(base, reg, bits) \
735         ((readl(ADDR_ALIGN_L(base, reg)) >> SHIFT_BITS(reg)) & MASK(bits))
736
737 #define azx_writel(chip, reg, value) \
738         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
739 #define azx_readl(chip, reg) \
740         readl((chip)->remap_addr + ICH6_REG_##reg)
741 #define azx_writew(chip, reg, value) \
742         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 16)
743 #define azx_readw(chip, reg) \
744         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 16)
745 #define azx_writeb(chip, reg, value) \
746         tegra_write((chip)->remap_addr, ICH6_REG_##reg, value, 8)
747 #define azx_readb(chip, reg) \
748         tegra_read((chip)->remap_addr, ICH6_REG_##reg, 8)
749
750 #define azx_sd_writel(dev, reg, value) \
751         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
752 #define azx_sd_readl(dev, reg) \
753         readl((dev)->sd_addr + ICH6_REG_##reg)
754 #define azx_sd_writew(dev, reg, value) \
755         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 16)
756 #define azx_sd_readw(dev, reg) \
757         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 16)
758 #define azx_sd_writeb(dev, reg, value) \
759         tegra_write((dev)->sd_addr, ICH6_REG_##reg, value, 8)
760 #define azx_sd_readb(dev, reg) \
761         tegra_read((dev)->sd_addr, ICH6_REG_##reg, 8)
762
763 #else /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
764 #define azx_writel(chip,reg,value) \
765         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
766 #define azx_readl(chip,reg) \
767         readl((chip)->remap_addr + ICH6_REG_##reg)
768 #define azx_writew(chip,reg,value) \
769         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
770 #define azx_readw(chip,reg) \
771         readw((chip)->remap_addr + ICH6_REG_##reg)
772 #define azx_writeb(chip,reg,value) \
773         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
774 #define azx_readb(chip,reg) \
775         readb((chip)->remap_addr + ICH6_REG_##reg)
776
777 #define azx_sd_writel(dev,reg,value) \
778         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
779 #define azx_sd_readl(dev,reg) \
780         readl((dev)->sd_addr + ICH6_REG_##reg)
781 #define azx_sd_writew(dev,reg,value) \
782         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
783 #define azx_sd_readw(dev,reg) \
784         readw((dev)->sd_addr + ICH6_REG_##reg)
785 #define azx_sd_writeb(dev,reg,value) \
786         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
787 #define azx_sd_readb(dev,reg) \
788         readb((dev)->sd_addr + ICH6_REG_##reg)
789
790 #endif /* CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA */
791
792 /* for pcm support */
793 #define get_azx_dev(substream) (substream->runtime->private_data)
794
795 #ifdef CONFIG_X86
796 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
797 {
798         int pages;
799
800         if (azx_snoop(chip))
801                 return;
802         if (!dmab || !dmab->area || !dmab->bytes)
803                 return;
804
805 #ifdef CONFIG_SND_DMA_SGBUF
806         if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
807                 struct snd_sg_buf *sgbuf = dmab->private_data;
808                 if (on)
809                         set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
810                 else
811                         set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
812                 return;
813         }
814 #endif
815
816         pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
817         if (on)
818                 set_memory_wc((unsigned long)dmab->area, pages);
819         else
820                 set_memory_wb((unsigned long)dmab->area, pages);
821 }
822
823 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
824                                  bool on)
825 {
826         __mark_pages_wc(chip, buf, on);
827 }
828 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
829                                    struct snd_pcm_substream *substream, bool on)
830 {
831         if (azx_dev->wc_marked != on) {
832                 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
833                 azx_dev->wc_marked = on;
834         }
835 }
836 #else
837 /* NOP for other archs */
838 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
839                                  bool on)
840 {
841 }
842 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
843                                    struct snd_pcm_substream *substream, bool on)
844 {
845 }
846 #endif
847
848 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
849 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
850 static inline const char *azx_name(const struct azx *chip)
851 {
852         if (chip->pci)
853                 return pci_name(chip->pci);
854         else /* for platform bus based devices */
855                 return dev_name(&chip->pdev->dev);
856 }
857
858 /*
859  * Interface for HD codec
860  */
861
862 /*
863  * CORB / RIRB interface
864  */
865 static int azx_alloc_cmd_io(struct azx *chip)
866 {
867         int err;
868
869         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
870         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
871                                   chip->dev,
872                                   PAGE_SIZE, &chip->rb);
873         if (err < 0) {
874                 snd_printk(KERN_ERR SFX "%s: cannot allocate CORB/RIRB\n", azx_name(chip));
875                 return err;
876         }
877         mark_pages_wc(chip, &chip->rb, true);
878         return 0;
879 }
880
881 static void azx_init_cmd_io(struct azx *chip)
882 {
883         spin_lock_irq(&chip->reg_lock);
884         /* CORB set up */
885         chip->corb.addr = chip->rb.addr;
886         chip->corb.buf = (u32 *)chip->rb.area;
887         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
888         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
889
890         /* set the corb size to 256 entries (ULI requires explicitly) */
891         azx_writeb(chip, CORBSIZE, 0x02);
892         /* set the corb write pointer to 0 */
893         azx_writew(chip, CORBWP, 0);
894         /* reset the corb hw read pointer */
895         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
896         /* enable corb dma */
897         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
898
899         /* RIRB set up */
900         chip->rirb.addr = chip->rb.addr + 2048;
901         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
902         chip->rirb.wp = chip->rirb.rp = 0;
903         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
904         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
905         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
906
907         /* set the rirb size to 256 entries (ULI requires explicitly) */
908         azx_writeb(chip, RIRBSIZE, 0x02);
909         /* reset the rirb hw write pointer */
910         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
911         /* set N=1, get RIRB response interrupt for new entry */
912         if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
913                 azx_writew(chip, RINTCNT, 0xc0);
914         else
915                 azx_writew(chip, RINTCNT, 1);
916         /* enable rirb dma and response irq */
917         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
918         spin_unlock_irq(&chip->reg_lock);
919 }
920
921 static void azx_free_cmd_io(struct azx *chip)
922 {
923         spin_lock_irq(&chip->reg_lock);
924         /* disable ringbuffer DMAs */
925         azx_writeb(chip, RIRBCTL, 0);
926         azx_writeb(chip, CORBCTL, 0);
927         spin_unlock_irq(&chip->reg_lock);
928 }
929
930 static unsigned int azx_command_addr(u32 cmd)
931 {
932         unsigned int addr = cmd >> 28;
933
934         if (addr >= AZX_MAX_CODECS) {
935                 snd_BUG();
936                 addr = 0;
937         }
938
939         return addr;
940 }
941
942 static unsigned int azx_response_addr(u32 res)
943 {
944         unsigned int addr = res & 0xf;
945
946         if (addr >= AZX_MAX_CODECS) {
947                 snd_BUG();
948                 addr = 0;
949         }
950
951         return addr;
952 }
953
954 /* send a command */
955 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
956 {
957         struct azx *chip = bus->private_data;
958         unsigned int addr = azx_command_addr(val);
959         unsigned int wp, rp;
960
961         spin_lock_irq(&chip->reg_lock);
962
963         /* add command to corb */
964         wp = azx_readw(chip, CORBWP);
965         if (wp == 0xffff) {
966                 /* something wrong, controller likely turned to D3 */
967                 spin_unlock_irq(&chip->reg_lock);
968                 return -EIO;
969         }
970         wp++;
971         wp %= ICH6_MAX_CORB_ENTRIES;
972
973         rp = azx_readw(chip, CORBRP);
974         if (wp == rp) {
975                 /* oops, it's full */
976                 spin_unlock_irq(&chip->reg_lock);
977                 return -EAGAIN;
978         }
979
980         chip->rirb.cmds[addr]++;
981         chip->corb.buf[wp] = cpu_to_le32(val);
982         azx_writel(chip, CORBWP, wp);
983
984         spin_unlock_irq(&chip->reg_lock);
985
986         return 0;
987 }
988
989 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
990
991 /* retrieve RIRB entry - called from interrupt handler */
992 static void azx_update_rirb(struct azx *chip)
993 {
994         unsigned int rp, wp;
995         unsigned int addr;
996         u32 res, res_ex;
997
998         wp = azx_readw(chip, RIRBWP);
999         if (wp == 0xffff) {
1000                 /* something wrong, controller likely turned to D3 */
1001                 return;
1002         }
1003
1004         if (wp == chip->rirb.wp)
1005                 return;
1006         chip->rirb.wp = wp;
1007
1008         while (chip->rirb.rp != wp) {
1009                 chip->rirb.rp++;
1010                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
1011
1012                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
1013                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
1014                 res = le32_to_cpu(chip->rirb.buf[rp]);
1015                 addr = azx_response_addr(res_ex);
1016                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
1017                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
1018                 else if (chip->rirb.cmds[addr]) {
1019                         chip->rirb.res[addr] = res;
1020                         smp_wmb();
1021                         chip->rirb.cmds[addr]--;
1022                 } else
1023                         snd_printk(KERN_ERR SFX "%s: spurious response %#x:%#x, "
1024                                    "last cmd=%#08x\n",
1025                                    azx_name(chip),
1026                                    res, res_ex,
1027                                    chip->last_cmd[addr]);
1028         }
1029 }
1030
1031 /* receive a response */
1032 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
1033                                           unsigned int addr)
1034 {
1035         struct azx *chip = bus->private_data;
1036         unsigned long timeout;
1037         unsigned long loopcounter;
1038         int do_poll = 0;
1039
1040  again:
1041         timeout = jiffies + msecs_to_jiffies(1000);
1042
1043         for (loopcounter = 0;; loopcounter++) {
1044                 if (chip->polling_mode || do_poll) {
1045                         spin_lock_irq(&chip->reg_lock);
1046                         azx_update_rirb(chip);
1047                         spin_unlock_irq(&chip->reg_lock);
1048                 }
1049                 if (!chip->rirb.cmds[addr]) {
1050                         smp_rmb();
1051                         bus->rirb_error = 0;
1052
1053                         if (!do_poll)
1054                                 chip->poll_count = 0;
1055                         return chip->rirb.res[addr]; /* the last value */
1056                 }
1057                 if (time_after(jiffies, timeout))
1058                         break;
1059                 if (bus->needs_damn_long_delay || loopcounter > 3000)
1060                         msleep(2); /* temporary workaround */
1061                 else {
1062                         udelay(10);
1063                         cond_resched();
1064                 }
1065         }
1066
1067         if (!chip->polling_mode && chip->poll_count < 2) {
1068                 snd_printdd(SFX "%s: azx_get_response timeout, "
1069                            "polling the codec once: last cmd=0x%08x\n",
1070                            azx_name(chip), chip->last_cmd[addr]);
1071                 do_poll = 1;
1072                 chip->poll_count++;
1073                 goto again;
1074         }
1075
1076
1077         if (!chip->polling_mode) {
1078                 snd_printk(KERN_WARNING SFX "%s: azx_get_response timeout, "
1079                            "switching to polling mode: last cmd=0x%08x\n",
1080                            azx_name(chip), chip->last_cmd[addr]);
1081                 chip->polling_mode = 1;
1082                 goto again;
1083         }
1084
1085         if (chip->msi) {
1086                 snd_printk(KERN_WARNING SFX "%s: No response from codec, "
1087                            "disabling MSI: last cmd=0x%08x\n",
1088                            azx_name(chip), chip->last_cmd[addr]);
1089                 free_irq(chip->irq, chip);
1090                 chip->irq = -1;
1091                 pci_disable_msi(chip->pci);
1092                 chip->msi = 0;
1093                 if (azx_acquire_irq(chip, 1) < 0) {
1094                         bus->rirb_error = 1;
1095                         return -1;
1096                 }
1097                 goto again;
1098         }
1099
1100         if (chip->probing) {
1101                 /* If this critical timeout happens during the codec probing
1102                  * phase, this is likely an access to a non-existing codec
1103                  * slot.  Better to return an error and reset the system.
1104                  */
1105                 return -1;
1106         }
1107
1108         /* a fatal communication error; need either to reset or to fallback
1109          * to the single_cmd mode
1110          */
1111         bus->rirb_error = 1;
1112         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
1113                 bus->response_reset = 1;
1114                 return -1; /* give a chance to retry */
1115         }
1116
1117         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
1118                    "switching to single_cmd mode: last cmd=0x%08x\n",
1119                    chip->last_cmd[addr]);
1120         chip->single_cmd = 1;
1121         bus->response_reset = 0;
1122         /* release CORB/RIRB */
1123         azx_free_cmd_io(chip);
1124         /* disable unsolicited responses */
1125         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
1126         return -1;
1127 }
1128
1129 /*
1130  * Use the single immediate command instead of CORB/RIRB for simplicity
1131  *
1132  * Note: according to Intel, this is not preferred use.  The command was
1133  *       intended for the BIOS only, and may get confused with unsolicited
1134  *       responses.  So, we shouldn't use it for normal operation from the
1135  *       driver.
1136  *       I left the codes, however, for debugging/testing purposes.
1137  */
1138
1139 /* receive a response */
1140 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
1141 {
1142         int timeout = 50;
1143
1144         while (timeout--) {
1145                 /* check IRV busy bit */
1146                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
1147                         /* reuse rirb.res as the response return value */
1148                         chip->rirb.res[addr] = azx_readl(chip, IR);
1149                         return 0;
1150                 }
1151                 udelay(1);
1152         }
1153         if (printk_ratelimit())
1154                 snd_printd(SFX "%s: get_response timeout: IRS=0x%x\n",
1155                            azx_name(chip), azx_readw(chip, IRS));
1156         chip->rirb.res[addr] = -1;
1157         return -EIO;
1158 }
1159
1160 /* send a command */
1161 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
1162 {
1163         struct azx *chip = bus->private_data;
1164         unsigned int addr = azx_command_addr(val);
1165         int timeout = 50;
1166
1167         bus->rirb_error = 0;
1168         while (timeout--) {
1169                 /* check ICB busy bit */
1170                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
1171                         /* Clear IRV valid bit */
1172                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1173                                    ICH6_IRS_VALID);
1174                         azx_writel(chip, IC, val);
1175                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
1176                                    ICH6_IRS_BUSY);
1177                         return azx_single_wait_for_response(chip, addr);
1178                 }
1179                 udelay(1);
1180         }
1181         if (printk_ratelimit())
1182                 snd_printd(SFX "%s: send_cmd timeout: IRS=0x%x, val=0x%x\n",
1183                            azx_name(chip), azx_readw(chip, IRS), val);
1184         return -EIO;
1185 }
1186
1187 /* receive a response */
1188 static unsigned int azx_single_get_response(struct hda_bus *bus,
1189                                             unsigned int addr)
1190 {
1191         struct azx *chip = bus->private_data;
1192         return chip->rirb.res[addr];
1193 }
1194
1195 /*
1196  * The below are the main callbacks from hda_codec.
1197  *
1198  * They are just the skeleton to call sub-callbacks according to the
1199  * current setting of chip->single_cmd.
1200  */
1201
1202 /* send a command */
1203 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1204 {
1205         struct azx *chip = bus->private_data;
1206         unsigned int ret = 0;
1207
1208         if (chip->disabled)
1209                 return 0;
1210
1211         pm_runtime_get_sync(chip->dev);
1212         chip->last_cmd[azx_command_addr(val)] = val;
1213         if (chip->single_cmd)
1214                 ret = azx_single_send_cmd(bus, val);
1215         else
1216                 ret = azx_corb_send_cmd(bus, val);
1217         pm_runtime_put(chip->dev);
1218
1219         return ret;
1220 }
1221
1222 /* get a response */
1223 static unsigned int azx_get_response(struct hda_bus *bus,
1224                                      unsigned int addr)
1225 {
1226         struct azx *chip = bus->private_data;
1227         unsigned int ret = 0;
1228         if (chip->disabled)
1229                 return ret;
1230         pm_runtime_get_sync(chip->dev);
1231         if (chip->single_cmd)
1232                 ret = azx_single_get_response(bus, addr);
1233         else
1234                 ret = azx_rirb_get_response(bus, addr);
1235         pm_runtime_put(chip->dev);
1236
1237         return ret;
1238 }
1239
1240 #ifdef CONFIG_PM
1241 static void azx_power_notify(struct hda_bus *bus, bool power_up);
1242 #endif
1243
1244 #ifdef CONFIG_SND_HDA_DSP_LOADER
1245 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1246                                 unsigned int byte_size,
1247                                 struct snd_dma_buffer *bufp);
1248 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
1249 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1250                                  struct snd_dma_buffer *dmab);
1251 #endif
1252
1253 /* reset codec link */
1254 static int azx_reset(struct azx *chip, int full_reset)
1255 {
1256         unsigned long timeout;
1257
1258         if (!full_reset)
1259                 goto __skip;
1260
1261         /* clear STATESTS */
1262         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1263
1264         /* reset controller */
1265         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
1266
1267         timeout = jiffies + msecs_to_jiffies(100);
1268         while (azx_readb(chip, GCTL) &&
1269                         time_before(jiffies, timeout))
1270                 usleep_range(500, 1000);
1271
1272         /* delay for >= 100us for codec PLL to settle per spec
1273          * Rev 0.9 section 5.5.1
1274          */
1275         usleep_range(500, 1000);
1276
1277         /* Bring controller out of reset */
1278         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
1279
1280         timeout = jiffies + msecs_to_jiffies(100);
1281         while (!azx_readb(chip, GCTL) &&
1282                         time_before(jiffies, timeout))
1283                 usleep_range(500, 1000);
1284
1285         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
1286         usleep_range(1000, 1200);
1287
1288       __skip:
1289         /* check to see if controller is ready */
1290         if (!azx_readb(chip, GCTL)) {
1291                 snd_printd(SFX "%s: azx_reset: controller not ready!\n", azx_name(chip));
1292                 return -EBUSY;
1293         }
1294
1295         /* Accept unsolicited responses */
1296         if (!chip->single_cmd)
1297                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
1298                            ICH6_GCTL_UNSOL);
1299
1300         /* detect codecs */
1301         if (!chip->codec_mask) {
1302                 chip->codec_mask = azx_readw(chip, STATESTS);
1303                 snd_printdd(SFX "%s: codec_mask = 0x%x\n", azx_name(chip), chip->codec_mask);
1304         }
1305
1306         return 0;
1307 }
1308
1309
1310 /*
1311  * Lowlevel interface
1312  */
1313
1314 /* enable interrupts */
1315 static void azx_int_enable(struct azx *chip)
1316 {
1317         /* enable controller CIE and GIE */
1318         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
1319                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
1320 }
1321
1322 /* disable interrupts */
1323 static void azx_int_disable(struct azx *chip)
1324 {
1325         int i;
1326
1327         /* disable interrupts in stream descriptor */
1328         for (i = 0; i < chip->num_streams; i++) {
1329                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1330                 azx_sd_writeb(azx_dev, SD_CTL,
1331                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
1332         }
1333
1334         /* disable SIE for all streams */
1335         azx_writeb(chip, INTCTL, 0);
1336
1337         /* disable controller CIE and GIE */
1338         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
1339                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
1340 }
1341
1342 /* clear interrupts */
1343 static void azx_int_clear(struct azx *chip)
1344 {
1345         int i;
1346
1347         /* clear stream status */
1348         for (i = 0; i < chip->num_streams; i++) {
1349                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1350                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1351         }
1352
1353         /* clear STATESTS */
1354         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
1355
1356         /* clear rirb status */
1357         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1358
1359         /* clear int status */
1360         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
1361 }
1362
1363 /* start a stream */
1364 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
1365 {
1366         /*
1367          * Before stream start, initialize parameter
1368          */
1369         azx_dev->insufficient = 1;
1370
1371         /* enable SIE */
1372         azx_writel(chip, INTCTL,
1373                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
1374         /* set DMA start and interrupt mask */
1375         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1376                       SD_CTL_DMA_START | SD_INT_MASK);
1377 }
1378
1379 /* stop DMA */
1380 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
1381 {
1382         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
1383                       ~(SD_CTL_DMA_START | SD_INT_MASK));
1384         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
1385 }
1386
1387 /* stop a stream */
1388 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
1389 {
1390         azx_stream_clear(chip, azx_dev);
1391         /* disable SIE */
1392         azx_writel(chip, INTCTL,
1393                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
1394 }
1395
1396
1397 /*
1398  * reset and start the controller registers
1399  */
1400 static void azx_init_chip(struct azx *chip, int full_reset)
1401 {
1402         if (chip->initialized)
1403                 return;
1404
1405         /* reset controller */
1406         azx_reset(chip, full_reset);
1407
1408         /* initialize interrupts */
1409         azx_int_clear(chip);
1410         azx_int_enable(chip);
1411
1412         /* initialize the codec command I/O */
1413         if (!chip->single_cmd)
1414                 azx_init_cmd_io(chip);
1415
1416         /* program the position buffer */
1417         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1418         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1419
1420         chip->initialized = 1;
1421 }
1422
1423 /*
1424  * initialize the PCI registers
1425  */
1426 /* update bits in a PCI register byte */
1427 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1428                             unsigned char mask, unsigned char val)
1429 {
1430         unsigned char data;
1431
1432         pci_read_config_byte(pci, reg, &data);
1433         data &= ~mask;
1434         data |= (val & mask);
1435         pci_write_config_byte(pci, reg, data);
1436 }
1437
1438 static void azx_init_pci(struct azx *chip)
1439 {
1440         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1441          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1442          * Ensuring these bits are 0 clears playback static on some HD Audio
1443          * codecs.
1444          * The PCI register TCSEL is defined in the Intel manuals.
1445          */
1446         if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
1447                 snd_printdd(SFX "%s: Clearing TCSEL\n", azx_name(chip));
1448                 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1449         }
1450
1451         /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
1452          * we need to enable snoop.
1453          */
1454         if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
1455                 snd_printdd(SFX "%s: Setting ATI snoop: %d\n", azx_name(chip), azx_snoop(chip));
1456                 update_pci_byte(chip->pci,
1457                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
1458                                 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
1459         }
1460
1461         /* For NVIDIA HDA, enable snoop */
1462         if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
1463                 snd_printdd(SFX "%s: Setting Nvidia snoop: %d\n", azx_name(chip), azx_snoop(chip));
1464                 update_pci_byte(chip->pci,
1465                                 NVIDIA_HDA_TRANSREG_ADDR,
1466                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1467                 update_pci_byte(chip->pci,
1468                                 NVIDIA_HDA_ISTRM_COH,
1469                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1470                 update_pci_byte(chip->pci,
1471                                 NVIDIA_HDA_OSTRM_COH,
1472                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1473         }
1474
1475         /* Enable SCH/PCH snoop if needed */
1476         if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
1477                 unsigned short snoop;
1478                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1479                 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
1480                     (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
1481                         snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
1482                         if (!azx_snoop(chip))
1483                                 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
1484                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
1485                         pci_read_config_word(chip->pci,
1486                                 INTEL_SCH_HDA_DEVC, &snoop);
1487                 }
1488                 snd_printdd(SFX "%s: SCH snoop: %s\n",
1489                                 azx_name(chip), (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1490                                 ? "Disabled" : "Enabled");
1491         }
1492 }
1493
1494 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
1495 /*
1496  * initialize the platform specific registers
1497  */
1498 static void reg_update_bits(void __iomem *base, unsigned int reg,
1499                             unsigned int mask, unsigned int val)
1500 {
1501         unsigned int data;
1502
1503         data = readl(base + reg);
1504         data &= ~mask;
1505         data |= (val & mask);
1506         writel(data, base + reg);
1507 }
1508
1509 static void azx_init_platform(struct azx *chip)
1510 {
1511         switch (chip->driver_type) {
1512 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1513         case AZX_DRIVER_NVIDIA_TEGRA:
1514                 /*Enable the PCI access */
1515                 reg_update_bits(chip->remap_config_addr,
1516                                 NVIDIA_TEGRA_HDA_IPFS_CONFIG,
1517                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI,
1518                                 NVIDIA_TEGRA_HDA_IPFS_EN_FPCI);
1519                 /* Enable MEM/IO space and bus master */
1520                 reg_update_bits(chip->remap_config_addr,
1521                                 NVIDIA_TEGRA_HDA_CFG_CMD_OFFSET, 0x507,
1522                                 NVIDIA_TEGRA_HDA_ENABLE_MEM_SPACE |
1523                                 NVIDIA_TEGRA_HDA_ENABLE_IO_SPACE |
1524                                 NVIDIA_TEGRA_HDA_ENABLE_BUS_MASTER |
1525                                 NVIDIA_TEGRA_HDA_ENABLE_SERR);
1526                 reg_update_bits(chip->remap_config_addr,
1527                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1528                                 NVIDIA_TEGRA_HDA_BAR0_INIT_PROGRAM);
1529                 reg_update_bits(chip->remap_config_addr,
1530                                 NVIDIA_TEGRA_HDA_CFG_BAR0_OFFSET, 0xFFFFFFFF,
1531                                 NVIDIA_TEGRA_HDA_BAR0_FINAL_PROGRAM);
1532                 reg_update_bits(chip->remap_config_addr,
1533                                 NVIDIA_TEGRA_HDA_IPFS_FPCI_BAR0, 0xFFFFFFFF,
1534                                 NVIDIA_TEGRA_HDA_FPCI_BAR0_START);
1535                 reg_update_bits(chip->remap_config_addr,
1536                                 NVIDIA_TEGRA_HDA_IPFS_INTR_MASK,
1537                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR,
1538                                 NVIDIA_TEGRA_HDA_IPFS_EN_INTR);
1539                 break;
1540 #endif
1541         default:
1542                 break;
1543         }
1544
1545         return;
1546 }
1547
1548
1549 static void __azx_platform_enable_clocks(struct azx *chip)
1550 {
1551         int i;
1552         int partition_id;
1553
1554 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1555 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
1556         partition_id = tegra_pd_get_powergate_id(tegra_disb_pd);
1557         if (partition_id < 0)
1558                 return -EINVAL;
1559 #else
1560         partition_id = TEGRA_POWERGATE_DISB;
1561 #endif
1562         tegra_unpowergate_partition(partition_id);
1563 #endif
1564
1565         for (i = 0; i < chip->platform_clk_count; i++)
1566                 clk_enable(chip->platform_clks[i]);
1567
1568         chip->platform_clk_enable++;
1569
1570 }
1571
1572 static void azx_platform_enable_clocks(struct azx *chip)
1573 {
1574 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1575         pm_runtime_get_sync(chip->dev);
1576 #endif
1577         __azx_platform_enable_clocks(chip);
1578 }
1579
1580 static void __azx_platform_disable_clocks(struct azx *chip)
1581 {
1582         int i;
1583         int partition_id;
1584
1585         if (!chip->platform_clk_enable)
1586                 return;
1587
1588         for (i = 0; i < chip->platform_clk_count; i++)
1589                 clk_disable(chip->platform_clks[i]);
1590
1591 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1592 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
1593         partition_id = tegra_pd_get_powergate_id(tegra_disb_pd);
1594         if (partition_id < 0)
1595                 return -EINVAL;
1596 #else
1597         partition_id = TEGRA_POWERGATE_DISB;
1598 #endif
1599         tegra_powergate_partition(partition_id);
1600 #endif
1601
1602         chip->platform_clk_enable--;
1603 }
1604
1605 static void azx_platform_disable_clocks(struct azx *chip)
1606 {
1607         __azx_platform_disable_clocks(chip);
1608 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
1609         pm_runtime_put(chip->dev);
1610 #endif
1611 }
1612
1613 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
1614
1615 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1616
1617 /*
1618  * interrupt handler
1619  */
1620 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1621 {
1622         struct azx *chip = dev_id;
1623         struct azx_dev *azx_dev;
1624         u32 status;
1625         u8 sd_status;
1626         int i, ok;
1627
1628 #ifdef CONFIG_PM_RUNTIME
1629         if (chip->dev->power.runtime_status != RPM_ACTIVE)
1630                 return IRQ_NONE;
1631 #endif
1632
1633         spin_lock(&chip->reg_lock);
1634
1635         if (chip->disabled) {
1636                 spin_unlock(&chip->reg_lock);
1637                 return IRQ_NONE;
1638         }
1639
1640         status = azx_readl(chip, INTSTS);
1641         if (status == 0) {
1642                 spin_unlock(&chip->reg_lock);
1643                 return IRQ_NONE;
1644         }
1645
1646         for (i = 0; i < chip->num_streams; i++) {
1647                 azx_dev = &chip->azx_dev[i];
1648                 if (status & azx_dev->sd_int_sta_mask) {
1649                         sd_status = azx_sd_readb(azx_dev, SD_STS);
1650                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1651                         if (!azx_dev->substream || !azx_dev->running ||
1652                             !(sd_status & SD_INT_COMPLETE))
1653                                 continue;
1654                         /* check whether this IRQ is really acceptable */
1655                         ok = azx_position_ok(chip, azx_dev);
1656                         if (ok == 1) {
1657                                 azx_dev->irq_pending = 0;
1658                                 spin_unlock(&chip->reg_lock);
1659                                 snd_pcm_period_elapsed(azx_dev->substream);
1660                                 spin_lock(&chip->reg_lock);
1661                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1662                                 /* bogus IRQ, process it later */
1663                                 azx_dev->irq_pending = 1;
1664                                 queue_work(chip->bus->workq,
1665                                            &chip->irq_pending_work);
1666                         }
1667                 }
1668         }
1669
1670         /* clear rirb int */
1671         status = azx_readb(chip, RIRBSTS);
1672         if (status & RIRB_INT_MASK) {
1673                 if (status & RIRB_INT_RESPONSE) {
1674                         if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1675                                 udelay(80);
1676                         azx_update_rirb(chip);
1677                 }
1678                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1679         }
1680
1681 #if 0
1682         /* clear state status int */
1683         if (azx_readb(chip, STATESTS) & 0x04)
1684                 azx_writeb(chip, STATESTS, 0x04);
1685 #endif
1686         spin_unlock(&chip->reg_lock);
1687
1688         return IRQ_HANDLED;
1689 }
1690
1691
1692 /*
1693  * set up a BDL entry
1694  */
1695 static int setup_bdle(struct azx *chip,
1696                       struct snd_dma_buffer *dmab,
1697                       struct azx_dev *azx_dev, u32 **bdlp,
1698                       int ofs, int size, int with_ioc)
1699 {
1700         u32 *bdl = *bdlp;
1701
1702         while (size > 0) {
1703                 dma_addr_t addr;
1704                 int chunk;
1705
1706                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1707                         return -EINVAL;
1708
1709                 addr = snd_sgbuf_get_addr(dmab, ofs);
1710                 /* program the address field of the BDL entry */
1711                 bdl[0] = cpu_to_le32((u32)addr);
1712                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1713                 /* program the size field of the BDL entry */
1714                 chunk = snd_sgbuf_get_chunk_size(dmab, ofs, size);
1715                 /* one BDLE cannot cross 4K boundary on CTHDA chips */
1716                 if (chip->driver_caps & AZX_DCAPS_4K_BDLE_BOUNDARY) {
1717                         u32 remain = 0x1000 - (ofs & 0xfff);
1718                         if (chunk > remain)
1719                                 chunk = remain;
1720                 }
1721                 bdl[2] = cpu_to_le32(chunk);
1722                 /* program the IOC to enable interrupt
1723                  * only when the whole fragment is processed
1724                  */
1725                 size -= chunk;
1726                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1727                 bdl += 4;
1728                 azx_dev->frags++;
1729                 ofs += chunk;
1730         }
1731         *bdlp = bdl;
1732         return ofs;
1733 }
1734
1735 /*
1736  * set up BDL entries
1737  */
1738 static int azx_setup_periods(struct azx *chip,
1739                              struct snd_pcm_substream *substream,
1740                              struct azx_dev *azx_dev)
1741 {
1742         u32 *bdl;
1743         int i, ofs, periods, period_bytes;
1744         int pos_adj;
1745
1746         /* reset BDL address */
1747         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1748         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1749
1750         period_bytes = azx_dev->period_bytes;
1751         periods = azx_dev->bufsize / period_bytes;
1752
1753         /* program the initial BDL entries */
1754         bdl = (u32 *)azx_dev->bdl.area;
1755         ofs = 0;
1756         azx_dev->frags = 0;
1757         pos_adj = bdl_pos_adj[chip->dev_index];
1758         if (!azx_dev->no_period_wakeup && pos_adj > 0) {
1759                 struct snd_pcm_runtime *runtime = substream->runtime;
1760                 int pos_align = pos_adj;
1761                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1762                 if (!pos_adj)
1763                         pos_adj = pos_align;
1764                 else
1765                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1766                                 pos_align;
1767                 pos_adj = frames_to_bytes(runtime, pos_adj);
1768                 if (pos_adj >= period_bytes) {
1769                         snd_printk(KERN_WARNING SFX "%s: Too big adjustment %d\n",
1770                                    azx_name(chip), bdl_pos_adj[chip->dev_index]);
1771                         pos_adj = 0;
1772                 } else {
1773                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1774                                          azx_dev,
1775                                          &bdl, ofs, pos_adj, true);
1776                         if (ofs < 0)
1777                                 goto error;
1778                 }
1779         } else
1780                 pos_adj = 0;
1781         for (i = 0; i < periods; i++) {
1782                 if (i == periods - 1 && pos_adj)
1783                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1784                                          azx_dev, &bdl, ofs,
1785                                          period_bytes - pos_adj, 0);
1786                 else
1787                         ofs = setup_bdle(chip, snd_pcm_get_dma_buf(substream),
1788                                          azx_dev, &bdl, ofs,
1789                                          period_bytes,
1790                                          !azx_dev->no_period_wakeup);
1791                 if (ofs < 0)
1792                         goto error;
1793         }
1794         return 0;
1795
1796  error:
1797         snd_printk(KERN_ERR SFX "%s: Too many BDL entries: buffer=%d, period=%d\n",
1798                    azx_name(chip), azx_dev->bufsize, period_bytes);
1799         return -EINVAL;
1800 }
1801
1802 /* reset stream */
1803 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1804 {
1805         unsigned char val;
1806         int timeout;
1807
1808         azx_stream_clear(chip, azx_dev);
1809
1810         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1811                       SD_CTL_STREAM_RESET);
1812         udelay(3);
1813         timeout = 300;
1814         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1815                --timeout)
1816                 ;
1817         val &= ~SD_CTL_STREAM_RESET;
1818         udelay(100); /* WAR: Delay added to avoid mcerr */
1819         azx_sd_writeb(azx_dev, SD_CTL, val);
1820         udelay(3);
1821
1822         timeout = 300;
1823         /* waiting for hardware to report that the stream is out of reset */
1824         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1825                --timeout)
1826                 ;
1827
1828         /* reset first position - may not be synced with hw at this time */
1829         *azx_dev->posbuf = 0;
1830 }
1831
1832 /*
1833  * set up the SD for streaming
1834  */
1835 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1836 {
1837         unsigned int val;
1838         /* make sure the run bit is zero for SD */
1839         azx_stream_clear(chip, azx_dev);
1840         /* program the stream_tag */
1841         val = azx_sd_readl(azx_dev, SD_CTL);
1842         val = (val & ~SD_CTL_STREAM_TAG_MASK) |
1843                 (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT);
1844         if (!azx_snoop(chip))
1845                 val |= SD_CTL_TRAFFIC_PRIO;
1846         azx_sd_writel(azx_dev, SD_CTL, val);
1847
1848         /* program the length of samples in cyclic buffer */
1849         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1850
1851         /* program the stream format */
1852         /* this value needs to be the same as the one programmed */
1853         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1854
1855         /* program the stream LVI (last valid index) of the BDL */
1856         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1857
1858         /* program the BDL address */
1859         /* lower BDL address */
1860         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1861         /* upper BDL address */
1862         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1863
1864         /* enable the position buffer */
1865         if (chip->position_fix[0] != POS_FIX_LPIB ||
1866             chip->position_fix[1] != POS_FIX_LPIB) {
1867                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1868                         azx_writel(chip, DPLBASE,
1869                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1870         }
1871
1872         /* set the interrupt enable bits in the descriptor control register */
1873         azx_sd_writel(azx_dev, SD_CTL,
1874                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1875
1876         return 0;
1877 }
1878
1879 /*
1880  * Probe the given codec address
1881  */
1882 static int probe_codec(struct azx *chip, int addr)
1883 {
1884         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1885                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1886         unsigned int res;
1887
1888         mutex_lock(&chip->bus->cmd_mutex);
1889         chip->probing = 1;
1890         azx_send_cmd(chip->bus, cmd);
1891         res = azx_get_response(chip->bus, addr);
1892         chip->probing = 0;
1893         mutex_unlock(&chip->bus->cmd_mutex);
1894         if (res == -1)
1895                 return -EIO;
1896         snd_printdd(SFX "%s: codec #%d probed OK\n", azx_name(chip), addr);
1897         return 0;
1898 }
1899
1900 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1901                                  struct hda_pcm *cpcm);
1902 static void azx_stop_chip(struct azx *chip);
1903
1904 static void azx_bus_reset(struct hda_bus *bus)
1905 {
1906         struct azx *chip = bus->private_data;
1907
1908         bus->in_reset = 1;
1909         azx_stop_chip(chip);
1910         azx_init_chip(chip, 1);
1911 #ifdef CONFIG_PM
1912         if (chip->initialized) {
1913                 struct azx_pcm *p;
1914                 list_for_each_entry(p, &chip->pcm_list, list)
1915                         snd_pcm_suspend_all(p->pcm);
1916                 snd_hda_suspend(chip->bus);
1917                 snd_hda_resume(chip->bus);
1918         }
1919 #endif
1920         bus->in_reset = 0;
1921 }
1922
1923 static int get_jackpoll_interval(struct azx *chip)
1924 {
1925         int i = jackpoll_ms[chip->dev_index];
1926         unsigned int j;
1927         if (i == 0)
1928                 return 0;
1929         if (i < 50 || i > 60000)
1930                 j = 0;
1931         else
1932                 j = msecs_to_jiffies(i);
1933         if (j == 0)
1934                 snd_printk(KERN_WARNING SFX
1935                            "jackpoll_ms value out of range: %d\n", i);
1936         return j;
1937 }
1938
1939 /*
1940  * Codec initialization
1941  */
1942
1943 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1944 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
1945         [AZX_DRIVER_NVIDIA] = 8,
1946         [AZX_DRIVER_TERA] = 1,
1947 };
1948
1949 static int azx_codec_create(struct azx *chip, const char *model)
1950 {
1951         struct hda_bus_template bus_temp;
1952         int c, codecs, err;
1953         int max_slots;
1954
1955         memset(&bus_temp, 0, sizeof(bus_temp));
1956         bus_temp.private_data = chip;
1957         bus_temp.modelname = model;
1958         bus_temp.pci = chip->pci;
1959         bus_temp.pdev = chip->pdev;
1960         bus_temp.ops.command = azx_send_cmd;
1961         bus_temp.ops.get_response = azx_get_response;
1962         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1963         bus_temp.ops.bus_reset = azx_bus_reset;
1964 #ifdef CONFIG_PM
1965         bus_temp.power_save = &power_save;
1966         bus_temp.ops.pm_notify = azx_power_notify;
1967 #endif
1968 #ifdef CONFIG_SND_HDA_DSP_LOADER
1969         bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1970         bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1971         bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1972 #endif
1973
1974         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1975         if (err < 0)
1976                 return err;
1977
1978         if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1979                 snd_printd(SFX "%s: Enable delay in RIRB handling\n", azx_name(chip));
1980                 chip->bus->needs_damn_long_delay = 1;
1981         }
1982
1983         codecs = 0;
1984         max_slots = azx_max_codecs[chip->driver_type];
1985         if (!max_slots)
1986                 max_slots = AZX_DEFAULT_CODECS;
1987
1988         /* First try to probe all given codec slots */
1989         for (c = 0; c < max_slots; c++) {
1990                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1991                         if (probe_codec(chip, c) < 0) {
1992                                 /* Some BIOSen give you wrong codec addresses
1993                                  * that don't exist
1994                                  */
1995                                 snd_printk(KERN_WARNING SFX
1996                                            "%s: Codec #%d probe error; "
1997                                            "disabling it...\n", azx_name(chip), c);
1998                                 chip->codec_mask &= ~(1 << c);
1999                                 /* More badly, accessing to a non-existing
2000                                  * codec often screws up the controller chip,
2001                                  * and disturbs the further communications.
2002                                  * Thus if an error occurs during probing,
2003                                  * better to reset the controller chip to
2004                                  * get back to the sanity state.
2005                                  */
2006                                 azx_stop_chip(chip);
2007                                 azx_init_chip(chip, 1);
2008                         }
2009                 }
2010         }
2011
2012         /* AMD chipsets often cause the communication stalls upon certain
2013          * sequence like the pin-detection.  It seems that forcing the synced
2014          * access works around the stall.  Grrr...
2015          */
2016         if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
2017                 snd_printd(SFX "%s: Enable sync_write for stable communication\n",
2018                         azx_name(chip));
2019                 chip->bus->sync_write = 1;
2020                 chip->bus->allow_bus_reset = 1;
2021         }
2022
2023         /* Then create codec instances */
2024         for (c = 0; c < max_slots; c++) {
2025                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
2026                         struct hda_codec *codec;
2027                         err = snd_hda_codec_new(chip->bus, c, &codec);
2028                         if (err < 0)
2029                                 continue;
2030                         codec->jackpoll_interval = get_jackpoll_interval(chip);
2031                         codec->beep_mode = chip->beep_mode;
2032                         codecs++;
2033                 }
2034         }
2035         if (!codecs) {
2036                 snd_printk(KERN_ERR SFX "%s: no codecs initialized\n", azx_name(chip));
2037                 return -ENXIO;
2038         }
2039         return 0;
2040 }
2041
2042 /* configure each codec instance */
2043 static int azx_codec_configure(struct azx *chip)
2044 {
2045         struct hda_codec *codec;
2046         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2047                 snd_hda_codec_configure(codec);
2048         }
2049         return 0;
2050 }
2051
2052
2053 /*
2054  * PCM support
2055  */
2056
2057 /* assign a stream for the PCM */
2058 static inline struct azx_dev *
2059 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
2060 {
2061         int dev, i, nums;
2062         struct azx_dev *res = NULL;
2063         /* make a non-zero unique key for the substream */
2064         int key = (substream->pcm->device << 16) | (substream->number << 2) |
2065                 (substream->stream + 1);
2066
2067         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2068                 dev = chip->playback_index_offset;
2069                 nums = chip->playback_streams;
2070         } else {
2071                 dev = chip->capture_index_offset;
2072                 nums = chip->capture_streams;
2073         }
2074         for (i = 0; i < nums; i++, dev++) {
2075                 struct azx_dev *azx_dev = &chip->azx_dev[dev];
2076                 dsp_lock(azx_dev);
2077                 if (!azx_dev->opened && !dsp_is_locked(azx_dev)) {
2078                         res = azx_dev;
2079                         if (res->assigned_key == key) {
2080                                 res->opened = 1;
2081                                 res->assigned_key = key;
2082                                 dsp_unlock(azx_dev);
2083                                 return azx_dev;
2084                         }
2085                 }
2086                 dsp_unlock(azx_dev);
2087         }
2088         if (res) {
2089                 dsp_lock(res);
2090                 res->opened = 1;
2091                 res->assigned_key = key;
2092                 dsp_unlock(res);
2093         }
2094         return res;
2095 }
2096
2097 /* release the assigned stream */
2098 static inline void azx_release_device(struct azx_dev *azx_dev)
2099 {
2100         azx_dev->opened = 0;
2101 }
2102
2103 static cycle_t azx_cc_read(const struct cyclecounter *cc)
2104 {
2105         struct azx_dev *azx_dev = container_of(cc, struct azx_dev, azx_cc);
2106         struct snd_pcm_substream *substream = azx_dev->substream;
2107         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2108         struct azx *chip = apcm->chip;
2109
2110         return azx_readl(chip, WALLCLK);
2111 }
2112
2113 static void azx_timecounter_init(struct snd_pcm_substream *substream,
2114                                 bool force, cycle_t last)
2115 {
2116         struct azx_dev *azx_dev = get_azx_dev(substream);
2117         struct timecounter *tc = &azx_dev->azx_tc;
2118         struct cyclecounter *cc = &azx_dev->azx_cc;
2119         u64 nsec;
2120
2121         cc->read = azx_cc_read;
2122         cc->mask = CLOCKSOURCE_MASK(32);
2123
2124         /*
2125          * Converting from 24 MHz to ns means applying a 125/3 factor.
2126          * To avoid any saturation issues in intermediate operations,
2127          * the 125 factor is applied first. The division is applied
2128          * last after reading the timecounter value.
2129          * Applying the 1/3 factor as part of the multiplication
2130          * requires at least 20 bits for a decent precision, however
2131          * overflows occur after about 4 hours or less, not a option.
2132          */
2133
2134         cc->mult = 125; /* saturation after 195 years */
2135         cc->shift = 0;
2136
2137         nsec = 0; /* audio time is elapsed time since trigger */
2138         timecounter_init(tc, cc, nsec);
2139         if (force)
2140                 /*
2141                  * force timecounter to use predefined value,
2142                  * used for synchronized starts
2143                  */
2144                 tc->cycle_last = last;
2145 }
2146
2147 static u64 azx_adjust_codec_delay(struct snd_pcm_substream *substream,
2148                                 u64 nsec)
2149 {
2150         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2151         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2152         u64 codec_frames, codec_nsecs;
2153
2154         if (!hinfo->ops.get_delay)
2155                 return nsec;
2156
2157         codec_frames = hinfo->ops.get_delay(hinfo, apcm->codec, substream);
2158         codec_nsecs = div_u64(codec_frames * 1000000000LL,
2159                               substream->runtime->rate);
2160
2161         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2162                 return nsec + codec_nsecs;
2163
2164         return (nsec > codec_nsecs) ? nsec - codec_nsecs : 0;
2165 }
2166
2167 static int azx_get_wallclock_tstamp(struct snd_pcm_substream *substream,
2168                                 struct timespec *ts)
2169 {
2170         struct azx_dev *azx_dev = get_azx_dev(substream);
2171         u64 nsec;
2172
2173         nsec = timecounter_read(&azx_dev->azx_tc);
2174         nsec = div_u64(nsec, 3); /* can be optimized */
2175         nsec = azx_adjust_codec_delay(substream, nsec);
2176
2177         *ts = ns_to_timespec(nsec);
2178
2179         return 0;
2180 }
2181
2182 static struct snd_pcm_hardware azx_pcm_hw = {
2183         .info =                 (SNDRV_PCM_INFO_MMAP |
2184                                  SNDRV_PCM_INFO_INTERLEAVED |
2185                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
2186                                  SNDRV_PCM_INFO_MMAP_VALID |
2187                                  /* No full-resume yet implemented */
2188                                  /* SNDRV_PCM_INFO_RESUME |*/
2189                                  SNDRV_PCM_INFO_PAUSE |
2190                                  SNDRV_PCM_INFO_SYNC_START |
2191                                  SNDRV_PCM_INFO_HAS_WALL_CLOCK |
2192                                  SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
2193         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
2194         .rates =                SNDRV_PCM_RATE_48000,
2195         .rate_min =             48000,
2196         .rate_max =             48000,
2197         .channels_min =         2,
2198         .channels_max =         2,
2199         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
2200         .period_bytes_min =     128,
2201         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
2202         .periods_min =          2,
2203         .periods_max =          AZX_MAX_FRAG,
2204         .fifo_size =            0,
2205 };
2206
2207 static int azx_pcm_open(struct snd_pcm_substream *substream)
2208 {
2209         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2210         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2211         struct azx *chip = apcm->chip;
2212         struct azx_dev *azx_dev;
2213         struct snd_pcm_runtime *runtime = substream->runtime;
2214         unsigned long flags;
2215         int err;
2216         int buff_step;
2217
2218         mutex_lock(&chip->open_mutex);
2219         azx_dev = azx_assign_device(chip, substream);
2220         if (azx_dev == NULL) {
2221                 mutex_unlock(&chip->open_mutex);
2222                 return -EBUSY;
2223         }
2224         runtime->hw = azx_pcm_hw;
2225         runtime->hw.channels_min = hinfo->channels_min;
2226         runtime->hw.channels_max = hinfo->channels_max;
2227         runtime->hw.formats = hinfo->formats;
2228         runtime->hw.rates = hinfo->rates;
2229         snd_pcm_limit_hw_rates(runtime);
2230         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
2231
2232         /* avoid wrap-around with wall-clock */
2233         snd_pcm_hw_constraint_minmax(runtime, SNDRV_PCM_HW_PARAM_BUFFER_TIME,
2234                                 20,
2235                                 178000000);
2236
2237         if (chip->align_buffer_size)
2238                 /* constrain buffer sizes to be multiple of 128
2239                    bytes. This is more efficient in terms of memory
2240                    access but isn't required by the HDA spec and
2241                    prevents users from specifying exact period/buffer
2242                    sizes. For example for 44.1kHz, a period size set
2243                    to 20ms will be rounded to 19.59ms. */
2244                 buff_step = 128;
2245         else
2246                 /* Don't enforce steps on buffer sizes, still need to
2247                    be multiple of 4 bytes (HDA spec). Tested on Intel
2248                    HDA controllers, may not work on all devices where
2249                    option needs to be disabled */
2250                 buff_step = 4;
2251
2252         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
2253                                    buff_step);
2254         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
2255                                    buff_step);
2256         snd_hda_power_up_d3wait(apcm->codec);
2257         err = hinfo->ops.open(hinfo, apcm->codec, substream);
2258         if (err < 0) {
2259                 azx_release_device(azx_dev);
2260                 snd_hda_power_down(apcm->codec);
2261                 mutex_unlock(&chip->open_mutex);
2262                 return err;
2263         }
2264         snd_pcm_limit_hw_rates(runtime);
2265         /* sanity check */
2266         if (snd_BUG_ON(!runtime->hw.channels_min) ||
2267             snd_BUG_ON(!runtime->hw.channels_max) ||
2268             snd_BUG_ON(!runtime->hw.formats) ||
2269             snd_BUG_ON(!runtime->hw.rates)) {
2270                 azx_release_device(azx_dev);
2271                 hinfo->ops.close(hinfo, apcm->codec, substream);
2272                 snd_hda_power_down(apcm->codec);
2273                 mutex_unlock(&chip->open_mutex);
2274                 return -EINVAL;
2275         }
2276
2277         /* disable WALLCLOCK timestamps for capture streams
2278            until we figure out how to handle digital inputs */
2279         if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
2280                 runtime->hw.info &= ~SNDRV_PCM_INFO_HAS_WALL_CLOCK;
2281
2282         spin_lock_irqsave(&chip->reg_lock, flags);
2283         azx_dev->substream = substream;
2284         azx_dev->running = 0;
2285         spin_unlock_irqrestore(&chip->reg_lock, flags);
2286
2287         runtime->private_data = azx_dev;
2288         snd_pcm_set_sync(substream);
2289         mutex_unlock(&chip->open_mutex);
2290         return 0;
2291 }
2292
2293 static int azx_pcm_close(struct snd_pcm_substream *substream)
2294 {
2295         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2296         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2297         struct azx *chip = apcm->chip;
2298         struct azx_dev *azx_dev = get_azx_dev(substream);
2299         unsigned long flags;
2300
2301         mutex_lock(&chip->open_mutex);
2302         spin_lock_irqsave(&chip->reg_lock, flags);
2303         azx_dev->substream = NULL;
2304         azx_dev->running = 0;
2305         spin_unlock_irqrestore(&chip->reg_lock, flags);
2306         azx_release_device(azx_dev);
2307         hinfo->ops.close(hinfo, apcm->codec, substream);
2308         snd_hda_power_down(apcm->codec);
2309         mutex_unlock(&chip->open_mutex);
2310         return 0;
2311 }
2312
2313 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
2314                              struct snd_pcm_hw_params *hw_params)
2315 {
2316         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2317         struct azx *chip = apcm->chip;
2318         struct azx_dev *azx_dev = get_azx_dev(substream);
2319         int ret;
2320
2321         dsp_lock(azx_dev);
2322         if (dsp_is_locked(azx_dev)) {
2323                 ret = -EBUSY;
2324                 goto unlock;
2325         }
2326
2327         mark_runtime_wc(chip, azx_dev, substream, false);
2328         azx_dev->bufsize = 0;
2329         azx_dev->period_bytes = 0;
2330         azx_dev->format_val = 0;
2331         ret = snd_pcm_lib_malloc_pages(substream,
2332                                         params_buffer_bytes(hw_params));
2333         if (ret < 0)
2334                 goto unlock;
2335         mark_runtime_wc(chip, azx_dev, substream, true);
2336  unlock:
2337         dsp_unlock(azx_dev);
2338         return ret;
2339 }
2340
2341 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
2342 {
2343         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2344         struct azx_dev *azx_dev = get_azx_dev(substream);
2345         struct azx *chip = apcm->chip;
2346         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2347
2348         /* reset BDL address */
2349         dsp_lock(azx_dev);
2350         if (!dsp_is_locked(azx_dev)) {
2351                 azx_sd_writel(azx_dev, SD_BDLPL, 0);
2352                 azx_sd_writel(azx_dev, SD_BDLPU, 0);
2353                 azx_sd_writel(azx_dev, SD_CTL, 0);
2354                 azx_dev->bufsize = 0;
2355                 azx_dev->period_bytes = 0;
2356                 azx_dev->format_val = 0;
2357         }
2358
2359         snd_hda_codec_cleanup(apcm->codec, hinfo, substream);
2360
2361         mark_runtime_wc(chip, azx_dev, substream, false);
2362         azx_dev->prepared = 0;
2363         dsp_unlock(azx_dev);
2364         return snd_pcm_lib_free_pages(substream);
2365 }
2366
2367 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
2368 {
2369         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2370         struct azx *chip = apcm->chip;
2371         struct azx_dev *azx_dev = get_azx_dev(substream);
2372         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
2373         struct snd_pcm_runtime *runtime = substream->runtime;
2374         unsigned int bufsize, period_bytes, format_val, stream_tag;
2375         int err;
2376         struct hda_spdif_out *spdif =
2377                 snd_hda_spdif_out_of_nid(apcm->codec, hinfo->nid);
2378         unsigned short ctls = spdif ? spdif->ctls : 0;
2379
2380         dsp_lock(azx_dev);
2381         if (dsp_is_locked(azx_dev)) {
2382                 err = -EBUSY;
2383                 goto unlock;
2384         }
2385
2386         azx_stream_reset(chip, azx_dev);
2387         format_val = snd_hda_calc_stream_format(runtime->rate,
2388                                                 runtime->channels,
2389                                                 runtime->format,
2390                                                 hinfo->maxbps,
2391                                                 ctls);
2392         if (!format_val) {
2393                 snd_printk(KERN_ERR SFX
2394                            "%s: invalid format_val, rate=%d, ch=%d, format=%d\n",
2395                            azx_name(chip), runtime->rate, runtime->channels, runtime->format);
2396                 err = -EINVAL;
2397                 goto unlock;
2398         }
2399
2400         bufsize = snd_pcm_lib_buffer_bytes(substream);
2401         period_bytes = snd_pcm_lib_period_bytes(substream);
2402
2403         snd_printdd(SFX "%s: azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
2404                     azx_name(chip), bufsize, format_val);
2405
2406         if (bufsize != azx_dev->bufsize ||
2407             period_bytes != azx_dev->period_bytes ||
2408             format_val != azx_dev->format_val ||
2409             runtime->no_period_wakeup != azx_dev->no_period_wakeup) {
2410                 azx_dev->bufsize = bufsize;
2411                 azx_dev->period_bytes = period_bytes;
2412                 azx_dev->format_val = format_val;
2413                 azx_dev->no_period_wakeup = runtime->no_period_wakeup;
2414                 err = azx_setup_periods(chip, substream, azx_dev);
2415                 if (err < 0)
2416                         goto unlock;
2417         }
2418
2419         /* wallclk has 24Mhz clock source */
2420         azx_dev->period_wallclk = (((runtime->period_size * 24000) /
2421                                                 runtime->rate) * 1000);
2422         azx_setup_controller(chip, azx_dev);
2423         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
2424                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
2425         else
2426                 azx_dev->fifo_size = 0;
2427
2428         stream_tag = azx_dev->stream_tag;
2429         /* CA-IBG chips need the playback stream starting from 1 */
2430         if ((chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND) &&
2431             stream_tag > chip->capture_streams)
2432                 stream_tag -= chip->capture_streams;
2433         err = snd_hda_codec_prepare(apcm->codec, hinfo, stream_tag,
2434                                      azx_dev->format_val, substream);
2435
2436  unlock:
2437         if (!err)
2438                 azx_dev->prepared = 1;
2439         dsp_unlock(azx_dev);
2440         return err;
2441 }
2442
2443 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
2444 {
2445         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2446         struct azx *chip = apcm->chip;
2447         struct azx_dev *azx_dev;
2448         struct snd_pcm_substream *s;
2449         int rstart = 0, start, nsync = 0, sbits = 0;
2450         int nwait, timeout;
2451
2452         azx_dev = get_azx_dev(substream);
2453         trace_azx_pcm_trigger(chip, azx_dev, cmd);
2454
2455         if (dsp_is_locked(azx_dev) || !azx_dev->prepared)
2456                 return -EPIPE;
2457
2458         switch (cmd) {
2459         case SNDRV_PCM_TRIGGER_START:
2460                 rstart = 1;
2461         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
2462         case SNDRV_PCM_TRIGGER_RESUME:
2463                 start = 1;
2464                 break;
2465         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
2466         case SNDRV_PCM_TRIGGER_SUSPEND:
2467         case SNDRV_PCM_TRIGGER_STOP:
2468                 start = 0;
2469                 break;
2470         default:
2471                 return -EINVAL;
2472         }
2473
2474         snd_pcm_group_for_each_entry(s, substream) {
2475                 if (s->pcm->card != substream->pcm->card)
2476                         continue;
2477                 azx_dev = get_azx_dev(s);
2478                 sbits |= 1 << azx_dev->index;
2479                 nsync++;
2480                 snd_pcm_trigger_done(s, substream);
2481         }
2482
2483         spin_lock(&chip->reg_lock);
2484
2485         /* first, set SYNC bits of corresponding streams */
2486         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2487                 azx_writel(chip, OLD_SSYNC,
2488                         azx_readl(chip, OLD_SSYNC) | sbits);
2489         else
2490                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) | sbits);
2491
2492         snd_pcm_group_for_each_entry(s, substream) {
2493                 if (s->pcm->card != substream->pcm->card)
2494                         continue;
2495                 azx_dev = get_azx_dev(s);
2496                 if (start) {
2497                         azx_dev->start_wallclk = azx_readl(chip, WALLCLK);
2498                         if (!rstart)
2499                                 azx_dev->start_wallclk -=
2500                                                 azx_dev->period_wallclk;
2501                         azx_stream_start(chip, azx_dev);
2502                 } else {
2503                         azx_stream_stop(chip, azx_dev);
2504                 }
2505                 azx_dev->running = start;
2506         }
2507         spin_unlock(&chip->reg_lock);
2508         if (start) {
2509                 /* wait until all FIFOs get ready */
2510                 for (timeout = 5000; timeout; timeout--) {
2511                         nwait = 0;
2512                         snd_pcm_group_for_each_entry(s, substream) {
2513                                 if (s->pcm->card != substream->pcm->card)
2514                                         continue;
2515                                 azx_dev = get_azx_dev(s);
2516                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
2517                                       SD_STS_FIFO_READY))
2518                                         nwait++;
2519                         }
2520                         if (!nwait)
2521                                 break;
2522                         cpu_relax();
2523                 }
2524         } else {
2525                 /* wait until all RUN bits are cleared */
2526                 for (timeout = 5000; timeout; timeout--) {
2527                         nwait = 0;
2528                         snd_pcm_group_for_each_entry(s, substream) {
2529                                 if (s->pcm->card != substream->pcm->card)
2530                                         continue;
2531                                 azx_dev = get_azx_dev(s);
2532                                 if (azx_sd_readb(azx_dev, SD_CTL) &
2533                                     SD_CTL_DMA_START)
2534                                         nwait++;
2535                         }
2536                         if (!nwait)
2537                                 break;
2538                         cpu_relax();
2539                 }
2540         }
2541         spin_lock(&chip->reg_lock);
2542         /* reset SYNC bits */
2543         if (chip->driver_caps & AZX_DCAPS_OLD_SSYNC)
2544                 azx_writel(chip, OLD_SSYNC,
2545                         azx_readl(chip, OLD_SSYNC) & ~sbits);
2546         else
2547                 azx_writel(chip, SSYNC, azx_readl(chip, SSYNC) & ~sbits);
2548         if (start) {
2549                 azx_timecounter_init(substream, 0, 0);
2550                 if (nsync > 1) {
2551                         cycle_t cycle_last;
2552
2553                         /* same start cycle for master and group */
2554                         azx_dev = get_azx_dev(substream);
2555                         cycle_last = azx_dev->azx_tc.cycle_last;
2556
2557                         snd_pcm_group_for_each_entry(s, substream) {
2558                                 if (s->pcm->card != substream->pcm->card)
2559                                         continue;
2560                                 azx_timecounter_init(s, 1, cycle_last);
2561                         }
2562                 }
2563         }
2564         spin_unlock(&chip->reg_lock);
2565         return 0;
2566 }
2567
2568 /* get the current DMA position with correction on VIA chips */
2569 static unsigned int azx_via_get_position(struct azx *chip,
2570                                          struct azx_dev *azx_dev)
2571 {
2572         unsigned int link_pos, mini_pos, bound_pos;
2573         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
2574         unsigned int fifo_size;
2575
2576         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
2577         if (azx_dev->substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
2578                 /* Playback, no problem using link position */
2579                 return link_pos;
2580         }
2581
2582         /* Capture */
2583         /* For new chipset,
2584          * use mod to get the DMA position just like old chipset
2585          */
2586         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
2587         mod_dma_pos %= azx_dev->period_bytes;
2588
2589         /* azx_dev->fifo_size can't get FIFO size of in stream.
2590          * Get from base address + offset.
2591          */
2592         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
2593
2594         if (azx_dev->insufficient) {
2595                 /* Link position never gather than FIFO size */
2596                 if (link_pos <= fifo_size)
2597                         return 0;
2598
2599                 azx_dev->insufficient = 0;
2600         }
2601
2602         if (link_pos <= fifo_size)
2603                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
2604         else
2605                 mini_pos = link_pos - fifo_size;
2606
2607         /* Find nearest previous boudary */
2608         mod_mini_pos = mini_pos % azx_dev->period_bytes;
2609         mod_link_pos = link_pos % azx_dev->period_bytes;
2610         if (mod_link_pos >= fifo_size)
2611                 bound_pos = link_pos - mod_link_pos;
2612         else if (mod_dma_pos >= mod_mini_pos)
2613                 bound_pos = mini_pos - mod_mini_pos;
2614         else {
2615                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
2616                 if (bound_pos >= azx_dev->bufsize)
2617                         bound_pos = 0;
2618         }
2619
2620         /* Calculate real DMA position we want */
2621         return bound_pos + mod_dma_pos;
2622 }
2623
2624 static unsigned int azx_get_position(struct azx *chip,
2625                                      struct azx_dev *azx_dev,
2626                                      bool with_check)
2627 {
2628         struct snd_pcm_substream *substream = azx_dev->substream;
2629         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2630         unsigned int pos;
2631         int stream = substream->stream;
2632         struct hda_pcm_stream *hinfo = apcm->hinfo[stream];
2633         int delay = 0;
2634
2635         switch (chip->position_fix[stream]) {
2636         case POS_FIX_LPIB:
2637                 /* read LPIB */
2638                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2639                 break;
2640         case POS_FIX_VIACOMBO:
2641                 pos = azx_via_get_position(chip, azx_dev);
2642                 break;
2643         default:
2644                 /* use the position buffer */
2645                 pos = le32_to_cpu(*azx_dev->posbuf);
2646                 if (with_check && chip->position_fix[stream] == POS_FIX_AUTO) {
2647                         if (!pos || pos == (u32)-1) {
2648                                 printk(KERN_WARNING
2649                                        "hda-intel: Invalid position buffer, "
2650                                        "using LPIB read method instead.\n");
2651                                 chip->position_fix[stream] = POS_FIX_LPIB;
2652                                 pos = azx_sd_readl(azx_dev, SD_LPIB);
2653                         } else
2654                                 chip->position_fix[stream] = POS_FIX_POSBUF;
2655                 }
2656                 break;
2657         }
2658
2659         if (pos >= azx_dev->bufsize)
2660                 pos = 0;
2661
2662         /* calculate runtime delay from LPIB */
2663         if (substream->runtime &&
2664             chip->position_fix[stream] == POS_FIX_POSBUF &&
2665             (chip->driver_caps & AZX_DCAPS_COUNT_LPIB_DELAY)) {
2666                 unsigned int lpib_pos = azx_sd_readl(azx_dev, SD_LPIB);
2667                 if (stream == SNDRV_PCM_STREAM_PLAYBACK)
2668                         delay = pos - lpib_pos;
2669                 else
2670                         delay = lpib_pos - pos;
2671                 if (delay < 0)
2672                         delay += azx_dev->bufsize;
2673                 if (delay >= azx_dev->period_bytes) {
2674                         snd_printk(KERN_WARNING SFX
2675                                    "%s: Unstable LPIB (%d >= %d); "
2676                                    "disabling LPIB delay counting\n",
2677                                    azx_name(chip), delay, azx_dev->period_bytes);
2678                         delay = 0;
2679                         chip->driver_caps &= ~AZX_DCAPS_COUNT_LPIB_DELAY;
2680                 }
2681                 delay = bytes_to_frames(substream->runtime, delay);
2682         }
2683
2684         if (substream->runtime) {
2685                 if (hinfo->ops.get_delay)
2686                         delay += hinfo->ops.get_delay(hinfo, apcm->codec,
2687                                                       substream);
2688                 substream->runtime->delay = delay;
2689         }
2690
2691         trace_azx_get_position(chip, azx_dev, pos, delay);
2692         return pos;
2693 }
2694
2695 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
2696 {
2697         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2698         struct azx *chip = apcm->chip;
2699         struct azx_dev *azx_dev = get_azx_dev(substream);
2700         return bytes_to_frames(substream->runtime,
2701                                azx_get_position(chip, azx_dev, false));
2702 }
2703
2704 /*
2705  * Check whether the current DMA position is acceptable for updating
2706  * periods.  Returns non-zero if it's OK.
2707  *
2708  * Many HD-audio controllers appear pretty inaccurate about
2709  * the update-IRQ timing.  The IRQ is issued before actually the
2710  * data is processed.  So, we need to process it afterwords in a
2711  * workqueue.
2712  */
2713 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
2714 {
2715         u32 wallclk;
2716         unsigned int pos;
2717
2718         wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
2719         if (wallclk < (azx_dev->period_wallclk * 2) / 3)
2720                 return -1;      /* bogus (too early) interrupt */
2721
2722         pos = azx_get_position(chip, azx_dev, true);
2723
2724         if (WARN_ONCE(!azx_dev->period_bytes,
2725                       "hda-intel: zero azx_dev->period_bytes"))
2726                 return -1; /* this shouldn't happen! */
2727         if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
2728             pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
2729                 /* NG - it's below the first next period boundary */
2730                 return bdl_pos_adj[chip->dev_index] ? 0 : -1;
2731         azx_dev->start_wallclk += wallclk;
2732         return 1; /* OK, it's fine */
2733 }
2734
2735 /*
2736  * The work for pending PCM period updates.
2737  */
2738 static void azx_irq_pending_work(struct work_struct *work)
2739 {
2740         struct azx *chip = container_of(work, struct azx, irq_pending_work);
2741         int i, pending, ok;
2742
2743         if (!chip->irq_pending_warned) {
2744                 printk(KERN_WARNING
2745                        "hda-intel: IRQ timing workaround is activated "
2746                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
2747                        chip->card->number);
2748                 chip->irq_pending_warned = 1;
2749         }
2750
2751         for (;;) {
2752                 pending = 0;
2753                 spin_lock_irq(&chip->reg_lock);
2754                 for (i = 0; i < chip->num_streams; i++) {
2755                         struct azx_dev *azx_dev = &chip->azx_dev[i];
2756                         if (!azx_dev->irq_pending ||
2757                             !azx_dev->substream ||
2758                             !azx_dev->running)
2759                                 continue;
2760                         ok = azx_position_ok(chip, azx_dev);
2761                         if (ok > 0) {
2762                                 azx_dev->irq_pending = 0;
2763                                 spin_unlock(&chip->reg_lock);
2764                                 snd_pcm_period_elapsed(azx_dev->substream);
2765                                 spin_lock(&chip->reg_lock);
2766                         } else if (ok < 0) {
2767                                 pending = 0;    /* too early */
2768                         } else
2769                                 pending++;
2770                 }
2771                 spin_unlock_irq(&chip->reg_lock);
2772                 if (!pending)
2773                         return;
2774                 msleep(1);
2775         }
2776 }
2777
2778 /* clear irq_pending flags and assure no on-going workq */
2779 static void azx_clear_irq_pending(struct azx *chip)
2780 {
2781         int i;
2782
2783         spin_lock_irq(&chip->reg_lock);
2784         for (i = 0; i < chip->num_streams; i++)
2785                 chip->azx_dev[i].irq_pending = 0;
2786         spin_unlock_irq(&chip->reg_lock);
2787 }
2788
2789 #ifdef CONFIG_X86
2790 static int azx_pcm_mmap(struct snd_pcm_substream *substream,
2791                         struct vm_area_struct *area)
2792 {
2793         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2794         struct azx *chip = apcm->chip;
2795         if (!azx_snoop(chip))
2796                 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2797         return snd_pcm_lib_default_mmap(substream, area);
2798 }
2799 #else
2800 #define azx_pcm_mmap    NULL
2801 #endif
2802
2803 static struct snd_pcm_ops azx_pcm_ops = {
2804         .open = azx_pcm_open,
2805         .close = azx_pcm_close,
2806         .ioctl = snd_pcm_lib_ioctl,
2807         .hw_params = azx_pcm_hw_params,
2808         .hw_free = azx_pcm_hw_free,
2809         .prepare = azx_pcm_prepare,
2810         .trigger = azx_pcm_trigger,
2811         .pointer = azx_pcm_pointer,
2812         .wall_clock =  azx_get_wallclock_tstamp,
2813         .mmap = azx_pcm_mmap,
2814         .page = snd_pcm_sgbuf_ops_page,
2815 };
2816
2817 static void azx_pcm_free(struct snd_pcm *pcm)
2818 {
2819         struct azx_pcm *apcm = pcm->private_data;
2820         if (apcm) {
2821                 list_del(&apcm->list);
2822                 kfree(apcm);
2823         }
2824 }
2825
2826 #define MAX_PREALLOC_SIZE       (32 * 1024 * 1024)
2827
2828 static int
2829 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
2830                       struct hda_pcm *cpcm)
2831 {
2832         struct azx *chip = bus->private_data;
2833         struct snd_pcm *pcm;
2834         struct azx_pcm *apcm;
2835         int pcm_dev = cpcm->device;
2836         unsigned int size;
2837         int s, err;
2838
2839         list_for_each_entry(apcm, &chip->pcm_list, list) {
2840                 if (apcm->pcm->device == pcm_dev) {
2841                         snd_printk(KERN_ERR SFX "%s: PCM %d already exists\n",
2842                                    azx_name(chip), pcm_dev);
2843                         return -EBUSY;
2844                 }
2845         }
2846         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2847                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2848                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2849                           &pcm);
2850         if (err < 0)
2851                 return err;
2852         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2853         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2854         if (apcm == NULL)
2855                 return -ENOMEM;
2856         apcm->chip = chip;
2857         apcm->pcm = pcm;
2858         apcm->codec = codec;
2859         pcm->private_data = apcm;
2860         pcm->private_free = azx_pcm_free;
2861         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2862                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2863         list_add_tail(&apcm->list, &chip->pcm_list);
2864         cpcm->pcm = pcm;
2865         for (s = 0; s < 2; s++) {
2866                 apcm->hinfo[s] = &cpcm->stream[s];
2867                 if (cpcm->stream[s].substreams)
2868                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2869         }
2870         /* buffer pre-allocation */
2871         size = CONFIG_SND_HDA_PREALLOC_SIZE * 1024;
2872         if (size > MAX_PREALLOC_SIZE)
2873                 size = MAX_PREALLOC_SIZE;
2874 #ifdef CONFIG_SND_HDA_VPR
2875         chip->buf_size = size;
2876         for (s = 0; s < 2; s++) {
2877                 struct snd_pcm_substream *substream;
2878                 for (substream = pcm->streams[s].substream;
2879                      substream; substream = substream->next) {
2880
2881                         DEFINE_DMA_ATTRS(dmaattrs);
2882                         chip->dmaattrs = dmaattrs;
2883                         (void)dma_alloc_attrs(&tegra_vpr_dev,
2884                                 chip->buf_size, &chip->iova_addr,
2885                                 DMA_MEMORY_NOMAP, &chip->dmaattrs);
2886                         if (dma_mapping_error(&tegra_vpr_dev,
2887                                         chip->iova_addr)) {
2888                                 chip->iova_addr = 0;
2889                                 err = -ENOMEM;
2890                                 goto dma_alloc_fail;
2891                         }
2892                         snd_printk(KERN_DEBUG SFX
2893                                 "iova_addr=%pad\n", &chip->iova_addr);
2894                         substream->dma_buffer.area = NULL;
2895                         substream->dma_buffer.addr = chip->iova_addr;
2896                         substream->dma_buffer.bytes = size;
2897                         substream->dma_buffer.dev.dev = chip->dev;
2898                         if (substream->dma_buffer.bytes > 0)
2899                                 substream->buffer_bytes_max =
2900                                    substream->dma_buffer.bytes;
2901                         substream->dma_max = MAX_PREALLOC_SIZE;
2902                         continue;
2903 dma_alloc_fail:
2904                         return err;
2905                 }
2906         }
2907 #else
2908         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2909                                               chip->dev,
2910                                               size, MAX_PREALLOC_SIZE);
2911 #endif
2912         return 0;
2913 }
2914
2915 /*
2916  * mixer creation - all stuff is implemented in hda module
2917  */
2918 static int azx_mixer_create(struct azx *chip)
2919 {
2920         return snd_hda_build_controls(chip->bus);
2921 }
2922
2923
2924 /*
2925  * initialize SD streams
2926  */
2927 static int azx_init_stream(struct azx *chip)
2928 {
2929         int i;
2930
2931         /* initialize each stream (aka device)
2932          * assign the starting bdl address to each stream (device)
2933          * and initialize
2934          */
2935         for (i = 0; i < chip->num_streams; i++) {
2936                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2937                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2938                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2939                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2940                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2941                 azx_dev->sd_int_sta_mask = 1 << i;
2942                 /* stream tag: must be non-zero and unique */
2943                 azx_dev->index = i;
2944                 azx_dev->stream_tag = i + 1;
2945         }
2946
2947         return 0;
2948 }
2949
2950 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2951 {
2952         if (request_irq(chip->irq_id, azx_interrupt,
2953                         chip->msi ? 0 : IRQF_SHARED,
2954                         KBUILD_MODNAME, chip)) {
2955                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2956                        "disabling device\n", chip->irq_id);
2957                 if (do_disconnect)
2958                         snd_card_disconnect(chip->card);
2959                 return -1;
2960         }
2961         chip->irq = chip->irq_id;
2962         if (chip->pci)
2963                 pci_intx(chip->pci, !chip->msi);
2964
2965         return 0;
2966 }
2967
2968
2969 static void azx_stop_chip(struct azx *chip)
2970 {
2971         if (!chip->initialized)
2972                 return;
2973
2974         /* disable interrupts */
2975         azx_int_disable(chip);
2976         azx_int_clear(chip);
2977         synchronize_irq(chip->irq_id);
2978
2979         /* disable CORB/RIRB */
2980         azx_free_cmd_io(chip);
2981
2982         /* disable position buffer */
2983         azx_writel(chip, DPLBASE, 0);
2984         azx_writel(chip, DPUBASE, 0);
2985
2986         chip->initialized = 0;
2987 }
2988
2989 #ifdef CONFIG_SND_HDA_DSP_LOADER
2990 /*
2991  * DSP loading code (e.g. for CA0132)
2992  */
2993
2994 /* use the first stream for loading DSP */
2995 static struct azx_dev *
2996 azx_get_dsp_loader_dev(struct azx *chip)
2997 {
2998         return &chip->azx_dev[chip->playback_index_offset];
2999 }
3000
3001 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
3002                                 unsigned int byte_size,
3003                                 struct snd_dma_buffer *bufp)
3004 {
3005         u32 *bdl;
3006         struct azx *chip = bus->private_data;
3007         struct azx_dev *azx_dev;
3008         int err;
3009
3010         azx_dev = azx_get_dsp_loader_dev(chip);
3011
3012         dsp_lock(azx_dev);
3013         spin_lock_irq(&chip->reg_lock);
3014         if (azx_dev->running || azx_dev->locked) {
3015                 spin_unlock_irq(&chip->reg_lock);
3016                 err = -EBUSY;
3017                 goto unlock;
3018         }
3019         azx_dev->prepared = 0;
3020         chip->saved_azx_dev = *azx_dev;
3021         azx_dev->locked = 1;
3022         spin_unlock_irq(&chip->reg_lock);
3023
3024         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV_SG,
3025                                   snd_dma_pci_data(chip->pci),
3026                                   byte_size, bufp);
3027         if (err < 0)
3028                 goto err_alloc;
3029
3030         mark_pages_wc(chip, bufp, true);
3031         azx_dev->bufsize = byte_size;
3032         azx_dev->period_bytes = byte_size;
3033         azx_dev->format_val = format;
3034
3035         azx_stream_reset(chip, azx_dev);
3036
3037         /* reset BDL address */
3038         azx_sd_writel(azx_dev, SD_BDLPL, 0);
3039         azx_sd_writel(azx_dev, SD_BDLPU, 0);
3040
3041         azx_dev->frags = 0;
3042         bdl = (u32 *)azx_dev->bdl.area;
3043         err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
3044         if (err < 0)
3045                 goto error;
3046
3047         azx_setup_controller(chip, azx_dev);
3048         dsp_unlock(azx_dev);
3049         return azx_dev->stream_tag;
3050
3051  error:
3052         mark_pages_wc(chip, bufp, false);
3053         snd_dma_free_pages(bufp);
3054  err_alloc:
3055         spin_lock_irq(&chip->reg_lock);
3056         if (azx_dev->opened)
3057                 *azx_dev = chip->saved_azx_dev;
3058         azx_dev->locked = 0;
3059         spin_unlock_irq(&chip->reg_lock);
3060  unlock:
3061         dsp_unlock(azx_dev);
3062         return err;
3063 }
3064
3065 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
3066 {
3067         struct azx *chip = bus->private_data;
3068         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
3069
3070         if (start)
3071                 azx_stream_start(chip, azx_dev);
3072         else
3073                 azx_stream_stop(chip, azx_dev);
3074         azx_dev->running = start;
3075 }
3076
3077 static void azx_load_dsp_cleanup(struct hda_bus *bus,
3078                                  struct snd_dma_buffer *dmab)
3079 {
3080         struct azx *chip = bus->private_data;
3081         struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
3082
3083         if (!dmab->area || !azx_dev->locked)
3084                 return;
3085
3086         dsp_lock(azx_dev);
3087         /* reset BDL address */
3088         azx_sd_writel(azx_dev, SD_BDLPL, 0);
3089         azx_sd_writel(azx_dev, SD_BDLPU, 0);
3090         azx_sd_writel(azx_dev, SD_CTL, 0);
3091         azx_dev->bufsize = 0;
3092         azx_dev->period_bytes = 0;
3093         azx_dev->format_val = 0;
3094
3095         mark_pages_wc(chip, dmab, false);
3096         snd_dma_free_pages(dmab);
3097         dmab->area = NULL;
3098
3099         spin_lock_irq(&chip->reg_lock);
3100         if (azx_dev->opened)
3101                 *azx_dev = chip->saved_azx_dev;
3102         azx_dev->locked = 0;
3103         spin_unlock_irq(&chip->reg_lock);
3104         dsp_unlock(azx_dev);
3105 }
3106 #endif /* CONFIG_SND_HDA_DSP_LOADER */
3107
3108 #ifdef CONFIG_PM
3109 /* power-up/down the controller */
3110 static void azx_power_notify(struct hda_bus *bus, bool power_up)
3111 {
3112         struct azx *chip = bus->private_data;
3113
3114         if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3115                 return;
3116
3117         if (power_up)
3118                 pm_runtime_get_sync(chip->dev);
3119         else
3120                 pm_runtime_put_sync(chip->dev);
3121
3122 }
3123
3124 static DEFINE_MUTEX(card_list_lock);
3125 static LIST_HEAD(card_list);
3126
3127 static void azx_add_card_list(struct azx *chip)
3128 {
3129         mutex_lock(&card_list_lock);
3130         list_add(&chip->list, &card_list);
3131         mutex_unlock(&card_list_lock);
3132 }
3133
3134 static void azx_del_card_list(struct azx *chip)
3135 {
3136         mutex_lock(&card_list_lock);
3137         list_del_init(&chip->list);
3138         mutex_unlock(&card_list_lock);
3139 }
3140
3141 /* trigger power-save check at writing parameter */
3142 static int param_set_xint(const char *val, const struct kernel_param *kp)
3143 {
3144         struct azx *chip;
3145         struct hda_codec *c;
3146         int prev = power_save;
3147         int ret = param_set_int(val, kp);
3148
3149         if (ret || prev == power_save)
3150                 return ret;
3151
3152         mutex_lock(&card_list_lock);
3153         list_for_each_entry(chip, &card_list, list) {
3154                 if (!chip->bus || chip->disabled)
3155                         continue;
3156                 list_for_each_entry(c, &chip->bus->codec_list, list)
3157                         snd_hda_power_sync(c);
3158         }
3159         mutex_unlock(&card_list_lock);
3160         return 0;
3161 }
3162 #else
3163 #define azx_add_card_list(chip) /* NOP */
3164 #define azx_del_card_list(chip) /* NOP */
3165 #endif /* CONFIG_PM */
3166
3167 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
3168 /*
3169  * power management
3170  */
3171 static int azx_suspend(struct device *dev)
3172 {
3173         struct snd_card *card = dev_get_drvdata(dev);
3174         struct azx *chip = card->private_data;
3175         struct azx_pcm *p;
3176
3177         if (chip->disabled)
3178                 return 0;
3179
3180 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER)
3181         if (chip->pdev)
3182                 __azx_platform_enable_clocks(chip);
3183 #endif
3184
3185         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
3186         azx_clear_irq_pending(chip);
3187         list_for_each_entry(p, &chip->pcm_list, list)
3188                 snd_pcm_suspend_all(p->pcm);
3189         if (chip->initialized)
3190                 snd_hda_suspend(chip->bus);
3191         azx_stop_chip(chip);
3192         if (chip->irq >= 0) {
3193                 free_irq(chip->irq, chip);
3194                 chip->irq = -1;
3195         }
3196
3197         if (chip->pci) {
3198                 struct pci_dev *pci = to_pci_dev(dev);
3199
3200                 if (chip->msi)
3201                         pci_disable_msi(chip->pci);
3202                 pci_disable_device(pci);
3203                 pci_save_state(pci);
3204                 pci_set_power_state(pci, PCI_D3hot);
3205         }
3206
3207 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3208         if (chip->pdev) {
3209                 /* Disable all clk references */
3210                 while (chip->platform_clk_enable)
3211                         __azx_platform_disable_clocks(chip);
3212         }
3213 #endif
3214
3215         return 0;
3216 }
3217
3218 static int azx_resume(struct device *dev)
3219 {
3220         struct snd_card *card = dev_get_drvdata(dev);
3221         struct azx *chip = card->private_data;
3222
3223         if (chip->disabled)
3224                 return 0;
3225
3226 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3227         if (chip->pdev)
3228                 __azx_platform_enable_clocks(chip);
3229 #endif
3230
3231         if (chip->pci) {
3232                 pci_set_power_state(chip->pci, PCI_D0);
3233                 pci_restore_state(chip->pci);
3234                 if (pci_enable_device(chip->pci) < 0) {
3235                         printk(KERN_ERR "hda-intel: pci_enable_device failed, "
3236                                "disabling device\n");
3237                         snd_card_disconnect(card);
3238                         return -EIO;
3239                 }
3240                 pci_set_master(chip->pci);
3241                 if (chip->msi)
3242                         if (pci_enable_msi(chip->pci) < 0)
3243                                 chip->msi = 0;
3244         } else if (chip->pdev) {
3245                 pm_runtime_disable(chip->dev);
3246                 pm_runtime_set_active(chip->dev);
3247                 pm_runtime_get_noresume(chip->dev);
3248                 pm_runtime_enable(chip->dev);
3249         }
3250
3251         if (azx_acquire_irq(chip, 1) < 0)
3252                 return -EIO;
3253
3254         if (chip->pci)
3255                 azx_init_pci(chip);
3256
3257 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3258         if (chip->pdev)
3259                 azx_init_platform(chip);
3260 #endif
3261
3262         azx_init_chip(chip, 1);
3263
3264         snd_hda_resume(chip->bus);
3265         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
3266
3267 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3268         if (chip->pdev)
3269                 pm_runtime_put(chip->dev);
3270 #endif
3271
3272         return 0;
3273 }
3274 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
3275
3276 #ifdef CONFIG_PM_RUNTIME
3277 static int azx_runtime_suspend(struct device *dev)
3278 {
3279         struct snd_card *card = dev_get_drvdata(dev);
3280         struct azx *chip = card->private_data;
3281
3282         if (!power_save_controller ||
3283                 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3284                 return -EAGAIN;
3285
3286         azx_stop_chip(chip);
3287         azx_clear_irq_pending(chip);
3288
3289 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3290         if (chip->pdev)
3291                 __azx_platform_disable_clocks(chip);
3292 #endif
3293
3294         return 0;
3295 }
3296
3297 static int azx_runtime_resume(struct device *dev)
3298 {
3299         struct snd_card *card = dev_get_drvdata(dev);
3300         struct azx *chip = card->private_data;
3301
3302         if (chip->pci)
3303                 azx_init_pci(chip);
3304
3305 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3306         if (chip->pdev) {
3307                 __azx_platform_enable_clocks(chip);
3308                 azx_init_platform(chip);
3309         }
3310 #endif
3311         azx_init_chip(chip, 1);
3312         return 0;
3313 }
3314
3315 static int azx_runtime_idle(struct device *dev)
3316 {
3317         struct snd_card *card = dev_get_drvdata(dev);
3318         struct azx *chip = card->private_data;
3319
3320         if (!power_save_controller ||
3321             !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
3322                 return -EBUSY;
3323
3324         return 0;
3325 }
3326
3327 #endif /* CONFIG_PM_RUNTIME */
3328
3329 #ifdef CONFIG_PM
3330 static const struct dev_pm_ops azx_pm = {
3331         SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
3332         SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
3333 };
3334
3335 #define AZX_PM_OPS      &azx_pm
3336 #else
3337 #define AZX_PM_OPS      NULL
3338 #endif /* CONFIG_PM */
3339
3340
3341 /*
3342  * reboot notifier for hang-up problem at power-down
3343  */
3344 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
3345 {
3346         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
3347
3348 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER)
3349         if (chip->pdev)
3350                 azx_platform_enable_clocks(chip);
3351 #endif
3352
3353         snd_hda_bus_reboot_notify(chip->bus);
3354         azx_stop_chip(chip);
3355
3356 #if defined(CONFIG_SND_HDA_PLATFORM_DRIVER)
3357         if (chip->pdev)
3358                 azx_platform_disable_clocks(chip);
3359 #endif
3360
3361         return NOTIFY_OK;
3362 }
3363
3364 static void azx_notifier_register(struct azx *chip)
3365 {
3366         chip->reboot_notifier.notifier_call = azx_halt;
3367         register_reboot_notifier(&chip->reboot_notifier);
3368 }
3369
3370 static void azx_notifier_unregister(struct azx *chip)
3371 {
3372         if (chip->reboot_notifier.notifier_call)
3373                 unregister_reboot_notifier(&chip->reboot_notifier);
3374 }
3375
3376 static int azx_first_init(struct azx *chip);
3377 static int azx_probe_continue(struct azx *chip);
3378
3379 #ifdef SUPPORT_VGA_SWITCHEROO
3380 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
3381
3382 static void azx_vs_set_state(struct pci_dev *pci,
3383                              enum vga_switcheroo_state state)
3384 {
3385         struct snd_card *card = pci_get_drvdata(pci);
3386         struct azx *chip = card->private_data;
3387         bool disabled;
3388
3389         wait_for_completion(&chip->probe_wait);
3390         if (chip->init_failed)
3391                 return;
3392
3393         disabled = (state == VGA_SWITCHEROO_OFF);
3394         if (chip->disabled == disabled)
3395                 return;
3396
3397         if (!chip->bus) {
3398                 chip->disabled = disabled;
3399                 if (!disabled) {
3400                         snd_printk(KERN_INFO SFX
3401                                    "%s: Start delayed initialization\n",
3402                                    azx_name(chip));
3403                         if (azx_first_init(chip) < 0 ||
3404                             azx_probe_continue(chip) < 0) {
3405                                 snd_printk(KERN_ERR SFX
3406                                            "%s: initialization error\n",
3407                                            azx_name(chip));
3408                                 chip->init_failed = true;
3409                         }
3410                 }
3411         } else {
3412                 snd_printk(KERN_INFO SFX
3413                            "%s: %s via VGA-switcheroo\n", azx_name(chip),
3414                            disabled ? "Disabling" : "Enabling");
3415                 if (disabled) {
3416                         azx_suspend(&pci->dev);
3417                         chip->disabled = true;
3418                         if (snd_hda_lock_devices(chip->bus))
3419                                 snd_printk(KERN_WARNING SFX "%s: Cannot lock devices!\n",
3420                                            azx_name(chip));
3421                 } else {
3422                         snd_hda_unlock_devices(chip->bus);
3423                         chip->disabled = false;
3424                         azx_resume(&pci->dev);
3425                 }
3426         }
3427 }
3428
3429 static bool azx_vs_can_switch(struct pci_dev *pci)
3430 {
3431         struct snd_card *card = pci_get_drvdata(pci);
3432         struct azx *chip = card->private_data;
3433
3434         wait_for_completion(&chip->probe_wait);
3435         if (chip->init_failed)
3436                 return false;
3437         if (chip->disabled || !chip->bus)
3438                 return true;
3439         if (snd_hda_lock_devices(chip->bus))
3440                 return false;
3441         snd_hda_unlock_devices(chip->bus);
3442         return true;
3443 }
3444
3445 static void init_vga_switcheroo(struct azx *chip)
3446 {
3447         struct pci_dev *p = get_bound_vga(chip->pci);
3448         if (p) {
3449                 snd_printk(KERN_INFO SFX
3450                            "%s: Handle VGA-switcheroo audio client\n",
3451                            azx_name(chip));
3452                 chip->use_vga_switcheroo = 1;
3453                 pci_dev_put(p);
3454         }
3455 }
3456
3457 static const struct vga_switcheroo_client_ops azx_vs_ops = {
3458         .set_gpu_state = azx_vs_set_state,
3459         .can_switch = azx_vs_can_switch,
3460 };
3461
3462 static int register_vga_switcheroo(struct azx *chip)
3463 {
3464         int err;
3465
3466         if (!chip->use_vga_switcheroo)
3467                 return 0;
3468         /* FIXME: currently only handling DIS controller
3469          * is there any machine with two switchable HDMI audio controllers?
3470          */
3471         err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
3472                                                     VGA_SWITCHEROO_DIS,
3473                                                     chip->bus != NULL);
3474         if (err < 0)
3475                 return err;
3476         chip->vga_switcheroo_registered = 1;
3477         return 0;
3478 }
3479 #else
3480 #define init_vga_switcheroo(chip)               /* NOP */
3481 #define register_vga_switcheroo(chip)           0
3482 #define check_hdmi_disabled(pci)        false
3483 #endif /* SUPPORT_VGA_SWITCHER */
3484
3485 /*
3486  * destructor
3487  */
3488 static int azx_free(struct azx *chip)
3489 {
3490         int i;
3491
3492         azx_del_card_list(chip);
3493
3494         azx_notifier_unregister(chip);
3495
3496         chip->init_failed = 1; /* to be sure */
3497         complete_all(&chip->probe_wait);
3498
3499         if (use_vga_switcheroo(chip)) {
3500                 if (chip->disabled && chip->bus)
3501                         snd_hda_unlock_devices(chip->bus);
3502                 if (chip->vga_switcheroo_registered)
3503                         vga_switcheroo_unregister_client(chip->pci);
3504         }
3505
3506         if (chip->initialized) {
3507                 azx_clear_irq_pending(chip);
3508                 for (i = 0; i < chip->num_streams; i++)
3509                         azx_stream_stop(chip, &chip->azx_dev[i]);
3510                 azx_stop_chip(chip);
3511         }
3512
3513 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3514         azx_platform_disable_clocks(chip);
3515         for (i = 0; i < chip->platform_clk_count; i++)
3516                 clk_put(chip->platform_clks[i]);
3517 #endif
3518
3519         if (chip->irq >= 0)
3520                 free_irq(chip->irq, (void*)chip);
3521         if (chip->pci && chip->msi)
3522                 pci_disable_msi(chip->pci);
3523         if (chip->remap_addr) {
3524                 void __iomem *addr2unmap;
3525                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
3526                         addr2unmap = chip->remap_config_addr;
3527                 } else {
3528                         addr2unmap = chip->remap_addr;
3529                 }
3530                 iounmap(addr2unmap);
3531         }
3532
3533
3534         if (chip->azx_dev) {
3535                 for (i = 0; i < chip->num_streams; i++)
3536                         if (chip->azx_dev[i].bdl.area) {
3537                                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, false);
3538                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
3539                         }
3540         }
3541         if (chip->rb.area) {
3542                 mark_pages_wc(chip, &chip->rb, false);
3543                 snd_dma_free_pages(&chip->rb);
3544         }
3545         if (chip->posbuf.area) {
3546                 mark_pages_wc(chip, &chip->posbuf, false);
3547                 snd_dma_free_pages(&chip->posbuf);
3548         }
3549         if (chip->pci) {
3550                 if (chip->region_requested)
3551                         pci_release_regions(chip->pci);
3552                 pci_disable_device(chip->pci);
3553         }
3554         kfree(chip->azx_dev);
3555 #ifdef CONFIG_SND_HDA_PATCH_LOADER
3556         if (chip->fw)
3557                 release_firmware(chip->fw);
3558 #endif
3559         kfree(chip);
3560 #ifdef CONFIG_SND_HDA_VPR
3561         if (chip->iova_addr) {
3562                 dma_free_attrs(&tegra_vpr_dev, chip->buf_size,
3563                                 (void *)(uintptr_t)chip->iova_addr,
3564                                 chip->iova_addr, &chip->dmaattrs);
3565         }
3566 #endif
3567
3568         return 0;
3569 }
3570
3571 static int azx_dev_free(struct snd_device *device)
3572 {
3573         return azx_free(device->device_data);
3574 }
3575
3576 #ifdef SUPPORT_VGA_SWITCHEROO
3577 /*
3578  * Check of disabled HDMI controller by vga-switcheroo
3579  */
3580 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
3581 {
3582         struct pci_dev *p;
3583
3584         /* check only discrete GPU */
3585         switch (pci->vendor) {
3586         case PCI_VENDOR_ID_ATI:
3587         case PCI_VENDOR_ID_AMD:
3588         case PCI_VENDOR_ID_NVIDIA:
3589                 if (pci->devfn == 1) {
3590                         p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
3591                                                         pci->bus->number, 0);
3592                         if (p) {
3593                                 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
3594                                         return p;
3595                                 pci_dev_put(p);
3596                         }
3597                 }
3598                 break;
3599         }
3600         return NULL;
3601 }
3602
3603 static bool check_hdmi_disabled(struct pci_dev *pci)
3604 {
3605         bool vga_inactive = false;
3606         struct pci_dev *p = get_bound_vga(pci);
3607
3608         if (p) {
3609                 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
3610                         vga_inactive = true;
3611                 pci_dev_put(p);
3612         }
3613         return vga_inactive;
3614 }
3615 #endif /* SUPPORT_VGA_SWITCHEROO */
3616
3617 /*
3618  * white/black-listing for position_fix
3619  */
3620 static struct snd_pci_quirk position_fix_list[] = {
3621         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
3622         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
3623         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
3624         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
3625         SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
3626         SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
3627         SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
3628         SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
3629         SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
3630         SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
3631         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
3632         SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
3633         SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
3634         SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
3635         {}
3636 };
3637
3638 static int check_position_fix(struct azx *chip, int fix)
3639 {
3640         const struct snd_pci_quirk *q;
3641
3642         switch (fix) {
3643         case POS_FIX_AUTO:
3644         case POS_FIX_LPIB:
3645         case POS_FIX_POSBUF:
3646         case POS_FIX_VIACOMBO:
3647         case POS_FIX_COMBO:
3648                 return fix;
3649         }
3650
3651         if (chip->pci) {
3652                 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
3653                 if (q) {
3654                         printk(KERN_INFO
3655                                "hda_intel: position_fix set to %d "
3656                                "for device %04x:%04x\n",
3657                                q->value, q->subvendor, q->subdevice);
3658                         return q->value;
3659                 }
3660         }
3661
3662         /* Check VIA/ATI HD Audio Controller exist */
3663         if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
3664                 snd_printd(SFX "%s: Using VIACOMBO position fix\n", azx_name(chip));
3665                 return POS_FIX_VIACOMBO;
3666         }
3667         if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
3668                 snd_printd(SFX "%s: Using LPIB position fix\n", azx_name(chip));
3669                 return POS_FIX_LPIB;
3670         }
3671         return POS_FIX_AUTO;
3672 }
3673
3674 /*
3675  * black-lists for probe_mask
3676  */
3677 static struct snd_pci_quirk probe_mask_list[] = {
3678         /* Thinkpad often breaks the controller communication when accessing
3679          * to the non-working (or non-existing) modem codec slot.
3680          */
3681         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
3682         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
3683         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
3684         /* broken BIOS */
3685         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
3686         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
3687         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
3688         /* forced codec slots */
3689         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
3690         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
3691         /* WinFast VP200 H (Teradici) user reported broken communication */
3692         SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
3693         {}
3694 };
3695
3696 #define AZX_FORCE_CODEC_MASK    0x100
3697
3698 static void check_probe_mask(struct azx *chip, int dev)
3699 {
3700         const struct snd_pci_quirk *q;
3701
3702         chip->codec_probe_mask = probe_mask[dev];
3703         if (chip->pci && (chip->codec_probe_mask == -1)) {
3704                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
3705                 if (q) {
3706                         printk(KERN_INFO
3707                                "hda_intel: probe_mask set to 0x%x "
3708                                "for device %04x:%04x\n",
3709                                q->value, q->subvendor, q->subdevice);
3710                         chip->codec_probe_mask = q->value;
3711                 }
3712         }
3713
3714         /* check forced option */
3715         if (chip->codec_probe_mask != -1 &&
3716             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
3717                 chip->codec_mask = chip->codec_probe_mask & 0xff;
3718                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
3719                        chip->codec_mask);
3720         }
3721 }
3722
3723 /*
3724  * white/black-list for enable_msi
3725  */
3726 static struct snd_pci_quirk msi_black_list[] = {
3727         SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
3728         SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
3729         SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
3730         SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
3731         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
3732         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
3733         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
3734         SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
3735         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
3736         SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
3737         {}
3738 };
3739
3740 static void check_msi(struct azx *chip)
3741 {
3742         const struct snd_pci_quirk *q;
3743
3744         /* Disable MSI if chip is not a pci device */
3745         if (!chip->pci) {
3746                 chip->msi = 0;
3747                 return;
3748         }
3749
3750         if (enable_msi >= 0) {
3751                 chip->msi = !!enable_msi;
3752                 return;
3753         }
3754         chip->msi = 1;  /* enable MSI as default */
3755         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
3756         if (q) {
3757                 printk(KERN_INFO
3758                        "hda_intel: msi for device %04x:%04x set to %d\n",
3759                        q->subvendor, q->subdevice, q->value);
3760                 chip->msi = q->value;
3761                 return;
3762         }
3763
3764         /* NVidia chipsets seem to cause troubles with MSI */
3765         if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
3766                 printk(KERN_INFO "hda_intel: Disabling MSI\n");
3767                 chip->msi = 0;
3768         }
3769 }
3770
3771 /* check the snoop mode availability */
3772 static void azx_check_snoop_available(struct azx *chip)
3773 {
3774         bool snoop = chip->snoop;
3775
3776         switch (chip->driver_type) {
3777         case AZX_DRIVER_VIA:
3778                 /* force to non-snoop mode for a new VIA controller
3779                  * when BIOS is set
3780                  */
3781                 if (snoop) {
3782                         u8 val;
3783                         pci_read_config_byte(chip->pci, 0x42, &val);
3784                         if (!(val & 0x80) && chip->pci->revision == 0x30)
3785                                 snoop = false;
3786                 }
3787                 break;
3788         case AZX_DRIVER_ATIHDMI_NS:
3789                 /* new ATI HDMI requires non-snoop */
3790                 snoop = false;
3791                 break;
3792         case AZX_DRIVER_CTHDA:
3793                 snoop = false;
3794                 break;
3795         }
3796
3797         if (snoop != chip->snoop) {
3798                 snd_printk(KERN_INFO SFX "%s: Force to %s mode\n",
3799                            azx_name(chip), snoop ? "snoop" : "non-snoop");
3800                 chip->snoop = snoop;
3801         }
3802 }
3803
3804 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3805 static const char *tegra_clk_names[] = {
3806         "hda",
3807         "hda2codec",
3808         "hda2hdmi",
3809 };
3810 static struct clk *tegra_clks[ARRAY_SIZE(tegra_clk_names)];
3811 #endif
3812
3813 /*
3814  * constructor
3815  */
3816 static int azx_create(struct snd_card *card, struct pci_dev *pci,
3817                                 struct platform_device *pdev,
3818                                 int dev, unsigned int driver_caps,
3819                                 struct azx **rchip)
3820 {
3821         static struct snd_device_ops ops = {
3822                 .dev_free = azx_dev_free,
3823         };
3824         struct azx *chip;
3825         int err;
3826
3827         *rchip = NULL;
3828
3829         if (pci) {
3830                 err = pci_enable_device(pci);
3831                 if (err < 0)
3832                         return err;
3833         } else if (pdev) {
3834                 err = pm_runtime_set_active(&pdev->dev);
3835                 if (err < 0)
3836                         return err;
3837                 pm_runtime_get_noresume(&pdev->dev);
3838                 pm_runtime_enable(&pdev->dev);
3839         }
3840
3841         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
3842         if (!chip) {
3843                 if (pci) {
3844                         snd_printk(KERN_ERR SFX "%s: Cannot allocate chip\n", pci_name(pci));
3845                         pci_disable_device(pci);
3846                 } else
3847                         snd_printk(KERN_ERR SFX "Cannot allocate chip\n");
3848                 return -ENOMEM;
3849         }
3850
3851         spin_lock_init(&chip->reg_lock);
3852         mutex_init(&chip->open_mutex);
3853         chip->card = card;
3854         chip->pci = pci;
3855         chip->pdev = pdev;
3856         chip->dev = pci ? snd_dma_pci_data(pci) : &pdev->dev;
3857         chip->irq_id = pci ? pci->irq : platform_get_irq(pdev, 0);
3858         chip->irq = -1;
3859         chip->driver_caps = driver_caps;
3860         chip->driver_type = driver_caps & 0xff;
3861         check_msi(chip);
3862         chip->dev_index = dev;
3863         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
3864         INIT_LIST_HEAD(&chip->pcm_list);
3865         INIT_LIST_HEAD(&chip->list);
3866         init_vga_switcheroo(chip);
3867         init_completion(&chip->probe_wait);
3868
3869         chip->position_fix[0] = chip->position_fix[1] =
3870                 check_position_fix(chip, position_fix[dev]);
3871         /* combo mode uses LPIB for playback */
3872         if (chip->position_fix[0] == POS_FIX_COMBO) {
3873                 chip->position_fix[0] = POS_FIX_LPIB;
3874                 chip->position_fix[1] = POS_FIX_AUTO;
3875         }
3876
3877         check_probe_mask(chip, dev);
3878
3879         chip->single_cmd = single_cmd;
3880         chip->snoop = hda_snoop;
3881         azx_check_snoop_available(chip);
3882
3883         if (bdl_pos_adj[dev] < 0) {
3884                 switch (chip->driver_type) {
3885                 case AZX_DRIVER_ICH:
3886                 case AZX_DRIVER_PCH:
3887                         bdl_pos_adj[dev] = 1;
3888                         break;
3889                 default:
3890                         bdl_pos_adj[dev] = 32;
3891                         break;
3892                 }
3893         }
3894
3895         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
3896         if (err < 0) {
3897                 snd_printk(KERN_ERR SFX "%s: Error creating device [card]!\n",
3898                    azx_name(chip));
3899                 azx_free(chip);
3900                 return err;
3901         }
3902
3903         *rchip = chip;
3904
3905         return 0;
3906 }
3907
3908 static int azx_first_init(struct azx *chip)
3909 {
3910         int dev = chip->dev_index;
3911         struct pci_dev *pci = chip->pci;
3912         struct snd_card *card = chip->card;
3913         int i, err = 0;
3914         unsigned short gcap;
3915
3916 #if BITS_PER_LONG != 64
3917         /* Fix up base address on ULI M5461 */
3918         if (chip->driver_type == AZX_DRIVER_ULI) {
3919                 u16 tmp3;
3920                 pci_read_config_word(pci, 0x40, &tmp3);
3921                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
3922                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
3923         }
3924 #endif
3925
3926         if (chip->pci) {
3927                 err = pci_request_regions(pci, "ICH HD audio");
3928                 if (err < 0)
3929                         return err;
3930                 chip->region_requested = 1;
3931
3932                 chip->addr = pci_resource_start(pci, 0);
3933                 chip->remap_addr = pci_ioremap_bar(pci, 0);
3934                 if (chip->remap_addr == NULL) {
3935                         snd_printk(KERN_ERR SFX "%s: ioremap error\n", azx_name(chip));
3936                         return -ENXIO;
3937                 }
3938         }
3939
3940 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
3941         if (chip->pdev) {
3942                 struct resource *res, *region;
3943
3944                 /* Do platform specific initialization */
3945                 switch (chip->driver_type) {
3946 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3947                 case AZX_DRIVER_NVIDIA_TEGRA:
3948                         for (i = 0; i < ARRAY_SIZE(tegra_clk_names); i++) {
3949                                 tegra_clks[i] = clk_get(&chip->pdev->dev,
3950                                                         tegra_clk_names[i]);
3951                                 if (IS_ERR_OR_NULL(tegra_clks[i])) {
3952                                         return PTR_ERR(tegra_clks[i]);
3953                                 }
3954                         }
3955                         chip->platform_clk_count = ARRAY_SIZE(tegra_clk_names);
3956                         chip->platform_clks = tegra_clks;
3957                         break;
3958 #endif
3959                 default:
3960                         break;
3961                 }
3962
3963                 azx_platform_enable_clocks(chip);
3964
3965                 res = platform_get_resource(chip->pdev, IORESOURCE_MEM, 0);
3966                 if (res == NULL) {
3967                         return -EINVAL;
3968                 }
3969
3970                 region = devm_request_mem_region(chip->dev, res->start,
3971                                                  resource_size(res),
3972                                                  chip->pdev->name);
3973                 if (!region) {
3974                         snd_printk(KERN_ERR SFX "Mem region already claimed\n");
3975                         return -EINVAL;
3976                 }
3977
3978                 chip->addr = res->start;
3979                 chip->remap_addr = devm_ioremap(chip->dev,
3980                                                 res->start,
3981                                                 resource_size(res));
3982                 if (chip->remap_addr == NULL) {
3983                         snd_printk(KERN_ERR SFX "ioremap error\n");
3984                         return -ENXIO;
3985                 }
3986
3987 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
3988                 if (chip->driver_type == AZX_DRIVER_NVIDIA_TEGRA) {
3989                         chip->remap_config_addr = chip->remap_addr;
3990                         chip->remap_addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3991                         chip->addr += NVIDIA_TEGRA_HDA_BAR0_OFFSET;
3992                 }
3993 #endif
3994
3995                 azx_init_platform(chip);
3996         }
3997 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
3998
3999         if (azx_acquire_irq(chip, 0) < 0)
4000                 return -EBUSY;
4001
4002         if (chip->pci)
4003                 pci_set_master(pci);
4004
4005         synchronize_irq(chip->irq);
4006
4007         gcap = azx_readw(chip, GCAP);
4008         snd_printdd(SFX "%s: chipset global capabilities = 0x%x\n", azx_name(chip), gcap);
4009
4010         /* disable SB600 64bit support for safety */
4011         if (chip->pci && chip->pci->vendor == PCI_VENDOR_ID_ATI) {
4012                 struct pci_dev *p_smbus;
4013                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
4014                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
4015                                          NULL);
4016                 if (p_smbus) {
4017                         if (p_smbus->revision < 0x30)
4018                                 gcap &= ~ICH6_GCAP_64OK;
4019                         pci_dev_put(p_smbus);
4020                 }
4021         }
4022
4023         /* disable 64bit DMA address on some devices */
4024         if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
4025                 snd_printd(SFX "%s: Disabling 64bit DMA\n", azx_name(chip));
4026                 gcap &= ~ICH6_GCAP_64OK;
4027         }
4028
4029         /* disable buffer size rounding to 128-byte multiples if supported */
4030         if (align_buffer_size >= 0)
4031                 chip->align_buffer_size = !!align_buffer_size;
4032         else {
4033                 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
4034                         chip->align_buffer_size = 0;
4035                 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
4036                         chip->align_buffer_size = 1;
4037                 else
4038                         chip->align_buffer_size = 1;
4039         }
4040
4041         if (chip->pci) {
4042                 /* allow 64bit DMA address if supported by H/W */
4043                 if ((gcap & ICH6_GCAP_64OK) &&
4044                     !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
4045                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
4046                 else {
4047                         pci_set_dma_mask(pci, DMA_BIT_MASK(32));
4048                         pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
4049                 }
4050         }
4051
4052         /* read number of streams from GCAP register instead of using
4053          * hardcoded value
4054          */
4055         chip->capture_streams = (gcap >> 8) & 0x0f;
4056         chip->playback_streams = (gcap >> 12) & 0x0f;
4057         if (!chip->playback_streams && !chip->capture_streams) {
4058                 /* gcap didn't give any info, switching to old method */
4059
4060                 switch (chip->driver_type) {
4061                 case AZX_DRIVER_ULI:
4062                         chip->playback_streams = ULI_NUM_PLAYBACK;
4063                         chip->capture_streams = ULI_NUM_CAPTURE;
4064                         break;
4065                 case AZX_DRIVER_ATIHDMI:
4066                 case AZX_DRIVER_ATIHDMI_NS:
4067                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
4068                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
4069                         break;
4070                 case AZX_DRIVER_GENERIC:
4071                 default:
4072                         chip->playback_streams = ICH6_NUM_PLAYBACK;
4073                         chip->capture_streams = ICH6_NUM_CAPTURE;
4074                         break;
4075                 }
4076         }
4077         chip->capture_index_offset = 0;
4078         chip->playback_index_offset = chip->capture_streams;
4079         chip->num_streams = chip->playback_streams + chip->capture_streams;
4080         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
4081                                 GFP_KERNEL);
4082         if (!chip->azx_dev) {
4083                 snd_printk(KERN_ERR SFX "%s: cannot malloc azx_dev\n", azx_name(chip));
4084                 return -ENOMEM;
4085         }
4086
4087         for (i = 0; i < chip->num_streams; i++) {
4088                 dsp_lock_init(&chip->azx_dev[i]);
4089                 /* allocate memory for the BDL for each stream */
4090                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
4091                                           chip->dev,
4092                                           BDL_SIZE, &chip->azx_dev[i].bdl);
4093                 if (err < 0) {
4094                         snd_printk(KERN_ERR SFX "%s: cannot allocate BDL\n", azx_name(chip));
4095                         return -ENOMEM;
4096                 }
4097                 mark_pages_wc(chip, &chip->azx_dev[i].bdl, true);
4098         }
4099         /* allocate memory for the position buffer */
4100         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
4101                                   chip->dev,
4102                                   chip->num_streams * 8, &chip->posbuf);
4103         if (err < 0) {
4104                 snd_printk(KERN_ERR SFX "%s: cannot allocate posbuf\n", azx_name(chip));
4105                 return -ENOMEM;
4106         }
4107         mark_pages_wc(chip, &chip->posbuf, true);
4108         /* allocate CORB/RIRB */
4109         err = azx_alloc_cmd_io(chip);
4110         if (err < 0)
4111                 return err;
4112
4113         /* initialize streams */
4114         azx_init_stream(chip);
4115
4116         /* initialize chip */
4117         if (chip->pci)
4118                 azx_init_pci(chip);
4119
4120 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4121         if (chip->pdev)
4122                 azx_init_platform(chip);
4123 #endif
4124         azx_init_chip(chip, (probe_only[dev] & 2) == 0);
4125
4126         /* codec detection */
4127         if (!chip->codec_mask) {
4128                 snd_printk(KERN_ERR SFX "%s: no codecs found!\n", azx_name(chip));
4129                 return -ENODEV;
4130         }
4131
4132         strcpy(card->driver, "HDA-Intel");
4133         strlcpy(card->shortname, driver_short_names[chip->driver_type],
4134                 sizeof(card->shortname));
4135         snprintf(card->longname, sizeof(card->longname),
4136                  "%s at 0x%lx irq %i",
4137                  card->shortname, chip->addr, chip->irq);
4138
4139         return 0;
4140 }
4141
4142 static void power_down_all_codecs(struct azx *chip)
4143 {
4144 #ifdef CONFIG_PM
4145         /* The codecs were powered up in snd_hda_codec_new().
4146          * Now all initialization done, so turn them down if possible
4147          */
4148         struct hda_codec *codec;
4149         list_for_each_entry(codec, &chip->bus->codec_list, list) {
4150                 snd_hda_power_down(codec);
4151         }
4152 #endif
4153 }
4154
4155 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4156 /* callback from request_firmware_nowait() */
4157 static void azx_firmware_cb(const struct firmware *fw, void *context)
4158 {
4159         struct snd_card *card = context;
4160         struct azx *chip = card->private_data;
4161         struct pci_dev *pci = chip->pci;
4162
4163         if (!fw) {
4164                 snd_printk(KERN_ERR SFX "%s: Cannot load firmware, aborting\n",
4165                            azx_name(chip));
4166                 goto error;
4167         }
4168
4169         chip->fw = fw;
4170         if (!chip->disabled) {
4171                 /* continue probing */
4172                 if (azx_probe_continue(chip))
4173                         goto error;
4174         }
4175         return; /* OK */
4176
4177  error:
4178         snd_card_free(card);
4179         pci_set_drvdata(pci, NULL);
4180 }
4181 #endif
4182
4183 static int azx_probe(struct pci_dev *pci,
4184                                struct platform_device *pdev,
4185                                int driver_data)
4186 {
4187         static int dev;
4188         struct snd_card *card;
4189         struct azx *chip;
4190         bool probe_now;
4191         struct device *azx_dev = pci ? &pci->dev : &pdev->dev;
4192         int err;
4193
4194         if (dev >= SNDRV_CARDS)
4195                 return -ENODEV;
4196         if (!enable[dev]) {
4197                 dev++;
4198                 return -ENOENT;
4199         }
4200
4201         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
4202         if (err < 0) {
4203                 snd_printk(KERN_ERR "hda-intel: Error creating card!\n");
4204                 return err;
4205         }
4206
4207         snd_card_set_dev(card, azx_dev);
4208
4209         err = azx_create(card, pci, pdev, dev, driver_data, &chip);
4210         if (err < 0)
4211                 goto out_free;
4212         card->private_data = chip;
4213
4214         if (pci)
4215                 pci_set_drvdata(pci, card);
4216         else
4217                 dev_set_drvdata(&pdev->dev, card);
4218
4219         err = register_vga_switcheroo(chip);
4220         if (err < 0) {
4221                 snd_printk(KERN_ERR SFX
4222                            "%s: Error registering VGA-switcheroo client\n", azx_name(chip));
4223                 goto out_free;
4224         }
4225
4226         if (check_hdmi_disabled(pci)) {
4227                 snd_printk(KERN_INFO SFX "%s: VGA controller is disabled\n",
4228                            azx_name(chip));
4229                 snd_printk(KERN_INFO SFX "%s: Delaying initialization\n", azx_name(chip));
4230                 chip->disabled = true;
4231         }
4232
4233         probe_now = !chip->disabled;
4234         if (probe_now) {
4235                 err = azx_first_init(chip);
4236                 if (err < 0)
4237                         goto out_free;
4238         }
4239
4240 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4241         if (patch[dev] && *patch[dev]) {
4242                 snd_printk(KERN_ERR SFX "%s: Applying patch firmware '%s'\n",
4243                            azx_name(chip), patch[dev]);
4244                 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
4245                                               &pci->dev, GFP_KERNEL, card,
4246                                               azx_firmware_cb);
4247                 if (err < 0)
4248                         goto out_free;
4249                 probe_now = false; /* continued in azx_firmware_cb() */
4250         }
4251 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
4252
4253         if (probe_now) {
4254                 err = azx_probe_continue(chip);
4255                 if (err < 0)
4256                         goto out_free;
4257         }
4258
4259         if (pci) {
4260                 pci_set_drvdata(pci, card);
4261
4262         if (pci_dev_run_wake(pci))
4263                 pm_runtime_put_noidle(&pci->dev);
4264         } else if (pdev) {
4265                 dev_set_drvdata(&pdev->dev, card);
4266 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
4267                 tegra_pd_add_device(chip->dev);
4268 #endif
4269                 pm_runtime_put(chip->dev);
4270         }
4271
4272         err = register_vga_switcheroo(chip);
4273         if (err < 0) {
4274                 snd_printk(KERN_ERR SFX
4275                            "Error registering VGA-switcheroo client\n");
4276                 goto out_free;
4277         }
4278
4279         dev++;
4280         complete_all(&chip->probe_wait);
4281
4282         if (pdev)
4283                 pm_runtime_put(chip->dev);
4284
4285         return 0;
4286
4287 out_free:
4288         snd_card_free(card);
4289         if (pci)
4290                 pci_set_drvdata(pci, NULL);
4291         else
4292                 dev_set_drvdata(&pdev->dev, NULL);
4293         return err;
4294 }
4295
4296 static int azx_probe_continue(struct azx *chip)
4297 {
4298         int dev = chip->dev_index;
4299         int err;
4300
4301 #ifdef CONFIG_SND_HDA_INPUT_BEEP
4302         chip->beep_mode = beep_mode[dev];
4303 #endif
4304
4305         /* create codec instances */
4306         err = azx_codec_create(chip, model[dev]);
4307         if (err < 0)
4308                 goto out_free;
4309 #ifdef CONFIG_SND_HDA_PATCH_LOADER
4310         if (chip->fw) {
4311                 err = snd_hda_load_patch(chip->bus, chip->fw->size,
4312                                          chip->fw->data);
4313                 if (err < 0)
4314                         goto out_free;
4315 #ifndef CONFIG_PM
4316                 release_firmware(chip->fw); /* no longer needed */
4317                 chip->fw = NULL;
4318 #endif
4319         }
4320 #endif
4321         if ((probe_only[dev] & 1) == 0) {
4322                 err = azx_codec_configure(chip);
4323                 if (err < 0)
4324                         goto out_free;
4325         }
4326
4327         /* create PCM streams */
4328         err = snd_hda_build_pcms(chip->bus);
4329         if (err < 0)
4330                 goto out_free;
4331
4332         /* create mixer controls */
4333         err = azx_mixer_create(chip);
4334         if (err < 0)
4335                 goto out_free;
4336
4337         err = snd_card_register(chip->card);
4338         if (err < 0)
4339                 goto out_free;
4340
4341         if (chip->pci)
4342                 pci_set_drvdata(chip->pci, chip->card);
4343         else
4344                 dev_set_drvdata(&chip->pdev->dev, chip->card);
4345
4346         chip->running = 1;
4347         power_down_all_codecs(chip);
4348         azx_notifier_register(chip);
4349         azx_add_card_list(chip);
4350
4351         return 0;
4352
4353 out_free:
4354         chip->init_failed = 1;
4355         return err;
4356 }
4357
4358 static int azx_probe_pci(struct pci_dev *pci,
4359                                    const struct pci_device_id *pci_id)
4360 {
4361         return azx_probe(pci, NULL, pci_id->driver_data);
4362 }
4363
4364 static void azx_remove_pci(struct pci_dev *pci)
4365 {
4366         struct snd_card *card = pci_get_drvdata(pci);
4367
4368         if (pci_dev_run_wake(pci))
4369                 pm_runtime_get_noresume(&pci->dev);
4370
4371         if (card)
4372                 snd_card_free(card);
4373         pci_set_drvdata(pci, NULL);
4374 }
4375
4376 /* PCI IDs */
4377 static DEFINE_PCI_DEVICE_TABLE(azx_pci_ids) = {
4378         /* CPT */
4379         { PCI_DEVICE(0x8086, 0x1c20),
4380           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4381         /* PBG */
4382         { PCI_DEVICE(0x8086, 0x1d20),
4383           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4384         /* Panther Point */
4385         { PCI_DEVICE(0x8086, 0x1e20),
4386           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
4387         /* Lynx Point */
4388         { PCI_DEVICE(0x8086, 0x8c20),
4389           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4390         /* 9 Series */
4391         { PCI_DEVICE(0x8086, 0x8ca0),
4392           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4393         /* Wellsburg */
4394         { PCI_DEVICE(0x8086, 0x8d20),
4395           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4396         { PCI_DEVICE(0x8086, 0x8d21),
4397           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4398         /* Lynx Point-LP */
4399         { PCI_DEVICE(0x8086, 0x9c20),
4400           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4401         /* Lynx Point-LP */
4402         { PCI_DEVICE(0x8086, 0x9c21),
4403           .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
4404         /* Haswell */
4405         { PCI_DEVICE(0x8086, 0x0a0c),
4406           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4407         { PCI_DEVICE(0x8086, 0x0c0c),
4408           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4409         { PCI_DEVICE(0x8086, 0x0d0c),
4410           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH },
4411         /* 5 Series/3400 */
4412         { PCI_DEVICE(0x8086, 0x3b56),
4413           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4414         /* Poulsbo */
4415         { PCI_DEVICE(0x8086, 0x811b),
4416           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4417         /* Oaktrail */
4418         { PCI_DEVICE(0x8086, 0x080a),
4419           .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
4420         /* ICH */
4421         { PCI_DEVICE(0x8086, 0x2668),
4422           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4423           AZX_DCAPS_BUFSIZE },  /* ICH6 */
4424         { PCI_DEVICE(0x8086, 0x27d8),
4425           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4426           AZX_DCAPS_BUFSIZE },  /* ICH7 */
4427         { PCI_DEVICE(0x8086, 0x269a),
4428           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4429           AZX_DCAPS_BUFSIZE },  /* ESB2 */
4430         { PCI_DEVICE(0x8086, 0x284b),
4431           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4432           AZX_DCAPS_BUFSIZE },  /* ICH8 */
4433         { PCI_DEVICE(0x8086, 0x293e),
4434           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4435           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4436         { PCI_DEVICE(0x8086, 0x293f),
4437           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4438           AZX_DCAPS_BUFSIZE },  /* ICH9 */
4439         { PCI_DEVICE(0x8086, 0x3a3e),
4440           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4441           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4442         { PCI_DEVICE(0x8086, 0x3a6e),
4443           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
4444           AZX_DCAPS_BUFSIZE },  /* ICH10 */
4445         /* Generic Intel */
4446         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
4447           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4448           .class_mask = 0xffffff,
4449           .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
4450         /* ATI SB 450/600/700/800/900 */
4451         { PCI_DEVICE(0x1002, 0x437b),
4452           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4453         { PCI_DEVICE(0x1002, 0x4383),
4454           .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
4455         /* AMD Hudson */
4456         { PCI_DEVICE(0x1022, 0x780d),
4457           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
4458         /* ATI HDMI */
4459         { PCI_DEVICE(0x1002, 0x793b),
4460           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4461         { PCI_DEVICE(0x1002, 0x7919),
4462           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4463         { PCI_DEVICE(0x1002, 0x960f),
4464           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4465         { PCI_DEVICE(0x1002, 0x970f),
4466           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4467         { PCI_DEVICE(0x1002, 0xaa00),
4468           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4469         { PCI_DEVICE(0x1002, 0xaa08),
4470           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4471         { PCI_DEVICE(0x1002, 0xaa10),
4472           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4473         { PCI_DEVICE(0x1002, 0xaa18),
4474           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4475         { PCI_DEVICE(0x1002, 0xaa20),
4476           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4477         { PCI_DEVICE(0x1002, 0xaa28),
4478           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4479         { PCI_DEVICE(0x1002, 0xaa30),
4480           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4481         { PCI_DEVICE(0x1002, 0xaa38),
4482           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4483         { PCI_DEVICE(0x1002, 0xaa40),
4484           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4485         { PCI_DEVICE(0x1002, 0xaa48),
4486           .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
4487         { PCI_DEVICE(0x1002, 0x9902),
4488           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4489         { PCI_DEVICE(0x1002, 0xaaa0),
4490           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4491         { PCI_DEVICE(0x1002, 0xaaa8),
4492           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4493         { PCI_DEVICE(0x1002, 0xaab0),
4494           .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
4495         /* VIA VT8251/VT8237A */
4496         { PCI_DEVICE(0x1106, 0x3288),
4497           .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
4498         /* VIA GFX VT7122/VX900 */
4499         { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
4500         /* VIA GFX VT6122/VX11 */
4501         { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
4502         /* SIS966 */
4503         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
4504         /* ULI M5461 */
4505         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
4506         /* NVIDIA MCP */
4507         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
4508           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4509           .class_mask = 0xffffff,
4510           .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
4511         /* Teradici */
4512         { PCI_DEVICE(0x6549, 0x1200),
4513           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4514         { PCI_DEVICE(0x6549, 0x2200),
4515           .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
4516         /* Creative X-Fi (CA0110-IBG) */
4517         /* CTHDA chips */
4518         { PCI_DEVICE(0x1102, 0x0010),
4519           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4520         { PCI_DEVICE(0x1102, 0x0012),
4521           .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
4522 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
4523         /* the following entry conflicts with snd-ctxfi driver,
4524          * as ctxfi driver mutates from HD-audio to native mode with
4525          * a special command sequence.
4526          */
4527         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
4528           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4529           .class_mask = 0xffffff,
4530           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4531           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4532 #else
4533         /* this entry seems still valid -- i.e. without emu20kx chip */
4534         { PCI_DEVICE(0x1102, 0x0009),
4535           .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
4536           AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
4537 #endif
4538         /* Vortex86MX */
4539         { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
4540         /* VMware HDAudio */
4541         { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
4542         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
4543         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
4544           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4545           .class_mask = 0xffffff,
4546           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4547         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
4548           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
4549           .class_mask = 0xffffff,
4550           .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
4551         { 0, }
4552 };
4553 MODULE_DEVICE_TABLE(pci, azx_pci_ids);
4554
4555 /* pci_driver definition */
4556 static struct pci_driver azx_driver = {
4557         .name = KBUILD_MODNAME,
4558         .id_table = azx_pci_ids,
4559         .probe = azx_probe_pci,
4560         .remove = azx_remove_pci,
4561         .driver = {
4562                 .pm = AZX_PM_OPS,
4563         },
4564 };
4565
4566 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4567
4568 static int hda_driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_PM_RUNTIME;
4569
4570 static const struct of_device_id hda_device[] = {
4571         {.compatible = "nvidia,tegra30-hda", .data = &hda_driver_data},
4572         {},
4573 };
4574 MODULE_DEVICE_TABLE(of, hda_device);
4575
4576 static int azx_probe_platform(struct platform_device *pdev)
4577 {
4578         const struct platform_device_id *pdev_id;
4579         const struct of_device_id *match;
4580         int driver_data;
4581
4582         if (pdev->dev.of_node) {
4583                 match = of_match_device(of_match_ptr(hda_device),
4584                                  &pdev->dev);
4585                 if (match) {
4586                         driver_data = *(int *)(match->data);
4587                 } else {
4588                         snd_printk(KERN_WARNING "%s matching device not found\n",
4589                                  __func__);
4590                         return -EINVAL;
4591                 }
4592         } else {
4593                 pdev_id = platform_get_device_id(pdev);
4594                 driver_data = pdev_id->driver_data;
4595         }
4596         return azx_probe(NULL, pdev, driver_data);
4597 }
4598
4599 static int azx_remove_platform(struct platform_device *pdev)
4600 {
4601         pm_runtime_get_noresume(&pdev->dev);
4602         return snd_card_free(dev_get_drvdata(&pdev->dev));
4603 }
4604
4605 static const struct platform_device_id azx_platform_ids[] = {
4606 #ifdef CONFIG_SND_HDA_PLATFORM_NVIDIA_TEGRA
4607         { "tegra30-hda",
4608           .driver_data = AZX_DRIVER_NVIDIA_TEGRA | AZX_DCAPS_PM_RUNTIME },
4609 #endif
4610         { },
4611 };
4612 MODULE_DEVICE_TABLE(platform, azx_platform_ids);
4613
4614 /* platform_driver definition */
4615 static struct platform_driver hda_platform_driver = {
4616         .driver = {
4617                 .name = "hda-platform",
4618                 .pm = AZX_PM_OPS,
4619                 .of_match_table = of_match_ptr(hda_device),
4620         },
4621         .probe = azx_probe_platform,
4622         .remove = azx_remove_platform,
4623         .id_table = azx_platform_ids,
4624 };
4625 #endif /* CONFIG_SND_HDA_PLATFORM_DRIVER */
4626
4627 static int __init alsa_card_azx_init(void)
4628 {
4629         int err = 0;
4630
4631         err = pci_register_driver(&azx_driver);
4632         if (err < 0) {
4633                 snd_printk(KERN_ERR SFX "Failed to register pci driver\n");
4634                 return err;
4635         }
4636
4637 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4638         err = platform_driver_register(&hda_platform_driver);
4639         if (err < 0) {
4640                 snd_printk(KERN_ERR SFX "Failed to register platform driver\n");
4641                 pci_unregister_driver(&azx_driver);
4642                 return err;
4643         }
4644 #endif
4645
4646         return 0;
4647 }
4648
4649 static void __exit alsa_card_azx_exit(void)
4650 {
4651 #ifdef CONFIG_SND_HDA_PLATFORM_DRIVER
4652         platform_driver_unregister(&hda_platform_driver);
4653 #endif
4654
4655         pci_unregister_driver(&azx_driver);
4656 }
4657
4658 module_init(alsa_card_azx_init)
4659 module_exit(alsa_card_azx_exit)