kernel: Fix build breaks
[linux-3.10.git] / include / media / nvc_image.h
1 /* Copyright (C) 2012 NVIDIA Corporation.
2  *
3  * This program is free software; you can redistribute it and/or modify
4  * it under the terms of the GNU General Public License version 2 as
5  * published by the Free Software Foundation.
6  *
7  * This program is distributed in the hope that it will be useful,
8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
10  * GNU General Public License for more details.
11  *
12  * You should have received a copy of the GNU General Public License
13  * along with this program; if not, write to the Free Software
14  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
15  * 02111-1307, USA
16  */
17
18 #ifndef __NVC_IMAGE_H__
19 #define __NVC_IMAGE_H__
20
21 #include <linux/ioctl.h>
22
23 #define NVC_IMAGER_API_CAPS_VER         2
24 #define NVC_IMAGER_API_STATIC_VER       1
25 #define NVC_IMAGER_API_DYNAMIC_VER      1
26 #define NVC_IMAGER_API_BAYER_VER        1
27
28 #define NVC_IMAGER_TEST_NONE            0
29 #define NVC_IMAGER_TEST_COLORBARS       1
30 #define NVC_IMAGER_TEST_CHECKERBOARD    2
31 #define NVC_IMAGER_TEST_WALKING1S       3
32
33 #define NVC_IMAGER_CROPMODE_NONE        1
34 #define NVC_IMAGER_CROPMODE_PARTIAL     2
35
36 #define NVC_IMAGER_TYPE_HUH             0
37 #define NVC_IMAGER_TYPE_RAW             1
38 #define NVC_IMAGER_TYPE_SOC             2
39
40 /**
41  * Defines camera imager types.
42  * Mirrors "NvOdmImagerRegion" in "imager/include/nvodm_imager.h".
43  * These must remain in sync.
44  */
45 #define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_8          1
46 #define NVC_IMAGER_SENSOR_INTERFACE_PARALLEL_10         2
47 #define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_A            3
48 #define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_B            4
49 #define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_C            5
50 #define NVC_IMAGER_SENSOR_INTERFACE_SERIAL_AB           6
51 #define NVC_IMAGER_SENSOR_INTERFACE_CCIR                7
52 #define NVC_IMAGER_SENSOR_INTERFACE_HOST                8
53 #define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_A          9
54 #define NVC_IMAGER_SENSOR_INTERFACE_HOST_CSI_B          10
55 #define NVC_IMAGER_SENSOR_INTERFACE_NUM                 11
56
57 #define NVC_IMAGER_IDENTIFIER_MAX       32
58 #define NVC_IMAGER_FORMAT_MAX           4
59 #define NVC_IMAGER_CLOCK_PROFILE_MAX    2
60 #define NVC_IMAGER_CAPABILITIES_VERSION2        ((0x3434 << 16) | 2)
61
62 #define NVC_IMAGER_INT2FLOAT_DIVISOR    1000
63
64 #define NVC_FOCUS_INTERNAL              (0x665F4E5643414D69ULL)
65 #define NVC_FOCUS_GUID(n) (0x665F4E5643414D30ULL | ((n) & 0xF))
66 #define NVC_TORCH_GUID(n) (0x6C5F4E5643414D30ULL | ((n) & 0xF))
67
68
69 struct nvc_imager_static_nvc {
70         __u32 api_version;
71         __u32 sensor_type;
72         __u32 bits_per_pixel;
73         __u32 sensor_id;
74         __u32 sensor_id_minor;
75         __u32 focal_len;
76         __u32 max_aperture;
77         __u32 fnumber;
78         __u32 view_angle_h;
79         __u32 view_angle_v;
80         __u32 stereo_cap;
81         __u32 res_chg_wait_time;
82         __u8 support_isp;
83         __u8 align1;
84         __u8 align2;
85         __u8 align3;
86         __u8 fuse_id[16];
87         __u32 place_holder1;
88         __u32 place_holder2;
89         __u32 place_holder3;
90         __u32 place_holder4;
91 } __packed;
92
93 struct nvc_imager_dynamic_nvc {
94         __u32 api_version;
95         __s32 region_start_x;
96         __s32 region_start_y;
97         __u32 x_scale;
98         __u32 y_scale;
99         __u32 bracket_caps;
100         __u32 flush_count;
101         __u32 init_intra_frame_skip;
102         __u32 ss_intra_frame_skip;
103         __u32 ss_frame_number;
104         __u32 coarse_time;
105         __u32 max_coarse_diff;
106         __u32 min_exposure_course;
107         __u32 max_exposure_course;
108         __u32 diff_integration_time;
109         __u32 line_length;
110         __u32 frame_length;
111         __u32 min_frame_length;
112         __u32 max_frame_length;
113         __u32 min_gain;
114         __u32 max_gain;
115         __u32 inherent_gain;
116         __u32 inherent_gain_bin_en;
117         __u8 support_bin_control;
118         __u8 support_fast_mode;
119         __u8 align2;
120         __u8 align3;
121         __u32 pll_mult;
122         __u32 pll_div;
123         __u32 mode_sw_wait_frames;
124         __u32 place_holder1;
125         __u32 place_holder2;
126         __u32 place_holder3;
127 } __packed;
128
129 struct nvc_imager_bayer {
130         __u32 api_version;
131         __s32 res_x;
132         __s32 res_y;
133         __u32 frame_length;
134         __u32 coarse_time;
135         __u32 gain;
136         __u8 bin_en;
137         __u8 align1;
138         __u8 align2;
139         __u8 align3;
140         __u32 place_holder1;
141         __u32 place_holder2;
142         __u32 place_holder3;
143         __u32 place_holder4;
144 } __packed;
145
146 struct nvc_imager_mode {
147         __s32 res_x;
148         __s32 res_y;
149         __s32 active_start_x;
150         __s32 active_stary_y;
151         __u32 peak_frame_rate;
152         __u32 pixel_aspect_ratio;
153         __u32 pll_multiplier;
154         __u32 crop_mode;
155         __u32 rect_left;
156         __u32 rect_top;
157         __u32 rect_right;
158         __u32 rect_bottom;
159         __u32 point_x;
160         __u32 point_y;
161         __u32 type;
162 } __packed;
163
164 struct nvc_imager_dnvc {
165         __s32 res_x;
166         __s32 res_y;
167         struct nvc_imager_mode *p_mode;
168         struct nvc_imager_dynamic_nvc *p_dnvc;
169 } __packed;
170
171 struct nvc_imager_mode_list {
172         struct nvc_imager_mode *p_modes;
173         __u32 *p_num_mode;
174 } __packed;
175
176 struct nvc_clock_profile {
177         __u32 external_clock_khz;
178         __u32 clock_multiplier;
179 } __packed;
180
181 struct nvc_imager_cap {
182         char identifier[NVC_IMAGER_IDENTIFIER_MAX];
183         __u32 sensor_nvc_interface;
184         __u32 pixel_types[NVC_IMAGER_FORMAT_MAX];
185         __u32 orientation;
186         __u32 direction;
187         __u32 initial_clock_rate_khz;
188         struct nvc_clock_profile clock_profiles[NVC_IMAGER_CLOCK_PROFILE_MAX];
189         __u32 h_sync_edge;
190         __u32 v_sync_edge;
191         __u32 mclk_on_vgp0;
192         __u8 csi_port;
193         __u8 data_lanes;
194         __u8 virtual_channel_id;
195         __u8 discontinuous_clk_mode;
196         __u8 cil_threshold_settle;
197         __u8 align1;
198         __u8 align2;
199         __u8 align3;
200         __s32 min_blank_time_width;
201         __s32 min_blank_time_height;
202         __u32 preferred_mode_index;
203         __u64 focuser_guid;
204         __u64 torch_guid;
205         __u32 cap_version;
206         __u8 flash_control_enabled;
207         __u8 adjustable_flash_timing;
208         __u8 align4;
209         __u8 align5;
210 } __packed;
211
212 struct nvc_imager_ae {
213         __u32 frame_length;
214         __u8  frame_length_enable;
215         __u32 coarse_time;
216         __u8  coarse_time_enable;
217         __u32 gain;
218         __u8  gain_enable;
219 } __packed;
220
221 union nvc_imager_flash_control {
222         __u16 mode;
223         struct {
224                 __u16 enable:1;         /* enable the on-sensor flash control */
225                 __u16 edge_trig_en:1;   /* two types of flash controls:
226                                          * 0 - LED_FLASH_EN - supports continued
227                                          *     flash level only, doesn't
228                                          *     support start edge/repeat/dly.
229                                          * 1 - FLASH_EN - supports control pulse
230                                          *     control pulse attributes are
231                                          *     defined below.
232                                          */
233                 __u16 start_edge:1;     /* flash control pulse rise position:
234                                          * 0 - at the start of the next frame.
235                                          * 1 - at the effective pixel end
236                                          *     position of the next frame.
237                                          */
238                 __u16 repeat:1;         /* flash control pulse repeat:
239                                          * 0 - only triggers one frame.
240                                          * 1 - trigger repeats every frame until
241                                          * Flash_EN = 0.
242                                          */
243                 __u16 delay_frm:2;      /* flash control pulse can be delayed
244                                          * in frame units: (0 - 3) - frame
245                                          * numbers the pulse is delayed.
246                                          */
247         } settings;
248 };
249
250 #define NVC_IOCTL_CAPS_RD       _IOWR('o', 106, struct nvc_imager_cap)
251 #define NVC_IOCTL_MODE_WR       _IOW('o', 107, struct nvc_imager_bayer)
252 #define NVC_IOCTL_MODE_RD       _IOWR('o', 108, struct nvc_imager_mode_list)
253 #define NVC_IOCTL_STATIC_RD     _IOWR('o', 109, struct nvc_imager_static_nvc)
254 #define NVC_IOCTL_DYNAMIC_RD    _IOWR('o', 110, struct nvc_imager_dnvc)
255
256 #endif /* __NVC_IMAGE_H__ */