regulator: tps65911: Add new chip version
[linux-3.10.git] / include / linux / mfd / tps65910.h
1 /*
2  * tps65910.h  --  TI TPS6591x
3  *
4  * Copyright 2010-2011 Texas Instruments Inc.
5  *
6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
7  * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
8  * Author: Arnaud Deconinck <a-deconinck@ti.com>
9  *
10  *  This program is free software; you can redistribute it and/or modify it
11  *  under  the terms of the GNU General  Public License as published by the
12  *  Free Software Foundation;  either version 2 of the License, or (at your
13  *  option) any later version.
14  *
15  */
16
17 #ifndef __LINUX_MFD_TPS65910_H
18 #define __LINUX_MFD_TPS65910_H
19
20 /* TPS chip id list */
21 #define TPS65910                        0
22 #define TPS65911                        1
23
24 /* TPS regulator type list */
25 #define REGULATOR_LDO                   0
26 #define REGULATOR_DCDC                  1
27
28 /*
29  * List of registers for component TPS65910
30  *
31  */
32
33 #define TPS65910_SECONDS                                0x0
34 #define TPS65910_MINUTES                                0x1
35 #define TPS65910_HOURS                                  0x2
36 #define TPS65910_DAYS                                   0x3
37 #define TPS65910_MONTHS                                 0x4
38 #define TPS65910_YEARS                                  0x5
39 #define TPS65910_WEEKS                                  0x6
40 #define TPS65910_ALARM_SECONDS                          0x8
41 #define TPS65910_ALARM_MINUTES                          0x9
42 #define TPS65910_ALARM_HOURS                            0xA
43 #define TPS65910_ALARM_DAYS                             0xB
44 #define TPS65910_ALARM_MONTHS                           0xC
45 #define TPS65910_ALARM_YEARS                            0xD
46 #define TPS65910_RTC_CTRL                               0x10
47 #define TPS65910_RTC_STATUS                             0x11
48 #define TPS65910_RTC_INTERRUPTS                         0x12
49 #define TPS65910_RTC_COMP_LSB                           0x13
50 #define TPS65910_RTC_COMP_MSB                           0x14
51 #define TPS65910_RTC_RES_PROG                           0x15
52 #define TPS65910_RTC_RESET_STATUS                       0x16
53 #define TPS65910_BCK1                                   0x17
54 #define TPS65910_BCK2                                   0x18
55 #define TPS65910_BCK3                                   0x19
56 #define TPS65910_BCK4                                   0x1A
57 #define TPS65910_BCK5                                   0x1B
58 #define TPS65910_PUADEN                                 0x1C
59 #define TPS65910_REF                                    0x1D
60 #define TPS65910_VRTC                                   0x1E
61 #define TPS65910_VIO                                    0x20
62 #define TPS65910_VDD1                                   0x21
63 #define TPS65910_VDD1_OP                                0x22
64 #define TPS65910_VDD1_SR                                0x23
65 #define TPS65910_VDD2                                   0x24
66 #define TPS65910_VDD2_OP                                0x25
67 #define TPS65910_VDD2_SR                                0x26
68 #define TPS65910_VDD3                                   0x27
69 #define TPS65910_VDIG1                                  0x30
70 #define TPS65910_VDIG2                                  0x31
71 #define TPS65910_VAUX1                                  0x32
72 #define TPS65910_VAUX2                                  0x33
73 #define TPS65910_VAUX33                                 0x34
74 #define TPS65910_VMMC                                   0x35
75 #define TPS65910_VPLL                                   0x36
76 #define TPS65910_VDAC                                   0x37
77 #define TPS65910_THERM                                  0x38
78 #define TPS65910_BBCH                                   0x39
79 #define TPS65910_DCDCCTRL                               0x3E
80 #define TPS65910_DEVCTRL                                0x3F
81 #define TPS65910_DEVCTRL2                               0x40
82 #define TPS65910_SLEEP_KEEP_LDO_ON                      0x41
83 #define TPS65910_SLEEP_KEEP_RES_ON                      0x42
84 #define TPS65910_SLEEP_SET_LDO_OFF                      0x43
85 #define TPS65910_SLEEP_SET_RES_OFF                      0x44
86 #define TPS65910_EN1_LDO_ASS                            0x45
87 #define TPS65910_EN1_SMPS_ASS                           0x46
88 #define TPS65910_EN2_LDO_ASS                            0x47
89 #define TPS65910_EN2_SMPS_ASS                           0x48
90 #define TPS65910_EN3_LDO_ASS                            0x49
91 #define TPS65910_SPARE                                  0x4A
92 #define TPS65910_INT_STS                                0x50
93 #define TPS65910_INT_MSK                                0x51
94 #define TPS65910_INT_STS2                               0x52
95 #define TPS65910_INT_MSK2                               0x53
96 #define TPS65910_INT_STS3                               0x54
97 #define TPS65910_INT_MSK3                               0x55
98 #define TPS65910_GPIO0                                  0x60
99 #define TPS65910_GPIO1                                  0x61
100 #define TPS65910_GPIO2                                  0x62
101 #define TPS65910_GPIO3                                  0x63
102 #define TPS65910_GPIO4                                  0x64
103 #define TPS65910_GPIO5                                  0x65
104 #define TPS65910_JTAGVERNUM                             0x80
105 #define TPS65910_MAX_REGISTER                           0x80
106
107 /*
108  * List of registers specific to TPS65911
109  */
110 #define TPS65911_VDDCTRL                                0x27
111 #define TPS65911_VDDCTRL_OP                             0x28
112 #define TPS65911_VDDCTRL_SR                             0x29
113 #define TPS65911_LDO1                                   0x30
114 #define TPS65911_LDO2                                   0x31
115 #define TPS65911_LDO5                                   0x32
116 #define TPS65911_LDO8                                   0x33
117 #define TPS65911_LDO7                                   0x34
118 #define TPS65911_LDO6                                   0x35
119 #define TPS65911_LDO4                                   0x36
120 #define TPS65911_LDO3                                   0x37
121
122 /*
123  * List of register bitfields for component TPS65910
124  *
125  */
126
127
128 /*Register BCK1  (0x80) register.RegisterDescription */
129 #define BCK1_BCKUP_MASK                                 0xFF
130 #define BCK1_BCKUP_SHIFT                                0
131
132
133 /*Register BCK2  (0x80) register.RegisterDescription */
134 #define BCK2_BCKUP_MASK                                 0xFF
135 #define BCK2_BCKUP_SHIFT                                0
136
137
138 /*Register BCK3  (0x80) register.RegisterDescription */
139 #define BCK3_BCKUP_MASK                                 0xFF
140 #define BCK3_BCKUP_SHIFT                                0
141
142
143 /*Register BCK4  (0x80) register.RegisterDescription */
144 #define BCK4_BCKUP_MASK                                 0xFF
145 #define BCK4_BCKUP_SHIFT                                0
146
147
148 /*Register BCK5  (0x80) register.RegisterDescription */
149 #define BCK5_BCKUP_MASK                                 0xFF
150 #define BCK5_BCKUP_SHIFT                                0
151
152
153 /*Register PUADEN  (0x80) register.RegisterDescription */
154 #define PUADEN_EN3P_MASK                                0x80
155 #define PUADEN_EN3P_SHIFT                               7
156 #define PUADEN_I2CCTLP_MASK                             0x40
157 #define PUADEN_I2CCTLP_SHIFT                            6
158 #define PUADEN_I2CSRP_MASK                              0x20
159 #define PUADEN_I2CSRP_SHIFT                             5
160 #define PUADEN_PWRONP_MASK                              0x10
161 #define PUADEN_PWRONP_SHIFT                             4
162 #define PUADEN_SLEEPP_MASK                              0x08
163 #define PUADEN_SLEEPP_SHIFT                             3
164 #define PUADEN_PWRHOLDP_MASK                            0x04
165 #define PUADEN_PWRHOLDP_SHIFT                           2
166 #define PUADEN_BOOT1P_MASK                              0x02
167 #define PUADEN_BOOT1P_SHIFT                             1
168 #define PUADEN_BOOT0P_MASK                              0x01
169 #define PUADEN_BOOT0P_SHIFT                             0
170
171
172 /*Register REF  (0x80) register.RegisterDescription */
173 #define REF_VMBCH_SEL_MASK                              0x0C
174 #define REF_VMBCH_SEL_SHIFT                             2
175 #define REF_ST_MASK                                     0x03
176 #define REF_ST_SHIFT                                    0
177
178
179 /*Register VRTC  (0x80) register.RegisterDescription */
180 #define VRTC_VRTC_OFFMASK_MASK                          0x08
181 #define VRTC_VRTC_OFFMASK_SHIFT                         3
182 #define VRTC_ST_MASK                                    0x03
183 #define VRTC_ST_SHIFT                                   0
184
185
186 /*Register VIO  (0x80) register.RegisterDescription */
187 #define VIO_ILMAX_MASK                                  0xC0
188 #define VIO_ILMAX_SHIFT                                 6
189 #define VIO_SEL_MASK                                    0x0C
190 #define VIO_SEL_SHIFT                                   2
191 #define VIO_ST_MASK                                     0x03
192 #define VIO_ST_SHIFT                                    0
193
194
195 /*Register VDD1  (0x80) register.RegisterDescription */
196 #define VDD1_VGAIN_SEL_MASK                             0xC0
197 #define VDD1_VGAIN_SEL_SHIFT                            6
198 #define VDD1_ILMAX_MASK                                 0x20
199 #define VDD1_ILMAX_SHIFT                                5
200 #define VDD1_TSTEP_MASK                                 0x1C
201 #define VDD1_TSTEP_SHIFT                                2
202 #define VDD1_ST_MASK                                    0x03
203 #define VDD1_ST_SHIFT                                   0
204
205
206 /*Register VDD1_OP  (0x80) register.RegisterDescription */
207 #define VDD1_OP_CMD_MASK                                0x80
208 #define VDD1_OP_CMD_SHIFT                               7
209 #define VDD1_OP_SEL_MASK                                0x7F
210 #define VDD1_OP_SEL_SHIFT                               0
211
212
213 /*Register VDD1_SR  (0x80) register.RegisterDescription */
214 #define VDD1_SR_SEL_MASK                                0x7F
215 #define VDD1_SR_SEL_SHIFT                               0
216
217
218 /*Register VDD2  (0x80) register.RegisterDescription */
219 #define VDD2_VGAIN_SEL_MASK                             0xC0
220 #define VDD2_VGAIN_SEL_SHIFT                            6
221 #define VDD2_ILMAX_MASK                                 0x20
222 #define VDD2_ILMAX_SHIFT                                5
223 #define VDD2_TSTEP_MASK                                 0x1C
224 #define VDD2_TSTEP_SHIFT                                2
225 #define VDD2_ST_MASK                                    0x03
226 #define VDD2_ST_SHIFT                                   0
227
228
229 /*Register VDD2_OP  (0x80) register.RegisterDescription */
230 #define VDD2_OP_CMD_MASK                                0x80
231 #define VDD2_OP_CMD_SHIFT                               7
232 #define VDD2_OP_SEL_MASK                                0x7F
233 #define VDD2_OP_SEL_SHIFT                               0
234
235 /*Register VDD2_SR  (0x80) register.RegisterDescription */
236 #define VDD2_SR_SEL_MASK                                0x7F
237 #define VDD2_SR_SEL_SHIFT                               0
238
239
240 /*Registers VDD1, VDD2 voltage values definitions */
241 #define VDD1_2_NUM_VOLTS                                73
242 #define VDD1_2_MIN_VOLT                                 6000
243 #define VDD1_2_OFFSET                                   125
244
245
246 /*Register VDD3  (0x80) register.RegisterDescription */
247 #define VDD3_CKINEN_MASK                                0x04
248 #define VDD3_CKINEN_SHIFT                               2
249 #define VDD3_ST_MASK                                    0x03
250 #define VDD3_ST_SHIFT                                   0
251 #define VDDCTRL_MIN_VOLT                                6000
252 #define VDDCTRL_OFFSET                                  125
253
254 /*Registers VDIG (0x80) to VDAC register.RegisterDescription */
255 #define LDO_SEL_MASK                                    0x0C
256 #define LDO_SEL_SHIFT                                   2
257 #define LDO_ST_MASK                                     0x03
258 #define LDO_ST_SHIFT                                    0
259 #define LDO_ST_ON_BIT                                   0x01
260 #define LDO_ST_MODE_BIT                                 0x02    
261
262
263 /* Registers LDO1 to LDO8 in tps65910 */
264 #define LDO1_SEL_MASK                                   0xFC
265 #define LDO3_SEL_MASK                                   0x7C
266 #define LDO_MIN_VOLT                                    1000
267 #define LDO_MAX_VOLT                                    3300;
268
269
270 /*Register VDIG1  (0x80) register.RegisterDescription */
271 #define VDIG1_SEL_MASK                                  0x0C
272 #define VDIG1_SEL_SHIFT                                 2
273 #define VDIG1_ST_MASK                                   0x03
274 #define VDIG1_ST_SHIFT                                  0
275
276
277 /*Register VDIG2  (0x80) register.RegisterDescription */
278 #define VDIG2_SEL_MASK                                  0x0C
279 #define VDIG2_SEL_SHIFT                                 2
280 #define VDIG2_ST_MASK                                   0x03
281 #define VDIG2_ST_SHIFT                                  0
282
283
284 /*Register VAUX1  (0x80) register.RegisterDescription */
285 #define VAUX1_SEL_MASK                                  0x0C
286 #define VAUX1_SEL_SHIFT                                 2
287 #define VAUX1_ST_MASK                                   0x03
288 #define VAUX1_ST_SHIFT                                  0
289
290
291 /*Register VAUX2  (0x80) register.RegisterDescription */
292 #define VAUX2_SEL_MASK                                  0x0C
293 #define VAUX2_SEL_SHIFT                                 2
294 #define VAUX2_ST_MASK                                   0x03
295 #define VAUX2_ST_SHIFT                                  0
296
297
298 /*Register VAUX33  (0x80) register.RegisterDescription */
299 #define VAUX33_SEL_MASK                                 0x0C
300 #define VAUX33_SEL_SHIFT                                2
301 #define VAUX33_ST_MASK                                  0x03
302 #define VAUX33_ST_SHIFT                                 0
303
304
305 /*Register VMMC  (0x80) register.RegisterDescription */
306 #define VMMC_SEL_MASK                                   0x0C
307 #define VMMC_SEL_SHIFT                                  2
308 #define VMMC_ST_MASK                                    0x03
309 #define VMMC_ST_SHIFT                                   0
310
311
312 /*Register VPLL  (0x80) register.RegisterDescription */
313 #define VPLL_SEL_MASK                                   0x0C
314 #define VPLL_SEL_SHIFT                                  2
315 #define VPLL_ST_MASK                                    0x03
316 #define VPLL_ST_SHIFT                                   0
317
318
319 /*Register VDAC  (0x80) register.RegisterDescription */
320 #define VDAC_SEL_MASK                                   0x0C
321 #define VDAC_SEL_SHIFT                                  2
322 #define VDAC_ST_MASK                                    0x03
323 #define VDAC_ST_SHIFT                                   0
324
325
326 /*Register THERM  (0x80) register.RegisterDescription */
327 #define THERM_THERM_HD_MASK                             0x20
328 #define THERM_THERM_HD_SHIFT                            5
329 #define THERM_THERM_TS_MASK                             0x10
330 #define THERM_THERM_TS_SHIFT                            4
331 #define THERM_THERM_HDSEL_MASK                          0x0C
332 #define THERM_THERM_HDSEL_SHIFT                         2
333 #define THERM_RSVD1_MASK                                0x02
334 #define THERM_RSVD1_SHIFT                               1
335 #define THERM_THERM_STATE_MASK                          0x01
336 #define THERM_THERM_STATE_SHIFT                         0
337
338
339 /*Register BBCH  (0x80) register.RegisterDescription */
340 #define BBCH_BBSEL_MASK                                 0x06
341 #define BBCH_BBSEL_SHIFT                                1
342 #define BBCH_BBCHEN_MASK                                0x01
343 #define BBCH_BBCHEN_SHIFT                               0
344
345
346 /*Register DCDCCTRL  (0x80) register.RegisterDescription */
347 #define DCDCCTRL_VDD2_PSKIP_MASK                        0x20
348 #define DCDCCTRL_VDD2_PSKIP_SHIFT                       5
349 #define DCDCCTRL_VDD1_PSKIP_MASK                        0x10
350 #define DCDCCTRL_VDD1_PSKIP_SHIFT                       4
351 #define DCDCCTRL_VIO_PSKIP_MASK                         0x08
352 #define DCDCCTRL_VIO_PSKIP_SHIFT                        3
353 #define DCDCCTRL_DCDCCKEXT_MASK                         0x04
354 #define DCDCCTRL_DCDCCKEXT_SHIFT                        2
355 #define DCDCCTRL_DCDCCKSYNC_MASK                        0x03
356 #define DCDCCTRL_DCDCCKSYNC_SHIFT                       0
357
358
359 /*Register DEVCTRL  (0x80) register.RegisterDescription */
360 #define DEVCTRL_RTC_PWDN_MASK                           0x40
361 #define DEVCTRL_RTC_PWDN_SHIFT                          6
362 #define DEVCTRL_CK32K_CTRL_MASK                         0x20
363 #define DEVCTRL_CK32K_CTRL_SHIFT                        5
364 #define DEVCTRL_SR_CTL_I2C_SEL_MASK                     0x10
365 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT                    4
366 #define DEVCTRL_DEV_OFF_RST_MASK                        0x08
367 #define DEVCTRL_DEV_OFF_RST_SHIFT                       3
368 #define DEVCTRL_DEV_ON_MASK                             0x04
369 #define DEVCTRL_DEV_ON_SHIFT                            2
370 #define DEVCTRL_DEV_SLP_MASK                            0x02
371 #define DEVCTRL_DEV_SLP_SHIFT                           1
372 #define DEVCTRL_DEV_OFF_MASK                            0x01
373 #define DEVCTRL_DEV_OFF_SHIFT                           0
374
375
376 /*Register DEVCTRL2  (0x80) register.RegisterDescription */
377 #define DEVCTRL2_TSLOT_LENGTH_MASK                      0x30
378 #define DEVCTRL2_TSLOT_LENGTH_SHIFT                     4
379 #define DEVCTRL2_SLEEPSIG_POL_MASK                      0x08
380 #define DEVCTRL2_SLEEPSIG_POL_SHIFT                     3
381 #define DEVCTRL2_PWON_LP_OFF_MASK                       0x04
382 #define DEVCTRL2_PWON_LP_OFF_SHIFT                      2
383 #define DEVCTRL2_PWON_LP_RST_MASK                       0x02
384 #define DEVCTRL2_PWON_LP_RST_SHIFT                      1
385 #define DEVCTRL2_IT_POL_MASK                            0x01
386 #define DEVCTRL2_IT_POL_SHIFT                           0
387
388
389 /*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
390 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK              0x80
391 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT             7
392 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK              0x40
393 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT             6
394 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK            0x20
395 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT           5
396 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK             0x10
397 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT            4
398 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK             0x08
399 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT            3
400 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK             0x04
401 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT            2
402 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK             0x02
403 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT            1
404 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK              0x01
405 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT             0
406
407
408 /*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
409 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK             0x80
410 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT            7
411 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK         0x40
412 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT        6
413 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK              0x20
414 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT             5
415 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK             0x10
416 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT            4
417 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK              0x08
418 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT             3
419 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK              0x04
420 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT             2
421 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK              0x02
422 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT             1
423 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK               0x01
424 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT              0
425
426
427 /*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
428 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK              0x80
429 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT             7
430 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK              0x40
431 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT             6
432 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK            0x20
433 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT           5
434 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK             0x10
435 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT            4
436 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK             0x08
437 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT            3
438 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK             0x04
439 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT            2
440 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK             0x02
441 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT            1
442 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK              0x01
443 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT             0
444
445
446 /*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
447 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK             0x80
448 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT            7
449 #define SLEEP_SET_RES_OFF_RSVD_MASK                     0x60
450 #define SLEEP_SET_RES_OFF_RSVD_SHIFT                    5
451 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK             0x10
452 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT            4
453 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK              0x08
454 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT             3
455 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK              0x04
456 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT             2
457 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK              0x02
458 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT             1
459 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK               0x01
460 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT              0
461
462
463 /*Register EN1_LDO_ASS  (0x80) register.RegisterDescription */
464 #define EN1_LDO_ASS_VDAC_EN1_MASK                       0x80
465 #define EN1_LDO_ASS_VDAC_EN1_SHIFT                      7
466 #define EN1_LDO_ASS_VPLL_EN1_MASK                       0x40
467 #define EN1_LDO_ASS_VPLL_EN1_SHIFT                      6
468 #define EN1_LDO_ASS_VAUX33_EN1_MASK                     0x20
469 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT                    5
470 #define EN1_LDO_ASS_VAUX2_EN1_MASK                      0x10
471 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT                     4
472 #define EN1_LDO_ASS_VAUX1_EN1_MASK                      0x08
473 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT                     3
474 #define EN1_LDO_ASS_VDIG2_EN1_MASK                      0x04
475 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT                     2
476 #define EN1_LDO_ASS_VDIG1_EN1_MASK                      0x02
477 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT                     1
478 #define EN1_LDO_ASS_VMMC_EN1_MASK                       0x01
479 #define EN1_LDO_ASS_VMMC_EN1_SHIFT                      0
480
481
482 /*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
483 #define EN1_SMPS_ASS_RSVD_MASK                          0xE0
484 #define EN1_SMPS_ASS_RSVD_SHIFT                         5
485 #define EN1_SMPS_ASS_SPARE_EN1_MASK                     0x10
486 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT                    4
487 #define EN1_SMPS_ASS_VDD3_EN1_MASK                      0x08
488 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT                     3
489 #define EN1_SMPS_ASS_VDD2_EN1_MASK                      0x04
490 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT                     2
491 #define EN1_SMPS_ASS_VDD1_EN1_MASK                      0x02
492 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT                     1
493 #define EN1_SMPS_ASS_VIO_EN1_MASK                       0x01
494 #define EN1_SMPS_ASS_VIO_EN1_SHIFT                      0
495
496
497 /*Register EN2_LDO_ASS  (0x80) register.RegisterDescription */
498 #define EN2_LDO_ASS_VDAC_EN2_MASK                       0x80
499 #define EN2_LDO_ASS_VDAC_EN2_SHIFT                      7
500 #define EN2_LDO_ASS_VPLL_EN2_MASK                       0x40
501 #define EN2_LDO_ASS_VPLL_EN2_SHIFT                      6
502 #define EN2_LDO_ASS_VAUX33_EN2_MASK                     0x20
503 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT                    5
504 #define EN2_LDO_ASS_VAUX2_EN2_MASK                      0x10
505 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT                     4
506 #define EN2_LDO_ASS_VAUX1_EN2_MASK                      0x08
507 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT                     3
508 #define EN2_LDO_ASS_VDIG2_EN2_MASK                      0x04
509 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT                     2
510 #define EN2_LDO_ASS_VDIG1_EN2_MASK                      0x02
511 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT                     1
512 #define EN2_LDO_ASS_VMMC_EN2_MASK                       0x01
513 #define EN2_LDO_ASS_VMMC_EN2_SHIFT                      0
514
515
516 /*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
517 #define EN2_SMPS_ASS_RSVD_MASK                          0xE0
518 #define EN2_SMPS_ASS_RSVD_SHIFT                         5
519 #define EN2_SMPS_ASS_SPARE_EN2_MASK                     0x10
520 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT                    4
521 #define EN2_SMPS_ASS_VDD3_EN2_MASK                      0x08
522 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT                     3
523 #define EN2_SMPS_ASS_VDD2_EN2_MASK                      0x04
524 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT                     2
525 #define EN2_SMPS_ASS_VDD1_EN2_MASK                      0x02
526 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT                     1
527 #define EN2_SMPS_ASS_VIO_EN2_MASK                       0x01
528 #define EN2_SMPS_ASS_VIO_EN2_SHIFT                      0
529
530
531 /*Register EN3_LDO_ASS  (0x80) register.RegisterDescription */
532 #define EN3_LDO_ASS_VDAC_EN3_MASK                       0x80
533 #define EN3_LDO_ASS_VDAC_EN3_SHIFT                      7
534 #define EN3_LDO_ASS_VPLL_EN3_MASK                       0x40
535 #define EN3_LDO_ASS_VPLL_EN3_SHIFT                      6
536 #define EN3_LDO_ASS_VAUX33_EN3_MASK                     0x20
537 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT                    5
538 #define EN3_LDO_ASS_VAUX2_EN3_MASK                      0x10
539 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT                     4
540 #define EN3_LDO_ASS_VAUX1_EN3_MASK                      0x08
541 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT                     3
542 #define EN3_LDO_ASS_VDIG2_EN3_MASK                      0x04
543 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT                     2
544 #define EN3_LDO_ASS_VDIG1_EN3_MASK                      0x02
545 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT                     1
546 #define EN3_LDO_ASS_VMMC_EN3_MASK                       0x01
547 #define EN3_LDO_ASS_VMMC_EN3_SHIFT                      0
548
549
550 /*Register SPARE  (0x80) register.RegisterDescription */
551 #define SPARE_SPARE_MASK                                0xFF
552 #define SPARE_SPARE_SHIFT                               0
553
554
555 /*Register INT_STS  (0x80) register.RegisterDescription */
556 #define INT_STS_RTC_PERIOD_IT_MASK                      0x80
557 #define INT_STS_RTC_PERIOD_IT_SHIFT                     7
558 #define INT_STS_RTC_ALARM_IT_MASK                       0x40
559 #define INT_STS_RTC_ALARM_IT_SHIFT                      6
560 #define INT_STS_HOTDIE_IT_MASK                          0x20
561 #define INT_STS_HOTDIE_IT_SHIFT                         5
562 #define INT_STS_PWRHOLD_IT_MASK                         0x10
563 #define INT_STS_PWRHOLD_IT_SHIFT                        4
564 #define INT_STS_PWRON_LP_IT_MASK                        0x08
565 #define INT_STS_PWRON_LP_IT_SHIFT                       3
566 #define INT_STS_PWRON_IT_MASK                           0x04
567 #define INT_STS_PWRON_IT_SHIFT                          2
568 #define INT_STS_VMBHI_IT_MASK                           0x02
569 #define INT_STS_VMBHI_IT_SHIFT                          1
570 #define INT_STS_VMBDCH_IT_MASK                          0x01
571 #define INT_STS_VMBDCH_IT_SHIFT                         0
572
573
574 /*Register INT_MSK  (0x80) register.RegisterDescription */
575 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK                  0x80
576 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                 7
577 #define INT_MSK_RTC_ALARM_IT_MSK_MASK                   0x40
578 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
579 #define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
580 #define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
581 #define INT_MSK_PWRHOLD_IT_MSK_MASK                     0x10
582 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT                    4
583 #define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
584 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
585 #define INT_MSK_PWRON_IT_MSK_MASK                       0x04
586 #define INT_MSK_PWRON_IT_MSK_SHIFT                      2
587 #define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
588 #define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
589 #define INT_MSK_VMBDCH_IT_MSK_MASK                      0x01
590 #define INT_MSK_VMBDCH_IT_MSK_SHIFT                     0
591
592
593 /*Register INT_STS2  (0x80) register.RegisterDescription */
594 #define INT_STS2_GPIO3_F_IT_MASK                        0x80
595 #define INT_STS2_GPIO3_F_IT_SHIFT                       7
596 #define INT_STS2_GPIO3_R_IT_MASK                        0x40
597 #define INT_STS2_GPIO3_R_IT_SHIFT                       6
598 #define INT_STS2_GPIO2_F_IT_MASK                        0x20
599 #define INT_STS2_GPIO2_F_IT_SHIFT                       5
600 #define INT_STS2_GPIO2_R_IT_MASK                        0x10
601 #define INT_STS2_GPIO2_R_IT_SHIFT                       4
602 #define INT_STS2_GPIO1_F_IT_MASK                        0x08
603 #define INT_STS2_GPIO1_F_IT_SHIFT                       3
604 #define INT_STS2_GPIO1_R_IT_MASK                        0x04
605 #define INT_STS2_GPIO1_R_IT_SHIFT                       2
606 #define INT_STS2_GPIO0_F_IT_MASK                        0x02
607 #define INT_STS2_GPIO0_F_IT_SHIFT                       1
608 #define INT_STS2_GPIO0_R_IT_MASK                        0x01
609 #define INT_STS2_GPIO0_R_IT_SHIFT                       0
610
611
612 /*Register INT_MSK2  (0x80) register.RegisterDescription */
613 #define INT_MSK2_GPIO3_F_IT_MSK_MASK                    0x80
614 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT                   7
615 #define INT_MSK2_GPIO3_R_IT_MSK_MASK                    0x40
616 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT                   6
617 #define INT_MSK2_GPIO2_F_IT_MSK_MASK                    0x20
618 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT                   5
619 #define INT_MSK2_GPIO2_R_IT_MSK_MASK                    0x10
620 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT                   4
621 #define INT_MSK2_GPIO1_F_IT_MSK_MASK                    0x08
622 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT                   3
623 #define INT_MSK2_GPIO1_R_IT_MSK_MASK                    0x04
624 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT                   2
625 #define INT_MSK2_GPIO0_F_IT_MSK_MASK                    0x02
626 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT                   1
627 #define INT_MSK2_GPIO0_R_IT_MSK_MASK                    0x01
628 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT                   0
629
630
631 /*Register INT_STS3  (0x80) register.RegisterDescription */
632 #define INT_STS3_GPIO5_F_IT_MASK                        0x08
633 #define INT_STS3_GPIO5_F_IT_SHIFT                       3
634 #define INT_STS3_GPIO5_R_IT_MASK                        0x04
635 #define INT_STS3_GPIO5_R_IT_SHIFT                       2
636 #define INT_STS3_GPIO4_F_IT_MASK                        0x02
637 #define INT_STS3_GPIO4_F_IT_SHIFT                       1
638 #define INT_STS3_GPIO4_R_IT_MASK                        0x01
639 #define INT_STS3_GPIO4_R_IT_SHIFT                       0
640
641
642 /*Register INT_MSK3  (0x80) register.RegisterDescription */
643 #define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
644 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
645 #define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
646 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT                   2
647 #define INT_MSK3_GPIO4_F_IT_MSK_MASK                    0x02
648 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT                   1
649 #define INT_MSK3_GPIO4_R_IT_MSK_MASK                    0x01
650 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT                   0
651
652
653 /*Register GPIO0  (0x80) register.RegisterDescription */
654 #define GPIO0_GPIO_DEB_MASK                             0x10
655 #define GPIO0_GPIO_DEB_SHIFT                            4
656 #define GPIO0_GPIO_PUEN_MASK                            0x08
657 #define GPIO0_GPIO_PUEN_SHIFT                           3
658 #define GPIO0_GPIO_CFG_MASK                             0x04
659 #define GPIO0_GPIO_CFG_SHIFT                            2
660 #define GPIO0_GPIO_STS_MASK                             0x02
661 #define GPIO0_GPIO_STS_SHIFT                            1
662 #define GPIO0_GPIO_SET_MASK                             0x01
663 #define GPIO0_GPIO_SET_SHIFT                            0
664
665
666 /*Register GPIO1  (0x80) register.RegisterDescription */
667 #define GPIO1_GPIO_DEB_MASK                             0x10
668 #define GPIO1_GPIO_DEB_SHIFT                            4
669 #define GPIO1_GPIO_PUEN_MASK                            0x08
670 #define GPIO1_GPIO_PUEN_SHIFT                           3
671 #define GPIO1_GPIO_CFG_MASK                             0x04
672 #define GPIO1_GPIO_CFG_SHIFT                            2
673 #define GPIO1_GPIO_STS_MASK                             0x02
674 #define GPIO1_GPIO_STS_SHIFT                            1
675 #define GPIO1_GPIO_SET_MASK                             0x01
676 #define GPIO1_GPIO_SET_SHIFT                            0
677
678
679 /*Register GPIO2  (0x80) register.RegisterDescription */
680 #define GPIO2_GPIO_DEB_MASK                             0x10
681 #define GPIO2_GPIO_DEB_SHIFT                            4
682 #define GPIO2_GPIO_PUEN_MASK                            0x08
683 #define GPIO2_GPIO_PUEN_SHIFT                           3
684 #define GPIO2_GPIO_CFG_MASK                             0x04
685 #define GPIO2_GPIO_CFG_SHIFT                            2
686 #define GPIO2_GPIO_STS_MASK                             0x02
687 #define GPIO2_GPIO_STS_SHIFT                            1
688 #define GPIO2_GPIO_SET_MASK                             0x01
689 #define GPIO2_GPIO_SET_SHIFT                            0
690
691
692 /*Register GPIO3  (0x80) register.RegisterDescription */
693 #define GPIO3_GPIO_DEB_MASK                             0x10
694 #define GPIO3_GPIO_DEB_SHIFT                            4
695 #define GPIO3_GPIO_PUEN_MASK                            0x08
696 #define GPIO3_GPIO_PUEN_SHIFT                           3
697 #define GPIO3_GPIO_CFG_MASK                             0x04
698 #define GPIO3_GPIO_CFG_SHIFT                            2
699 #define GPIO3_GPIO_STS_MASK                             0x02
700 #define GPIO3_GPIO_STS_SHIFT                            1
701 #define GPIO3_GPIO_SET_MASK                             0x01
702 #define GPIO3_GPIO_SET_SHIFT                            0
703
704
705 /*Register GPIO4  (0x80) register.RegisterDescription */
706 #define GPIO4_GPIO_DEB_MASK                             0x10
707 #define GPIO4_GPIO_DEB_SHIFT                            4
708 #define GPIO4_GPIO_PUEN_MASK                            0x08
709 #define GPIO4_GPIO_PUEN_SHIFT                           3
710 #define GPIO4_GPIO_CFG_MASK                             0x04
711 #define GPIO4_GPIO_CFG_SHIFT                            2
712 #define GPIO4_GPIO_STS_MASK                             0x02
713 #define GPIO4_GPIO_STS_SHIFT                            1
714 #define GPIO4_GPIO_SET_MASK                             0x01
715 #define GPIO4_GPIO_SET_SHIFT                            0
716
717
718 /*Register GPIO5  (0x80) register.RegisterDescription */
719 #define GPIO5_GPIO_DEB_MASK                             0x10
720 #define GPIO5_GPIO_DEB_SHIFT                            4
721 #define GPIO5_GPIO_PUEN_MASK                            0x08
722 #define GPIO5_GPIO_PUEN_SHIFT                           3
723 #define GPIO5_GPIO_CFG_MASK                             0x04
724 #define GPIO5_GPIO_CFG_SHIFT                            2
725 #define GPIO5_GPIO_STS_MASK                             0x02
726 #define GPIO5_GPIO_STS_SHIFT                            1
727 #define GPIO5_GPIO_SET_MASK                             0x01
728 #define GPIO5_GPIO_SET_SHIFT                            0
729
730
731 /*Register JTAGVERNUM  (0x80) register.RegisterDescription */
732 #define JTAGVERNUM_VERNUM_MASK                          0x0F
733 #define JTAGVERNUM_VERNUM_SHIFT                         0
734
735
736 /* Register VDDCTRL (0x27) bit definitions */
737 #define VDDCTRL_ST_MASK                                  0x03
738 #define VDDCTRL_ST_SHIFT                                 0
739
740
741 /*Register VDDCTRL_OP  (0x28) bit definitios */
742 #define VDDCTRL_OP_CMD_MASK                              0x80
743 #define VDDCTRL_OP_CMD_SHIFT                             7
744 #define VDDCTRL_OP_SEL_MASK                              0x7F
745 #define VDDCTRL_OP_SEL_SHIFT                             0
746
747
748 /*Register VDDCTRL_SR  (0x29) bit definitions */
749 #define VDDCTRL_SR_SEL_MASK                              0x7F
750 #define VDDCTRL_SR_SEL_SHIFT                             0
751
752
753 /* IRQ Definitions */
754 #define TPS65910_IRQ_VBAT_VMBDCH                        0
755 #define TPS65910_IRQ_VBAT_VMHI                          1
756 #define TPS65910_IRQ_PWRON                              2
757 #define TPS65910_IRQ_PWRON_LP                           3
758 #define TPS65910_IRQ_PWRHOLD                            4
759 #define TPS65910_IRQ_HOTDIE                             5
760 #define TPS65910_IRQ_RTC_ALARM                          6
761 #define TPS65910_IRQ_RTC_PERIOD                         7
762 #define TPS65910_IRQ_GPIO_R                             8
763 #define TPS65910_IRQ_GPIO_F                             9
764 #define TPS65910_NUM_IRQ                                10
765
766 /* GPIO Register Definitions */
767 #define TPS65910_GPIO_DEB                               BIT(2)
768 #define TPS65910_GPIO_PUEN                              BIT(3)
769 #define TPS65910_GPIO_CFG                               BIT(2)
770 #define TPS65910_GPIO_STS                               BIT(1)
771 #define TPS65910_GPIO_SET                               BIT(0)
772
773 /**
774  * struct tps65910_board
775  * Board platform data may be used to initialize regulators.
776  */
777
778 struct tps65910_board {
779         int gpio_base;
780         int irq;
781         int irq_base;
782         struct regulator_init_data *tps65910_pmic_init_data;
783 };
784
785 /**
786  * struct tps65910 - tps65910 sub-driver chip access routines
787  */
788
789 struct tps65910 {
790         struct device *dev;
791         struct i2c_client *i2c_client;
792         struct mutex io_mutex;
793         unsigned int id;
794         int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
795         int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
796
797         /* Client devices */
798         struct tps65910_pmic *pmic;
799         struct tps65910_rtc *rtc;
800         struct tps65910_power *power;
801
802         /* GPIO Handling */
803         struct gpio_chip gpio;
804
805         /* IRQ Handling */
806         struct mutex irq_lock;
807         int chip_irq;
808         int irq_base;
809         u16 irq_mask;
810 };
811
812 struct tps65910_platform_data {
813         int irq;
814         int irq_base;
815 };
816
817 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
818 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
819 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
820 int tps65910_irq_init(struct tps65910 *tps65910, int irq,
821                 struct tps65910_platform_data *pdata);
822
823 static inline int tps65910_chip_id(struct tps65910 *tps65910)
824 {
825         return tps65910->id;
826 }
827
828 #endif /*  __LINUX_MFD_TPS65910_H */