extcon: extcon-palmas: Provision ID status check from VBUS interrupt
[linux-3.10.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011-2013 Texas Instruments Inc.
5  * Copyright (c) 2013-2014, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  * Author: Ian Lartey <ian@slimlogic.co.uk>
9  *
10  *  This program is free software; you can redistribute it and/or modify it
11  *  under  the terms of the GNU General  Public License as published by the
12  *  Free Software Foundation;  either version 2 of the License, or (at your
13  *  option) any later version.
14  *
15  */
16
17 #ifndef __LINUX_MFD_PALMAS_H
18 #define __LINUX_MFD_PALMAS_H
19
20 #include <linux/i2c.h>
21 #include <linux/usb/otg.h>
22 #include <linux/leds.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/driver.h>
25 #include <linux/regulator/machine.h>
26 #include <linux/kthread.h>
27 #include <linux/iio/machine.h>
28 #include <linux/extcon.h>
29 #include <linux/thermal.h>
30
31 #define PALMAS_NUM_CLIENTS      4
32
33 /* Fuel Gauge Constatnts */
34 #define MAX_CAPACITY    0x7fff
35 #define MAX_SOC         100
36 #define MAX_PERCENTAGE  100
37
38 /* Num, cycles with no Learning, after this many cycles, the gauge
39    start adjusting FCC, based on Estimated Cell Degradation */
40 #define NO_LEARNING_CYCLES      25
41
42 /* Size of the OCV Lookup table */
43 #define OCV_TABLE_SIZE  21
44
45 /* OCV Configuration */
46 struct ocv_config {
47         unsigned char voltage_diff;
48         unsigned char current_diff;
49
50         unsigned short sleep_enter_current;
51         unsigned char sleep_enter_samples;
52
53         unsigned short sleep_exit_current;
54         unsigned char sleep_exit_samples;
55
56         unsigned short long_sleep_current;
57
58         unsigned int ocv_period;
59         unsigned int relax_period;
60
61         unsigned char flat_zone_low;
62         unsigned char flat_zone_high;
63
64         unsigned short max_ocv_discharge;
65
66         unsigned short table[OCV_TABLE_SIZE];
67 };
68
69 /* EDV Point */
70 struct edv_point {
71         short voltage;
72         unsigned char percent;
73 };
74
75 /* EDV Point tracking data */
76 struct edv_state {
77         short voltage;
78         unsigned char percent;
79         short min_capacity;
80         unsigned char edv_cmp;
81 };
82
83 /* EDV Configuration */
84 struct edv_config {
85         bool averaging;
86
87         unsigned char seq_edv;
88
89         unsigned char filter_light;
90         unsigned char filter_heavy;
91         short overload_current;
92
93         struct edv_point edv[3];
94 };
95
96 /* General Battery Cell Configuration */
97 struct cell_config {
98         int technology;
99         bool cc_polarity;
100         bool cc_out;
101         bool ocv_below_edv1;
102
103         short cc_voltage;
104         short cc_current;
105         unsigned char cc_capacity;
106         unsigned char seq_cc;
107
108         unsigned short design_capacity;
109         short design_qmax;
110
111         unsigned char r_sense;
112
113         unsigned char qmax_adjust;
114         unsigned char fcc_adjust;
115
116         unsigned short max_overcharge;
117         unsigned short electronics_load; /* *10uAh */
118
119         short max_increment;
120         short max_decrement;
121         unsigned char low_temp;
122         unsigned short deep_dsg_voltage;
123         unsigned short max_dsg_estimate;
124         unsigned char light_load;
125         unsigned short near_full;
126         unsigned short cycle_threshold;
127         unsigned short recharge;
128
129         unsigned char mode_switch_capacity;
130
131         unsigned char call_period;
132
133         struct ocv_config *ocv;
134         struct edv_config *edv;
135 };
136
137 /* Cell State */
138 struct cell_state {
139         short soc;
140
141         short nac;
142
143         short fcc;
144         short qmax;
145
146         short voltage;
147         short av_voltage;
148         short cur;
149         short av_current;
150
151         short temperature;
152         short cycle_count;
153
154         bool sleep;
155         bool relax;
156
157         bool chg;
158         bool dsg;
159
160         bool edv0;
161         bool edv1;
162         bool edv2;
163         bool ocv;
164         bool cc;
165         bool full;
166
167         bool vcq;
168         bool vdq;
169         bool init;
170
171         struct timeval last_correction;
172         struct timeval last_ocv;
173         struct timeval sleep_timer;
174         struct timeval el_timer;
175         unsigned int cumulative_sleep;
176
177         short prev_soc;
178         short learn_q;
179         unsigned short dod_eoc;
180         short learn_offset;
181         unsigned short learned_cycle;
182         short new_fcc;
183         short ocv_total_q;
184         short ocv_enter_q;
185         short negative_q;
186         short overcharge_q;
187         short charge_cycle_q;
188         short discharge_cycle_q;
189         short cycle_q;
190         short top_off_q;
191         unsigned char seq_cc_voltage;
192         unsigned char seq_cc_current;
193         unsigned char sleep_samples;
194         unsigned char seq_edvs;
195
196         unsigned int electronics_load;
197         unsigned short cycle_dsg_estimate;
198
199         struct edv_state edv;
200
201         bool updated;
202         bool calibrate;
203
204         struct cell_config *config;
205         struct device *dev;
206
207         int *charge_status;
208 };
209
210 /* The ID_REVISION NUMBERS */
211 #define PALMAS_CHIP_OLD_ID              0x0000
212 #define PALMAS_CHIP_ID                  0xC035
213 #define PALMAS_CHIP_CHARGER_ID          0xC036
214
215 #define is_palmas(a)    (((a) == PALMAS_CHIP_OLD_ID) || \
216                         ((a) == PALMAS_CHIP_ID))
217 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
218
219 struct palmas_pmic;
220 struct palmas_gpadc;
221 struct palmas_resource;
222 struct palmas_usb;
223 struct palmas_rtc;
224 struct palmas_battery_info;
225
226 #define palmas_rails(_name) "palmas_"#_name
227 #define PALMAS_MAX_FN_REGISTERS         64
228
229 struct palmas {
230         struct device *dev;
231
232         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
233         struct regmap *regmap[PALMAS_NUM_CLIENTS];
234         DECLARE_BITMAP(volatile_smps_registers, PALMAS_MAX_FN_REGISTERS);
235
236         /* Stored chip id */
237         u32 id;
238
239         unsigned int submodule_lists;
240
241         /* IRQ Data */
242         int irq;
243         u32 irq_mask;
244         struct palmas_irq_chip_data *irq_chip_data;
245
246         /* Child Devices */
247         struct palmas_pmic *pmic;
248         struct palmas_gpadc *gpadc;
249         struct palmas_resource *resource;
250         struct palmas_usb *usb;
251         struct palmas_rtc *rtc;
252         struct palmas_battery_info *battery;
253
254         /* GPIO MUXing */
255         u8 ngpio;
256         u16 gpio_muxed;
257         u8 led_muxed;
258         u8 pwm_muxed;
259
260         int design_revision;
261         int sw_otp_version;
262         int es_minor_version;
263         int es_major_version;
264         struct mutex mutex_config0;
265         bool shutdown;
266 };
267
268 /*
269  * ADC auto conv property: Generate auto conv interrupt when threshold crossed.
270  * @adc_channel_number: ADC channel number for monitoring.
271  * @adc_high_threshold: ADC High raw data for upper threshold to generate int.
272  * @adc_low_threshold: ADC low raw data for lower threshold to generate int.
273  * @adc_shutdown: Shutdown when interrupt generated.
274  */
275 struct palmas_adc_auto_conv_property {
276         int adc_channel_number;
277         int adc_high_threshold;
278         int adc_low_threshold;
279         bool adc_shutdown;
280 };
281
282 struct palmas_gpadc_platform_data {
283         /* Channel 3 current source is only enabled during conversion */
284         int ch3_current;
285
286         /* Channel 0 current source can be used for battery detection.
287          * If used for battery detection this will cause a permanent current
288          * consumption depending on current level set here.
289          */
290         int ch0_current;
291         bool ch3_dual_current;
292         bool extended_delay;
293
294         /* default BAT_REMOVAL_DAT setting on device probe */
295         int bat_removal;
296
297         /* Sets the START_POLARITY bit in the RT_CTRL register */
298         int start_polarity;
299
300         struct iio_map *iio_maps;
301         int auto_conversion_period_ms;
302         struct palmas_adc_auto_conv_property *adc_auto_conv0_data;
303         struct palmas_adc_auto_conv_property *adc_auto_conv1_data;
304 };
305
306 struct palmas_reg_init {
307         /* warm_rest controls the voltage levels after a warm reset
308          *
309          * 0: reload default values from OTP on warm reset
310          * 1: maintain voltage from VSEL on warm reset
311          */
312         int warm_reset;
313
314         /* roof_floor controls whether the regulator uses the i2c style
315          * of DVS or uses the method where a GPIO or other control method is
316          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
317          *
318          * For SMPS
319          *
320          * 0: i2c selection of voltage
321          * 1: pin selection of voltage.
322          *
323          * For LDO unused
324          */
325         int roof_floor;
326
327         /*
328          * If the rail is externally controlled and the external signal is
329          * connected to gpios of the SoCs then this can be provided by
330          * enable_gpio;
331          */
332         int enable_gpio;
333
334         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
335          * the data sheet.
336          *
337          * For SMPS
338          *
339          * 0: Off
340          * 1: AUTO
341          * 2: ECO
342          * 3: Forced PWM
343          *
344          * For LDO
345          *
346          * 0: Off
347          * 1: On
348          */
349         int mode_sleep;
350
351         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
352          * register. Set this is the default voltage set in OTP needs
353          * to be overridden.
354          */
355         u8 vsel;
356
357         /* Configuration flags */
358         unsigned int config_flags;
359
360         /*
361          * tracking_regulator will tell which regulator will be tracked
362          * This will be used when regulator tracking is enabled and
363          * device supports.
364          */
365         int tracking_regulator;
366
367         /*
368          * disable active discharge on idle. This will keep disablign active
369          * discharge on idle state and enable on suspend/shutdown.
370          */
371         bool disable_active_discharge_idle;
372
373         /* Disable pull down for SMPS/LDO */
374         bool disable_pull_down;
375
376         /* Set regulator on bypass mode when it is more than bypass voltage */
377         int bypass_voltage;
378 };
379
380 enum palmas_regulators {
381         /* SMPS regulators */
382         PALMAS_REG_SMPS12,
383         PALMAS_REG_SMPS123,
384         PALMAS_REG_SMPS3,
385         PALMAS_REG_SMPS45,
386         PALMAS_REG_SMPS457,
387         PALMAS_REG_SMPS6,
388         PALMAS_REG_SMPS7,
389         PALMAS_REG_SMPS8,
390         PALMAS_REG_SMPS9,
391         PALMAS_REG_SMPS10_OUT2,
392         PALMAS_REG_SMPS10_OUT1,
393         /* LDO regulators */
394         PALMAS_REG_LDO1,
395         PALMAS_REG_LDO2,
396         PALMAS_REG_LDO3,
397         PALMAS_REG_LDO4,
398         PALMAS_REG_LDO5,
399         PALMAS_REG_LDO6,
400         PALMAS_REG_LDO7,
401         PALMAS_REG_LDO8,
402         PALMAS_REG_LDO9,
403         PALMAS_REG_LDO10,
404         PALMAS_REG_LDO11,
405         PALMAS_REG_LDO12,
406         PALMAS_REG_LDO13,
407         PALMAS_REG_LDO14,
408         PALMAS_REG_LDOLN,
409         PALMAS_REG_LDOUSB,
410         /* External regulators */
411         PALMAS_REG_REGEN1,
412         PALMAS_REG_REGEN2,
413         PALMAS_REG_REGEN3,
414         PALMAS_REG_REGEN4,
415         PALMAS_REG_REGEN5,
416         PALMAS_REG_REGEN7,
417         PALMAS_REG_SYSEN1,
418         PALMAS_REG_SYSEN2,
419         PALMAS_REG_CHARGER_PUMP,
420         /* Total number of regulators */
421         PALMAS_NUM_REGS,
422 };
423
424 enum palmas_chip_id {
425         PALMAS,
426         TWL6035,
427         TWL6037,
428         TPS65913,
429         TPS80036,
430         PALMAS_MAX_CHIP_ID,
431 };
432
433 enum PALMAS_CLOCK32K {
434         PALMAS_CLOCK32KG,
435         PALMAS_CLOCK32KG_AUDIO,
436
437         /* Last entry */
438         PALMAS_CLOCK32K_NR,
439 };
440
441 struct palmas_clk32k_init_data {
442         int clk32k_id;
443         bool enable;
444         int sleep_control;
445 };
446
447 struct palmas_dvfs_init_data {
448         bool    en_pwm;
449         int     ext_ctrl;
450         int     reg_id;
451         bool    step_20mV;
452         int     base_voltage_uV;
453         int     max_voltage_uV;
454         bool    smps3_ctrl;
455 };
456
457 struct palmas_pmic_platform_data {
458         /* An array of pointers to regulator init data indexed by regulator
459          * ID
460          */
461         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
462
463         /* An array of pointers to structures containing sleep mode and DVS
464          * configuration for regulators indexed by ID
465          */
466         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
467
468         /* CL DVFS init data */
469         struct palmas_dvfs_init_data *dvfs_init_data;
470         int dvfs_init_data_size;
471
472         /* use LDO6 for vibrator control */
473         int ldo6_vibrator;
474
475         bool disable_smps10_boost_suspend;
476 };
477
478 struct palmas_usb_platform_data {
479         /* Set this if platform wishes its own vbus control */
480         int no_control_vbus;
481
482         /* Do we enable the wakeup comparator on probe */
483         int wakeup;
484 };
485
486 struct palmas_resource_platform_data {
487         int regen1_mode_sleep;
488         int regen2_mode_sleep;
489         int sysen1_mode_sleep;
490         int sysen2_mode_sleep;
491
492         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
493         u8 nsleep_res;
494         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
495         u8 nsleep_smps;
496         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
497         u8 nsleep_ldo1;
498         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
499         u8 nsleep_ldo2;
500
501         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
502         u8 enable1_res;
503         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
504         u8 enable1_smps;
505         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
506         u8 enable1_ldo1;
507         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
508         u8 enable1_ldo2;
509
510         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
511         u8 enable2_res;
512         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
513         u8 enable2_smps;
514         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
515         u8 enable2_ldo1;
516         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
517         u8 enable2_ldo2;
518 };
519
520 struct palmas_clk_platform_data {
521         int clk32kg_mode_sleep;
522         int clk32kgaudio_mode_sleep;
523 };
524
525 struct palmas_vbus_platform_data {
526         int num_consumer_supplies;
527         struct regulator_consumer_supply *consumer_supplies;
528 };
529
530 struct palmas_bcharger_platform_data {
531         const char *battery_tz_name;
532         int max_charge_volt_mV;
533         int max_charge_current_mA;
534         int charging_term_current_mA;
535         int wdt_timeout;
536         int rtc_alarm_time;
537         int num_consumer_supplies;
538         struct regulator_consumer_supply *consumer_supplies;
539         int chg_restart_time;
540         int temperature_poll_period_secs;
541 };
542
543 struct palmas_charger_platform_data {
544         struct palmas_vbus_platform_data *vbus_pdata;
545         struct palmas_bcharger_platform_data *bcharger_pdata;
546 };
547
548
549 struct palmas_rtc_platform_data {
550         bool backup_battery_chargeable;
551         bool backup_battery_charge_high_current;
552 };
553
554 struct palmas_pm_platform_data {
555         bool use_power_off;
556         bool use_power_reset;
557 };
558
559 struct palmas_pinctrl_config {
560         const char *pin;
561         const char *function;
562         const char *prop_bias_pull;
563         const char *prop_open_drain;
564 };
565
566 struct palmas_pinctrl_platform_data {
567         struct palmas_pinctrl_config *pincfg;
568         int num_pinctrl;
569         bool dvfs1_enable;
570         bool dvfs2_enable;
571 };
572
573 struct palmas_extcon_platform_data {
574         const char *connection_name;
575         bool enable_vbus_detection;
576         bool enable_id_pin_detection;
577         /* Do we enable the wakeup comparator on probe */
578         int wakeup;
579 };
580
581 struct palmas_battery_platform_data {
582         const char *therm_zone_name;
583         /* Battery Values */
584         int battery_soldered; /* if battery detection should not be used */
585         int battery_status_interval; /* time in ms for charge status polling */
586         int *battery_temperature_chart;
587         int battery_temperature_chart_size;
588         int gpadc_retry_count;
589
590
591         /* Fuelgauge Config */
592         int current_avg_interval;
593         struct cell_config *cell_cfg;
594         int is_battery_present;
595         bool enable_ovc_alarm;
596         int ovc_period;
597         int ovc_threshold;
598 };
599
600 struct palmas_sim_platform_data {
601         unsigned dbcnt:5;
602         unsigned pwrdncnt:5;
603         unsigned pwrdnen1:1;
604         unsigned pwrdnen2:1;
605         unsigned det_polarity:1;
606         unsigned det1_pu:1;
607         unsigned det1_pd:1;
608         unsigned det2_pu:1;
609         unsigned det2_pd:1;
610 };
611
612 struct palmas_ldousb_in_platform_data {
613         u32 ldousb_in_threshold_voltage;
614         u32 threshold_voltage_tolerance;
615         bool enable_in1_above_threshold;
616 };
617
618 struct palmas_platform_data {
619         int irq_flags;
620         int gpio_base;
621         int irq_base;
622
623         /* bit value to be loaded to the POWER_CTRL register */
624         u8 power_ctrl;
625
626         struct palmas_pmic_platform_data *pmic_pdata;
627         struct palmas_gpadc_platform_data *gpadc_pdata;
628         struct palmas_usb_platform_data *usb_pdata;
629         struct palmas_resource_platform_data *resource_pdata;
630         struct palmas_clk_platform_data *clk_pdata;
631         struct palmas_rtc_platform_data *rtc_pdata;
632         struct palmas_pm_platform_data *pm_pdata;
633         struct palmas_battery_platform_data *battery_pdata;
634         struct palmas_sim_platform_data *sim_pdata;
635         struct palmas_ldousb_in_platform_data  *ldousb_in_pdata;
636
637         struct palmas_clk32k_init_data  *clk32k_init_data;
638         int clk32k_init_data_size;
639         /* LDOUSB is enabled or disabled on VBUS detection */
640         bool auto_ldousb_en;
641
642         struct palmas_pinctrl_platform_data *pinctrl_pdata;
643         struct palmas_extcon_platform_data *extcon_pdata;
644         struct palmas_charger_platform_data *charger_pdata;
645
646         int watchdog_timer_initial_period;
647
648         /* Hotdie Threshold temperature */
649         unsigned long hd_threshold_temp;
650         char *tz_name;
651
652         /* Long press delay for hard shutdown */
653         int long_press_delay;
654 };
655
656 struct palmas_gpadc_result {
657         s32 raw_code;
658         s32 corrected_code;
659         s32 result;
660 };
661
662 #define PALMAS_MAX_CHANNELS 16
663
664 /* Define the palmas IRQ numbers */
665 enum palmas_irqs {
666         /* INT1 registers */
667         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
668         PALMAS_PWRON_IRQ,
669         PALMAS_LONG_PRESS_KEY_IRQ,
670         PALMAS_RPWRON_IRQ,
671         PALMAS_PWRDOWN_IRQ,
672         PALMAS_HOTDIE_IRQ,
673         PALMAS_VSYS_MON_IRQ,
674         PALMAS_VBAT_MON_IRQ,
675         /* INT2 registers */
676         PALMAS_RTC_ALARM_IRQ,
677         PALMAS_RTC_TIMER_IRQ,
678         PALMAS_WDT_IRQ,
679         PALMAS_BATREMOVAL_IRQ,
680         PALMAS_RESET_IN_IRQ,
681         PALMAS_FBI_BB_IRQ,
682         PALMAS_SHORT_IRQ,
683         PALMAS_VAC_ACOK_IRQ,
684         /* INT3 registers */
685         PALMAS_GPADC_AUTO_0_IRQ,
686         PALMAS_GPADC_AUTO_1_IRQ,
687         PALMAS_GPADC_EOC_SW_IRQ,
688         PALMAS_GPADC_EOC_RT_IRQ,
689         PALMAS_ID_OTG_IRQ,
690         PALMAS_ID_IRQ,
691         PALMAS_VBUS_OTG_IRQ,
692         PALMAS_VBUS_IRQ,
693         /* INT4 registers */
694         PALMAS_GPIO_0_IRQ,
695         PALMAS_GPIO_1_IRQ,
696         PALMAS_GPIO_2_IRQ,
697         PALMAS_GPIO_3_IRQ,
698         PALMAS_GPIO_4_IRQ,
699         PALMAS_GPIO_5_IRQ,
700         PALMAS_GPIO_6_IRQ,
701         PALMAS_GPIO_7_IRQ,
702         /* INT5 registers */
703         PALMAS_GPIO_8_IRQ,
704         PALMAS_GPIO_9_IRQ,
705         PALMAS_GPIO_10_IRQ,
706         PALMAS_GPIO_11_IRQ,
707         PALMAS_GPIO_12_IRQ,
708         PALMAS_GPIO_13_IRQ,
709         PALMAS_GPIO_14_IRQ,
710         PALMAS_GPIO_15_IRQ,
711         /* INT6 interrupts */
712         PALMAS_CHARGER_IRQ,
713         PALMAS_SIM1_IRQ,
714         PALMAS_SIM2_IRQ,
715         /* INT7 interrupts */
716         PALMAS_BAT_TEMP_FAULT_IRQ,
717         /* Total Number IRQs */
718         PALMAS_NUM_IRQ,
719 };
720
721 struct palmas_pmic {
722         struct palmas *palmas;
723         struct device *dev;
724         struct regulator_desc desc[PALMAS_NUM_REGS];
725         struct regulator_dev *rdev[PALMAS_NUM_REGS];
726         struct mutex mutex;
727
728         int smps123;
729         int smps457;
730         int irq;
731         bool smps10_regulator_enabled;
732         int ldo_vref0p425;
733         bool smps10_boost_disable_deferred;
734         bool shutdown;
735
736         int range[PALMAS_REG_SMPS10_OUT1];
737         unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
738         bool ramp_delay_support[PALMAS_NUM_REGS];
739         unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
740         unsigned long config_flags[PALMAS_NUM_REGS];
741         bool disable_active_discharge_idle[PALMAS_NUM_REGS];
742         bool disable_pull_down[PALMAS_NUM_REGS];
743         struct palmas_pmic_platform_data *pdata;
744 };
745
746 struct palmas_resource {
747         struct palmas *palmas;
748         struct device *dev;
749 };
750
751 enum palmas_usb_state {
752         PALMAS_USB_STATE_INIT,
753         PALMAS_USB_STATE_DISCONNECT,
754         PALMAS_USB_STATE_ID_FLOAT = PALMAS_USB_STATE_DISCONNECT,
755         PALMAS_USB_STATE_VBUS,
756         PALMAS_USB_STATE_ID_GND,
757         PALMAS_USB_STATE_ID_A,
758         PALMAS_USB_STATE_ID_B,
759         PALMAS_USB_STATE_ID_C,
760 };
761
762 struct palmas_usb {
763         struct palmas *palmas;
764         struct device *dev;
765
766         struct extcon_dev edev;
767
768         int id_otg_irq;
769         int id_irq;
770         int vbus_otg_irq;
771         int vbus_irq;
772
773         enum palmas_usb_state id_linkstat;
774         enum palmas_usb_state vbus_linkstat;
775         int wakeup;
776         bool enable_vbus_detection;
777         bool enable_id_detection;
778         bool enable_id_detect_on_vbus;
779         struct delayed_work cable_update_wq;
780         int cable_debounce_time;
781         int cur_cable_index;
782 };
783
784 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
785
786 enum usb_irq_events {
787         /* Wakeup events from INT3 */
788         PALMAS_USB_ID_WAKEPUP,
789         PALMAS_USB_VBUS_WAKEUP,
790
791         /* ID_OTG_EVENTS */
792         PALMAS_USB_ID_GND,
793         N_PALMAS_USB_ID_GND,
794         PALMAS_USB_ID_C,
795         N_PALMAS_USB_ID_C,
796         PALMAS_USB_ID_B,
797         N_PALMAS_USB_ID_B,
798         PALMAS_USB_ID_A,
799         N_PALMAS_USB_ID_A,
800         PALMAS_USB_ID_FLOAT,
801         N_PALMAS_USB_ID_FLOAT,
802
803         /* VBUS_OTG_EVENTS */
804         PALMAS_USB_VB_SESS_END,
805         N_PALMAS_USB_VB_SESS_END,
806         PALMAS_USB_VB_SESS_VLD,
807         N_PALMAS_USB_VB_SESS_VLD,
808         PALMAS_USB_VA_SESS_VLD,
809         N_PALMAS_USB_VA_SESS_VLD,
810         PALMAS_USB_VA_VBUS_VLD,
811         N_PALMAS_USB_VA_VBUS_VLD,
812         PALMAS_USB_VADP_SNS,
813         N_PALMAS_USB_VADP_SNS,
814         PALMAS_USB_VADP_PRB,
815         N_PALMAS_USB_VADP_PRB,
816         PALMAS_USB_VOTG_SESS_VLD,
817         N_PALMAS_USB_VOTG_SESS_VLD,
818 };
819
820 /* defines so we can store the mux settings */
821 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
822 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
823 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
824 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
825 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
826 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
827 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
828 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
829 #define PALMAS_GPIO_8_MUXED                                     (1 << 8)
830 #define PALMAS_GPIO_9_MUXED                                     (1 << 9)
831 #define PALMAS_GPIO_10_MUXED                                    (1 << 10)
832 #define PALMAS_GPIO_11_MUXED                                    (1 << 11)
833 #define PALMAS_GPIO_12_MUXED                                    (1 << 12)
834 #define PALMAS_GPIO_13_MUXED                                    (1 << 13)
835 #define PALMAS_GPIO_14_MUXED                                    (1 << 14)
836 #define PALMAS_GPIO_15_MUXED                                    (1 << 15)
837
838 #define PALMAS_LED1_MUXED                                       (1 << 0)
839 #define PALMAS_LED2_MUXED                                       (1 << 1)
840
841 #define PALMAS_PWM1_MUXED                                       (1 << 0)
842 #define PALMAS_PWM2_MUXED                                       (1 << 1)
843
844 /* helper macro to get correct slave number */
845 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
846 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
847 #define PALMAS_REG_TO_FN_ADDR(x, y)     ((y) - ((x) & 0xff))
848 #define RTC_SLAVE                       0
849
850 /* Base addresses of IP blocks in Palmas */
851 #define PALMAS_SMPS_DVS_BASE                                    0x20
852 #define PALMAS_RTC_BASE                                         0x100
853 #define PALMAS_VALIDITY_BASE                                    0x118
854 #define PALMAS_SMPS_BASE                                        0x120
855 #define PALMAS_LDO_BASE                                         0x150
856 #define PALMAS_DVFS_BASE                                        0x180
857 #define PALMAS_SIMCARD_BASE                                     0X19E
858 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
859 #define PALMAS_RESOURCE_BASE                                    0x1D4
860 #define PALMAS_PU_PD_OD_BASE                                    0x1F0
861 #define PALMAS_LED_BASE                                         0x200
862 #define PALMAS_INTERRUPT_BASE                                   0x210
863 #define PALMAS_FUEL_GAUGE_BASE                                  0x230
864 #define PALMAS_USB_OTG_BASE                                     0x250
865 #define PALMAS_VIBRATOR_BASE                                    0x270
866 #define PALMAS_GPIO_BASE                                        0x280
867 #define PALMAS_USB_BASE                                         0x290
868 #define PALMAS_GPADC_BASE                                       0x2C0
869 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
870 #define PALMAS_PAGE3_BASE                                       0x300
871 #define PALMAS_CHARGER_BASE                                     0x400
872
873 #define PALMAS_CHARGE_PUMP_CTRL                                 0x7C
874 /* Bit definitions for CHARGE_PUMP_CTRL */
875 #define  PALMAS_PALMAS_CHARGE_PUMP_CTRL_STATUS                  0x10
876 #define PALMAS_CHARGE_PUMP_CTRL_STATUS_SHIFT                    4
877 #define PALMAS_CHARGE_PUMP_CTRL_MODE_SLEEP                      0x04
878 #define PALMAS_CHARGE_PUMP_CTRL_MODE_SLEEP_SHIFT                2
879 #define PALMAS_CHARGE_PUMP_CTRL_MODE_ACTIVE                     0x01
880 #define PALMAS_CHARGE_PUMP_CTRL_MODE_ACTIVE_SHIFT               0
881
882 /* Registers for function RTC */
883 #define PALMAS_SECONDS_REG                                      0x0
884 #define PALMAS_MINUTES_REG                                      0x1
885 #define PALMAS_HOURS_REG                                        0x2
886 #define PALMAS_DAYS_REG                                         0x3
887 #define PALMAS_MONTHS_REG                                       0x4
888 #define PALMAS_YEARS_REG                                        0x5
889 #define PALMAS_WEEKS_REG                                        0x6
890 #define PALMAS_ALARM_SECONDS_REG                                0x8
891 #define PALMAS_ALARM_MINUTES_REG                                0x9
892 #define PALMAS_ALARM_HOURS_REG                                  0xA
893 #define PALMAS_ALARM_DAYS_REG                                   0xB
894 #define PALMAS_ALARM_MONTHS_REG                                 0xC
895 #define PALMAS_ALARM_YEARS_REG                                  0xD
896 #define PALMAS_RTC_CTRL_REG                                     0x10
897 #define PALMAS_RTC_STATUS_REG                                   0x11
898 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
899 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
900 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
901 #define PALMAS_RTC_RES_PROG_REG                                 0x15
902 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
903
904 /* Bit definitions for SECONDS_REG */
905 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
906 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
907 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
908 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
909
910 /* Bit definitions for MINUTES_REG */
911 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
912 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
913 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
914 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
915
916 /* Bit definitions for HOURS_REG */
917 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
918 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
919 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
920 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
921 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
922 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
923
924 /* Bit definitions for DAYS_REG */
925 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
926 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
927 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
928 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
929
930 /* Bit definitions for MONTHS_REG */
931 #define PALMAS_MONTHS_REG_MONTH1                                0x10
932 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
933 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
934 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
935
936 /* Bit definitions for YEARS_REG */
937 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
938 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
939 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
940 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
941
942 /* Bit definitions for WEEKS_REG */
943 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
944 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
945
946 /* Bit definitions for ALARM_SECONDS_REG */
947 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
948 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
949 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
950 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
951
952 /* Bit definitions for ALARM_MINUTES_REG */
953 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
954 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
955 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
956 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
957
958 /* Bit definitions for ALARM_HOURS_REG */
959 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
960 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
961 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
962 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
963 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
964 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
965
966 /* Bit definitions for ALARM_DAYS_REG */
967 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
968 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
969 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
970 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
971
972 /* Bit definitions for ALARM_MONTHS_REG */
973 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
974 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
975 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
976 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
977
978 /* Bit definitions for ALARM_YEARS_REG */
979 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
980 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
981 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
982 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
983
984 /* Bit definitions for RTC_CTRL_REG */
985 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
986 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
987 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
988 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
989 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
990 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
991 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
992 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
993 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
994 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
995 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
996 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
997 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
998 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
999 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
1000 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
1001
1002 /* Bit definitions for RTC_STATUS_REG */
1003 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
1004 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
1005 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
1006 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
1007 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
1008 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
1009 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
1010 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
1011 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
1012 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
1013 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
1014 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
1015 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
1016 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
1017
1018 /* Bit definitions for RTC_INTERRUPTS_REG */
1019 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
1020 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
1021 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
1022 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
1023 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
1024 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
1025 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
1026 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
1027
1028 /* Bit definitions for RTC_COMP_LSB_REG */
1029 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
1030 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
1031
1032 /* Bit definitions for RTC_COMP_MSB_REG */
1033 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
1034 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
1035
1036 /* Bit definitions for RTC_RES_PROG_REG */
1037 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
1038 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
1039
1040 /* Bit definitions for RTC_RESET_STATUS_REG */
1041 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
1042 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
1043
1044 /* Registers for function BACKUP */
1045 #define PALMAS_BACKUP0                                          0x0
1046 #define PALMAS_BACKUP1                                          0x1
1047 #define PALMAS_BACKUP2                                          0x2
1048 #define PALMAS_BACKUP3                                          0x3
1049 #define PALMAS_BACKUP4                                          0x4
1050 #define PALMAS_BACKUP5                                          0x5
1051 #define PALMAS_BACKUP6                                          0x6
1052 #define PALMAS_BACKUP7                                          0x7
1053
1054 /* Bit definitions for BACKUP0 */
1055 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
1056 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
1057
1058 /* Bit definitions for BACKUP1 */
1059 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
1060 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
1061
1062 /* Bit definitions for BACKUP2 */
1063 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
1064 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
1065
1066 /* Bit definitions for BACKUP3 */
1067 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
1068 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
1069
1070 /* Bit definitions for BACKUP4 */
1071 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
1072 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
1073
1074 /* Bit definitions for BACKUP5 */
1075 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
1076 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
1077
1078 /* Bit definitions for BACKUP6 */
1079 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
1080 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
1081
1082 /* Bit definitions for BACKUP7 */
1083 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
1084 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
1085
1086 /* Registers for function SMPS */
1087 #define PALMAS_SMPS12_CTRL                                      0x0
1088 #define PALMAS_SMPS12_TSTEP                                     0x1
1089 #define PALMAS_SMPS12_FORCE                                     0x2
1090 #define PALMAS_SMPS12_VOLTAGE                                   0x3
1091 #define PALMAS_SMPS3_CTRL                                       0x4
1092 #define PALMAS_SMPS3_TSTEP                                      0x5
1093 #define PALMAS_SMPS3_FORCE                                      0x6
1094 #define PALMAS_SMPS3_VOLTAGE                                    0x7
1095 #define PALMAS_SMPS45_CTRL                                      0x8
1096 #define PALMAS_SMPS45_TSTEP                                     0x9
1097 #define PALMAS_SMPS45_FORCE                                     0xA
1098 #define PALMAS_SMPS45_VOLTAGE                                   0xB
1099 #define PALMAS_SMPS6_CTRL                                       0xC
1100 #define PALMAS_SMPS6_TSTEP                                      0xD
1101 #define PALMAS_SMPS6_FORCE                                      0xE
1102 #define PALMAS_SMPS6_VOLTAGE                                    0xF
1103 #define PALMAS_SMPS7_CTRL                                       0x10
1104 #define PALMAS_SMPS7_VOLTAGE                                    0x13
1105 #define PALMAS_SMPS8_CTRL                                       0x14
1106 #define PALMAS_SMPS8_TSTEP                                      0x15
1107 #define PALMAS_SMPS8_FORCE                                      0x16
1108 #define PALMAS_SMPS8_VOLTAGE                                    0x17
1109 #define PALMAS_SMPS9_CTRL                                       0x18
1110 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
1111 #define PALMAS_SMPS10_CTRL                                      0x1C
1112 #define PALMAS_SMPS10_STATUS                                    0x1F
1113 #define PALMAS_SMPS_CTRL                                        0x24
1114 #define PALMAS_SMPS_PD_CTRL                                     0x25
1115 #define PALMAS_SMPS_DITHER_EN                                   0x26
1116 #define PALMAS_SMPS_THERMAL_EN                                  0x27
1117 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
1118 #define PALMAS_SMPS_SHORT_STATUS                                0x29
1119 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
1120 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
1121 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
1122
1123 /* Bit definitions for SMPS12_CTRL */
1124 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
1125 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
1126 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
1127 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
1128 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
1129 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
1130 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
1131 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
1132 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
1133 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
1134
1135 /* Bit definitions for SMPS12_TSTEP */
1136 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
1137 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
1138
1139 /* Bit definitions for SMPS12_FORCE */
1140 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
1141 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
1142 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
1143 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
1144
1145 /* Bit definitions for SMPS12_VOLTAGE */
1146 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
1147 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
1148 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
1149 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
1150
1151 /* Bit definitions for SMPS3_CTRL */
1152 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
1153 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
1154 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
1155 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
1156 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
1157 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
1158 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
1159 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
1160
1161 /* Bit definitions for SMPS3_VOLTAGE */
1162 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
1163 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
1164 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
1165 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
1166
1167 /* Bit definitions for SMPS45_CTRL */
1168 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
1169 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
1170 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
1171 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
1172 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
1173 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
1174 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
1175 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
1176 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
1177 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
1178
1179 /* Bit definitions for SMPS45_TSTEP */
1180 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
1181 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
1182
1183 /* Bit definitions for SMPS45_FORCE */
1184 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
1185 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
1186 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
1187 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
1188
1189 /* Bit definitions for SMPS45_VOLTAGE */
1190 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
1191 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
1192 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
1193 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
1194
1195 /* Bit definitions for SMPS6_CTRL */
1196 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
1197 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
1198 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
1199 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
1200 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
1201 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
1202 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
1203 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
1204 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
1205 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
1206
1207 /* Bit definitions for SMPS6_TSTEP */
1208 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
1209 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
1210
1211 /* Bit definitions for SMPS6_FORCE */
1212 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
1213 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
1214 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
1215 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
1216
1217 /* Bit definitions for SMPS6_VOLTAGE */
1218 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
1219 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
1220 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
1221 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
1222
1223 /* Bit definitions for SMPS7_CTRL */
1224 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
1225 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
1226 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
1227 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
1228 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
1229 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
1230 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
1231 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
1232
1233 /* Bit definitions for SMPS7_VOLTAGE */
1234 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
1235 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
1236 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
1237 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
1238
1239 /* Bit definitions for SMPS8_CTRL */
1240 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
1241 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
1242 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
1243 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
1244 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
1245 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
1246 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
1247 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
1248 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
1249 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
1250
1251 /* Bit definitions for SMPS8_TSTEP */
1252 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
1253 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
1254
1255 /* Bit definitions for SMPS8_FORCE */
1256 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
1257 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
1258 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
1259 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
1260
1261 /* Bit definitions for SMPS8_VOLTAGE */
1262 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
1263 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
1264 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
1265 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
1266
1267 /* Bit definitions for SMPS9_CTRL */
1268 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
1269 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
1270 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
1271 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
1272 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
1273 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
1274 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
1275 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
1276
1277 /* Bit definitions for SMPS9_VOLTAGE */
1278 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
1279 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
1280 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
1281 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
1282
1283 /* Bit definitions for SMPS10_CTRL */
1284 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
1285 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
1286 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
1287 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
1288
1289 /* Bit definitions for SMPS10_STATUS */
1290 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
1291 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
1292
1293 /* Bit definitions for SMPS_CTRL */
1294 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
1295 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
1296 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
1297 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
1298 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
1299 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
1300 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
1301 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
1302
1303 /* Bit definitions for SMPS_PD_CTRL */
1304 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
1305 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
1306 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
1307 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
1308 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
1309 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
1310 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
1311 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
1312 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
1313 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
1314 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
1315 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
1316 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
1317 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
1318
1319 /* Bit definitions for SMPS_THERMAL_EN */
1320 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
1321 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
1322 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
1323 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
1324 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
1325 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
1326 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
1327 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
1328 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
1329 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
1330
1331 /* Bit definitions for SMPS_THERMAL_STATUS */
1332 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
1333 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
1334 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
1335 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
1336 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
1337 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
1338 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
1339 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
1340 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
1341 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
1342
1343 /* Bit definitions for SMPS_SHORT_STATUS */
1344 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
1345 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
1346 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
1347 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
1348 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
1349 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
1350 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
1351 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
1352 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
1353 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
1354 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
1355 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
1356 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
1357 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
1358 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
1359 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
1360
1361 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1362 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
1363 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
1364 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
1365 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
1366 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
1367 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
1368 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
1369 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
1370 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
1371 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
1372 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
1373 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
1374 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
1375 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
1376
1377 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1378 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
1379 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
1380 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
1381 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
1382 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
1383 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
1384 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
1385 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
1386 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
1387 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
1388 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
1389 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
1390 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
1391 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
1392 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
1393 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
1394
1395 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1396 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
1397 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
1398 #define PALMAS_SMPS_POWERGOOD_MASK2_OVC_ALARM                   0x10
1399 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
1400 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
1401 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
1402 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
1403 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
1404 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
1405
1406 /* Registers for function LDO */
1407 #define PALMAS_LDO1_CTRL                                        0x0
1408 #define PALMAS_LDO1_VOLTAGE                                     0x1
1409 #define PALMAS_LDO2_CTRL                                        0x2
1410 #define PALMAS_LDO2_VOLTAGE                                     0x3
1411 #define PALMAS_LDO3_CTRL                                        0x4
1412 #define PALMAS_LDO3_VOLTAGE                                     0x5
1413 #define PALMAS_LDO4_CTRL                                        0x6
1414 #define PALMAS_LDO4_VOLTAGE                                     0x7
1415 #define PALMAS_LDO5_CTRL                                        0x8
1416 #define PALMAS_LDO5_VOLTAGE                                     0x9
1417 #define PALMAS_LDO6_CTRL                                        0xA
1418 #define PALMAS_LDO6_VOLTAGE                                     0xB
1419 #define PALMAS_LDO7_CTRL                                        0xC
1420 #define PALMAS_LDO7_VOLTAGE                                     0xD
1421 #define PALMAS_LDO8_CTRL                                        0xE
1422 #define PALMAS_LDO8_VOLTAGE                                     0xF
1423 #define PALMAS_LDO9_CTRL                                        0x10
1424 #define PALMAS_LDO9_VOLTAGE                                     0x11
1425 #define PALMAS_LDOLN_CTRL                                       0x12
1426 #define PALMAS_LDOLN_VOLTAGE                                    0x13
1427 #define PALMAS_LDOUSB_CTRL                                      0x14
1428 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
1429 #define PALMAS_LDO10_CTRL                                       0x16
1430 #define PALMAS_LDO10_VOLTAGE                                    0x17
1431 #define PALMAS_LDO11_CTRL                                       0x18
1432 #define PALMAS_LDO11_VOLTAGE                                    0x19
1433 #define PALMAS_LDO12_CTRL                                       0x1F
1434 #define PALMAS_LDO12_VOLTAGE                                    0x20
1435 #define PALMAS_LDO13_CTRL                                       0x21
1436 #define PALMAS_LDO13_VOLTAGE                                    0x22
1437 #define PALMAS_LDO14_CTRL                                       0x23
1438 #define PALMAS_LDO14_VOLTAGE                                    0x24
1439 #define PALMAS_LDO_CTRL                                         0x1A
1440 #define PALMAS_LDO_PD_CTRL1                                     0x1B
1441 #define PALMAS_LDO_PD_CTRL2                                     0x1C
1442 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
1443 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
1444
1445 /* Bit definitions for LDO1_CTRL */
1446 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
1447 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
1448 #define PALMAS_LDO1_CTRL_LDO_BYPASS_EN                          0x40
1449 #define PALMAS_LDO1_CTRL_LDO_BYPASS_EN_SHIFT                    6
1450 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
1451 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
1452 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
1453 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
1454 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
1455 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
1456
1457 /* Bit definitions for LDO1_VOLTAGE */
1458 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
1459 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
1460
1461 /* Bit definitions for LDO2_CTRL */
1462 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1463 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
1464 #define PALMAS_LDO2_CTRL_LDO_BYPASS_EN                          0x40
1465 #define PALMAS_LDO2_CTRL_LDO_BYPASS_EN_SHIFT                    6
1466 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1467 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
1468 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1469 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
1470 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1471 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
1472
1473 /* Bit definitions for LDO2_VOLTAGE */
1474 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
1475 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
1476
1477 /* Bit definitions for LDO3_CTRL */
1478 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1479 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
1480 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1481 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
1482 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1483 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
1484 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1485 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
1486
1487 /* Bit definitions for LDO3_VOLTAGE */
1488 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
1489 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
1490
1491 /* Bit definitions for LDO4_CTRL */
1492 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1493 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
1494 #define PALMAS_LDO4_CTRL_LDO_BYPASS_EN                          0x40
1495 #define PALMAS_LDO4_CTRL_LDO_BYPASS_EN_SHIFT                    6
1496 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1497 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
1498 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1499 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
1500 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1501 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
1502
1503 /* Bit definitions for LDO4_VOLTAGE */
1504 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
1505 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
1506
1507 /* Bit definitions for LDO5_CTRL */
1508 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1509 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1510 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1511 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1512 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1513 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1514 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1515 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1516
1517 /* Bit definitions for LDO5_VOLTAGE */
1518 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1519 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1520
1521 /* Bit definitions for LDO6_CTRL */
1522 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1523 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1524 #define PALMAS_LDO6_CTRL_LDO_BYPASS_EN                          0x40
1525 #define PALMAS_LDO6_CTRL_LDO_BYPASS_EN_SHIFT                    6
1526 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1527 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1528 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1529 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1530 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1531 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1532 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1533 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1534
1535 /* Bit definitions for LDO6_VOLTAGE */
1536 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1537 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1538
1539 /* Bit definitions for LDO7_CTRL */
1540 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1541 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1542 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1543 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1544 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1545 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1546 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1547 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1548
1549 /* Bit definitions for LDO7_VOLTAGE */
1550 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1551 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1552
1553 /* Bit definitions for LDO8_CTRL */
1554 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1555 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1556 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1557 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1558 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1559 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1560 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1561 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1562 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1563 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1564
1565 /* Bit definitions for LDO8_VOLTAGE */
1566 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1567 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1568
1569 /* Bit definitions for LDO9_CTRL */
1570 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1571 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1572 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1573 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1574 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1575 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1576 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1577 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1578 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1579 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1580
1581 /* Bit definitions for LDO9_VOLTAGE */
1582 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1583 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1584
1585 /* Bit definitions for LDO10_CTRL */
1586 #define PALMAS_LDO10_CTRL_WR_S                                  0x80
1587 #define PALMAS_LDO10_CTRL_WR_S_SHIFT                            7
1588 #define PALMAS_LDO10_CTRL_LDO_BYPASS_EN                         0x40
1589 #define PALMAS_LDO10_CTRL_LDO_BYPASS_EN_SHIFT                   6
1590 #define PALMAS_LDO10_CTRL_STATUS                                0x10
1591 #define PALMAS_LDO10_CTRL_STATUS_SHIFT                          4
1592 #define PALMAS_LDO10_CTRL_MODE_SLEEP                            0x04
1593 #define PALMAS_LDO10_CTRL_MODE_SLEEP_SHIFT                      2
1594 #define PALMAS_LDO10_CTRL_MODE_ACTIVE                           0x01
1595 #define PALMAS_LDO10_CTRL_MODE_ACTIVE_SHIFT                     0
1596
1597 /* Bit definitions for LDO10_VOLTAGE */
1598 #define PALMAS_LDO10_VOLTAGE_VSEL_MASK                          0x3f
1599 #define PALMAS_LDO10_VOLTAGE_VSEL_SHIFT                         0
1600
1601 /* Bit definitions for LDO11_CTRL */
1602 #define PALMAS_LDO11_CTRL_WR_S                                  0x80
1603 #define PALMAS_LDO11_CTRL_WR_S_SHIFT                            7
1604 #define PALMAS_LDO11_CTRL_LDO_BYPASS_EN                         0x40
1605 #define PALMAS_LDO11_CTRL_LDO_BYPASS_EN_SHIFT                   6
1606 #define PALMAS_LDO11_CTRL_STATUS                                0x10
1607 #define PALMAS_LDO11_CTRL_STATUS_SHIFT                          4
1608 #define PALMAS_LDO11_CTRL_MODE_SLEEP                            0x04
1609 #define PALMAS_LDO11_CTRL_MODE_SLEEP_SHIFT                      2
1610 #define PALMAS_LDO11_CTRL_MODE_ACTIVE                           0x01
1611 #define PALMAS_LDO11_CTRL_MODE_ACTIVE_SHIFT                     0
1612
1613 /* Bit definitions for LDO11_VOLTAGE */
1614 #define PALMAS_LDO11_VOLTAGE_VSEL_MASK                          0x3f
1615 #define PALMAS_LDO11_VOLTAGE_VSEL_SHIFT                         0
1616
1617 /* Bit definitions for LDO12_CTRL */
1618 #define PALMAS_LDO12_CTRL_WR_S                                  0x80
1619 #define PALMAS_LDO12_CTRL_WR_S_SHIFT                            7
1620 #define PALMAS_LDO12_CTRL_LDO_BYPASS_EN                         0x40
1621 #define PALMAS_LDO12_CTRL_LDO_BYPASS_EN_SHIFT                   6
1622 #define PALMAS_LDO12_CTRL_STATUS                                0x10
1623 #define PALMAS_LDO12_CTRL_STATUS_SHIFT                          4
1624 #define PALMAS_LDO12_CTRL_MODE_SLEEP                            0x04
1625 #define PALMAS_LDO12_CTRL_MODE_SLEEP_SHIFT                      2
1626 #define PALMAS_LDO12_CTRL_MODE_ACTIVE                           0x01
1627 #define PALMAS_LDO12_CTRL_MODE_ACTIVE_SHIFT                     0
1628
1629 /* Bit definitions for LDO12_VOLTAGE */
1630 #define PALMAS_LDO12_VOLTAGE_VSEL_MASK                          0x3f
1631 #define PALMAS_LDO12_VOLTAGE_VSEL_SHIFT                         0
1632
1633 /* Bit definitions for LDO13_CTRL */
1634 #define PALMAS_LDO13_CTRL_WR_S                                  0x80
1635 #define PALMAS_LDO13_CTRL_WR_S_SHIFT                            7
1636 #define PALMAS_LDO13_CTRL_LDO_BYPASS_EN                         0x40
1637 #define PALMAS_LDO13_CTRL_LDO_BYPASS_EN_SHIFT                   6
1638 #define PALMAS_LDO13_CTRL_STATUS                                0x10
1639 #define PALMAS_LDO13_CTRL_STATUS_SHIFT                          4
1640 #define PALMAS_LDO13_CTRL_MODE_SLEEP                            0x04
1641 #define PALMAS_LDO13_CTRL_MODE_SLEEP_SHIFT                      2
1642 #define PALMAS_LDO13_CTRL_MODE_ACTIVE                           0x01
1643 #define PALMAS_LDO13_CTRL_MODE_ACTIVE_SHIFT                     0
1644
1645 /* Bit definitions for LDO13_VOLTAGE */
1646 #define PALMAS_LDO13_VOLTAGE_VSEL_MASK                          0x3f
1647 #define PALMAS_LDO13_VOLTAGE_VSEL_SHIFT                         0
1648
1649 /* Bit definitions for LDO14_CTRL */
1650 #define PALMAS_LDO14_CTRL_WR_S                                  0x80
1651 #define PALMAS_LDO14_CTRL_WR_S_SHIFT                            7
1652 #define PALMAS_LDO14_CTRL_LDO_BYPASS_EN                         0x40
1653 #define PALMAS_LDO14_CTRL_LDO_BYPASS_EN_SHIFT                   6
1654 #define PALMAS_LDO14_CTRL_STATUS                                0x10
1655 #define PALMAS_LDO14_CTRL_STATUS_SHIFT                          4
1656 #define PALMAS_LDO14_CTRL_MODE_SLEEP                            0x04
1657 #define PALMAS_LDO14_CTRL_MODE_SLEEP_SHIFT                      2
1658 #define PALMAS_LDO14_CTRL_MODE_ACTIVE                           0x01
1659 #define PALMAS_LDO14_CTRL_MODE_ACTIVE_SHIFT                     0
1660
1661 /* Bit definitions for LDO14_VOLTAGE */
1662 #define PALMAS_LDO14_VOLTAGE_VSEL_MASK                          0x3f
1663 #define PALMAS_LDO14_VOLTAGE_VSEL_SHIFT                         0
1664
1665 /* Bit definitions for LDOLN_CTRL */
1666 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1667 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1668 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1669 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1670 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1671 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1672 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1673 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1674
1675 /* Bit definitions for LDOLN_VOLTAGE */
1676 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1677 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1678
1679 /* Bit definitions for LDOUSB_CTRL */
1680 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1681 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1682 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1683 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1684 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1685 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1686 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1687 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1688
1689 /* Bit definitions for LDOUSB_VOLTAGE */
1690 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1691 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1692
1693 /* Bit definitions for LDO_CTRL */
1694 #define PALMAS_LDO_CTRL_VREF_425                                0x08
1695 #define PALMAS_LDO_CTRL_VREF_425_SHIFT                          3
1696 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_MASK                0x6
1697 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_DISABLE             0x0
1698 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS12              0x2
1699 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS3               0x4
1700 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS6               0x6
1701 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1702 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1703 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_MASK                0x1
1704 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_IN1                 0x1
1705 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_IN2                 0x0
1706
1707 /* Bit definitions for LDO_PD_CTRL1 */
1708 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1709 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1710 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1711 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1712 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1713 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1714 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1715 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1716 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1717 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1718 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1719 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1720 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1721 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1722 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1723 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1724
1725 /* Bit definitions for LDO_PD_CTRL2 */
1726 #define PALMAS_LDO_PD_CTRL2_LDO14                               0x80
1727 #define PALMAS_LDO_PD_CTRL2_LDO14_SHIFT                         7
1728 #define PALMAS_LDO_PD_CTRL2_LDO13                               0x40
1729 #define PALMAS_LDO_PD_CTRL2_LDO13_SHIFT                         6
1730 #define PALMAS_LDO_PD_CTRL2_LDO12                               0x20
1731 #define PALMAS_LDO_PD_CTRL2_LDO12_SHIFT                         5
1732 #define PALMAS_LDO_PD_CTRL2_LDO11                               0x10
1733 #define PALMAS_LDO_PD_CTRL2_LDO11_SHIFT                         4
1734 #define PALMAS_LDO_PD_CTRL2_LDO10                               0x08
1735 #define PALMAS_LDO_PD_CTRL2_LDO10_SHIFT                         3
1736 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1737 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1738 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1739 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1740 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1741 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1742
1743 /* Bit definitions for LDO_SHORT_STATUS1 */
1744 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1745 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1746 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1747 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1748 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1749 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1750 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1751 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1752 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1753 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1754 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1755 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1756 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1757 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1758 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1759 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1760
1761 /* Bit definitions for LDO_SHORT_STATUS2 */
1762 #define PALMAS_LDO_SHORT_STATUS2_LDO14                          0x80
1763 #define PALMAS_LDO_SHORT_STATUS2_LDO14_SHIFT                    7
1764 #define PALMAS_LDO_SHORT_STATUS2_LDO13                          0x40
1765 #define PALMAS_LDO_SHORT_STATUS2_LDO13_SHIFT                    6
1766 #define PALMAS_LDO_SHORT_STATUS2_LDO12                          0x20
1767 #define PALMAS_LDO_SHORT_STATUS2_LDO12_SHIFT                    5
1768 #define PALMAS_LDO_SHORT_STATUS2_LDO11                          0x10
1769 #define PALMAS_LDO_SHORT_STATUS2_LDO11_SHIFT                    4
1770 #define PALMAS_LDO_SHORT_STATUS2_LDO10                          0x08
1771 #define PALMAS_LDO_SHORT_STATUS2_LDO10_SHIFT                    3
1772 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1773 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1774 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1775 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1776 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1777 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1778 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1779 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1780
1781 /* Registers for function DVFS Func */
1782 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1783 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1784 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1785 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1786 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1787 #define PALMAS_SMPS_DVFS1_SMPS_SELECT_SHIFT                     4
1788 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1789 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1790
1791 #define DVFS_BASE_VOLTAGE_UV                                    500000
1792 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1793 #define DVFS_VOLTAGE_STEP_UV                                    10000
1794
1795 /* Registers for function SIMCARD Func */
1796 #define PALMAS_SIM_DEBOUNCE                                     0x0
1797 #define PALMAS_SIM_PWR_DOWN                                     0x1
1798
1799 /* Bit definitions for SIM_DEBOUNCE */
1800 #define PALMAS_SIM_DEBOUNCE_SIM2_IR                             0x80
1801 #define PALMAS_SIM_DEBOUNCE_SIM2_IR_SHIFT                       7
1802 #define PALMAS_SIM_DEBOUNCE_SIM1_IR                             0x40
1803 #define PALMAS_SIM_DEBOUNCE_SIM1_IR_SHIFT                       6
1804 #define PALMAS_SIM_DEBOUNCE_SIM_DET1_PIN_STATE                  0x20
1805 #define PALMAS_SIM_DEBOUNCE_SIM_DET1_PIN_STATE_SHIFT            5
1806 #define PALMAS_SIM_DEBOUNCE_DBCNT_MASK                          0x1F
1807 #define PALMAS_SIM_DEBOUNCE_DBCNT_SHIFT                         0
1808
1809 /* Bit definitions for SIM_PWR_DOWN */
1810 #define PALMAS_SIM_PWR_DOWN_PWRDNEN2                            0x80
1811 #define PALMAS_SIM_PWR_DOWN_PWRDNEN2_SHIFT                      7
1812 #define PALMAS_SIM_PWR_DOWN_PWRDNEN1                            0x40
1813 #define PALMAS_SIM_PWR_DOWN_PWRDNEN1_SHIFT                      6
1814 #define PALMAS_SIM_PWR_DOWN_SIM_DET2_PIN_STATE                  0x20
1815 #define PALMAS_SIM_PWR_DOWN_SIM_DET2_PIN_STATE_SHIFT            5
1816 #define PALMAS_SIM_PWR_DOWN_PWRDNCNT_MASK                       0x1F
1817 #define PALMAS_SIM_PWR_DOWN_PWRDNCNT_SHIFT                      0
1818
1819 /* Registers for function PMU_CONTROL */
1820 #define PALMAS_DEV_CTRL                                         0x0
1821 #define PALMAS_POWER_CTRL                                       0x1
1822 #define PALMAS_VSYS_LO                                          0x2
1823 #define PALMAS_VSYS_MON                                         0x3
1824 #define PALMAS_VBAT_MON                                         0x4
1825 #define PALMAS_WATCHDOG                                         0x5
1826 #define PALMAS_BOOT_STATUS                                      0x6
1827 #define PALMAS_BATTERY_BOUNCE                                   0x7
1828 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1829 #define PALMAS_LONG_PRESS_KEY                                   0x9
1830 #define PALMAS_OSC_THERM_CTRL                                   0xA
1831 #define PALMAS_BATDEBOUNCING                                    0xB
1832 #define PALMAS_SWOFF_HWRST                                      0xF
1833 #define PALMAS_SWOFF_COLDRST                                    0x10
1834 #define PALMAS_SWOFF_STATUS                                     0x11
1835 #define PALMAS_PMU_CONFIG                                       0x12
1836 #define PALMAS_SPARE                                            0x14
1837 #define PALMAS_PMU_SECONDARY_INT                                0x15
1838 #define PALMAS_SW_REVISION                                      0x17
1839 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1840 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1841 #define PALMAS_USB_CHGCTL1                                      0x1A
1842 #define PALMAS_USB_CHGCTL2                                      0x1B
1843
1844 /* Bit definitions for DEV_CTRL */
1845 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1846 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1847 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1848 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1849 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1850 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1851
1852 /* Bit definitions for POWER_CTRL */
1853 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1854 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1855 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1856 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1857 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1858 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1859
1860 /* Bit definitions for VSYS_LO */
1861 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1862 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1863
1864 /* Bit definitions for VSYS_MON */
1865 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1866 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1867 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1868 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1869
1870 /* Bit definitions for VBAT_MON */
1871 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1872 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1873 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1874 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1875
1876 /* Bit definitions for WATCHDOG */
1877 #define PALMAS_WATCHDOG_LOCK                                    0x20
1878 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1879 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1880 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1881 #define PALMAS_WATCHDOG_MODE                                    0x08
1882 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1883 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1884 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1885
1886 /* Bit definitions for BOOT_STATUS */
1887 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1888 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1889 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1890 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1891
1892 /* Bit definitions for BATTERY_BOUNCE */
1893 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1894 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1895
1896 /* Bit definitions for BACKUP_BATTERY_CTRL */
1897 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1898 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1899 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1900 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1901 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1902 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1903 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1904 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1905 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1906 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1907 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1908 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1909 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1910 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1911
1912 /* Bit definitions for LONG_PRESS_KEY */
1913 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1914 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1915 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1916 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1917 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1918 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1919 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1920 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1921
1922 /* Register bit values for various Long_Press_key durations */
1923 #define PALMAS_LONG_PRESS_KEY_TIME_DEFAULT      -1
1924 #define PALMAS_LONG_PRESS_KEY_TIME_6SECONDS     0
1925 #define PALMAS_LONG_PRESS_KEY_TIME_8SECONDS     1
1926 #define PALMAS_LONG_PRESS_KEY_TIME_10SECONDS    2
1927 #define PALMAS_LONG_PRESS_KEY_TIME_12SECONDS    3
1928
1929 /* Bit definitions for OSC_THERM_CTRL */
1930 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1931 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1932 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1933 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1934 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1935 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1936 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1937 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1938 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1939 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1940 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1941 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1942 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1943 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1944
1945 /* Bit definitions for BATDEBOUNCING */
1946 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1947 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1948 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1949 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1950 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1951 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1952
1953 /* Bit definitions for SWOFF_HWRST */
1954 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1955 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1956 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1957 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1958 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1959 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1960 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1961 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1962 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1963 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1964 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1965 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1966 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1967 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1968 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1969 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1970
1971 /* Bit definitions for SWOFF_COLDRST */
1972 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1973 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1974 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1975 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1976 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1977 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1978 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1979 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1980 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1981 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1982 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1983 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1984 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1985 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1986 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1987 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1988
1989 /* Bit definitions for SWOFF_STATUS */
1990 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1991 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1992 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1993 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1994 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1995 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1996 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1997 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1998 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1999 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
2000 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
2001 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
2002 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
2003 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
2004 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
2005 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
2006
2007 /* Bit definitions for PMU_CONFIG */
2008 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
2009 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
2010 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
2011 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
2012 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
2013 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
2014 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
2015 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
2016 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
2017 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
2018
2019 /* Bit definitions for SPARE */
2020 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
2021 #define PALMAS_SPARE_SPARE_SHIFT                                3
2022 #define PALMAS_SPARE_REGEN3_OD                                  0x04
2023 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
2024 #define PALMAS_SPARE_REGEN2_OD                                  0x02
2025 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
2026 #define PALMAS_SPARE_REGEN1_OD                                  0x01
2027 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
2028
2029 /* Bit definitions for PMU_SECONDARY_INT */
2030 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
2031 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
2032 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
2033 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
2034 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
2035 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
2036 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
2037 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
2038 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
2039 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
2040 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
2041 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
2042 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
2043 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
2044 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
2045 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
2046
2047 /* Bit definitions for SW_REVISION */
2048 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
2049 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
2050
2051 /* Bit definitions for EXT_CHRG_CTRL */
2052 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
2053 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
2054 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
2055 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
2056 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
2057 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
2058 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
2059 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
2060 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
2061 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
2062 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
2063 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
2064
2065 /* Bit definitions for PMU_SECONDARY_INT2 */
2066 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
2067 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
2068 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
2069 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
2070 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
2071 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
2072 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
2073 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
2074
2075 /* Bit definitions for USB_CHGCTL1 */
2076 #define PALMAS_USB_CHGCTL1_USB_SUSPEND                          0x04
2077
2078 /* Bit definitions for USB_CHGCTL2 */
2079 #define PALMAS_USB_CHGCTL2_BOOST_EN                             0x08
2080
2081 /* Registers for function RESOURCE */
2082 #define PALMAS_CLK32KG_CTRL                                     0x0
2083 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
2084 #define PALMAS_REGEN1_CTRL                                      0x2
2085 #define PALMAS_REGEN2_CTRL                                      0x3
2086 #define PALMAS_SYSEN1_CTRL                                      0x4
2087 #define PALMAS_SYSEN2_CTRL                                      0x5
2088 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
2089 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
2090 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
2091 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
2092 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
2093 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
2094 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
2095 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
2096 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
2097 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
2098 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
2099 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
2100 #define PALMAS_REGEN3_CTRL                                      0x12
2101 #define PALMAS_REGEN4_CTRL                                      0x13
2102 #define PALMAS_REGEN5_CTRL                                      0x14
2103 #define PALMAS_REGEN7_CTRL                                      0x16
2104 #define PALMAS_NSLEEP_RES_ASSIGN2                               0x18
2105 #define PALMAS_ENABLE1_RES_ASSIGN2                              0x19
2106 #define PALMAS_ENABLE2_RES_ASSIGN2                              0x1A
2107
2108 /* Bit definitions for CLK32KG_CTRL */
2109 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
2110 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
2111 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
2112 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
2113 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
2114 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
2115
2116 /* Bit definitions for CLK32KGAUDIO_CTRL */
2117 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
2118 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
2119 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
2120 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
2121 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
2122 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
2123 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
2124 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
2125
2126 /* Bit definitions for REGEN1_CTRL */
2127 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
2128 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
2129 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
2130 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
2131 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
2132 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
2133
2134 /* Bit definitions for REGEN2_CTRL */
2135 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
2136 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
2137 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
2138 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
2139 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
2140 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
2141
2142 /* Bit definitions for SYSEN1_CTRL */
2143 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
2144 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
2145 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
2146 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
2147 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
2148 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
2149
2150 /* Bit definitions for SYSEN2_CTRL */
2151 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
2152 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
2153 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
2154 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
2155 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
2156 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
2157
2158 /* Bit definitions for NSLEEP_RES_ASSIGN */
2159 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN4                         0x80
2160 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN4_SHIFT                   7
2161 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
2162 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
2163 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
2164 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
2165 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
2166 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
2167 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
2168 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
2169 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
2170 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
2171 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
2172 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
2173 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
2174 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
2175
2176 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
2177 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
2178 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
2179 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
2180 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
2181 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
2182 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
2183 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
2184 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
2185 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
2186 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
2187 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
2188 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
2189 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
2190 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
2191 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
2192 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
2193
2194 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
2195 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
2196 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
2197 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
2198 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
2199 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
2200 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
2201 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
2202 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
2203 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
2204 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
2205 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
2206 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
2207 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
2208 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
2209 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
2210 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
2211
2212 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
2213 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO14                         0x80
2214 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO14_SHIFT                   7
2215 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO13                         0x40
2216 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO13_SHIFT                   6
2217 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO12                         0x20
2218 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO12_SHIFT                   5
2219 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO11                         0x10
2220 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO11_SHIFT                   4
2221 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO10                         0x08
2222 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO10_SHIFT                   3
2223 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
2224 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
2225 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
2226 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
2227 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
2228 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
2229
2230 /* Bit definitions for ENABLE1_RES_ASSIGN */
2231 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN4                        0x80
2232 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN4_SHIFT                  7
2233 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
2234 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
2235 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
2236 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
2237 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
2238 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
2239 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
2240 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
2241 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
2242 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
2243 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
2244 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
2245 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
2246 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
2247
2248 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
2249 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
2250 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
2251 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
2252 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
2253 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
2254 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
2255 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
2256 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
2257 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
2258 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
2259 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
2260 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
2261 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
2262 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
2263 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
2264 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
2265
2266 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
2267 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
2268 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
2269 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
2270 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
2271 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
2272 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
2273 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
2274 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
2275 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
2276 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
2277 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
2278 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
2279 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
2280 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
2281 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
2282 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
2283
2284 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
2285 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO14                        0x80
2286 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO14_SHIFT                  7
2287 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO13                        0x40
2288 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO13_SHIFT                  6
2289 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO12                        0x20
2290 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO12_SHIFT                  5
2291 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO11                        0x10
2292 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO11_SHIFT                  4
2293 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO10                        0x08
2294 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO10_SHIFT                  3
2295 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
2296 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
2297 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
2298 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
2299 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
2300 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
2301
2302 /* Bit definitions for ENABLE2_RES_ASSIGN */
2303 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN4                        0x80
2304 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN4_SHIFT                  7
2305 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
2306 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
2307 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
2308 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
2309 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
2310 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
2311 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
2312 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
2313 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
2314 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
2315 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
2316 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
2317 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
2318 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
2319
2320 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
2321 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
2322 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
2323 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
2324 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
2325 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
2326 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
2327 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
2328 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
2329 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
2330 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
2331 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
2332 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
2333 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
2334 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
2335 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
2336 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
2337
2338 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
2339 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
2340 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
2341 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
2342 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
2343 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
2344 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
2345 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
2346 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
2347 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
2348 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
2349 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
2350 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
2351 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
2352 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
2353 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
2354 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
2355
2356 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
2357 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO14                        0x80
2358 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO14_SHIFT                  7
2359 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO13                        0x40
2360 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO13_SHIFT                  6
2361 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO12                        0x20
2362 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO12_SHIFT                  5
2363 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO11                        0x10
2364 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO11_SHIFT                  4
2365 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO10                        0x08
2366 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO10_SHIFT                  3
2367 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
2368 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
2369 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
2370 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
2371 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
2372 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
2373
2374 /* Bit definitions for REGEN3_CTRL */
2375 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
2376 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
2377 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
2378 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
2379 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
2380 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
2381
2382 /* Bit definitions for REGEN4_CTRL */
2383 #define PALMAS_REGEN4_CTRL_STATUS                               0x10
2384 #define PALMAS_REGEN4_CTRL_STATUS_SHIFT                         4
2385 #define PALMAS_REGEN4_CTRL_MODE_SLEEP                           0x04
2386 #define PALMAS_REGEN4_CTRL_MODE_SLEEP_SHIFT                     2
2387 #define PALMAS_REGEN4_CTRL_MODE_ACTIVE                          0x01
2388 #define PALMAS_REGEN4_CTRL_MODE_ACTIVE_SHIFT                    0
2389
2390 /* Bit definitions for REGEN5_CTRL */
2391 #define PALMAS_REGEN5_CTRL_STATUS                               0x10
2392 #define PALMAS_REGEN5_CTRL_STATUS_SHIFT                         4
2393 #define PALMAS_REGEN5_CTRL_MODE_SLEEP                           0x04
2394 #define PALMAS_REGEN5_CTRL_MODE_SLEEP_SHIFT                     2
2395 #define PALMAS_REGEN5_CTRL_MODE_ACTIVE                          0x01
2396 #define PALMAS_REGEN5_CTRL_MODE_ACTIVE_SHIFT                    0
2397
2398 /* Bit definitions for REGEN7_CTRL */
2399 #define PALMAS_REGEN7_CTRL_STATUS                               0x10
2400 #define PALMAS_REGEN7_CTRL_STATUS_SHIFT                         4
2401 #define PALMAS_REGEN7_CTRL_MODE_SLEEP                           0x04
2402 #define PALMAS_REGEN7_CTRL_MODE_SLEEP_SHIFT                     2
2403 #define PALMAS_REGEN7_CTRL_MODE_ACTIVE                          0x01
2404 #define PALMAS_REGEN7_CTRL_MODE_ACTIVE_SHIFT                    0
2405
2406 /* Bit definitions for NSLEEP_RES_ASSIGN2 */
2407 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN7                         0x04
2408 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN7_SHIFT                   2
2409 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN5                         0x01
2410 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN5_SHIFT                   0
2411
2412 /* Bit definitions for ENABLE1_RES_ASSIGN2 */
2413 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN7                        0x04
2414 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN7_SHIFT                  2
2415 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN5                        0x01
2416 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN5_SHIFT                  0
2417
2418 /* Bit definitions for ENABLE2_RES_ASSIGN2 */
2419 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN7                        0x04
2420 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN7_SHIFT                  2
2421 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN5                        0x01
2422 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN5_SHIFT                  0
2423
2424 /* Registers for function PAD_CONTROL */
2425 #define PALMAS_OD_OUTPUT_CTRL2                                  0x2
2426 #define PALMAS_POLARITY_CTRL2                                   0x3
2427 #define PALMAS_PU_PD_INPUT_CTRL1                                0x4
2428 #define PALMAS_PU_PD_INPUT_CTRL2                                0x5
2429 #define PALMAS_PU_PD_INPUT_CTRL3                                0x6
2430 #define PALMAS_PU_PD_INPUT_CTRL5                                0x7
2431 #define PALMAS_OD_OUTPUT_CTRL                                   0x8
2432 #define PALMAS_POLARITY_CTRL                                    0x9
2433 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0xA
2434 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0xB
2435 #define PALMAS_I2C_SPI                                          0xC
2436 #define PALMAS_PU_PD_INPUT_CTRL4                                0xD
2437 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xE
2438 #define PALMAS_PRIMARY_SECONDARY_PAD4                           0xF
2439
2440 /* Bit definitions for OD_OUTPUT_CTRL2 */
2441 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN7                        0x40
2442 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN7_SHIFT                  6
2443 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN5                        0x10
2444 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN5_SHIFT                  4
2445 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN4                        0x08
2446 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN4_SHIFT                  3
2447 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN2                        0x02
2448 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN2_SHIFT                  1
2449 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN1                        0x01
2450 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN1_SHIFT                  0
2451
2452 /* Bit definitions for POLARITY_CTRL2 */
2453 #define PALMAS_POLARITY_CTRL2_DET_POLARITY                      0x01
2454 #define PALMAS_POLARITY_CTRL2_DET_POLARITY_SHIFT                0
2455
2456 /* Bit definitions for PU_PD_INPUT_CTRL1 */
2457 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
2458 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
2459 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
2460 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
2461 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
2462 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
2463 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
2464 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
2465 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
2466 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
2467
2468 /* Bit definitions for PU_PD_INPUT_CTRL2 */
2469 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
2470 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
2471 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
2472 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
2473 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
2474 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
2475 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
2476 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
2477 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
2478 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
2479 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
2480 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
2481
2482 /* Bit definitions for PU_PD_INPUT_CTRL3 */
2483 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
2484 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
2485 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
2486 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
2487 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
2488 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
2489 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
2490 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
2491
2492 /* Bit definitions for PU_PD_INPUT_CTRL5 */
2493 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PU                        0x80
2494 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PU_SHIFT                  7
2495 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PD                        0x40
2496 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PD_SHIFT                  6
2497 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PU                        0x20
2498 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PU_SHIFT                  5
2499 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PD                        0x10
2500 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PD_SHIFT                  4
2501
2502 /* Bit definitions for OD_OUTPUT_CTRL */
2503 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
2504 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
2505 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
2506 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
2507 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
2508 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
2509 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
2510 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
2511
2512 /* Bit definitions for POLARITY_CTRL */
2513 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
2514 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
2515 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
2516 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
2517 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
2518 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
2519 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
2520 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
2521 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
2522 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
2523 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
2524 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
2525 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
2526 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
2527 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
2528 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
2529
2530 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2531 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
2532 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
2533 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
2534 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
2535 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
2536 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
2537 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
2538 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
2539 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
2540 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
2541 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
2542 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
2543
2544 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2545 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_MSB                0x04
2546 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_MSB_SHIFT          6
2547 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
2548 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
2549 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
2550 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
2551 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
2552 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
2553 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
2554 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
2555
2556 /* Bit definitions for I2C_SPI */
2557 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
2558 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
2559 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
2560 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
2561 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
2562 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
2563 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
2564 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
2565 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
2566 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
2567
2568 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2569 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
2570 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
2571 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
2572 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
2573 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
2574 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
2575 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
2576 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
2577
2578 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2579 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
2580 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
2581 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
2582 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
2583
2584 /* Bit definitions for PRIMARY_SECONDARY_PAD4 */
2585 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_15_MASK              0x80
2586 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_15_SHIFT             7
2587 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_14_MASK              0x40
2588 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_14_SHIFT             6
2589 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_13_MASK              0x20
2590 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_13_SHIFT             5
2591 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_12_MASK              0x10
2592 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_12_SHIFT             4
2593 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_11_MASK              0x08
2594 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_11_SHIFT             3
2595 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_10_MASK              0x04
2596 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_10_SHIFT             2
2597 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_9_MASK               0x02
2598 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_9_SHIFT              1
2599 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_8_MASK               0x01
2600 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_8_SHIFT              0
2601
2602 /* Registers for function LED_PWM */
2603 #define PALMAS_LED_PERIOD_CTRL                                  0x0
2604 #define PALMAS_LED_CTRL                                         0x1
2605 #define PALMAS_PWM_CTRL1                                        0x2
2606 #define PALMAS_PWM_CTRL2                                        0x3
2607
2608 /* Bit definitions for LED_PERIOD_CTRL */
2609 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
2610 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
2611 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
2612 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
2613
2614 /* Bit definitions for LED_CTRL */
2615 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
2616 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
2617 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
2618 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
2619 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
2620 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
2621 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
2622 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
2623
2624 /* Bit definitions for PWM_CTRL1 */
2625 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
2626 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
2627 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
2628 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
2629
2630 /* Bit definitions for PWM_CTRL2 */
2631 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
2632 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
2633
2634 /* Maximum INT mask/edge regsiter */
2635 #define PALMAS_MAX_INTERRUPT_MASK_REG                           6
2636 #define PALMAS_MAX_INTERRUPT_EDGE_REG                           12
2637
2638 /* Registers for function INTERRUPT */
2639 #define PALMAS_INT1_STATUS                                      0x0
2640 #define PALMAS_INT1_MASK                                        0x1
2641 #define PALMAS_INT1_LINE_STATE                                  0x2
2642 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
2643 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
2644 #define PALMAS_INT2_STATUS                                      0x5
2645 #define PALMAS_INT2_MASK                                        0x6
2646 #define PALMAS_INT2_LINE_STATE                                  0x7
2647 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
2648 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
2649 #define PALMAS_INT3_STATUS                                      0xA
2650 #define PALMAS_INT3_MASK                                        0xB
2651 #define PALMAS_INT3_LINE_STATE                                  0xC
2652 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
2653 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
2654 #define PALMAS_INT4_STATUS                                      0xF
2655 #define PALMAS_INT4_MASK                                        0x10
2656 #define PALMAS_INT4_LINE_STATE                                  0x11
2657 #define PALMAS_INT4_EDGE_DETECT1                                0x12
2658 #define PALMAS_INT4_EDGE_DETECT2                                0x13
2659 #define PALMAS_INT5_STATUS                                      0x15
2660 #define PALMAS_INT5_MASK                                        0x16
2661 #define PALMAS_INT5_LINE_STATE                                  0x17
2662 #define PALMAS_INT5_EDGE_DETECT1                                0x18
2663 #define PALMAS_INT5_EDGE_DETECT2                                0x19
2664 #define PALMAS_INT_CTRL                                         0x14
2665 #define PALMAS_INT5_STATUS                                      0x15
2666 #define PALMAS_INT5_MASK                                        0x16
2667 #define PALMAS_INT5_LINE_STATE                                  0x17
2668 #define PALMAS_INT5_EDGE_DETECT1                                0x18
2669 #define PALMAS_INT5_EDGE_DETECT2                                0x19
2670 #define PALMAS_INT6_STATUS                                      0x1A
2671 #define PALMAS_INT6_MASK                                        0x1B
2672 #define PALMAS_INT6_LINE_STATE                                  0x1C
2673 #define PALMAS_INT6_EDGE_DETECT1_RESERVED                       0x1D
2674 #define PALMAS_INT6_EDGE_DETECT2_RESERVED                       0x1E
2675
2676 /* Bit definitions for INT1_STATUS */
2677 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
2678 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
2679 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
2680 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
2681 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
2682 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
2683 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
2684 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
2685 #define PALMAS_INT1_STATUS_RPWRON                               0x08
2686 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
2687 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
2688 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
2689 #define PALMAS_INT1_STATUS_PWRON                                0x02
2690 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
2691 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
2692 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
2693
2694 /* Bit definitions for INT1_MASK */
2695 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
2696 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
2697 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
2698 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
2699 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
2700 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
2701 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
2702 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
2703 #define PALMAS_INT1_MASK_RPWRON                                 0x08
2704 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
2705 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
2706 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
2707 #define PALMAS_INT1_MASK_PWRON                                  0x02
2708 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
2709 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
2710 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
2711
2712 /* Bit definitions for INT1_LINE_STATE */
2713 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
2714 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
2715 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
2716 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
2717 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
2718 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
2719 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
2720 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
2721 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
2722 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
2723 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
2724 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
2725 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
2726 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
2727 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
2728 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
2729
2730 /* Bit definitions for INT2_STATUS */
2731 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
2732 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
2733 #define PALMAS_INT2_STATUS_SHORT                                0x40
2734 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
2735 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
2736 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
2737 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
2738 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
2739 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
2740 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
2741 #define PALMAS_INT2_STATUS_WDT                                  0x04
2742 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
2743 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
2744 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
2745 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
2746 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
2747
2748 /* Bit definitions for INT2_MASK */
2749 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
2750 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
2751 #define PALMAS_INT2_MASK_SHORT                                  0x40
2752 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
2753 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
2754 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
2755 #define PALMAS_INT2_MASK_RESET_IN                               0x10
2756 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
2757 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
2758 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
2759 #define PALMAS_INT2_MASK_WDT                                    0x04
2760 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
2761 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
2762 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
2763 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
2764 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
2765
2766 /* Bit definitions for INT2_LINE_STATE */
2767 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
2768 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
2769 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
2770 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
2771 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
2772 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
2773 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
2774 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
2775 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
2776 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
2777 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
2778 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
2779 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
2780 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
2781 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
2782 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
2783
2784 /* Bit definitions for INT3_STATUS */
2785 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2786 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
2787 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2788 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
2789 #define PALMAS_INT3_STATUS_ID                                   0x20
2790 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
2791 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2792 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
2793 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2794 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
2795 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2796 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2797 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2798 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2799 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2800 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2801
2802 /* Bit definitions for INT3_MASK */
2803 #define PALMAS_INT3_MASK_VBUS                                   0x80
2804 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2805 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2806 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2807 #define PALMAS_INT3_MASK_ID                                     0x20
2808 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2809 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2810 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2811 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2812 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2813 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2814 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2815 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2816 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2817 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2818 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2819
2820 /* Bit definitions for INT3_LINE_STATE */
2821 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2822 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2823 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2824 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2825 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2826 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2827 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2828 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2829 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2830 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2831 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2832 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2833 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2834 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2835 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2836 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2837
2838 /* Bit definitions for INT4_STATUS */
2839 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2840 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2841 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2842 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2843 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2844 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2845 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2846 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2847 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2848 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2849 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2850 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2851 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2852 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2853 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2854 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2855
2856 /* Bit definitions for INT4_MASK */
2857 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2858 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2859 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2860 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2861 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2862 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2863 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2864 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2865 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2866 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2867 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2868 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2869 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2870 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2871 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2872 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2873
2874 /* Bit definitions for INT4_LINE_STATE */
2875 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2876 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2877 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2878 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2879 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2880 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2881 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2882 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2883 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2884 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2885 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2886 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2887 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2888 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2889 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2890 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2891
2892 /* Bit definitions for INT4_EDGE_DETECT1 */
2893 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2894 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2895 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2896 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2897 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2898 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2899 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2900 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2901 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2902 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2903 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2904 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2905 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2906 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2907 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2908 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2909
2910 /* Bit definitions for INT4_EDGE_DETECT2 */
2911 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2912 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2913 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2914 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2915 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2916 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2917 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2918 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2919 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2920 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2921 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2922 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2923 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2924 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2925 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2926 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2927
2928 /* Bit definitions for INT5_STATUS */
2929 #define PALMAS_INT5_STATUS_GPIO_15                              0x80
2930 #define PALMAS_INT5_STATUS_GPIO_15_SHIFT                        7
2931 #define PALMAS_INT5_STATUS_GPIO_14                              0x40
2932 #define PALMAS_INT5_STATUS_GPIO_14_SHIFT                        6
2933 #define PALMAS_INT5_STATUS_GPIO_13                              0x20
2934 #define PALMAS_INT5_STATUS_GPIO_13_SHIFT                        5
2935 #define PALMAS_INT5_STATUS_GPIO_12                              0x10
2936 #define PALMAS_INT5_STATUS_GPIO_12_SHIFT                        4
2937 #define PALMAS_INT5_STATUS_GPIO_11                              0x08
2938 #define PALMAS_INT5_STATUS_GPIO_11_SHIFT                        3
2939 #define PALMAS_INT5_STATUS_GPIO_10                              0x04
2940 #define PALMAS_INT5_STATUS_GPIO_10_SHIFT                        2
2941 #define PALMAS_INT5_STATUS_GPIO_9                               0x02
2942 #define PALMAS_INT5_STATUS_GPIO_9_SHIFT                         1
2943 #define PALMAS_INT5_STATUS_GPIO_8                               0x01
2944 #define PALMAS_INT5_STATUS_GPIO_8_SHIFT                         0
2945
2946 /* Bit definitions for INT5_MASK */
2947 #define PALMAS_INT5_MASK_GPIO_15                                0x80
2948 #define PALMAS_INT5_MASK_GPIO_15_SHIFT                          7
2949 #define PALMAS_INT5_MASK_GPIO_14                                0x40
2950 #define PALMAS_INT5_MASK_GPIO_14_SHIFT                          6
2951 #define PALMAS_INT5_MASK_GPIO_13                                0x20
2952 #define PALMAS_INT5_MASK_GPIO_13_SHIFT                          5
2953 #define PALMAS_INT5_MASK_GPIO_12                                0x10
2954 #define PALMAS_INT5_MASK_GPIO_12_SHIFT                          4
2955 #define PALMAS_INT5_MASK_GPIO_11                                0x08
2956 #define PALMAS_INT5_MASK_GPIO_11_SHIFT                          3
2957 #define PALMAS_INT5_MASK_GPIO_10                                0x04
2958 #define PALMAS_INT5_MASK_GPIO_10_SHIFT                          2
2959 #define PALMAS_INT5_MASK_GPIO_9                                 0x02
2960 #define PALMAS_INT5_MASK_GPIO_9_SHIFT                           1
2961 #define PALMAS_INT5_MASK_GPIO_8                                 0x01
2962 #define PALMAS_INT5_MASK_GPIO_8_SHIFT                           0
2963
2964 /* Bit definitions for INT5_LINE_STATE */
2965 #define PALMAS_INT5_LINE_STATE_GPIO_15                          0x80
2966 #define PALMAS_INT5_LINE_STATE_GPIO_15_SHIFT                    7
2967 #define PALMAS_INT5_LINE_STATE_GPIO_14                          0x40
2968 #define PALMAS_INT5_LINE_STATE_GPIO_14_SHIFT                    6
2969 #define PALMAS_INT5_LINE_STATE_GPIO_13                          0x20
2970 #define PALMAS_INT5_LINE_STATE_GPIO_13_SHIFT                    5
2971 #define PALMAS_INT5_LINE_STATE_GPIO_12                          0x10
2972 #define PALMAS_INT5_LINE_STATE_GPIO_12_SHIFT                    4
2973 #define PALMAS_INT5_LINE_STATE_GPIO_11                          0x08
2974 #define PALMAS_INT5_LINE_STATE_GPIO_11_SHIFT                    3
2975 #define PALMAS_INT5_LINE_STATE_GPIO_10                          0x04
2976 #define PALMAS_INT5_LINE_STATE_GPIO_10_SHIFT                    2
2977 #define PALMAS_INT5_LINE_STATE_GPIO_9                           0x02
2978 #define PALMAS_INT5_LINE_STATE_GPIO_9_SHIFT                     1
2979 #define PALMAS_INT5_LINE_STATE_GPIO_8                           0x01
2980 #define PALMAS_INT5_LINE_STATE_GPIO_8_SHIFT                     0
2981
2982 /* Bit definitions for INT5_EDGE_DETECT1 */
2983 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_RISING                 0x80
2984 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_RISING_SHIFT           7
2985 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_FALLING                0x40
2986 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_FALLING_SHIFT          6
2987 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_RISING                 0x20
2988 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_RISING_SHIFT           5
2989 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_FALLING                0x10
2990 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_FALLING_SHIFT          4
2991 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_RISING                  0x08
2992 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_RISING_SHIFT            3
2993 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_FALLING                 0x04
2994 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_FALLING_SHIFT           2
2995 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_RISING                  0x02
2996 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_RISING_SHIFT            1
2997 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_FALLING                 0x01
2998 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_FALLING_SHIFT           0
2999
3000 /* Bit definitions for INT5_EDGE_DETECT2 */
3001 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_RISING                 0x80
3002 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_RISING_SHIFT           7
3003 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_FALLING                0x40
3004 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_FALLING_SHIFT          6
3005 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_RISING                 0x20
3006 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_RISING_SHIFT           5
3007 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_FALLING                0x10
3008 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_FALLING_SHIFT          4
3009 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_RISING                 0x08
3010 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_RISING_SHIFT           3
3011 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_FALLING                0x04
3012 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_FALLING_SHIFT          2
3013 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_RISING                 0x02
3014 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_RISING_SHIFT           1
3015 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_FALLING                0x01
3016 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_FALLING_SHIFT          0
3017
3018 /* Bit definitions for INT_CTRL */
3019 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
3020 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
3021 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
3022 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
3023
3024 /* Bit definitions for INT6_STATUS */
3025 #define PALMAS_INT6_STATUS_SIM2                                 0x80
3026 #define PALMAS_INT6_STATUS_SIM2_SHIFT                           7
3027 #define PALMAS_INT6_STATUS_SIM1                                 0x40
3028 #define PALMAS_INT6_STATUS_SIM1_SHIFT                           6
3029 #define PALMAS_INT6_STATUS_CHARGER                              0x20
3030 #define PALMAS_INT6_STATUS_CHARGER_SHIFT                        5
3031 #define PALMAS_INT6_STATUS_CC_AUTOCAL                           0x10
3032 #define PALMAS_INT6_STATUS_CC_AUTOCAL_SHIFT                     4
3033 #define PALMAS_INT6_STATUS_CC_BAT_STABLE                        0x08
3034 #define PALMAS_INT6_STATUS_CC_BAT_STABLE_SHIFT                  3
3035 #define PALMAS_INT6_STATUS_CC_OVC_LIMIT                         0x04
3036 #define PALMAS_INT6_STATUS_CC_OVC_LIMIT_SHIFT                   2
3037 #define PALMAS_INT6_STATUS_CC_SYNC_EOC                          0x02
3038 #define PALMAS_INT6_STATUS_CC_SYNC_EOC_SHIFT                    1
3039 #define PALMAS_INT6_STATUS_CC_EOC                               0x01
3040 #define PALMAS_INT6_STATUS_CC_EOC_SHIFT                         0
3041
3042 /* Bit definitions for INT6_MASK */
3043 #define PALMAS_INT6_MASK_SIM2                                   0x80
3044 #define PALMAS_INT6_MASK_SIM2_SHIFT                             7
3045 #define PALMAS_INT6_MASK_SIM1                                   0x40
3046 #define PALMAS_INT6_MASK_SIM1_SHIFT                             6
3047 #define PALMAS_INT6_MASK_CHARGER                                0x20
3048 #define PALMAS_INT6_MASK_CHARGER_SHIFT                          5
3049 #define PALMAS_INT6_MASK_CC_AUTOCAL                             0x10
3050 #define PALMAS_INT6_MASK_CC_AUTOCAL_SHIFT                       4
3051 #define PALMAS_INT6_MASK_CC_BAT_STABLE                          0x08
3052 #define PALMAS_INT6_MASK_CC_BAT_STABLE_SHIFT                    3
3053 #define PALMAS_INT6_MASK_CC_OVC_LIMIT                           0x04
3054 #define PALMAS_INT6_MASK_CC_OVC_LIMIT_SHIFT                     2
3055 #define PALMAS_INT6_MASK_CC_SYNC_EOC                            0x02
3056 #define PALMAS_INT6_MASK_CC_SYNC_EOC_SHIFT                      1
3057 #define PALMAS_INT6_MASK_CC_EOC                                 0x01
3058 #define PALMAS_INT6_MASK_CC_EOC_SHIFT                           0
3059
3060 /* Bit definitions for INT6_LINE_STATE */
3061 #define PALMAS_INT6_LINE_STATE_SIM2                             0x80
3062 #define PALMAS_INT6_LINE_STATE_SIM2_SHIFT                       7
3063 #define PALMAS_INT6_LINE_STATE_SIM1                             0x40
3064 #define PALMAS_INT6_LINE_STATE_SIM1_SHIFT                       6
3065 #define PALMAS_INT6_LINE_STATE_CHARGER                          0x20
3066 #define PALMAS_INT6_LINE_STATE_CHARGER_SHIFT                    5
3067 #define PALMAS_INT6_LINE_STATE_CC_AUTOCAL                       0x10
3068 #define PALMAS_INT6_LINE_STATE_CC_AUTOCAL_SHIFT                 4
3069 #define PALMAS_INT6_LINE_STATE_CC_BAT_STABLE                    0x08
3070 #define PALMAS_INT6_LINE_STATE_CC_BAT_STABLE_SHIFT              3
3071 #define PALMAS_INT6_LINE_STATE_CC_OVC_LIMIT                     0x04
3072 #define PALMAS_INT6_LINE_STATE_CC_OVC_LIMIT_SHIFT               2
3073 #define PALMAS_INT6_LINE_STATE_CC_SYNC_EOC                      0x02
3074 #define PALMAS_INT6_LINE_STATE_CC_SYNC_EOC_SHIFT                1
3075 #define PALMAS_INT6_LINE_STATE_CC_EOC                           0x01
3076 #define PALMAS_INT6_LINE_STATE_CC_EOC_SHIFT                     0
3077
3078 /* Registers for function USB_OTG */
3079 #define PALMAS_USB_WAKEUP                                       0x3
3080 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
3081 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
3082 #define PALMAS_USB_ID_CTRL_SET                                  0x6
3083 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
3084 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
3085 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
3086 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
3087 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
3088 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
3089 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
3090 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
3091 #define PALMAS_USB_ID_INT_SRC                                   0xF
3092 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
3093 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
3094 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
3095 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
3096 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
3097 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
3098 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
3099 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
3100 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
3101 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
3102 #define PALMAS_USB_OTG_REVISION                                 0x1A
3103
3104 /* Bit definitions for USB_WAKEUP */
3105 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
3106 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
3107
3108 /* Bit definitions for USB_VBUS_CTRL_SET */
3109 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
3110 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
3111 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
3112 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
3113 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
3114 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
3115 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
3116 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
3117 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
3118 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
3119
3120 /* Bit definitions for USB_VBUS_CTRL_CLR */
3121 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
3122 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
3123 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
3124 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
3125 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
3126 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
3127 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
3128 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
3129 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
3130 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
3131
3132 /* Bit definitions for USB_ID_CTRL_SET */
3133 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
3134 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
3135 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
3136 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
3137 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
3138 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
3139 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
3140 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
3141 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
3142 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
3143 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
3144 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
3145
3146 /* Bit definitions for USB_ID_CTRL_CLEAR */
3147 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
3148 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
3149 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
3150 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
3151 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
3152 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
3153 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
3154 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
3155 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
3156 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
3157 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
3158 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
3159
3160 /* Bit definitions for USB_VBUS_INT_SRC */
3161 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
3162 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
3163 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
3164 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
3165 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
3166 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
3167 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
3168 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
3169 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
3170 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
3171 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
3172 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
3173 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
3174 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
3175
3176 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
3177 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
3178 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
3179 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
3180 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
3181 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
3182 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
3183 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
3184 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
3185 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
3186 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
3187 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
3188 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
3189 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
3190 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
3191 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
3192 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
3193
3194 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
3195 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
3196 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
3197 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
3198 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
3199 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
3200 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
3201 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
3202 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
3203 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
3204 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
3205 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
3206 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
3207 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
3208 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
3209 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
3210 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
3211
3212 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
3213 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
3214 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
3215 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
3216 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
3217 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
3218 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
3219 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
3220 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
3221 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
3222 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
3223 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
3224 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
3225 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
3226 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
3227
3228 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
3229 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
3230 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
3231 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
3232 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
3233 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
3234 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
3235 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
3236 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
3237 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
3238 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
3239 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
3240 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
3241 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
3242 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
3243
3244 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
3245 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
3246 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
3247 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
3248 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
3249 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
3250 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
3251 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
3252 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
3253 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
3254 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
3255 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
3256 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
3257 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
3258 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
3259 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
3260 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
3261
3262 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
3263 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
3264 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
3265 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
3266 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
3267 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
3268 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
3269 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
3270 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
3271 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
3272 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
3273 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
3274 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
3275 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
3276 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
3277 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
3278 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
3279
3280 /* Bit definitions for USB_ID_INT_SRC */
3281 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
3282 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
3283 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
3284 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
3285 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
3286 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
3287 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
3288 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
3289 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
3290 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
3291
3292 /* Bit definitions for USB_ID_INT_LATCH_SET */
3293 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
3294 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
3295 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
3296 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
3297 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
3298 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
3299 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
3300 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
3301 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
3302 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
3303
3304 /* Bit definitions for USB_ID_INT_LATCH_CLR */
3305 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
3306 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
3307 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
3308 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
3309 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
3310 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
3311 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
3312 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
3313 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
3314 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
3315
3316 /* Bit definitions for USB_ID_INT_EN_LO_SET */
3317 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
3318 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
3319 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
3320 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
3321 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
3322 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
3323 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
3324 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
3325 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
3326 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
3327
3328 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
3329 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
3330 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
3331 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
3332 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
3333 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
3334 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
3335 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
3336 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
3337 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
3338 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
3339
3340 /* Bit definitions for USB_ID_INT_EN_HI_SET */
3341 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
3342 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
3343 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
3344 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
3345 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
3346 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
3347 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
3348 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
3349 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
3350 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
3351
3352 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
3353 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
3354 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
3355 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
3356 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
3357 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
3358 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
3359 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
3360 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
3361 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
3362 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
3363
3364 /* Bit definitions for USB_OTG_ADP_CTRL */
3365 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
3366 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
3367 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
3368 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
3369
3370 /* Bit definitions for USB_OTG_ADP_HIGH */
3371 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
3372 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
3373
3374 /* Bit definitions for USB_OTG_ADP_LOW */
3375 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
3376 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
3377
3378 /* Bit definitions for USB_OTG_ADP_RISE */
3379 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
3380 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
3381
3382 /* Bit definitions for USB_OTG_REVISION */
3383 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
3384 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
3385
3386 /* Registers for function VIBRATOR */
3387 #define PALMAS_VIBRA_CTRL                                       0x0
3388
3389 /* Bit definitions for VIBRA_CTRL */
3390 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
3391 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
3392 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
3393 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
3394
3395 /* Registers for function GPIO */
3396 #define PALMAS_GPIO_DATA_IN                                     0x0
3397 #define PALMAS_GPIO_DATA_DIR                                    0x1
3398 #define PALMAS_GPIO_DATA_OUT                                    0x2
3399 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
3400 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
3401 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
3402 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
3403 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
3404 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
3405 #define PALMAS_GPIO_DATA_IN2                                    0x9
3406 #define PALMAS_GPIO_DATA_DIR2                                   0x0A
3407 #define PALMAS_GPIO_DATA_OUT2                                   0x0B
3408 #define PALMAS_GPIO_DEBOUNCE_EN2                                0x0C
3409 #define PALMAS_GPIO_CLEAR_DATA_OUT2                             0x0D
3410 #define PALMAS_GPIO_SET_DATA_OUT2                               0x0E
3411 #define PALMAS_PU_PD_GPIO_CTRL3                                 0x0F
3412 #define PALMAS_PU_PD_GPIO_CTRL4                                 0x10
3413 #define PALMAS_OD_OUTPUT_GPIO_CTRL2                             0x11
3414
3415 /* Bit definitions for GPIO_DATA_IN */
3416 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
3417 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
3418 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
3419 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
3420 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
3421 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
3422 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
3423 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
3424 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
3425 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
3426 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
3427 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
3428 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
3429 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
3430 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
3431 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
3432
3433 /* Bit definitions for GPIO_DATA_DIR */
3434 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
3435 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
3436 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
3437 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
3438 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
3439 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
3440 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
3441 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
3442 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
3443 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
3444 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
3445 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
3446 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
3447 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
3448 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
3449 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
3450
3451 /* Bit definitions for GPIO_DATA_OUT */
3452 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
3453 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
3454 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
3455 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
3456 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
3457 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
3458 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
3459 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
3460 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
3461 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
3462 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
3463 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
3464 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
3465 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
3466 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
3467 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
3468
3469 /* Bit definitions for GPIO_DEBOUNCE_EN */
3470 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
3471 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
3472 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
3473 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
3474 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
3475 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
3476 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
3477 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
3478 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
3479 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
3480 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
3481 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
3482 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
3483 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
3484 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
3485 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
3486
3487 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
3488 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
3489 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
3490 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
3491 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
3492 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
3493 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
3494 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
3495 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
3496 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
3497 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
3498 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
3499 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
3500 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
3501 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
3502 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
3503 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
3504
3505 /* Bit definitions for GPIO_SET_DATA_OUT */
3506 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
3507 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
3508 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
3509 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
3510 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
3511 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
3512 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
3513 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
3514 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
3515 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
3516 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
3517 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
3518 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
3519 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
3520 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
3521 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
3522
3523 /* Bit definitions for PU_PD_GPIO_CTRL1 */
3524 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
3525 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
3526 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
3527 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
3528 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
3529 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
3530 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
3531 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
3532 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
3533 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
3534 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
3535 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
3536
3537 /* Bit definitions for PU_PD_GPIO_CTRL2 */
3538 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
3539 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
3540 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
3541 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
3542 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
3543 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
3544 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
3545 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
3546 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
3547 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
3548 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
3549 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
3550 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
3551 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
3552
3553 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
3554 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
3555 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
3556 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
3557 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
3558 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
3559 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
3560
3561 /* Bit definitions for GPIO_DATA_IN2 */
3562 #define PALMAS_GPIO_DATA_IN_GPIO_15_IN                          0x80
3563 #define PALMAS_GPIO_DATA_IN_GPIO_15_IN_SHIFT                    7
3564 #define PALMAS_GPIO_DATA_IN_GPIO_14_IN                          0x40
3565 #define PALMAS_GPIO_DATA_IN_GPIO_14_IN_SHIFT                    6
3566 #define PALMAS_GPIO_DATA_IN_GPIO_13_IN                          0x20
3567 #define PALMAS_GPIO_DATA_IN_GPIO_13_IN_SHIFT                    5
3568 #define PALMAS_GPIO_DATA_IN_GPIO_12_IN                          0x10
3569 #define PALMAS_GPIO_DATA_IN_GPIO_12_IN_SHIFT                    4
3570 #define PALMAS_GPIO_DATA_IN_GPIO_11_IN                          0x08
3571 #define PALMAS_GPIO_DATA_IN_GPIO_11_IN_SHIFT                    3
3572 #define PALMAS_GPIO_DATA_IN_GPIO_10_IN                          0x04
3573 #define PALMAS_GPIO_DATA_IN_GPIO_10_IN_SHIFT                    2
3574 #define PALMAS_GPIO_DATA_IN_GPIO_9_IN                           0x02
3575 #define PALMAS_GPIO_DATA_IN_GPIO_9_IN_SHIFT                     1
3576 #define PALMAS_GPIO_DATA_IN_GPIO_8_IN                           0x01
3577 #define PALMAS_GPIO_DATA_IN_GPIO_8_IN_SHIFT                     0
3578
3579 /* Bit definitions for GPIO_DATA_DIR2 */
3580 #define PALMAS_GPIO_DATA_DIR_GPIO_15_DIR                        0x80
3581 #define PALMAS_GPIO_DATA_DIR_GPIO_15_DIR_SHIFT                  7
3582 #define PALMAS_GPIO_DATA_DIR_GPIO_14_DIR                        0x40
3583 #define PALMAS_GPIO_DATA_DIR_GPIO_14_DIR_SHIFT                  6
3584 #define PALMAS_GPIO_DATA_DIR_GPIO_13_DIR                        0x20
3585 #define PALMAS_GPIO_DATA_DIR_GPIO_13_DIR_SHIFT                  5
3586 #define PALMAS_GPIO_DATA_DIR_GPIO_12_DIR                        0x10
3587 #define PALMAS_GPIO_DATA_DIR_GPIO_12_DIR_SHIFT                  4
3588 #define PALMAS_GPIO_DATA_DIR_GPIO_11_DIR                        0x08
3589 #define PALMAS_GPIO_DATA_DIR_GPIO_11_DIR_SHIFT                  3
3590 #define PALMAS_GPIO_DATA_DIR_GPIO_10_DIR                        0x04
3591 #define PALMAS_GPIO_DATA_DIR_GPIO_10_DIR_SHIFT                  2
3592 #define PALMAS_GPIO_DATA_DIR_GPIO_9_DIR                         0x02
3593 #define PALMAS_GPIO_DATA_DIR_GPIO_9_DIR_SHIFT                   1
3594 #define PALMAS_GPIO_DATA_DIR_GPIO_8_DIR                         0x01
3595 #define PALMAS_GPIO_DATA_DIR_GPIO_8_DIR_SHIFT                   0
3596
3597 /* Bit definitions for GPIO_DATA_OUT2 */
3598 #define PALMAS_GPIO_DATA_OUT_GPIO_15_OUT                        0x80
3599 #define PALMAS_GPIO_DATA_OUT_GPIO_15_OUT_SHIFT                  7
3600 #define PALMAS_GPIO_DATA_OUT_GPIO_14_OUT                        0x40
3601 #define PALMAS_GPIO_DATA_OUT_GPIO_14_OUT_SHIFT                  6
3602 #define PALMAS_GPIO_DATA_OUT_GPIO_13_OUT                        0x20
3603 #define PALMAS_GPIO_DATA_OUT_GPIO_13_OUT_SHIFT                  5
3604 #define PALMAS_GPIO_DATA_OUT_GPIO_12_OUT                        0x10
3605 #define PALMAS_GPIO_DATA_OUT_GPIO_12_OUT_SHIFT                  4
3606 #define PALMAS_GPIO_DATA_OUT_GPIO_11_OUT                        0x08
3607 #define PALMAS_GPIO_DATA_OUT_GPIO_11_OUT_SHIFT                  3
3608 #define PALMAS_GPIO_DATA_OUT_GPIO_10_OUT                        0x04
3609 #define PALMAS_GPIO_DATA_OUT_GPIO_10_OUT_SHIFT                  2
3610 #define PALMAS_GPIO_DATA_OUT_GPIO_9_OUT                         0x02
3611 #define PALMAS_GPIO_DATA_OUT_GPIO_9_OUT_SHIFT                   1
3612 #define PALMAS_GPIO_DATA_OUT_GPIO_8_OUT                         0x01
3613 #define PALMAS_GPIO_DATA_OUT_GPIO_8_OUT_SHIFT                   0
3614
3615 /* Bit definitions for GPIO_DEBOUNCE_EN2 */
3616 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_15_DEBOUNCE_EN             0x80
3617 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_15_DEBOUNCE_EN_SHIFT       7
3618 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_14_DEBOUNCE_EN             0x40
3619 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_14_DEBOUNCE_EN_SHIFT       6
3620 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_13_DEBOUNCE_EN             0x20
3621 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_13_DEBOUNCE_EN_SHIFT       5
3622 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_12_DEBOUNCE_EN             0x10
3623 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_12_DEBOUNCE_EN_SHIFT       4
3624 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_11_DEBOUNCE_EN             0x08
3625 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_11_DEBOUNCE_EN_SHIFT       3
3626 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_10_DEBOUNCE_EN             0x04
3627 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_10_DEBOUNCE_EN_SHIFT       2
3628 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_9_DEBOUNCE_EN              0x02
3629 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_9_DEBOUNCE_EN_SHIFT        1
3630 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_8_DEBOUNCE_EN              0x01
3631 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_8_DEBOUNCE_EN_SHIFT        0
3632
3633 /* Bit definitions for GPIO_CLEAR_DATA_OUT2 */
3634 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_15_CLEAR_DATA_OUT       0x80
3635 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_15_CLEAR_DATA_OUT_SHIFT 7
3636 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_14_CLEAR_DATA_OUT       0x40
3637 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_14_CLEAR_DATA_OUT_SHIFT 6
3638 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_13_CLEAR_DATA_OUT       0x20
3639 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_13_CLEAR_DATA_OUT_SHIFT 5
3640 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_12_CLEAR_DATA_OUT       0x10
3641 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_12_CLEAR_DATA_OUT_SHIFT 4
3642 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_11_CLEAR_DATA_OUT       0x08
3643 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_11_CLEAR_DATA_OUT_SHIFT 3
3644 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_10_CLEAR_DATA_OUT       0x04
3645 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_10_CLEAR_DATA_OUT_SHIFT 2
3646 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_9_CLEAR_DATA_OUT        0x02
3647 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_9_CLEAR_DATA_OUT_SHIFT  1
3648 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_8_CLEAR_DATA_OUT        0x01
3649 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_8_CLEAR_DATA_OUT_SHIFT  0
3650
3651 /* Bit definitions for GPIO_SET_DATA_OUT2 */
3652 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_15_SET_DATA_OUT           0x80
3653 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_15_SET_DATA_OUT_SHIFT     7
3654 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_14_SET_DATA_OUT           0x40
3655 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_14_SET_DATA_OUT_SHIFT     6
3656 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_13_SET_DATA_OUT           0x20
3657 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_13_SET_DATA_OUT_SHIFT     5
3658 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_12_SET_DATA_OUT           0x10
3659 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_12_SET_DATA_OUT_SHIFT     4
3660 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_11_SET_DATA_OUT           0x08
3661 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_11_SET_DATA_OUT_SHIFT     3
3662 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_10_SET_DATA_OUT           0x04
3663 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_10_SET_DATA_OUT_SHIFT     2
3664 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_9_SET_DATA_OUT            0x02
3665 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_9_SET_DATA_OUT_SHIFT      1
3666 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_8_SET_DATA_OUT            0x01
3667 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_8_SET_DATA_OUT_SHIFT      0
3668
3669 /* Bit definitions for PU_PD_GPIO_CTRL3 */
3670 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_11_PD                      0x40
3671 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_11_PD_SHIFT                6
3672 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PU                      0x20
3673 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PU_SHIFT                5
3674 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PD                      0x10
3675 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PD_SHIFT                4
3676 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PU                       0x08
3677 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PU_SHIFT                 3
3678 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PD                       0x04
3679 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PD_SHIFT                 2
3680
3681 /* Bit definitions for PU_PD_GPIO_CTRL4 */
3682 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PU                      0x20
3683 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PU_SHIFT                5
3684 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PD                      0x10
3685 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PD_SHIFT                4
3686
3687 /* Bit definitions for OD_OUTPUT_GPIO_CTRL2 */
3688 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_10_OD                   0x04
3689 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_10_OD_SHIFT             2
3690
3691 /* Registers for function GPADC */
3692 #define PALMAS_GPADC_CTRL1                                      0x0
3693 #define PALMAS_GPADC_CTRL2                                      0x1
3694 #define PALMAS_GPADC_RT_CTRL                                    0x2
3695 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
3696 #define PALMAS_GPADC_STATUS                                     0x4
3697 #define PALMAS_GPADC_RT_SELECT                                  0x5
3698 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
3699 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
3700 #define PALMAS_GPADC_AUTO_SELECT                                0x8
3701 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
3702 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
3703 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
3704 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
3705 #define PALMAS_GPADC_SW_SELECT                                  0xD
3706 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
3707 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
3708 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
3709 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
3710 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
3711 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
3712 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
3713 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
3714
3715 /* Bit definitions for GPADC_CTRL1 */
3716 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
3717 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
3718 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
3719 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
3720 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
3721 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
3722 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
3723 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
3724 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
3725 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
3726
3727 /* Bit definitions for GPADC_CTRL2 */
3728 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
3729 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
3730
3731 /* Bit definitions for GPADC_RT_CTRL */
3732 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
3733 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
3734 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
3735 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
3736
3737 /* Bit definitions for GPADC_AUTO_CTRL */
3738 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
3739 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
3740 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
3741 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
3742 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
3743 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
3744 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
3745 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
3746 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
3747 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
3748
3749 /* Bit definitions for GPADC_STATUS */
3750 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
3751 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
3752
3753 /* Bit definitions for GPADC_RT_SELECT */
3754 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
3755 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
3756 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
3757 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
3758
3759 /* Bit definitions for GPADC_RT_CONV0_LSB */
3760 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
3761 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
3762
3763 /* Bit definitions for GPADC_RT_CONV0_MSB */
3764 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
3765 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
3766
3767 /* Bit definitions for GPADC_AUTO_SELECT */
3768 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
3769 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
3770 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
3771 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
3772
3773 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
3774 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
3775 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
3776
3777 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
3778 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
3779 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
3780
3781 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
3782 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
3783 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
3784
3785 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
3786 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
3787 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
3788
3789 /* Bit definitions for GPADC_SW_SELECT */
3790 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
3791 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
3792 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
3793 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
3794 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
3795 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
3796
3797 /* Bit definitions for GPADC_SW_CONV0_LSB */
3798 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
3799 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
3800
3801 /* Bit definitions for GPADC_SW_CONV0_MSB */
3802 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
3803 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
3804
3805 /* Bit definitions for GPADC_THRES_CONV0_LSB */
3806 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
3807 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
3808
3809 /* Bit definitions for GPADC_THRES_CONV0_MSB */
3810 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
3811 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
3812 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
3813 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
3814
3815 /* Bit definitions for GPADC_THRES_CONV1_LSB */
3816 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
3817 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
3818
3819 /* Bit definitions for GPADC_THRES_CONV1_MSB */
3820 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
3821 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
3822 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
3823 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
3824
3825 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
3826 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
3827 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
3828 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
3829 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
3830 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
3831 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
3832
3833 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3834 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
3835 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
3836 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
3837 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
3838
3839 #define PALMAS_INTERNAL_DESIGNREV                               0x57
3840 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
3841
3842 /* Registers for function GPADC */
3843 #define PALMAS_GPADC_TRIM1                                      0x0
3844 #define PALMAS_GPADC_TRIM2                                      0x1
3845 #define PALMAS_GPADC_TRIM3                                      0x2
3846 #define PALMAS_GPADC_TRIM4                                      0x3
3847 #define PALMAS_GPADC_TRIM5                                      0x4
3848 #define PALMAS_GPADC_TRIM6                                      0x5
3849 #define PALMAS_GPADC_TRIM7                                      0x6
3850 #define PALMAS_GPADC_TRIM8                                      0x7
3851 #define PALMAS_GPADC_TRIM9                                      0x8
3852 #define PALMAS_GPADC_TRIM10                                     0x9
3853 #define PALMAS_GPADC_TRIM11                                     0xA
3854 #define PALMAS_GPADC_TRIM12                                     0xB
3855 #define PALMAS_GPADC_TRIM13                                     0xC
3856 #define PALMAS_GPADC_TRIM14                                     0xD
3857 #define PALMAS_GPADC_TRIM15                                     0xE
3858 #define PALMAS_GPADC_TRIM16                                     0xF
3859 #define PALMAS_GPADC_TRIMINVALID                                -1
3860
3861 /* Registers for function BQ24192 */
3862 #define PALMAS_CHARGER_REG00                                    0x00
3863 #define PALMAS_CHARGER_REG01                                    0x01
3864 #define PALMAS_CHARGER_REG02                                    0x02
3865 #define PALMAS_CHARGER_REG03                                    0x03
3866 #define PALMAS_CHARGER_REG04                                    0x04
3867 #define PALMAS_CHARGER_REG05                                    0x05
3868 #define PALMAS_CHARGER_REG06                                    0x06
3869 #define PALMAS_CHARGER_REG07                                    0x07
3870 #define PALMAS_CHARGER_REG08                                    0x08
3871 #define PALMAS_CHARGER_REG09                                    0x09
3872 #define PALMAS_CHARGER_REG10                                    0x0a
3873
3874 #define BQ24190_IC_VER                  0x20
3875 #define BQ24192_IC_VER                  0x28
3876 #define BQ24192i_IC_VER                 0x18
3877
3878 #define PALMAS_ENABLE_CHARGE_MASK      0x30
3879 #define PALMAS_DISABLE_CHARGE          0x00
3880 #define PALMAS_ENABLE_CHARGE           0x10
3881 #define PALMAS_ENABLE_VBUS             0x20
3882 #define PALMAS_DISABLE_CHARGE           0x00
3883
3884 #define PALMAS_REG0                    0x0
3885 #define PALMAS_EN_HIZ                  BIT(7)
3886
3887 #define PALMAS_CHRG_CTRL_REG_3A        0xC0
3888 #define PALMAS_OTP_CURRENT_500MA       0x32
3889
3890 #define PALMAS_WD                      0x5
3891 #define PALMAS_WD_MASK                 0x30
3892 #define PALMAS_WD_DISABLE              0x00
3893 #define PALMAS_WD_40ms                 0x10
3894 #define PALMAS_WD_80ms                 0x20
3895 #define PALMAS_WD_160ms                0x30
3896
3897 #define PALMAS_VBUS_STAT               0xc0
3898 #define PALMAS_VBUS_UNKNOWN            0x00
3899 #define PALMAS_VBUS_USB                0x40
3900 #define PALMAS_VBUS_AC                 0x80
3901
3902 #define PALMAS_CHRG_STATE_MASK                 0x30
3903 #define PALMAS_CHRG_STATE_NOTCHARGING          0x00
3904 #define PALMAS_CHRG_STATE_PRE_CHARGE           0x10
3905 #define PALMAS_CHRG_STATE_POST_CHARGE          0x20
3906 #define PALMAS_CHRG_STATE_CHARGE_DONE          0x30
3907
3908 #define PALMAS_FAULT_WATCHDOG_FAULT            BIT(7)
3909 #define PALMAS_FAULT_BOOST_FAULT               BIT(6)
3910 #define PALMAS_FAULT_CHRG_FAULT_MASK           0x30
3911 #define PALMAS_FAULT_CHRG_NORMAL               0x00
3912 #define PALMAS_FAULT_CHRG_INPUT                0x10
3913 #define PALMAS_FAULT_CHRG_THERMAL              0x20
3914 #define PALMAS_FAULT_CHRG_SAFTY                0x30
3915
3916 #define PALMAS_FAULT_NTC_FAULT                 0x07
3917
3918 #define PALMAS_CONFIG_MASK             0x7
3919 #define PALMAS_INPUT_VOLTAGE_MASK      0x78
3920 #define PALMAS_NVCHARGER_INPUT_VOL_SEL 0x40
3921 #define PALMAS_DEFAULT_INPUT_VOL_SEL   0x30
3922
3923 #define PALMAS_CHARGE_VOLTAGE_MASK              0xFC
3924 #define PALMAS_CHARGE_VOLTAGE_4112MV            0x98
3925 #define PALMAS_CHARGE_VOLTAGE_4048MV            0x88
3926
3927 #define PALMAS_MAX_REGS                (PALMAS_REVISION_REG + 1)
3928
3929 /* Registers for function FUEL_GAUGE */
3930 #define PALMAS_FG_REG_00                                      0x0
3931 #define PALMAS_FG_REG_01                                      0x1
3932 #define PALMAS_FG_REG_02                                      0x2
3933 #define PALMAS_FG_REG_03                                      0x3
3934 #define PALMAS_FG_REG_04                                      0x4
3935 #define PALMAS_FG_REG_05                                      0x5
3936 #define PALMAS_FG_REG_06                                      0x6
3937 #define PALMAS_FG_REG_07                                      0x7
3938 #define PALMAS_FG_REG_08                                      0x8
3939 #define PALMAS_FG_REG_09                                      0x9
3940 #define PALMAS_FG_REG_10                                      0xA
3941 #define PALMAS_FG_REG_11                                      0xB
3942 #define PALMAS_FG_REG_12                                      0xC
3943 #define PALMAS_FG_REG_13                                      0xD
3944 #define PALMAS_FG_REG_14                                      0xE
3945 #define PALMAS_FG_REG_15                                      0xF
3946 #define PALMAS_FG_REG_16                                      0x10
3947 #define PALMAS_FG_REG_17                                      0x11
3948 #define PALMAS_FG_REG_18                                      0x12
3949 #define PALMAS_FG_REG_19                                      0x13
3950 #define PALMAS_FG_REG_20                                      0x14
3951 #define PALMAS_FG_REG_21                                      0x15
3952 #define PALMAS_FG_REG_22                                      0x16
3953
3954 /* Bit definitions for FG_REG_00 */
3955 #define PALMAS_FG_REG_00_CC_ACTIVE_MODE_MASK                  0xc0
3956 #define PALMAS_FG_REG_00_CC_ACTIVE_MODE_SHIFT                 6
3957 #define PALMAS_FG_REG_00_CC_BAT_STABLE_EN                     0x20
3958 #define PALMAS_FG_REG_00_CC_BAT_STABLE_EN_SHIFT                       5
3959 #define PALMAS_FG_REG_00_CC_DITH_EN                           0x10
3960 #define PALMAS_FG_REG_00_CC_DITH_EN_SHIFT                     4
3961 #define PALMAS_FG_REG_00_CC_FG_EN                             0x08
3962 #define PALMAS_FG_REG_00_CC_FG_EN_SHIFT                               3
3963 #define PALMAS_FG_REG_00_CC_AUTOCLEAR                         0x04
3964 #define PALMAS_FG_REG_00_CC_AUTOCLEAR_SHIFT                   2
3965 #define PALMAS_FG_REG_00_CC_CAL_EN                            0x02
3966 #define PALMAS_FG_REG_00_CC_CAL_EN_SHIFT                      1
3967 #define PALMAS_FG_REG_00_CC_PAUSE                             0x01
3968 #define PALMAS_FG_REG_00_CC_PAUSE_SHIFT                               0
3969
3970 /* Bit definitions for FG_REG_01 */
3971 #define PALMAS_FG_REG_01_CC_SAMPLE_CNTR_MASK                  0xff
3972 #define PALMAS_FG_REG_01_CC_SAMPLE_CNTR_SHIFT                 0
3973
3974 /* Bit definitions for FG_REG_02 */
3975 #define PALMAS_FG_REG_02_CC_SAMPLE_CNTR_MASK                  0xff
3976 #define PALMAS_FG_REG_02_CC_SAMPLE_CNTR_SHIFT                 0
3977
3978 /* Bit definitions for FG_REG_03 */
3979 #define PALMAS_FG_REG_03_CC_SAMPLE_CNTR_MASK                  0xff
3980 #define PALMAS_FG_REG_03_CC_SAMPLE_CNTR_SHIFT                 0
3981
3982 /* Bit definitions for FG_REG_04 */
3983 #define PALMAS_FG_REG_04_CC_ACCUM_MASK                                0xff
3984 #define PALMAS_FG_REG_04_CC_ACCUM_SHIFT                               0
3985
3986 /* Bit definitions for FG_REG_05 */
3987 #define PALMAS_FG_REG_05_CC_ACCUM_MASK                                0xff
3988 #define PALMAS_FG_REG_05_CC_ACCUM_SHIFT                               0
3989
3990 /* Bit definitions for FG_REG_06 */
3991 #define PALMAS_FG_REG_06_CC_ACCUM_MASK                                0xff
3992 #define PALMAS_FG_REG_06_CC_ACCUM_SHIFT                               0
3993
3994 /* Bit definitions for FG_REG_07 */
3995 #define PALMAS_FG_REG_07_CC_ACCUM_MASK                                0xff
3996 #define PALMAS_FG_REG_07_CC_ACCUM_SHIFT                               0
3997
3998 /* Bit definitions for FG_REG_08 */
3999 #define PALMAS_FG_REG_08_CC_OFFSET_MASK                               0xff
4000 #define PALMAS_FG_REG_08_CC_OFFSET_SHIFT                      0
4001
4002 /* Bit definitions for FG_REG_09 */
4003 #define PALMAS_FG_REG_09_CC_OFFSET_MASK                               0x03
4004 #define PALMAS_FG_REG_09_CC_OFFSET_SHIFT                      0
4005
4006 /* Bit definitions for FG_REG_10 */
4007 #define PALMAS_FG_REG_10_CC_INTEG_MASK                                0xff
4008 #define PALMAS_FG_REG_10_CC_INTEG_SHIFT                               0
4009
4010 /* Bit definitions for FG_REG_11 */
4011 #define PALMAS_FG_REG_11_CC_INTEG_MASK                                0x3f
4012 #define PALMAS_FG_REG_11_CC_INTEG_SHIFT                               0
4013
4014 /* Bit definitions for FG_REG_12 */
4015 #define PALMAS_FG_REG_12_CC_VBAT_SYNC_MASK                    0xfc
4016 #define PALMAS_FG_REG_12_CC_VBAT_SYNC_SHIFT                   2
4017 #define PALMAS_FG_REG_12_CC_SYNC_EN                           0x02
4018 #define PALMAS_FG_REG_12_CC_SYNC_EN_SHIFT                     1
4019 #define PALMAS_FG_REG_12_CC_SYNC_RDY                          0x01
4020 #define PALMAS_FG_REG_12_CC_SYNC_RDY_SHIFT                    0
4021
4022 /* Bit definitions for FG_REG_13 */
4023 #define PALMAS_FG_REG_13_CC_VBAT_SYNC_MASK                    0x3f
4024 #define PALMAS_FG_REG_13_CC_VBAT_SYNC_SHIFT                   0
4025
4026 /* Bit definitions for FG_REG_14 */
4027 #define PALMAS_FG_REG_14_CC_VBAT_CNTR_MASK                    0xff
4028 #define PALMAS_FG_REG_14_CC_VBAT_CNTR_SHIFT                   0
4029
4030 /* Bit definitions for FG_REG_15 */
4031 #define PALMAS_FG_REG_15_CC_VBAT_CNTR_MASK                    0x03
4032 #define PALMAS_FG_REG_15_CC_VBAT_CNTR_SHIFT                   0
4033
4034 /* Bit definitions for FG_REG_16 */
4035 #define PALMAS_FG_REG_16_CC_VBAT_ACCUM_MASK                   0xff
4036 #define PALMAS_FG_REG_16_CC_VBAT_ACCUM_SHIFT                  0
4037
4038 /* Bit definitions for FG_REG_17 */
4039 #define PALMAS_FG_REG_17_CC_VBAT_ACCUM_MASK                   0xff
4040 #define PALMAS_FG_REG_17_CC_VBAT_ACCUM_SHIFT                  0
4041
4042 /* Bit definitions for FG_REG_18 */
4043 #define PALMAS_FG_REG_18_CC_VBAT_ACCUM_MASK                   0x3f
4044 #define PALMAS_FG_REG_18_CC_VBAT_ACCUM_SHIFT                  0
4045
4046 /* Bit definitions for FG_REG_19 */
4047 #define PALMAS_FG_REG_19_CC_CUR_LVL_MASK                      0x3f
4048 #define PALMAS_FG_REG_19_CC_CUR_LVL_SHIFT                     0
4049
4050 /* Bit definitions for FG_REG_20 */
4051 #define PALMAS_FG_REG_20_BAT_SLEEP_STATUS                     0x40
4052 #define PALMAS_FG_REG_20_BAT_SLEEP_STATUS_SHIFT                       6
4053 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_PERIOD_MASK             0x30
4054 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_PERIOD_SHIFT            4
4055 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_EXIT_MASK                       0x0c
4056 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_EXIT_SHIFT              2
4057 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_ENTER_MASK              0x03
4058 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_ENTER_SHIFT             0
4059
4060 /* Bit definitions for FG_REG_21 */
4061 #define PALMAS_FG_REG_21_CC_OVERCUR_THRES_MASK                        0x7f
4062 #define PALMAS_FG_REG_21_CC_OVERCUR_THRES_SHIFT                       0
4063
4064 /* Bit definitions for FG_REG_22 */
4065 #define PALMAS_FG_REG_22_CC_CHOPPER_DIS                               0x80
4066 #define PALMAS_FG_REG_22_CC_CHOPPER_DIS_SHIFT                 7
4067 #define PALMAS_FG_REG_22_CC_NSLEEP_GATE                               0x08
4068 #define PALMAS_FG_REG_22_CC_NSLEEP_GATE_SHIFT                 3
4069 #define PALMAS_FG_REG_22_CC_OVC_EN                            0x04
4070 #define PALMAS_FG_REG_22_CC_OVC_EN_SHIFT                      2
4071 #define PALMAS_FG_REG_22_CC_OVC_PER_MASK                      0x03
4072 #define PALMAS_FG_REG_22_CC_OVC_PER_SHIFT                     0
4073
4074 enum {
4075         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
4076         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
4077         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
4078 };
4079
4080 /**
4081  * Palmas regulator configs
4082  * PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF: Force off on suspend
4083  * PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE: Enable tracking of regualtor.
4084  * PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE: Disable tracking in
4085                 suspend.
4086  */
4087 enum {
4088         PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF               = 0x1,
4089         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE                 = 0x2,
4090         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE        = 0x4,
4091         PALMAS_REGULATOR_CONFIG_VSEL_VOLATILE                   = 0x8,
4092 };
4093
4094 /*
4095  *PALMAS GPIOs
4096  */
4097 enum {
4098         PALMAS_GPIO0,
4099         PALMAS_GPIO1,
4100         PALMAS_GPIO2,
4101         PALMAS_GPIO3,
4102         PALMAS_GPIO4,
4103         PALMAS_GPIO5,
4104         PALMAS_GPIO6,
4105         PALMAS_GPIO7,
4106         PALMAS_GPIO8,
4107         PALMAS_GPIO9,
4108         PALMAS_GPIO10,
4109         PALMAS_GPIO11,
4110         PALMAS_GPIO12,
4111         PALMAS_GPIO13,
4112         PALMAS_GPIO14,
4113         PALMAS_GPIO15,
4114
4115         PALMAS_GPIO_NR,
4116 };
4117
4118 /* Palma GPADC Channels */
4119 enum {
4120         PALMAS_ADC_CH_IN0,
4121         PALMAS_ADC_CH_IN1,
4122         PALMAS_ADC_CH_IN2,
4123         PALMAS_ADC_CH_IN3,
4124         PALMAS_ADC_CH_IN4,
4125         PALMAS_ADC_CH_IN5,
4126         PALMAS_ADC_CH_IN6,
4127         PALMAS_ADC_CH_IN7,
4128         PALMAS_ADC_CH_IN8,
4129         PALMAS_ADC_CH_IN9,
4130         PALMAS_ADC_CH_IN10,
4131         PALMAS_ADC_CH_IN11,
4132         PALMAS_ADC_CH_IN12,
4133         PALMAS_ADC_CH_IN13,
4134         PALMAS_ADC_CH_IN14,
4135         PALMAS_ADC_CH_IN15,
4136
4137         PALMAS_ADC_CH_MAX,
4138 };
4139
4140 /* Palma GPADC Channel0 Current Source */
4141 enum {
4142         PALMAS_ADC_CH0_CURRENT_SRC_0,
4143         PALMAS_ADC_CH0_CURRENT_SRC_5,
4144         PALMAS_ADC_CH0_CURRENT_SRC_15,
4145         PALMAS_ADC_CH0_CURRENT_SRC_20,
4146 };
4147
4148 /* Palma GPADC Channel3 Current Source */
4149 enum {
4150         PALMAS_ADC_CH3_CURRENT_SRC_0,
4151         PALMAS_ADC_CH3_CURRENT_SRC_10,
4152         PALMAS_ADC_CH3_CURRENT_SRC_400,
4153         PALMAS_ADC_CH3_CURRENT_SRC_800,
4154 };
4155
4156 /* Palma Sleep requestor IDs IDs */
4157 enum {
4158         PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
4159         PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
4160         PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
4161         PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
4162         PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
4163         PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
4164         PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
4165         PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
4166         PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
4167         PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
4168         PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
4169         PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
4170         PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
4171         PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
4172         PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
4173         PALMAS_EXTERNAL_REQSTR_ID_LDO1,
4174         PALMAS_EXTERNAL_REQSTR_ID_LDO2,
4175         PALMAS_EXTERNAL_REQSTR_ID_LDO3,
4176         PALMAS_EXTERNAL_REQSTR_ID_LDO4,
4177         PALMAS_EXTERNAL_REQSTR_ID_LDO5,
4178         PALMAS_EXTERNAL_REQSTR_ID_LDO6,
4179         PALMAS_EXTERNAL_REQSTR_ID_LDO7,
4180         PALMAS_EXTERNAL_REQSTR_ID_LDO8,
4181         PALMAS_EXTERNAL_REQSTR_ID_LDO9,
4182         PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
4183         PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
4184         PALMAS_EXTERNAL_REQSTR_ID_LDO10,
4185         PALMAS_EXTERNAL_REQSTR_ID_LDO11,
4186         PALMAS_EXTERNAL_REQSTR_ID_LDO12,
4187         PALMAS_EXTERNAL_REQSTR_ID_LDO13,
4188         PALMAS_EXTERNAL_REQSTR_ID_LDO14,
4189         PALMAS_EXTERNAL_REQSTR_ID_REGEN4,
4190         PALMAS_EXTERNAL_REQSTR_ID_REGEN5,
4191         PALMAS_EXTERNAL_REQSTR_ID_REGEN7,
4192
4193         /* Last entry */
4194         PALMAS_EXTERNAL_REQSTR_ID_MAX,
4195 };
4196
4197 extern int palmas_ext_power_req_config(struct palmas *palmas,
4198                 int id,  int ext_pwr_ctrl, bool enable);
4199
4200 static inline int palmas_read(struct palmas *palmas, unsigned int base,
4201                 unsigned int reg, unsigned int *val)
4202 {
4203         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
4204         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4205
4206         return regmap_read(palmas->regmap[slave_id], addr, val);
4207 }
4208
4209 static inline int palmas_write(struct palmas *palmas, unsigned int base,
4210                 unsigned int reg, unsigned int value)
4211 {
4212         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4213         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4214
4215         return regmap_write(palmas->regmap[slave_id], addr, value);
4216 }
4217
4218 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
4219         unsigned int reg, const void *val, size_t val_count)
4220 {
4221         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4222         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4223
4224         return regmap_bulk_write(palmas->regmap[slave_id], addr,
4225                         val, val_count);
4226 }
4227
4228 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
4229                 unsigned int reg, void *val, size_t val_count)
4230 {
4231         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4232         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4233
4234         return regmap_bulk_read(palmas->regmap[slave_id], addr,
4235                 val, val_count);
4236 }
4237
4238 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
4239         unsigned int reg, unsigned int mask, unsigned int val)
4240 {
4241         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4242         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4243
4244         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
4245 }
4246
4247 static inline void palmas_allow_atomic_xfer(struct palmas *palmas)
4248 {
4249         i2c_shutdown_clear_adapter(palmas->i2c_clients[0]->adapter);
4250 }
4251
4252 extern int palmas_irq_get_virq(struct palmas *palmas, int irq);
4253
4254 static inline int palmas_is_es_version_or_less(struct palmas *palmas,
4255         int major, int minor)
4256 {
4257         if (palmas->es_major_version < major)
4258                 return true;
4259
4260         if ((palmas->es_major_version == major) &&
4261                 (palmas->es_minor_version <= minor))
4262                 return true;
4263
4264         return false;
4265 }
4266
4267 #define PALMAS_DATASHEET_NAME(_name)    "palmas-gpadc-chan-"#_name
4268
4269 #define PALMAS_GPADC_IIO_MAP(chan, _consumer, _comsumer_channel_name)   \
4270 {                                                                       \
4271         .adc_channel_label = PALMAS_DATASHEET_NAME(chan),               \
4272         .consumer_dev_name = _consumer,                                 \
4273         .consumer_channel = _comsumer_channel_name,                     \
4274 }
4275
4276 #endif /*  __LINUX_MFD_PALMAS_H */