thermal: Add palmas thermal support
[linux-3.10.git] / include / linux / mfd / palmas.h
1 /*
2  * TI Palmas
3  *
4  * Copyright 2011-2013 Texas Instruments Inc.
5  * Copyright (c) 2013, NVIDIA CORPORATION.  All rights reserved.
6  *
7  * Author: Graeme Gregory <gg@slimlogic.co.uk>
8  * Author: Ian Lartey <ian@slimlogic.co.uk>
9  *
10  *  This program is free software; you can redistribute it and/or modify it
11  *  under  the terms of the GNU General  Public License as published by the
12  *  Free Software Foundation;  either version 2 of the License, or (at your
13  *  option) any later version.
14  *
15  */
16
17 #ifndef __LINUX_MFD_PALMAS_H
18 #define __LINUX_MFD_PALMAS_H
19
20 #include <linux/usb/otg.h>
21 #include <linux/leds.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/driver.h>
24 #include <linux/regulator/machine.h>
25 #include <linux/kthread.h>
26 #include <linux/iio/machine.h>
27 #include <linux/extcon.h>
28 #include <linux/thermal.h>
29
30 #define PALMAS_NUM_CLIENTS      4
31
32 /* Fuel Gauge Constatnts */
33 #define MAX_CAPACITY    0x7fff
34 #define MAX_SOC         100
35 #define MAX_PERCENTAGE  100
36
37 /* Num, cycles with no Learning, after this many cycles, the gauge
38    start adjusting FCC, based on Estimated Cell Degradation */
39 #define NO_LEARNING_CYCLES      25
40
41 /* Size of the OCV Lookup table */
42 #define OCV_TABLE_SIZE  21
43
44 /* OCV Configuration */
45 struct ocv_config {
46         unsigned char voltage_diff;
47         unsigned char current_diff;
48
49         unsigned short sleep_enter_current;
50         unsigned char sleep_enter_samples;
51
52         unsigned short sleep_exit_current;
53         unsigned char sleep_exit_samples;
54
55         unsigned short long_sleep_current;
56
57         unsigned int ocv_period;
58         unsigned int relax_period;
59
60         unsigned char flat_zone_low;
61         unsigned char flat_zone_high;
62
63         unsigned short max_ocv_discharge;
64
65         unsigned short table[OCV_TABLE_SIZE];
66 };
67
68 /* EDV Point */
69 struct edv_point {
70         short voltage;
71         unsigned char percent;
72 };
73
74 /* EDV Point tracking data */
75 struct edv_state {
76         short voltage;
77         unsigned char percent;
78         short min_capacity;
79         unsigned char edv_cmp;
80 };
81
82 /* EDV Configuration */
83 struct edv_config {
84         bool averaging;
85
86         unsigned char seq_edv;
87
88         unsigned char filter_light;
89         unsigned char filter_heavy;
90         short overload_current;
91
92         struct edv_point edv[3];
93 };
94
95 /* General Battery Cell Configuration */
96 struct cell_config {
97         int technology;
98         bool cc_polarity;
99         bool cc_out;
100         bool ocv_below_edv1;
101
102         short cc_voltage;
103         short cc_current;
104         unsigned char cc_capacity;
105         unsigned char seq_cc;
106
107         unsigned short design_capacity;
108         short design_qmax;
109
110         unsigned char r_sense;
111
112         unsigned char qmax_adjust;
113         unsigned char fcc_adjust;
114
115         unsigned short max_overcharge;
116         unsigned short electronics_load; /* *10uAh */
117
118         short max_increment;
119         short max_decrement;
120         unsigned char low_temp;
121         unsigned short deep_dsg_voltage;
122         unsigned short max_dsg_estimate;
123         unsigned char light_load;
124         unsigned short near_full;
125         unsigned short cycle_threshold;
126         unsigned short recharge;
127
128         unsigned char mode_switch_capacity;
129
130         unsigned char call_period;
131
132         struct ocv_config *ocv;
133         struct edv_config *edv;
134 };
135
136 /* Cell State */
137 struct cell_state {
138         short soc;
139
140         short nac;
141
142         short fcc;
143         short qmax;
144
145         short voltage;
146         short av_voltage;
147         short cur;
148         short av_current;
149
150         short temperature;
151         short cycle_count;
152
153         bool sleep;
154         bool relax;
155
156         bool chg;
157         bool dsg;
158
159         bool edv0;
160         bool edv1;
161         bool edv2;
162         bool ocv;
163         bool cc;
164         bool full;
165
166         bool vcq;
167         bool vdq;
168         bool init;
169
170         struct timeval last_correction;
171         struct timeval last_ocv;
172         struct timeval sleep_timer;
173         struct timeval el_timer;
174         unsigned int cumulative_sleep;
175
176         short prev_soc;
177         short learn_q;
178         unsigned short dod_eoc;
179         short learn_offset;
180         unsigned short learned_cycle;
181         short new_fcc;
182         short ocv_total_q;
183         short ocv_enter_q;
184         short negative_q;
185         short overcharge_q;
186         short charge_cycle_q;
187         short discharge_cycle_q;
188         short cycle_q;
189         short top_off_q;
190         unsigned char seq_cc_voltage;
191         unsigned char seq_cc_current;
192         unsigned char sleep_samples;
193         unsigned char seq_edvs;
194
195         unsigned int electronics_load;
196         unsigned short cycle_dsg_estimate;
197
198         struct edv_state edv;
199
200         bool updated;
201         bool calibrate;
202
203         struct cell_config *config;
204         struct device *dev;
205
206         int *charge_status;
207 };
208
209 /* The ID_REVISION NUMBERS */
210 #define PALMAS_CHIP_OLD_ID              0x0000
211 #define PALMAS_CHIP_ID                  0xC035
212 #define PALMAS_CHIP_CHARGER_ID          0xC036
213
214 #define is_palmas(a)    (((a) == PALMAS_CHIP_OLD_ID) || \
215                         ((a) == PALMAS_CHIP_ID))
216 #define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
217
218 struct palmas_pmic;
219 struct palmas_gpadc;
220 struct palmas_resource;
221 struct palmas_usb;
222 struct palmas_rtc;
223 struct palmas_battery_info;
224
225 #define palmas_rails(_name) "palmas_"#_name
226
227 struct palmas {
228         struct device *dev;
229
230         struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
231         struct regmap *regmap[PALMAS_NUM_CLIENTS];
232
233         /* Stored chip id */
234         int id;
235
236         unsigned int submodule_lists;
237
238         /* IRQ Data */
239         int irq;
240         u32 irq_mask;
241         struct palmas_irq_chip_data *irq_chip_data;
242
243         /* Child Devices */
244         struct palmas_pmic *pmic;
245         struct palmas_gpadc *gpadc;
246         struct palmas_resource *resource;
247         struct palmas_usb *usb;
248         struct palmas_rtc *rtc;
249         struct palmas_battery_info *battery;
250
251         /* GPIO MUXing */
252         u8 ngpio;
253         u16 gpio_muxed;
254         u8 led_muxed;
255         u8 pwm_muxed;
256
257         int design_revision;
258         int sw_otp_version;
259         int es_minor_version;
260         int es_major_version;
261 };
262
263 /*
264  * ADC wakeup property: Wakup the system from suspend when threshold crossed.
265  * @adc_channel_number: ADC channel number for monitoring.
266  * @adc_high_threshold: ADC High raw data for upper threshold to generate int.
267  * @adc_low_threshold: ADC low raw data for lower threshold to generate int.
268  */
269 struct palmas_adc_wakeup_property {
270         int adc_channel_number;
271         int adc_high_threshold;
272         int adc_low_threshold;
273 };
274
275 struct palmas_gpadc_platform_data {
276         /* Channel 3 current source is only enabled during conversion */
277         int ch3_current;
278
279         /* Channel 0 current source can be used for battery detection.
280          * If used for battery detection this will cause a permanent current
281          * consumption depending on current level set here.
282          */
283         int ch0_current;
284
285         /* default BAT_REMOVAL_DAT setting on device probe */
286         int bat_removal;
287
288         /* Sets the START_POLARITY bit in the RT_CTRL register */
289         int start_polarity;
290
291         struct iio_map *iio_maps;
292         int auto_conversion_period_ms;
293         struct palmas_adc_wakeup_property *adc_wakeup1_data;
294         struct palmas_adc_wakeup_property *adc_wakeup2_data;
295 };
296
297 struct palmas_reg_init {
298         /* warm_rest controls the voltage levels after a warm reset
299          *
300          * 0: reload default values from OTP on warm reset
301          * 1: maintain voltage from VSEL on warm reset
302          */
303         int warm_reset;
304
305         /* roof_floor controls whether the regulator uses the i2c style
306          * of DVS or uses the method where a GPIO or other control method is
307          * attached to the NSLEEP/ENABLE1/ENABLE2 pins
308          *
309          * For SMPS
310          *
311          * 0: i2c selection of voltage
312          * 1: pin selection of voltage.
313          *
314          * For LDO unused
315          */
316         int roof_floor;
317
318         /*
319          * If the rail is externally controlled and the external signal is
320          * connected to gpios of the SoCs then this can be provided by
321          * enable_gpio;
322          */
323         int enable_gpio;
324
325         /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
326          * the data sheet.
327          *
328          * For SMPS
329          *
330          * 0: Off
331          * 1: AUTO
332          * 2: ECO
333          * 3: Forced PWM
334          *
335          * For LDO
336          *
337          * 0: Off
338          * 1: On
339          */
340         int mode_sleep;
341
342         /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
343          * register. Set this is the default voltage set in OTP needs
344          * to be overridden.
345          */
346         u8 vsel;
347
348         /* Configuration flags */
349         unsigned int config_flags;
350
351         /*
352          * tracking_regulator will tell which regulator will be tracked
353          * This will be used when regulator tracking is enabled and
354          * device supports.
355          */
356         int tracking_regulator;
357 };
358
359 enum palmas_regulators {
360         /* SMPS regulators */
361         PALMAS_REG_SMPS12,
362         PALMAS_REG_SMPS123,
363         PALMAS_REG_SMPS3,
364         PALMAS_REG_SMPS45,
365         PALMAS_REG_SMPS457,
366         PALMAS_REG_SMPS6,
367         PALMAS_REG_SMPS7,
368         PALMAS_REG_SMPS8,
369         PALMAS_REG_SMPS9,
370         PALMAS_REG_SMPS10,
371         /* LDO regulators */
372         PALMAS_REG_LDO1,
373         PALMAS_REG_LDO2,
374         PALMAS_REG_LDO3,
375         PALMAS_REG_LDO4,
376         PALMAS_REG_LDO5,
377         PALMAS_REG_LDO6,
378         PALMAS_REG_LDO7,
379         PALMAS_REG_LDO8,
380         PALMAS_REG_LDO9,
381         PALMAS_REG_LDO10,
382         PALMAS_REG_LDO11,
383         PALMAS_REG_LDO12,
384         PALMAS_REG_LDO13,
385         PALMAS_REG_LDO14,
386         PALMAS_REG_LDOLN,
387         PALMAS_REG_LDOUSB,
388         /* External regulators */
389         PALMAS_REG_REGEN1,
390         PALMAS_REG_REGEN2,
391         PALMAS_REG_REGEN3,
392         PALMAS_REG_REGEN4,
393         PALMAS_REG_REGEN5,
394         PALMAS_REG_REGEN7,
395         PALMAS_REG_SYSEN1,
396         PALMAS_REG_SYSEN2,
397         PALMAS_REG_CHARGER_PUMP,
398         /* Total number of regulators */
399         PALMAS_NUM_REGS,
400 };
401
402 enum palmas_chip_id {
403         PALMAS,
404         TWL6035,
405         TWL6037,
406         TPS65913,
407         TPS80036,
408         PALMAS_MAX_CHIP_ID,
409 };
410
411 enum PALMAS_CLOCK32K {
412         PALMAS_CLOCK32KG,
413         PALMAS_CLOCK32KG_AUDIO,
414
415         /* Last entry */
416         PALMAS_CLOCK32K_NR,
417 };
418
419 struct palmas_clk32k_init_data {
420         int clk32k_id;
421         bool enable;
422         int sleep_control;
423 };
424
425 struct palmas_dvfs_init_data {
426         bool    en_pwm;
427         int     ext_ctrl;
428         int     reg_id;
429         bool    step_20mV;
430         int     base_voltage_uV;
431         int     max_voltage_uV;
432         bool    smps3_ctrl;
433 };
434
435 struct palmas_pmic_platform_data {
436         /* An array of pointers to regulator init data indexed by regulator
437          * ID
438          */
439         struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
440
441         /* An array of pointers to structures containing sleep mode and DVS
442          * configuration for regulators indexed by ID
443          */
444         struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
445
446         /* CL DVFS init data */
447         struct palmas_dvfs_init_data *dvfs_init_data;
448         int dvfs_init_data_size;
449
450         /* use LDO6 for vibrator control */
451         int ldo6_vibrator;
452
453         bool disable_smps10_boost_suspend;
454 };
455
456 struct palmas_usb_platform_data {
457         /* Set this if platform wishes its own vbus control */
458         int no_control_vbus;
459
460         /* Do we enable the wakeup comparator on probe */
461         int wakeup;
462 };
463
464 struct palmas_resource_platform_data {
465         int regen1_mode_sleep;
466         int regen2_mode_sleep;
467         int sysen1_mode_sleep;
468         int sysen2_mode_sleep;
469
470         /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
471         u8 nsleep_res;
472         /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
473         u8 nsleep_smps;
474         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
475         u8 nsleep_ldo1;
476         /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
477         u8 nsleep_ldo2;
478
479         /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
480         u8 enable1_res;
481         /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
482         u8 enable1_smps;
483         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
484         u8 enable1_ldo1;
485         /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
486         u8 enable1_ldo2;
487
488         /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
489         u8 enable2_res;
490         /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
491         u8 enable2_smps;
492         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
493         u8 enable2_ldo1;
494         /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
495         u8 enable2_ldo2;
496 };
497
498 struct palmas_clk_platform_data {
499         int clk32kg_mode_sleep;
500         int clk32kgaudio_mode_sleep;
501 };
502
503 struct palmas_vbus_platform_data {
504         int num_consumer_supplies;
505         struct regulator_consumer_supply *consumer_supplies;
506 };
507
508 struct palmas_bcharger_platform_data {
509         const char *battery_tz_name;
510         int max_charge_volt_mV;
511         int max_charge_current_mA;
512         int charging_term_current_mA;
513         int wdt_timeout;
514         int rtc_alarm_time;
515         int num_consumer_supplies;
516         struct regulator_consumer_supply *consumer_supplies;
517         int chg_restart_time;
518         int temperature_poll_period_secs;
519 };
520
521 struct palmas_charger_platform_data {
522         struct palmas_vbus_platform_data *vbus_pdata;
523         struct palmas_bcharger_platform_data *bcharger_pdata;
524 };
525
526
527 struct palmas_rtc_platform_data {
528         bool backup_battery_chargeable;
529         bool backup_battery_charge_high_current;
530 };
531
532 struct palmas_pm_platform_data {
533         bool use_power_off;
534         bool use_power_reset;
535 };
536
537 struct palmas_pinctrl_config {
538         const char *pin;
539         const char *function;
540         const char *prop_bias_pull;
541         const char *prop_open_drain;
542 };
543
544 struct palmas_pinctrl_platform_data {
545         struct palmas_pinctrl_config *pincfg;
546         int num_pinctrl;
547         bool dvfs1_enable;
548         bool dvfs2_enable;
549 };
550
551 struct palmas_extcon_platform_data {
552         const char *connection_name;
553         bool enable_vbus_detection;
554         bool enable_id_pin_detection;
555         /* Do we enable the wakeup comparator on probe */
556         int wakeup;
557 };
558
559 struct palmas_battery_platform_data {
560         const char *therm_zone_name;
561         /* Battery Values */
562         int battery_soldered; /* if battery detection should not be used */
563         int battery_status_interval; /* time in ms for charge status polling */
564         int *battery_temperature_chart;
565         int battery_temperature_chart_size;
566         int gpadc_retry_count;
567
568
569         /* Fuelgauge Config */
570         int current_avg_interval;
571         struct cell_config *cell_cfg;
572         int is_battery_present;
573         bool enable_ovc_alarm;
574         int ovc_period;
575         int ovc_threshold;
576 };
577
578 struct palmas_sim_platform_data {
579         unsigned dbcnt:5;
580         unsigned pwrdncnt:5;
581         unsigned pwrdnen1:1;
582         unsigned pwrdnen2:1;
583         unsigned det_polarity:1;
584         unsigned det1_pu:1;
585         unsigned det1_pd:1;
586         unsigned det2_pu:1;
587         unsigned det2_pd:1;
588 };
589
590 struct palmas_platform_data {
591         int irq_flags;
592         int gpio_base;
593         int irq_base;
594
595         /* bit value to be loaded to the POWER_CTRL register */
596         u8 power_ctrl;
597
598         struct palmas_pmic_platform_data *pmic_pdata;
599         struct palmas_gpadc_platform_data *gpadc_pdata;
600         struct palmas_usb_platform_data *usb_pdata;
601         struct palmas_resource_platform_data *resource_pdata;
602         struct palmas_clk_platform_data *clk_pdata;
603         struct palmas_rtc_platform_data *rtc_pdata;
604         struct palmas_pm_platform_data *pm_pdata;
605         struct palmas_battery_platform_data *battery_pdata;
606         struct palmas_sim_platform_data *sim_pdata;
607
608         struct palmas_clk32k_init_data  *clk32k_init_data;
609         int clk32k_init_data_size;
610         /* LDOUSB is enabled or disabled on VBUS detection */
611         bool auto_ldousb_en;
612
613         struct palmas_pinctrl_platform_data *pinctrl_pdata;
614         struct palmas_extcon_platform_data *extcon_pdata;
615         struct palmas_charger_platform_data *charger_pdata;
616
617         int watchdog_timer_initial_period;
618
619         /* Hotdie Threshold temperature */
620         unsigned long hd_threshold_temp;
621         char *tz_name;
622
623         /* Long press delay for hard shutdown */
624         int long_press_delay;
625 };
626
627 struct palmas_gpadc_result {
628         s32 raw_code;
629         s32 corrected_code;
630         s32 result;
631 };
632
633 #define PALMAS_MAX_CHANNELS 16
634
635 /* Define the palmas IRQ numbers */
636 enum palmas_irqs {
637         /* INT1 registers */
638         PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
639         PALMAS_PWRON_IRQ,
640         PALMAS_LONG_PRESS_KEY_IRQ,
641         PALMAS_RPWRON_IRQ,
642         PALMAS_PWRDOWN_IRQ,
643         PALMAS_HOTDIE_IRQ,
644         PALMAS_VSYS_MON_IRQ,
645         PALMAS_VBAT_MON_IRQ,
646         /* INT2 registers */
647         PALMAS_RTC_ALARM_IRQ,
648         PALMAS_RTC_TIMER_IRQ,
649         PALMAS_WDT_IRQ,
650         PALMAS_BATREMOVAL_IRQ,
651         PALMAS_RESET_IN_IRQ,
652         PALMAS_FBI_BB_IRQ,
653         PALMAS_SHORT_IRQ,
654         PALMAS_VAC_ACOK_IRQ,
655         /* INT3 registers */
656         PALMAS_GPADC_AUTO_0_IRQ,
657         PALMAS_GPADC_AUTO_1_IRQ,
658         PALMAS_GPADC_EOC_SW_IRQ,
659         PALMAS_GPADC_EOC_RT_IRQ,
660         PALMAS_ID_OTG_IRQ,
661         PALMAS_ID_IRQ,
662         PALMAS_VBUS_OTG_IRQ,
663         PALMAS_VBUS_IRQ,
664         /* INT4 registers */
665         PALMAS_GPIO_0_IRQ,
666         PALMAS_GPIO_1_IRQ,
667         PALMAS_GPIO_2_IRQ,
668         PALMAS_GPIO_3_IRQ,
669         PALMAS_GPIO_4_IRQ,
670         PALMAS_GPIO_5_IRQ,
671         PALMAS_GPIO_6_IRQ,
672         PALMAS_GPIO_7_IRQ,
673         /* INT5 registers */
674         PALMAS_GPIO_8_IRQ,
675         PALMAS_GPIO_9_IRQ,
676         PALMAS_GPIO_10_IRQ,
677         PALMAS_GPIO_11_IRQ,
678         PALMAS_GPIO_12_IRQ,
679         PALMAS_GPIO_13_IRQ,
680         PALMAS_GPIO_14_IRQ,
681         PALMAS_GPIO_15_IRQ,
682         /* INT6 interrupts */
683         PALMAS_CHARGER_IRQ,
684         PALMAS_SIM1_IRQ,
685         PALMAS_SIM2_IRQ,
686         /* INT7 interrupts */
687         PALMAS_BAT_TEMP_FAULT_IRQ,
688         /* Total Number IRQs */
689         PALMAS_NUM_IRQ,
690 };
691
692 struct palmas_pmic {
693         struct palmas *palmas;
694         struct device *dev;
695         struct regulator_desc desc[PALMAS_NUM_REGS];
696         struct regulator_dev *rdev[PALMAS_NUM_REGS];
697         struct mutex mutex;
698
699         int smps123;
700         int smps457;
701         bool smps10_regulator_enabled;
702         int ldo_vref0p425;
703         bool smps10_boost_disable_deferred;
704
705         int range[PALMAS_REG_SMPS10];
706         unsigned int ramp_delay[PALMAS_REG_SMPS10];
707         bool ramp_delay_support[PALMAS_NUM_REGS];
708         unsigned int current_reg_mode[PALMAS_REG_SMPS10];
709         unsigned long roof_floor[PALMAS_NUM_REGS];
710         unsigned long config_flags[PALMAS_NUM_REGS];
711 };
712
713 struct palmas_resource {
714         struct palmas *palmas;
715         struct device *dev;
716 };
717
718 enum palmas_usb_state {
719         PALMAS_USB_STATE_INIT,
720         PALMAS_USB_STATE_DISCONNECT,
721         PALMAS_USB_STATE_ID_FLOAT = PALMAS_USB_STATE_DISCONNECT,
722         PALMAS_USB_STATE_VBUS,
723         PALMAS_USB_STATE_ID_GND,
724         PALMAS_USB_STATE_ID_A,
725         PALMAS_USB_STATE_ID_B,
726         PALMAS_USB_STATE_ID_C,
727 };
728
729 struct palmas_usb {
730         struct palmas *palmas;
731         struct device *dev;
732
733         struct extcon_dev edev;
734
735         int id_otg_irq;
736         int id_irq;
737         int vbus_otg_irq;
738         int vbus_irq;
739
740         enum palmas_usb_state id_linkstat;
741         enum palmas_usb_state vbus_linkstat;
742         int wakeup;
743         bool enable_vbus_detection;
744         bool enable_id_detection;
745         struct delayed_work cable_update_wq;
746         int cable_debaunce_time;
747         int cur_cable_index;
748 };
749
750 #define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
751
752 enum usb_irq_events {
753         /* Wakeup events from INT3 */
754         PALMAS_USB_ID_WAKEPUP,
755         PALMAS_USB_VBUS_WAKEUP,
756
757         /* ID_OTG_EVENTS */
758         PALMAS_USB_ID_GND,
759         N_PALMAS_USB_ID_GND,
760         PALMAS_USB_ID_C,
761         N_PALMAS_USB_ID_C,
762         PALMAS_USB_ID_B,
763         N_PALMAS_USB_ID_B,
764         PALMAS_USB_ID_A,
765         N_PALMAS_USB_ID_A,
766         PALMAS_USB_ID_FLOAT,
767         N_PALMAS_USB_ID_FLOAT,
768
769         /* VBUS_OTG_EVENTS */
770         PALMAS_USB_VB_SESS_END,
771         N_PALMAS_USB_VB_SESS_END,
772         PALMAS_USB_VB_SESS_VLD,
773         N_PALMAS_USB_VB_SESS_VLD,
774         PALMAS_USB_VA_SESS_VLD,
775         N_PALMAS_USB_VA_SESS_VLD,
776         PALMAS_USB_VA_VBUS_VLD,
777         N_PALMAS_USB_VA_VBUS_VLD,
778         PALMAS_USB_VADP_SNS,
779         N_PALMAS_USB_VADP_SNS,
780         PALMAS_USB_VADP_PRB,
781         N_PALMAS_USB_VADP_PRB,
782         PALMAS_USB_VOTG_SESS_VLD,
783         N_PALMAS_USB_VOTG_SESS_VLD,
784 };
785
786 /* defines so we can store the mux settings */
787 #define PALMAS_GPIO_0_MUXED                                     (1 << 0)
788 #define PALMAS_GPIO_1_MUXED                                     (1 << 1)
789 #define PALMAS_GPIO_2_MUXED                                     (1 << 2)
790 #define PALMAS_GPIO_3_MUXED                                     (1 << 3)
791 #define PALMAS_GPIO_4_MUXED                                     (1 << 4)
792 #define PALMAS_GPIO_5_MUXED                                     (1 << 5)
793 #define PALMAS_GPIO_6_MUXED                                     (1 << 6)
794 #define PALMAS_GPIO_7_MUXED                                     (1 << 7)
795 #define PALMAS_GPIO_8_MUXED                                     (1 << 8)
796 #define PALMAS_GPIO_9_MUXED                                     (1 << 9)
797 #define PALMAS_GPIO_10_MUXED                                    (1 << 10)
798 #define PALMAS_GPIO_11_MUXED                                    (1 << 11)
799 #define PALMAS_GPIO_12_MUXED                                    (1 << 12)
800 #define PALMAS_GPIO_13_MUXED                                    (1 << 13)
801 #define PALMAS_GPIO_14_MUXED                                    (1 << 14)
802 #define PALMAS_GPIO_15_MUXED                                    (1 << 15)
803
804 #define PALMAS_LED1_MUXED                                       (1 << 0)
805 #define PALMAS_LED2_MUXED                                       (1 << 1)
806
807 #define PALMAS_PWM1_MUXED                                       (1 << 0)
808 #define PALMAS_PWM2_MUXED                                       (1 << 1)
809
810 /* helper macro to get correct slave number */
811 #define PALMAS_BASE_TO_SLAVE(x)         ((x >> 8) - 1)
812 #define PALMAS_BASE_TO_REG(x, y)        ((x & 0xff) + y)
813 #define RTC_SLAVE                       0
814
815 /* Base addresses of IP blocks in Palmas */
816 #define PALMAS_SMPS_DVS_BASE                                    0x20
817 #define PALMAS_RTC_BASE                                         0x100
818 #define PALMAS_VALIDITY_BASE                                    0x118
819 #define PALMAS_SMPS_BASE                                        0x120
820 #define PALMAS_LDO_BASE                                         0x150
821 #define PALMAS_DVFS_BASE                                        0x180
822 #define PALMAS_SIMCARD_BASE                                     0X19E
823 #define PALMAS_PMU_CONTROL_BASE                                 0x1A0
824 #define PALMAS_RESOURCE_BASE                                    0x1D4
825 #define PALMAS_PU_PD_OD_BASE                                    0x1F0
826 #define PALMAS_LED_BASE                                         0x200
827 #define PALMAS_INTERRUPT_BASE                                   0x210
828 #define PALMAS_FUEL_GAUGE_BASE                                  0x230
829 #define PALMAS_USB_OTG_BASE                                     0x250
830 #define PALMAS_VIBRATOR_BASE                                    0x270
831 #define PALMAS_GPIO_BASE                                        0x280
832 #define PALMAS_USB_BASE                                         0x290
833 #define PALMAS_GPADC_BASE                                       0x2C0
834 #define PALMAS_TRIM_GPADC_BASE                                  0x3CD
835 #define PALMAS_PAGE3_BASE                                       0x300
836 #define PALMAS_CHARGER_BASE                                     0x400
837
838 #define PALMAS_CHARGE_PUMP_CTRL                                 0x7C
839 /* Bit definitions for CHARGE_PUMP_CTRL */
840 #define  PALMAS_PALMAS_CHARGE_PUMP_CTRL_STATUS                  0x10
841 #define PALMAS_CHARGE_PUMP_CTRL_STATUS_SHIFT                    4
842 #define PALMAS_CHARGE_PUMP_CTRL_MODE_SLEEP                      0x04
843 #define PALMAS_CHARGE_PUMP_CTRL_MODE_SLEEP_SHIFT                2
844 #define PALMAS_CHARGE_PUMP_CTRL_MODE_ACTIVE                     0x01
845 #define PALMAS_CHARGE_PUMP_CTRL_MODE_ACTIVE_SHIFT               0
846
847 /* Registers for function RTC */
848 #define PALMAS_SECONDS_REG                                      0x0
849 #define PALMAS_MINUTES_REG                                      0x1
850 #define PALMAS_HOURS_REG                                        0x2
851 #define PALMAS_DAYS_REG                                         0x3
852 #define PALMAS_MONTHS_REG                                       0x4
853 #define PALMAS_YEARS_REG                                        0x5
854 #define PALMAS_WEEKS_REG                                        0x6
855 #define PALMAS_ALARM_SECONDS_REG                                0x8
856 #define PALMAS_ALARM_MINUTES_REG                                0x9
857 #define PALMAS_ALARM_HOURS_REG                                  0xA
858 #define PALMAS_ALARM_DAYS_REG                                   0xB
859 #define PALMAS_ALARM_MONTHS_REG                                 0xC
860 #define PALMAS_ALARM_YEARS_REG                                  0xD
861 #define PALMAS_RTC_CTRL_REG                                     0x10
862 #define PALMAS_RTC_STATUS_REG                                   0x11
863 #define PALMAS_RTC_INTERRUPTS_REG                               0x12
864 #define PALMAS_RTC_COMP_LSB_REG                                 0x13
865 #define PALMAS_RTC_COMP_MSB_REG                                 0x14
866 #define PALMAS_RTC_RES_PROG_REG                                 0x15
867 #define PALMAS_RTC_RESET_STATUS_REG                             0x16
868
869 /* Bit definitions for SECONDS_REG */
870 #define PALMAS_SECONDS_REG_SEC1_MASK                            0x70
871 #define PALMAS_SECONDS_REG_SEC1_SHIFT                           4
872 #define PALMAS_SECONDS_REG_SEC0_MASK                            0x0f
873 #define PALMAS_SECONDS_REG_SEC0_SHIFT                           0
874
875 /* Bit definitions for MINUTES_REG */
876 #define PALMAS_MINUTES_REG_MIN1_MASK                            0x70
877 #define PALMAS_MINUTES_REG_MIN1_SHIFT                           4
878 #define PALMAS_MINUTES_REG_MIN0_MASK                            0x0f
879 #define PALMAS_MINUTES_REG_MIN0_SHIFT                           0
880
881 /* Bit definitions for HOURS_REG */
882 #define PALMAS_HOURS_REG_PM_NAM                                 0x80
883 #define PALMAS_HOURS_REG_PM_NAM_SHIFT                           7
884 #define PALMAS_HOURS_REG_HOUR1_MASK                             0x30
885 #define PALMAS_HOURS_REG_HOUR1_SHIFT                            4
886 #define PALMAS_HOURS_REG_HOUR0_MASK                             0x0f
887 #define PALMAS_HOURS_REG_HOUR0_SHIFT                            0
888
889 /* Bit definitions for DAYS_REG */
890 #define PALMAS_DAYS_REG_DAY1_MASK                               0x30
891 #define PALMAS_DAYS_REG_DAY1_SHIFT                              4
892 #define PALMAS_DAYS_REG_DAY0_MASK                               0x0f
893 #define PALMAS_DAYS_REG_DAY0_SHIFT                              0
894
895 /* Bit definitions for MONTHS_REG */
896 #define PALMAS_MONTHS_REG_MONTH1                                0x10
897 #define PALMAS_MONTHS_REG_MONTH1_SHIFT                          4
898 #define PALMAS_MONTHS_REG_MONTH0_MASK                           0x0f
899 #define PALMAS_MONTHS_REG_MONTH0_SHIFT                          0
900
901 /* Bit definitions for YEARS_REG */
902 #define PALMAS_YEARS_REG_YEAR1_MASK                             0xf0
903 #define PALMAS_YEARS_REG_YEAR1_SHIFT                            4
904 #define PALMAS_YEARS_REG_YEAR0_MASK                             0x0f
905 #define PALMAS_YEARS_REG_YEAR0_SHIFT                            0
906
907 /* Bit definitions for WEEKS_REG */
908 #define PALMAS_WEEKS_REG_WEEK_MASK                              0x07
909 #define PALMAS_WEEKS_REG_WEEK_SHIFT                             0
910
911 /* Bit definitions for ALARM_SECONDS_REG */
912 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK                0x70
913 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT               4
914 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK                0x0f
915 #define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT               0
916
917 /* Bit definitions for ALARM_MINUTES_REG */
918 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK                0x70
919 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT               4
920 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK                0x0f
921 #define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT               0
922
923 /* Bit definitions for ALARM_HOURS_REG */
924 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM                     0x80
925 #define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT               7
926 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK                 0x30
927 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT                4
928 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK                 0x0f
929 #define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT                0
930
931 /* Bit definitions for ALARM_DAYS_REG */
932 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK                   0x30
933 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT                  4
934 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK                   0x0f
935 #define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT                  0
936
937 /* Bit definitions for ALARM_MONTHS_REG */
938 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1                    0x10
939 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT              4
940 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK               0x0f
941 #define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT              0
942
943 /* Bit definitions for ALARM_YEARS_REG */
944 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK                 0xf0
945 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT                4
946 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK                 0x0f
947 #define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT                0
948
949 /* Bit definitions for RTC_CTRL_REG */
950 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT                           0x80
951 #define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT                     7
952 #define PALMAS_RTC_CTRL_REG_GET_TIME                            0x40
953 #define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT                      6
954 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER                      0x20
955 #define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT                5
956 #define PALMAS_RTC_CTRL_REG_TEST_MODE                           0x10
957 #define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT                     4
958 #define PALMAS_RTC_CTRL_REG_MODE_12_24                          0x08
959 #define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT                    3
960 #define PALMAS_RTC_CTRL_REG_AUTO_COMP                           0x04
961 #define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT                     2
962 #define PALMAS_RTC_CTRL_REG_ROUND_30S                           0x02
963 #define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT                     1
964 #define PALMAS_RTC_CTRL_REG_STOP_RTC                            0x01
965 #define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT                      0
966
967 /* Bit definitions for RTC_STATUS_REG */
968 #define PALMAS_RTC_STATUS_REG_POWER_UP                          0x80
969 #define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT                    7
970 #define PALMAS_RTC_STATUS_REG_ALARM                             0x40
971 #define PALMAS_RTC_STATUS_REG_ALARM_SHIFT                       6
972 #define PALMAS_RTC_STATUS_REG_EVENT_1D                          0x20
973 #define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT                    5
974 #define PALMAS_RTC_STATUS_REG_EVENT_1H                          0x10
975 #define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT                    4
976 #define PALMAS_RTC_STATUS_REG_EVENT_1M                          0x08
977 #define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT                    3
978 #define PALMAS_RTC_STATUS_REG_EVENT_1S                          0x04
979 #define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT                    2
980 #define PALMAS_RTC_STATUS_REG_RUN                               0x02
981 #define PALMAS_RTC_STATUS_REG_RUN_SHIFT                         1
982
983 /* Bit definitions for RTC_INTERRUPTS_REG */
984 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN              0x10
985 #define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT        4
986 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM                      0x08
987 #define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT                3
988 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER                      0x04
989 #define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT                2
990 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK                    0x03
991 #define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT                   0
992
993 /* Bit definitions for RTC_COMP_LSB_REG */
994 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK               0xff
995 #define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT              0
996
997 /* Bit definitions for RTC_COMP_MSB_REG */
998 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK               0xff
999 #define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT              0
1000
1001 /* Bit definitions for RTC_RES_PROG_REG */
1002 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK                0x3f
1003 #define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT               0
1004
1005 /* Bit definitions for RTC_RESET_STATUS_REG */
1006 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS                0x01
1007 #define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT          0
1008
1009 /* Registers for function BACKUP */
1010 #define PALMAS_BACKUP0                                          0x0
1011 #define PALMAS_BACKUP1                                          0x1
1012 #define PALMAS_BACKUP2                                          0x2
1013 #define PALMAS_BACKUP3                                          0x3
1014 #define PALMAS_BACKUP4                                          0x4
1015 #define PALMAS_BACKUP5                                          0x5
1016 #define PALMAS_BACKUP6                                          0x6
1017 #define PALMAS_BACKUP7                                          0x7
1018
1019 /* Bit definitions for BACKUP0 */
1020 #define PALMAS_BACKUP0_BACKUP_MASK                              0xff
1021 #define PALMAS_BACKUP0_BACKUP_SHIFT                             0
1022
1023 /* Bit definitions for BACKUP1 */
1024 #define PALMAS_BACKUP1_BACKUP_MASK                              0xff
1025 #define PALMAS_BACKUP1_BACKUP_SHIFT                             0
1026
1027 /* Bit definitions for BACKUP2 */
1028 #define PALMAS_BACKUP2_BACKUP_MASK                              0xff
1029 #define PALMAS_BACKUP2_BACKUP_SHIFT                             0
1030
1031 /* Bit definitions for BACKUP3 */
1032 #define PALMAS_BACKUP3_BACKUP_MASK                              0xff
1033 #define PALMAS_BACKUP3_BACKUP_SHIFT                             0
1034
1035 /* Bit definitions for BACKUP4 */
1036 #define PALMAS_BACKUP4_BACKUP_MASK                              0xff
1037 #define PALMAS_BACKUP4_BACKUP_SHIFT                             0
1038
1039 /* Bit definitions for BACKUP5 */
1040 #define PALMAS_BACKUP5_BACKUP_MASK                              0xff
1041 #define PALMAS_BACKUP5_BACKUP_SHIFT                             0
1042
1043 /* Bit definitions for BACKUP6 */
1044 #define PALMAS_BACKUP6_BACKUP_MASK                              0xff
1045 #define PALMAS_BACKUP6_BACKUP_SHIFT                             0
1046
1047 /* Bit definitions for BACKUP7 */
1048 #define PALMAS_BACKUP7_BACKUP_MASK                              0xff
1049 #define PALMAS_BACKUP7_BACKUP_SHIFT                             0
1050
1051 /* Registers for function SMPS */
1052 #define PALMAS_SMPS12_CTRL                                      0x0
1053 #define PALMAS_SMPS12_TSTEP                                     0x1
1054 #define PALMAS_SMPS12_FORCE                                     0x2
1055 #define PALMAS_SMPS12_VOLTAGE                                   0x3
1056 #define PALMAS_SMPS3_CTRL                                       0x4
1057 #define PALMAS_SMPS3_TSTEP                                      0x5
1058 #define PALMAS_SMPS3_FORCE                                      0x6
1059 #define PALMAS_SMPS3_VOLTAGE                                    0x7
1060 #define PALMAS_SMPS45_CTRL                                      0x8
1061 #define PALMAS_SMPS45_TSTEP                                     0x9
1062 #define PALMAS_SMPS45_FORCE                                     0xA
1063 #define PALMAS_SMPS45_VOLTAGE                                   0xB
1064 #define PALMAS_SMPS6_CTRL                                       0xC
1065 #define PALMAS_SMPS6_TSTEP                                      0xD
1066 #define PALMAS_SMPS6_FORCE                                      0xE
1067 #define PALMAS_SMPS6_VOLTAGE                                    0xF
1068 #define PALMAS_SMPS7_CTRL                                       0x10
1069 #define PALMAS_SMPS7_VOLTAGE                                    0x13
1070 #define PALMAS_SMPS8_CTRL                                       0x14
1071 #define PALMAS_SMPS8_TSTEP                                      0x15
1072 #define PALMAS_SMPS8_FORCE                                      0x16
1073 #define PALMAS_SMPS8_VOLTAGE                                    0x17
1074 #define PALMAS_SMPS9_CTRL                                       0x18
1075 #define PALMAS_SMPS9_VOLTAGE                                    0x1B
1076 #define PALMAS_SMPS10_CTRL                                      0x1C
1077 #define PALMAS_SMPS10_STATUS                                    0x1F
1078 #define PALMAS_SMPS_CTRL                                        0x24
1079 #define PALMAS_SMPS_PD_CTRL                                     0x25
1080 #define PALMAS_SMPS_DITHER_EN                                   0x26
1081 #define PALMAS_SMPS_THERMAL_EN                                  0x27
1082 #define PALMAS_SMPS_THERMAL_STATUS                              0x28
1083 #define PALMAS_SMPS_SHORT_STATUS                                0x29
1084 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN                   0x2A
1085 #define PALMAS_SMPS_POWERGOOD_MASK1                             0x2B
1086 #define PALMAS_SMPS_POWERGOOD_MASK2                             0x2C
1087
1088 /* Bit definitions for SMPS12_CTRL */
1089 #define PALMAS_SMPS12_CTRL_WR_S                                 0x80
1090 #define PALMAS_SMPS12_CTRL_WR_S_SHIFT                           7
1091 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN                        0x40
1092 #define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT                  6
1093 #define PALMAS_SMPS12_CTRL_STATUS_MASK                          0x30
1094 #define PALMAS_SMPS12_CTRL_STATUS_SHIFT                         4
1095 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK                      0x0c
1096 #define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT                     2
1097 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK                     0x03
1098 #define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT                    0
1099
1100 /* Bit definitions for SMPS12_TSTEP */
1101 #define PALMAS_SMPS12_TSTEP_TSTEP_MASK                          0x03
1102 #define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT                         0
1103
1104 /* Bit definitions for SMPS12_FORCE */
1105 #define PALMAS_SMPS12_FORCE_CMD                                 0x80
1106 #define PALMAS_SMPS12_FORCE_CMD_SHIFT                           7
1107 #define PALMAS_SMPS12_FORCE_VSEL_MASK                           0x7f
1108 #define PALMAS_SMPS12_FORCE_VSEL_SHIFT                          0
1109
1110 /* Bit definitions for SMPS12_VOLTAGE */
1111 #define PALMAS_SMPS12_VOLTAGE_RANGE                             0x80
1112 #define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT                       7
1113 #define PALMAS_SMPS12_VOLTAGE_VSEL_MASK                         0x7f
1114 #define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT                        0
1115
1116 /* Bit definitions for SMPS3_CTRL */
1117 #define PALMAS_SMPS3_CTRL_WR_S                                  0x80
1118 #define PALMAS_SMPS3_CTRL_WR_S_SHIFT                            7
1119 #define PALMAS_SMPS3_CTRL_STATUS_MASK                           0x30
1120 #define PALMAS_SMPS3_CTRL_STATUS_SHIFT                          4
1121 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK                       0x0c
1122 #define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT                      2
1123 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK                      0x03
1124 #define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT                     0
1125
1126 /* Bit definitions for SMPS3_VOLTAGE */
1127 #define PALMAS_SMPS3_VOLTAGE_RANGE                              0x80
1128 #define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT                        7
1129 #define PALMAS_SMPS3_VOLTAGE_VSEL_MASK                          0x7f
1130 #define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT                         0
1131
1132 /* Bit definitions for SMPS45_CTRL */
1133 #define PALMAS_SMPS45_CTRL_WR_S                                 0x80
1134 #define PALMAS_SMPS45_CTRL_WR_S_SHIFT                           7
1135 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN                        0x40
1136 #define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT                  6
1137 #define PALMAS_SMPS45_CTRL_STATUS_MASK                          0x30
1138 #define PALMAS_SMPS45_CTRL_STATUS_SHIFT                         4
1139 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK                      0x0c
1140 #define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT                     2
1141 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK                     0x03
1142 #define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT                    0
1143
1144 /* Bit definitions for SMPS45_TSTEP */
1145 #define PALMAS_SMPS45_TSTEP_TSTEP_MASK                          0x03
1146 #define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT                         0
1147
1148 /* Bit definitions for SMPS45_FORCE */
1149 #define PALMAS_SMPS45_FORCE_CMD                                 0x80
1150 #define PALMAS_SMPS45_FORCE_CMD_SHIFT                           7
1151 #define PALMAS_SMPS45_FORCE_VSEL_MASK                           0x7f
1152 #define PALMAS_SMPS45_FORCE_VSEL_SHIFT                          0
1153
1154 /* Bit definitions for SMPS45_VOLTAGE */
1155 #define PALMAS_SMPS45_VOLTAGE_RANGE                             0x80
1156 #define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT                       7
1157 #define PALMAS_SMPS45_VOLTAGE_VSEL_MASK                         0x7f
1158 #define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT                        0
1159
1160 /* Bit definitions for SMPS6_CTRL */
1161 #define PALMAS_SMPS6_CTRL_WR_S                                  0x80
1162 #define PALMAS_SMPS6_CTRL_WR_S_SHIFT                            7
1163 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN                         0x40
1164 #define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT                   6
1165 #define PALMAS_SMPS6_CTRL_STATUS_MASK                           0x30
1166 #define PALMAS_SMPS6_CTRL_STATUS_SHIFT                          4
1167 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK                       0x0c
1168 #define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT                      2
1169 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK                      0x03
1170 #define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT                     0
1171
1172 /* Bit definitions for SMPS6_TSTEP */
1173 #define PALMAS_SMPS6_TSTEP_TSTEP_MASK                           0x03
1174 #define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT                          0
1175
1176 /* Bit definitions for SMPS6_FORCE */
1177 #define PALMAS_SMPS6_FORCE_CMD                                  0x80
1178 #define PALMAS_SMPS6_FORCE_CMD_SHIFT                            7
1179 #define PALMAS_SMPS6_FORCE_VSEL_MASK                            0x7f
1180 #define PALMAS_SMPS6_FORCE_VSEL_SHIFT                           0
1181
1182 /* Bit definitions for SMPS6_VOLTAGE */
1183 #define PALMAS_SMPS6_VOLTAGE_RANGE                              0x80
1184 #define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT                        7
1185 #define PALMAS_SMPS6_VOLTAGE_VSEL_MASK                          0x7f
1186 #define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT                         0
1187
1188 /* Bit definitions for SMPS7_CTRL */
1189 #define PALMAS_SMPS7_CTRL_WR_S                                  0x80
1190 #define PALMAS_SMPS7_CTRL_WR_S_SHIFT                            7
1191 #define PALMAS_SMPS7_CTRL_STATUS_MASK                           0x30
1192 #define PALMAS_SMPS7_CTRL_STATUS_SHIFT                          4
1193 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK                       0x0c
1194 #define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT                      2
1195 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK                      0x03
1196 #define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT                     0
1197
1198 /* Bit definitions for SMPS7_VOLTAGE */
1199 #define PALMAS_SMPS7_VOLTAGE_RANGE                              0x80
1200 #define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT                        7
1201 #define PALMAS_SMPS7_VOLTAGE_VSEL_MASK                          0x7f
1202 #define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT                         0
1203
1204 /* Bit definitions for SMPS8_CTRL */
1205 #define PALMAS_SMPS8_CTRL_WR_S                                  0x80
1206 #define PALMAS_SMPS8_CTRL_WR_S_SHIFT                            7
1207 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN                         0x40
1208 #define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT                   6
1209 #define PALMAS_SMPS8_CTRL_STATUS_MASK                           0x30
1210 #define PALMAS_SMPS8_CTRL_STATUS_SHIFT                          4
1211 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK                       0x0c
1212 #define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT                      2
1213 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK                      0x03
1214 #define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT                     0
1215
1216 /* Bit definitions for SMPS8_TSTEP */
1217 #define PALMAS_SMPS8_TSTEP_TSTEP_MASK                           0x03
1218 #define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT                          0
1219
1220 /* Bit definitions for SMPS8_FORCE */
1221 #define PALMAS_SMPS8_FORCE_CMD                                  0x80
1222 #define PALMAS_SMPS8_FORCE_CMD_SHIFT                            7
1223 #define PALMAS_SMPS8_FORCE_VSEL_MASK                            0x7f
1224 #define PALMAS_SMPS8_FORCE_VSEL_SHIFT                           0
1225
1226 /* Bit definitions for SMPS8_VOLTAGE */
1227 #define PALMAS_SMPS8_VOLTAGE_RANGE                              0x80
1228 #define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT                        7
1229 #define PALMAS_SMPS8_VOLTAGE_VSEL_MASK                          0x7f
1230 #define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT                         0
1231
1232 /* Bit definitions for SMPS9_CTRL */
1233 #define PALMAS_SMPS9_CTRL_WR_S                                  0x80
1234 #define PALMAS_SMPS9_CTRL_WR_S_SHIFT                            7
1235 #define PALMAS_SMPS9_CTRL_STATUS_MASK                           0x30
1236 #define PALMAS_SMPS9_CTRL_STATUS_SHIFT                          4
1237 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK                       0x0c
1238 #define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT                      2
1239 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK                      0x03
1240 #define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT                     0
1241
1242 /* Bit definitions for SMPS9_VOLTAGE */
1243 #define PALMAS_SMPS9_VOLTAGE_RANGE                              0x80
1244 #define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT                        7
1245 #define PALMAS_SMPS9_VOLTAGE_VSEL_MASK                          0x7f
1246 #define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT                         0
1247
1248 /* Bit definitions for SMPS10_CTRL */
1249 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK                      0xf0
1250 #define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT                     4
1251 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK                     0x0f
1252 #define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT                    0
1253
1254 /* Bit definitions for SMPS10_STATUS */
1255 #define PALMAS_SMPS10_STATUS_STATUS_MASK                        0x0f
1256 #define PALMAS_SMPS10_STATUS_STATUS_SHIFT                       0
1257
1258 /* Bit definitions for SMPS_CTRL */
1259 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN                      0x20
1260 #define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT                5
1261 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN                      0x10
1262 #define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT                4
1263 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK                 0x0c
1264 #define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT                2
1265 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK                0x03
1266 #define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT               0
1267
1268 /* Bit definitions for SMPS_PD_CTRL */
1269 #define PALMAS_SMPS_PD_CTRL_SMPS9                               0x40
1270 #define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT                         6
1271 #define PALMAS_SMPS_PD_CTRL_SMPS8                               0x20
1272 #define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT                         5
1273 #define PALMAS_SMPS_PD_CTRL_SMPS7                               0x10
1274 #define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT                         4
1275 #define PALMAS_SMPS_PD_CTRL_SMPS6                               0x08
1276 #define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT                         3
1277 #define PALMAS_SMPS_PD_CTRL_SMPS45                              0x04
1278 #define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT                        2
1279 #define PALMAS_SMPS_PD_CTRL_SMPS3                               0x02
1280 #define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT                         1
1281 #define PALMAS_SMPS_PD_CTRL_SMPS12                              0x01
1282 #define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT                        0
1283
1284 /* Bit definitions for SMPS_THERMAL_EN */
1285 #define PALMAS_SMPS_THERMAL_EN_SMPS9                            0x40
1286 #define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT                      6
1287 #define PALMAS_SMPS_THERMAL_EN_SMPS8                            0x20
1288 #define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT                      5
1289 #define PALMAS_SMPS_THERMAL_EN_SMPS6                            0x08
1290 #define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT                      3
1291 #define PALMAS_SMPS_THERMAL_EN_SMPS457                          0x04
1292 #define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT                    2
1293 #define PALMAS_SMPS_THERMAL_EN_SMPS123                          0x01
1294 #define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT                    0
1295
1296 /* Bit definitions for SMPS_THERMAL_STATUS */
1297 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9                        0x40
1298 #define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT                  6
1299 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8                        0x20
1300 #define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT                  5
1301 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6                        0x08
1302 #define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT                  3
1303 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457                      0x04
1304 #define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT                2
1305 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123                      0x01
1306 #define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT                0
1307
1308 /* Bit definitions for SMPS_SHORT_STATUS */
1309 #define PALMAS_SMPS_SHORT_STATUS_SMPS10                         0x80
1310 #define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT                   7
1311 #define PALMAS_SMPS_SHORT_STATUS_SMPS9                          0x40
1312 #define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT                    6
1313 #define PALMAS_SMPS_SHORT_STATUS_SMPS8                          0x20
1314 #define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT                    5
1315 #define PALMAS_SMPS_SHORT_STATUS_SMPS7                          0x10
1316 #define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT                    4
1317 #define PALMAS_SMPS_SHORT_STATUS_SMPS6                          0x08
1318 #define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT                    3
1319 #define PALMAS_SMPS_SHORT_STATUS_SMPS45                         0x04
1320 #define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT                   2
1321 #define PALMAS_SMPS_SHORT_STATUS_SMPS3                          0x02
1322 #define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT                    1
1323 #define PALMAS_SMPS_SHORT_STATUS_SMPS12                         0x01
1324 #define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT                   0
1325
1326 /* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1327 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9             0x40
1328 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT       6
1329 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8             0x20
1330 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT       5
1331 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7             0x10
1332 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT       4
1333 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6             0x08
1334 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT       3
1335 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45            0x04
1336 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT      2
1337 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3             0x02
1338 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT       1
1339 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12            0x01
1340 #define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT      0
1341
1342 /* Bit definitions for SMPS_POWERGOOD_MASK1 */
1343 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10                      0x80
1344 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT                7
1345 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9                       0x40
1346 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT                 6
1347 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8                       0x20
1348 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT                 5
1349 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7                       0x10
1350 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT                 4
1351 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6                       0x08
1352 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT                 3
1353 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45                      0x04
1354 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT                2
1355 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3                       0x02
1356 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT                 1
1357 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12                      0x01
1358 #define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT                0
1359
1360 /* Bit definitions for SMPS_POWERGOOD_MASK2 */
1361 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT       0x80
1362 #define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 7
1363 #define PALMAS_SMPS_POWERGOOD_MASK2_OVC_ALARM                   0x10
1364 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7                      0x04
1365 #define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT                2
1366 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS                        0x02
1367 #define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT                  1
1368 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK                        0x01
1369 #define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT                  0
1370
1371 /* Registers for function LDO */
1372 #define PALMAS_LDO1_CTRL                                        0x0
1373 #define PALMAS_LDO1_VOLTAGE                                     0x1
1374 #define PALMAS_LDO2_CTRL                                        0x2
1375 #define PALMAS_LDO2_VOLTAGE                                     0x3
1376 #define PALMAS_LDO3_CTRL                                        0x4
1377 #define PALMAS_LDO3_VOLTAGE                                     0x5
1378 #define PALMAS_LDO4_CTRL                                        0x6
1379 #define PALMAS_LDO4_VOLTAGE                                     0x7
1380 #define PALMAS_LDO5_CTRL                                        0x8
1381 #define PALMAS_LDO5_VOLTAGE                                     0x9
1382 #define PALMAS_LDO6_CTRL                                        0xA
1383 #define PALMAS_LDO6_VOLTAGE                                     0xB
1384 #define PALMAS_LDO7_CTRL                                        0xC
1385 #define PALMAS_LDO7_VOLTAGE                                     0xD
1386 #define PALMAS_LDO8_CTRL                                        0xE
1387 #define PALMAS_LDO8_VOLTAGE                                     0xF
1388 #define PALMAS_LDO9_CTRL                                        0x10
1389 #define PALMAS_LDO9_VOLTAGE                                     0x11
1390 #define PALMAS_LDOLN_CTRL                                       0x12
1391 #define PALMAS_LDOLN_VOLTAGE                                    0x13
1392 #define PALMAS_LDOUSB_CTRL                                      0x14
1393 #define PALMAS_LDOUSB_VOLTAGE                                   0x15
1394 #define PALMAS_LDO10_CTRL                                       0x16
1395 #define PALMAS_LDO10_VOLTAGE                                    0x17
1396 #define PALMAS_LDO11_CTRL                                       0x18
1397 #define PALMAS_LDO11_VOLTAGE                                    0x19
1398 #define PALMAS_LDO12_CTRL                                       0x1F
1399 #define PALMAS_LDO12_VOLTAGE                                    0x20
1400 #define PALMAS_LDO13_CTRL                                       0x21
1401 #define PALMAS_LDO13_VOLTAGE                                    0x22
1402 #define PALMAS_LDO14_CTRL                                       0x23
1403 #define PALMAS_LDO14_VOLTAGE                                    0x24
1404 #define PALMAS_LDO_CTRL                                         0x1A
1405 #define PALMAS_LDO_PD_CTRL1                                     0x1B
1406 #define PALMAS_LDO_PD_CTRL2                                     0x1C
1407 #define PALMAS_LDO_SHORT_STATUS1                                0x1D
1408 #define PALMAS_LDO_SHORT_STATUS2                                0x1E
1409
1410 /* Bit definitions for LDO1_CTRL */
1411 #define PALMAS_LDO1_CTRL_WR_S                                   0x80
1412 #define PALMAS_LDO1_CTRL_WR_S_SHIFT                             7
1413 #define PALMAS_LDO1_CTRL_LDO_BYPASS_EN                          0x40
1414 #define PALMAS_LDO1_CTRL_LDO_BYPASS_EN_SHIFT                    6
1415 #define PALMAS_LDO1_CTRL_STATUS                                 0x10
1416 #define PALMAS_LDO1_CTRL_STATUS_SHIFT                           4
1417 #define PALMAS_LDO1_CTRL_MODE_SLEEP                             0x04
1418 #define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT                       2
1419 #define PALMAS_LDO1_CTRL_MODE_ACTIVE                            0x01
1420 #define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT                      0
1421
1422 /* Bit definitions for LDO1_VOLTAGE */
1423 #define PALMAS_LDO1_VOLTAGE_VSEL_MASK                           0x3f
1424 #define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT                          0
1425
1426 /* Bit definitions for LDO2_CTRL */
1427 #define PALMAS_LDO2_CTRL_WR_S                                   0x80
1428 #define PALMAS_LDO2_CTRL_WR_S_SHIFT                             7
1429 #define PALMAS_LDO2_CTRL_LDO_BYPASS_EN                          0x40
1430 #define PALMAS_LDO2_CTRL_LDO_BYPASS_EN_SHIFT                    6
1431 #define PALMAS_LDO2_CTRL_STATUS                                 0x10
1432 #define PALMAS_LDO2_CTRL_STATUS_SHIFT                           4
1433 #define PALMAS_LDO2_CTRL_MODE_SLEEP                             0x04
1434 #define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT                       2
1435 #define PALMAS_LDO2_CTRL_MODE_ACTIVE                            0x01
1436 #define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT                      0
1437
1438 /* Bit definitions for LDO2_VOLTAGE */
1439 #define PALMAS_LDO2_VOLTAGE_VSEL_MASK                           0x3f
1440 #define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT                          0
1441
1442 /* Bit definitions for LDO3_CTRL */
1443 #define PALMAS_LDO3_CTRL_WR_S                                   0x80
1444 #define PALMAS_LDO3_CTRL_WR_S_SHIFT                             7
1445 #define PALMAS_LDO3_CTRL_STATUS                                 0x10
1446 #define PALMAS_LDO3_CTRL_STATUS_SHIFT                           4
1447 #define PALMAS_LDO3_CTRL_MODE_SLEEP                             0x04
1448 #define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT                       2
1449 #define PALMAS_LDO3_CTRL_MODE_ACTIVE                            0x01
1450 #define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT                      0
1451
1452 /* Bit definitions for LDO3_VOLTAGE */
1453 #define PALMAS_LDO3_VOLTAGE_VSEL_MASK                           0x3f
1454 #define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT                          0
1455
1456 /* Bit definitions for LDO4_CTRL */
1457 #define PALMAS_LDO4_CTRL_WR_S                                   0x80
1458 #define PALMAS_LDO4_CTRL_WR_S_SHIFT                             7
1459 #define PALMAS_LDO4_CTRL_LDO_BYPASS_EN                          0x40
1460 #define PALMAS_LDO4_CTRL_LDO_BYPASS_EN_SHIFT                    6
1461 #define PALMAS_LDO4_CTRL_STATUS                                 0x10
1462 #define PALMAS_LDO4_CTRL_STATUS_SHIFT                           4
1463 #define PALMAS_LDO4_CTRL_MODE_SLEEP                             0x04
1464 #define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT                       2
1465 #define PALMAS_LDO4_CTRL_MODE_ACTIVE                            0x01
1466 #define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT                      0
1467
1468 /* Bit definitions for LDO4_VOLTAGE */
1469 #define PALMAS_LDO4_VOLTAGE_VSEL_MASK                           0x3f
1470 #define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT                          0
1471
1472 /* Bit definitions for LDO5_CTRL */
1473 #define PALMAS_LDO5_CTRL_WR_S                                   0x80
1474 #define PALMAS_LDO5_CTRL_WR_S_SHIFT                             7
1475 #define PALMAS_LDO5_CTRL_STATUS                                 0x10
1476 #define PALMAS_LDO5_CTRL_STATUS_SHIFT                           4
1477 #define PALMAS_LDO5_CTRL_MODE_SLEEP                             0x04
1478 #define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT                       2
1479 #define PALMAS_LDO5_CTRL_MODE_ACTIVE                            0x01
1480 #define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT                      0
1481
1482 /* Bit definitions for LDO5_VOLTAGE */
1483 #define PALMAS_LDO5_VOLTAGE_VSEL_MASK                           0x3f
1484 #define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT                          0
1485
1486 /* Bit definitions for LDO6_CTRL */
1487 #define PALMAS_LDO6_CTRL_WR_S                                   0x80
1488 #define PALMAS_LDO6_CTRL_WR_S_SHIFT                             7
1489 #define PALMAS_LDO6_CTRL_LDO_BYPASS_EN                          0x40
1490 #define PALMAS_LDO6_CTRL_LDO_BYPASS_EN_SHIFT                    6
1491 #define PALMAS_LDO6_CTRL_LDO_VIB_EN                             0x40
1492 #define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT                       6
1493 #define PALMAS_LDO6_CTRL_STATUS                                 0x10
1494 #define PALMAS_LDO6_CTRL_STATUS_SHIFT                           4
1495 #define PALMAS_LDO6_CTRL_MODE_SLEEP                             0x04
1496 #define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT                       2
1497 #define PALMAS_LDO6_CTRL_MODE_ACTIVE                            0x01
1498 #define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT                      0
1499
1500 /* Bit definitions for LDO6_VOLTAGE */
1501 #define PALMAS_LDO6_VOLTAGE_VSEL_MASK                           0x3f
1502 #define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT                          0
1503
1504 /* Bit definitions for LDO7_CTRL */
1505 #define PALMAS_LDO7_CTRL_WR_S                                   0x80
1506 #define PALMAS_LDO7_CTRL_WR_S_SHIFT                             7
1507 #define PALMAS_LDO7_CTRL_STATUS                                 0x10
1508 #define PALMAS_LDO7_CTRL_STATUS_SHIFT                           4
1509 #define PALMAS_LDO7_CTRL_MODE_SLEEP                             0x04
1510 #define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT                       2
1511 #define PALMAS_LDO7_CTRL_MODE_ACTIVE                            0x01
1512 #define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT                      0
1513
1514 /* Bit definitions for LDO7_VOLTAGE */
1515 #define PALMAS_LDO7_VOLTAGE_VSEL_MASK                           0x3f
1516 #define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT                          0
1517
1518 /* Bit definitions for LDO8_CTRL */
1519 #define PALMAS_LDO8_CTRL_WR_S                                   0x80
1520 #define PALMAS_LDO8_CTRL_WR_S_SHIFT                             7
1521 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN                        0x40
1522 #define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT                  6
1523 #define PALMAS_LDO8_CTRL_STATUS                                 0x10
1524 #define PALMAS_LDO8_CTRL_STATUS_SHIFT                           4
1525 #define PALMAS_LDO8_CTRL_MODE_SLEEP                             0x04
1526 #define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT                       2
1527 #define PALMAS_LDO8_CTRL_MODE_ACTIVE                            0x01
1528 #define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT                      0
1529
1530 /* Bit definitions for LDO8_VOLTAGE */
1531 #define PALMAS_LDO8_VOLTAGE_VSEL_MASK                           0x3f
1532 #define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT                          0
1533
1534 /* Bit definitions for LDO9_CTRL */
1535 #define PALMAS_LDO9_CTRL_WR_S                                   0x80
1536 #define PALMAS_LDO9_CTRL_WR_S_SHIFT                             7
1537 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN                          0x40
1538 #define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT                    6
1539 #define PALMAS_LDO9_CTRL_STATUS                                 0x10
1540 #define PALMAS_LDO9_CTRL_STATUS_SHIFT                           4
1541 #define PALMAS_LDO9_CTRL_MODE_SLEEP                             0x04
1542 #define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT                       2
1543 #define PALMAS_LDO9_CTRL_MODE_ACTIVE                            0x01
1544 #define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT                      0
1545
1546 /* Bit definitions for LDO9_VOLTAGE */
1547 #define PALMAS_LDO9_VOLTAGE_VSEL_MASK                           0x3f
1548 #define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT                          0
1549
1550 /* Bit definitions for LDO10_CTRL */
1551 #define PALMAS_LDO10_CTRL_WR_S                                  0x80
1552 #define PALMAS_LDO10_CTRL_WR_S_SHIFT                            7
1553 #define PALMAS_LDO10_CTRL_LDO_BYPASS_EN                         0x40
1554 #define PALMAS_LDO10_CTRL_LDO_BYPASS_EN_SHIFT                   6
1555 #define PALMAS_LDO10_CTRL_STATUS                                0x10
1556 #define PALMAS_LDO10_CTRL_STATUS_SHIFT                          4
1557 #define PALMAS_LDO10_CTRL_MODE_SLEEP                            0x04
1558 #define PALMAS_LDO10_CTRL_MODE_SLEEP_SHIFT                      2
1559 #define PALMAS_LDO10_CTRL_MODE_ACTIVE                           0x01
1560 #define PALMAS_LDO10_CTRL_MODE_ACTIVE_SHIFT                     0
1561
1562 /* Bit definitions for LDO10_VOLTAGE */
1563 #define PALMAS_LDO10_VOLTAGE_VSEL_MASK                          0x3f
1564 #define PALMAS_LDO10_VOLTAGE_VSEL_SHIFT                         0
1565
1566 /* Bit definitions for LDO11_CTRL */
1567 #define PALMAS_LDO11_CTRL_WR_S                                  0x80
1568 #define PALMAS_LDO11_CTRL_WR_S_SHIFT                            7
1569 #define PALMAS_LDO11_CTRL_LDO_BYPASS_EN                         0x40
1570 #define PALMAS_LDO11_CTRL_LDO_BYPASS_EN_SHIFT                   6
1571 #define PALMAS_LDO11_CTRL_STATUS                                0x10
1572 #define PALMAS_LDO11_CTRL_STATUS_SHIFT                          4
1573 #define PALMAS_LDO11_CTRL_MODE_SLEEP                            0x04
1574 #define PALMAS_LDO11_CTRL_MODE_SLEEP_SHIFT                      2
1575 #define PALMAS_LDO11_CTRL_MODE_ACTIVE                           0x01
1576 #define PALMAS_LDO11_CTRL_MODE_ACTIVE_SHIFT                     0
1577
1578 /* Bit definitions for LDO11_VOLTAGE */
1579 #define PALMAS_LDO11_VOLTAGE_VSEL_MASK                          0x3f
1580 #define PALMAS_LDO11_VOLTAGE_VSEL_SHIFT                         0
1581
1582 /* Bit definitions for LDO12_CTRL */
1583 #define PALMAS_LDO12_CTRL_WR_S                                  0x80
1584 #define PALMAS_LDO12_CTRL_WR_S_SHIFT                            7
1585 #define PALMAS_LDO12_CTRL_LDO_BYPASS_EN                         0x40
1586 #define PALMAS_LDO12_CTRL_LDO_BYPASS_EN_SHIFT                   6
1587 #define PALMAS_LDO12_CTRL_STATUS                                0x10
1588 #define PALMAS_LDO12_CTRL_STATUS_SHIFT                          4
1589 #define PALMAS_LDO12_CTRL_MODE_SLEEP                            0x04
1590 #define PALMAS_LDO12_CTRL_MODE_SLEEP_SHIFT                      2
1591 #define PALMAS_LDO12_CTRL_MODE_ACTIVE                           0x01
1592 #define PALMAS_LDO12_CTRL_MODE_ACTIVE_SHIFT                     0
1593
1594 /* Bit definitions for LDO12_VOLTAGE */
1595 #define PALMAS_LDO12_VOLTAGE_VSEL_MASK                          0x3f
1596 #define PALMAS_LDO12_VOLTAGE_VSEL_SHIFT                         0
1597
1598 /* Bit definitions for LDO13_CTRL */
1599 #define PALMAS_LDO13_CTRL_WR_S                                  0x80
1600 #define PALMAS_LDO13_CTRL_WR_S_SHIFT                            7
1601 #define PALMAS_LDO13_CTRL_LDO_BYPASS_EN                         0x40
1602 #define PALMAS_LDO13_CTRL_LDO_BYPASS_EN_SHIFT                   6
1603 #define PALMAS_LDO13_CTRL_STATUS                                0x10
1604 #define PALMAS_LDO13_CTRL_STATUS_SHIFT                          4
1605 #define PALMAS_LDO13_CTRL_MODE_SLEEP                            0x04
1606 #define PALMAS_LDO13_CTRL_MODE_SLEEP_SHIFT                      2
1607 #define PALMAS_LDO13_CTRL_MODE_ACTIVE                           0x01
1608 #define PALMAS_LDO13_CTRL_MODE_ACTIVE_SHIFT                     0
1609
1610 /* Bit definitions for LDO13_VOLTAGE */
1611 #define PALMAS_LDO13_VOLTAGE_VSEL_MASK                          0x3f
1612 #define PALMAS_LDO13_VOLTAGE_VSEL_SHIFT                         0
1613
1614 /* Bit definitions for LDO14_CTRL */
1615 #define PALMAS_LDO14_CTRL_WR_S                                  0x80
1616 #define PALMAS_LDO14_CTRL_WR_S_SHIFT                            7
1617 #define PALMAS_LDO14_CTRL_LDO_BYPASS_EN                         0x40
1618 #define PALMAS_LDO14_CTRL_LDO_BYPASS_EN_SHIFT                   6
1619 #define PALMAS_LDO14_CTRL_STATUS                                0x10
1620 #define PALMAS_LDO14_CTRL_STATUS_SHIFT                          4
1621 #define PALMAS_LDO14_CTRL_MODE_SLEEP                            0x04
1622 #define PALMAS_LDO14_CTRL_MODE_SLEEP_SHIFT                      2
1623 #define PALMAS_LDO14_CTRL_MODE_ACTIVE                           0x01
1624 #define PALMAS_LDO14_CTRL_MODE_ACTIVE_SHIFT                     0
1625
1626 /* Bit definitions for LDO14_VOLTAGE */
1627 #define PALMAS_LDO14_VOLTAGE_VSEL_MASK                          0x3f
1628 #define PALMAS_LDO14_VOLTAGE_VSEL_SHIFT                         0
1629
1630 /* Bit definitions for LDOLN_CTRL */
1631 #define PALMAS_LDOLN_CTRL_WR_S                                  0x80
1632 #define PALMAS_LDOLN_CTRL_WR_S_SHIFT                            7
1633 #define PALMAS_LDOLN_CTRL_STATUS                                0x10
1634 #define PALMAS_LDOLN_CTRL_STATUS_SHIFT                          4
1635 #define PALMAS_LDOLN_CTRL_MODE_SLEEP                            0x04
1636 #define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT                      2
1637 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE                           0x01
1638 #define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT                     0
1639
1640 /* Bit definitions for LDOLN_VOLTAGE */
1641 #define PALMAS_LDOLN_VOLTAGE_VSEL_MASK                          0x3f
1642 #define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT                         0
1643
1644 /* Bit definitions for LDOUSB_CTRL */
1645 #define PALMAS_LDOUSB_CTRL_WR_S                                 0x80
1646 #define PALMAS_LDOUSB_CTRL_WR_S_SHIFT                           7
1647 #define PALMAS_LDOUSB_CTRL_STATUS                               0x10
1648 #define PALMAS_LDOUSB_CTRL_STATUS_SHIFT                         4
1649 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP                           0x04
1650 #define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT                     2
1651 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE                          0x01
1652 #define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT                    0
1653
1654 /* Bit definitions for LDOUSB_VOLTAGE */
1655 #define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK                         0x3f
1656 #define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT                        0
1657
1658 /* Bit definitions for LDO_CTRL */
1659 #define PALMAS_LDO_CTRL_VREF_425                                0x08
1660 #define PALMAS_LDO_CTRL_VREF_425_SHIFT                          3
1661 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_MASK                0x6
1662 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_DISABLE             0x0
1663 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS12              0x2
1664 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS3               0x4
1665 #define PALMAS_LDO_CTRL_LDO5_BYPASS_SRC_SEL_SMPS6               0x6
1666 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS                     0x01
1667 #define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT               0
1668
1669 /* Bit definitions for LDO_PD_CTRL1 */
1670 #define PALMAS_LDO_PD_CTRL1_LDO8                                0x80
1671 #define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT                          7
1672 #define PALMAS_LDO_PD_CTRL1_LDO7                                0x40
1673 #define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT                          6
1674 #define PALMAS_LDO_PD_CTRL1_LDO6                                0x20
1675 #define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT                          5
1676 #define PALMAS_LDO_PD_CTRL1_LDO5                                0x10
1677 #define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT                          4
1678 #define PALMAS_LDO_PD_CTRL1_LDO4                                0x08
1679 #define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT                          3
1680 #define PALMAS_LDO_PD_CTRL1_LDO3                                0x04
1681 #define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT                          2
1682 #define PALMAS_LDO_PD_CTRL1_LDO2                                0x02
1683 #define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT                          1
1684 #define PALMAS_LDO_PD_CTRL1_LDO1                                0x01
1685 #define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT                          0
1686
1687 /* Bit definitions for LDO_PD_CTRL2 */
1688 #define PALMAS_LDO_PD_CTRL2_LDO14                               0x80
1689 #define PALMAS_LDO_PD_CTRL2_LDO14_SHIFT                         7
1690 #define PALMAS_LDO_PD_CTRL2_LDO13                               0x40
1691 #define PALMAS_LDO_PD_CTRL2_LDO13_SHIFT                         6
1692 #define PALMAS_LDO_PD_CTRL2_LDO12                               0x20
1693 #define PALMAS_LDO_PD_CTRL2_LDO12_SHIFT                         5
1694 #define PALMAS_LDO_PD_CTRL2_LDO11                               0x10
1695 #define PALMAS_LDO_PD_CTRL2_LDO11_SHIFT                         4
1696 #define PALMAS_LDO_PD_CTRL2_LDO10                               0x08
1697 #define PALMAS_LDO_PD_CTRL2_LDO10_SHIFT                         3
1698 #define PALMAS_LDO_PD_CTRL2_LDOUSB                              0x04
1699 #define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT                        2
1700 #define PALMAS_LDO_PD_CTRL2_LDOLN                               0x02
1701 #define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT                         1
1702 #define PALMAS_LDO_PD_CTRL2_LDO9                                0x01
1703 #define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT                          0
1704
1705 /* Bit definitions for LDO_SHORT_STATUS1 */
1706 #define PALMAS_LDO_SHORT_STATUS1_LDO8                           0x80
1707 #define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT                     7
1708 #define PALMAS_LDO_SHORT_STATUS1_LDO7                           0x40
1709 #define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT                     6
1710 #define PALMAS_LDO_SHORT_STATUS1_LDO6                           0x20
1711 #define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT                     5
1712 #define PALMAS_LDO_SHORT_STATUS1_LDO5                           0x10
1713 #define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT                     4
1714 #define PALMAS_LDO_SHORT_STATUS1_LDO4                           0x08
1715 #define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT                     3
1716 #define PALMAS_LDO_SHORT_STATUS1_LDO3                           0x04
1717 #define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT                     2
1718 #define PALMAS_LDO_SHORT_STATUS1_LDO2                           0x02
1719 #define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT                     1
1720 #define PALMAS_LDO_SHORT_STATUS1_LDO1                           0x01
1721 #define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT                     0
1722
1723 /* Bit definitions for LDO_SHORT_STATUS2 */
1724 #define PALMAS_LDO_SHORT_STATUS2_LDO14                          0x80
1725 #define PALMAS_LDO_SHORT_STATUS2_LDO14_SHIFT                    7
1726 #define PALMAS_LDO_SHORT_STATUS2_LDO13                          0x40
1727 #define PALMAS_LDO_SHORT_STATUS2_LDO13_SHIFT                    6
1728 #define PALMAS_LDO_SHORT_STATUS2_LDO12                          0x20
1729 #define PALMAS_LDO_SHORT_STATUS2_LDO12_SHIFT                    5
1730 #define PALMAS_LDO_SHORT_STATUS2_LDO11                          0x10
1731 #define PALMAS_LDO_SHORT_STATUS2_LDO11_SHIFT                    4
1732 #define PALMAS_LDO_SHORT_STATUS2_LDO10                          0x08
1733 #define PALMAS_LDO_SHORT_STATUS2_LDO10_SHIFT                    3
1734 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA                        0x08
1735 #define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT                  3
1736 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB                         0x04
1737 #define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT                   2
1738 #define PALMAS_LDO_SHORT_STATUS2_LDOLN                          0x02
1739 #define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT                    1
1740 #define PALMAS_LDO_SHORT_STATUS2_LDO9                           0x01
1741 #define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT                     0
1742
1743 /* Registers for function DVFS Func */
1744 #define PALMAS_SMPS_DVFS1_CTRL                                  0x0
1745 #define PALMAS_SMPS_DVFS1_ENABLE_SHIFT                          0
1746 #define PALMAS_SMPS_DVFS1_OFFSET_STEP_SHIFT                     1
1747 #define PALMAS_SMPS_DVFS1_ENABLE_RST_SHIFT                      2
1748 #define PALMAS_SMPS_DVFS1_RESTORE_VALUE_SHIFT                   3
1749 #define PALMAS_SMPS_DVFS1_SMPS_SELECT_SHIFT                     4
1750 #define PALMAS_SMPS_DVFS1_VOLTAGE_MAX                           0x1
1751 #define PALMAS_SMPS_DVFS1_STATUS                                0x2
1752
1753 #define DVFS_BASE_VOLTAGE_UV                                    500000
1754 #define DVFS_MAX_VOLTAGE_UV                                     1650000
1755 #define DVFS_VOLTAGE_STEP_UV                                    10000
1756
1757 /* Registers for function SIMCARD Func */
1758 #define PALMAS_SIM_DEBOUNCE                                     0x0
1759 #define PALMAS_SIM_PWR_DOWN                                     0x1
1760
1761 /* Bit definitions for SIM_DEBOUNCE */
1762 #define PALMAS_SIM_DEBOUNCE_SIM2_IR                             0x80
1763 #define PALMAS_SIM_DEBOUNCE_SIM2_IR_SHIFT                       7
1764 #define PALMAS_SIM_DEBOUNCE_SIM1_IR                             0x40
1765 #define PALMAS_SIM_DEBOUNCE_SIM1_IR_SHIFT                       6
1766 #define PALMAS_SIM_DEBOUNCE_SIM_DET1_PIN_STATE                  0x20
1767 #define PALMAS_SIM_DEBOUNCE_SIM_DET1_PIN_STATE_SHIFT            5
1768 #define PALMAS_SIM_DEBOUNCE_DBCNT_MASK                          0x1F
1769 #define PALMAS_SIM_DEBOUNCE_DBCNT_SHIFT                         0
1770
1771 /* Bit definitions for SIM_PWR_DOWN */
1772 #define PALMAS_SIM_PWR_DOWN_PWRDNEN2                            0x80
1773 #define PALMAS_SIM_PWR_DOWN_PWRDNEN2_SHIFT                      7
1774 #define PALMAS_SIM_PWR_DOWN_PWRDNEN1                            0x40
1775 #define PALMAS_SIM_PWR_DOWN_PWRDNEN1_SHIFT                      6
1776 #define PALMAS_SIM_PWR_DOWN_SIM_DET2_PIN_STATE                  0x20
1777 #define PALMAS_SIM_PWR_DOWN_SIM_DET2_PIN_STATE_SHIFT            5
1778 #define PALMAS_SIM_PWR_DOWN_PWRDNCNT_MASK                       0x1F
1779 #define PALMAS_SIM_PWR_DOWN_PWRDNCNT_SHIFT                      0
1780
1781 /* Registers for function PMU_CONTROL */
1782 #define PALMAS_DEV_CTRL                                         0x0
1783 #define PALMAS_POWER_CTRL                                       0x1
1784 #define PALMAS_VSYS_LO                                          0x2
1785 #define PALMAS_VSYS_MON                                         0x3
1786 #define PALMAS_VBAT_MON                                         0x4
1787 #define PALMAS_WATCHDOG                                         0x5
1788 #define PALMAS_BOOT_STATUS                                      0x6
1789 #define PALMAS_BATTERY_BOUNCE                                   0x7
1790 #define PALMAS_BACKUP_BATTERY_CTRL                              0x8
1791 #define PALMAS_LONG_PRESS_KEY                                   0x9
1792 #define PALMAS_OSC_THERM_CTRL                                   0xA
1793 #define PALMAS_BATDEBOUNCING                                    0xB
1794 #define PALMAS_SWOFF_HWRST                                      0xF
1795 #define PALMAS_SWOFF_COLDRST                                    0x10
1796 #define PALMAS_SWOFF_STATUS                                     0x11
1797 #define PALMAS_PMU_CONFIG                                       0x12
1798 #define PALMAS_SPARE                                            0x14
1799 #define PALMAS_PMU_SECONDARY_INT                                0x15
1800 #define PALMAS_SW_REVISION                                      0x17
1801 #define PALMAS_EXT_CHRG_CTRL                                    0x18
1802 #define PALMAS_PMU_SECONDARY_INT2                               0x19
1803 #define PALMAS_USB_CHGCTL1                                      0x1A
1804 #define PALMAS_USB_CHGCTL2                                      0x1B
1805
1806 /* Bit definitions for DEV_CTRL */
1807 #define PALMAS_DEV_CTRL_DEV_STATUS_MASK                         0x0c
1808 #define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT                        2
1809 #define PALMAS_DEV_CTRL_SW_RST                                  0x02
1810 #define PALMAS_DEV_CTRL_SW_RST_SHIFT                            1
1811 #define PALMAS_DEV_CTRL_DEV_ON                                  0x01
1812 #define PALMAS_DEV_CTRL_DEV_ON_SHIFT                            0
1813
1814 /* Bit definitions for POWER_CTRL */
1815 #define PALMAS_POWER_CTRL_ENABLE2_MASK                          0x04
1816 #define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT                    2
1817 #define PALMAS_POWER_CTRL_ENABLE1_MASK                          0x02
1818 #define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT                    1
1819 #define PALMAS_POWER_CTRL_NSLEEP_MASK                           0x01
1820 #define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT                     0
1821
1822 /* Bit definitions for VSYS_LO */
1823 #define PALMAS_VSYS_LO_THRESHOLD_MASK                           0x1f
1824 #define PALMAS_VSYS_LO_THRESHOLD_SHIFT                          0
1825
1826 /* Bit definitions for VSYS_MON */
1827 #define PALMAS_VSYS_MON_ENABLE                                  0x80
1828 #define PALMAS_VSYS_MON_ENABLE_SHIFT                            7
1829 #define PALMAS_VSYS_MON_THRESHOLD_MASK                          0x3f
1830 #define PALMAS_VSYS_MON_THRESHOLD_SHIFT                         0
1831
1832 /* Bit definitions for VBAT_MON */
1833 #define PALMAS_VBAT_MON_ENABLE                                  0x80
1834 #define PALMAS_VBAT_MON_ENABLE_SHIFT                            7
1835 #define PALMAS_VBAT_MON_THRESHOLD_MASK                          0x3f
1836 #define PALMAS_VBAT_MON_THRESHOLD_SHIFT                         0
1837
1838 /* Bit definitions for WATCHDOG */
1839 #define PALMAS_WATCHDOG_LOCK                                    0x20
1840 #define PALMAS_WATCHDOG_LOCK_SHIFT                              5
1841 #define PALMAS_WATCHDOG_ENABLE                                  0x10
1842 #define PALMAS_WATCHDOG_ENABLE_SHIFT                            4
1843 #define PALMAS_WATCHDOG_MODE                                    0x08
1844 #define PALMAS_WATCHDOG_MODE_SHIFT                              3
1845 #define PALMAS_WATCHDOG_TIMER_MASK                              0x07
1846 #define PALMAS_WATCHDOG_TIMER_SHIFT                             0
1847
1848 /* Bit definitions for BOOT_STATUS */
1849 #define PALMAS_BOOT_STATUS_BOOT1                                0x02
1850 #define PALMAS_BOOT_STATUS_BOOT1_SHIFT                          1
1851 #define PALMAS_BOOT_STATUS_BOOT0                                0x01
1852 #define PALMAS_BOOT_STATUS_BOOT0_SHIFT                          0
1853
1854 /* Bit definitions for BATTERY_BOUNCE */
1855 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK                     0x3f
1856 #define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT                    0
1857
1858 /* Bit definitions for BACKUP_BATTERY_CTRL */
1859 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15                   0x80
1860 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT             7
1861 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP                  0x40
1862 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT            6
1863 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF                  0x20
1864 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT            5
1865 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN                    0x10
1866 #define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT              4
1867 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG            0x08
1868 #define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT      3
1869 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK                  0x06
1870 #define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT                 1
1871 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN                    0x01
1872 #define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT              0
1873
1874 /* Bit definitions for LONG_PRESS_KEY */
1875 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK                          0x80
1876 #define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT                    7
1877 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR                       0x10
1878 #define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT                 4
1879 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK                     0x0c
1880 #define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT                    2
1881 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK               0x03
1882 #define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT              0
1883
1884 /* Register bit values for various Long_Press_key durations */
1885 #define PALMAS_LONG_PRESS_KEY_TIME_DEFAULT      -1
1886 #define PALMAS_LONG_PRESS_KEY_TIME_6SECONDS     0
1887 #define PALMAS_LONG_PRESS_KEY_TIME_8SECONDS     1
1888 #define PALMAS_LONG_PRESS_KEY_TIME_10SECONDS    2
1889 #define PALMAS_LONG_PRESS_KEY_TIME_12SECONDS    3
1890
1891 /* Bit definitions for OSC_THERM_CTRL */
1892 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP                  0x80
1893 #define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT            7
1894 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP                 0x40
1895 #define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT           6
1896 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP               0x20
1897 #define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT         5
1898 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP                0x10
1899 #define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT          4
1900 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK                 0x0c
1901 #define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT                2
1902 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS                        0x02
1903 #define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT                  1
1904 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE                        0x01
1905 #define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT                  0
1906
1907 /* Bit definitions for BATDEBOUNCING */
1908 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS                     0x80
1909 #define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT               7
1910 #define PALMAS_BATDEBOUNCING_BINS_DEB_MASK                      0x78
1911 #define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT                     3
1912 #define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK                      0x07
1913 #define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT                     0
1914
1915 /* Bit definitions for SWOFF_HWRST */
1916 #define PALMAS_SWOFF_HWRST_PWRON_LPK                            0x80
1917 #define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT                      7
1918 #define PALMAS_SWOFF_HWRST_PWRDOWN                              0x40
1919 #define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT                        6
1920 #define PALMAS_SWOFF_HWRST_WTD                                  0x20
1921 #define PALMAS_SWOFF_HWRST_WTD_SHIFT                            5
1922 #define PALMAS_SWOFF_HWRST_TSHUT                                0x10
1923 #define PALMAS_SWOFF_HWRST_TSHUT_SHIFT                          4
1924 #define PALMAS_SWOFF_HWRST_RESET_IN                             0x08
1925 #define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT                       3
1926 #define PALMAS_SWOFF_HWRST_SW_RST                               0x04
1927 #define PALMAS_SWOFF_HWRST_SW_RST_SHIFT                         2
1928 #define PALMAS_SWOFF_HWRST_VSYS_LO                              0x02
1929 #define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT                        1
1930 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN                       0x01
1931 #define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT                 0
1932
1933 /* Bit definitions for SWOFF_COLDRST */
1934 #define PALMAS_SWOFF_COLDRST_PWRON_LPK                          0x80
1935 #define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT                    7
1936 #define PALMAS_SWOFF_COLDRST_PWRDOWN                            0x40
1937 #define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT                      6
1938 #define PALMAS_SWOFF_COLDRST_WTD                                0x20
1939 #define PALMAS_SWOFF_COLDRST_WTD_SHIFT                          5
1940 #define PALMAS_SWOFF_COLDRST_TSHUT                              0x10
1941 #define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT                        4
1942 #define PALMAS_SWOFF_COLDRST_RESET_IN                           0x08
1943 #define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT                     3
1944 #define PALMAS_SWOFF_COLDRST_SW_RST                             0x04
1945 #define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT                       2
1946 #define PALMAS_SWOFF_COLDRST_VSYS_LO                            0x02
1947 #define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT                      1
1948 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN                     0x01
1949 #define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT               0
1950
1951 /* Bit definitions for SWOFF_STATUS */
1952 #define PALMAS_SWOFF_STATUS_PWRON_LPK                           0x80
1953 #define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT                     7
1954 #define PALMAS_SWOFF_STATUS_PWRDOWN                             0x40
1955 #define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT                       6
1956 #define PALMAS_SWOFF_STATUS_WTD                                 0x20
1957 #define PALMAS_SWOFF_STATUS_WTD_SHIFT                           5
1958 #define PALMAS_SWOFF_STATUS_TSHUT                               0x10
1959 #define PALMAS_SWOFF_STATUS_TSHUT_SHIFT                         4
1960 #define PALMAS_SWOFF_STATUS_RESET_IN                            0x08
1961 #define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT                      3
1962 #define PALMAS_SWOFF_STATUS_SW_RST                              0x04
1963 #define PALMAS_SWOFF_STATUS_SW_RST_SHIFT                        2
1964 #define PALMAS_SWOFF_STATUS_VSYS_LO                             0x02
1965 #define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT                       1
1966 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN                      0x01
1967 #define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT                0
1968
1969 /* Bit definitions for PMU_CONFIG */
1970 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN                         0x40
1971 #define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT                   6
1972 #define PALMAS_PMU_CONFIG_SPARE_MASK                            0x30
1973 #define PALMAS_PMU_CONFIG_SPARE_SHIFT                           4
1974 #define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK                        0x0c
1975 #define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT                       2
1976 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT                        0x02
1977 #define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT                  1
1978 #define PALMAS_PMU_CONFIG_AUTODEVON                             0x01
1979 #define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT                       0
1980
1981 /* Bit definitions for SPARE */
1982 #define PALMAS_SPARE_SPARE_MASK                                 0xf8
1983 #define PALMAS_SPARE_SPARE_SHIFT                                3
1984 #define PALMAS_SPARE_REGEN3_OD                                  0x04
1985 #define PALMAS_SPARE_REGEN3_OD_SHIFT                            2
1986 #define PALMAS_SPARE_REGEN2_OD                                  0x02
1987 #define PALMAS_SPARE_REGEN2_OD_SHIFT                            1
1988 #define PALMAS_SPARE_REGEN1_OD                                  0x01
1989 #define PALMAS_SPARE_REGEN1_OD_SHIFT                            0
1990
1991 /* Bit definitions for PMU_SECONDARY_INT */
1992 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC               0x80
1993 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT         7
1994 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC            0x40
1995 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT      6
1996 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC                     0x20
1997 #define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT               5
1998 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC                    0x10
1999 #define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT              4
2000 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK                  0x08
2001 #define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT            3
2002 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK               0x04
2003 #define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT         2
2004 #define PALMAS_PMU_SECONDARY_INT_BB_MASK                        0x02
2005 #define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT                  1
2006 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK                       0x01
2007 #define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT                 0
2008
2009 /* Bit definitions for SW_REVISION */
2010 #define PALMAS_SW_REVISION_SW_REVISION_MASK                     0xff
2011 #define PALMAS_SW_REVISION_SW_REVISION_SHIFT                    0
2012
2013 /* Bit definitions for EXT_CHRG_CTRL */
2014 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS                    0x80
2015 #define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT              7
2016 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS                 0x40
2017 #define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT           6
2018 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY                0x08
2019 #define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT          3
2020 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N                         0x04
2021 #define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT                   2
2022 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN                        0x02
2023 #define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT                  1
2024 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN                     0x01
2025 #define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT               0
2026
2027 /* Bit definitions for PMU_SECONDARY_INT2 */
2028 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC                 0x20
2029 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT           5
2030 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC                 0x10
2031 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT           4
2032 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK                    0x02
2033 #define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT              1
2034 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK                    0x01
2035 #define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT              0
2036
2037 /* Bit definitions for USB_CHGCTL1 */
2038 #define PALMAS_USB_CHGCTL1_USB_SUSPEND                          0x04
2039
2040 /* Bit definitions for USB_CHGCTL2 */
2041 #define PALMAS_USB_CHGCTL2_BOOST_EN                             0x08
2042
2043 /* Registers for function RESOURCE */
2044 #define PALMAS_CLK32KG_CTRL                                     0x0
2045 #define PALMAS_CLK32KGAUDIO_CTRL                                0x1
2046 #define PALMAS_REGEN1_CTRL                                      0x2
2047 #define PALMAS_REGEN2_CTRL                                      0x3
2048 #define PALMAS_SYSEN1_CTRL                                      0x4
2049 #define PALMAS_SYSEN2_CTRL                                      0x5
2050 #define PALMAS_NSLEEP_RES_ASSIGN                                0x6
2051 #define PALMAS_NSLEEP_SMPS_ASSIGN                               0x7
2052 #define PALMAS_NSLEEP_LDO_ASSIGN1                               0x8
2053 #define PALMAS_NSLEEP_LDO_ASSIGN2                               0x9
2054 #define PALMAS_ENABLE1_RES_ASSIGN                               0xA
2055 #define PALMAS_ENABLE1_SMPS_ASSIGN                              0xB
2056 #define PALMAS_ENABLE1_LDO_ASSIGN1                              0xC
2057 #define PALMAS_ENABLE1_LDO_ASSIGN2                              0xD
2058 #define PALMAS_ENABLE2_RES_ASSIGN                               0xE
2059 #define PALMAS_ENABLE2_SMPS_ASSIGN                              0xF
2060 #define PALMAS_ENABLE2_LDO_ASSIGN1                              0x10
2061 #define PALMAS_ENABLE2_LDO_ASSIGN2                              0x11
2062 #define PALMAS_REGEN3_CTRL                                      0x12
2063 #define PALMAS_REGEN4_CTRL                                      0x13
2064 #define PALMAS_REGEN5_CTRL                                      0x14
2065 #define PALMAS_REGEN7_CTRL                                      0x16
2066 #define PALMAS_NSLEEP_RES_ASSIGN2                               0x18
2067 #define PALMAS_ENABLE1_RES_ASSIGN2                              0x19
2068 #define PALMAS_ENABLE2_RES_ASSIGN2                              0x1A
2069
2070 /* Bit definitions for CLK32KG_CTRL */
2071 #define PALMAS_CLK32KG_CTRL_STATUS                              0x10
2072 #define PALMAS_CLK32KG_CTRL_STATUS_SHIFT                        4
2073 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP                          0x04
2074 #define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT                    2
2075 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE                         0x01
2076 #define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT                   0
2077
2078 /* Bit definitions for CLK32KGAUDIO_CTRL */
2079 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS                         0x10
2080 #define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT                   4
2081 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3                      0x08
2082 #define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT                3
2083 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP                     0x04
2084 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT               2
2085 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE                    0x01
2086 #define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT              0
2087
2088 /* Bit definitions for REGEN1_CTRL */
2089 #define PALMAS_REGEN1_CTRL_STATUS                               0x10
2090 #define PALMAS_REGEN1_CTRL_STATUS_SHIFT                         4
2091 #define PALMAS_REGEN1_CTRL_MODE_SLEEP                           0x04
2092 #define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT                     2
2093 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE                          0x01
2094 #define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT                    0
2095
2096 /* Bit definitions for REGEN2_CTRL */
2097 #define PALMAS_REGEN2_CTRL_STATUS                               0x10
2098 #define PALMAS_REGEN2_CTRL_STATUS_SHIFT                         4
2099 #define PALMAS_REGEN2_CTRL_MODE_SLEEP                           0x04
2100 #define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT                     2
2101 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE                          0x01
2102 #define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT                    0
2103
2104 /* Bit definitions for SYSEN1_CTRL */
2105 #define PALMAS_SYSEN1_CTRL_STATUS                               0x10
2106 #define PALMAS_SYSEN1_CTRL_STATUS_SHIFT                         4
2107 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP                           0x04
2108 #define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT                     2
2109 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE                          0x01
2110 #define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT                    0
2111
2112 /* Bit definitions for SYSEN2_CTRL */
2113 #define PALMAS_SYSEN2_CTRL_STATUS                               0x10
2114 #define PALMAS_SYSEN2_CTRL_STATUS_SHIFT                         4
2115 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP                           0x04
2116 #define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT                     2
2117 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE                          0x01
2118 #define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT                    0
2119
2120 /* Bit definitions for NSLEEP_RES_ASSIGN */
2121 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN4                         0x80
2122 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN4_SHIFT                   7
2123 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3                         0x40
2124 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT                   6
2125 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO                   0x20
2126 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT             5
2127 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG                        0x10
2128 #define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT                  4
2129 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2                         0x08
2130 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT                   3
2131 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1                         0x04
2132 #define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT                   2
2133 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2                         0x02
2134 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT                   1
2135 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1                         0x01
2136 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT                   0
2137
2138 /* Bit definitions for NSLEEP_SMPS_ASSIGN */
2139 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10                        0x80
2140 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT                  7
2141 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9                         0x40
2142 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT                   6
2143 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8                         0x20
2144 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT                   5
2145 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7                         0x10
2146 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT                   4
2147 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6                         0x08
2148 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT                   3
2149 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45                        0x04
2150 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT                  2
2151 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3                         0x02
2152 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT                   1
2153 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12                        0x01
2154 #define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT                  0
2155
2156 /* Bit definitions for NSLEEP_LDO_ASSIGN1 */
2157 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8                          0x80
2158 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT                    7
2159 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7                          0x40
2160 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT                    6
2161 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6                          0x20
2162 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT                    5
2163 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5                          0x10
2164 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT                    4
2165 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4                          0x08
2166 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT                    3
2167 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3                          0x04
2168 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT                    2
2169 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2                          0x02
2170 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT                    1
2171 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1                          0x01
2172 #define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT                    0
2173
2174 /* Bit definitions for NSLEEP_LDO_ASSIGN2 */
2175 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO14                         0x80
2176 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO14_SHIFT                   7
2177 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO13                         0x40
2178 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO13_SHIFT                   6
2179 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO12                         0x20
2180 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO12_SHIFT                   5
2181 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO11                         0x10
2182 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO11_SHIFT                   4
2183 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO10                         0x08
2184 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO10_SHIFT                   3
2185 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB                        0x04
2186 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT                  2
2187 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN                         0x02
2188 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT                   1
2189 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9                          0x01
2190 #define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT                    0
2191
2192 /* Bit definitions for ENABLE1_RES_ASSIGN */
2193 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN4                        0x80
2194 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN4_SHIFT                  7
2195 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3                        0x40
2196 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT                  6
2197 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO                  0x20
2198 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
2199 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG                       0x10
2200 #define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT                 4
2201 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2                        0x08
2202 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT                  3
2203 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1                        0x04
2204 #define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT                  2
2205 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2                        0x02
2206 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT                  1
2207 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1                        0x01
2208 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT                  0
2209
2210 /* Bit definitions for ENABLE1_SMPS_ASSIGN */
2211 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10                       0x80
2212 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT                 7
2213 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9                        0x40
2214 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT                  6
2215 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8                        0x20
2216 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT                  5
2217 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7                        0x10
2218 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT                  4
2219 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6                        0x08
2220 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT                  3
2221 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45                       0x04
2222 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT                 2
2223 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3                        0x02
2224 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT                  1
2225 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12                       0x01
2226 #define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT                 0
2227
2228 /* Bit definitions for ENABLE1_LDO_ASSIGN1 */
2229 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8                         0x80
2230 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT                   7
2231 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7                         0x40
2232 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT                   6
2233 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6                         0x20
2234 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT                   5
2235 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5                         0x10
2236 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT                   4
2237 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4                         0x08
2238 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT                   3
2239 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3                         0x04
2240 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT                   2
2241 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2                         0x02
2242 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT                   1
2243 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1                         0x01
2244 #define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT                   0
2245
2246 /* Bit definitions for ENABLE1_LDO_ASSIGN2 */
2247 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO14                        0x80
2248 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO14_SHIFT                  7
2249 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO13                        0x40
2250 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO13_SHIFT                  6
2251 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO12                        0x20
2252 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO12_SHIFT                  5
2253 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO11                        0x10
2254 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO11_SHIFT                  4
2255 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO10                        0x08
2256 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO10_SHIFT                  3
2257 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB                       0x04
2258 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT                 2
2259 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN                        0x02
2260 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT                  1
2261 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9                         0x01
2262 #define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT                   0
2263
2264 /* Bit definitions for ENABLE2_RES_ASSIGN */
2265 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN4                        0x80
2266 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN4_SHIFT                  7
2267 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3                        0x40
2268 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT                  6
2269 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO                  0x20
2270 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT            5
2271 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG                       0x10
2272 #define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT                 4
2273 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2                        0x08
2274 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT                  3
2275 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1                        0x04
2276 #define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT                  2
2277 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2                        0x02
2278 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT                  1
2279 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1                        0x01
2280 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT                  0
2281
2282 /* Bit definitions for ENABLE2_SMPS_ASSIGN */
2283 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10                       0x80
2284 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT                 7
2285 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9                        0x40
2286 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT                  6
2287 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8                        0x20
2288 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT                  5
2289 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7                        0x10
2290 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT                  4
2291 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6                        0x08
2292 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT                  3
2293 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45                       0x04
2294 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT                 2
2295 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3                        0x02
2296 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT                  1
2297 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12                       0x01
2298 #define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT                 0
2299
2300 /* Bit definitions for ENABLE2_LDO_ASSIGN1 */
2301 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8                         0x80
2302 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT                   7
2303 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7                         0x40
2304 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT                   6
2305 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6                         0x20
2306 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT                   5
2307 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5                         0x10
2308 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT                   4
2309 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4                         0x08
2310 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT                   3
2311 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3                         0x04
2312 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT                   2
2313 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2                         0x02
2314 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT                   1
2315 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1                         0x01
2316 #define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT                   0
2317
2318 /* Bit definitions for ENABLE2_LDO_ASSIGN2 */
2319 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO14                        0x80
2320 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO14_SHIFT                  7
2321 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO13                        0x40
2322 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO13_SHIFT                  6
2323 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO12                        0x20
2324 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO12_SHIFT                  5
2325 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO11                        0x10
2326 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO11_SHIFT                  4
2327 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO10                        0x08
2328 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO10_SHIFT                  3
2329 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB                       0x04
2330 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT                 2
2331 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN                        0x02
2332 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT                  1
2333 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9                         0x01
2334 #define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT                   0
2335
2336 /* Bit definitions for REGEN3_CTRL */
2337 #define PALMAS_REGEN3_CTRL_STATUS                               0x10
2338 #define PALMAS_REGEN3_CTRL_STATUS_SHIFT                         4
2339 #define PALMAS_REGEN3_CTRL_MODE_SLEEP                           0x04
2340 #define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT                     2
2341 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE                          0x01
2342 #define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT                    0
2343
2344 /* Bit definitions for REGEN4_CTRL */
2345 #define PALMAS_REGEN4_CTRL_STATUS                               0x10
2346 #define PALMAS_REGEN4_CTRL_STATUS_SHIFT                         4
2347 #define PALMAS_REGEN4_CTRL_MODE_SLEEP                           0x04
2348 #define PALMAS_REGEN4_CTRL_MODE_SLEEP_SHIFT                     2
2349 #define PALMAS_REGEN4_CTRL_MODE_ACTIVE                          0x01
2350 #define PALMAS_REGEN4_CTRL_MODE_ACTIVE_SHIFT                    0
2351
2352 /* Bit definitions for REGEN5_CTRL */
2353 #define PALMAS_REGEN5_CTRL_STATUS                               0x10
2354 #define PALMAS_REGEN5_CTRL_STATUS_SHIFT                         4
2355 #define PALMAS_REGEN5_CTRL_MODE_SLEEP                           0x04
2356 #define PALMAS_REGEN5_CTRL_MODE_SLEEP_SHIFT                     2
2357 #define PALMAS_REGEN5_CTRL_MODE_ACTIVE                          0x01
2358 #define PALMAS_REGEN5_CTRL_MODE_ACTIVE_SHIFT                    0
2359
2360 /* Bit definitions for REGEN7_CTRL */
2361 #define PALMAS_REGEN7_CTRL_STATUS                               0x10
2362 #define PALMAS_REGEN7_CTRL_STATUS_SHIFT                         4
2363 #define PALMAS_REGEN7_CTRL_MODE_SLEEP                           0x04
2364 #define PALMAS_REGEN7_CTRL_MODE_SLEEP_SHIFT                     2
2365 #define PALMAS_REGEN7_CTRL_MODE_ACTIVE                          0x01
2366 #define PALMAS_REGEN7_CTRL_MODE_ACTIVE_SHIFT                    0
2367
2368 /* Bit definitions for NSLEEP_RES_ASSIGN2 */
2369 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN7                         0x04
2370 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN7_SHIFT                   2
2371 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN5                         0x01
2372 #define PALMAS_NSLEEP_RES_ASSIGN_REGEN5_SHIFT                   0
2373
2374 /* Bit definitions for ENABLE1_RES_ASSIGN2 */
2375 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN7                        0x04
2376 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN7_SHIFT                  2
2377 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN5                        0x01
2378 #define PALMAS_ENABLE1_RES_ASSIGN_REGEN5_SHIFT                  0
2379
2380 /* Bit definitions for ENABLE2_RES_ASSIGN2 */
2381 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN7                        0x04
2382 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN7_SHIFT                  2
2383 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN5                        0x01
2384 #define PALMAS_ENABLE2_RES_ASSIGN_REGEN5_SHIFT                  0
2385
2386 /* Registers for function PAD_CONTROL */
2387 #define PALMAS_OD_OUTPUT_CTRL2                                  0x2
2388 #define PALMAS_POLARITY_CTRL2                                   0x3
2389 #define PALMAS_PU_PD_INPUT_CTRL1                                0x4
2390 #define PALMAS_PU_PD_INPUT_CTRL2                                0x5
2391 #define PALMAS_PU_PD_INPUT_CTRL3                                0x6
2392 #define PALMAS_PU_PD_INPUT_CTRL5                                0x7
2393 #define PALMAS_OD_OUTPUT_CTRL                                   0x8
2394 #define PALMAS_POLARITY_CTRL                                    0x9
2395 #define PALMAS_PRIMARY_SECONDARY_PAD1                           0xA
2396 #define PALMAS_PRIMARY_SECONDARY_PAD2                           0xB
2397 #define PALMAS_I2C_SPI                                          0xC
2398 #define PALMAS_PU_PD_INPUT_CTRL4                                0xD
2399 #define PALMAS_PRIMARY_SECONDARY_PAD3                           0xE
2400 #define PALMAS_PRIMARY_SECONDARY_PAD4                           0xF
2401
2402 /* Bit definitions for OD_OUTPUT_CTRL2 */
2403 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN7                        0x40
2404 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN7_SHIFT                  6
2405 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN5                        0x10
2406 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN5_SHIFT                  4
2407 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN4                        0x08
2408 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN4_SHIFT                  3
2409 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN2                        0x02
2410 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN2_SHIFT                  1
2411 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN1                        0x01
2412 #define PALMAS_OD_OUTPUT_CTRL2_OD_REGEN1_SHIFT                  0
2413
2414 /* Bit definitions for POLARITY_CTRL2 */
2415 #define PALMAS_POLARITY_CTRL2_DET_POLARITY                      0x01
2416 #define PALMAS_POLARITY_CTRL2_DET_POLARITY_SHIFT                0
2417
2418 /* Bit definitions for PU_PD_INPUT_CTRL1 */
2419 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD                    0x40
2420 #define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT              6
2421 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU                 0x20
2422 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT           5
2423 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD                 0x10
2424 #define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT           4
2425 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD                     0x04
2426 #define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT               2
2427 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU                    0x02
2428 #define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT              1
2429
2430 /* Bit definitions for PU_PD_INPUT_CTRL2 */
2431 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU                     0x20
2432 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT               5
2433 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD                     0x10
2434 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT               4
2435 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU                     0x08
2436 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT               3
2437 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD                     0x04
2438 #define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT               2
2439 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU                      0x02
2440 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT                1
2441 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD                      0x01
2442 #define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT                0
2443
2444 /* Bit definitions for PU_PD_INPUT_CTRL3 */
2445 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD                        0x40
2446 #define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT                  6
2447 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD                  0x10
2448 #define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT            4
2449 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD                   0x04
2450 #define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT             2
2451 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD                     0x01
2452 #define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT               0
2453
2454 /* Bit definitions for PU_PD_INPUT_CTRL5 */
2455 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PU                        0x80
2456 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PU_SHIFT                  7
2457 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PD                        0x40
2458 #define PALMAS_PU_PD_INPUT_CTRL5_DET2_PD_SHIFT                  6
2459 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PU                        0x20
2460 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PU_SHIFT                  5
2461 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PD                        0x10
2462 #define PALMAS_PU_PD_INPUT_CTRL5_DET1_PD_SHIFT                  4
2463
2464 /* Bit definitions for OD_OUTPUT_CTRL */
2465 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD                          0x80
2466 #define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT                    7
2467 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD                        0x40
2468 #define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT                  6
2469 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD                          0x20
2470 #define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT                    5
2471 #define PALMAS_OD_OUTPUT_CTRL_INT_OD                            0x08
2472 #define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT                      3
2473
2474 /* Bit definitions for POLARITY_CTRL */
2475 #define PALMAS_POLARITY_CTRL_INT_POLARITY                       0x80
2476 #define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT                 7
2477 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY                   0x40
2478 #define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT             6
2479 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY                   0x20
2480 #define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT             5
2481 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY                    0x10
2482 #define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT              4
2483 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY                  0x08
2484 #define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT            3
2485 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY         0x04
2486 #define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT   2
2487 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY        0x02
2488 #define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT  1
2489 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY                   0x01
2490 #define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT             0
2491
2492 /* Bit definitions for PRIMARY_SECONDARY_PAD1 */
2493 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3                    0x80
2494 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT              7
2495 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK               0x60
2496 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT              5
2497 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK               0x18
2498 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT              3
2499 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0                    0x04
2500 #define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT              2
2501 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC                       0x02
2502 #define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT                 1
2503 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD                 0x01
2504 #define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT           0
2505
2506 /* Bit definitions for PRIMARY_SECONDARY_PAD2 */
2507 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_MSB                0x04
2508 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_MSB_SHIFT          6
2509 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK               0x30
2510 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT              4
2511 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6                    0x08
2512 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT              3
2513 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK               0x06
2514 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT              1
2515 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4                    0x01
2516 #define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT              0
2517
2518 /* Bit definitions for I2C_SPI */
2519 #define PALMAS_I2C_SPI_I2C2OTP_EN                               0x80
2520 #define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT                         7
2521 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL                          0x40
2522 #define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT                    6
2523 #define PALMAS_I2C_SPI_ID_I2C2                                  0x20
2524 #define PALMAS_I2C_SPI_ID_I2C2_SHIFT                            5
2525 #define PALMAS_I2C_SPI_I2C_SPI                                  0x10
2526 #define PALMAS_I2C_SPI_I2C_SPI_SHIFT                            4
2527 #define PALMAS_I2C_SPI_ID_I2C1_MASK                             0x0f
2528 #define PALMAS_I2C_SPI_ID_I2C1_SHIFT                            0
2529
2530 /* Bit definitions for PU_PD_INPUT_CTRL4 */
2531 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD                   0x40
2532 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT             6
2533 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD                   0x10
2534 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT             4
2535 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD                   0x04
2536 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT             2
2537 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD                   0x01
2538 #define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT             0
2539
2540 /* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2541 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2                     0x02
2542 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT               1
2543 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1                     0x01
2544 #define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT               0
2545
2546 /* Bit definitions for PRIMARY_SECONDARY_PAD4 */
2547 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_15_MASK              0x80
2548 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_15_SHIFT             7
2549 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_14_MASK              0x40
2550 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_14_SHIFT             6
2551 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_13_MASK              0x20
2552 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_13_SHIFT             5
2553 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_12_MASK              0x10
2554 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_12_SHIFT             4
2555 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_11_MASK              0x08
2556 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_11_SHIFT             3
2557 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_10_MASK              0x04
2558 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_10_SHIFT             2
2559 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_9_MASK               0x02
2560 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_9_SHIFT              1
2561 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_8_MASK               0x01
2562 #define PALMAS_PRIMARY_SECONDARY_PAD4_GPIO_8_SHIFT              0
2563
2564 /* Registers for function LED_PWM */
2565 #define PALMAS_LED_PERIOD_CTRL                                  0x0
2566 #define PALMAS_LED_CTRL                                         0x1
2567 #define PALMAS_PWM_CTRL1                                        0x2
2568 #define PALMAS_PWM_CTRL2                                        0x3
2569
2570 /* Bit definitions for LED_PERIOD_CTRL */
2571 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK                0x38
2572 #define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT               3
2573 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK                0x07
2574 #define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT               0
2575
2576 /* Bit definitions for LED_CTRL */
2577 #define PALMAS_LED_CTRL_LED_2_SEQ                               0x20
2578 #define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT                         5
2579 #define PALMAS_LED_CTRL_LED_1_SEQ                               0x10
2580 #define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT                         4
2581 #define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK                      0x0c
2582 #define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT                     2
2583 #define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK                      0x03
2584 #define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT                     0
2585
2586 /* Bit definitions for PWM_CTRL1 */
2587 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN                            0x02
2588 #define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT                      1
2589 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL                           0x01
2590 #define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT                     0
2591
2592 /* Bit definitions for PWM_CTRL2 */
2593 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK                      0xff
2594 #define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT                     0
2595
2596 /* Maximum INT mask/edge regsiter */
2597 #define PALMAS_MAX_INTERRUPT_MASK_REG                           6
2598 #define PALMAS_MAX_INTERRUPT_EDGE_REG                           12
2599
2600 /* Registers for function INTERRUPT */
2601 #define PALMAS_INT1_STATUS                                      0x0
2602 #define PALMAS_INT1_MASK                                        0x1
2603 #define PALMAS_INT1_LINE_STATE                                  0x2
2604 #define PALMAS_INT1_EDGE_DETECT1_RESERVED                       0x3
2605 #define PALMAS_INT1_EDGE_DETECT2_RESERVED                       0x4
2606 #define PALMAS_INT2_STATUS                                      0x5
2607 #define PALMAS_INT2_MASK                                        0x6
2608 #define PALMAS_INT2_LINE_STATE                                  0x7
2609 #define PALMAS_INT2_EDGE_DETECT1_RESERVED                       0x8
2610 #define PALMAS_INT2_EDGE_DETECT2_RESERVED                       0x9
2611 #define PALMAS_INT3_STATUS                                      0xA
2612 #define PALMAS_INT3_MASK                                        0xB
2613 #define PALMAS_INT3_LINE_STATE                                  0xC
2614 #define PALMAS_INT3_EDGE_DETECT1_RESERVED                       0xD
2615 #define PALMAS_INT3_EDGE_DETECT2_RESERVED                       0xE
2616 #define PALMAS_INT4_STATUS                                      0xF
2617 #define PALMAS_INT4_MASK                                        0x10
2618 #define PALMAS_INT4_LINE_STATE                                  0x11
2619 #define PALMAS_INT4_EDGE_DETECT1                                0x12
2620 #define PALMAS_INT4_EDGE_DETECT2                                0x13
2621 #define PALMAS_INT5_STATUS                                      0x15
2622 #define PALMAS_INT5_MASK                                        0x16
2623 #define PALMAS_INT5_LINE_STATE                                  0x17
2624 #define PALMAS_INT5_EDGE_DETECT1                                0x18
2625 #define PALMAS_INT5_EDGE_DETECT2                                0x19
2626 #define PALMAS_INT_CTRL                                         0x14
2627 #define PALMAS_INT5_STATUS                                      0x15
2628 #define PALMAS_INT5_MASK                                        0x16
2629 #define PALMAS_INT5_LINE_STATE                                  0x17
2630 #define PALMAS_INT5_EDGE_DETECT1                                0x18
2631 #define PALMAS_INT5_EDGE_DETECT2                                0x19
2632 #define PALMAS_INT6_STATUS                                      0x1A
2633 #define PALMAS_INT6_MASK                                        0x1B
2634 #define PALMAS_INT6_LINE_STATE                                  0x1C
2635 #define PALMAS_INT6_EDGE_DETECT1_RESERVED                       0x1D
2636 #define PALMAS_INT6_EDGE_DETECT2_RESERVED                       0x1E
2637
2638 /* Bit definitions for INT1_STATUS */
2639 #define PALMAS_INT1_STATUS_VBAT_MON                             0x80
2640 #define PALMAS_INT1_STATUS_VBAT_MON_SHIFT                       7
2641 #define PALMAS_INT1_STATUS_VSYS_MON                             0x40
2642 #define PALMAS_INT1_STATUS_VSYS_MON_SHIFT                       6
2643 #define PALMAS_INT1_STATUS_HOTDIE                               0x20
2644 #define PALMAS_INT1_STATUS_HOTDIE_SHIFT                         5
2645 #define PALMAS_INT1_STATUS_PWRDOWN                              0x10
2646 #define PALMAS_INT1_STATUS_PWRDOWN_SHIFT                        4
2647 #define PALMAS_INT1_STATUS_RPWRON                               0x08
2648 #define PALMAS_INT1_STATUS_RPWRON_SHIFT                         3
2649 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY                       0x04
2650 #define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT                 2
2651 #define PALMAS_INT1_STATUS_PWRON                                0x02
2652 #define PALMAS_INT1_STATUS_PWRON_SHIFT                          1
2653 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV                 0x01
2654 #define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT           0
2655
2656 /* Bit definitions for INT1_MASK */
2657 #define PALMAS_INT1_MASK_VBAT_MON                               0x80
2658 #define PALMAS_INT1_MASK_VBAT_MON_SHIFT                         7
2659 #define PALMAS_INT1_MASK_VSYS_MON                               0x40
2660 #define PALMAS_INT1_MASK_VSYS_MON_SHIFT                         6
2661 #define PALMAS_INT1_MASK_HOTDIE                                 0x20
2662 #define PALMAS_INT1_MASK_HOTDIE_SHIFT                           5
2663 #define PALMAS_INT1_MASK_PWRDOWN                                0x10
2664 #define PALMAS_INT1_MASK_PWRDOWN_SHIFT                          4
2665 #define PALMAS_INT1_MASK_RPWRON                                 0x08
2666 #define PALMAS_INT1_MASK_RPWRON_SHIFT                           3
2667 #define PALMAS_INT1_MASK_LONG_PRESS_KEY                         0x04
2668 #define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT                   2
2669 #define PALMAS_INT1_MASK_PWRON                                  0x02
2670 #define PALMAS_INT1_MASK_PWRON_SHIFT                            1
2671 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV                   0x01
2672 #define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT             0
2673
2674 /* Bit definitions for INT1_LINE_STATE */
2675 #define PALMAS_INT1_LINE_STATE_VBAT_MON                         0x80
2676 #define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT                   7
2677 #define PALMAS_INT1_LINE_STATE_VSYS_MON                         0x40
2678 #define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT                   6
2679 #define PALMAS_INT1_LINE_STATE_HOTDIE                           0x20
2680 #define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT                     5
2681 #define PALMAS_INT1_LINE_STATE_PWRDOWN                          0x10
2682 #define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT                    4
2683 #define PALMAS_INT1_LINE_STATE_RPWRON                           0x08
2684 #define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT                     3
2685 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY                   0x04
2686 #define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT             2
2687 #define PALMAS_INT1_LINE_STATE_PWRON                            0x02
2688 #define PALMAS_INT1_LINE_STATE_PWRON_SHIFT                      1
2689 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV             0x01
2690 #define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT       0
2691
2692 /* Bit definitions for INT2_STATUS */
2693 #define PALMAS_INT2_STATUS_VAC_ACOK                             0x80
2694 #define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT                       7
2695 #define PALMAS_INT2_STATUS_SHORT                                0x40
2696 #define PALMAS_INT2_STATUS_SHORT_SHIFT                          6
2697 #define PALMAS_INT2_STATUS_FBI_BB                               0x20
2698 #define PALMAS_INT2_STATUS_FBI_BB_SHIFT                         5
2699 #define PALMAS_INT2_STATUS_RESET_IN                             0x10
2700 #define PALMAS_INT2_STATUS_RESET_IN_SHIFT                       4
2701 #define PALMAS_INT2_STATUS_BATREMOVAL                           0x08
2702 #define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT                     3
2703 #define PALMAS_INT2_STATUS_WDT                                  0x04
2704 #define PALMAS_INT2_STATUS_WDT_SHIFT                            2
2705 #define PALMAS_INT2_STATUS_RTC_TIMER                            0x02
2706 #define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT                      1
2707 #define PALMAS_INT2_STATUS_RTC_ALARM                            0x01
2708 #define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT                      0
2709
2710 /* Bit definitions for INT2_MASK */
2711 #define PALMAS_INT2_MASK_VAC_ACOK                               0x80
2712 #define PALMAS_INT2_MASK_VAC_ACOK_SHIFT                         7
2713 #define PALMAS_INT2_MASK_SHORT                                  0x40
2714 #define PALMAS_INT2_MASK_SHORT_SHIFT                            6
2715 #define PALMAS_INT2_MASK_FBI_BB                                 0x20
2716 #define PALMAS_INT2_MASK_FBI_BB_SHIFT                           5
2717 #define PALMAS_INT2_MASK_RESET_IN                               0x10
2718 #define PALMAS_INT2_MASK_RESET_IN_SHIFT                         4
2719 #define PALMAS_INT2_MASK_BATREMOVAL                             0x08
2720 #define PALMAS_INT2_MASK_BATREMOVAL_SHIFT                       3
2721 #define PALMAS_INT2_MASK_WDT                                    0x04
2722 #define PALMAS_INT2_MASK_WDT_SHIFT                              2
2723 #define PALMAS_INT2_MASK_RTC_TIMER                              0x02
2724 #define PALMAS_INT2_MASK_RTC_TIMER_SHIFT                        1
2725 #define PALMAS_INT2_MASK_RTC_ALARM                              0x01
2726 #define PALMAS_INT2_MASK_RTC_ALARM_SHIFT                        0
2727
2728 /* Bit definitions for INT2_LINE_STATE */
2729 #define PALMAS_INT2_LINE_STATE_VAC_ACOK                         0x80
2730 #define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT                   7
2731 #define PALMAS_INT2_LINE_STATE_SHORT                            0x40
2732 #define PALMAS_INT2_LINE_STATE_SHORT_SHIFT                      6
2733 #define PALMAS_INT2_LINE_STATE_FBI_BB                           0x20
2734 #define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT                     5
2735 #define PALMAS_INT2_LINE_STATE_RESET_IN                         0x10
2736 #define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT                   4
2737 #define PALMAS_INT2_LINE_STATE_BATREMOVAL                       0x08
2738 #define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT                 3
2739 #define PALMAS_INT2_LINE_STATE_WDT                              0x04
2740 #define PALMAS_INT2_LINE_STATE_WDT_SHIFT                        2
2741 #define PALMAS_INT2_LINE_STATE_RTC_TIMER                        0x02
2742 #define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT                  1
2743 #define PALMAS_INT2_LINE_STATE_RTC_ALARM                        0x01
2744 #define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT                  0
2745
2746 /* Bit definitions for INT3_STATUS */
2747 #define PALMAS_INT3_STATUS_VBUS                                 0x80
2748 #define PALMAS_INT3_STATUS_VBUS_SHIFT                           7
2749 #define PALMAS_INT3_STATUS_VBUS_OTG                             0x40
2750 #define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT                       6
2751 #define PALMAS_INT3_STATUS_ID                                   0x20
2752 #define PALMAS_INT3_STATUS_ID_SHIFT                             5
2753 #define PALMAS_INT3_STATUS_ID_OTG                               0x10
2754 #define PALMAS_INT3_STATUS_ID_OTG_SHIFT                         4
2755 #define PALMAS_INT3_STATUS_GPADC_EOC_RT                         0x08
2756 #define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT                   3
2757 #define PALMAS_INT3_STATUS_GPADC_EOC_SW                         0x04
2758 #define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT                   2
2759 #define PALMAS_INT3_STATUS_GPADC_AUTO_1                         0x02
2760 #define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT                   1
2761 #define PALMAS_INT3_STATUS_GPADC_AUTO_0                         0x01
2762 #define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT                   0
2763
2764 /* Bit definitions for INT3_MASK */
2765 #define PALMAS_INT3_MASK_VBUS                                   0x80
2766 #define PALMAS_INT3_MASK_VBUS_SHIFT                             7
2767 #define PALMAS_INT3_MASK_VBUS_OTG                               0x40
2768 #define PALMAS_INT3_MASK_VBUS_OTG_SHIFT                         6
2769 #define PALMAS_INT3_MASK_ID                                     0x20
2770 #define PALMAS_INT3_MASK_ID_SHIFT                               5
2771 #define PALMAS_INT3_MASK_ID_OTG                                 0x10
2772 #define PALMAS_INT3_MASK_ID_OTG_SHIFT                           4
2773 #define PALMAS_INT3_MASK_GPADC_EOC_RT                           0x08
2774 #define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT                     3
2775 #define PALMAS_INT3_MASK_GPADC_EOC_SW                           0x04
2776 #define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT                     2
2777 #define PALMAS_INT3_MASK_GPADC_AUTO_1                           0x02
2778 #define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT                     1
2779 #define PALMAS_INT3_MASK_GPADC_AUTO_0                           0x01
2780 #define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT                     0
2781
2782 /* Bit definitions for INT3_LINE_STATE */
2783 #define PALMAS_INT3_LINE_STATE_VBUS                             0x80
2784 #define PALMAS_INT3_LINE_STATE_VBUS_SHIFT                       7
2785 #define PALMAS_INT3_LINE_STATE_VBUS_OTG                         0x40
2786 #define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT                   6
2787 #define PALMAS_INT3_LINE_STATE_ID                               0x20
2788 #define PALMAS_INT3_LINE_STATE_ID_SHIFT                         5
2789 #define PALMAS_INT3_LINE_STATE_ID_OTG                           0x10
2790 #define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT                     4
2791 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT                     0x08
2792 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT               3
2793 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW                     0x04
2794 #define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT               2
2795 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1                     0x02
2796 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT               1
2797 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0                     0x01
2798 #define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT               0
2799
2800 /* Bit definitions for INT4_STATUS */
2801 #define PALMAS_INT4_STATUS_GPIO_7                               0x80
2802 #define PALMAS_INT4_STATUS_GPIO_7_SHIFT                         7
2803 #define PALMAS_INT4_STATUS_GPIO_6                               0x40
2804 #define PALMAS_INT4_STATUS_GPIO_6_SHIFT                         6
2805 #define PALMAS_INT4_STATUS_GPIO_5                               0x20
2806 #define PALMAS_INT4_STATUS_GPIO_5_SHIFT                         5
2807 #define PALMAS_INT4_STATUS_GPIO_4                               0x10
2808 #define PALMAS_INT4_STATUS_GPIO_4_SHIFT                         4
2809 #define PALMAS_INT4_STATUS_GPIO_3                               0x08
2810 #define PALMAS_INT4_STATUS_GPIO_3_SHIFT                         3
2811 #define PALMAS_INT4_STATUS_GPIO_2                               0x04
2812 #define PALMAS_INT4_STATUS_GPIO_2_SHIFT                         2
2813 #define PALMAS_INT4_STATUS_GPIO_1                               0x02
2814 #define PALMAS_INT4_STATUS_GPIO_1_SHIFT                         1
2815 #define PALMAS_INT4_STATUS_GPIO_0                               0x01
2816 #define PALMAS_INT4_STATUS_GPIO_0_SHIFT                         0
2817
2818 /* Bit definitions for INT4_MASK */
2819 #define PALMAS_INT4_MASK_GPIO_7                                 0x80
2820 #define PALMAS_INT4_MASK_GPIO_7_SHIFT                           7
2821 #define PALMAS_INT4_MASK_GPIO_6                                 0x40
2822 #define PALMAS_INT4_MASK_GPIO_6_SHIFT                           6
2823 #define PALMAS_INT4_MASK_GPIO_5                                 0x20
2824 #define PALMAS_INT4_MASK_GPIO_5_SHIFT                           5
2825 #define PALMAS_INT4_MASK_GPIO_4                                 0x10
2826 #define PALMAS_INT4_MASK_GPIO_4_SHIFT                           4
2827 #define PALMAS_INT4_MASK_GPIO_3                                 0x08
2828 #define PALMAS_INT4_MASK_GPIO_3_SHIFT                           3
2829 #define PALMAS_INT4_MASK_GPIO_2                                 0x04
2830 #define PALMAS_INT4_MASK_GPIO_2_SHIFT                           2
2831 #define PALMAS_INT4_MASK_GPIO_1                                 0x02
2832 #define PALMAS_INT4_MASK_GPIO_1_SHIFT                           1
2833 #define PALMAS_INT4_MASK_GPIO_0                                 0x01
2834 #define PALMAS_INT4_MASK_GPIO_0_SHIFT                           0
2835
2836 /* Bit definitions for INT4_LINE_STATE */
2837 #define PALMAS_INT4_LINE_STATE_GPIO_7                           0x80
2838 #define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT                     7
2839 #define PALMAS_INT4_LINE_STATE_GPIO_6                           0x40
2840 #define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT                     6
2841 #define PALMAS_INT4_LINE_STATE_GPIO_5                           0x20
2842 #define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT                     5
2843 #define PALMAS_INT4_LINE_STATE_GPIO_4                           0x10
2844 #define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT                     4
2845 #define PALMAS_INT4_LINE_STATE_GPIO_3                           0x08
2846 #define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT                     3
2847 #define PALMAS_INT4_LINE_STATE_GPIO_2                           0x04
2848 #define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT                     2
2849 #define PALMAS_INT4_LINE_STATE_GPIO_1                           0x02
2850 #define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT                     1
2851 #define PALMAS_INT4_LINE_STATE_GPIO_0                           0x01
2852 #define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT                     0
2853
2854 /* Bit definitions for INT4_EDGE_DETECT1 */
2855 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING                  0x80
2856 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT            7
2857 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING                 0x40
2858 #define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT           6
2859 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING                  0x20
2860 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT            5
2861 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING                 0x10
2862 #define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT           4
2863 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING                  0x08
2864 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT            3
2865 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING                 0x04
2866 #define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT           2
2867 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING                  0x02
2868 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT            1
2869 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING                 0x01
2870 #define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT           0
2871
2872 /* Bit definitions for INT4_EDGE_DETECT2 */
2873 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING                  0x80
2874 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT            7
2875 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING                 0x40
2876 #define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT           6
2877 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING                  0x20
2878 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT            5
2879 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING                 0x10
2880 #define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT           4
2881 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING                  0x08
2882 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT            3
2883 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING                 0x04
2884 #define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT           2
2885 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING                  0x02
2886 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT            1
2887 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING                 0x01
2888 #define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT           0
2889
2890 /* Bit definitions for INT5_STATUS */
2891 #define PALMAS_INT5_STATUS_GPIO_15                              0x80
2892 #define PALMAS_INT5_STATUS_GPIO_15_SHIFT                        7
2893 #define PALMAS_INT5_STATUS_GPIO_14                              0x40
2894 #define PALMAS_INT5_STATUS_GPIO_14_SHIFT                        6
2895 #define PALMAS_INT5_STATUS_GPIO_13                              0x20
2896 #define PALMAS_INT5_STATUS_GPIO_13_SHIFT                        5
2897 #define PALMAS_INT5_STATUS_GPIO_12                              0x10
2898 #define PALMAS_INT5_STATUS_GPIO_12_SHIFT                        4
2899 #define PALMAS_INT5_STATUS_GPIO_11                              0x08
2900 #define PALMAS_INT5_STATUS_GPIO_11_SHIFT                        3
2901 #define PALMAS_INT5_STATUS_GPIO_10                              0x04
2902 #define PALMAS_INT5_STATUS_GPIO_10_SHIFT                        2
2903 #define PALMAS_INT5_STATUS_GPIO_9                               0x02
2904 #define PALMAS_INT5_STATUS_GPIO_9_SHIFT                         1
2905 #define PALMAS_INT5_STATUS_GPIO_8                               0x01
2906 #define PALMAS_INT5_STATUS_GPIO_8_SHIFT                         0
2907
2908 /* Bit definitions for INT5_MASK */
2909 #define PALMAS_INT5_MASK_GPIO_15                                0x80
2910 #define PALMAS_INT5_MASK_GPIO_15_SHIFT                          7
2911 #define PALMAS_INT5_MASK_GPIO_14                                0x40
2912 #define PALMAS_INT5_MASK_GPIO_14_SHIFT                          6
2913 #define PALMAS_INT5_MASK_GPIO_13                                0x20
2914 #define PALMAS_INT5_MASK_GPIO_13_SHIFT                          5
2915 #define PALMAS_INT5_MASK_GPIO_12                                0x10
2916 #define PALMAS_INT5_MASK_GPIO_12_SHIFT                          4
2917 #define PALMAS_INT5_MASK_GPIO_11                                0x08
2918 #define PALMAS_INT5_MASK_GPIO_11_SHIFT                          3
2919 #define PALMAS_INT5_MASK_GPIO_10                                0x04
2920 #define PALMAS_INT5_MASK_GPIO_10_SHIFT                          2
2921 #define PALMAS_INT5_MASK_GPIO_9                                 0x02
2922 #define PALMAS_INT5_MASK_GPIO_9_SHIFT                           1
2923 #define PALMAS_INT5_MASK_GPIO_8                                 0x01
2924 #define PALMAS_INT5_MASK_GPIO_8_SHIFT                           0
2925
2926 /* Bit definitions for INT5_LINE_STATE */
2927 #define PALMAS_INT5_LINE_STATE_GPIO_15                          0x80
2928 #define PALMAS_INT5_LINE_STATE_GPIO_15_SHIFT                    7
2929 #define PALMAS_INT5_LINE_STATE_GPIO_14                          0x40
2930 #define PALMAS_INT5_LINE_STATE_GPIO_14_SHIFT                    6
2931 #define PALMAS_INT5_LINE_STATE_GPIO_13                          0x20
2932 #define PALMAS_INT5_LINE_STATE_GPIO_13_SHIFT                    5
2933 #define PALMAS_INT5_LINE_STATE_GPIO_12                          0x10
2934 #define PALMAS_INT5_LINE_STATE_GPIO_12_SHIFT                    4
2935 #define PALMAS_INT5_LINE_STATE_GPIO_11                          0x08
2936 #define PALMAS_INT5_LINE_STATE_GPIO_11_SHIFT                    3
2937 #define PALMAS_INT5_LINE_STATE_GPIO_10                          0x04
2938 #define PALMAS_INT5_LINE_STATE_GPIO_10_SHIFT                    2
2939 #define PALMAS_INT5_LINE_STATE_GPIO_9                           0x02
2940 #define PALMAS_INT5_LINE_STATE_GPIO_9_SHIFT                     1
2941 #define PALMAS_INT5_LINE_STATE_GPIO_8                           0x01
2942 #define PALMAS_INT5_LINE_STATE_GPIO_8_SHIFT                     0
2943
2944 /* Bit definitions for INT5_EDGE_DETECT1 */
2945 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_RISING                 0x80
2946 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_RISING_SHIFT           7
2947 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_FALLING                0x40
2948 #define PALMAS_INT5_EDGE_DETECT1_GPIO_11_FALLING_SHIFT          6
2949 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_RISING                 0x20
2950 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_RISING_SHIFT           5
2951 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_FALLING                0x10
2952 #define PALMAS_INT5_EDGE_DETECT1_GPIO_10_FALLING_SHIFT          4
2953 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_RISING                  0x08
2954 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_RISING_SHIFT            3
2955 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_FALLING                 0x04
2956 #define PALMAS_INT5_EDGE_DETECT1_GPIO_9_FALLING_SHIFT           2
2957 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_RISING                  0x02
2958 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_RISING_SHIFT            1
2959 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_FALLING                 0x01
2960 #define PALMAS_INT5_EDGE_DETECT1_GPIO_8_FALLING_SHIFT           0
2961
2962 /* Bit definitions for INT5_EDGE_DETECT2 */
2963 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_RISING                 0x80
2964 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_RISING_SHIFT           7
2965 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_FALLING                0x40
2966 #define PALMAS_INT5_EDGE_DETECT2_GPIO_15_FALLING_SHIFT          6
2967 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_RISING                 0x20
2968 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_RISING_SHIFT           5
2969 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_FALLING                0x10
2970 #define PALMAS_INT5_EDGE_DETECT2_GPIO_14_FALLING_SHIFT          4
2971 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_RISING                 0x08
2972 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_RISING_SHIFT           3
2973 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_FALLING                0x04
2974 #define PALMAS_INT5_EDGE_DETECT2_GPIO_13_FALLING_SHIFT          2
2975 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_RISING                 0x02
2976 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_RISING_SHIFT           1
2977 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_FALLING                0x01
2978 #define PALMAS_INT5_EDGE_DETECT2_GPIO_12_FALLING_SHIFT          0
2979
2980 /* Bit definitions for INT_CTRL */
2981 #define PALMAS_INT_CTRL_INT_PENDING                             0x04
2982 #define PALMAS_INT_CTRL_INT_PENDING_SHIFT                       2
2983 #define PALMAS_INT_CTRL_INT_CLEAR                               0x01
2984 #define PALMAS_INT_CTRL_INT_CLEAR_SHIFT                         0
2985
2986 /* Bit definitions for INT6_STATUS */
2987 #define PALMAS_INT6_STATUS_SIM2                                 0x80
2988 #define PALMAS_INT6_STATUS_SIM2_SHIFT                           7
2989 #define PALMAS_INT6_STATUS_SIM1                                 0x40
2990 #define PALMAS_INT6_STATUS_SIM1_SHIFT                           6
2991 #define PALMAS_INT6_STATUS_CHARGER                              0x20
2992 #define PALMAS_INT6_STATUS_CHARGER_SHIFT                        5
2993 #define PALMAS_INT6_STATUS_CC_AUTOCAL                           0x10
2994 #define PALMAS_INT6_STATUS_CC_AUTOCAL_SHIFT                     4
2995 #define PALMAS_INT6_STATUS_CC_BAT_STABLE                        0x08
2996 #define PALMAS_INT6_STATUS_CC_BAT_STABLE_SHIFT                  3
2997 #define PALMAS_INT6_STATUS_CC_OVC_LIMIT                         0x04
2998 #define PALMAS_INT6_STATUS_CC_OVC_LIMIT_SHIFT                   2
2999 #define PALMAS_INT6_STATUS_CC_SYNC_EOC                          0x02
3000 #define PALMAS_INT6_STATUS_CC_SYNC_EOC_SHIFT                    1
3001 #define PALMAS_INT6_STATUS_CC_EOC                               0x01
3002 #define PALMAS_INT6_STATUS_CC_EOC_SHIFT                         0
3003
3004 /* Bit definitions for INT6_MASK */
3005 #define PALMAS_INT6_MASK_SIM2                                   0x80
3006 #define PALMAS_INT6_MASK_SIM2_SHIFT                             7
3007 #define PALMAS_INT6_MASK_SIM1                                   0x40
3008 #define PALMAS_INT6_MASK_SIM1_SHIFT                             6
3009 #define PALMAS_INT6_MASK_CHARGER                                0x20
3010 #define PALMAS_INT6_MASK_CHARGER_SHIFT                          5
3011 #define PALMAS_INT6_MASK_CC_AUTOCAL                             0x10
3012 #define PALMAS_INT6_MASK_CC_AUTOCAL_SHIFT                       4
3013 #define PALMAS_INT6_MASK_CC_BAT_STABLE                          0x08
3014 #define PALMAS_INT6_MASK_CC_BAT_STABLE_SHIFT                    3
3015 #define PALMAS_INT6_MASK_CC_OVC_LIMIT                           0x04
3016 #define PALMAS_INT6_MASK_CC_OVC_LIMIT_SHIFT                     2
3017 #define PALMAS_INT6_MASK_CC_SYNC_EOC                            0x02
3018 #define PALMAS_INT6_MASK_CC_SYNC_EOC_SHIFT                      1
3019 #define PALMAS_INT6_MASK_CC_EOC                                 0x01
3020 #define PALMAS_INT6_MASK_CC_EOC_SHIFT                           0
3021
3022 /* Bit definitions for INT6_LINE_STATE */
3023 #define PALMAS_INT6_LINE_STATE_SIM2                             0x80
3024 #define PALMAS_INT6_LINE_STATE_SIM2_SHIFT                       7
3025 #define PALMAS_INT6_LINE_STATE_SIM1                             0x40
3026 #define PALMAS_INT6_LINE_STATE_SIM1_SHIFT                       6
3027 #define PALMAS_INT6_LINE_STATE_CHARGER                          0x20
3028 #define PALMAS_INT6_LINE_STATE_CHARGER_SHIFT                    5
3029 #define PALMAS_INT6_LINE_STATE_CC_AUTOCAL                       0x10
3030 #define PALMAS_INT6_LINE_STATE_CC_AUTOCAL_SHIFT                 4
3031 #define PALMAS_INT6_LINE_STATE_CC_BAT_STABLE                    0x08
3032 #define PALMAS_INT6_LINE_STATE_CC_BAT_STABLE_SHIFT              3
3033 #define PALMAS_INT6_LINE_STATE_CC_OVC_LIMIT                     0x04
3034 #define PALMAS_INT6_LINE_STATE_CC_OVC_LIMIT_SHIFT               2
3035 #define PALMAS_INT6_LINE_STATE_CC_SYNC_EOC                      0x02
3036 #define PALMAS_INT6_LINE_STATE_CC_SYNC_EOC_SHIFT                1
3037 #define PALMAS_INT6_LINE_STATE_CC_EOC                           0x01
3038 #define PALMAS_INT6_LINE_STATE_CC_EOC_SHIFT                     0
3039
3040 /* Registers for function USB_OTG */
3041 #define PALMAS_USB_WAKEUP                                       0x3
3042 #define PALMAS_USB_VBUS_CTRL_SET                                0x4
3043 #define PALMAS_USB_VBUS_CTRL_CLR                                0x5
3044 #define PALMAS_USB_ID_CTRL_SET                                  0x6
3045 #define PALMAS_USB_ID_CTRL_CLEAR                                0x7
3046 #define PALMAS_USB_VBUS_INT_SRC                                 0x8
3047 #define PALMAS_USB_VBUS_INT_LATCH_SET                           0x9
3048 #define PALMAS_USB_VBUS_INT_LATCH_CLR                           0xA
3049 #define PALMAS_USB_VBUS_INT_EN_LO_SET                           0xB
3050 #define PALMAS_USB_VBUS_INT_EN_LO_CLR                           0xC
3051 #define PALMAS_USB_VBUS_INT_EN_HI_SET                           0xD
3052 #define PALMAS_USB_VBUS_INT_EN_HI_CLR                           0xE
3053 #define PALMAS_USB_ID_INT_SRC                                   0xF
3054 #define PALMAS_USB_ID_INT_LATCH_SET                             0x10
3055 #define PALMAS_USB_ID_INT_LATCH_CLR                             0x11
3056 #define PALMAS_USB_ID_INT_EN_LO_SET                             0x12
3057 #define PALMAS_USB_ID_INT_EN_LO_CLR                             0x13
3058 #define PALMAS_USB_ID_INT_EN_HI_SET                             0x14
3059 #define PALMAS_USB_ID_INT_EN_HI_CLR                             0x15
3060 #define PALMAS_USB_OTG_ADP_CTRL                                 0x16
3061 #define PALMAS_USB_OTG_ADP_HIGH                                 0x17
3062 #define PALMAS_USB_OTG_ADP_LOW                                  0x18
3063 #define PALMAS_USB_OTG_ADP_RISE                                 0x19
3064 #define PALMAS_USB_OTG_REVISION                                 0x1A
3065
3066 /* Bit definitions for USB_WAKEUP */
3067 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP                         0x01
3068 #define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT                   0
3069
3070 /* Bit definitions for USB_VBUS_CTRL_SET */
3071 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS                 0x80
3072 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT           7
3073 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG                   0x20
3074 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT             5
3075 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC                  0x10
3076 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT            4
3077 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK                 0x08
3078 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT           3
3079 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP                  0x04
3080 #define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT            2
3081
3082 /* Bit definitions for USB_VBUS_CTRL_CLR */
3083 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS                 0x80
3084 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT           7
3085 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG                   0x20
3086 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT             5
3087 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC                  0x10
3088 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT            4
3089 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK                 0x08
3090 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT           3
3091 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP                  0x04
3092 #define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT            2
3093
3094 /* Bit definitions for USB_ID_CTRL_SET */
3095 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K                       0x80
3096 #define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT                 7
3097 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K                       0x40
3098 #define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT                 6
3099 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV                       0x20
3100 #define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT                 5
3101 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U                       0x10
3102 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT                 4
3103 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U                        0x08
3104 #define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT                  3
3105 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP                      0x04
3106 #define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT                2
3107
3108 /* Bit definitions for USB_ID_CTRL_CLEAR */
3109 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K                     0x80
3110 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT               7
3111 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K                     0x40
3112 #define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT               6
3113 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV                     0x20
3114 #define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT               5
3115 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U                     0x10
3116 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT               4
3117 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U                      0x08
3118 #define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT                3
3119 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP                    0x04
3120 #define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT              2
3121
3122 /* Bit definitions for USB_VBUS_INT_SRC */
3123 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD                   0x80
3124 #define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT             7
3125 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB                        0x40
3126 #define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT                  6
3127 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS                        0x20
3128 #define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT                  5
3129 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD                     0x08
3130 #define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT               3
3131 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD                     0x04
3132 #define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT               2
3133 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD                     0x02
3134 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT               1
3135 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END                     0x01
3136 #define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT               0
3137
3138 /* Bit definitions for USB_VBUS_INT_LATCH_SET */
3139 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD             0x80
3140 #define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT       7
3141 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB                  0x40
3142 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT            6
3143 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS                  0x20
3144 #define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT            5
3145 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP                       0x10
3146 #define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT                 4
3147 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD               0x08
3148 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT         3
3149 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD               0x04
3150 #define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT         2
3151 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD               0x02
3152 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT         1
3153 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END               0x01
3154 #define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT         0
3155
3156 /* Bit definitions for USB_VBUS_INT_LATCH_CLR */
3157 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD             0x80
3158 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT       7
3159 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB                  0x40
3160 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT            6
3161 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS                  0x20
3162 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT            5
3163 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP                       0x10
3164 #define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT                 4
3165 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD               0x08
3166 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT         3
3167 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD               0x04
3168 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT         2
3169 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD               0x02
3170 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT         1
3171 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END               0x01
3172 #define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT         0
3173
3174 /* Bit definitions for USB_VBUS_INT_EN_LO_SET */
3175 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD             0x80
3176 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT       7
3177 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB                  0x40
3178 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT            6
3179 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS                  0x20
3180 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT            5
3181 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD               0x08
3182 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT         3
3183 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD               0x04
3184 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT         2
3185 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD               0x02
3186 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT         1
3187 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END               0x01
3188 #define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT         0
3189
3190 /* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
3191 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD             0x80
3192 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT       7
3193 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB                  0x40
3194 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT            6
3195 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS                  0x20
3196 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT            5
3197 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD               0x08
3198 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT         3
3199 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD               0x04
3200 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT         2
3201 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD               0x02
3202 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT         1
3203 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END               0x01
3204 #define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT         0
3205
3206 /* Bit definitions for USB_VBUS_INT_EN_HI_SET */
3207 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD             0x80
3208 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT       7
3209 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB                  0x40
3210 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT            6
3211 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS                  0x20
3212 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT            5
3213 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP                       0x10
3214 #define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT                 4
3215 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD               0x08
3216 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT         3
3217 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD               0x04
3218 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT         2
3219 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD               0x02
3220 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT         1
3221 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END               0x01
3222 #define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT         0
3223
3224 /* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
3225 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD             0x80
3226 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT       7
3227 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB                  0x40
3228 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT            6
3229 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS                  0x20
3230 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT            5
3231 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP                       0x10
3232 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT                 4
3233 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD               0x08
3234 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT         3
3235 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD               0x04
3236 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT         2
3237 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD               0x02
3238 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT         1
3239 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END               0x01
3240 #define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT         0
3241
3242 /* Bit definitions for USB_ID_INT_SRC */
3243 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT                          0x10
3244 #define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT                    4
3245 #define PALMAS_USB_ID_INT_SRC_ID_A                              0x08
3246 #define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT                        3
3247 #define PALMAS_USB_ID_INT_SRC_ID_B                              0x04
3248 #define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT                        2
3249 #define PALMAS_USB_ID_INT_SRC_ID_C                              0x02
3250 #define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT                        1
3251 #define PALMAS_USB_ID_INT_SRC_ID_GND                            0x01
3252 #define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT                      0
3253
3254 /* Bit definitions for USB_ID_INT_LATCH_SET */
3255 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT                    0x10
3256 #define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT              4
3257 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A                        0x08
3258 #define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT                  3
3259 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B                        0x04
3260 #define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT                  2
3261 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C                        0x02
3262 #define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT                  1
3263 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND                      0x01
3264 #define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT                0
3265
3266 /* Bit definitions for USB_ID_INT_LATCH_CLR */
3267 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT                    0x10
3268 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT              4
3269 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A                        0x08
3270 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT                  3
3271 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B                        0x04
3272 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT                  2
3273 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C                        0x02
3274 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT                  1
3275 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND                      0x01
3276 #define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT                0
3277
3278 /* Bit definitions for USB_ID_INT_EN_LO_SET */
3279 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT                    0x10
3280 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT              4
3281 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A                        0x08
3282 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT                  3
3283 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B                        0x04
3284 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT                  2
3285 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C                        0x02
3286 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT                  1
3287 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND                      0x01
3288 #define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT                0
3289
3290 /* Bit definitions for USB_ID_INT_EN_LO_CLR */
3291 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT                    0x10
3292 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT              4
3293 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A                        0x08
3294 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT                  3
3295 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B                        0x04
3296 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT                  2
3297 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C                        0x02
3298 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT                  1
3299 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND                      0x01
3300 #define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT                0
3301
3302 /* Bit definitions for USB_ID_INT_EN_HI_SET */
3303 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT                    0x10
3304 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT              4
3305 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A                        0x08
3306 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT                  3
3307 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B                        0x04
3308 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT                  2
3309 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C                        0x02
3310 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT                  1
3311 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND                      0x01
3312 #define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT                0
3313
3314 /* Bit definitions for USB_ID_INT_EN_HI_CLR */
3315 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT                    0x10
3316 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT              4
3317 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A                        0x08
3318 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT                  3
3319 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B                        0x04
3320 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT                  2
3321 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C                        0x02
3322 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT                  1
3323 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND                      0x01
3324 #define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT                0
3325
3326 /* Bit definitions for USB_OTG_ADP_CTRL */
3327 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN                          0x04
3328 #define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT                    2
3329 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK                   0x03
3330 #define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT                  0
3331
3332 /* Bit definitions for USB_OTG_ADP_HIGH */
3333 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK                 0xff
3334 #define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT                0
3335
3336 /* Bit definitions for USB_OTG_ADP_LOW */
3337 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK                   0xff
3338 #define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT                  0
3339
3340 /* Bit definitions for USB_OTG_ADP_RISE */
3341 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK                 0xff
3342 #define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT                0
3343
3344 /* Bit definitions for USB_OTG_REVISION */
3345 #define PALMAS_USB_OTG_REVISION_OTG_REV                         0x01
3346 #define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT                   0
3347
3348 /* Registers for function VIBRATOR */
3349 #define PALMAS_VIBRA_CTRL                                       0x0
3350
3351 /* Bit definitions for VIBRA_CTRL */
3352 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK                     0x06
3353 #define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT                    1
3354 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL                          0x01
3355 #define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT                    0
3356
3357 /* Registers for function GPIO */
3358 #define PALMAS_GPIO_DATA_IN                                     0x0
3359 #define PALMAS_GPIO_DATA_DIR                                    0x1
3360 #define PALMAS_GPIO_DATA_OUT                                    0x2
3361 #define PALMAS_GPIO_DEBOUNCE_EN                                 0x3
3362 #define PALMAS_GPIO_CLEAR_DATA_OUT                              0x4
3363 #define PALMAS_GPIO_SET_DATA_OUT                                0x5
3364 #define PALMAS_PU_PD_GPIO_CTRL1                                 0x6
3365 #define PALMAS_PU_PD_GPIO_CTRL2                                 0x7
3366 #define PALMAS_OD_OUTPUT_GPIO_CTRL                              0x8
3367 #define PALMAS_GPIO_DATA_IN2                                    0x9
3368 #define PALMAS_GPIO_DATA_DIR2                                   0x0A
3369 #define PALMAS_GPIO_DATA_OUT2                                   0x0B
3370 #define PALMAS_GPIO_DEBOUNCE_EN2                                0x0C
3371 #define PALMAS_GPIO_CLEAR_DATA_OUT2                             0x0D
3372 #define PALMAS_GPIO_SET_DATA_OUT2                               0x0E
3373 #define PALMAS_PU_PD_GPIO_CTRL3                                 0x0F
3374 #define PALMAS_PU_PD_GPIO_CTRL4                                 0x10
3375 #define PALMAS_OD_OUTPUT_GPIO_CTRL2                             0x11
3376
3377 /* Bit definitions for GPIO_DATA_IN */
3378 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN                           0x80
3379 #define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT                     7
3380 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN                           0x40
3381 #define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT                     6
3382 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN                           0x20
3383 #define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT                     5
3384 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN                           0x10
3385 #define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT                     4
3386 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN                           0x08
3387 #define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT                     3
3388 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN                           0x04
3389 #define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT                     2
3390 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN                           0x02
3391 #define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT                     1
3392 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN                           0x01
3393 #define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT                     0
3394
3395 /* Bit definitions for GPIO_DATA_DIR */
3396 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR                         0x80
3397 #define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT                   7
3398 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR                         0x40
3399 #define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT                   6
3400 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR                         0x20
3401 #define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT                   5
3402 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR                         0x10
3403 #define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT                   4
3404 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR                         0x08
3405 #define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT                   3
3406 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR                         0x04
3407 #define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT                   2
3408 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR                         0x02
3409 #define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT                   1
3410 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR                         0x01
3411 #define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT                   0
3412
3413 /* Bit definitions for GPIO_DATA_OUT */
3414 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT                         0x80
3415 #define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT                   7
3416 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT                         0x40
3417 #define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT                   6
3418 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT                         0x20
3419 #define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT                   5
3420 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT                         0x10
3421 #define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT                   4
3422 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT                         0x08
3423 #define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT                   3
3424 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT                         0x04
3425 #define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT                   2
3426 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT                         0x02
3427 #define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT                   1
3428 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT                         0x01
3429 #define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT                   0
3430
3431 /* Bit definitions for GPIO_DEBOUNCE_EN */
3432 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN              0x80
3433 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT        7
3434 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN              0x40
3435 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT        6
3436 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN              0x20
3437 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT        5
3438 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN              0x10
3439 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT        4
3440 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN              0x08
3441 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT        3
3442 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN              0x04
3443 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT        2
3444 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN              0x02
3445 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT        1
3446 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN              0x01
3447 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT        0
3448
3449 /* Bit definitions for GPIO_CLEAR_DATA_OUT */
3450 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT        0x80
3451 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT  7
3452 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT        0x40
3453 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT  6
3454 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT        0x20
3455 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT  5
3456 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT        0x10
3457 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT  4
3458 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT        0x08
3459 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT  3
3460 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT        0x04
3461 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT  2
3462 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT        0x02
3463 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT  1
3464 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT        0x01
3465 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT  0
3466
3467 /* Bit definitions for GPIO_SET_DATA_OUT */
3468 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT            0x80
3469 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT      7
3470 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT            0x40
3471 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT      6
3472 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT            0x20
3473 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT      5
3474 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT            0x10
3475 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT      4
3476 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT            0x08
3477 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT      3
3478 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT            0x04
3479 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT      2
3480 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT            0x02
3481 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT      1
3482 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT            0x01
3483 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT      0
3484
3485 /* Bit definitions for PU_PD_GPIO_CTRL1 */
3486 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD                       0x40
3487 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT                 6
3488 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU                       0x20
3489 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT                 5
3490 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD                       0x10
3491 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT                 4
3492 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU                       0x08
3493 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT                 3
3494 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD                       0x04
3495 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT                 2
3496 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD                       0x01
3497 #define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT                 0
3498
3499 /* Bit definitions for PU_PD_GPIO_CTRL2 */
3500 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD                       0x40
3501 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT                 6
3502 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU                       0x20
3503 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT                 5
3504 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD                       0x10
3505 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT                 4
3506 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU                       0x08
3507 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT                 3
3508 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD                       0x04
3509 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT                 2
3510 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU                       0x02
3511 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT                 1
3512 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD                       0x01
3513 #define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT                 0
3514
3515 /* Bit definitions for OD_OUTPUT_GPIO_CTRL */
3516 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD                    0x20
3517 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT              5
3518 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD                    0x04
3519 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT              2
3520 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD                    0x02
3521 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT              1
3522
3523 /* Bit definitions for GPIO_DATA_IN2 */
3524 #define PALMAS_GPIO_DATA_IN_GPIO_15_IN                          0x80
3525 #define PALMAS_GPIO_DATA_IN_GPIO_15_IN_SHIFT                    7
3526 #define PALMAS_GPIO_DATA_IN_GPIO_14_IN                          0x40
3527 #define PALMAS_GPIO_DATA_IN_GPIO_14_IN_SHIFT                    6
3528 #define PALMAS_GPIO_DATA_IN_GPIO_13_IN                          0x20
3529 #define PALMAS_GPIO_DATA_IN_GPIO_13_IN_SHIFT                    5
3530 #define PALMAS_GPIO_DATA_IN_GPIO_12_IN                          0x10
3531 #define PALMAS_GPIO_DATA_IN_GPIO_12_IN_SHIFT                    4
3532 #define PALMAS_GPIO_DATA_IN_GPIO_11_IN                          0x08
3533 #define PALMAS_GPIO_DATA_IN_GPIO_11_IN_SHIFT                    3
3534 #define PALMAS_GPIO_DATA_IN_GPIO_10_IN                          0x04
3535 #define PALMAS_GPIO_DATA_IN_GPIO_10_IN_SHIFT                    2
3536 #define PALMAS_GPIO_DATA_IN_GPIO_9_IN                           0x02
3537 #define PALMAS_GPIO_DATA_IN_GPIO_9_IN_SHIFT                     1
3538 #define PALMAS_GPIO_DATA_IN_GPIO_8_IN                           0x01
3539 #define PALMAS_GPIO_DATA_IN_GPIO_8_IN_SHIFT                     0
3540
3541 /* Bit definitions for GPIO_DATA_DIR2 */
3542 #define PALMAS_GPIO_DATA_DIR_GPIO_15_DIR                        0x80
3543 #define PALMAS_GPIO_DATA_DIR_GPIO_15_DIR_SHIFT                  7
3544 #define PALMAS_GPIO_DATA_DIR_GPIO_14_DIR                        0x40
3545 #define PALMAS_GPIO_DATA_DIR_GPIO_14_DIR_SHIFT                  6
3546 #define PALMAS_GPIO_DATA_DIR_GPIO_13_DIR                        0x20
3547 #define PALMAS_GPIO_DATA_DIR_GPIO_13_DIR_SHIFT                  5
3548 #define PALMAS_GPIO_DATA_DIR_GPIO_12_DIR                        0x10
3549 #define PALMAS_GPIO_DATA_DIR_GPIO_12_DIR_SHIFT                  4
3550 #define PALMAS_GPIO_DATA_DIR_GPIO_11_DIR                        0x08
3551 #define PALMAS_GPIO_DATA_DIR_GPIO_11_DIR_SHIFT                  3
3552 #define PALMAS_GPIO_DATA_DIR_GPIO_10_DIR                        0x04
3553 #define PALMAS_GPIO_DATA_DIR_GPIO_10_DIR_SHIFT                  2
3554 #define PALMAS_GPIO_DATA_DIR_GPIO_9_DIR                         0x02
3555 #define PALMAS_GPIO_DATA_DIR_GPIO_9_DIR_SHIFT                   1
3556 #define PALMAS_GPIO_DATA_DIR_GPIO_8_DIR                         0x01
3557 #define PALMAS_GPIO_DATA_DIR_GPIO_8_DIR_SHIFT                   0
3558
3559 /* Bit definitions for GPIO_DATA_OUT2 */
3560 #define PALMAS_GPIO_DATA_OUT_GPIO_15_OUT                        0x80
3561 #define PALMAS_GPIO_DATA_OUT_GPIO_15_OUT_SHIFT                  7
3562 #define PALMAS_GPIO_DATA_OUT_GPIO_14_OUT                        0x40
3563 #define PALMAS_GPIO_DATA_OUT_GPIO_14_OUT_SHIFT                  6
3564 #define PALMAS_GPIO_DATA_OUT_GPIO_13_OUT                        0x20
3565 #define PALMAS_GPIO_DATA_OUT_GPIO_13_OUT_SHIFT                  5
3566 #define PALMAS_GPIO_DATA_OUT_GPIO_12_OUT                        0x10
3567 #define PALMAS_GPIO_DATA_OUT_GPIO_12_OUT_SHIFT                  4
3568 #define PALMAS_GPIO_DATA_OUT_GPIO_11_OUT                        0x08
3569 #define PALMAS_GPIO_DATA_OUT_GPIO_11_OUT_SHIFT                  3
3570 #define PALMAS_GPIO_DATA_OUT_GPIO_10_OUT                        0x04
3571 #define PALMAS_GPIO_DATA_OUT_GPIO_10_OUT_SHIFT                  2
3572 #define PALMAS_GPIO_DATA_OUT_GPIO_9_OUT                         0x02
3573 #define PALMAS_GPIO_DATA_OUT_GPIO_9_OUT_SHIFT                   1
3574 #define PALMAS_GPIO_DATA_OUT_GPIO_8_OUT                         0x01
3575 #define PALMAS_GPIO_DATA_OUT_GPIO_8_OUT_SHIFT                   0
3576
3577 /* Bit definitions for GPIO_DEBOUNCE_EN2 */
3578 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_15_DEBOUNCE_EN             0x80
3579 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_15_DEBOUNCE_EN_SHIFT       7
3580 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_14_DEBOUNCE_EN             0x40
3581 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_14_DEBOUNCE_EN_SHIFT       6
3582 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_13_DEBOUNCE_EN             0x20
3583 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_13_DEBOUNCE_EN_SHIFT       5
3584 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_12_DEBOUNCE_EN             0x10
3585 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_12_DEBOUNCE_EN_SHIFT       4
3586 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_11_DEBOUNCE_EN             0x08
3587 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_11_DEBOUNCE_EN_SHIFT       3
3588 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_10_DEBOUNCE_EN             0x04
3589 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_10_DEBOUNCE_EN_SHIFT       2
3590 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_9_DEBOUNCE_EN              0x02
3591 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_9_DEBOUNCE_EN_SHIFT        1
3592 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_8_DEBOUNCE_EN              0x01
3593 #define PALMAS_GPIO_DEBOUNCE_EN_GPIO_8_DEBOUNCE_EN_SHIFT        0
3594
3595 /* Bit definitions for GPIO_CLEAR_DATA_OUT2 */
3596 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_15_CLEAR_DATA_OUT       0x80
3597 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_15_CLEAR_DATA_OUT_SHIFT 7
3598 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_14_CLEAR_DATA_OUT       0x40
3599 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_14_CLEAR_DATA_OUT_SHIFT 6
3600 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_13_CLEAR_DATA_OUT       0x20
3601 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_13_CLEAR_DATA_OUT_SHIFT 5
3602 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_12_CLEAR_DATA_OUT       0x10
3603 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_12_CLEAR_DATA_OUT_SHIFT 4
3604 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_11_CLEAR_DATA_OUT       0x08
3605 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_11_CLEAR_DATA_OUT_SHIFT 3
3606 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_10_CLEAR_DATA_OUT       0x04
3607 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_10_CLEAR_DATA_OUT_SHIFT 2
3608 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_9_CLEAR_DATA_OUT        0x02
3609 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_9_CLEAR_DATA_OUT_SHIFT  1
3610 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_8_CLEAR_DATA_OUT        0x01
3611 #define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_8_CLEAR_DATA_OUT_SHIFT  0
3612
3613 /* Bit definitions for GPIO_SET_DATA_OUT2 */
3614 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_15_SET_DATA_OUT           0x80
3615 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_15_SET_DATA_OUT_SHIFT     7
3616 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_14_SET_DATA_OUT           0x40
3617 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_14_SET_DATA_OUT_SHIFT     6
3618 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_13_SET_DATA_OUT           0x20
3619 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_13_SET_DATA_OUT_SHIFT     5
3620 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_12_SET_DATA_OUT           0x10
3621 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_12_SET_DATA_OUT_SHIFT     4
3622 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_11_SET_DATA_OUT           0x08
3623 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_11_SET_DATA_OUT_SHIFT     3
3624 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_10_SET_DATA_OUT           0x04
3625 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_10_SET_DATA_OUT_SHIFT     2
3626 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_9_SET_DATA_OUT            0x02
3627 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_9_SET_DATA_OUT_SHIFT      1
3628 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_8_SET_DATA_OUT            0x01
3629 #define PALMAS_GPIO_SET_DATA_OUT_GPIO_8_SET_DATA_OUT_SHIFT      0
3630
3631 /* Bit definitions for PU_PD_GPIO_CTRL3 */
3632 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_11_PD                      0x40
3633 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_11_PD_SHIFT                6
3634 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PU                      0x20
3635 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PU_SHIFT                5
3636 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PD                      0x10
3637 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_10_PD_SHIFT                4
3638 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PU                       0x08
3639 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PU_SHIFT                 3
3640 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PD                       0x04
3641 #define PALMAS_PU_PD_GPIO_CTRL3_GPIO_9_PD_SHIFT                 2
3642
3643 /* Bit definitions for PU_PD_GPIO_CTRL4 */
3644 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PU                      0x20
3645 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PU_SHIFT                5
3646 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PD                      0x10
3647 #define PALMAS_PU_PD_GPIO_CTRL4_GPIO_14_PD_SHIFT                4
3648
3649 /* Bit definitions for OD_OUTPUT_GPIO_CTRL2 */
3650 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_10_OD                   0x04
3651 #define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_10_OD_SHIFT             2
3652
3653 /* Registers for function GPADC */
3654 #define PALMAS_GPADC_CTRL1                                      0x0
3655 #define PALMAS_GPADC_CTRL2                                      0x1
3656 #define PALMAS_GPADC_RT_CTRL                                    0x2
3657 #define PALMAS_GPADC_AUTO_CTRL                                  0x3
3658 #define PALMAS_GPADC_STATUS                                     0x4
3659 #define PALMAS_GPADC_RT_SELECT                                  0x5
3660 #define PALMAS_GPADC_RT_CONV0_LSB                               0x6
3661 #define PALMAS_GPADC_RT_CONV0_MSB                               0x7
3662 #define PALMAS_GPADC_AUTO_SELECT                                0x8
3663 #define PALMAS_GPADC_AUTO_CONV0_LSB                             0x9
3664 #define PALMAS_GPADC_AUTO_CONV0_MSB                             0xA
3665 #define PALMAS_GPADC_AUTO_CONV1_LSB                             0xB
3666 #define PALMAS_GPADC_AUTO_CONV1_MSB                             0xC
3667 #define PALMAS_GPADC_SW_SELECT                                  0xD
3668 #define PALMAS_GPADC_SW_CONV0_LSB                               0xE
3669 #define PALMAS_GPADC_SW_CONV0_MSB                               0xF
3670 #define PALMAS_GPADC_THRES_CONV0_LSB                            0x10
3671 #define PALMAS_GPADC_THRES_CONV0_MSB                            0x11
3672 #define PALMAS_GPADC_THRES_CONV1_LSB                            0x12
3673 #define PALMAS_GPADC_THRES_CONV1_MSB                            0x13
3674 #define PALMAS_GPADC_SMPS_ILMONITOR_EN                          0x14
3675 #define PALMAS_GPADC_SMPS_VSEL_MONITORING                       0x15
3676
3677 /* Bit definitions for GPADC_CTRL1 */
3678 #define PALMAS_GPADC_CTRL1_RESERVED_MASK                        0xc0
3679 #define PALMAS_GPADC_CTRL1_RESERVED_SHIFT                       6
3680 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK                 0x30
3681 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT                4
3682 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK                 0x0c
3683 #define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT                2
3684 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET                      0x02
3685 #define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT                1
3686 #define PALMAS_GPADC_CTRL1_GPADC_FORCE                          0x01
3687 #define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT                    0
3688
3689 /* Bit definitions for GPADC_CTRL2 */
3690 #define PALMAS_GPADC_CTRL2_RESERVED_MASK                        0x06
3691 #define PALMAS_GPADC_CTRL2_RESERVED_SHIFT                       1
3692
3693 /* Bit definitions for GPADC_RT_CTRL */
3694 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY                       0x02
3695 #define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT                 1
3696 #define PALMAS_GPADC_RT_CTRL_START_POLARITY                     0x01
3697 #define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT               0
3698
3699 /* Bit definitions for GPADC_AUTO_CTRL */
3700 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1                   0x80
3701 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT             7
3702 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0                   0x40
3703 #define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT             6
3704 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN                    0x20
3705 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT              5
3706 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN                    0x10
3707 #define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT              4
3708 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK                0x0f
3709 #define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT               0
3710
3711 /* Bit definitions for GPADC_STATUS */
3712 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE                     0x10
3713 #define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT               4
3714
3715 /* Bit definitions for GPADC_RT_SELECT */
3716 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN                       0x80
3717 #define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT                 7
3718 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK                0x0f
3719 #define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT               0
3720
3721 /* Bit definitions for GPADC_RT_CONV0_LSB */
3722 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK             0xff
3723 #define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT            0
3724
3725 /* Bit definitions for GPADC_RT_CONV0_MSB */
3726 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK             0x0f
3727 #define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT            0
3728
3729 /* Bit definitions for GPADC_AUTO_SELECT */
3730 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK            0xf0
3731 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT           4
3732 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK            0x0f
3733 #define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT           0
3734
3735 /* Bit definitions for GPADC_AUTO_CONV0_LSB */
3736 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK         0xff
3737 #define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT        0
3738
3739 /* Bit definitions for GPADC_AUTO_CONV0_MSB */
3740 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK         0x0f
3741 #define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT        0
3742
3743 /* Bit definitions for GPADC_AUTO_CONV1_LSB */
3744 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK         0xff
3745 #define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT        0
3746
3747 /* Bit definitions for GPADC_AUTO_CONV1_MSB */
3748 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK         0x0f
3749 #define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT        0
3750
3751 /* Bit definitions for GPADC_SW_SELECT */
3752 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN                       0x80
3753 #define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT                 7
3754 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0                   0x10
3755 #define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT             4
3756 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK                0x0f
3757 #define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT               0
3758
3759 /* Bit definitions for GPADC_SW_CONV0_LSB */
3760 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK             0xff
3761 #define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT            0
3762
3763 /* Bit definitions for GPADC_SW_CONV0_MSB */
3764 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK             0x0f
3765 #define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT            0
3766
3767 /* Bit definitions for GPADC_THRES_CONV0_LSB */
3768 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK       0xff
3769 #define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT      0
3770
3771 /* Bit definitions for GPADC_THRES_CONV0_MSB */
3772 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL            0x80
3773 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT      7
3774 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK       0x0f
3775 #define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT      0
3776
3777 /* Bit definitions for GPADC_THRES_CONV1_LSB */
3778 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK       0xff
3779 #define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT      0
3780
3781 /* Bit definitions for GPADC_THRES_CONV1_MSB */
3782 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL            0x80
3783 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT      7
3784 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK       0x0f
3785 #define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT      0
3786
3787 /* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
3788 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN            0x20
3789 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT      5
3790 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT          0x10
3791 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT    4
3792 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK      0x0f
3793 #define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT     0
3794
3795 /* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
3796 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE          0x80
3797 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT    7
3798 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK     0x7f
3799 #define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT    0
3800
3801 #define PALMAS_INTERNAL_DESIGNREV                               0x57
3802 #define PALMAS_INTERNAL_DESIGNREV_DESIGNREV(val)                ((val) & 0xF)
3803
3804 /* Registers for function GPADC */
3805 #define PALMAS_GPADC_TRIM1                                      0x0
3806 #define PALMAS_GPADC_TRIM2                                      0x1
3807 #define PALMAS_GPADC_TRIM3                                      0x2
3808 #define PALMAS_GPADC_TRIM4                                      0x3
3809 #define PALMAS_GPADC_TRIM5                                      0x4
3810 #define PALMAS_GPADC_TRIM6                                      0x5
3811 #define PALMAS_GPADC_TRIM7                                      0x6
3812 #define PALMAS_GPADC_TRIM8                                      0x7
3813 #define PALMAS_GPADC_TRIM9                                      0x8
3814 #define PALMAS_GPADC_TRIM10                                     0x9
3815 #define PALMAS_GPADC_TRIM11                                     0xA
3816 #define PALMAS_GPADC_TRIM12                                     0xB
3817 #define PALMAS_GPADC_TRIM13                                     0xC
3818 #define PALMAS_GPADC_TRIM14                                     0xD
3819 #define PALMAS_GPADC_TRIM15                                     0xE
3820 #define PALMAS_GPADC_TRIM16                                     0xF
3821 #define PALMAS_GPADC_TRIMINVALID                                -1
3822
3823 /* Registers for function BQ24192 */
3824 #define PALMAS_CHARGER_REG00                                    0x00
3825 #define PALMAS_CHARGER_REG01                                    0x01
3826 #define PALMAS_CHARGER_REG02                                    0x02
3827 #define PALMAS_CHARGER_REG03                                    0x03
3828 #define PALMAS_CHARGER_REG04                                    0x04
3829 #define PALMAS_CHARGER_REG05                                    0x05
3830 #define PALMAS_CHARGER_REG06                                    0x06
3831 #define PALMAS_CHARGER_REG07                                    0x07
3832 #define PALMAS_CHARGER_REG08                                    0x08
3833 #define PALMAS_CHARGER_REG09                                    0x09
3834 #define PALMAS_CHARGER_REG10                                    0x0a
3835
3836 #define BQ24190_IC_VER                  0x40
3837 #define BQ24192_IC_VER                  0x28
3838 #define BQ24192i_IC_VER                 0x18
3839
3840 #define PALMAS_ENABLE_CHARGE_MASK      0x30
3841 #define PALMAS_DISABLE_CHARGE          0x00
3842 #define PALMAS_ENABLE_CHARGE           0x10
3843 #define PALMAS_ENABLE_VBUS             0x20
3844 #define PALMAS_DISABLE_CHARGE           0x00
3845
3846 #define PALMAS_REG0                    0x0
3847 #define PALMAS_EN_HIZ                  BIT(7)
3848
3849 #define PALMAS_CHRG_CTRL_REG_3A        0xC0
3850 #define PALMAS_OTP_CURRENT_500MA       0x32
3851
3852 #define PALMAS_WD                      0x5
3853 #define PALMAS_WD_MASK                 0x30
3854 #define PALMAS_WD_DISABLE              0x00
3855 #define PALMAS_WD_40ms                 0x10
3856 #define PALMAS_WD_80ms                 0x20
3857 #define PALMAS_WD_160ms                0x30
3858
3859 #define PALMAS_VBUS_STAT               0xc0
3860 #define PALMAS_VBUS_UNKNOWN            0x00
3861 #define PALMAS_VBUS_USB                0x40
3862 #define PALMAS_VBUS_AC                 0x80
3863
3864 #define PALMAS_CHRG_STATE_MASK                 0x30
3865 #define PALMAS_CHRG_STATE_NOTCHARGING          0x00
3866 #define PALMAS_CHRG_STATE_PRE_CHARGE           0x10
3867 #define PALMAS_CHRG_STATE_POST_CHARGE          0x20
3868 #define PALMAS_CHRG_STATE_CHARGE_DONE          0x30
3869
3870 #define PALMAS_FAULT_WATCHDOG_FAULT            BIT(7)
3871 #define PALMAS_FAULT_BOOST_FAULT               BIT(6)
3872 #define PALMAS_FAULT_CHRG_FAULT_MASK           0x30
3873 #define PALMAS_FAULT_CHRG_NORMAL               0x00
3874 #define PALMAS_FAULT_CHRG_INPUT                0x10
3875 #define PALMAS_FAULT_CHRG_THERMAL              0x20
3876 #define PALMAS_FAULT_CHRG_SAFTY                0x30
3877
3878 #define PALMAS_FAULT_NTC_FAULT                 0x07
3879
3880 #define PALMAS_CONFIG_MASK             0x7
3881 #define PALMAS_INPUT_VOLTAGE_MASK      0x78
3882 #define PALMAS_NVCHARGER_INPUT_VOL_SEL 0x40
3883 #define PALMAS_DEFAULT_INPUT_VOL_SEL   0x30
3884
3885 #define PALMAS_CHARGE_VOLTAGE_MASK              0xFC
3886 #define PALMAS_CHARGE_VOLTAGE_4112MV            0x98
3887 #define PALMAS_CHARGE_VOLTAGE_4048MV            0x88
3888
3889 #define PALMAS_MAX_REGS                (PALMAS_REVISION_REG + 1)
3890
3891 /* Registers for function FUEL_GAUGE */
3892 #define PALMAS_FG_REG_00                                      0x0
3893 #define PALMAS_FG_REG_01                                      0x1
3894 #define PALMAS_FG_REG_02                                      0x2
3895 #define PALMAS_FG_REG_03                                      0x3
3896 #define PALMAS_FG_REG_04                                      0x4
3897 #define PALMAS_FG_REG_05                                      0x5
3898 #define PALMAS_FG_REG_06                                      0x6
3899 #define PALMAS_FG_REG_07                                      0x7
3900 #define PALMAS_FG_REG_08                                      0x8
3901 #define PALMAS_FG_REG_09                                      0x9
3902 #define PALMAS_FG_REG_10                                      0xA
3903 #define PALMAS_FG_REG_11                                      0xB
3904 #define PALMAS_FG_REG_12                                      0xC
3905 #define PALMAS_FG_REG_13                                      0xD
3906 #define PALMAS_FG_REG_14                                      0xE
3907 #define PALMAS_FG_REG_15                                      0xF
3908 #define PALMAS_FG_REG_16                                      0x10
3909 #define PALMAS_FG_REG_17                                      0x11
3910 #define PALMAS_FG_REG_18                                      0x12
3911 #define PALMAS_FG_REG_19                                      0x13
3912 #define PALMAS_FG_REG_20                                      0x14
3913 #define PALMAS_FG_REG_21                                      0x15
3914 #define PALMAS_FG_REG_22                                      0x16
3915
3916 /* Bit definitions for FG_REG_00 */
3917 #define PALMAS_FG_REG_00_CC_ACTIVE_MODE_MASK                  0xc0
3918 #define PALMAS_FG_REG_00_CC_ACTIVE_MODE_SHIFT                 6
3919 #define PALMAS_FG_REG_00_CC_BAT_STABLE_EN                     0x20
3920 #define PALMAS_FG_REG_00_CC_BAT_STABLE_EN_SHIFT                       5
3921 #define PALMAS_FG_REG_00_CC_DITH_EN                           0x10
3922 #define PALMAS_FG_REG_00_CC_DITH_EN_SHIFT                     4
3923 #define PALMAS_FG_REG_00_CC_FG_EN                             0x08
3924 #define PALMAS_FG_REG_00_CC_FG_EN_SHIFT                               3
3925 #define PALMAS_FG_REG_00_CC_AUTOCLEAR                         0x04
3926 #define PALMAS_FG_REG_00_CC_AUTOCLEAR_SHIFT                   2
3927 #define PALMAS_FG_REG_00_CC_CAL_EN                            0x02
3928 #define PALMAS_FG_REG_00_CC_CAL_EN_SHIFT                      1
3929 #define PALMAS_FG_REG_00_CC_PAUSE                             0x01
3930 #define PALMAS_FG_REG_00_CC_PAUSE_SHIFT                               0
3931
3932 /* Bit definitions for FG_REG_01 */
3933 #define PALMAS_FG_REG_01_CC_SAMPLE_CNTR_MASK                  0xff
3934 #define PALMAS_FG_REG_01_CC_SAMPLE_CNTR_SHIFT                 0
3935
3936 /* Bit definitions for FG_REG_02 */
3937 #define PALMAS_FG_REG_02_CC_SAMPLE_CNTR_MASK                  0xff
3938 #define PALMAS_FG_REG_02_CC_SAMPLE_CNTR_SHIFT                 0
3939
3940 /* Bit definitions for FG_REG_03 */
3941 #define PALMAS_FG_REG_03_CC_SAMPLE_CNTR_MASK                  0xff
3942 #define PALMAS_FG_REG_03_CC_SAMPLE_CNTR_SHIFT                 0
3943
3944 /* Bit definitions for FG_REG_04 */
3945 #define PALMAS_FG_REG_04_CC_ACCUM_MASK                                0xff
3946 #define PALMAS_FG_REG_04_CC_ACCUM_SHIFT                               0
3947
3948 /* Bit definitions for FG_REG_05 */
3949 #define PALMAS_FG_REG_05_CC_ACCUM_MASK                                0xff
3950 #define PALMAS_FG_REG_05_CC_ACCUM_SHIFT                               0
3951
3952 /* Bit definitions for FG_REG_06 */
3953 #define PALMAS_FG_REG_06_CC_ACCUM_MASK                                0xff
3954 #define PALMAS_FG_REG_06_CC_ACCUM_SHIFT                               0
3955
3956 /* Bit definitions for FG_REG_07 */
3957 #define PALMAS_FG_REG_07_CC_ACCUM_MASK                                0xff
3958 #define PALMAS_FG_REG_07_CC_ACCUM_SHIFT                               0
3959
3960 /* Bit definitions for FG_REG_08 */
3961 #define PALMAS_FG_REG_08_CC_OFFSET_MASK                               0xff
3962 #define PALMAS_FG_REG_08_CC_OFFSET_SHIFT                      0
3963
3964 /* Bit definitions for FG_REG_09 */
3965 #define PALMAS_FG_REG_09_CC_OFFSET_MASK                               0x03
3966 #define PALMAS_FG_REG_09_CC_OFFSET_SHIFT                      0
3967
3968 /* Bit definitions for FG_REG_10 */
3969 #define PALMAS_FG_REG_10_CC_INTEG_MASK                                0xff
3970 #define PALMAS_FG_REG_10_CC_INTEG_SHIFT                               0
3971
3972 /* Bit definitions for FG_REG_11 */
3973 #define PALMAS_FG_REG_11_CC_INTEG_MASK                                0x3f
3974 #define PALMAS_FG_REG_11_CC_INTEG_SHIFT                               0
3975
3976 /* Bit definitions for FG_REG_12 */
3977 #define PALMAS_FG_REG_12_CC_VBAT_SYNC_MASK                    0xfc
3978 #define PALMAS_FG_REG_12_CC_VBAT_SYNC_SHIFT                   2
3979 #define PALMAS_FG_REG_12_CC_SYNC_EN                           0x02
3980 #define PALMAS_FG_REG_12_CC_SYNC_EN_SHIFT                     1
3981 #define PALMAS_FG_REG_12_CC_SYNC_RDY                          0x01
3982 #define PALMAS_FG_REG_12_CC_SYNC_RDY_SHIFT                    0
3983
3984 /* Bit definitions for FG_REG_13 */
3985 #define PALMAS_FG_REG_13_CC_VBAT_SYNC_MASK                    0x3f
3986 #define PALMAS_FG_REG_13_CC_VBAT_SYNC_SHIFT                   0
3987
3988 /* Bit definitions for FG_REG_14 */
3989 #define PALMAS_FG_REG_14_CC_VBAT_CNTR_MASK                    0xff
3990 #define PALMAS_FG_REG_14_CC_VBAT_CNTR_SHIFT                   0
3991
3992 /* Bit definitions for FG_REG_15 */
3993 #define PALMAS_FG_REG_15_CC_VBAT_CNTR_MASK                    0x03
3994 #define PALMAS_FG_REG_15_CC_VBAT_CNTR_SHIFT                   0
3995
3996 /* Bit definitions for FG_REG_16 */
3997 #define PALMAS_FG_REG_16_CC_VBAT_ACCUM_MASK                   0xff
3998 #define PALMAS_FG_REG_16_CC_VBAT_ACCUM_SHIFT                  0
3999
4000 /* Bit definitions for FG_REG_17 */
4001 #define PALMAS_FG_REG_17_CC_VBAT_ACCUM_MASK                   0xff
4002 #define PALMAS_FG_REG_17_CC_VBAT_ACCUM_SHIFT                  0
4003
4004 /* Bit definitions for FG_REG_18 */
4005 #define PALMAS_FG_REG_18_CC_VBAT_ACCUM_MASK                   0x3f
4006 #define PALMAS_FG_REG_18_CC_VBAT_ACCUM_SHIFT                  0
4007
4008 /* Bit definitions for FG_REG_19 */
4009 #define PALMAS_FG_REG_19_CC_CUR_LVL_MASK                      0x3f
4010 #define PALMAS_FG_REG_19_CC_CUR_LVL_SHIFT                     0
4011
4012 /* Bit definitions for FG_REG_20 */
4013 #define PALMAS_FG_REG_20_BAT_SLEEP_STATUS                     0x40
4014 #define PALMAS_FG_REG_20_BAT_SLEEP_STATUS_SHIFT                       6
4015 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_PERIOD_MASK             0x30
4016 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_PERIOD_SHIFT            4
4017 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_EXIT_MASK                       0x0c
4018 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_EXIT_SHIFT              2
4019 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_ENTER_MASK              0x03
4020 #define PALMAS_FG_REG_20_CC_BAT_SLEEP_ENTER_SHIFT             0
4021
4022 /* Bit definitions for FG_REG_21 */
4023 #define PALMAS_FG_REG_21_CC_OVERCUR_THRES_MASK                        0x7f
4024 #define PALMAS_FG_REG_21_CC_OVERCUR_THRES_SHIFT                       0
4025
4026 /* Bit definitions for FG_REG_22 */
4027 #define PALMAS_FG_REG_22_CC_CHOPPER_DIS                               0x80
4028 #define PALMAS_FG_REG_22_CC_CHOPPER_DIS_SHIFT                 7
4029 #define PALMAS_FG_REG_22_CC_NSLEEP_GATE                               0x08
4030 #define PALMAS_FG_REG_22_CC_NSLEEP_GATE_SHIFT                 3
4031 #define PALMAS_FG_REG_22_CC_OVC_EN                            0x04
4032 #define PALMAS_FG_REG_22_CC_OVC_EN_SHIFT                      2
4033 #define PALMAS_FG_REG_22_CC_OVC_PER_MASK                      0x03
4034 #define PALMAS_FG_REG_22_CC_OVC_PER_SHIFT                     0
4035
4036 enum {
4037         PALMAS_EXT_CONTROL_ENABLE1      = 0x1,
4038         PALMAS_EXT_CONTROL_ENABLE2      = 0x2,
4039         PALMAS_EXT_CONTROL_NSLEEP       = 0x4,
4040 };
4041
4042 /**
4043  * Palmas regulator configs
4044  * PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF: Force off on suspend
4045  * PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE: Enable tracking of regualtor.
4046  * PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE: Disable tracking in
4047                 suspend.
4048  */
4049 enum {
4050         PALMAS_REGULATOR_CONFIG_SUSPEND_FORCE_OFF               = 0x1,
4051         PALMAS_REGULATOR_CONFIG_TRACKING_ENABLE                 = 0x2,
4052         PALMAS_REGULATOR_CONFIG_SUSPEND_TRACKING_DISABLE        = 0x4,
4053 };
4054
4055 /*
4056  *PALMAS GPIOs
4057  */
4058 enum {
4059         PALMAS_GPIO0,
4060         PALMAS_GPIO1,
4061         PALMAS_GPIO2,
4062         PALMAS_GPIO3,
4063         PALMAS_GPIO4,
4064         PALMAS_GPIO5,
4065         PALMAS_GPIO6,
4066         PALMAS_GPIO7,
4067         PALMAS_GPIO8,
4068         PALMAS_GPIO9,
4069         PALMAS_GPIO10,
4070         PALMAS_GPIO11,
4071         PALMAS_GPIO12,
4072         PALMAS_GPIO13,
4073         PALMAS_GPIO14,
4074         PALMAS_GPIO15,
4075
4076         PALMAS_GPIO_NR,
4077 };
4078
4079 /* Palma GPADC Channels */
4080 enum {
4081         PALMAS_ADC_CH_IN0,
4082         PALMAS_ADC_CH_IN1,
4083         PALMAS_ADC_CH_IN2,
4084         PALMAS_ADC_CH_IN3,
4085         PALMAS_ADC_CH_IN4,
4086         PALMAS_ADC_CH_IN5,
4087         PALMAS_ADC_CH_IN6,
4088         PALMAS_ADC_CH_IN7,
4089         PALMAS_ADC_CH_IN8,
4090         PALMAS_ADC_CH_IN9,
4091         PALMAS_ADC_CH_IN10,
4092         PALMAS_ADC_CH_IN11,
4093         PALMAS_ADC_CH_IN12,
4094         PALMAS_ADC_CH_IN13,
4095         PALMAS_ADC_CH_IN14,
4096         PALMAS_ADC_CH_IN15,
4097
4098         PALMAS_ADC_CH_MAX,
4099 };
4100
4101 /* Palma Sleep requestor IDs IDs */
4102 enum {
4103         PALMAS_SLEEP_REQSTR_ID_REGEN1,
4104         PALMAS_SLEEP_REQSTR_ID_REGEN2,
4105         PALMAS_SLEEP_REQSTR_ID_SYSEN1,
4106         PALMAS_SLEEP_REQSTR_ID_SYSEN2,
4107         PALMAS_SLEEP_REQSTR_ID_CLK32KG,
4108         PALMAS_SLEEP_REQSTR_ID_CLK32KGAUDIO,
4109         PALMAS_SLEEP_REQSTR_ID_REGEN3,
4110         PALMAS_SLEEP_REQSTR_ID_SMPS12,
4111         PALMAS_SLEEP_REQSTR_ID_SMPS3,
4112         PALMAS_SLEEP_REQSTR_ID_SMPS45,
4113         PALMAS_SLEEP_REQSTR_ID_SMPS6,
4114         PALMAS_SLEEP_REQSTR_ID_SMPS7,
4115         PALMAS_SLEEP_REQSTR_ID_SMPS8,
4116         PALMAS_SLEEP_REQSTR_ID_SMPS9,
4117         PALMAS_SLEEP_REQSTR_ID_SMPS10,
4118         PALMAS_SLEEP_REQSTR_ID_LDO1,
4119         PALMAS_SLEEP_REQSTR_ID_LDO2,
4120         PALMAS_SLEEP_REQSTR_ID_LDO3,
4121         PALMAS_SLEEP_REQSTR_ID_LDO4,
4122         PALMAS_SLEEP_REQSTR_ID_LDO5,
4123         PALMAS_SLEEP_REQSTR_ID_LDO6,
4124         PALMAS_SLEEP_REQSTR_ID_LDO7,
4125         PALMAS_SLEEP_REQSTR_ID_LDO8,
4126         PALMAS_SLEEP_REQSTR_ID_LDO9,
4127         PALMAS_SLEEP_REQSTR_ID_LDOLN,
4128         PALMAS_SLEEP_REQSTR_ID_LDOUSB,
4129         PALMAS_SLEEP_REQSTR_ID_LDO10,
4130         PALMAS_SLEEP_REQSTR_ID_LDO11,
4131         PALMAS_SLEEP_REQSTR_ID_LDO12,
4132         PALMAS_SLEEP_REQSTR_ID_LDO13,
4133         PALMAS_SLEEP_REQSTR_ID_LDO14,
4134         PALMAS_SLEEP_REQSTR_ID_REGEN4,
4135         PALMAS_SLEEP_REQSTR_ID_REGEN5,
4136         PALMAS_SLEEP_REQSTR_ID_REGEN7,
4137
4138         /* Last entry */
4139         PALMAS_SLEEP_REQSTR_ID_MAX,
4140 };
4141
4142 extern int palmas_ext_power_req_config(struct palmas *palmas,
4143                 int id,  int ext_pwr_ctrl, bool enable);
4144
4145 static inline int palmas_read(struct palmas *palmas, unsigned int base,
4146                 unsigned int reg, unsigned int *val)
4147 {
4148         unsigned int addr =  PALMAS_BASE_TO_REG(base, reg);
4149         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4150
4151         return regmap_read(palmas->regmap[slave_id], addr, val);
4152 }
4153
4154 static inline int palmas_write(struct palmas *palmas, unsigned int base,
4155                 unsigned int reg, unsigned int value)
4156 {
4157         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4158         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4159
4160         return regmap_write(palmas->regmap[slave_id], addr, value);
4161 }
4162
4163 static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
4164         unsigned int reg, const void *val, size_t val_count)
4165 {
4166         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4167         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4168
4169         return regmap_bulk_write(palmas->regmap[slave_id], addr,
4170                         val, val_count);
4171 }
4172
4173 static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
4174                 unsigned int reg, void *val, size_t val_count)
4175 {
4176         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4177         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4178
4179         return regmap_bulk_read(palmas->regmap[slave_id], addr,
4180                 val, val_count);
4181 }
4182
4183 static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
4184         unsigned int reg, unsigned int mask, unsigned int val)
4185 {
4186         unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
4187         int slave_id = PALMAS_BASE_TO_SLAVE(base);
4188
4189         return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
4190 }
4191
4192 extern int palmas_irq_get_virq(struct palmas *palmas, int irq);
4193
4194 static inline int palmas_is_es_version_or_less(struct palmas *palmas,
4195         int major, int minor)
4196 {
4197         if (palmas->es_major_version < major)
4198                 return true;
4199
4200         if ((palmas->es_major_version == major) &&
4201                 (palmas->es_minor_version <= minor))
4202                 return true;
4203
4204         return false;
4205 }
4206
4207 #define PALMAS_DATASHEET_NAME(_name)    "palmas-gpadc-chan-"#_name
4208
4209 #define PALMAS_GPADC_IIO_MAP(chan, _consumer, _comsumer_channel_name)   \
4210 {                                                                       \
4211         .adc_channel_label = PALMAS_DATASHEET_NAME(chan),               \
4212         .consumer_dev_name = _consumer,                                 \
4213         .consumer_channel = _comsumer_channel_name,                     \
4214 }
4215
4216 #endif /*  __LINUX_MFD_PALMAS_H */