[PATCH] ARM: Don't try to send a signal to pid0
[linux-3.10.git] / include / asm-arm / system.h
1 #ifndef __ASM_ARM_SYSTEM_H
2 #define __ASM_ARM_SYSTEM_H
3
4 #ifdef __KERNEL__
5
6 #include <linux/config.h>
7
8 #define CPU_ARCH_UNKNOWN        0
9 #define CPU_ARCH_ARMv3          1
10 #define CPU_ARCH_ARMv4          2
11 #define CPU_ARCH_ARMv4T         3
12 #define CPU_ARCH_ARMv5          4
13 #define CPU_ARCH_ARMv5T         5
14 #define CPU_ARCH_ARMv5TE        6
15 #define CPU_ARCH_ARMv5TEJ       7
16 #define CPU_ARCH_ARMv6          8
17
18 /*
19  * CR1 bits (CP#15 CR1)
20  */
21 #define CR_M    (1 << 0)        /* MMU enable                           */
22 #define CR_A    (1 << 1)        /* Alignment abort enable               */
23 #define CR_C    (1 << 2)        /* Dcache enable                        */
24 #define CR_W    (1 << 3)        /* Write buffer enable                  */
25 #define CR_P    (1 << 4)        /* 32-bit exception handler             */
26 #define CR_D    (1 << 5)        /* 32-bit data address range            */
27 #define CR_L    (1 << 6)        /* Implementation defined               */
28 #define CR_B    (1 << 7)        /* Big endian                           */
29 #define CR_S    (1 << 8)        /* System MMU protection                */
30 #define CR_R    (1 << 9)        /* ROM MMU protection                   */
31 #define CR_F    (1 << 10)       /* Implementation defined               */
32 #define CR_Z    (1 << 11)       /* Implementation defined               */
33 #define CR_I    (1 << 12)       /* Icache enable                        */
34 #define CR_V    (1 << 13)       /* Vectors relocated to 0xffff0000      */
35 #define CR_RR   (1 << 14)       /* Round Robin cache replacement        */
36 #define CR_L4   (1 << 15)       /* LDR pc can set T bit                 */
37 #define CR_DT   (1 << 16)
38 #define CR_IT   (1 << 18)
39 #define CR_ST   (1 << 19)
40 #define CR_FI   (1 << 21)       /* Fast interrupt (lower latency mode)  */
41 #define CR_U    (1 << 22)       /* Unaligned access operation           */
42 #define CR_XP   (1 << 23)       /* Extended page tables                 */
43 #define CR_VE   (1 << 24)       /* Vectored interrupts                  */
44
45 #define CPUID_ID        0
46 #define CPUID_CACHETYPE 1
47 #define CPUID_TCM       2
48 #define CPUID_TLBTYPE   3
49
50 #define read_cpuid(reg)                                                 \
51         ({                                                              \
52                 unsigned int __val;                                     \
53                 asm("mrc        p15, 0, %0, c0, c0, " __stringify(reg)  \
54                     : "=r" (__val)                                      \
55                     :                                                   \
56                     : "cc");                                            \
57                 __val;                                                  \
58         })
59
60 /*
61  * This is used to ensure the compiler did actually allocate the register we
62  * asked it for some inline assembly sequences.  Apparently we can't trust
63  * the compiler from one version to another so a bit of paranoia won't hurt.
64  * This string is meant to be concatenated with the inline asm string and
65  * will cause compilation to stop on mismatch.
66  * (for details, see gcc PR 15089)
67  */
68 #define __asmeq(x, y)  ".ifnc " x "," y " ; .err ; .endif\n\t"
69
70 #ifndef __ASSEMBLY__
71
72 #include <linux/linkage.h>
73
74 struct thread_info;
75 struct task_struct;
76
77 /* information about the system we're running on */
78 extern unsigned int system_rev;
79 extern unsigned int system_serial_low;
80 extern unsigned int system_serial_high;
81 extern unsigned int mem_fclk_21285;
82
83 struct pt_regs;
84
85 void die(const char *msg, struct pt_regs *regs, int err)
86                 __attribute__((noreturn));
87
88 struct siginfo;
89 void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
90                 unsigned long err, unsigned long trap);
91
92 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
93                                        struct pt_regs *),
94                      int sig, const char *name);
95
96 #include <asm/proc-fns.h>
97
98 #define xchg(ptr,x) \
99         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
100
101 #define tas(ptr) (xchg((ptr),1))
102
103 extern asmlinkage void __backtrace(void);
104 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
105 extern void show_pte(struct mm_struct *mm, unsigned long addr);
106 extern void __show_regs(struct pt_regs *);
107
108 extern int cpu_architecture(void);
109 extern void cpu_init(void);
110
111 #define set_cr(x)                                       \
112         __asm__ __volatile__(                           \
113         "mcr    p15, 0, %0, c1, c0, 0   @ set CR"       \
114         : : "r" (x) : "cc")
115
116 #define get_cr()                                        \
117         ({                                              \
118         unsigned int __val;                             \
119         __asm__ __volatile__(                           \
120         "mrc    p15, 0, %0, c1, c0, 0   @ get CR"       \
121         : "=r" (__val) : : "cc");                       \
122         __val;                                          \
123         })
124
125 extern unsigned long cr_no_alignment;   /* defined in entry-armv.S */
126 extern unsigned long cr_alignment;      /* defined in entry-armv.S */
127
128 #define UDBG_UNDEFINED  (1 << 0)
129 #define UDBG_SYSCALL    (1 << 1)
130 #define UDBG_BADABORT   (1 << 2)
131 #define UDBG_SEGV       (1 << 3)
132 #define UDBG_BUS        (1 << 4)
133
134 extern unsigned int user_debug;
135
136 #if __LINUX_ARM_ARCH__ >= 4
137 #define vectors_high()  (cr_alignment & CR_V)
138 #else
139 #define vectors_high()  (0)
140 #endif
141
142 #define mb() __asm__ __volatile__ ("" : : : "memory")
143 #define rmb() mb()
144 #define wmb() mb()
145 #define read_barrier_depends() do { } while(0)
146 #define set_mb(var, value)  do { var = value; mb(); } while (0)
147 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
148 #define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
149
150 /*
151  * switch_mm() may do a full cache flush over the context switch,
152  * so enable interrupts over the context switch to avoid high
153  * latency.
154  */
155 #define __ARCH_WANT_INTERRUPTS_ON_CTXSW
156
157 /*
158  * switch_to(prev, next) should switch from task `prev' to `next'
159  * `prev' will never be the same as `next'.  schedule() itself
160  * contains the memory barrier to tell GCC not to cache `current'.
161  */
162 extern struct task_struct *__switch_to(struct task_struct *, struct thread_info *, struct thread_info *);
163
164 #define switch_to(prev,next,last)                                       \
165 do {                                                                    \
166         last = __switch_to(prev,prev->thread_info,next->thread_info);   \
167 } while (0)
168
169 /*
170  * CPU interrupt mask handling.
171  */
172 #if __LINUX_ARM_ARCH__ >= 6
173
174 #define local_irq_save(x)                                       \
175         ({                                                      \
176         __asm__ __volatile__(                                   \
177         "mrs    %0, cpsr                @ local_irq_save\n"     \
178         "cpsid  i"                                              \
179         : "=r" (x) : : "memory", "cc");                         \
180         })
181
182 #define local_irq_enable()  __asm__("cpsie i    @ __sti" : : : "memory", "cc")
183 #define local_irq_disable() __asm__("cpsid i    @ __cli" : : : "memory", "cc")
184 #define local_fiq_enable()  __asm__("cpsie f    @ __stf" : : : "memory", "cc")
185 #define local_fiq_disable() __asm__("cpsid f    @ __clf" : : : "memory", "cc")
186
187 #else
188
189 /*
190  * Save the current interrupt enable state & disable IRQs
191  */
192 #define local_irq_save(x)                                       \
193         ({                                                      \
194                 unsigned long temp;                             \
195                 (void) (&temp == &x);                           \
196         __asm__ __volatile__(                                   \
197         "mrs    %0, cpsr                @ local_irq_save\n"     \
198 "       orr     %1, %0, #128\n"                                 \
199 "       msr     cpsr_c, %1"                                     \
200         : "=r" (x), "=r" (temp)                                 \
201         :                                                       \
202         : "memory", "cc");                                      \
203         })
204         
205 /*
206  * Enable IRQs
207  */
208 #define local_irq_enable()                                      \
209         ({                                                      \
210                 unsigned long temp;                             \
211         __asm__ __volatile__(                                   \
212         "mrs    %0, cpsr                @ local_irq_enable\n"   \
213 "       bic     %0, %0, #128\n"                                 \
214 "       msr     cpsr_c, %0"                                     \
215         : "=r" (temp)                                           \
216         :                                                       \
217         : "memory", "cc");                                      \
218         })
219
220 /*
221  * Disable IRQs
222  */
223 #define local_irq_disable()                                     \
224         ({                                                      \
225                 unsigned long temp;                             \
226         __asm__ __volatile__(                                   \
227         "mrs    %0, cpsr                @ local_irq_disable\n"  \
228 "       orr     %0, %0, #128\n"                                 \
229 "       msr     cpsr_c, %0"                                     \
230         : "=r" (temp)                                           \
231         :                                                       \
232         : "memory", "cc");                                      \
233         })
234
235 /*
236  * Enable FIQs
237  */
238 #define local_fiq_enable()                                      \
239         ({                                                      \
240                 unsigned long temp;                             \
241         __asm__ __volatile__(                                   \
242         "mrs    %0, cpsr                @ stf\n"                \
243 "       bic     %0, %0, #64\n"                                  \
244 "       msr     cpsr_c, %0"                                     \
245         : "=r" (temp)                                           \
246         :                                                       \
247         : "memory", "cc");                                      \
248         })
249
250 /*
251  * Disable FIQs
252  */
253 #define local_fiq_disable()                                     \
254         ({                                                      \
255                 unsigned long temp;                             \
256         __asm__ __volatile__(                                   \
257         "mrs    %0, cpsr                @ clf\n"                \
258 "       orr     %0, %0, #64\n"                                  \
259 "       msr     cpsr_c, %0"                                     \
260         : "=r" (temp)                                           \
261         :                                                       \
262         : "memory", "cc");                                      \
263         })
264
265 #endif
266
267 /*
268  * Save the current interrupt enable state.
269  */
270 #define local_save_flags(x)                                     \
271         ({                                                      \
272         __asm__ __volatile__(                                   \
273         "mrs    %0, cpsr                @ local_save_flags"     \
274         : "=r" (x) : : "memory", "cc");                         \
275         })
276
277 /*
278  * restore saved IRQ & FIQ state
279  */
280 #define local_irq_restore(x)                                    \
281         __asm__ __volatile__(                                   \
282         "msr    cpsr_c, %0              @ local_irq_restore\n"  \
283         :                                                       \
284         : "r" (x)                                               \
285         : "memory", "cc")
286
287 #define irqs_disabled()                 \
288 ({                                      \
289         unsigned long flags;            \
290         local_save_flags(flags);        \
291         (int)(flags & PSR_I_BIT);       \
292 })
293
294 #ifdef CONFIG_SMP
295
296 #define smp_mb()                mb()
297 #define smp_rmb()               rmb()
298 #define smp_wmb()               wmb()
299 #define smp_read_barrier_depends()              read_barrier_depends()
300
301 #else
302
303 #define smp_mb()                barrier()
304 #define smp_rmb()               barrier()
305 #define smp_wmb()               barrier()
306 #define smp_read_barrier_depends()              do { } while(0)
307
308 #endif /* CONFIG_SMP */
309
310 #if defined(CONFIG_CPU_SA1100) || defined(CONFIG_CPU_SA110)
311 /*
312  * On the StrongARM, "swp" is terminally broken since it bypasses the
313  * cache totally.  This means that the cache becomes inconsistent, and,
314  * since we use normal loads/stores as well, this is really bad.
315  * Typically, this causes oopsen in filp_close, but could have other,
316  * more disasterous effects.  There are two work-arounds:
317  *  1. Disable interrupts and emulate the atomic swap
318  *  2. Clean the cache, perform atomic swap, flush the cache
319  *
320  * We choose (1) since its the "easiest" to achieve here and is not
321  * dependent on the processor type.
322  *
323  * NOTE that this solution won't work on an SMP system, so explcitly
324  * forbid it here.
325  */
326 #ifdef CONFIG_SMP
327 #error SMP is not supported on SA1100/SA110
328 #else
329 #define swp_is_buggy
330 #endif
331 #endif
332
333 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
334 {
335         extern void __bad_xchg(volatile void *, int);
336         unsigned long ret;
337 #ifdef swp_is_buggy
338         unsigned long flags;
339 #endif
340
341         switch (size) {
342 #ifdef swp_is_buggy
343                 case 1:
344                         local_irq_save(flags);
345                         ret = *(volatile unsigned char *)ptr;
346                         *(volatile unsigned char *)ptr = x;
347                         local_irq_restore(flags);
348                         break;
349
350                 case 4:
351                         local_irq_save(flags);
352                         ret = *(volatile unsigned long *)ptr;
353                         *(volatile unsigned long *)ptr = x;
354                         local_irq_restore(flags);
355                         break;
356 #else
357                 case 1: __asm__ __volatile__ ("swpb %0, %1, [%2]"
358                                         : "=&r" (ret)
359                                         : "r" (x), "r" (ptr)
360                                         : "memory", "cc");
361                         break;
362                 case 4: __asm__ __volatile__ ("swp %0, %1, [%2]"
363                                         : "=&r" (ret)
364                                         : "r" (x), "r" (ptr)
365                                         : "memory", "cc");
366                         break;
367 #endif
368                 default: __bad_xchg(ptr, size), ret = 0;
369         }
370
371         return ret;
372 }
373
374 #endif /* __ASSEMBLY__ */
375
376 #define arch_align_stack(x) (x)
377
378 #endif /* __KERNEL__ */
379
380 #endif