video: tegra: adf: replace nvmap_alloc_dmabuf with v4l2 API
[linux-3.10.git] / drivers / video / tegra / tegra_adf.c
1 /*
2  * Copyright (C) 2013 Google, Inc.
3  * Copyright (c) 2014, NVIDIA CORPORATION, All rights reserved.
4  *
5  * modified from drivers/video/tegra/dc/{mode.c,ext/dev.c}
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  */
17
18 #include <linux/gfp.h>
19 #include <media/videobuf2-dma-contig.h>
20 #include <video/adf.h>
21 #include <video/adf_fbdev.h>
22 #include <video/adf_format.h>
23
24 #include "dc/dc_config.h"
25 #include "dc/dc_priv.h"
26 #include "tegra_adf.h"
27
28 struct tegra_adf_info {
29         struct adf_device               base;
30         struct adf_interface            intf;
31         struct adf_overlay_engine       eng;
32         struct tegra_dc                 *dc;
33         void                            *vb2_dma_conf;
34 };
35
36 #define adf_dev_to_tegra(p) \
37         container_of(p, struct tegra_adf_info, base)
38
39 #define adf_intf_to_tegra(p) \
40         container_of(p, struct tegra_adf_info, intf)
41
42 const u8 tegra_adf_fourcc_to_dc_fmt(u32 fourcc)
43 {
44         switch (fourcc) {
45         case TEGRA_ADF_FORMAT_P1:
46                 return TEGRA_WIN_FMT_P1;
47         case TEGRA_ADF_FORMAT_P2:
48                 return TEGRA_WIN_FMT_P2;
49         case TEGRA_ADF_FORMAT_P4:
50                 return TEGRA_WIN_FMT_P4;
51         case TEGRA_ADF_FORMAT_P8:
52                 return TEGRA_WIN_FMT_P8;
53         case DRM_FORMAT_BGRA4444:
54                 return TEGRA_WIN_FMT_B4G4R4A4;
55         case DRM_FORMAT_BGRA5551:
56                 return TEGRA_WIN_FMT_B5G5R5A;
57         case DRM_FORMAT_BGR565:
58                 return TEGRA_WIN_FMT_B5G6R5;
59         case DRM_FORMAT_BGRA8888:
60         case DRM_FORMAT_BGRX8888:
61                 return TEGRA_WIN_FMT_B8G8R8A8;
62         case DRM_FORMAT_RGBA8888:
63         case DRM_FORMAT_RGBX8888:
64                 return TEGRA_WIN_FMT_R8G8B8A8;
65         case TEGRA_ADF_FORMAT_B6x2G6x2R6x2A8:
66                 return TEGRA_WIN_FMT_B6x2G6x2R6x2A8;
67         case TEGRA_ADF_FORMAT_R6x2G6x2B6x2A8:
68                 return TEGRA_WIN_FMT_R6x2G6x2B6x2A8;
69         case DRM_FORMAT_YUV420:
70                 return TEGRA_WIN_FMT_YCbCr420P;
71         case DRM_FORMAT_YUV422:
72                 return TEGRA_WIN_FMT_YCbCr422P;
73         case TEGRA_ADF_FORMAT_YCbCr422R:
74                 return TEGRA_WIN_FMT_YCbCr422R;
75         case DRM_FORMAT_UYVY:
76                 return TEGRA_WIN_FMT_YCbCr422;
77         case DRM_FORMAT_NV12:
78                 return TEGRA_WIN_FMT_YCbCr420SP;
79         case DRM_FORMAT_NV21:
80                 return TEGRA_WIN_FMT_YCrCb420SP;
81         default:
82                 BUG();
83         }
84 }
85
86 static int tegra_dc_to_drm_modeinfo(struct drm_mode_modeinfo *dmode,
87         const struct tegra_dc_mode *mode)
88 {
89         long mode_pclk;
90
91         if (!dmode || !mode || !mode->pclk)
92                 return -EINVAL;
93         if (mode->rated_pclk >= 1000) /* handle DSI one-shot modes */
94                 mode_pclk = mode->rated_pclk;
95         else if (mode->pclk >= 1000) /* normal continous modes */
96                 mode_pclk = mode->pclk;
97         else
98                 mode_pclk = 0;
99         memset(dmode, 0, sizeof(*dmode));
100         dmode->hdisplay = mode->h_active;
101         dmode->vdisplay = mode->v_active;
102         dmode->hsync_start = dmode->hdisplay + mode->h_front_porch;
103         dmode->vsync_start = dmode->vdisplay + mode->v_front_porch;
104         dmode->hsync_end = dmode->hsync_start + mode->h_sync_width;
105         dmode->vsync_end = dmode->vsync_start + mode->v_sync_width;
106         dmode->htotal = dmode->hsync_end + mode->h_back_porch;
107         dmode->vtotal = dmode->vsync_end + mode->v_back_porch;
108 #if 0
109         if (mode->stereo_mode) {
110 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
111                 /* Double the pixel clock and update v_active only for
112                  * frame packed mode */
113                 mode_pclk /= 2;
114                 /* total v_active = yres*2 + activespace */
115                 fbmode->vdisplay = (mode->v_active - mode->v_sync_width -
116                         mode->v_back_porch - mode->v_front_porch) / 2;
117                 fbmode->vmode |= FB_VMODE_STEREO_FRAME_PACK;
118 #else
119                 fbmode->vmode |= FB_VMODE_STEREO_LEFT_RIGHT;
120 #endif
121         }
122 #endif
123
124         if (mode->flags & FB_VMODE_INTERLACED)
125                 dmode->flags |= DRM_MODE_FLAG_INTERLACE;
126
127         if ((mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC))
128                 dmode->flags |= DRM_MODE_FLAG_NHSYNC;
129         else
130                 dmode->flags |= DRM_MODE_FLAG_PHSYNC;
131         if ((mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC))
132                 dmode->flags |= DRM_MODE_FLAG_NVSYNC;
133         else
134                 dmode->flags |= DRM_MODE_FLAG_PVSYNC;
135 #if 0
136         if (mode->avi_m == TEGRA_DC_MODE_AVI_M_16_9)
137                 fbmode->flag |= FB_FLAG_RATIO_16_9;
138         else if (mode->avi_m == TEGRA_DC_MODE_AVI_M_4_3)
139                 fbmode->flag |= FB_FLAG_RATIO_4_3;
140 #endif
141
142         dmode->clock = mode_pclk / 1000;
143         dmode->vrefresh = tegra_dc_calc_refresh(mode) / 1000;
144
145         adf_modeinfo_set_name(dmode);
146
147         return 0;
148 }
149
150 static int tegra_adf_convert_monspecs(struct tegra_adf_info *adf_info,
151                 struct fb_monspecs *specs, struct drm_mode_modeinfo **modelist,
152                 size_t *n_modes)
153 {
154         struct tegra_dc *dc = adf_info->dc;
155         struct drm_mode_modeinfo *modes;
156         size_t n = 0;
157         u32 i;
158
159         modes = kmalloc(specs->modedb_len * sizeof(modes[0]), GFP_KERNEL);
160         if (!modes)
161                 return -ENOMEM;
162
163         for (i = 0; i < specs->modedb_len; i++) {
164                 struct fb_videomode *fb_mode = &specs->modedb[i];
165                 if (dc->out_ops->mode_filter &&
166                                 !dc->out_ops->mode_filter(dc, fb_mode))
167                         continue;
168                 adf_modeinfo_from_fb_videomode(fb_mode, &modes[n]);
169                 n++;
170         }
171
172         *modelist = modes;
173         *n_modes = n;
174         return 0;
175 }
176
177 static int tegra_adf_convert_builtin_modes(struct tegra_adf_info *adf_info,
178                 struct drm_mode_modeinfo **modelist, size_t *n_modes)
179 {
180         struct tegra_dc *dc = adf_info->dc;
181         struct drm_mode_modeinfo *modes;
182         u32 i;
183
184         modes = kmalloc(dc->out->n_modes * sizeof(modes[0]), GFP_KERNEL);
185         if (!modes)
186                 return -ENOMEM;
187
188         for (i = 0; i < dc->out->n_modes; i++) {
189                 int err = tegra_dc_to_drm_modeinfo(&modes[i],
190                                 &dc->out->modes[i]);
191                 if (err < 0)
192                         return err;
193         }
194
195         *modelist = modes;
196         *n_modes = dc->out->n_modes;
197         return 0;
198 }
199
200 static int tegra_adf_do_hotplug(struct tegra_adf_info *adf_info,
201                 struct drm_mode_modeinfo *modelist, size_t n_modes)
202 {
203         int err = tegra_dc_set_drm_mode(adf_info->dc, modelist, false);
204         if (err < 0)
205                 return err;
206         memcpy(&adf_info->intf.current_mode, &modelist[0], sizeof(modelist[0]));
207
208         return adf_hotplug_notify_connected(&adf_info->intf, modelist, n_modes);
209 }
210
211 int tegra_adf_process_hotplug_connected(struct tegra_adf_info *adf_info,
212                 struct fb_monspecs *specs)
213 {
214         struct tegra_dc_out *out = adf_info->dc->out;
215         struct drm_mode_modeinfo *modes;
216         size_t n_modes;
217         int err;
218
219         if (!specs && !out->modes) {
220                 struct drm_mode_modeinfo reset_mode = {0};
221                 return tegra_adf_do_hotplug(adf_info, &reset_mode, 1);
222         }
223
224         if (specs)
225                 err = tegra_adf_convert_monspecs(adf_info, specs, &modes,
226                                 &n_modes);
227         else
228                 err = tegra_adf_convert_builtin_modes(adf_info, &modes,
229                                 &n_modes);
230
231         if (err < 0)
232                 return err;
233
234         err = tegra_adf_do_hotplug(adf_info, modes, n_modes);
235         kfree(modes);
236         return err;
237 }
238
239 void tegra_adf_process_hotplug_disconnected(struct tegra_adf_info *adf_info)
240 {
241         adf_hotplug_notify_disconnected(&adf_info->intf);
242 }
243
244 static int tegra_adf_dev_custom_data(struct adf_obj *obj, void *data,
245                 size_t *size)
246 {
247         struct tegra_adf_capabilities *caps = data;
248
249         caps->caps = TEGRA_ADF_CAPABILITIES_CURSOR_MODE |
250                         TEGRA_ADF_CAPABILITIES_BLOCKLINEAR;
251         *size = sizeof(*caps);
252         return 0;
253 }
254
255 static int tegra_adf_dev_validate_custom_format(struct adf_device *dev,
256                 struct adf_buffer *buf)
257 {
258         u8 dc_fmt = tegra_adf_fourcc_to_dc_fmt(buf->format);
259
260         if (tegra_dc_is_yuv(dc_fmt)) {
261                 return -EINVAL; /* TODO */
262         } else {
263                 u8 cpp = tegra_dc_fmt_bpp(dc_fmt) / 8;
264                 return adf_format_validate_rgb(dev, buf, cpp);
265         }
266
267         return 0;
268 }
269
270 const u32 tegra_adf_formats[] = {
271         TEGRA_ADF_FORMAT_P1,
272         TEGRA_ADF_FORMAT_P2,
273         TEGRA_ADF_FORMAT_P4,
274         TEGRA_ADF_FORMAT_P8,
275         DRM_FORMAT_BGRA4444,
276         DRM_FORMAT_BGRA5551,
277         DRM_FORMAT_BGR565,
278         DRM_FORMAT_ABGR1555,
279         DRM_FORMAT_BGRA8888,
280         DRM_FORMAT_BGRX8888,
281         DRM_FORMAT_RGBA8888,
282         DRM_FORMAT_RGBX8888,
283         TEGRA_ADF_FORMAT_B6x2G6x2R6x2A8,
284         TEGRA_ADF_FORMAT_R6x2G6x2B6x2A8,
285         TEGRA_ADF_FORMAT_R6x2G6x2B6x2A8,
286         DRM_FORMAT_YUV420,
287         DRM_FORMAT_YUV422,
288         TEGRA_ADF_FORMAT_YCbCr422R,
289         DRM_FORMAT_UYVY,
290         DRM_FORMAT_NV12,
291         DRM_FORMAT_NV21,
292 };
293
294 static int tegra_adf_check_windowattr(struct tegra_adf_info *adf_info,
295                 const struct tegra_adf_flip_windowattr *attr, u32 fourcc)
296 {
297         long *addr;
298         struct tegra_dc *dc = adf_info->dc;
299         struct device *dev = &adf_info->base.base.dev;
300         u8 fmt = tegra_adf_fourcc_to_dc_fmt(fourcc);
301
302         addr = tegra_dc_parse_feature(dc, attr->win_index, GET_WIN_FORMATS);
303         /* Check if the window exists */
304         if (!addr) {
305                 dev_err(dev, "window %d feature is not found.\n",
306                                 attr->win_index);
307                 goto fail;
308         }
309         /* Check the window format */
310         if (!test_bit(fmt, addr)) {
311                 dev_err(dev,
312                         "Color format of window %d is invalid.\n",
313                         attr->win_index);
314                 goto fail;
315         }
316
317         /* Check window size */
318         addr = tegra_dc_parse_feature(dc, attr->win_index, GET_WIN_SIZE);
319         if (CHECK_SIZE(attr->out_w, addr[MIN_WIDTH], addr[MAX_WIDTH]) ||
320                 CHECK_SIZE(attr->out_h, addr[MIN_HEIGHT], addr[MAX_HEIGHT])) {
321                 dev_err(dev,
322                         "Size of window %d is invalid with %d wide %d high.\n",
323                         attr->win_index, attr->out_w, attr->out_h);
324                 goto fail;
325         }
326
327         if (attr->flags & TEGRA_ADF_FLIP_FLAG_BLOCKLINEAR) {
328                 if (attr->flags & TEGRA_ADF_FLIP_FLAG_TILED) {
329                         dev_err(&dc->ndev->dev, "Layout cannot be both blocklinear and tile for window %d.\n",
330                                 attr->win_index);
331                         goto fail;
332                 }
333
334                 /* TODO: also check current window blocklinear support */
335         }
336
337         return 0;
338 fail:
339         return -EINVAL;
340 }
341
342 static int tegra_adf_sanitize_flip_args(struct tegra_adf_info *adf_info,
343                 struct adf_post *cfg,
344                 struct tegra_adf_flip_windowattr *win, int win_num)
345 {
346         struct device *dev = &adf_info->base.base.dev;
347         int i, used_windows = 0;
348
349         if (win_num > DC_N_WINDOWS) {
350                 dev_err(dev, "too many windows (%u > %u)\n", win_num,
351                                 DC_N_WINDOWS);
352                 return -EINVAL;
353         }
354
355         for (i = 0; i < win_num; i++) {
356                 int index = win[i].win_index;
357                 int buf_index = win[i].buf_index;
358                 int err;
359
360                 if (index < 0)
361                         continue;
362
363                 if (index >= DC_N_WINDOWS) {
364                         dev_err(dev, "invalid window index %u\n", index);
365                         return -EINVAL;
366                 }
367
368                 if (used_windows & BIT(index)) {
369                         dev_err(dev, "window index %u already used\n", index);
370                         return -EINVAL;
371                 }
372
373                 if (buf_index >= 0) {
374                         if (buf_index >= cfg->n_bufs) {
375                                 dev_err(dev, "invalid buffer index %d (n_bufs = %u)\n",
376                                                 buf_index, cfg->n_bufs);
377                                 return -EINVAL;
378                         }
379
380                         err = tegra_adf_check_windowattr(adf_info, &win[i],
381                                         cfg->bufs[buf_index].format);
382                         if (err < 0)
383                                 return err;
384                 }
385
386                 used_windows |= BIT(index);
387         }
388
389         if (!used_windows) {
390                 dev_err(dev, "no windows used\n");
391                 return -EINVAL;
392         }
393
394         return 0;
395 }
396
397 int tegra_adf_dev_validate(struct adf_device *dev, struct adf_post *cfg,
398                 void **driver_state)
399 {
400         struct tegra_adf_flip *args = cfg->custom_data;
401         struct tegra_adf_info *adf_info = adf_dev_to_tegra(dev);
402         struct tegra_adf_flip_windowattr *win;
403         unsigned int win_num;
404         size_t custom_data_size = sizeof(*args);
405         u32 *syncpt_max;
406         int ret = 0;
407
408         if (cfg->custom_data_size < custom_data_size) {
409                 dev_err(dev->dev, "custom data size too small (%u < %u)\n",
410                                 cfg->custom_data_size, custom_data_size);
411                 return -EINVAL;
412         }
413
414         win = args->win;
415         win_num = args->win_num;
416
417         custom_data_size += win_num * sizeof(win[0]);
418         if (cfg->custom_data_size != custom_data_size) {
419                 dev_err(dev->dev, "expected %u bytes of custom data for %u windows, received %u\n",
420                                 custom_data_size, args->win_num,
421                                 cfg->custom_data_size);
422                 return -EINVAL;
423         }
424
425         ret = tegra_adf_sanitize_flip_args(adf_info, cfg, win, win_num);
426         if (ret)
427                 return ret;
428
429         BUG_ON(win_num > DC_N_WINDOWS);
430
431         syncpt_max = kzalloc(win_num * sizeof(syncpt_max[0]), GFP_KERNEL);
432         if (!syncpt_max)
433                 return -ENOMEM;
434
435         *driver_state = syncpt_max;
436         return 0;
437 }
438
439 static inline dma_addr_t tegra_adf_phys_addr(struct adf_buffer *buf,
440                 struct adf_buffer_mapping *mapping,
441                 size_t plane)
442 {
443         dma_addr_t addr = buf->dma_bufs[plane] ?
444                         sg_dma_address(mapping->sg_tables[plane]->sgl) :
445                         sg_dma_address(mapping->sg_tables[TEGRA_DC_Y]->sgl);
446         addr += buf->offset[plane];
447         return addr;
448 }
449
450 static void tegra_adf_set_windowattr(struct tegra_adf_info *adf_info,
451                 struct tegra_dc_win *win,
452                 const struct tegra_adf_flip_windowattr *attr,
453                 struct adf_buffer *buf, struct adf_buffer_mapping *mapping)
454 {
455         s64 timestamp_ns;
456
457         if (!buf) {
458                 win->flags = 0;
459                 return;
460         }
461
462         win->flags = TEGRA_WIN_FLAG_ENABLED;
463         if (attr->blend == TEGRA_DC_EXT_BLEND_PREMULT)
464                 win->flags |= TEGRA_WIN_FLAG_BLEND_PREMULT;
465         else if (attr->blend == TEGRA_DC_EXT_BLEND_COVERAGE)
466                 win->flags |= TEGRA_WIN_FLAG_BLEND_COVERAGE;
467         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_TILED)
468                 win->flags |= TEGRA_WIN_FLAG_TILED;
469         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_INVERT_H)
470                 win->flags |= TEGRA_WIN_FLAG_INVERT_H;
471         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_INVERT_V)
472                 win->flags |= TEGRA_WIN_FLAG_INVERT_V;
473         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_GLOBAL_ALPHA)
474                 win->global_alpha = attr->global_alpha;
475         else
476                 win->global_alpha = 255;
477 #if defined(CONFIG_TEGRA_DC_SCAN_COLUMN)
478         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_SCAN_COLUMN)
479                 win->flags |= TEGRA_WIN_FLAG_SCAN_COLUMN;
480 #endif
481 #if defined(CONFIG_TEGRA_DC_BLOCK_LINEAR)
482         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_BLOCKLINEAR) {
483                 win->flags |= TEGRA_WIN_FLAG_BLOCKLINEAR;
484                 win->block_height_log2 = attr->block_height_log2;
485         }
486 #endif
487 #if defined(CONFIG_TEGRA_DC_INTERLACE)
488         if (attr->flags & TEGRA_DC_EXT_FLIP_FLAG_INTERLACE)
489                 win->flags |= TEGRA_WIN_FLAG_INTERLACE;
490 #endif
491
492         win->fmt = tegra_adf_fourcc_to_dc_fmt(buf->format);
493         win->x.full = attr->x;
494         win->y.full = attr->y;
495         win->w.full = dfixed_const(buf->w);
496         win->h.full = dfixed_const(buf->h);
497         /* XXX verify that this doesn't go outside display's active region */
498         win->out_x = attr->out_x;
499         win->out_y = attr->out_y;
500         win->out_w = attr->out_w;
501         win->out_h = attr->out_h;
502         win->z = attr->z;
503
504         /* XXX verify that this won't read outside of the surface */
505         win->phys_addr = tegra_adf_phys_addr(buf, mapping, TEGRA_DC_Y);
506         win->phys_addr_u = tegra_adf_phys_addr(buf, mapping, TEGRA_DC_U);
507         win->phys_addr_v = tegra_adf_phys_addr(buf, mapping, TEGRA_DC_V);
508
509         win->stride = buf->pitch[0];
510         win->stride_uv = buf->pitch[1];
511
512 #if defined(CONFIG_TEGRA_DC_INTERLACE)
513         if (adf_info->dc->mode.vmode == FB_VMODE_INTERLACED) {
514                 if (attr->flags & TEGRA_ADF_FLIP_FLAG_INTERLACE) {
515                         win->phys_addr2 = win->phys_addr + attr->offset2;
516                         win->phys_addr_u2 = win->phys_addr_u + attr->offset_u2;
517                         win->phys_addr_v2 = win->phys_addr_v + attr->offset_v2;
518                 } else {
519                         win->phys_addr2 = win->phys_addr;
520                         win->phys_addr_u2 = win->phys_addr_u;
521                         win->phys_addr_v2 = win->phys_addr_v;
522                 }
523         }
524 #endif
525
526         if (tegra_platform_is_silicon()) {
527                 timestamp_ns = timespec_to_ns(&attr->timestamp);
528
529                 dev_WARN_ONCE(&adf_info->base.base.dev, timestamp_ns,
530                                 "timestamping not implemented\n");
531                 /* TODO: implement timestamping */
532 #if 0
533                 if (timestamp_ns) {
534                         /* XXX: Should timestamping be overridden by "no_vsync"
535                          * flag */
536                         tegra_dc_config_frame_end_intr(win->dc, true);
537                         err = wait_event_interruptible(win->dc->timestamp_wq,
538                                 tegra_dc_is_within_n_vsync(win->dc,
539                                                 timestamp_ns));
540                         tegra_dc_config_frame_end_intr(win->dc, false);
541                 }
542 #endif
543         }
544 }
545
546 static void tegra_adf_dev_post(struct adf_device *dev, struct adf_post *cfg,
547                 void *driver_state)
548 {
549         struct tegra_adf_info *adf_info = adf_dev_to_tegra(dev);
550         struct tegra_adf_flip *args = cfg->custom_data;
551         int win_num = args->win_num;
552         struct tegra_dc_win *wins[DC_N_WINDOWS];
553         int i, nr_win = 0;
554         bool skip_flip = false;
555
556         BUG_ON(win_num > DC_N_WINDOWS);
557         for (i = 0; i < win_num; i++) {
558                 struct tegra_adf_flip_windowattr *attr = &args->win[i];
559                 int index = attr->win_index;
560                 struct adf_buffer *buf;
561                 struct adf_buffer_mapping *mapping;
562                 struct tegra_dc_win *win;
563
564                 if (index < 0)
565                         continue;
566
567                 if (attr->buf_index < 0) {
568                         buf = NULL;
569                         mapping = NULL;
570                 } else {
571                         buf = &cfg->bufs[attr->buf_index];
572                         mapping = &cfg->mappings[attr->buf_index];
573                 }
574
575                 win = tegra_dc_get_window(adf_info->dc, index);
576
577 #if 0
578                 if (flip_win->flags & TEGRA_DC_EXT_FLIP_FLAG_CURSOR)
579                         skip_flip = true;
580
581                 mutex_lock(&ext_win->queue_lock);
582                 list_for_each_entry(temp, &ext_win->timestamp_queue,
583                                 timestamp_node) {
584                         if (!tegra_platform_is_silicon())
585                                 continue;
586                         if (j == 0) {
587                                 if (unlikely(temp != data))
588                                         dev_err(&win->dc->ndev->dev,
589                                                         "work queue did NOT dequeue head!!!");
590                                 else
591                                         head_timestamp =
592                                                 timespec_to_ns(&flip_win->attr.timestamp);
593                         } else {
594                                 s64 timestamp =
595                                         timespec_to_ns(&temp->win[i].attr.timestamp);
596
597                                 skip_flip = !tegra_dc_does_vsync_separate(ext->dc,
598                                                 timestamp, head_timestamp);
599                                 /* Look ahead only one flip */
600                                 break;
601                         }
602                         j++;
603                 }
604                 if (!list_empty(&ext_win->timestamp_queue))
605                         list_del(&data->timestamp_node);
606                 mutex_unlock(&ext_win->queue_lock);
607
608                 if (skip_flip)
609                         old_handle = flip_win->handle[TEGRA_DC_Y];
610                 else
611                         old_handle = ext_win->cur_handle[TEGRA_DC_Y];
612
613                 if (old_handle) {
614                         int j;
615                         for (j = 0; j < TEGRA_DC_NUM_PLANES; j++) {
616                                 if (skip_flip)
617                                         old_handle = flip_win->handle[j];
618                                 else
619                                         old_handle = ext_win->cur_handle[j];
620
621                                 if (!old_handle)
622                                         continue;
623
624                                 unpin_handles[nr_unpin++] = old_handle;
625                         }
626                 }
627
628                 if (!skip_flip)
629 #endif
630                         tegra_adf_set_windowattr(adf_info, win, attr, buf,
631                                         mapping);
632
633                 wins[nr_win++] = win;
634         }
635
636         if (!skip_flip) {
637                 tegra_dc_update_windows(wins, nr_win);
638                 /* TODO: implement swapinterval here */
639                 tegra_dc_sync_windows(wins, nr_win);
640                 if (!tegra_dc_has_multiple_dc())
641                         tegra_dc_call_flip_callback();
642         }
643 }
644
645 static struct sync_fence *tegra_adf_dev_complete_fence(struct adf_device *dev,
646                 struct adf_post *cfg, void *driver_state)
647 {
648         struct tegra_adf_info *adf_info = adf_dev_to_tegra(dev);
649         struct tegra_adf_flip *args = cfg->custom_data;
650         struct tegra_adf_flip_windowattr *win = args->win;
651         u32 *syncpt_max = driver_state;
652         u32 syncpt_val;
653         int work_index = -1;
654         unsigned int win_num = args->win_num, i;
655
656         for (i = 0; i < win_num; i++) {
657                 int index = win[i].win_index;
658
659                 if (index < 0)
660                         continue;
661
662                 syncpt_max[i] = tegra_dc_incr_syncpt_max(adf_info->dc,
663                                 index);
664
665                 /*
666                  * Any of these windows' syncpoints should be equivalent for
667                  * the client, so we just send back an arbitrary one of them
668                  */
669                 syncpt_val = syncpt_max[i];
670                 work_index = index;
671         }
672         if (work_index < 0)
673                 return ERR_PTR(-EINVAL);
674
675         return tegra_dc_create_fence(adf_info->dc, work_index, syncpt_val);
676 }
677
678 static void tegra_adf_dev_advance_timeline(struct adf_device *dev,
679                 struct adf_post *cfg, void *driver_state)
680 {
681         struct tegra_adf_info *adf_info = adf_dev_to_tegra(dev);
682         struct tegra_adf_flip *args = cfg->custom_data;
683         struct tegra_adf_flip_windowattr *win = args->win;
684         u32 *syncpt_max = driver_state;
685         unsigned int win_num = args->win_num, i;
686
687         for (i = 0; i < win_num; i++) {
688                 int index = win[i].win_index;
689
690                 if (index < 0)
691                         continue;
692
693                 tegra_dc_incr_syncpt_min(adf_info->dc, index, syncpt_max[i]);
694         }
695 }
696
697 static void tegra_adf_dev_state_free(struct adf_device *dev, void *driver_state)
698 {
699         kfree(driver_state);
700 }
701
702 void tegra_adf_process_vblank(struct tegra_adf_info *adf_info,
703                 ktime_t timestamp)
704 {
705         adf_vsync_notify(&adf_info->intf, timestamp);
706 }
707
708 static bool tegra_adf_intf_supports_event(struct adf_obj *obj,
709                 enum adf_event_type type)
710 {
711         struct adf_interface *intf = adf_obj_to_interface(obj);
712         struct tegra_adf_info *tegra_adf = adf_intf_to_tegra(intf);
713
714         switch (type) {
715         case ADF_EVENT_VSYNC:
716                 return true;
717         case ADF_EVENT_HOTPLUG:
718                 return tegra_dc_get_out(tegra_adf->dc) == TEGRA_DC_OUT_HDMI;
719         default:
720                 return false;
721         }
722 }
723
724 static void tegra_adf_set_vsync(struct tegra_adf_info *tegra_adf, bool enabled)
725 {
726         if (enabled) {
727                 tegra_dc_hold_dc_out(tegra_adf->dc);
728                 tegra_dc_vsync_enable(tegra_adf->dc);
729         } else {
730                 tegra_dc_vsync_disable(tegra_adf->dc);
731                 tegra_dc_release_dc_out(tegra_adf->dc);
732         }
733 }
734
735 static void tegra_adf_intf_set_event(struct adf_obj *obj,
736                 enum adf_event_type type, bool enabled)
737 {
738         struct adf_interface *intf = adf_obj_to_interface(obj);
739         struct tegra_adf_info *tegra_adf = adf_intf_to_tegra(intf);
740
741         switch (type) {
742         case ADF_EVENT_VSYNC:
743                 tegra_adf_set_vsync(tegra_adf, enabled);
744                 return;
745
746         case ADF_EVENT_HOTPLUG:
747                 return;
748
749         default:
750                 BUG();
751         }
752 }
753
754 static enum adf_interface_type tegra_adf_interface_type(struct tegra_dc *dc)
755 {
756         /* TODO: can RGB and LVDS be mapped to existing ADF_INTF types?
757          * Should they be added to ADF's list? */
758         switch (tegra_dc_get_out(dc)) {
759         case TEGRA_DC_OUT_RGB:
760                 return TEGRA_ADF_INTF_RGB;
761         case TEGRA_DC_OUT_HDMI:
762                 return ADF_INTF_HDMI;
763         case TEGRA_DC_OUT_DSI:
764                 return ADF_INTF_DSI;
765         case TEGRA_DC_OUT_DP:
766                 return ADF_INTF_eDP;
767         case TEGRA_DC_OUT_LVDS:
768                 return TEGRA_ADF_INTF_LVDS;
769         default:
770                 BUG();
771         }
772 }
773
774 static const char *tegra_adf_intf_type_str(struct adf_interface *intf)
775 {
776         switch ((enum tegra_adf_interface_type)intf->type) {
777         case TEGRA_ADF_INTF_RGB:
778                 return "RGB";
779         case TEGRA_ADF_INTF_LVDS:
780                 return "LVDS";
781         default:
782                 BUG();
783         }
784 }
785
786 static int tegra_adf_intf_blank(struct adf_interface *intf, u8 state)
787 {
788         struct tegra_adf_info *adf_info = adf_intf_to_tegra(intf);
789
790         switch (state) {
791         case DRM_MODE_DPMS_ON:
792                 tegra_dc_enable(adf_info->dc);
793                 return 0;
794
795         case DRM_MODE_DPMS_STANDBY:
796                 tegra_dc_blank(adf_info->dc);
797                 return 0;
798
799         case DRM_MODE_DPMS_SUSPEND:
800         case DRM_MODE_DPMS_OFF:
801                 tegra_dc_disable(adf_info->dc);
802                 return 0;
803
804         default:
805                 return -ENOTTY;
806         }
807 }
808
809 static int tegra_adf_intf_alloc_simple_buffer(struct adf_interface *intf,
810                 u16 w, u16 h, u32 format,
811                 struct dma_buf **dma_buf, u32 *offset, u32 *pitch)
812 {
813         size_t i;
814         struct tegra_adf_info *adf_info = adf_intf_to_tegra(intf);
815         const struct vb2_mem_ops *mem_ops = &vb2_dma_contig_memops;
816         void *vb2_buf;
817         bool format_valid = false;
818
819         for (i = 0; i < ARRAY_SIZE(tegra_adf_formats); i++) {
820                 if (tegra_adf_formats[i] == format) {
821                         format_valid = true;
822                         break;
823                 }
824         }
825
826         if (!format_valid)
827                 return -EINVAL;
828
829         *offset = 0;
830         *pitch = ALIGN(w * adf_format_bpp(format) / 8, 64);
831         *dma_buf = nvmap_alloc_dmabuf(h * *pitch, 0,
832                         NVMAP_HANDLE_WRITE_COMBINE | NVMAP_HANDLE_ZEROED_PAGES,
833                         0);
834         if (IS_ERR(*dma_buf))
835                 return PTR_ERR(*dma_buf);
836
837         return 0;
838 }
839
840 static int tegra_adf_intf_describe_simple_post(struct adf_interface *intf,
841                 struct adf_buffer *fb, void *data, size_t *size)
842 {
843         struct tegra_adf_info *adf_info = adf_intf_to_tegra(intf);
844         struct tegra_adf_flip *args = data;
845         int i;
846
847         args->win_num = adf_info->dc->n_windows;
848         for (i = 0; i < adf_info->dc->n_windows; i++) {
849                 args->win[i].win_index = i;
850                 args->win[i].buf_index = -1;
851         }
852         args->win[1].buf_index = 0;
853         args->win[1].out_w = intf->current_mode.hdisplay;
854         args->win[1].out_h = intf->current_mode.vdisplay;
855
856         *size = sizeof(*args) + args->win_num * sizeof(args->win[0]);
857         return 0;
858 }
859
860 static int tegra_adf_intf_modeset(struct adf_interface *intf,
861                 struct drm_mode_modeinfo *mode)
862 {
863         struct tegra_adf_info *adf_info = adf_intf_to_tegra(intf);
864         return tegra_dc_set_drm_mode(adf_info->dc, mode, false);
865 }
866
867 static int tegra_adf_intf_screen_size(struct adf_interface *intf, u16 *width_mm,
868                 u16 *height_mm)
869 {
870         struct tegra_adf_info *adf_info = adf_intf_to_tegra(intf);
871         struct tegra_dc_out *out = adf_info->dc->out;
872
873         if (!out->height)
874                 return -EINVAL;
875
876         *width_mm = out->width;
877         *height_mm = out->height;
878         return 0;
879 }
880
881 struct adf_device_ops tegra_adf_dev_ops = {
882         .owner = THIS_MODULE,
883         .base = {
884                 .custom_data = tegra_adf_dev_custom_data,
885         },
886         .validate_custom_format = tegra_adf_dev_validate_custom_format,
887         .validate = tegra_adf_dev_validate,
888         .complete_fence = tegra_adf_dev_complete_fence,
889         .post = tegra_adf_dev_post,
890         .advance_timeline = tegra_adf_dev_advance_timeline,
891         .state_free = tegra_adf_dev_state_free,
892 };
893
894 struct adf_interface_ops tegra_adf_intf_ops = {
895         .base = {
896                 .supports_event = tegra_adf_intf_supports_event,
897                 .set_event = tegra_adf_intf_set_event,
898         },
899         .blank = tegra_adf_intf_blank,
900         .alloc_simple_buffer = tegra_adf_intf_alloc_simple_buffer,
901         .describe_simple_post = tegra_adf_intf_describe_simple_post,
902         .modeset = tegra_adf_intf_modeset,
903         .screen_size = tegra_adf_intf_screen_size,
904         .type_str = tegra_adf_intf_type_str,
905 };
906
907 struct adf_overlay_engine_ops tegra_adf_eng_ops = {
908         .supported_formats = tegra_adf_formats,
909         .n_supported_formats = ARRAY_SIZE(tegra_adf_formats),
910 };
911
912 int tegra_adf_process_bandwidth_renegotiate(struct tegra_adf_info *adf_info,
913                                                 struct tegra_dc_bw_data *bw)
914 {
915         struct tegra_adf_event_bandwidth event;
916         event.base.type = TEGRA_ADF_EVENT_BANDWIDTH_RENEGOTIATE;
917         event.base.length = sizeof(event);
918         event.total_bw = bw->total_bw;
919         event.avail_bw = bw->avail_bw;
920         event.resvd_bw = bw->resvd_bw;
921         return adf_event_notify(&adf_info->base.base, &event.base);
922 }
923
924 struct tegra_adf_info *tegra_adf_init(struct platform_device *ndev,
925                 struct tegra_dc *dc,
926                 struct tegra_fb_data *fb_data)
927 {
928         struct tegra_adf_info *adf_info;
929         int err;
930         enum adf_interface_type intf_type;
931         u32 intf_flags = 0;
932
933         adf_info = kzalloc(sizeof(*adf_info), GFP_KERNEL);
934         if (!adf_info)
935                 return ERR_PTR(-ENOMEM);
936
937         adf_info->dc = dc;
938
939         err = adf_device_init(&adf_info->base, &ndev->dev,
940                         &tegra_adf_dev_ops, "%s", dev_name(&ndev->dev));
941         if (err < 0)
942                 goto err_dev_init;
943
944         intf_type = tegra_adf_interface_type(dc);
945
946         if (ndev->id == 0)
947                 intf_flags |= ADF_INTF_FLAG_PRIMARY;
948
949         if (intf_type == ADF_INTF_HDMI)
950                 intf_flags |= ADF_INTF_FLAG_EXTERNAL;
951
952         err = adf_interface_init(&adf_info->intf, &adf_info->base,
953                         intf_type, 0, intf_flags,
954                         &tegra_adf_intf_ops, "%s", dev_name(&ndev->dev));
955         if (err < 0)
956                 goto err_intf_init;
957
958         err = adf_overlay_engine_init(&adf_info->eng, &adf_info->base,
959                         &tegra_adf_eng_ops, "%s", dev_name(&ndev->dev));
960         if (err < 0)
961                 goto err_eng_init;
962
963         err = adf_attachment_allow(&adf_info->base, &adf_info->eng,
964                         &adf_info->intf);
965         if (err < 0)
966                 goto err_attach;
967
968         adf_info->vb2_dma_conf = vb2_dma_contig_init_ctx(&ndev->dev);
969         if ((err = IS_ERR(adf_info->vb2_dma_conf)))
970                 goto err_attach;
971
972         if (dc->out->n_modes) {
973                 err = tegra_adf_process_hotplug_connected(adf_info, NULL);
974                 if (err < 0)
975                         goto err_attach;
976         }
977
978         if (dc->enabled)
979                 adf_info->intf.dpms_state = DRM_MODE_DPMS_ON;
980
981         dev_info(&ndev->dev, "ADF initialized\n");
982
983         return adf_info;
984
985 err_attach:
986         adf_overlay_engine_destroy(&adf_info->eng);
987
988 err_eng_init:
989         adf_interface_destroy(&adf_info->intf);
990
991 err_intf_init:
992         adf_device_destroy(&adf_info->base);
993
994 err_dev_init:
995         kfree(adf_info);
996         return ERR_PTR(err);
997 }
998
999 void tegra_adf_unregister(struct tegra_adf_info *adf_info)
1000 {
1001         adf_overlay_engine_destroy(&adf_info->eng);
1002         adf_interface_destroy(&adf_info->intf);
1003         adf_device_destroy(&adf_info->base);
1004         kfree(adf_info);
1005 }