78523c5fa7c5f9dadc5f2061cfcbdd7de99b9db1
[linux-3.10.git] / drivers / video / tegra / dc / sor_regs.h
1 /*
2 * drivers/video/tegra/dc/sor_regs.h
3 *
4 * Copyright (c) 2011-2015, NVIDIA CORPORATION, All rights reserved.
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.   See the
13 * GNU General Public License for more details.
14 *
15 */
16
17 #ifndef __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
18 #define __DRIVER_VIDEO_TEGRA_DC_SOR_REGS_H__
19
20 #define NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(x)            ((x) & 0xff)
21 #define NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(x)         (((x) & 0xff) << 8)
22 #define NV_SOR_HDMI_INFOFRAME_HEADER_LEN(x)             (((x) & 0xf) << 16)
23 #define NV_SOR_HDMI_BRICK_MUL(x)                        (((x) >> 2) & 0x1f)
24 #define NV_SOR_HDMI_BRICK_DIV                           10
25
26 #define NV_SOR_SUPER_STATE0                                     (0x1)
27 #define NV_SOR_SUPER_STATE0_UPDATE_SHIFT                        (0)
28 #define NV_SOR_SUPER_STATE0_UPDATE_DEFAULT_MASK                 (0x1)
29 #define NV_SOR_SUPER_STATE1                                     (0x2)
30 #define NV_SOR_SUPER_STATE1_ATTACHED_SHIFT                      (3)
31 #define NV_SOR_SUPER_STATE1_ATTACHED_NO                         (0 << 3)
32 #define NV_SOR_SUPER_STATE1_ATTACHED_YES                        (1 << 3)
33 #define NV_SOR_SUPER_STATE1_ASY_ORMODE_SHIFT                    (2)
34 #define NV_SOR_SUPER_STATE1_ASY_ORMODE_SAFE                     (0 << 2)
35 #define NV_SOR_SUPER_STATE1_ASY_ORMODE_NORMAL                   (1 << 2)
36 #define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SHIFT                   (0)
37 #define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_DEFAULT_MASK            (0x3)
38 #define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SLEEP                   (0)
39 #define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_SNOOZE                  (1)
40 #define NV_SOR_SUPER_STATE1_ASY_HEAD_OP_AWAKE                   (2)
41 #define NV_SOR_STATE0                                           (0x3)
42 #define NV_SOR_STATE0_UPDATE_SHIFT                              (0)
43 #define NV_SOR_STATE0_UPDATE_DEFAULT_MASK                       (0x1)
44 #define NV_SOR_STATE0_UPDATE_UPDATE                             (0x1)
45 #define NV_SOR_STATE1                                           (0x4)
46 #define NV_SOR_STATE1_ASY_PIXELDEPTH_SHIFT                      (17)
47 #define NV_SOR_STATE1_ASY_PIXELDEPTH_DEFAULT_MASK               (0xf << 17)
48 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_16_422                 (1 << 17)
49 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_18_444                 (2 << 17)
50 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_20_422                 (3 << 17)
51 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_422                 (4 << 17)
52 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_24_444                 (5 << 17)
53 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_30_444                 (6 << 17)
54 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_32_422                 (7 << 17)
55 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_36_444                 (8 << 17)
56 #define NV_SOR_STATE1_ASY_PIXELDEPTH_BPP_48_444                 (9 << 17)
57 #define NV_SOR_STATE1_ASY_REPLICATE_SHIFT                       (15)
58 #define NV_SOR_STATE1_ASY_REPLICATE_DEFAULT_MASK                (0x3 << 15)
59 #define NV_SOR_STATE1_ASY_REPLICATE_OFF                         (0 << 15)
60 #define NV_SOR_STATE1_ASY_REPLICATE_X2                          (1 << 15)
61 #define NV_SOR_STATE1_ASY_REPLICATE_X4                          (2 << 15)
62 #define NV_SOR_STATE1_ASY_DEPOL_SHIFT                           (14)
63 #define NV_SOR_STATE1_ASY_DEPOL_DEFAULT_MASK                    (0x1 << 14)
64 #define NV_SOR_STATE1_ASY_DEPOL_POSITIVE_TRUE                   (0 << 14)
65 #define NV_SOR_STATE1_ASY_DEPOL_NEGATIVE_TRUE                   (1 << 14)
66 #define NV_SOR_STATE1_ASY_VSYNCPOL_SHIFT                        (13)
67 #define NV_SOR_STATE1_ASY_VSYNCPOL_DEFAULT_MASK                 (0x1 << 13)
68 #define NV_SOR_STATE1_ASY_VSYNCPOL_POSITIVE_TRUE                (0 << 13)
69 #define NV_SOR_STATE1_ASY_VSYNCPOL_NEGATIVE_TRUE                (1 << 13)
70 #define NV_SOR_STATE1_ASY_HSYNCPOL_SHIFT                        (12)
71 #define NV_SOR_STATE1_ASY_HSYNCPOL_DEFAULT_MASK                 (0x1 << 12)
72 #define NV_SOR_STATE1_ASY_HSYNCPOL_POSITIVE_TRUE                (0 << 12)
73 #define NV_SOR_STATE1_ASY_HSYNCPOL_NEGATIVE_TRUE                (1 << 12)
74 #define NV_SOR_STATE1_ASY_PROTOCOL_SHIFT                        (8)
75 #define NV_SOR_STATE1_ASY_PROTOCOL_DEFAULT_MASK                 (0xf << 8)
76 #define NV_SOR_STATE1_ASY_PROTOCOL_LVDS_CUSTOM                  (0 << 8)
77 #define NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_A                (1 << 8)
78 #define NV_SOR_STATE1_ASY_PROTOCOL_SINGLE_TMDS_B                (2 << 8)
79 #define NV_SOR_STATE1_ASY_PROTOCOL_DP_A                         (8 << 8)
80 #define NV_SOR_STATE1_ASY_PROTOCOL_DP_B                         (9 << 8)
81 #define NV_SOR_STATE1_ASY_PROTOCOL_CUSTOM                       (15 << 8)
82 #define NV_SOR_STATE1_ASY_CRCMODE_SHIFT                         (6)
83 #define NV_SOR_STATE1_ASY_CRCMODE_DEFAULT_MASK                  (0x3 << 6)
84 #define NV_SOR_STATE1_ASY_CRCMODE_ACTIVE_RASTER                 (0 << 6)
85 #define NV_SOR_STATE1_ASY_CRCMODE_COMPLETE_RASTER               (1 << 6)
86 #define NV_SOR_STATE1_ASY_CRCMODE_NON_ACTIVE_RASTER             (2 << 6)
87 #define NV_SOR_STATE1_ASY_SUBOWNER_SHIFT                        (4)
88 #define NV_SOR_STATE1_ASY_SUBOWNER_DEFAULT_MASK                 (0x3 << 4)
89 #define NV_SOR_STATE1_ASY_SUBOWNER_NONE                         (0 << 4)
90 #define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD0                     (1 << 4)
91 #define NV_SOR_STATE1_ASY_SUBOWNER_SUBHEAD1                     (2 << 4)
92 #define NV_SOR_STATE1_ASY_SUBOWNER_BOTH                         (3 << 4)
93 #define NV_SOR_STATE1_ASY_OWNER_SHIFT                           (0)
94 #define NV_SOR_STATE1_ASY_OWNER_DEFAULT_MASK                    (0xf)
95 #define NV_SOR_STATE1_ASY_OWNER_NONE                            (0)
96 #define NV_SOR_STATE1_ASY_OWNER_HEAD0                           (1)
97 #define NV_SOR_STATE1_ASY_OWNER_HEAD1                           (2)
98 #define NV_SOR_STATE1_ASY_OWNER_HEAD2                           (3)
99
100 #if defined(CONFIG_TEGRA_NVDISPLAY)
101 #define NV_HEAD_STATE0(i)                                       (0x151 + i)
102 #define NV_HEAD_STATE1(i)                                       (0x154 + i)
103 #define NV_HEAD_STATE2(i)                                       (0x157 + i)
104 #define NV_HEAD_STATE3(i)                                       (0x15a + i)
105 #define NV_HEAD_STATE4(i)                                       (0x15d + i)
106 #define NV_HEAD_STATE5(i)                                       (0x160 + i)
107 #else
108 #define NV_HEAD_STATE0(i)                                       (0x5 + i)
109 #define NV_HEAD_STATE1(i)                                       (0x7 + i)
110 #define NV_HEAD_STATE2(i)                                       (0x9 + i)
111 #define NV_HEAD_STATE3(i)                                       (0xb + i)
112 #define NV_HEAD_STATE4(i)                                       (0xd + i)
113 #define NV_HEAD_STATE5(i)                                       (0xf + i)
114 #endif
115
116 #define NV_HEAD_STATE0_INTERLACED_SHIFT                         (4)
117 #define NV_HEAD_STATE0_INTERLACED_DEFAULT_MASK                  (0x3 << 4)
118 #define NV_HEAD_STATE0_INTERLACED_PROGRESSIVE                   (0 << 4)
119 #define NV_HEAD_STATE0_INTERLACED_INTERLACED                    (1 << 4)
120 #define NV_HEAD_STATE0_RANGECOMPRESS_SHIFT                      (3)
121 #define NV_HEAD_STATE0_RANGECOMPRESS_DEFAULT_MASK               (0x1 << 3)
122 #define NV_HEAD_STATE0_RANGECOMPRESS_DISABLE                    (0 << 3)
123 #define NV_HEAD_STATE0_RANGECOMPRESS_ENABLE                     (1 << 3)
124 #define NV_HEAD_STATE0_DYNRANGE_SHIFT                           (2)
125 #define NV_HEAD_STATE0_DYNRANGE_DEFAULT_MASK                    (0x1 << 2)
126 #define NV_HEAD_STATE0_DYNRANGE_VESA                            (0 << 2)
127 #define NV_HEAD_STATE0_DYNRANGE_CEA                             (1 << 2)
128 #define NV_HEAD_STATE0_COLORSPACE_SHIFT                         (0)
129 #define NV_HEAD_STATE0_COLORSPACE_DEFAULT_MASK                  (0x3)
130 #define NV_HEAD_STATE0_COLORSPACE_RGB                           (0)
131 #define NV_HEAD_STATE0_COLORSPACE_YUV_601                       (1)
132 #define NV_HEAD_STATE0_COLORSPACE_YUV_709                       (2)
133
134 #define NV_HEAD_STATE1_VTOTAL_SHIFT                             (16)
135 #define NV_HEAD_STATE1_VTOTAL_DEFAULT_MASK                      (0x7fff  << 16)
136 #define NV_HEAD_STATE1_HTOTAL_SHIFT                             (0)
137 #define NV_HEAD_STATE1_HTOTAL_DEFAULT_MASK                      (0x7fff)
138
139 #define NV_HEAD_STATE2_VSYNC_END_SHIFT                          (16)
140 #define NV_HEAD_STATE2_VSYNC_END_DEFAULT_MASK                   (0x7fff << 16)
141 #define NV_HEAD_STATE2_HSYNC_END_SHIFT                          (0)
142 #define NV_HEAD_STATE2_HSYNC_END_DEFAULT_MASK                   (0x7fff)
143
144 #define NV_HEAD_STATE3_VBLANK_END_SHIFT                         (16)
145 #define NV_HEAD_STATE3_VBLANK_END_DEFAULT_MASK                  (0x7fff << 16)
146 #define NV_HEAD_STATE3_HBLANK_END_SHIFT                         (0)
147 #define NV_HEAD_STATE3_HBLANK_END_DEFAULT_MASK                  (0x7fff)
148
149 #define NV_HEAD_STATE4_VBLANK_START_SHIFT                       (16)
150 #define NV_HEAD_STATE4_VBLANK_START_DEFAULT_MASK                (0x7fff << 16)
151 #define NV_HEAD_STATE4_HBLANK_START_SHIFT                       (0)
152 #define NV_HEAD_STATE4_HBLANK_START_DEFAULT_MASK                (0x7fff)
153
154 #define NV_HEAD_STATE5_VBLANK_END_2_SHIFT                       (16)
155 #define NV_HEAD_STATE5_VBLANK_END_2_DEFAULT_MASK                (0x7fff << 16)
156 #define NV_HEAD_STATE5_HBLANK_END_2_SHIFT                       (0)
157 #define NV_HEAD_STATE5_HBLANK_END_2_DEFAULT_MASK                (0x7fff)
158
159 #define NV_SOR_CRC_CNTRL                                        (0x11)
160 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_SHIFT                   (0)
161 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DEFAULT_MASK            (0x1)
162 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_NO                      (0)
163 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_YES                     (1)
164 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_DIS                     (0)
165 #define NV_SOR_CRC_CNTRL_ARM_CRC_ENABLE_EN                      (1)
166 #define NV_SOR_CLK_CNTRL                                        (0x13)
167 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SHIFT                       (0)
168 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_MASK                        (0x3)
169 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK                 (0)
170 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_PCLK                   (1)
171 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK                (2)
172 #define NV_SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK                  (3)
173 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_SHIFT                    (2)
174 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_MASK                     (0x1f << 2)
175 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62                    (6 << 2)
176 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_LVDS                     (7 << 2)
177 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7                     (10 << 2)
178 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4                     (20 << 2)
179 #if defined(CONFIG_TEGRA_NVDISPLAY)
180 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_16                    (8 << 2)
181 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_43                    (9 << 2)
182 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G3_24                    (12 << 2)
183 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G4_32                    (16 << 2)
184 #define NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G8_1                     (30 << 2)
185 #endif
186
187 #define NV_SOR_CAP                                              (0x14)
188 #define NV_SOR_CAP_DP_A_SHIFT                                   (24)
189 #define NV_SOR_CAP_DP_A_DEFAULT_MASK                            (0x1 << 24)
190 #define NV_SOR_CAP_DP_A_FALSE                                   (0 << 24)
191 #define NV_SOR_CAP_DP_A_TRUE                                    (1 << 24)
192 #define NV_SOR_CAP_DP_B_SHIFT                                   (25)
193 #define NV_SOR_CAP_DP_B_DEFAULT_MASK                            (0x1 << 24)
194 #define NV_SOR_CAP_DP_B_FALSE                                   (0 << 24)
195 #define NV_SOR_CAP_DP_B_TRUE                                    (1 << 24)
196 #define NV_SOR_PWR                                              (0x15)
197 #define NV_SOR_PWR_SETTING_NEW_SHIFT                            (31)
198 #define NV_SOR_PWR_SETTING_NEW_DEFAULT_MASK                     (0x1 << 31)
199 #define NV_SOR_PWR_SETTING_NEW_DONE                             (0 << 31)
200 #define NV_SOR_PWR_SETTING_NEW_PENDING                          (1 << 31)
201 #define NV_SOR_PWR_SETTING_NEW_TRIGGER                          (1 << 31)
202 #define NV_SOR_PWR_MODE_SHIFT                                   (28)
203 #define NV_SOR_PWR_MODE_DEFAULT_MASK                            (0x1 << 28)
204 #define NV_SOR_PWR_MODE_NORMAL                                  (0 << 28)
205 #define NV_SOR_PWR_MODE_SAFE                                    (1 << 28)
206 #define NV_SOR_PWR_HALT_DELAY_SHIFT                             (24)
207 #define NV_SOR_PWR_HALT_DELAY_DEFAULT_MASK                      (0x1 << 24)
208 #define NV_SOR_PWR_HALT_DELAY_DONE                              (0 << 24)
209 #define NV_SOR_PWR_HALT_DELAY_ACTIVE                            (1 << 24)
210 #define NV_SOR_PWR_SAFE_START_SHIFT                             (17)
211 #define NV_SOR_PWR_SAFE_START_DEFAULT_MASK                      (0x1 << 17)
212 #define NV_SOR_PWR_SAFE_START_NORMAL                            (0 << 17)
213 #define NV_SOR_PWR_SAFE_START_ALT                               (1 << 17)
214 #define NV_SOR_PWR_SAFE_STATE_SHIFT                             (16)
215 #define NV_SOR_PWR_SAFE_STATE_DEFAULT_MASK                      (0x1 << 16)
216 #define NV_SOR_PWR_SAFE_STATE_PD                                (0 << 16)
217 #define NV_SOR_PWR_SAFE_STATE_PU                                (1 << 16)
218 #define NV_SOR_PWR_NORMAL_START_SHIFT                           (1)
219 #define NV_SOR_PWR_NORMAL_START_DEFAULT_MASK                    (0x1 << 1)
220 #define NV_SOR_PWR_NORMAL_START_NORMAL                          (0 << 16)
221 #define NV_SOR_PWR_NORMAL_START_ALT                             (1 << 16)
222 #define NV_SOR_PWR_NORMAL_STATE_SHIFT                           (0)
223 #define NV_SOR_PWR_NORMAL_STATE_DEFAULT_MASK                    (0x1)
224 #define NV_SOR_PWR_NORMAL_STATE_PD                              (0)
225 #define NV_SOR_PWR_NORMAL_STATE_PU                              (1)
226 #define NV_SOR_TEST                                             (0x16)
227 #define NV_SOR_TEST_TESTMUX_SHIFT                               (24)
228 #define NV_SOR_TEST_TESTMUX_DEFAULT_MASK                        (0xff << 24)
229 #define NV_SOR_TEST_TESTMUX_AVSS                                (0 << 24)
230 #define NV_SOR_TEST_TESTMUX_CLOCKIN                             (2 << 24)
231 #define NV_SOR_TEST_TESTMUX_PLL_VOL                             (4 << 24)
232 #define NV_SOR_TEST_TESTMUX_SLOWCLKINT                          (8 << 24)
233 #define NV_SOR_TEST_TESTMUX_AVDD                                (16 << 24)
234 #define NV_SOR_TEST_TESTMUX_VDDREG                              (32 << 24)
235 #define NV_SOR_TEST_TESTMUX_REGREF_VDDREG                       (64 << 24)
236 #define NV_SOR_TEST_TESTMUX_REGREF_AVDD                         (128 << 24)
237 #define NV_SOR_TEST_CRC_SHIFT                                   (23)
238 #define NV_SOR_TEST_CRC_DEFAULT_MASK                            (1 << 23)
239 #define NV_SOR_TEST_CRC_PRE_SERIALIZE                           (0 << 23)
240 #define NV_SOR_TEST_CRC_POST_DESERIALIZE                        (1 << 23)
241 #define NV_SOR_TEST_TPAT_SHIFT                                  (20)
242 #define NV_SOR_TEST_TPAT_DEFAULT_MASK                           (0x7 << 20)
243 #define NV_SOR_TEST_TPAT_LO                                     (0 << 20)
244 #define NV_SOR_TEST_TPAT_TDAT                                   (1 << 20)
245 #define NV_SOR_TEST_TPAT_RAMP                                   (2 << 20)
246 #define NV_SOR_TEST_TPAT_WALK                                   (3 << 20)
247 #define NV_SOR_TEST_TPAT_MAXSTEP                                (4 << 20)
248 #define NV_SOR_TEST_TPAT_MINSTEP                                (5 << 20)
249 #define NV_SOR_TEST_DSRC_SHIFT                                  (16)
250 #define NV_SOR_TEST_DSRC_DEFAULT_MASK                           (0x3 << 16)
251 #define NV_SOR_TEST_DSRC_NORMAL                                 (0 << 16)
252 #define NV_SOR_TEST_DSRC_DEBUG                                  (1 << 16)
253 #define NV_SOR_TEST_DSRC_TGEN                                   (2 << 16)
254 #define NV_SOR_TEST_HEAD_NUMBER_SHIFT                           (12)
255 #define NV_SOR_TEST_HEAD_NUMBER_DEFAULT_MASK                    (0x3 << 12)
256 #define NV_SOR_TEST_HEAD_NUMBER_NONE                            (0 << 12)
257 #define NV_SOR_TEST_HEAD_NUMBER_HEAD0                           (1 << 12)
258 #define NV_SOR_TEST_HEAD_NUMBER_HEAD1                           (2 << 12)
259 #define NV_SOR_TEST_HEAD_NUMBER_HEAD2                           (3 << 12)
260 #define NV_SOR_TEST_ATTACHED_SHIFT                              (10)
261 #define NV_SOR_TEST_ATTACHED_DEFAULT_MASK                       (0x1  << 10)
262 #define NV_SOR_TEST_ATTACHED_FALSE                              (0 << 10)
263 #define NV_SOR_TEST_ATTACHED_TRUE                               (1 << 10)
264 #define NV_SOR_TEST_ACT_HEAD_OPMODE_SHIFT                       (8)
265 #define NV_SOR_TEST_ACT_HEAD_OPMODE_DEFAULT_MASK                (0x3 << 8)
266 #define NV_SOR_TEST_ACT_HEAD_OPMODE_SLEEP                       (0 << 8)
267 #define NV_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE                      (1 << 8)
268 #define NV_SOR_TEST_ACT_HEAD_OPMODE_AWAKE                       (2 << 8)
269 #define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK                      (7)
270 #define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_MASK                 (0x1 << 7)
271 #define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_ENABLE               (1 << 7)
272 #define NV_SOR_TEST_ACT_HEAD_DEEP_LOOPBACK_DISABLE              (0 << 7)
273 #define NV_SOR_TEST_INVD_SHIFT                                  (6)
274 #define NV_SOR_TEST_INVD_DISABLE                                (0 << 6)
275 #define NV_SOR_TEST_INVD_ENABLE                                 (1 << 6)
276 #define NV_SOR_TEST_TEST_ENABLE_SHIFT                           (1)
277 #define NV_SOR_TEST_TEST_ENABLE_DISABLE                         (0 << 1)
278 #define NV_SOR_TEST_TEST_ENABLE_ENABLE                          (1 << 1)
279
280 #if defined(CONFIG_TEGRA_NVDISPLAY)
281 #define NV_SOR_PLL0                                             (0x163)
282 #define NV_SOR_PLL1                                             (0x164)
283 #define NV_SOR_PLL2                                             (0x165)
284 #define NV_SOR_PLL3                                             (0x166)
285 #define NV_SOR_PLL4                                             (0x167)
286 #else
287 #define NV_SOR_PLL0                                             (0x17)
288 #define NV_SOR_PLL1                                             (0x18)
289 #define NV_SOR_PLL2                                             (0x19)
290 #define NV_SOR_PLL3                                             (0x1a)
291 #endif
292
293 #define NV_SOR_PLL0_ICHPMP_SHFIT                                (24)
294 #define NV_SOR_PLL0_ICHPMP_DEFAULT_MASK                         (0xf << 24)
295 #define NV_SOR_PLL0_FILTER_SHIFT                                (16)
296 #define NV_SOR_PLL0_FILTER_DEFAULT_MASK                         (0xf << 16)
297 #define NV_SOR_PLL0_TXREG_LEVEL_SHIFT                           (12)
298 #define NV_SOR_PLL0_TXREG_LEVEL_DEFAULT_MASK                    (0x3 << 12)
299 #define NV_SOR_PLL0_TXREG_LEVEL_V25                             (0 << 12)
300 #define NV_SOR_PLL0_TXREG_LEVEL_V15                             (1 << 12)
301 #define NV_SOR_PLL0_TXREG_LEVEL_V35                             (2 << 12)
302 #define NV_SOR_PLL0_TXREG_LEVEL_V45                             (3 << 12)
303 #define NV_SOR_PLL0_VCOCAP_SHIFT                                (8)
304 #define NV_SOR_PLL0_VCOCAP_DEFAULT_MASK                         (0xf << 8)
305 #define NV_SOR_PLL0_PLLREG_LEVEL_SHIFT                          (6)
306 #define NV_SOR_PLL0_PLLREG_LEVEL_DEFAULT_MASK                   (0x3 << 6)
307 #define NV_SOR_PLL0_PLLREG_LEVEL_V25                            (0 << 6)
308 #define NV_SOR_PLL0_PLLREG_LEVEL_V15                            (1 << 6)
309 #define NV_SOR_PLL0_PLLREG_LEVEL_V35                            (2 << 6)
310 #define NV_SOR_PLL0_PLLREG_LEVEL_V45                            (3 << 6)
311 #define NV_SOR_PLL0_PULLDOWN_SHIFT                              (5)
312 #define NV_SOR_PLL0_PULLDOWN_DEFAULT_MASK                       (0x1 << 5)
313 #define NV_SOR_PLL0_PULLDOWN_DISABLE                            (0 << 5)
314 #define NV_SOR_PLL0_PULLDOWN_ENABLE                             (1 << 5)
315 #define NV_SOR_PLL0_RESISTORSEL_SHIFT                           (4)
316 #define NV_SOR_PLL0_RESISTORSEL_DEFAULT_MASK                    (0x1 << 4)
317 #define NV_SOR_PLL0_RESISTORSEL_INT                             (0 << 4)
318 #define NV_SOR_PLL0_RESISTORSEL_EXT                             (1 << 4)
319 #define NV_SOR_PLL0_VCOPD_SHIFT                                 (2)
320 #define NV_SOR_PLL0_VCOPD_MASK                                  (1 << 2)
321 #define NV_SOR_PLL0_VCOPD_RESCIND                               (0 << 2)
322 #define NV_SOR_PLL0_VCOPD_ASSERT                                (1 << 2)
323 #define NV_SOR_PLL0_PWR_SHIFT                                   (0)
324 #define NV_SOR_PLL0_PWR_MASK                                    (1)
325 #define NV_SOR_PLL0_PWR_ON                                      (0)
326 #define NV_SOR_PLL0_PWR_OFF                                     (1)
327
328 #define NV_SOR_PLL1_COHERENTMODE                                (29)
329 #define NV_SOR_PLL1_COHERENTMODE_DEFAULT_MASK                   (0x1 << 29)
330 #define NV_SOR_PLL1_COHERENTMODE_DISABLE                        (0x0 << 29)
331 #define NV_SOR_PLL1_COHERENTMODE_ENABLE                         (0x1 << 29)
332 #define NV_SOR_PLL1_LVDSCM_SHIFT                                (24)
333 #define NV_SOR_PLL1_LVDSCM_DEFAULT_MASK                         (0x3 << 24)
334 #define NV_SOR_PLL1_LOADADJ_SHIFT                               (20)
335 #define NV_SOR_PLL1_LOADADJ_DEFAULT_MASK                        (0xf << 20)
336 #define NV_SOR_PLL1_TERM_COMPOUT_SHIFT                          (15)
337 #define NV_SOR_PLL1_TERM_COMPOUT_LOW                            (0 << 15)
338 #define NV_SOR_PLL1_TERM_COMPOUT_HIGH                           (1 << 15)
339 #define NV_SOR_PLL1_TMDS_TERMADJ_SHIFT                          (9)
340 #define NV_SOR_PLL1_TMDS_TERMADJ_OHM500                         (8 << 9)
341 #define NV_SOR_PLL1_TMDS_TERMADJ_DEFAULT_MASK                   (0xf << 9)
342 #define NV_SOR_PLL1_TMDS_TERM_SHIFT                             (8)
343 #define NV_SOR_PLL1_TMDS_TERM_DISABLE                           (0 << 8)
344 #define NV_SOR_PLL1_TMDS_TERM_ENABLE                            (1 << 8)
345 #define NV_SOR_PLL1_TMDS_IOCURRENT                              (0)
346 #define NV_SOR_PLL1_TMDS_IOCURRENT_DEFAULT_MASK                 (0x1f << 0)
347 #define NV_SOR_PLL1_TMDS_IOCURRENT_RST                          (0)
348
349 #define NV_SOR_PLL2_DCIR_PLL_RESET_SHIFT                        (0)
350 #define NV_SOR_PLL2_DCIR_PLL_RESET_OVERRIDE                     (0 << 0)
351 #define NV_SOR_PLL2_DCIR_PLL_RESET_ALLOW                        (1 << 0)
352 #define NV_SOR_PLL2_PLL_PDIV_MODE                               (2)
353 #define NV_SOR_PLL2_PLL_PDIV_MODE_MASK                          (0x3 << 4)
354 #define NV_SOR_PLL2_PLL_PDIV                                    (4)
355 #define NV_SOR_PLL2_PLL_PDIV_MASK                               (0xf << 4)
356 #define NV_SOR_PLL2_PLL_NDIV                                    (8)
357 #define NV_SOR_PLL2_PLL_NDIV_MASK                               (0xff << 8)
358 #define NV_SOR_PLL2_AUX0_SHIFT                                  (16)
359 #define NV_SOR_PLL2_AUX0_MASK                                   (1 << 16)
360 #define NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_ALLOW                 (0 << 16)
361 #define NV_SOR_PLL2_AUX0_SEQ_PLL_PULLDOWN_OVERRIDE              (1 << 16)
362 #define NV_SOR_PLL2_AUX1_SHIFT                                  (17)
363 #define NV_SOR_PLL2_AUX1_SEQ_MASK                               (1 << 17)
364 #define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_ALLOW                     (0 << 17)
365 #define NV_SOR_PLL2_AUX1_SEQ_PLLCAPPD_OVERRIDE                  (1 << 17)
366 #define NV_SOR_PLL2_AUX2_SHIFT                                  (18)
367 #define NV_SOR_PLL2_AUX2_MASK                                   (1 << 18)
368 #define NV_SOR_PLL2_AUX2_OVERRIDE_POWERDOWN                     (0 << 18)
369 #define NV_SOR_PLL2_AUX2_ALLOW_POWERDOWN                        (1 << 18)
370 #define NV_SOR_PLL2_AUX3_SHIFT                                  (19)
371 #define NV_SOR_PLL2_AUX3_MASK                                   (1 << 19)
372 #define NV_SOR_PLL2_AUX3_ROTATE_DISABLE                         (0 << 19)
373 #define NV_SOR_PLL2_AUX3_ROTATE_ENABLE                          (1 << 19)
374 #define NV_SOR_PLL2_AUX6_SHIFT                                  (22)
375 #define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_MASK                 (1 << 22)
376 #define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_DISABLE              (0 << 22)
377 #define NV_SOR_PLL2_AUX6_BANDGAP_POWERDOWN_ENABLE               (1 << 22)
378 #define NV_SOR_PLL2_AUX7_SHIFT                                  (23)
379 #define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_MASK                    (1 << 23)
380 #define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_DISABLE                 (0 << 23)
381 #define NV_SOR_PLL2_AUX7_PORT_POWERDOWN_ENABLE                  (1 << 23)
382 #define NV_SOR_PLL2_AUX8_SHIFT                                  (24)
383 #define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_MASK              (1 << 24)
384 #define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_DISABLE           (0 << 24)
385 #define NV_SOR_PLL2_AUX8_SEQ_PLLCAPPD_ENFORCE_ENABLE            (1 << 24)
386 #define NV_SOR_PLL2_AUX9_SHIFT                                  (25)
387 #define NV_SOR_PLL2_AUX9_LVDSEN_ALLOW                           (0 << 25)
388 #define NV_SOR_PLL2_AUX9_LVDSEN_OVERRIDE                        (1 << 25)
389 #define NV_SOR_PLL2_CLKGEN_MODE                                 (26)
390 #define NV_SOR_PLL2_CLKGEN_MODE_MASK                            (0x3 << 26)
391 #define NV_SOR_PLL2_CLKGEN_MODE_DP_TMDS                         (1 << 26)
392 #define NV_SOR_PLL2_CLKGEN_MODE_LVDS                            (0 << 26)
393 #define NV_SOR_PLL2_PLL_MDIV                                    (28)
394 #define NV_SOR_PLL2_PLL_MDIV_MASK                               (0xf << 28)
395
396 #define NV_SOR_PLL3_BG_TEMP_COEFF_SHIFT                         (28)
397 #define NV_SOR_PLL3_BG_TEMP_COEFF_MASK                          (0xf << 28)
398 #define NV_SOR_PLL3_BG_VREF_LEVEL_SHIFT                         (24)
399 #define NV_SOR_PLL3_BG_VREF_LEVEL_MASK                          (0xf << 24)
400 #define NV_SOR_PLL3_PLL_BYPASS_SHIFT                            (14)
401 #define NV_SOR_PLL3_PLL_BYPASS_MASK                             (1 << 14)
402 #define NV_SOR_PLL3_PLL_BYPASS_DISABLE                          (0 << 14)
403 #define NV_SOR_PLL3_PLL_BYPASS_ENABLE                           (1 << 14)
404 #define NV_SOR_PLL3_PLLVDD_MODE_SHIFT                           (13)
405 #define NV_SOR_PLL3_PLLVDD_MODE_MASK                            (1 << 13)
406 #define NV_SOR_PLL3_PLLVDD_MODE_V1_8                            (0 << 13)
407 #define NV_SOR_PLL3_PLLVDD_MODE_V3_3                            (1 << 13)
408
409 #define NV_SOR_CSTM                                             (0x1b)
410 #define NV_SOR_CSTM_ROTDAT_SHIFT                                (28)
411 #define NV_SOR_CSTM_ROTDAT_DEFAULT_MASK                         (0x7 << 28)
412 #define NV_SOR_CSTM_ROTCLK_SHIFT                                (24)
413 #define NV_SOR_CSTM_ROTCLK_DEFAULT_MASK                         (0xf << 24)
414 #define NV_SOR_CSTM_PLLDIV_SHIFT                                (21)
415 #define NV_SOR_CSTM_PLLDIV_DEFAULT_MASK                         (0x1 << 21)
416 #define NV_SOR_CSTM_LVDS_EN_SHIFT                               (16)
417 #define NV_SOR_CSTM_LVDS_EN_DISABLE                             (0 << 16)
418 #define NV_SOR_CSTM_LVDS_EN_ENABLE                              (1 << 16)
419 #define NV_SOR_CSTM_LINKACTB_SHIFT                              (15)
420 #define NV_SOR_CSTM_LINKACTB_DISABLE                            (0 << 15)
421 #define NV_SOR_CSTM_LINKACTB_ENABLE                             (1 << 15)
422 #define NV_SOR_CSTM_LINKACTA_SHIFT                              (14)
423 #define NV_SOR_CSTM_LINKACTA_DISABLE                            (0 << 14)
424 #define NV_SOR_CSTM_LINKACTA_ENABLE                             (1 << 14)
425 #define NV_SOR_LVDS                                             (0x1c)
426 #define NV_SOR_LVDS_ROTDAT_SHIFT                                (28)
427 #define NV_SOR_LVDS_ROTDAT_DEFAULT_MASK                         (0x7 << 28)
428 #define NV_SOR_LVDS_ROTDAT_RST                                  (0 << 28)
429 #define NV_SOR_LVDS_ROTCLK_SHIFT                                (24)
430 #define NV_SOR_LVDS_ROTCLK_DEFAULT_MASK                         (0xf << 24)
431 #define NV_SOR_LVDS_ROTCLK_RST                                  (0 << 24)
432 #define NV_SOR_LVDS_PLLDIV_SHIFT                                (21)
433 #define NV_SOR_LVDS_PLLDIV_DEFAULT_MASK                         (0x1 << 21)
434 #define NV_SOR_LVDS_PLLDIV_BY_7                                 (0 << 21)
435 #define NV_SOR_LVDS_BALANCED_SHIFT                              (19)
436 #define NV_SOR_LVDS_BALANCED_DEFAULT_MASK                       (0x1 << 19)
437 #define NV_SOR_LVDS_BALANCED_DISABLE                            (0 << 19)
438 #define NV_SOR_LVDS_BALANCED_ENABLE                             (1 << 19)
439 #define NV_SOR_LVDS_NEW_MODE_SHIFT                              (18)
440 #define NV_SOR_LVDS_NEW_MODE_DEFAULT_MASK                       (0x1 << 18)
441 #define NV_SOR_LVDS_NEW_MODE_DISABLE                            (0 << 18)
442 #define NV_SOR_LVDS_NEW_MODE_ENABLE                             (1 << 18)
443 #define NV_SOR_LVDS_DUP_SYNC_SHIFT                              (17)
444 #define NV_SOR_LVDS_DUP_SYNC_DEFAULT_MASK                       (0x1 << 17)
445 #define NV_SOR_LVDS_DUP_SYNC_DISABLE                            (0 << 17)
446 #define NV_SOR_LVDS_DUP_SYNC_ENABLE                             (1 << 17)
447 #define NV_SOR_LVDS_LVDS_EN_SHIFT                               (16)
448 #define NV_SOR_LVDS_LVDS_EN_DEFAULT_MASK                        (0x1 << 16)
449 #define NV_SOR_LVDS_LVDS_EN_ENABLE                              (1 << 16)
450 #define NV_SOR_LVDS_LINKACTB_SHIFT                              (15)
451 #define NV_SOR_LVDS_LINKACTB_DEFAULT_MASK                       (0x1 << 15)
452 #define NV_SOR_LVDS_LINKACTB_DISABLE                            (0 << 15)
453 #define NV_SOR_LVDS_LINKACTB_ENABLE                             (1 << 15)
454 #define NV_SOR_LVDS_LINKACTA_SHIFT                              (14)
455 #define NV_SOR_LVDS_LINKACTA_DEFAULT_MASK                       (0x1 << 14)
456 #define NV_SOR_LVDS_LINKACTA_ENABLE                             (1 << 14)
457 #define NV_SOR_LVDS_MODE_SHIFT                                  (12)
458 #define NV_SOR_LVDS_MODE_DEFAULT_MASK                           (0x3 << 12)
459 #define NV_SOR_LVDS_MODE_LVDS                                   (0 << 12)
460 #define NV_SOR_LVDS_UPPER_SHIFT                                 (11)
461 #define NV_SOR_LVDS_UPPER_DEFAULT_MASK                          (0x1 << 11)
462 #define NV_SOR_LVDS_UPPER_FALSE                                 (0 << 11)
463 #define NV_SOR_LVDS_UPPER_TRUE                                  (1 << 11)
464 #define NV_SOR_LVDS_PD_TXCB_SHIFT                               (9)
465 #define NV_SOR_LVDS_PD_TXCB_DEFAULT_MASK                        (0x1 << 9)
466 #define NV_SOR_LVDS_PD_TXCB_ENABLE                              (0 << 9)
467 #define NV_SOR_LVDS_PD_TXCB_DISABLE                             (1 << 9)
468 #define NV_SOR_LVDS_PD_TXCA_SHIFT                               (8)
469 #define NV_SOR_LVDS_PD_TXCA_DEFAULT_MASK                        (0x1 << 8)
470 #define NV_SOR_LVDS_PD_TXCA_ENABLE                              (0 << 8)
471 #define NV_SOR_LVDS_PD_TXDB_3_SHIFT                             (7)
472 #define NV_SOR_LVDS_PD_TXDB_3_DEFAULT_MASK                      (0x1 << 7)
473 #define NV_SOR_LVDS_PD_TXDB_3_ENABLE                            (0 << 7)
474 #define NV_SOR_LVDS_PD_TXDB_3_DISABLE                           (1 << 7)
475 #define NV_SOR_LVDS_PD_TXDB_2_SHIFT                             (6)
476 #define NV_SOR_LVDS_PD_TXDB_2_DEFAULT_MASK                      (0x1 << 6)
477 #define NV_SOR_LVDS_PD_TXDB_2_ENABLE                            (0 << 6)
478 #define NV_SOR_LVDS_PD_TXDB_2_DISABLE                           (1 << 6)
479 #define NV_SOR_LVDS_PD_TXDB_1_SHIFT                             (5)
480 #define NV_SOR_LVDS_PD_TXDB_1_DEFAULT_MASK                      (0x1 << 5)
481 #define NV_SOR_LVDS_PD_TXDB_1_ENABLE                            (0 << 5)
482 #define NV_SOR_LVDS_PD_TXDB_1_DISABLE                           (1 << 5)
483 #define NV_SOR_LVDS_PD_TXDB_0_SHIFT                             (4)
484 #define NV_SOR_LVDS_PD_TXDB_0_DEFAULT_MASK                      (0x1 << 4)
485 #define NV_SOR_LVDS_PD_TXDB_0_ENABLE                            (0 << 4)
486 #define NV_SOR_LVDS_PD_TXDB_0_DISABLE                           (1 << 4)
487 #define NV_SOR_LVDS_PD_TXDA_3_SHIFT                             (3)
488 #define NV_SOR_LVDS_PD_TXDA_3_DEFAULT_MASK                      (0x1 << 3)
489 #define NV_SOR_LVDS_PD_TXDA_3_ENABLE                            (0 << 3)
490 #define NV_SOR_LVDS_PD_TXDA_3_DISABLE                           (1 << 3)
491 #define NV_SOR_LVDS_PD_TXDA_2_SHIFT                             (2)
492 #define NV_SOR_LVDS_PD_TXDA_2_DEFAULT_MASK                      (0x1 << 2)
493 #define NV_SOR_LVDS_PD_TXDA_2_ENABLE                            (0 << 2)
494 #define NV_SOR_LVDS_PD_TXDA_1_SHIFT                             (1)
495 #define NV_SOR_LVDS_PD_TXDA_1_DEFAULT_MASK                      (0x1 << 1)
496 #define NV_SOR_LVDS_PD_TXDA_1_ENABLE                            (0 << 1)
497 #define NV_SOR_LVDS_PD_TXDA_0_SHIFT                             (0)
498 #define NV_SOR_LVDS_PD_TXDA_0_DEFAULT_MASK                      (0x1)
499 #define NV_SOR_LVDS_PD_TXDA_0_ENABLE                            (0)
500 #define NV_SOR_CRCA                                             (0x1d)
501 #define NV_SOR_CRCA_VALID_SHIFT                                 (0)
502 #define NV_SOR_CRCA_VALID_DEFAULT_MASK                          (1)
503 #define NV_SOR_CRCA_VALID_FALSE                                 (0)
504 #define NV_SOR_CRCA_VALID_TRUE                                  (1)
505 #define NV_SOR_CRCA_VALID_RST                                   (1)
506 #define NV_SOR_CRCB                                             (0x1e)
507 #define NV_SOR_CRCB_CRC_DEFAULT_MASK                            (0xffffffff)
508 #define NV_SOR_SEQ_CTL                                          (0x20)
509 #define NV_SOR_SEQ_CTL_SWITCH_SHIFT                             (30)
510 #define NV_SOR_SEQ_CTL_SWITCH_MASK                              (0x1 << 30)
511 #define NV_SOR_SEQ_CTL_SWITCH_WAIT                              (0 << 30)
512 #define NV_SOR_SEQ_CTL_SWITCH_FORCE                             (1 << 30)
513 #define NV_SOR_SEQ_CTL_STATUS_SHIFT                             (28)
514 #define NV_SOR_SEQ_CTL_STATUS_MASK                              (0x1 << 28)
515 #define NV_SOR_SEQ_CTL_STATUS_STOPPED                           (0 << 28)
516 #define NV_SOR_SEQ_CTL_STATUS_RUNNING                           (1 << 28)
517 #define NV_SOR_SEQ_CTL_PC_SHIFT                                 (16)
518 #define NV_SOR_SEQ_CTL_PC_MASK                                  (0xf << 16)
519 #define NV_SOR_SEQ_CTL_PD_PC_ALT_SHIFT                          (12)
520 #define NV_SOR_SEQ_CTL_PD_PC_ALT_MASK                           (0xf << 12)
521 #define NV_SOR_SEQ_CTL_PD_PC_SHIFT                              (8)
522 #define NV_SOR_SEQ_CTL_PD_PC_MASK                               (0xf << 8)
523 #define NV_SOR_SEQ_CTL_PU_PC_ALT_SHIFT                          (4)
524 #define NV_SOR_SEQ_CTL_PU_PC_ALT_MASK                           (0xf << 4)
525 #define NV_SOR_SEQ_CTL_PU_PC_SHIFT                              (0)
526 #define NV_SOR_SEQ_CTL_PU_PC_MASK                               (0xf)
527 #define NV_SOR_LANE_SEQ_CTL                                     (0x21)
528 #define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_SHIFT                   (31)
529 #define NV_SOR_LANE_SEQ_CTL_SETTING_MASK                        (1 << 31)
530 #define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_DONE                    (0 << 31)
531 #define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_PENDING                 (1 << 31)
532 #define NV_SOR_LANE_SEQ_CTL_SETTING_NEW_TRIGGER                 (1 << 31)
533 #define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_SHIFT                     (28)
534 #define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_IDLE                      (0 << 28)
535 #define NV_SOR_LANE_SEQ_CTL_SEQ_STATE_BUSY                      (1 << 28)
536 #define NV_SOR_LANE_SEQ_CTL_SEQUENCE_SHIFT                      (20)
537 #define NV_SOR_LANE_SEQ_CTL_SEQUENCE_UP                         (0 << 20)
538 #define NV_SOR_LANE_SEQ_CTL_SEQUENCE_DOWN                       (1 << 20)
539 #define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_SHIFT               (16)
540 #define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PU                  (0 << 16)
541 #define NV_SOR_LANE_SEQ_CTL_NEW_POWER_STATE_PD                  (1 << 16)
542 #define NV_SOR_LANE_SEQ_CTL_DELAY_SHIFT                         (12)
543 #define NV_SOR_LANE_SEQ_CTL_DELAY_DEFAULT_MASK                  (0xf << 12)
544 #define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_SHIFT                   (9)
545 #define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERUP                 (0 << 9)
546 #define NV_SOR_LANE_SEQ_CTL_LANE9_STATE_POWERDOWN               (1 << 9)
547 #define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_SHIFT                   (8)
548 #define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERUP                 (0 << 8)
549 #define NV_SOR_LANE_SEQ_CTL_LANE8_STATE_POWERDOWN               (1 << 8)
550 #define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_SHIFT                   (7)
551 #define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERUP                 (0 << 7)
552 #define NV_SOR_LANE_SEQ_CTL_LANE7_STATE_POWERDOWN               (1 << 7)
553 #define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_SHIFT                   (6)
554 #define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERUP                 (0 << 6)
555 #define NV_SOR_LANE_SEQ_CTL_LANE6_STATE_POWERDOWN               (1 << 6)
556 #define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_SHIFT                   (5)
557 #define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERUP                 (0 << 5)
558 #define NV_SOR_LANE_SEQ_CTL_LANE5_STATE_POWERDOWN               (1 << 5)
559 #define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_SHIFT                   (4)
560 #define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERUP                 (0 << 4)
561 #define NV_SOR_LANE_SEQ_CTL_LANE4_STATE_POWERDOWN               (1 << 4)
562 #define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_SHIFT                   (3)
563 #define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERUP                 (0 << 3)
564 #define NV_SOR_LANE_SEQ_CTL_LANE3_STATE_POWERDOWN               (1 << 3)
565 #define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_SHIFT                   (2)
566 #define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERUP                 (0 << 2)
567 #define NV_SOR_LANE_SEQ_CTL_LANE2_STATE_POWERDOWN               (1 << 2)
568 #define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_SHIFT                   (1)
569 #define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERUP                 (0 << 1)
570 #define NV_SOR_LANE_SEQ_CTL_LANE1_STATE_POWERDOWN               (1 << 1)
571 #define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_SHIFT                   (0)
572 #define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERUP                 (0)
573 #define NV_SOR_LANE_SEQ_CTL_LANE0_STATE_POWERDOWN               (1)
574
575 #define NV_SOR_SEQ_INST(i)                                      (0x22 + i)
576 #define NV_SOR_SEQ_INST_PLL_PULLDOWN_SHIFT                      (31)
577 #define NV_SOR_SEQ_INST_PLL_PULLDOWN_DISABLE                    (0 << 31)
578 #define NV_SOR_SEQ_INST_PLL_PULLDOWN_ENABLE                     (1 << 31)
579 #define NV_SOR_SEQ_INST_POWERDOWN_MACRO_SHIFT                   (30)
580 #define NV_SOR_SEQ_INST_POWERDOWN_MACRO_NORMAL                  (0 << 30)
581 #define NV_SOR_SEQ_INST_POWERDOWN_MACRO_POWERDOWN               (1 << 30)
582 #define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_SHIFT                  (29)
583 #define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_NORMAL                 (0 << 29)
584 #define NV_SOR_SEQ_INST_ASSERT_PLL_RESET_RST                    (1 << 29)
585 #define NV_SOR_SEQ_INST_BLANK_V_SHIFT                           (28)
586 #define NV_SOR_SEQ_INST_BLANK_V_NORMAL                          (0 << 28)
587 #define NV_SOR_SEQ_INST_BLANK_V_INACTIVE                        (1 << 28)
588 #define NV_SOR_SEQ_INST_BLANK_H_SHIFT                           (27)
589 #define NV_SOR_SEQ_INST_BLANK_H_NORMAL                          (0 << 27)
590 #define NV_SOR_SEQ_INST_BLANK_H_INACTIVE                        (1 << 27)
591 #define NV_SOR_SEQ_INST_BLANK_DE_SHIFT                          (26)
592 #define NV_SOR_SEQ_INST_BLANK_DE_NORMAL                         (0 << 26)
593 #define NV_SOR_SEQ_INST_BLANK_DE_INACTIVE                       (1 << 26)
594 #define NV_SOR_SEQ_INST_BLACK_DATA_SHIFT                        (25)
595 #define NV_SOR_SEQ_INST_BLACK_DATA_NORMAL                       (0 << 25)
596 #define NV_SOR_SEQ_INST_BLACK_DATA_BLACK                        (1 << 25)
597 #define NV_SOR_SEQ_INST_TRISTATE_IOS_SHIFT                      (24)
598 #define NV_SOR_SEQ_INST_TRISTATE_IOS_ENABLE_PINS                (0 << 24)
599 #define NV_SOR_SEQ_INST_TRISTATE_IOS_TRISTATE                   (1 << 24)
600 #define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_SHIFT                  (23)
601 #define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_FALSE                  (0 << 23)
602 #define NV_SOR_SEQ_INST_DRIVE_PWM_OUT_LO_TRUE                   (1 << 23)
603 #define NV_SOR_SEQ_INST_PIN_B_SHIFT                             (22)
604 #define NV_SOR_SEQ_INST_PIN_B_LOW                               (0 << 22)
605 #define NV_SOR_SEQ_INST_PIN_B_HIGH                              (1 << 22)
606 #define NV_SOR_SEQ_INST_PIN_A_SHIFT                             (21)
607 #define NV_SOR_SEQ_INST_PIN_A_LOW                               (0 << 21)
608 #define NV_SOR_SEQ_INST_PIN_A_HIGH                              (1 << 21)
609 #define NV_SOR_SEQ_INST_SEQUENCE_SHIFT                          (19)
610 #define NV_SOR_SEQ_INST_SEQUENCE_UP                             (0 << 19)
611 #define NV_SOR_SEQ_INST_SEQUENCE_DOWN                           (1 << 19)
612 #define NV_SOR_SEQ_INST_LANE_SEQ_SHIFT                          (18)
613 #define NV_SOR_SEQ_INST_LANE_SEQ_STOP                           (0 << 18)
614 #define NV_SOR_SEQ_INST_LANE_SEQ_RUN                            (1 << 18)
615 #define NV_SOR_SEQ_INST_PDPORT_SHIFT                            (17)
616 #define NV_SOR_SEQ_INST_PDPORT_NO                               (0 << 17)
617 #define NV_SOR_SEQ_INST_PDPORT_YES                              (1 << 17)
618 #define NV_SOR_SEQ_INST_PDPLL_SHIFT                             (16)
619 #define NV_SOR_SEQ_INST_PDPLL_NO                                (0 << 16)
620 #define NV_SOR_SEQ_INST_PDPLL_YES                               (1 << 16)
621 #define NV_SOR_SEQ_INST_HALT_SHIFT                              (15)
622 #define NV_SOR_SEQ_INST_HALT_FALSE                              (0 << 15)
623 #define NV_SOR_SEQ_INST_HALT_TRUE                               (1 << 15)
624 #define NV_SOR_SEQ_INST_WAIT_UNITS_SHIFT                        (12)
625 #define NV_SOR_SEQ_INST_WAIT_UNITS_DEFAULT_MASK                 (0x3 << 12)
626 #define NV_SOR_SEQ_INST_WAIT_UNITS_US                           (0 << 12)
627 #define NV_SOR_SEQ_INST_WAIT_UNITS_MS                           (1 << 12)
628 #define NV_SOR_SEQ_INST_WAIT_UNITS_VSYNC                        (2 << 12)
629 #define NV_SOR_SEQ_INST_WAIT_TIME_SHIFT                         (0)
630 #define NV_SOR_SEQ_INST_WAIT_TIME_DEFAULT_MASK                  (0x3ff)
631 #define NV_SOR_PWM_DIV                                          (0x32)
632 #define NV_SOR_PWM_DIV_DIVIDE_DEFAULT_MASK                      (0xffffff)
633 #define NV_SOR_PWM_CTL                                          (0x33)
634 #define NV_SOR_PWM_CTL_SETTING_NEW_SHIFT                        (31)
635 #define NV_SOR_PWM_CTL_SETTING_NEW_DONE                         (0 << 31)
636 #define NV_SOR_PWM_CTL_SETTING_NEW_PENDING                      (1 << 31)
637 #define NV_SOR_PWM_CTL_SETTING_NEW_TRIGGER                      (1 << 31)
638 #define NV_SOR_PWM_CTL_CLKSEL_SHIFT                             (30)
639 #define NV_SOR_PWM_CTL_CLKSEL_PCLK                              (0 << 30)
640 #define NV_SOR_PWM_CTL_CLKSEL_XTAL                              (1 << 30)
641 #define NV_SOR_PWM_CTL_DUTY_CYCLE_SHIFT                         (0)
642 #define NV_SOR_PWM_CTL_DUTY_CYCLE_MASK                          (0xffffff)
643 #define NV_SOR_MSCHECK                                          (0x49)
644 #define NV_SOR_MSCHECK_CTL_SHIFT                                (31)
645 #define NV_SOR_MSCHECK_CTL_CLEAR                                (0 << 31)
646 #define NV_SOR_MSCHECK_CTL_RUN                                  (1 << 31)
647 #define NV_SOR_XBAR_CTRL                                        (0x4a)
648 #define NV_SOR_XBAR_BYPASS_MASK                                 (1 << 0)
649 #define NV_SOR_XBAR_LINK_SWAP_MASK                              (1 << 1)
650 #define NV_SOR_XBAR_LINK_XSEL_MASK                              (0x7)
651 #define NV_SOR_XBAR_POL                                         (0x4b)
652 #define NV_SOR_DP_LINKCTL(i)                                    (0x4c + (i))
653 #define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_SHIFT                 (31)
654 #define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO                    (0 << 31)
655 #define NV_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES                   (1 << 31)
656 #define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_SHIFT                 (28)
657 #define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_NOPATTERN             (0 << 28)
658 #define NV_SOR_DP_LINKCTL_COMPLIANCEPTTRN_COLORSQARE            (1 << 28)
659 #define NV_SOR_DP_LINKCTL_LANECOUNT_SHIFT                       (16)
660 #define NV_SOR_DP_LINKCTL_LANECOUNT_MASK                        (0x1f << 16)
661 #define NV_SOR_DP_LINKCTL_LANECOUNT_ZERO                        (0 << 16)
662 #define NV_SOR_DP_LINKCTL_LANECOUNT_ONE                         (1 << 16)
663 #define NV_SOR_DP_LINKCTL_LANECOUNT_TWO                         (3 << 16)
664 #define NV_SOR_DP_LINKCTL_LANECOUNT_FOUR                        (15 << 16)
665 #define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_SHIFT                   (14)
666 #define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE                 (0 << 14)
667 #define NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE                  (1 << 14)
668 #define NV_SOR_DP_LINKCTL_SYNCMODE_SHIFT                        (10)
669 #define NV_SOR_DP_LINKCTL_SYNCMODE_DISABLE                      (0 << 10)
670 #define NV_SOR_DP_LINKCTL_SYNCMODE_ENABLE                       (1 << 10)
671 #define NV_SOR_DP_LINKCTL_TUSIZE_SHIFT                          (2)
672 #define NV_SOR_DP_LINKCTL_TUSIZE_MASK                           (0x7f << 2)
673 #define NV_SOR_DP_LINKCTL_ENABLE_SHIFT                          (0)
674 #define NV_SOR_DP_LINKCTL_ENABLE_NO                             (0)
675 #define NV_SOR_DP_LINKCTL_ENABLE_YES                            (1)
676 #define NV_SOR_DC(i)                                            (0x4e + (i))
677 #define NV_SOR_DC_LANE3_DP_LANE3_SHIFT                          (24)
678 #define NV_SOR_DC_LANE3_DP_LANE3_MASK                           (0xff << 24)
679 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL0                      (17 << 24)
680 #define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL0                      (21 << 24)
681 #define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL0                      (26 << 24)
682 #define NV_SOR_DC_LANE3_DP_LANE3_P3_LEVEL0                      (34 << 24)
683 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL1                      (26 << 24)
684 #define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL1                      (32 << 24)
685 #define NV_SOR_DC_LANE3_DP_LANE3_P2_LEVEL1                      (39 << 24)
686 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL2                      (34 << 24)
687 #define NV_SOR_DC_LANE3_DP_LANE3_P1_LEVEL2                      (43 << 24)
688 #define NV_SOR_DC_LANE3_DP_LANE3_P0_LEVEL3                      (51 << 24)
689 #define NV_SOR_DC_LANE2_DP_LANE0_SHIFT                          (16)
690 #define NV_SOR_DC_LANE2_DP_LANE0_MASK                           (0xff << 16)
691 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL0                      (17 << 16)
692 #define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL0                      (21 << 16)
693 #define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL0                      (26 << 16)
694 #define NV_SOR_DC_LANE2_DP_LANE0_P3_LEVEL0                      (34 << 16)
695 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL1                      (26 << 16)
696 #define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL1                      (32 << 16)
697 #define NV_SOR_DC_LANE2_DP_LANE0_P2_LEVEL1                      (39 << 16)
698 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL2                      (34 << 16)
699 #define NV_SOR_DC_LANE2_DP_LANE0_P1_LEVEL2                      (43 << 16)
700 #define NV_SOR_DC_LANE2_DP_LANE0_P0_LEVEL3                      (51 << 16)
701 #define NV_SOR_DC_LANE1_DP_LANE1_SHIFT                          (8)
702 #define NV_SOR_DC_LANE1_DP_LANE1_MASK                           (0xff << 8)
703 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL0                      (17 << 8)
704 #define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL0                      (21 << 8)
705 #define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL0                      (26 << 8)
706 #define NV_SOR_DC_LANE1_DP_LANE1_P3_LEVEL0                      (34 << 8)
707 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL1                      (26 << 8)
708 #define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL1                      (32 << 8)
709 #define NV_SOR_DC_LANE1_DP_LANE1_P2_LEVEL1                      (39 << 8)
710 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL2                      (34 << 8)
711 #define NV_SOR_DC_LANE1_DP_LANE1_P1_LEVEL2                      (43 << 8)
712 #define NV_SOR_DC_LANE1_DP_LANE1_P0_LEVEL3                      (51 << 8)
713 #define NV_SOR_DC_LANE0_DP_LANE2_SHIFT                          (0)
714 #define NV_SOR_DC_LANE0_DP_LANE2_MASK                           (0xff)
715 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL0                      (17)
716 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL0                      (21)
717 #define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL0                      (26)
718 #define NV_SOR_DC_LANE0_DP_LANE2_P3_LEVEL0                      (34)
719 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL1                      (26)
720 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL1                      (32)
721 #define NV_SOR_DC_LANE0_DP_LANE2_P2_LEVEL1                      (39)
722 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL2                      (34)
723 #define NV_SOR_DC_LANE0_DP_LANE2_P1_LEVEL2                      (43)
724 #define NV_SOR_DC_LANE0_DP_LANE2_P0_LEVEL3                      (51)
725 #define NV_SOR_LANE_DRIVE_CURRENT(i)                            (0x4e + (i))
726 #define NV_SOR_PR(i)                                            (0x52 + (i))
727 #define NV_SOR_PR_LANE3_DP_LANE3_SHIFT                          (24)
728 #define NV_SOR_PR_LANE3_DP_LANE3_MASK                           (0xff << 24)
729 #define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL0                      (0 << 24)
730 #define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL0                      (0 << 24)
731 #define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL0                      (0 << 24)
732 #define NV_SOR_PR_LANE3_DP_LANE3_D3_LEVEL0                      (0 << 24)
733 #define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL1                      (4 << 24)
734 #define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL1                      (6 << 24)
735 #define NV_SOR_PR_LANE3_DP_LANE3_D2_LEVEL1                      (17 << 24)
736 #define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL2                      (8 << 24)
737 #define NV_SOR_PR_LANE3_DP_LANE3_D1_LEVEL2                      (13 << 24)
738 #define NV_SOR_PR_LANE3_DP_LANE3_D0_LEVEL3                      (17 << 24)
739 #define NV_SOR_PR_LANE2_DP_LANE0_SHIFT                          (16)
740 #define NV_SOR_PR_LANE2_DP_LANE0_MASK                           (0xff << 16)
741 #define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL0                      (0 << 16)
742 #define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL0                      (0 << 16)
743 #define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL0                      (0 << 16)
744 #define NV_SOR_PR_LANE2_DP_LANE0_D3_LEVEL0                      (0 << 16)
745 #define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL1                      (4 << 16)
746 #define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL1                      (6 << 16)
747 #define NV_SOR_PR_LANE2_DP_LANE0_D2_LEVEL1                      (17 << 16)
748 #define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL2                      (8 << 16)
749 #define NV_SOR_PR_LANE2_DP_LANE0_D1_LEVEL2                      (13 << 16)
750 #define NV_SOR_PR_LANE2_DP_LANE0_D0_LEVEL3                      (17 << 16)
751 #define NV_SOR_PR_LANE1_DP_LANE1_SHIFT                          (8)
752 #define NV_SOR_PR_LANE1_DP_LANE1_MASK                           (0xff << 8)
753 #define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL0                      (0 << 8)
754 #define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL0                      (0 << 8)
755 #define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL0                      (0 << 8)
756 #define NV_SOR_PR_LANE1_DP_LANE1_D3_LEVEL0                      (0 << 8)
757 #define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL1                      (4 << 8)
758 #define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL1                      (6 << 8)
759 #define NV_SOR_PR_LANE1_DP_LANE1_D2_LEVEL1                      (17 << 8)
760 #define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL2                      (8 << 8)
761 #define NV_SOR_PR_LANE1_DP_LANE1_D1_LEVEL2                      (13 << 8)
762 #define NV_SOR_PR_LANE1_DP_LANE1_D0_LEVEL3                      (17 << 8)
763 #define NV_SOR_PR_LANE0_DP_LANE2_SHIFT                          (0)
764 #define NV_SOR_PR_LANE0_DP_LANE2_MASK                           (0xff)
765 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL0                      (0)
766 #define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL0                      (0)
767 #define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL0                      (0)
768 #define NV_SOR_PR_LANE0_DP_LANE2_D3_LEVEL0                      (0)
769 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL1                      (4)
770 #define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL1                      (6)
771 #define NV_SOR_PR_LANE0_DP_LANE2_D2_LEVEL1                      (17)
772 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL2                      (8)
773 #define NV_SOR_PR_LANE0_DP_LANE2_D1_LEVEL2                      (13)
774 #define NV_SOR_PR_LANE0_DP_LANE2_D0_LEVEL3                      (17)
775 #define NV_SOR_LANE4_PREEMPHASIS(i)                             (0x54 + (i))
776 #define NV_SOR_POSTCURSOR(i)                                    (0x56 + (i))
777 #define NV_SOR_DP_CONFIG(i)                                     (0x58 + (i))
778 #define NV_SOR_DP_CONFIG_RD_RESET_VAL_SHIFT                     (31)
779 #define NV_SOR_DP_CONFIG_RD_RESET_VAL_POSITIVE                  (0 << 31)
780 #define NV_SOR_DP_CONFIG_RD_RESET_VAL_NEGATIVE                  (1 << 31)
781 #define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_SHIFT               (28)
782 #define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_DISABLE             (0 << 28)
783 #define NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE              (1 << 28)
784 #define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_SHIFT                   (26)
785 #define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_DISABLE                 (0 << 26)
786 #define NV_SOR_DP_CONFIG_ACTIVESYM_CNTL_ENABLE                  (1 << 26)
787 #define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_SHIFT               (24)
788 #define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE            (0 << 24)
789 #define NV_SOR_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE            (1 << 24)
790 #define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_SHIFT                   (16)
791 #define NV_SOR_DP_CONFIG_ACTIVESYM_FRAC_MASK                    (0xf << 16)
792 #define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_SHIFT                  (8)
793 #define NV_SOR_DP_CONFIG_ACTIVESYM_COUNT_MASK                   (0x7f << 8)
794 #define NV_SOR_DP_CONFIG_WATERMARK_SHIFT                        (0)
795 #define NV_SOR_DP_CONFIG_WATERMARK_MASK                         (0x3f)
796 #define NV_SOR_DP_MN(i)                                         (0x5a + i)
797 #define NV_SOR_DP_MN_M_MOD_SHIFT                                (30)
798 #define NV_SOR_DP_MN_M_MOD_DEFAULT_MASK                         (0x3 << 30)
799 #define NV_SOR_DP_MN_M_MOD_NONE                                 (0 << 30)
800 #define NV_SOR_DP_MN_M_MOD_INC                                  (1 << 30)
801 #define NV_SOR_DP_MN_M_MOD_DEC                                  (2 << 30)
802 #define NV_SOR_DP_MN_M_DELTA_SHIFT                              (24)
803 #define NV_SOR_DP_MN_M_DELTA_DEFAULT_MASK                       (0xf << 24)
804 #define NV_SOR_DP_MN_N_VAL_SHIFT                                (0)
805 #define NV_SOR_DP_MN_N_VAL_DEFAULT_MASK                         (0xffffff)
806
807 #if defined(CONFIG_TEGRA_NVDISPLAY)
808 #define NV_SOR_DP_PADCTL(i)                                     (0x168 + (i))
809 #else
810 #define NV_SOR_DP_PADCTL(i)                                     (0x5c + (i))
811 #endif
812
813 #define NV_SOR_DP_PADCTL_SPARE_SHIFT                            (25)
814 #define NV_SOR_DP_PADCTL_SPARE_DEFAULT_MASK                     (0x7f << 25)
815 #define NV_SOR_DP_PADCTL_VCO_2X_SHIFT                           (24)
816 #define NV_SOR_DP_PADCTL_VCO_2X_DISABLE                         (0 << 24)
817 #define NV_SOR_DP_PADCTL_VCO_2X_ENABLE                          (1 << 24)
818 #define NV_SOR_DP_PADCTL_PAD_CAL_PD_SHIFT                       (23)
819 #define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERUP                     (0 << 23)
820 #define NV_SOR_DP_PADCTL_PAD_CAL_PD_POWERDOWN                   (1 << 23)
821 #define NV_SOR_DP_PADCTL_TX_PU_SHIFT                            (22)
822 #define NV_SOR_DP_PADCTL_TX_PU_DISABLE                          (0 << 22)
823 #define NV_SOR_DP_PADCTL_TX_PU_ENABLE                           (1 << 22)
824 #define NV_SOR_DP_PADCTL_REG_CTRL_SHIFT                         (20)
825 #define NV_SOR_DP_PADCTL_REG_CTRL_DEFAULT_MASK                  (0x3 << 20)
826 #define NV_SOR_DP_PADCTL_VCMMODE_SHIFT                          (16)
827 #define NV_SOR_DP_PADCTL_VCMMODE_DEFAULT_MASK                   (0xf << 16)
828 #define NV_SOR_DP_PADCTL_VCMMODE_TRISTATE                       (0 << 16)
829 #define NV_SOR_DP_PADCTL_VCMMODE_TEST_MUX                       (1 << 16)
830 #define NV_SOR_DP_PADCTL_VCMMODE_WEAK_PULLDOWN                  (2 << 16)
831 #define NV_SOR_DP_PADCTL_VCMMODE_STRONG_PULLDOWN                (4 << 16)
832 #define NV_SOR_DP_PADCTL_TX_PU_VALUE_SHIFT                      (8)
833 #define NV_SOR_DP_PADCTL_TX_PU_VALUE_RBR_HBR                    (0x10 << 8)
834 #define NV_SOR_DP_PADCTL_TX_PU_VALUE_HBR2                       (0x20 << 8)
835 #define NV_SOR_DP_PADCTL_TX_PU_VALUE_DEFAULT_MASK               (0xff << 8)
836 #define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_SHIFT            (7)
837 #define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_DISABLE          (0 << 7)
838 #define NV_SOR_DP_PADCTL_COMODE_TXD_3_DP_TXD_3_ENABLE           (1 << 7)
839 #define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_SHIFT            (6)
840 #define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_DISABLE          (0 << 6)
841 #define NV_SOR_DP_PADCTL_COMODE_TXD_2_DP_TXD_0_ENABLE           (1 << 6)
842 #define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_SHIFT            (5)
843 #define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_DISABLE          (0 << 5)
844 #define NV_SOR_DP_PADCTL_COMODE_TXD_1_DP_TXD_1_ENABLE           (1 << 5)
845 #define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_SHIFT            (4)
846 #define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_DISABLE          (0 << 4)
847 #define NV_SOR_DP_PADCTL_COMODE_TXD_0_DP_TXD_2_ENABLE           (1 << 4)
848 #define NV_SOR_DP_PADCTL_PD_TXD_3_SHIFT                         (3)
849 #define NV_SOR_DP_PADCTL_PD_TXD_3_YES                           (0 << 3)
850 #define NV_SOR_DP_PADCTL_PD_TXD_3_NO                            (1 << 3)
851 #define NV_SOR_DP_PADCTL_PD_TXD_0_SHIFT                         (2)
852 #define NV_SOR_DP_PADCTL_PD_TXD_0_YES                           (0 << 2)
853 #define NV_SOR_DP_PADCTL_PD_TXD_0_NO                            (1 << 2)
854 #define NV_SOR_DP_PADCTL_PD_TXD_1_SHIFT                         (1)
855 #define NV_SOR_DP_PADCTL_PD_TXD_1_YES                           (0 << 1)
856 #define NV_SOR_DP_PADCTL_PD_TXD_1_NO                            (1 << 1)
857 #define NV_SOR_DP_PADCTL_PD_TXD_2_SHIFT                         (0)
858 #define NV_SOR_DP_PADCTL_PD_TXD_2_YES                           (0)
859 #define NV_SOR_DP_PADCTL_PD_TXD_2_NO                            (1)
860 #define NV_SOR_DP_PADCTL_PD_TXD_MASK                            (0xf)
861 #define NV_SOR_DP_DEBUG(i)                                      (0x5e + i)
862 #define NV_SOR_DP_SPARE(i)                                      (0x60 + (i))
863 #define NV_SOR_DP_SPARE_REG_SHIFT                               (3)
864 #define NV_SOR_DP_SPARE_REG_DEFAULT_MASK                        (0x1fffffff << 3)
865 #define NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_ENABLE               (1 << 3)
866 #define NV_SOR_DP_SPARE_VIDEO_PREANBLE_CYA_DISABLE              (0 << 3)
867 #define NV_SOR_DP_SPARE_SOR_CLK_SEL_SHIFT                       (2)
868 #define NV_SOR_DP_SPARE_SOR_CLK_SEL_DEFAULT_MASK                (0x1 << 2)
869 #define NV_SOR_DP_SPARE_SOR_CLK_SEL_SAFE_SORCLK                 (0 << 2)
870 #define NV_SOR_DP_SPARE_SOR_CLK_SEL_MACRO_SORCLK                (1 << 2)
871 #define NV_SOR_DP_SPARE_PANEL_SHIFT                             (1)
872 #define NV_SOR_DP_SPARE_PANEL_EXTERNAL                          (0 << 1)
873 #define NV_SOR_DP_SPARE_PANEL_INTERNAL                          (1 << 1)
874 #define NV_SOR_DP_SPARE_SEQ_ENABLE_SHIFT                        (0)
875 #define NV_SOR_DP_SPARE_SEQ_ENABLE_NO                           (0)
876 #define NV_SOR_DP_SPARE_SEQ_ENABLE_YES                          (1)
877 #define NV_SOR_DP_AUDIO_CTRL                                    (0x62)
878 #define NV_SOR_DP_AUDIO_CTRL_ENABLE                             (1)
879 #define NV_SOR_DP_AUDIO_CTRL_NEW_SETTINGS_TRIGGER               (1 << 31)
880 #define NV_SOR_DP_AUDIO_CTRL_CA_SELECT_HW                       (1 << 20)
881 #define NV_SOR_DP_AUDIO_CTRL_SS_SELECT_HW                       (1 << 19)
882 #define NV_SOR_DP_AUDIO_CTRL_SF_SELECT_HW                       (1 << 18)
883 #define NV_SOR_DP_AUDIO_CTRL_CC_SELECT_HW                       (1 << 17)
884 #define NV_SOR_DP_AUDIO_CTRL_CT_SELECT_HW                       (1 << 16)
885 #define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS                          (0x63)
886 #define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK                     (0x1ffff)
887 #define NV_SOR_DP_AUDIO_HBLANK_SYMBOLS_VALUE_SHIFT              (0)
888 #define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS                          (0x64)
889 #define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK                     (0x1ffff)
890 #define NV_SOR_DP_AUDIO_VBLANK_SYMBOLS_SHIFT                    (0)
891 #define NV_SOR_DP_GENERIC_INFOFRAME_HEADER                      (0x65)
892 #define NV_SOR_DP_GENERIC_INFOFRAME_SUBPACK(i)                  (0x66 + (i))
893 #define NV_SOR_DP_TPG                                           (0x6d)
894 #define NV_SOR_DP_TPG_LANE3_CHANNELCODING_SHIFT                 (30)
895 #define NV_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE               (0 << 30)
896 #define NV_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE                (1 << 30)
897 #define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_SHIFT                   (28)
898 #define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_GALIOS           (1 << 28)
899 #define NV_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE_FIBONACCI        (2 << 28)
900 #define NV_SOR_DP_TPG_LANE3_PATTERN_SHIFT                       (24)
901 #define NV_SOR_DP_TPG_LANE3_PATTERN_DEFAULT_MASK                (0xf << 24)
902 #define NV_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN                   (0 << 24)
903 #define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING1                   (1 << 24)
904 #define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING2                   (2 << 24)
905 #define NV_SOR_DP_TPG_LANE3_PATTERN_TRAINING3                   (3 << 24)
906 #define NV_SOR_DP_TPG_LANE3_PATTERN_D102                        (4 << 24)
907 #define NV_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE                  (5 << 24)
908 #define NV_SOR_DP_TPG_LANE3_PATTERN_PRBS7                       (6 << 24)
909 #define NV_SOR_DP_TPG_LANE3_PATTERN_CSTM                        (7 << 24)
910 #define NV_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE             (8 << 24)
911 #define NV_SOR_DP_TPG_LANE2_CHANNELCODING_SHIFT                 (22)
912 #define NV_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE               (0 << 22)
913 #define NV_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE                (1 << 22)
914 #define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_SHIFT                   (20)
915 #define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DEFAULT_MASK            (0x3 << 20)
916 #define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE                 (0 << 20)
917 #define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_GALIOS           (1 << 20)
918 #define NV_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE_FIBONACCI        (2 << 20)
919 #define NV_SOR_DP_TPG_LANE2_PATTERN_SHIFT                       (16)
920 #define NV_SOR_DP_TPG_LANE2_PATTERN_DEFAULT_MASK                (0xf << 16)
921 #define NV_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN                   (0 << 16)
922 #define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING1                   (1 << 16)
923 #define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING2                   (2 << 16)
924 #define NV_SOR_DP_TPG_LANE2_PATTERN_TRAINING3                   (3 << 16)
925 #define NV_SOR_DP_TPG_LANE2_PATTERN_D102                        (4 << 16)
926 #define NV_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE                  (5 << 16)
927 #define NV_SOR_DP_TPG_LANE2_PATTERN_PRBS7                       (6 << 16)
928 #define NV_SOR_DP_TPG_LANE2_PATTERN_CSTM                        (7 << 16)
929 #define NV_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE             (8 << 16)
930 #define NV_SOR_DP_TPG_LANE1_CHANNELCODING_SHIFT                 (14)
931 #define NV_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE               (0 << 14)
932 #define NV_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE                (1 << 14)
933 #define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_SHIFT                   (12)
934 #define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DEFAULT_MASK            (0x3 << 12)
935 #define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE                 (0 << 12)
936 #define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_GALIOS           (1 << 12)
937 #define NV_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE_FIBONACCI        (2 << 12)
938 #define NV_SOR_DP_TPG_LANE1_PATTERN_SHIFT                       (8)
939 #define NV_SOR_DP_TPG_LANE1_PATTERN_DEFAULT_MASK                (0xf << 8)
940 #define NV_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN                   (0 << 8)
941 #define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING1                   (1 << 8)
942 #define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING2                   (2 << 8)
943 #define NV_SOR_DP_TPG_LANE1_PATTERN_TRAINING3                   (3 << 8)
944 #define NV_SOR_DP_TPG_LANE1_PATTERN_D102                        (4 << 8)
945 #define NV_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE                  (5 << 8)
946 #define NV_SOR_DP_TPG_LANE1_PATTERN_PRBS7                       (6 << 8)
947 #define NV_SOR_DP_TPG_LANE1_PATTERN_CSTM                        (7 << 8)
948 #define NV_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE             (8 << 8)
949 #define NV_SOR_DP_TPG_LANE0_CHANNELCODING_SHIFT                 (6)
950 #define NV_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE               (0 << 6)
951 #define NV_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE                (1 << 6)
952 #define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_SHIFT                   (4)
953 #define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DEFAULT_MASK            (0x3 << 4)
954 #define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE                 (0 << 4)
955 #define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_GALIOS           (1 << 4)
956 #define NV_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE_FIBONACCI        (2 << 4)
957 #define NV_SOR_DP_TPG_LANE0_PATTERN_SHIFT                       (0)
958 #define NV_SOR_DP_TPG_LANE0_PATTERN_DEFAULT_MASK                (0xf)
959 #define NV_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN                   (0)
960 #define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING1                   (1)
961 #define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING2                   (2)
962 #define NV_SOR_DP_TPG_LANE0_PATTERN_TRAINING3                   (3)
963 #define NV_SOR_DP_TPG_LANE0_PATTERN_D102                        (4)
964 #define NV_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE                  (5)
965 #define NV_SOR_DP_TPG_LANE0_PATTERN_PRBS7                       (6)
966 #define NV_SOR_DP_TPG_LANE0_PATTERN_CSTM                        (7)
967 #define NV_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE             (8)
968 #define NV_SOR_DP_TPG_CONFIG                                    (0x6e)
969 #define NV_SOR_DP_LQ_CSTM_0                                     (0x6f)
970 #define NV_SOR_DP_LQ_CSTM_1                                     (0x70)
971 #define NV_SOR_DP_LQ_CSTM_2                                     (0x71)
972
973 #define NV_SOR_DP_INT_ENABLE                    0x171
974
975 #if defined(CONFIG_TEGRA_NVDISPLAY)
976 #define NV_SOR_FPGA_HDMI_HEAD_SEL                               (0x173)
977 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_MODE_FIELD         (1 << 0)
978 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_MODE_HDMI          (0 << 0)
979 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_OUT_EN_FIELD       (1 << 1)
980 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD0_OUT_EN_ENABLE      (1 << 1)
981 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_MODE_FIELD         (1 << 2)
982 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_MODE_HDMI          (0 << 2)
983 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_FIELD       (1 << 3)
984 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD1_OUT_EN_ENABLE      (1 << 3)
985 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_MODE_FIELD         (1 << 4)
986 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_MODE_HDMI          (0 << 4)
987 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_OUT_EN_FIELD       (1 << 5)
988 #define NV_SOR_FPGA_HDMI_HEAD_SEL_FPGA_HEAD2_OUT_EN_ENABLE      (1 << 5)
989
990 #define NV_SOR_FPGA_DISPCLK_HEAD_SEL                            (0x174)
991 #endif
992
993 #define NV_SOR_HDMI_ACR_CTRL                    0xb1
994 #define NV_SOR_HDMI_ACR_0320_SUBPACK_LOW        0xb2
995 #define NV_SOR_HDMI_ACR_0320_SUBPACK_HIGH       0xb3
996 #define NV_SOR_HDMI_ACR_0441_SUBPACK_LOW        0xb4
997 #define NV_SOR_HDMI_ACR_0441_SUBPACK_HIGH       0xb5
998 #define NV_SOR_HDMI_ACR_SB3(x)                  (((x) & 0xff) << 8)
999 #define NV_SOR_HDMI_ACR_SB2(x)                  (((x) & 0xff) << 16)
1000 #define NV_SOR_HDMI_ACR_SB1(x)                  (((x) & 0xff) << 24)
1001 #define NV_SOR_HDMI_ACR_SB6(x)                  (((x) & 0xff) << 0)
1002 #define NV_SOR_HDMI_ACR_SB5(x)                  (((x) & 0xff) << 8)
1003 #define NV_SOR_HDMI_ACR_SB4(x)                  (((x) & 0xff) << 16)
1004 #define NV_SOR_HDMI_ACR_SUBPACK_ENABLE          (1 << 31)
1005 #define NV_SOR_HDMI_ACR_SUBPACK_USE_HW_CTS      NV_SOR_HDMI_ACR_SB1(0)
1006 #define NV_SOR_HDMI_SPARE                       0xcb
1007 #define NV_SOR_HDMI_SPARE_HW_CTS_ENABLE         (1 << 0)
1008 #define NV_SOR_HDMI_SPARE_HW_CTS_DISABLE        (0 << 0)
1009 #define NV_SOR_HDMI_SPARE_FORCE_SW_CTS          (1 << 1)
1010 #define NV_SOR_HDMI_SPARE_SUPRESS_SP_B          (1 << 2)
1011 #define NV_SOR_HDMI_SPARE_CTS_RESET_VAL(x)      (((x) & 0x7) << 16)
1012 #define NV_SOR_HDMI_SPARE_ACR_PRIORITY_HIGH     (0 << 31)
1013 #define NV_SOR_HDMI_SPARE_ACR_PRIORITY_LOW      (1 << 31)
1014 #define NV_SOR_HDMI_GCP_CTRL                    (0xc3)
1015 #define NV_SOR_HDMI_GCP_CTRL_ENABLE             (1)
1016 #define NV_SOR_HDMI_GCP_CTRL_DISABLE            (0)
1017 #define NV_SOR_HDMI_GCP_CTRL_OTHER_DIS          (0 << 4)
1018 #define NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS         (0 << 8)
1019 #define NV_SOR_HDMI_GCP_STATUS                  (0xc4)
1020 #define NV_SOR_HDMI_GCP_STATUS_ACTIVE_END_PP_SHIFT      (8)
1021 #define NV_SOR_HDMI_GCP_STATUS_ACTIVE_END_PP_MASK       (0x7)
1022 #define NV_SOR_HDMI_GCP_SUBPACK(i)                      (0xc5 + i)
1023 #define NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT               (8)
1024 #define NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT               (16)
1025 #define NV_SOR_INPUT_CONTROL                            0xe8
1026 #define NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL       (0 << 1)
1027 #define NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED    (1 << 1)
1028 #define NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAY    (0 << 0)
1029 #define NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB   (1 << 0)
1030
1031 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL                        0x9a
1032 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_CHECKSUM_ENABLE        (1 << 9)
1033 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_CHECKSUM_DISABLE       (0 << 9)
1034 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE_ENABLE          (1 << 8)
1035 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_SINGLE_DISABLE         (0 << 8)
1036 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_OTHER_ENABLE           (1 << 4)
1037 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_OTHER_DISABLE          (0 << 4)
1038 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE_YES             (1)
1039 #define NV_SOR_HDMI_AUDIO_INFOFRAME_CTRL_ENABLE_NO              (0)
1040 #define NV_SOR_HDMI_AUDIO_INFOFRAME_HEADER                      0x9c
1041 #define NV_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW                0x9d
1042 #define NV_SOR_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH               0x9e
1043 #define NV_SOR_HDMI_AVI_INFOFRAME_HEADER                        0xa1
1044 #define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW                  0xa2
1045 #define NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH                 0xa3
1046 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL                          0x9f
1047 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE          (1 << 9)
1048 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_DISABLE         (0 << 9)
1049 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_ENABLE            (1 << 8)
1050 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE           (0 << 8)
1051 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_ENABLE             (1 << 4)
1052 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE            (0 << 4)
1053 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES               (1)
1054 #define NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO                (0)
1055
1056 #define NV_SOR_REFCLK                           0xe6
1057 #define NV_SOR_REFCLK_DIV_INT(x)                (((x) & 0xff) << 8)
1058 #define NV_SOR_REFCLK_DIV_FRAC(x)               (((x) & 0x3) << 6)
1059 #define NV_SOR_AUDIO_CTRL                       0xfc
1060
1061 #define NV_SOR_HDMI_GENERIC_CTRL                        0xa6
1062 #define NV_SOR_HDMI_GENERIC_CTRL_AUDIO_ENABLE                   (1 << 16)
1063 #define NV_SOR_HDMI_GENERIC_CTRL_AUDIO_DISABLE                  (0 << 16)
1064 #define NV_SOR_HDMI_GENERIC_CTRL_HBLANK_ENABLE                  (1 << 12)
1065 #define NV_SOR_HDMI_GENERIC_CTRL_HBLANK_DISABLE                 (0 << 12)
1066 #define NV_SOR_HDMI_GENERIC_CTRL_SINGLE_ENABLE                  (1 << 8)
1067 #define NV_SOR_HDMI_GENERIC_CTRL_SINGLE_DISABLE                 (0 << 8)
1068 #define NV_SOR_HDMI_GENERIC_CTRL_OTHER_ENABLE                   (1 << 4)
1069 #define NV_SOR_HDMI_GENERIC_CTRL_OTHER_DISABLE                  (0 << 4)
1070 #define NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES                             (1 << 0)
1071 #define NV_SOR_HDMI_GENERIC_CTRL_ENABLE_NO                              (0 << 0)
1072 #define NV_SOR_HDMI_GENERIC_HEADER              0xa8
1073 #define NV_SOR_HDMI_GENERIC_SUBPACK0_LOW                0xa9
1074 #define NV_SOR_HDMI_GENERIC_SUBPACK0_HIGH               0xaa
1075 #define NV_SOR_HDMI_GENERIC_SUBPACK1_LOW                0xab
1076 #define NV_SOR_HDMI_GENERIC_SUBPACK1_HIGH               0xac
1077 #define NV_SOR_HDMI_GENERIC_SUBPACK2_LOW                0xad
1078 #define NV_SOR_HDMI_GENERIC_SUBPACK2_HIGH               0xae
1079 #define NV_SOR_HDMI_GENERIC_SUBPACK3_LOW                0xaf
1080 #define NV_SOR_HDMI_GENERIC_SUBPACK3_HIGH               0xb0
1081 #define NV_SOR_AUDIO_CTRL_AFIFO_FLUSH           (1 << 12)
1082 #define NV_SOR_AUDIO_CTRL_SRC_HDA               (0x2 << 20)
1083 #define NV_SOR_AUDIO_CTRL_NULL_SAMPLE_EN        (1 << 29)
1084 #define NV_SOR_AUDIO_CTRL_NULL_SAMPLE_DIS       (0 << 29)
1085 #define NV_SOR_AUDIO_DEBUG                      0xfd
1086 #define NV_SOR_AUDIO_NVAL_0320                  0xff
1087 #define NV_SOR_AUDIO_NVAL_0441                  0x100
1088 #define NV_SOR_AUDIO_NVAL_0882                  0x101
1089 #define NV_SOR_AUDIO_NVAL_1764                  0x102
1090 #define NV_SOR_AUDIO_NVAL_0480                  0x103
1091 #define NV_SOR_AUDIO_NVAL_0960                  0x104
1092 #define NV_SOR_AUDIO_NVAL_1920                  0x105
1093 #define NV_SOR_SEQ_INST0                        0x22
1094 #define NV_SOR_SEQ_INST8                        0x2a
1095 #define NV_SOR_HDMI_CTRL                        0xc0
1096 #define NV_SOR_HDMI_CTRL_REKEY(x)               (((x) & 0x7f) << 0)
1097 #define NV_SOR_HDMI_CTRL_AUDIO_LAYOUT           (1 << 8)
1098 #define NV_SOR_HDMI_CTRL_SAMPLE_FLAT            (1 << 12)
1099 #define NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT    (1 << 10)
1100 #define NV_SOR_HDMI_CTRL_MAX_AC_PACKET(x)       (((x) & 0x1f) << 16)
1101 #define NV_SOR_HDMI_CTRL_ENABLE                 (1 << 30)
1102 #define NV_SOR_AUDIO_HDA_ELD_BUFWR              (0x10c)
1103 #define NV_SOR_AUDIO_HDA_ELD_BUFWR_INDEX(x)     (((x) & 0xff) << 8)
1104 #define NV_SOR_AUDIO_HDA_ELD_BUFWR_DATA(x)      (((x) & 0xff) << 0)
1105 #define NV_SOR_AUDIO_HDA_PRESENCE               (0x10d)
1106 #define NV_SOR_AUDIO_HDA_PRESENCE_ELDV(x)       ((x) << 1)
1107 #define NV_SOR_AUDIO_HDA_PRESENCE_PD(x)         (x)
1108 #define NV_SOR_AUDIO_AVAL_0320                  0x10f
1109 #define NV_SOR_AUDIO_AVAL_0441                  0x110
1110 #define NV_SOR_AUDIO_AVAL_0882                  0x111
1111 #define NV_SOR_AUDIO_AVAL_1764                  0x112
1112 #define NV_SOR_AUDIO_AVAL_0480                  0x113
1113 #define NV_SOR_AUDIO_AVAL_0960                  0x114
1114 #define NV_SOR_AUDIO_AVAL_1920                  0x115
1115 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL          0x123
1116 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE          (1 << 9)
1117 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_DISABLE         (0 << 9)
1118 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_ENABLE            (1 << 8)
1119 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE           (0 << 8)
1120 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_ENABLE             (1 << 4)
1121 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE            (0 << 4)
1122 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES               (1)
1123 #define NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_NO                (0)
1124 #define NV_SOR_HDMI_VSI_INFOFRAME_HEADER                        0x125
1125 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_LOW                  0x126
1126 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK0_HIGH                 0x127
1127 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_LOW                  0x128
1128 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK1_HIGH                 0x129
1129 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_LOW                  0x12a
1130 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK2_HIGH                 0x12b
1131 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_LOW                  0x12c
1132 #define NV_SOR_HDMI_VSI_INFOFRAME_SUBPACK3_HIGH                 0x12d
1133 #define NV_SOR_HDMI_AUDIO_N                     0x13c
1134 #define NV_SOR_HDMI_AUDIO_N_VALUE(x)            (((x) & 0xfffff) << 0)
1135 #define NV_SOR_HDMI_AUDIO_N_RESET_ASSERT        (1 << 20)
1136 #define NV_SOR_HDMI_AUDIO_N_RESET_DEASSERT      (0 << 20)
1137 #define NV_SOR_HDMI_AUDIO_N_GENERATE_NORMAL     (0 << 24)
1138 #define NV_SOR_HDMI_AUDIO_N_GENERATE_ALTERNALTE (1 << 24)
1139 #define NV_SOR_HDMI_AUDIO_N_LOOKUP_ENABLE       (1 << 28)
1140
1141 #define NV_SOR_DP_AUDIO_CRC                             0x12e
1142 #define NV_SOR_DP_AUDIO_TIMESTAMP_0320                  0x133
1143 #define NV_SOR_DP_AUDIO_TIMESTAMP_0441                  0x134
1144 #define NV_SOR_DP_AUDIO_TIMESTAMP_0882                  0x135
1145 #define NV_SOR_DP_AUDIO_TIMESTAMP_1764                  0x136
1146 #define NV_SOR_DP_AUDIO_TIMESTAMP_0480                  0x137
1147 #define NV_SOR_DP_AUDIO_TIMESTAMP_0960                  0x138
1148 #define NV_SOR_DP_AUDIO_TIMESTAMP_1920                  0x139
1149 #define NV_SOR_DP_OUTPUT_CHANNEL_STATUS1                0x13a
1150 #define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2                0x13b
1151 #define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2_OVERRIDE_EN            (1 << 31)
1152 #define NV_SOR_DP_OUTPUT_CHANNEL_STATUS2_OVERRIDE_DIS           (0 << 31)
1153
1154 #define NV_SOR_HDMI2_CTRL       0x13e
1155 #define NV_SOR_HDMI2_CTRL_SSCP_START            (0x200 << 16)
1156 #define NV_SOR_HDMI2_CTRL_SSCP_LEN              (0x8 << 4)
1157 #define NV_SOR_HDMI2_CTRL_CLK_MODE_NORMAL       (0 << 1)
1158 #define NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4     (1 << 1)
1159 #define NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE       (1)
1160 #define NV_SOR_HDMI2_CTRL_SCRAMBLE_DISABLE      (0)
1161
1162 #define NV_SOR_DP_HDCP_AN_MSB                           (0x75)
1163 #define NV_SOR_DP_HDCP_AN_LSB                           (0x76)
1164 #define NV_SOR_DP_HDCP_AKSV_MSB                         (0x77)
1165 #define NV_SOR_DP_HDCP_AKSV_LSB                         (0x78)
1166 #define NV_SOR_DP_HDCP_BKSV_MSB                         (0x79)
1167 #define NV_SOR_DP_HDCP_BKSV_LSB                         (0x7a)
1168 #define NV_SOR_DP_HDCP_CTRL                             (0x7b)
1169 #define NV_SOR_DP_HDCP_RI                               (0x7c)
1170 #define NV_SOR_DP_HDCP_CYA                              (0x7f)
1171
1172 #define NV_SOR_TMDS_HDCP_AN_MSB                         (0x80)
1173 #define NV_SOR_TMDS_HDCP_AN_LSB                         (0x81)
1174 #define NV_SOR_TMDS_HDCP_CN_MSB                         (0x82)
1175 #define NV_SOR_TMDS_HDCP_CN_LSB                         (0x83)
1176 #define NV_SOR_TMDS_HDCP_AKSV_MSB                       (0x84)
1177 #define NV_SOR_TMDS_HDCP_AKSV_LSB                       (0x85)
1178 #define NV_SOR_TMDS_HDCP_BKSV_MSB                       (0x86)
1179 #define REPEATER                                        (1 << 31)
1180 #define NV_SOR_TMDS_HDCP_BKSV_LSB                       (0x87)
1181 #define NV_SOR_TMDS_HDCP_CKSV_MSB                       (0x88)
1182 #define NV_SOR_TMDS_HDCP_CKSV_LSB                       (0x89)
1183 #define NV_SOR_TMDS_HDCP_DKSV_MSB                       (0x8a)
1184 #define NV_SOR_TMDS_HDCP_DKSV_LSB                       (0x8b)
1185 #define NV_SOR_TMDS_HDCP_CTRL                           (0x8c)
1186 #define HDCP_RUN_YES                                    (1 << 0)
1187 #define CRYPT_ENABLED                                   (1 << 1)
1188 #define ONEONE_ENABLED                                  (1 << 3)
1189 #define AN_VALID                                        (1 << 8)
1190 #define R0_VALID                                        (1 << 9)
1191 #define SPRIME_VALID                                    (1 << 10)
1192 #define MPRIME_VALID                                    (1 << 11)
1193 #define SROM_ERR                                        (1 << 13)
1194 #define NV_SOR_TMDS_HDCP_CMODE                          (0x8d)
1195 #define TMDS0_LINK0                                     (1 << 4)
1196 #define READ_S                                          (1 << 0)
1197 #define READ_M                                          (2 << 0)
1198 #define NV_SOR_TMDS_HDCP_MPRIME_MSB                     (0x8e)
1199 #define NV_SOR_TMDS_HDCP_MPRIME_LSB                     (0x8f)
1200 #define NV_SOR_TMDS_HDCP_SPRIME_MSB                     (0x90)
1201 #define STATUS_CS                                       (1 << 6)
1202 #define NV_SOR_TMDS_HDCP_SPRIME_LSB2                    (0x91)
1203 #define NV_SOR_TMDS_HDCP_SPRIME_LSB1                    (0x92)
1204 #define NV_SOR_TMDS_HDCP_RI                             (0x93)
1205 #define NV_SOR_TMDS_HDCP_CS_MSB                         (0x94)
1206 #define NV_SOR_TMDS_HDCP_CS_LSB                         (0x95)
1207
1208 #define NV_SOR_KEY_CTRL                                 (0xea)
1209 #define LOCAL_KEYS                                      (1 << 0)
1210 #define AUTOINC                                         (1 << 1)
1211 #define WRITE16                                         (1 << 4)
1212 #define PKEY_RELOAD_TRIGGER                             (1 << 5)
1213 #define PKEY_LOADED                                     (1 << 6)
1214
1215 #define NV_SOR_KEY_DEBUG0                               0xeb
1216 #define NV_SOR_KEY_DEBUG1                               0xec
1217 #define NV_SOR_KEY_DEBUG2                               0xed
1218 #define NV_SOR_KEY_HDCP_KEY_0                           0xee
1219 #define NV_SOR_KEY_HDCP_KEY_1                           0xef
1220 #define NV_SOR_KEY_HDCP_KEY_2                           0xf0
1221 #define NV_SOR_KEY_HDCP_KEY_3                           0xf1
1222 #define NV_SOR_KEY_HDCP_KEY_TRIG                        0xf2
1223 #define LOAD_HDCP_KEY                                   (1 << 8)
1224 #define NV_SOR_KEY_SKEY_INDEX                           0xf3
1225 #define NV_PDISP_SOR_AUDIO_SPARE0_0                     0xfe
1226 #define HDMI_AUDIO_HBR_ENABLE_SHIFT                     27
1227
1228 #define NV_SOR_HDMI_CTRL_REKEY_DEFAULT  58
1229
1230 #endif