ef6f0cd0a11bc05aeb55203ba8de024636cd1b72
[linux-3.10.git] / drivers / video / tegra / dc / hdmi2.0.c
1 /*
2  * drivers/video/tegra/dc/hdmi2.0.c
3  *
4  * Copyright (c) 2014-2015, NVIDIA CORPORATION, All rights reserved.
5  * Author: Animesh Kishore <ankishore@nvidia.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mutex.h>
23 #include <linux/device.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/nvhost.h>
26 #include <linux/gpio.h>
27 #include <linux/interrupt.h>
28 #include <linux/debugfs.h>
29 #include <linux/unistd.h>
30 #ifdef CONFIG_SWITCH
31 #include <linux/switch.h>
32 #endif
33 #include <linux/of_address.h>
34 #include <linux/tegra_pm_domains.h>
35
36 #include <mach/dc.h>
37 #include <mach/fb.h>
38 #include <mach/powergate.h>
39
40 #include "dc_reg.h"
41 #include "dc_priv.h"
42 #include "sor.h"
43 #include "sor_regs.h"
44 #include "edid.h"
45 #include "hdmi2.0.h"
46 #include "hdmihdcp.h"
47 #include "dpaux.h"
48 #ifdef CONFIG_ADF_TEGRA
49 #include "tegra_adf.h"
50 #endif
51 #include "hda_dc.h"
52 #include "hdmivrr.h"
53
54 #include <linux/tegra_prod.h>
55 #include "../../../../arch/arm/mach-tegra/iomap.h"
56
57 #define TMDS_NODE       "/host1x/sor1"
58
59 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
60 static struct of_device_id tegra_sor_pd[] = {
61         { .compatible = "nvidia, tegra210-sor-pd", },
62         { .compatible = "nvidia, tegra132-sor-pd", },
63         { .compatible = "nvidia, tegra124-sor-pd", },
64         {},
65 };
66 #endif
67
68 /* Possibly should be moved to hdmi_common.h */
69 static struct fb_videomode tegra_dc_vga_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
85         struct kobj_attribute *attr, const char *buf, size_t count);
86
87 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
88         struct kobj_attribute *attr, char *buf);
89
90 static struct kobj_attribute hdmi_ddc_power_config =
91         __ATTR(config, 0640, hdmi_ddc_power_show, hdmi_ddc_power_toggle);
92
93 static struct kobject *hdmi_ddc;
94
95 struct tmds_prod_pair {
96         int clk;
97         const char *name;
98 };
99
100 static struct tmds_prod_pair tmds_config_modes[] = {
101         { /* 54 MHz */
102         .clk = 54000000,
103         .name = "prod_c_54M"
104         },
105         { /* 75 MHz */
106         .clk = 75000000,
107         .name = "prod_c_75M"
108         },
109         { /* 150 MHz */
110         .clk = 150000000,
111         .name = "prod_c_150M"
112         },
113         { /* 300 MHz */
114         .clk = 300000000,
115         .name = "prod_c_300M"
116         },
117         { /* HDMI 2.0 */
118         .clk = 600000000,
119         .name = "prod_c_600M"
120         }
121 };
122
123 static struct tegra_hdmi *dc_hdmi;
124
125 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi);
126 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type);
127 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk);
128 static void tegra_hdmi_scdc_worker(struct work_struct *work);
129 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi);
130
131 static inline bool tegra_hdmi_is_connected(struct tegra_hdmi *hdmi)
132 {
133         return (hdmi->mon_spec.misc & FB_MISC_HDMI) ||
134                 (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM);
135 }
136
137 static inline void tegra_hdmi_irq_enable(struct tegra_hdmi *hdmi)
138 {
139         if (tegra_platform_is_fpga())
140                 return;
141
142         enable_irq(hdmi->irq);
143 }
144
145 static inline void tegra_hdmi_irq_disable(struct tegra_hdmi *hdmi)
146 {
147         if (tegra_platform_is_fpga())
148                 return;
149
150         disable_irq(hdmi->irq);
151 }
152
153 static inline bool tegra_hdmi_hpd_asserted(struct tegra_hdmi *hdmi)
154 {
155         return tegra_dc_hpd(hdmi->dc);
156 }
157
158 static inline void tegra_hdmi_reset(struct tegra_hdmi *hdmi)
159 {
160         if (tegra_platform_is_linsim())
161                 return;
162
163         tegra_periph_reset_assert(hdmi->sor->sor_clk);
164         mdelay(20);
165         tegra_periph_reset_deassert(hdmi->sor->sor_clk);
166         mdelay(20);
167 }
168
169 static inline void _tegra_hdmi_ddc_enable(struct tegra_hdmi *hdmi)
170 {
171         mutex_lock(&hdmi->ddc_refcount_lock);
172         if (hdmi->ddc_refcount++)
173                 goto fail;
174         tegra_hdmi_get(hdmi->dc);
175         /*
176          * hdmi uses i2c lane muxed on dpaux1 pad.
177          * Enable dpaux1 pads and configure the mux.
178          */
179         tegra_dpaux_config_pad_mode(hdmi->dc, TEGRA_DPAUX_INSTANCE_1,
180                                         TEGRA_DPAUX_PAD_MODE_I2C);
181
182 fail:
183         mutex_unlock(&hdmi->ddc_refcount_lock);
184 }
185
186 static inline void _tegra_hdmi_ddc_disable(struct tegra_hdmi *hdmi)
187 {
188         mutex_lock(&hdmi->ddc_refcount_lock);
189
190         if (WARN_ONCE(hdmi->ddc_refcount <= 0, "ddc refcount imbalance"))
191                 goto fail;
192         if (--hdmi->ddc_refcount != 0)
193                 goto fail;
194
195         /*
196          * hdmi uses i2c lane muxed on dpaux1 pad.
197          * Disable dpaux1 pads.
198          */
199         tegra_dpaux_pad_power(hdmi->dc, TEGRA_DPAUX_INSTANCE_1, false);
200         tegra_hdmi_put(hdmi->dc);
201
202 fail:
203         mutex_unlock(&hdmi->ddc_refcount_lock);
204 }
205
206 static int tegra_hdmi_ddc_i2c_xfer(struct tegra_dc *dc,
207                                         struct i2c_msg *msgs, int num)
208 {
209         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
210         int ret;
211
212         _tegra_hdmi_ddc_enable(hdmi);
213         ret = i2c_transfer(hdmi->ddc_i2c_client->adapter, msgs, num);
214         _tegra_hdmi_ddc_disable(hdmi);
215         return ret;
216 }
217
218 static int tegra_hdmi_ddc_init(struct tegra_hdmi *hdmi, int edid_src)
219 {
220         struct tegra_dc *dc = hdmi->dc;
221         struct i2c_adapter *i2c_adap;
222         int err = 0;
223         struct i2c_board_info i2c_dev_info = {
224                 .type = "tegra_hdmi2.0",
225                 .addr = 0x50,
226         };
227         if (edid_src == 0)
228                 hdmi->edid = tegra_edid_create(dc, tegra_hdmi_ddc_i2c_xfer);
229         else if (edid_src == 1)
230                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
231         if (IS_ERR_OR_NULL(hdmi->edid)) {
232                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
233                 return PTR_ERR(hdmi->edid);
234         }
235         tegra_dc_set_edid(dc, hdmi->edid);
236
237         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
238         if (!i2c_adap) {
239                 dev_err(&dc->ndev->dev,
240                         "hdmi: can't get adpater for ddc bus %d\n",
241                         dc->out->ddc_bus);
242                 err = -EBUSY;
243                 goto fail_edid_free;
244         }
245         hdmi->ddc_i2c_original_rate = i2c_get_adapter_bus_clk_rate(i2c_adap);
246
247         hdmi->ddc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
248         i2c_put_adapter(i2c_adap);
249         if (!hdmi->ddc_i2c_client) {
250                 dev_err(&dc->ndev->dev, "hdmi: can't create new i2c device\n");
251                 err = -EBUSY;
252                 goto fail_edid_free;
253         }
254
255         return 0;
256 fail_edid_free:
257         tegra_edid_destroy(hdmi->edid);
258         return err;
259 }
260
261 static int tegra_hdmi_scdc_i2c_xfer(struct tegra_dc *dc,
262                                         struct i2c_msg *msgs, int num)
263 {
264         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
265
266         return i2c_transfer(hdmi->scdc_i2c_client->adapter, msgs, num);
267 }
268
269 static int tegra_hdmi_scdc_init(struct tegra_hdmi *hdmi)
270 {
271         struct tegra_dc *dc = hdmi->dc;
272         struct i2c_adapter *i2c_adap;
273         int err = 0;
274         struct i2c_board_info i2c_dev_info = {
275                 .type = "tegra_hdmi_scdc",
276                 .addr = 0x54,
277         };
278
279         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
280         if (!i2c_adap) {
281                 dev_err(&dc->ndev->dev,
282                         "hdmi: can't get adpater for scdc bus %d\n",
283                         dc->out->ddc_bus);
284                 err = -EBUSY;
285                 goto fail;
286         }
287
288         hdmi->scdc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
289         i2c_put_adapter(i2c_adap);
290         if (!hdmi->scdc_i2c_client) {
291                 dev_err(&dc->ndev->dev,
292                         "hdmi: can't create scdc i2c device\n");
293                 err = -EBUSY;
294                 goto fail;
295         }
296
297         INIT_DELAYED_WORK(&hdmi->scdc_work, tegra_hdmi_scdc_worker);
298
299         return 0;
300 fail:
301         return err;
302 }
303
304 static bool tegra_hdmi_check_dc_constraint(const struct fb_videomode *mode)
305 {
306         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
307                 (mode->lower_margin + mode->vsync_len +
308                 mode->upper_margin > 1) &&
309                 (mode->xres >= 16) && (mode->yres >= 16);
310 }
311
312 /*  does not return precise tmds character rate */
313 static u32 tegra_hdmi_mode_min_tmds_rate(const struct fb_videomode *mode)
314 {
315         u32 tmds_csc_8bpc_khz = PICOS2KHZ(mode->pixclock);
316
317         if (mode->vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
318                 tmds_csc_8bpc_khz /= 2;
319
320         return tmds_csc_8bpc_khz;
321 }
322
323 __maybe_unused
324 static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
325                                         struct fb_videomode *mode)
326 {
327         struct tegra_hdmi *hdmi = dc->out_data;
328
329         if (!mode->pixclock)
330                 return false;
331
332         if (mode->xres > 4096)
333                 return false;
334
335         /* some non-compliant edids list 420vdb modes in vdb */
336         if ((mode->vmode & FB_VMODE_Y420) &&
337                 !(tegra_edid_is_hfvsdb_present(hdmi->edid) &&
338                 tegra_edid_is_scdc_present(hdmi->edid)) &&
339                 tegra_edid_is_420db_present(hdmi->edid)) {
340                 mode->vmode &= ~FB_VMODE_Y420;
341                 mode->vmode |= FB_VMODE_Y420_ONLY;
342         }
343
344         if (mode->vmode & FB_VMODE_YUV_MASK &&
345                 tegra_edid_get_quirks(hdmi->edid) & TEGRA_EDID_QUIRK_NO_YUV)
346                 return false;
347
348         /*
349          * There are currently many TVs in the market that actually do NOT support
350          * 4k@60fps 4:4:4 (594 MHz), (especially on the HDCP 2.2 ports), but
351          * advertise it in the DTD block in their EDIDs. The workaround for this port
352          * is to disable the 594 MHz mode if no HF-VSDB is present or if no SCDC
353          * support is indicated
354          */
355         if (tegra_hdmi_mode_min_tmds_rate(mode) / 1000 >= 340 &&
356                 (!tegra_edid_is_hfvsdb_present(hdmi->edid) ||
357                 !tegra_edid_is_scdc_present(hdmi->edid)))
358                 return false;
359
360         /*
361          * Check if mode's pixel clock requirement can be satisfied. Note that
362          * the pixclock value is in pico seconds.
363          */
364         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
365                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
366                 return false;
367
368         /*
369          * Work around for modes that fail the constraint:
370          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
371          */
372         if (mode->lower_margin == 1) {
373                 mode->lower_margin++;
374                 mode->upper_margin--;
375         }
376
377         if (!tegra_hdmi_check_dc_constraint(mode))
378                 return false;
379
380         return true;
381 }
382
383 static void tegra_hdmi_ddc_power_toggle(int value)
384 {
385         int partition_id;
386         if (dc_hdmi == NULL)
387                 return;
388
389 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
390         partition_id = tegra_pd_get_powergate_id(tegra_sor_pd);
391         if (partition_id < 0)
392                 return;
393 #else
394         partition_id = TEGRA_POWERGATE_SOR;
395 #endif
396
397         if (value == 0) {
398                 _tegra_hdmi_ddc_disable(dc_hdmi);
399                 tegra_powergate_partition(partition_id);
400         } else if (value == 1) {
401                 tegra_unpowergate_partition(partition_id);
402                 _tegra_hdmi_ddc_enable(dc_hdmi);
403         }
404
405         return;
406 }
407
408 static int tegra_hdmi_get_mon_spec(struct tegra_hdmi *hdmi)
409 {
410 #define MAX_RETRY 100
411 #define MIN_RETRY_DELAY_US 200
412 #define MAX_RETRY_DELAY_US (MIN_RETRY_DELAY_US + 200)
413
414         size_t attempt_cnt = 0;
415         int err = 0;
416         struct i2c_adapter *i2c_adap = i2c_get_adapter(hdmi->dc->out->ddc_bus);
417
418         if (IS_ERR_OR_NULL(hdmi->edid)) {
419                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid not initialized\n");
420                 return PTR_ERR(hdmi->edid);
421         }
422
423         tegra_edid_i2c_adap_change_rate(i2c_adap, hdmi->ddc_i2c_original_rate);
424
425         hdmi->mon_spec_valid = false;
426         if (hdmi->mon_spec_valid)
427                 fb_destroy_modedb(hdmi->mon_spec.modedb);
428         memset(&hdmi->mon_spec, 0, sizeof(hdmi->mon_spec));
429
430         do {
431                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
432                 if (err < 0)
433                         usleep_range(MIN_RETRY_DELAY_US, MAX_RETRY_DELAY_US);
434                 else
435                         break;
436         } while (++attempt_cnt < MAX_RETRY);
437
438         if (err < 0) {
439                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid read failed\n");
440                 /* Try to load and parse the fallback edid */
441                 hdmi->edid->errors = EDID_ERRORS_READ_FAILED;
442                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
443                 if (err < 0) {
444                         dev_err(&hdmi->dc->ndev->dev,
445                                 "hdmi: parsing fallback edid failed\n");
446                         return err;
447                 } else {
448                         dev_err(&hdmi->dc->ndev->dev,
449                                 "hdmi: using fallback edid\n");
450                 }
451         }
452
453         hdmi->mon_spec_valid = true;
454         return 0;
455
456 #undef MAX_RETRY_DELAY_US
457 #undef MIN_RETRY_DELAY_US
458 #undef MAX_RETRY
459 }
460
461 static inline int tegra_hdmi_edid_read(struct tegra_hdmi *hdmi)
462 {
463         int err;
464
465         err = tegra_hdmi_get_mon_spec(hdmi);
466
467         return err;
468 }
469
470 static int tegra_hdmi_get_eld(struct tegra_hdmi *hdmi)
471 {
472         int err;
473
474         hdmi->eld_valid = false;
475         memset(&hdmi->eld, 0, sizeof(hdmi->eld));
476
477         err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
478         if (err < 0) {
479                 dev_err(&hdmi->dc->ndev->dev, "hdmi: eld not available\n");
480                 return err;
481         }
482
483         hdmi->eld_valid = true;
484         return 0;
485 }
486
487 static inline int tegra_hdmi_eld_read(struct tegra_hdmi *hdmi)
488 {
489         return tegra_hdmi_get_eld(hdmi);
490 }
491
492 static void tegra_hdmi_edid_config(struct tegra_hdmi *hdmi)
493 {
494 #define CM_TO_MM(x) (x * 10)
495
496         struct tegra_dc *dc = hdmi->dc;
497
498         if (!hdmi->mon_spec_valid)
499                 return;
500
501         dc->out->h_size = CM_TO_MM(hdmi->mon_spec.max_x);
502         dc->out->v_size = CM_TO_MM(hdmi->mon_spec.max_y);
503
504         hdmi->dvi = !tegra_hdmi_is_connected(hdmi);
505 #undef CM_TO_MM
506 }
507
508 static void tegra_hdmi_hotplug_notify(struct tegra_hdmi *hdmi,
509                                         bool is_asserted)
510 {
511         struct tegra_dc *dc = hdmi->dc;
512         struct fb_monspecs *mon_spec;
513
514         if (is_asserted)
515                 mon_spec = &hdmi->mon_spec;
516         else
517                 mon_spec = NULL;
518
519 #ifdef CONFIG_ADF_TEGRA
520         if (dc->adf)
521                 tegra_adf_process_hotplug_connected(hdmi->dc->adf, mon_spec);
522 #else
523         if (dc->fb) {
524                 tegra_fb_update_monspecs(hdmi->dc->fb, mon_spec,
525                                         tegra_hdmi_fb_mode_filter,
526                                         tegra_hdmi_update_vrr_mode);
527                 tegra_fb_update_fix(hdmi->dc->fb, mon_spec);
528         }
529 #endif
530
531         dc->connected = is_asserted;
532         tegra_dc_ext_process_hotplug(dc->ndev->id, is_asserted);
533
534 #ifdef CONFIG_SWITCH
535         switch_set_state(&hdmi->hpd_switch, is_asserted ? 1 : 0);
536 #endif
537 }
538
539 static int tegra_hdmi_edid_eld_setup(struct tegra_hdmi *hdmi)
540 {
541         int err;
542
543         tegra_dc_unpowergate_locked(hdmi->dc);
544
545         err = tegra_hdmi_edid_read(hdmi);
546         if (err < 0)
547                 goto fail;
548
549         err = tegra_hdmi_eld_read(hdmi);
550         if (err < 0)
551                 goto fail;
552
553         err = tegra_hdmivrr_setup(hdmi);
554         if (err < 0)
555                 dev_info(&hdmi->dc->ndev->dev, "vrr_setup failed\n");
556
557         tegra_dc_powergate_locked(hdmi->dc);
558
559         tegra_hdmi_edid_config(hdmi);
560
561         /*
562          * eld is configured when audio needs it
563          * via tegra_hdmi_edid_config()
564          */
565
566         tegra_hdmi_hotplug_notify(hdmi, true);
567         return 0;
568 fail:
569         tegra_dc_powergate_locked(hdmi->dc);
570         return err;
571 }
572
573 static int tegra_hdmi_controller_disable(struct tegra_hdmi *hdmi)
574 {
575         struct tegra_dc_sor_data *sor = hdmi->sor;
576         struct tegra_dc *dc = hdmi->dc;
577
578         tegra_dc_get(dc);
579
580         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
581         tegra_dc_sor_detach(sor);
582         tegra_sor_power_lanes(sor, 4, false);
583         tegra_sor_hdmi_pad_power_down(sor);
584         tegra_hdmi_reset(hdmi);
585         tegra_hdmi_put(dc);
586
587         tegra_dc_put(dc);
588
589         return 0;
590 }
591
592 static int tegra_hdmi_disable(struct tegra_hdmi *hdmi)
593 {
594         struct tegra_dc *dc = hdmi->dc;
595
596         if (!hdmi->enabled) {
597                 dc->connected = false;
598                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
599 #ifdef CONFIG_SWITCH
600                 switch_set_state(&hdmi->hpd_switch, 0);
601 #endif
602                 return 0;
603         }
604
605         hdmi->enabled = false;
606         hdmi->eld_valid = false;
607         hdmi->mon_spec_valid = false;
608
609         tegra_dc_disable(hdmi->dc);
610
611         tegra_hdmi_hotplug_notify(hdmi, false);
612
613         return 0;
614 }
615
616 static int (*tegra_hdmi_state_func[])(struct tegra_hdmi *) = {
617         tegra_hdmi_disable,
618         tegra_hdmi_edid_eld_setup,
619 };
620
621 enum tegra_hdmi_plug_states {
622         TEGRA_HDMI_MONITOR_DISABLE,
623         TEGRA_HDMI_MONITOR_ENABLE,
624 };
625
626 static int read_edid_into_buffer(struct tegra_hdmi *hdmi,
627                                  u8 *edid_data, size_t edid_data_len)
628 {
629         int err, i;
630         int extension_blocks;
631         int max_ext_blocks = (edid_data_len / 128) - 1;
632
633         err = tegra_edid_read_block(hdmi->edid, 0, edid_data);
634         if (err) {
635                 dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(0) returned err %d\n",
636                         err);
637                 return err;
638         }
639         extension_blocks = edid_data[0x7e];
640         dev_info(&hdmi->dc->ndev->dev, "%s: extension_blocks = %d, max_ext_blocks = %d\n",
641                 __func__, extension_blocks, max_ext_blocks);
642         if (extension_blocks > max_ext_blocks)
643                 extension_blocks = max_ext_blocks;
644         for (i = 1; i <= extension_blocks; i++) {
645                 err = tegra_edid_read_block(hdmi->edid, i, edid_data + i * 128);
646                 if (err) {
647                         dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(%d) returned err %d\n",
648                                 i, err);
649                         return err;
650                 }
651         }
652         return i * 128;
653 }
654
655 static int hdmi_recheck_edid(struct tegra_hdmi *hdmi, int *match)
656 {
657         int ret;
658         u8 tmp[HDMI_EDID_MAX_LENGTH] = {0};
659         ret = read_edid_into_buffer(hdmi, tmp, sizeof(tmp));
660         dev_info(&hdmi->dc->ndev->dev, "%s: read_edid_into_buffer() returned %d\n",
661                 __func__, ret);
662         if (ret > 0) {
663                 struct tegra_dc_edid *data = tegra_edid_get_data(hdmi->edid);
664                 dev_info(&hdmi->dc->ndev->dev, "old edid len = %ld\n",
665                         (long int)data->len);
666                 *match = ((ret == data->len) &&
667                           !memcmp(tmp, data->buf, data->len));
668                 if (*match == 0) {
669                         print_hex_dump(KERN_INFO, "tmp :", DUMP_PREFIX_ADDRESS,
670                                        16, 4, tmp, ret, true);
671                         print_hex_dump(KERN_INFO, "data:", DUMP_PREFIX_ADDRESS,
672                                        16, 4, data->buf, data->len, true);
673                 }
674                 tegra_edid_put_data(data);
675                 ret = 0;
676         }
677
678         return ret;
679 }
680 static void tegra_hdmi_hpd_worker(struct work_struct *work)
681 {
682         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
683                                 struct tegra_hdmi, hpd_worker);
684         int err;
685         bool connected;
686         enum tegra_hdmi_plug_states orig_state;
687         int match = 0;
688
689         mutex_lock(&hdmi->hpd_lock);
690
691         connected = tegra_dc_hpd(hdmi->dc);
692         orig_state = hdmi->plug_state;
693
694         if ((connected && orig_state == TEGRA_HDMI_MONITOR_ENABLE)) {
695                 if (hdmi_recheck_edid(hdmi, &match)) {
696                         dev_info(&hdmi->dc->ndev->dev, "hdmi: unable to read EDID\n");
697                         goto fail;
698                 } else {
699                         if (match) {
700                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: No EDID change after HPD bounce, taking no action.\n");
701                                 goto fail;
702                         } else
703                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: EDID change after HPD bounce, resetting\n");
704                 }
705         }
706
707         if ((!connected && orig_state == TEGRA_HDMI_MONITOR_DISABLE)) {
708                 dev_info(&hdmi->dc->ndev->dev, "hdmi: spurious interrupt\n");
709                 mutex_unlock(&hdmi->hpd_lock);
710                 return;
711         }
712
713         if (connected)
714                 hdmi->plug_state = TEGRA_HDMI_MONITOR_ENABLE;
715         else
716                 hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
717
718         err = tegra_hdmi_state_func[hdmi->plug_state](hdmi);
719
720         if (err < 0) {
721                         dev_info(&hdmi->dc->ndev->dev,
722                                 "hdmi state %d failed during %splug\n",
723                                 hdmi->plug_state, connected ? "" : "un");
724                         hdmi->plug_state = orig_state;
725                 } else {
726                         dev_info(&hdmi->dc->ndev->dev, "hdmi: %splugged\n",
727                                         connected ? "" : "un");
728                 }
729
730 fail:
731         mutex_unlock(&hdmi->hpd_lock);
732         return;
733 }
734
735 static irqreturn_t tegra_hdmi_hpd_irq_handler(int irq, void *ptr)
736 {
737         struct tegra_dc *dc = ptr;
738         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
739
740         if (atomic_read(&hdmi->suspended))
741                 return IRQ_HANDLED;
742
743         cancel_delayed_work(&hdmi->hpd_worker);
744         schedule_delayed_work(&hdmi->hpd_worker,
745                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS));
746
747         return IRQ_HANDLED;
748 }
749
750 static int tegra_hdmi_hpd_init(struct tegra_hdmi *hdmi)
751 {
752         struct tegra_dc *dc = hdmi->dc;
753         int hotplug_gpio = dc->out->hotplug_gpio;
754         int hotplug_irq;
755         int err;
756
757         if (!gpio_is_valid(hotplug_gpio)) {
758                 dev_err(&dc->ndev->dev, "hdmi: invalid hotplug gpio\n");
759                 return -EINVAL;
760         }
761
762         hotplug_irq = gpio_to_irq(hotplug_gpio);
763         if (hotplug_irq < 0) {
764                 dev_err(&dc->ndev->dev,
765                         "hdmi: hotplug gpio to irq map failed\n");
766                 return -EINVAL;
767         }
768
769         err = gpio_request(hotplug_gpio, "hdmi2.0_hpd");
770         if (err < 0)
771                 dev_err(&dc->ndev->dev,
772                         "hdmi: hpd gpio_request failed %d\n", err);
773         gpio_direction_input(hotplug_gpio);
774
775         err = request_threaded_irq(hotplug_irq,
776                                 NULL, tegra_hdmi_hpd_irq_handler,
777                                 (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
778                                 IRQF_ONESHOT),
779                                 dev_name(&dc->ndev->dev), dc);
780         if (err) {
781                 dev_err(&dc->ndev->dev,
782                         "hdmi: request_threaded_irq failed: %d\n", err);
783                 goto fail;
784         }
785
786
787         INIT_DELAYED_WORK(&hdmi->hpd_worker, tegra_hdmi_hpd_worker);
788
789         mutex_init(&hdmi->hpd_lock);
790         hdmi->irq = hotplug_irq;
791
792         return 0;
793 fail:
794         gpio_free(hotplug_gpio);
795         return err;
796 }
797
798 static int tegra_hdmi_tmds_init(struct tegra_hdmi *hdmi)
799 {
800         struct device_node *np_prod = of_find_node_by_path(TMDS_NODE);
801
802         if (!np_prod) {
803                 dev_warn(&hdmi->dc->ndev->dev,
804                         "hdmi: find tmds prod node failed\n");
805                 return -EINVAL;
806         }
807
808         hdmi->prod_list =
809                 tegra_prod_init((const struct device_node *)np_prod);
810         if (IS_ERR(hdmi->prod_list)) {
811                 dev_warn(&hdmi->dc->ndev->dev,
812                         "hdmi: prod list init failed with error %ld\n",
813                         PTR_ERR(hdmi->prod_list));
814                 of_node_put(np_prod);
815                 return -EINVAL;
816         }
817
818         of_node_put(np_prod);
819         return 0;
820 }
821
822 static int tegra_hdmi_config_tmds(struct tegra_hdmi *hdmi)
823 {
824         size_t tmds_len;
825         int i;
826         int err = 0;
827
828         /* Select mode with smallest clk freq > pclk */
829         tmds_len = ARRAY_SIZE(tmds_config_modes);
830         for (i = 0; i < tmds_len - 1 &&
831                 tmds_config_modes[i].clk < hdmi->dc->mode.pclk; i++);
832
833         if (tegra_platform_is_linsim())
834                 return 0;
835
836         err = tegra_prod_set_by_name(&hdmi->sor->base,
837                                 tmds_config_modes[i].name, hdmi->prod_list);
838         if (err) {
839                 dev_warn(&hdmi->dc->ndev->dev,
840                         "hdmi: tmds prod set failed\n");
841                 return -EINVAL;
842         }
843
844         return 0;
845 }
846
847 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
848 {
849         struct tegra_hdmi *hdmi;
850         int err;
851         struct device_node *np = dc->ndev->dev.of_node;
852 #ifdef CONFIG_OF
853         struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE);
854 #else
855         struct device_node *np_hdmi = NULL;
856 #endif
857         struct device_node *np_panel = NULL;
858         int edid_src = 0;
859
860         hdmi = devm_kzalloc(&dc->ndev->dev, sizeof(*hdmi), GFP_KERNEL);
861         if (!hdmi) {
862                 of_node_put(np_hdmi);
863                 return -ENOMEM;
864         }
865
866         hdmi->sor = tegra_dc_sor_init(dc, NULL);
867         if (IS_ERR_OR_NULL(hdmi->sor)) {
868                 err = PTR_ERR(hdmi->sor);
869                 goto fail;
870         }
871
872         if (np) {
873                 if (np_hdmi && of_device_is_available(np_hdmi)) {
874                         np_panel = tegra_get_panel_node_out_type_check(dc,
875                                 TEGRA_DC_OUT_HDMI);
876                         if (np_panel && of_device_is_available(np_panel)) {
877                                 if (of_property_read_bool(np_panel,
878                                                         "nvidia,edid"))
879                                         edid_src = 1;
880                                 of_node_put(np_panel);
881                         }
882                 } else {
883                         err = -EINVAL;
884                         of_node_put(np_panel);
885                         goto fail;
886                 }
887         }
888
889         hdmi->pdata = dc->pdata->default_out->hdmi_out;
890         hdmi->dc = dc;
891         dc_hdmi = hdmi;
892         hdmi->ddc_refcount = 0; /* assumes this is disabled when starting */
893         mutex_init(&hdmi->ddc_refcount_lock);
894         hdmi->nvhdcp = NULL;
895         hdmi->mon_spec_valid = false;
896         hdmi->eld_valid = false;
897         hdmi->device_shutdown = false;
898         if (0) {
899                 /* TODO: seamless boot mode needs initialize the state */
900         } else {
901                 hdmi->enabled = false;
902                 atomic_set(&hdmi->clock_refcount, 0);
903         }
904         atomic_set(&hdmi->suspended, 0);
905
906 #ifdef CONFIG_TEGRA_HDMIHDCP
907         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
908                         dc->out->ddc_bus);
909         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
910                 err = PTR_ERR(hdmi->nvhdcp);
911                 goto fail;
912         }
913         tegra_nvhdcp_debugfs_init(hdmi->nvhdcp);
914 #endif
915
916         tegra_hdmi_ddc_init(hdmi, edid_src);
917
918         tegra_hdmi_scdc_init(hdmi);
919
920         tegra_hdmi_hpd_init(hdmi);
921
922         tegra_hdmi_vrr_init(hdmi);
923
924         tegra_hdmi_debugfs_init(hdmi);
925
926         tegra_hdmi_tmds_init(hdmi);
927
928         tegra_dc_set_outdata(dc, hdmi);
929
930         /* NOTE: Below code is applicable to L4T or embedded systems and is
931          * protected accordingly. This section early enables DC with first mode
932          * from the monitor specs.
933          * In case there is no hotplug we are falling back
934          * to default VGA mode.
935          */
936         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
937                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
938                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
939                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
940                 struct fb_monspecs specs;
941                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
942                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
943                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
944                         else {
945                         /* if for some reason there is no edid upon hotplug */
946                                 tegra_dc_set_fb_mode(dc,
947                                                 &tegra_dc_vga_mode, false);
948                         }
949                 } else
950                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
951         }
952
953 #ifdef CONFIG_SWITCH
954         hdmi->hpd_switch.name = "hdmi";
955         err = switch_dev_register(&hdmi->hpd_switch);
956         if (err)
957                 dev_err(&dc->ndev->dev,
958                         "hdmi: failed to register hpd switch %d\n", err);
959
960         hdmi->audio_switch.name = "hdmi_audio";
961         err = switch_dev_register(&hdmi->audio_switch);
962         if (err)
963                 dev_err(&dc->ndev->dev,
964                         "hdmi: failed to register audio switch %d\n", err);
965 #endif
966
967         hdmi_ddc = kobject_create_and_add("hdmi_ddc_power_toggle", kernel_kobj);
968         if (!hdmi_ddc) {
969                 pr_warn("kobject create_and_add hdmi_ddc_power_toggle failed\n");
970                 return 0;
971         }
972         err = sysfs_create_file(hdmi_ddc, &hdmi_ddc_power_config.attr);
973         if (err) {
974                 pr_warn("sysfs create file hdmi_ddc_power_toggle failed\n");
975                 return 0;
976         }
977
978         of_node_put(np_hdmi);
979         return 0;
980 fail:
981         devm_kfree(&dc->ndev->dev, hdmi);
982         of_node_put(np_hdmi);
983         return err;
984 }
985
986 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
987 {
988         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
989
990         tegra_dc_sor_destroy(hdmi->sor);
991         tegra_edid_destroy(hdmi->edid);
992         tegra_nvhdcp_destroy(hdmi->nvhdcp);
993         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
994         gpio_free(dc->out->hotplug_gpio);
995         devm_kfree(&dc->ndev->dev, hdmi);
996         tegra_prod_release(&hdmi->prod_list);
997
998 #ifdef CONFIG_SWITCH
999         switch_dev_unregister(&hdmi->hpd_switch);
1000         switch_dev_unregister(&hdmi->audio_switch);
1001 #endif
1002 }
1003
1004 static void tegra_hdmi_config(struct tegra_hdmi *hdmi)
1005 {
1006         struct tegra_dc_sor_data *sor = hdmi->sor;
1007         struct tegra_dc *dc = hdmi->dc;
1008 #ifndef CONFIG_TEGRA_NVDISPLAY
1009         u32 h_pulse_start, h_pulse_end;
1010 #endif
1011         u32 hblank, max_ac, rekey;
1012         unsigned long val;
1013         u32 dispclk_div_8_2;
1014
1015         if (tegra_platform_is_linsim())
1016                 return;
1017
1018         tegra_sor_write_field(sor, NV_SOR_INPUT_CONTROL,
1019                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED |
1020                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB,
1021                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL |
1022                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB);
1023
1024         dispclk_div_8_2 = clk_get_rate(hdmi->sor->sor_clk) / 1000000 * 4;
1025         tegra_sor_writel(sor, NV_SOR_REFCLK,
1026                         NV_SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1027                         NV_SOR_REFCLK_DIV_FRAC(dispclk_div_8_2));
1028
1029         rekey = NV_SOR_HDMI_CTRL_REKEY_DEFAULT;
1030         hblank = dc->mode.h_sync_width + dc->mode.h_back_porch +
1031                         dc->mode.h_front_porch;
1032         max_ac = (hblank - rekey - 18) / 32;
1033
1034         val = 0;
1035         val |= hdmi->dvi ? 0x0 : NV_SOR_HDMI_CTRL_ENABLE;
1036         /* The register wants "-2" of the required rekey val */
1037         val |= NV_SOR_HDMI_CTRL_REKEY(rekey - 2);
1038         val |= NV_SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac);
1039         val |= NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT;
1040         tegra_sor_writel(sor, NV_SOR_HDMI_CTRL, val);
1041
1042 #ifndef CONFIG_TEGRA_NVDISPLAY
1043         tegra_dc_writel(dc, 0x180, DC_DISP_H_PULSE2_CONTROL);
1044         h_pulse_start = dc->mode.h_ref_to_sync +
1045                                         dc->mode.h_sync_width +
1046                                         dc->mode.h_back_porch - 10;
1047         h_pulse_end = h_pulse_start + 8;
1048         tegra_dc_writel(dc, PULSE_START(h_pulse_start) | PULSE_END(h_pulse_end),
1049                   DC_DISP_H_PULSE2_POSITION_A);
1050
1051         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1052         val |= H_PULSE_2_ENABLE;
1053         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
1054 #endif
1055 }
1056
1057 void tegra_hdmi_infoframe_pkt_write(struct tegra_hdmi *hdmi,
1058                                                 u32 header_reg, u8 pkt_type,
1059                                                 u8 pkt_vs, u8 pkt_len,
1060                                                 void *reg_payload,
1061                                                 u32 reg_payload_len,
1062                                                 bool sw_checksum)
1063 {
1064         struct tegra_dc_sor_data *sor = hdmi->sor;
1065         u32 val;
1066         u32 *data = reg_payload;
1067         u32 data_reg = header_reg + 1;
1068
1069         val = NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(pkt_type) |
1070                 NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(pkt_vs) |
1071                 NV_SOR_HDMI_INFOFRAME_HEADER_LEN(pkt_len);
1072         tegra_sor_writel(sor, header_reg, val);
1073
1074         if (sw_checksum) {
1075                 u8 checksum = pkt_type + pkt_vs + pkt_len;
1076
1077                 for (val = 1; val <= pkt_len; val++)
1078                         checksum += ((u8 *)reg_payload)[val];
1079
1080                 /* The first byte of the payload must always be the checksum
1081                  * that we are going to calculate in SW */
1082                 ((u8 *)reg_payload)[0] = (256 - checksum);
1083         }
1084
1085         for (val = 0; val < reg_payload_len; val += 4, data_reg++, data++)
1086                 tegra_sor_writel(sor, data_reg, *data);
1087 }
1088
1089 static u32 tegra_hdmi_get_cea_modedb_size(struct tegra_hdmi *hdmi)
1090 {
1091         if (!tegra_hdmi_is_connected(hdmi) || !hdmi->mon_spec_valid)
1092                 return 0;
1093
1094         return (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM) ?
1095                 CEA_861_F_MODEDB_SIZE : CEA_861_D_MODEDB_SIZE;
1096 }
1097
1098 static void tegra_hdmi_get_cea_fb_videomode(struct fb_videomode *m,
1099                                                 struct tegra_hdmi *hdmi)
1100 {
1101         struct tegra_dc *dc = hdmi->dc;
1102         struct tegra_dc_mode dc_mode;
1103         int yuv_flag;
1104
1105         memcpy(&dc_mode, &dc->mode, sizeof(dc->mode));
1106
1107         /* get CEA video timings */
1108         yuv_flag = dc_mode.vmode & FB_VMODE_YUV_MASK;
1109         if (yuv_flag == (FB_VMODE_Y420      | FB_VMODE_Y24) ||
1110             yuv_flag == (FB_VMODE_Y420_ONLY | FB_VMODE_Y24)) {
1111                 dc_mode.h_back_porch *= 2;
1112                 dc_mode.h_front_porch *= 2;
1113                 dc_mode.h_sync_width *= 2;
1114                 dc_mode.h_active *= 2;
1115                 dc_mode.pclk *= 2;
1116         } else if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) {
1117                 dc_mode.h_back_porch = (dc_mode.h_back_porch * 8) / 5;
1118                 dc_mode.h_front_porch = (dc_mode.h_front_porch * 8) / 5;
1119                 dc_mode.h_sync_width = (dc_mode.h_sync_width * 8) / 5;
1120                 dc_mode.h_active = (dc_mode.h_active * 8) / 5;
1121                 dc_mode.pclk = (dc_mode.pclk / 5) * 8;
1122         }
1123
1124         if (dc_mode.vmode & FB_VMODE_1000DIV1001) {
1125                 dc_mode.pclk = DIV_ROUND_UP((u64)dc_mode.pclk * 1001,  1000);
1126                 dc_mode.vmode &= ~FB_VMODE_1000DIV1001;
1127         }
1128
1129         tegra_dc_to_fb_videomode(m, &dc_mode);
1130
1131         /* only interlaced required for VIC identification */
1132         m->vmode &= FB_VMODE_INTERLACED;
1133 }
1134
1135 __maybe_unused
1136 static int tegra_hdmi_find_cea_vic(struct tegra_hdmi *hdmi)
1137 {
1138         struct fb_videomode m;
1139         struct tegra_dc *dc = hdmi->dc;
1140         unsigned i;
1141         unsigned best = 0;
1142         u32 modedb_size = tegra_hdmi_get_cea_modedb_size(hdmi);
1143
1144         if (dc->initialized) {
1145                 u32 vic = tegra_sor_readl(hdmi->sor,
1146                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH) & 0xff;
1147                 if (!vic)
1148                         dev_warn(&dc->ndev->dev, "hdmi: BL set VIC 0\n");
1149                 return vic;
1150         }
1151
1152         tegra_hdmi_get_cea_fb_videomode(&m, hdmi);
1153
1154         m.flag &= ~FB_FLAG_RATIO_MASK;
1155         m.flag |= tegra_dc_get_aspect_ratio(dc);
1156
1157         for (i = 1; i < modedb_size; i++) {
1158                 const struct fb_videomode *curr = &cea_modes[i];
1159
1160                 if (!((m.refresh == curr->refresh ||
1161                        m.refresh + 1 == curr->refresh ||
1162                        m.refresh == curr->refresh + 1) &&
1163                       m.xres         == curr->xres &&
1164                       m.yres         == curr->yres &&
1165                       (m.pixclock    == curr->pixclock ||
1166                       (m.pixclock * 1001 / 1000) == curr->pixclock) &&
1167                       m.hsync_len    == curr->hsync_len &&
1168                       m.vsync_len    == curr->vsync_len &&
1169                       m.left_margin  == curr->left_margin &&
1170                       m.right_margin == curr->right_margin &&
1171                       m.upper_margin == curr->upper_margin &&
1172                       m.lower_margin == curr->lower_margin &&
1173                       m.sync         == curr->sync &&
1174                       m.vmode        == curr->vmode))
1175                         continue;
1176
1177                 if (!best)
1178                         best = i;
1179                 /* if either flag is set, then match is required */
1180                 if (curr->flag &
1181                         (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9 |
1182                         FB_FLAG_RATIO_64_27 | FB_FLAG_RATIO_256_135)) {
1183                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1184                                 best = i;
1185                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1186                                 best = i;
1187                         else if (m.flag & curr->flag & FB_FLAG_RATIO_64_27)
1188                                 best = i;
1189                         else if (m.flag & curr->flag & FB_FLAG_RATIO_256_135)
1190                                 best = i;
1191                 } else {
1192                         best = i;
1193                 }
1194         }
1195         return best;
1196 }
1197
1198 static u32 tegra_hdmi_get_aspect_ratio(struct tegra_hdmi *hdmi)
1199 {
1200         u32 aspect_ratio;
1201
1202         switch (hdmi->dc->mode.avi_m) {
1203         case TEGRA_DC_MODE_AVI_M_4_3:
1204                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1205                 break;
1206         case TEGRA_DC_MODE_AVI_M_16_9:
1207                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1208                 break;
1209         /*
1210          * no avi_m field for picture aspect ratio 64:27 and 256:135.
1211          * sink detects via VIC, avi_m is 0.
1212          */
1213         case TEGRA_DC_MODE_AVI_M_64_27: /* fall through */
1214         case TEGRA_DC_MODE_AVI_M_256_135: /* fall through */
1215         default:
1216                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1217         }
1218
1219         /* For seamless HDMI, read aspect ratio parameters from bootloader
1220          * set AVI Infoframe parameters
1221          */
1222         if ((aspect_ratio == HDMI_AVI_ASPECT_RATIO_NO_DATA) &&
1223                                         (hdmi->dc->initialized)) {
1224                 u32 temp = 0;
1225                 temp = tegra_sor_readl(hdmi->sor,
1226                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1227                 temp = (temp >> 20) & 0x3;
1228                 switch (temp) {
1229                 case 1:
1230                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1231                 break;
1232                 case 2:
1233                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1234                 break;
1235                 default:
1236                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1237                 }
1238         }
1239         return aspect_ratio;
1240 }
1241
1242 static u32 tegra_hdmi_get_rgb_ycc(struct tegra_hdmi *hdmi)
1243 {
1244         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1245
1246         /*
1247          * For seamless HDMI, read YUV flag parameters from bootloader
1248          * set AVI Infoframe parameters
1249          */
1250         if (hdmi->dc->initialized) {
1251                 u32 temp = 0;
1252                 temp = tegra_sor_readl(hdmi->sor,
1253                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1254                 temp = (temp >> 12) & 0x3;
1255                 switch (temp) {
1256                 case HDMI_AVI_RGB:
1257                         return HDMI_AVI_RGB;
1258                 case HDMI_AVI_YCC_420:
1259                         return HDMI_AVI_YCC_420;
1260                 default:
1261                         dev_warn(&hdmi->dc->ndev->dev, "hdmi: BL didn't set RGB/YUV indicator flag\n");
1262                         break;
1263                 }
1264         }
1265
1266         if (yuv_flag & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1267                 return HDMI_AVI_YCC_420;
1268         else if (yuv_flag & FB_VMODE_Y422)
1269                 return HDMI_AVI_YCC_422;
1270
1271         return HDMI_AVI_RGB;
1272 }
1273
1274 static bool tegra_hdmi_is_ex_colorimetry(struct tegra_hdmi *hdmi)
1275 {
1276         return !!(hdmi->dc->mode.vmode & FB_VMODE_EC_ENABLE);
1277 }
1278
1279 static u32 tegra_hdmi_get_ex_colorimetry(struct tegra_hdmi *hdmi)
1280 {
1281         u32 vmode = hdmi->dc->mode.vmode;
1282
1283         return tegra_hdmi_is_ex_colorimetry(hdmi) ?
1284                 ((vmode & FB_VMODE_EC_MASK) >> FB_VMODE_EC_SHIFT) :
1285                 HDMI_AVI_EXT_COLORIMETRY_INVALID;
1286 }
1287
1288 static void tegra_hdmi_avi_infoframe_update(struct tegra_hdmi *hdmi)
1289 {
1290         struct hdmi_avi_infoframe *avi = &hdmi->avi;
1291
1292         memset(&hdmi->avi, 0, sizeof(hdmi->avi));
1293
1294         if (tegra_platform_is_linsim())
1295                 return;
1296
1297         avi->scan = HDMI_AVI_UNDERSCAN;
1298         avi->bar_valid = HDMI_AVI_BAR_INVALID;
1299         avi->act_fmt_valid = HDMI_AVI_ACTIVE_FORMAT_VALID;
1300         avi->rgb_ycc = tegra_hdmi_get_rgb_ycc(hdmi);
1301
1302         avi->act_format = HDMI_AVI_ACTIVE_FORMAT_SAME;
1303         avi->aspect_ratio = tegra_hdmi_get_aspect_ratio(hdmi);
1304         avi->colorimetry = tegra_hdmi_is_ex_colorimetry(hdmi) ?
1305                         HDMI_AVI_COLORIMETRY_EXTENDED_VALID :
1306                         HDMI_AVI_COLORIMETRY_DEFAULT;
1307
1308         avi->scaling = HDMI_AVI_SCALING_UNKNOWN;
1309         avi->rgb_quant = HDMI_AVI_RGB_QUANT_DEFAULT;
1310         avi->ext_colorimetry = tegra_hdmi_get_ex_colorimetry(hdmi);
1311         avi->it_content = HDMI_AVI_IT_CONTENT_FALSE;
1312
1313         /* set correct vic if video format is cea defined else set 0 */
1314         avi->video_format = tegra_hdmi_find_cea_vic(hdmi);
1315
1316         avi->pix_rep = HDMI_AVI_NO_PIX_REPEAT;
1317         avi->it_content_type = HDMI_AVI_IT_CONTENT_NONE;
1318         avi->ycc_quant = HDMI_AVI_YCC_QUANT_NONE;
1319
1320         avi->top_bar_end_line_low_byte = 0;
1321         avi->top_bar_end_line_high_byte = 0;
1322
1323         avi->bot_bar_start_line_low_byte = 0;
1324         avi->bot_bar_start_line_high_byte = 0;
1325
1326         avi->left_bar_end_pixel_low_byte = 0;
1327         avi->left_bar_end_pixel_high_byte = 0;
1328
1329         avi->right_bar_start_pixel_low_byte = 0;
1330         avi->right_bar_start_pixel_high_byte = 0;
1331 }
1332
1333 static void tegra_hdmi_avi_infoframe(struct tegra_hdmi *hdmi)
1334 {
1335         struct tegra_dc_sor_data *sor = hdmi->sor;
1336
1337         if (hdmi->dvi)
1338                 return;
1339
1340         if (tegra_platform_is_linsim())
1341                 return;
1342
1343         /* disable avi infoframe before configuring except for seamless case */
1344         if (!hdmi->dc->initialized)
1345                 tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL, 0);
1346
1347         tegra_hdmi_avi_infoframe_update(hdmi);
1348
1349         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AVI_INFOFRAME_HEADER,
1350                                         HDMI_INFOFRAME_TYPE_AVI,
1351                                         HDMI_INFOFRAME_VS_AVI,
1352                                         HDMI_INFOFRAME_LEN_AVI,
1353                                         &hdmi->avi, sizeof(hdmi->avi),
1354                                         false);
1355
1356         /* Send infoframe every frame, checksum hw generated */
1357         tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL,
1358                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES |
1359                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE |
1360                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE |
1361                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1362 }
1363
1364 static int tegra_hdmi_get_extended_vic(const struct tegra_dc_mode *mode)
1365 {
1366         struct fb_videomode m;
1367         struct tegra_dc_mode mode_fixed;
1368         unsigned i;
1369
1370         mode_fixed = *mode;
1371
1372         if (mode_fixed.vmode & FB_VMODE_1000DIV1001) {
1373                 mode_fixed.pclk = DIV_ROUND_UP((u64)mode_fixed.pclk * 1001,
1374                                                         1000);
1375                 mode_fixed.vmode &= ~FB_VMODE_1000DIV1001;
1376         }
1377
1378         tegra_dc_to_fb_videomode(&m, &mode_fixed);
1379
1380         /* only interlaced required for VIC identification */
1381         m.vmode &= FB_VMODE_INTERLACED;
1382
1383         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1384                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1385
1386                 /*
1387                  * We have to make sure we explicitly don't check m.refresh ==
1388                  * curr->refresh (or use the fb_mode_is_equal() which does this
1389                  * check). This is because of the lack of accuracy when going
1390                  * between fb_videomode -> tegra_dc_mode -> fb_videomode. For
1391                  * 1000/1001 modes, the calculated m->refresh is actually not
1392                  * accurate. This is honestly a hack and does need to be fixed,
1393                  * but is a WAR for now for HDMI certification
1394                  */
1395                 if ((m.refresh == curr->refresh ||
1396                      m.refresh + 1 == curr->refresh) &&
1397                     m.xres         == curr->xres &&
1398                     m.yres         == curr->yres &&
1399                     m.pixclock     == curr->pixclock &&
1400                     m.hsync_len    == curr->hsync_len &&
1401                     m.vsync_len    == curr->vsync_len &&
1402                     m.left_margin  == curr->left_margin &&
1403                     m.right_margin == curr->right_margin &&
1404                     m.upper_margin == curr->upper_margin &&
1405                     m.lower_margin == curr->lower_margin &&
1406                     m.sync         == curr->sync &&
1407                     m.vmode        == curr->vmode)
1408                         return i;
1409         }
1410         return 0;
1411 }
1412
1413 static void tegra_hdmi_vendor_infoframe_update(struct tegra_hdmi *hdmi)
1414 {
1415         struct hdmi_vendor_infoframe *vsi = &hdmi->vsi;
1416         u8 extended_vic;
1417
1418         memset(&hdmi->vsi, 0, sizeof(hdmi->vsi));
1419
1420         vsi->oui = HDMI_LICENSING_LLC_OUI;
1421
1422         extended_vic = tegra_hdmi_get_extended_vic(&hdmi->dc->mode);
1423         if (extended_vic) {
1424                 vsi->video_format =
1425                         HDMI_VENDOR_VIDEO_FORMAT_EXTENDED;
1426                 vsi->extended_vic = extended_vic;
1427         }
1428 }
1429
1430 static void tegra_hdmi_vendor_infoframe(struct tegra_hdmi *hdmi)
1431 {
1432 /* hdmi licensing, LLC vsi playload len as per hdmi1.4b  */
1433 #define HDMI_INFOFRAME_LEN_VENDOR_LLC   (6)
1434
1435         struct tegra_dc_sor_data *sor = hdmi->sor;
1436
1437         if (hdmi->dvi)
1438                 return;
1439
1440         /* disable vsi infoframe before configuring */
1441         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL, 0);
1442
1443         tegra_hdmi_vendor_infoframe_update(hdmi);
1444
1445         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_VSI_INFOFRAME_HEADER,
1446                                         HDMI_INFOFRAME_TYPE_VENDOR,
1447                                         HDMI_INFOFRAME_VS_VENDOR,
1448                                         HDMI_INFOFRAME_LEN_VENDOR_LLC,
1449                                         &hdmi->vsi, sizeof(hdmi->vsi),
1450                                         false);
1451
1452         /* Send infoframe every frame, checksum hw generated */
1453         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL,
1454                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES |
1455                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE |
1456                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE |
1457                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1458
1459 #undef HDMI_INFOFRAME_LEN_VENDOR_LLC
1460 }
1461
1462 static void tegra_hdmi_hdr_infoframe_update(struct tegra_hdmi *hdmi)
1463 {
1464         struct hdmi_hdr_infoframe *hdr = &hdmi->hdr;
1465
1466         memset(&hdmi->hdr, 0, sizeof(hdmi->hdr));
1467
1468         if (tegra_platform_is_linsim())
1469                 return;
1470
1471         hdr->eotf = hdmi->dc->hdr.eotf;
1472         hdr->static_metadata_id = hdmi->dc->hdr.static_metadata_id;
1473
1474         /* PB3-14 : Group 1 : Static Metadata*/
1475         hdr->display_primaries_x_0_lsb = hdmi->dc->hdr.static_metadata[0];
1476         hdr->display_primaries_x_0_msb = hdmi->dc->hdr.static_metadata[1];
1477         hdr->display_primaries_y_0_lsb = hdmi->dc->hdr.static_metadata[2];
1478         hdr->display_primaries_y_0_msb = hdmi->dc->hdr.static_metadata[3];
1479         hdr->display_primaries_x_1_lsb = hdmi->dc->hdr.static_metadata[4];
1480         hdr->display_primaries_x_1_msb = hdmi->dc->hdr.static_metadata[5];
1481         hdr->display_primaries_y_1_lsb = hdmi->dc->hdr.static_metadata[6];
1482         hdr->display_primaries_y_1_msb = hdmi->dc->hdr.static_metadata[7];
1483         hdr->display_primaries_x_2_lsb = hdmi->dc->hdr.static_metadata[8];
1484         hdr->display_primaries_x_2_msb = hdmi->dc->hdr.static_metadata[9];
1485         hdr->display_primaries_y_2_lsb = hdmi->dc->hdr.static_metadata[10];
1486         hdr->display_primaries_y_2_msb = hdmi->dc->hdr.static_metadata[11];
1487
1488         /* PB15-18 : Group 2 : Static Metadata*/
1489         hdr->white_point_x_lsb = hdmi->dc->hdr.static_metadata[12];
1490         hdr->white_point_x_msb = hdmi->dc->hdr.static_metadata[13];
1491         hdr->white_point_y_lsb = hdmi->dc->hdr.static_metadata[14];
1492         hdr->white_point_y_msb = hdmi->dc->hdr.static_metadata[15];
1493
1494         /* PB19-20 : Group 3 : Static Metadata*/
1495         hdr->max_display_mastering_luminance_lsb =
1496                                         hdmi->dc->hdr.static_metadata[16];
1497         hdr->max_display_mastering_luminance_msb =
1498                                         hdmi->dc->hdr.static_metadata[17];
1499
1500         /* PB21-22 : Group 4 : Static Metadata*/
1501         hdr->min_display_mastering_luminance_lsb =
1502                                         hdmi->dc->hdr.static_metadata[18];
1503         hdr->min_display_mastering_luminance_msb =
1504                                         hdmi->dc->hdr.static_metadata[19];
1505
1506         /* PB23-24 : Group 5 : Static Metadata*/
1507         hdr->max_content_light_level_lsb = hdmi->dc->hdr.static_metadata[20];
1508         hdr->max_content_light_level_msb = hdmi->dc->hdr.static_metadata[21];
1509
1510         /* PB25-26 : Group 6 : Static Metadata*/
1511         hdr->max_frame_avg_light_level_lsb = hdmi->dc->hdr.static_metadata[22];
1512         hdr->min_frame_avg_light_level_msb = hdmi->dc->hdr.static_metadata[23];
1513
1514         return;
1515 }
1516
1517 static void tegra_hdmi_hdr_infoframe(struct tegra_hdmi *hdmi)
1518 {
1519         struct tegra_dc_sor_data *sor = hdmi->sor;
1520
1521         /* disable generic infoframe before configuring */
1522         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, 0);
1523
1524         tegra_hdmi_hdr_infoframe_update(hdmi);
1525
1526         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_GENERIC_HEADER,
1527                                         HDMI_INFOFRAME_TYPE_HDR,
1528                                         HDMI_INFOFRAME_VS_HDR,
1529                                         HDMI_INFOFRAME_LEN_HDR,
1530                                         &hdmi->hdr, sizeof(hdmi->hdr),
1531                                         true);
1532
1533         /* Send infoframe every frame, checksum hw generated */
1534         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL,
1535                 NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES |
1536                 NV_SOR_HDMI_GENERIC_CTRL_OTHER_DISABLE |
1537                 NV_SOR_HDMI_GENERIC_CTRL_SINGLE_DISABLE);
1538         return;
1539 }
1540
1541 __maybe_unused
1542 static int tegra_hdmi_scdc_read(struct tegra_hdmi *hdmi,
1543                                         u8 offset_data[][2], u32 n_entries)
1544 {
1545         u32 i;
1546         struct i2c_msg msg[] = {
1547                 {
1548                         .addr = 0x54,
1549                         .len = 1,
1550                         .buf = NULL,
1551                 },
1552                 {
1553                         .addr = 0x54,
1554                         .flags = I2C_M_RD,
1555                         .len = 1,
1556                         .buf = NULL,
1557                 },
1558         };
1559
1560         _tegra_hdmi_ddc_enable(hdmi);
1561
1562         for (i = 0; i < n_entries; i++) {
1563                 msg[0].buf = offset_data[i];
1564                 msg[1].buf = &offset_data[i][1];
1565                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1566         }
1567
1568         _tegra_hdmi_ddc_disable(hdmi);
1569
1570         return 0;
1571 }
1572
1573 static int tegra_hdmi_scdc_write(struct tegra_hdmi *hdmi,
1574                                         u8 offset_data[][2], u32 n_entries)
1575 {
1576         u32 i;
1577         struct i2c_msg msg[] = {
1578                 {
1579                         .addr = 0x54,
1580                         .len = 2,
1581                         .buf = NULL,
1582                 },
1583         };
1584
1585         _tegra_hdmi_ddc_enable(hdmi);
1586
1587         for (i = 0; i < n_entries; i++) {
1588                 msg[0].buf = offset_data[i];
1589                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1590         }
1591
1592         _tegra_hdmi_ddc_disable(hdmi);
1593
1594         return 0;
1595 }
1596
1597 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable)
1598 {
1599         u8 tmds_config_en[][2] = {
1600                 {
1601                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1602                         (HDMI_SCDC_TMDS_CONFIG_BIT_CLK_RATIO_40 |
1603                         HDMI_SCDC_TMDS_CONFIG_SCRAMBLING_EN)
1604                 },
1605         };
1606         u8 tmds_config_dis[][2] = {
1607                 {
1608                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1609                         0
1610                 },
1611         };
1612
1613         if (hdmi->dc->vedid)
1614                 goto skip_scdc_i2c;
1615
1616         tegra_hdmi_scdc_write(hdmi,
1617                         enable ? tmds_config_en : tmds_config_dis,
1618                         ARRAY_SIZE(tmds_config_en));
1619
1620 skip_scdc_i2c:
1621         return 0;
1622 }
1623
1624 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable)
1625 {
1626         u32 val = NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1627                 NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4;
1628
1629         tegra_sor_write_field(hdmi->sor, NV_SOR_HDMI2_CTRL,
1630                         NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1631                         NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4,
1632                         enable ? val : 0);
1633 }
1634
1635 static int _tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1636 {
1637 #define SCDC_STABILIZATION_DELAY_MS (20)
1638
1639         /* disable hdmi2.x config on host and monitor only
1640          * if bootloader didn't initialize hdmi
1641          */
1642         if (!hdmi->dc->initialized) {
1643                 tegra_hdmi_v2_x_mon_config(hdmi, false);
1644                 tegra_hdmi_v2_x_host_config(hdmi, false);
1645         }
1646
1647         /* enable hdmi2.x config on host and monitor */
1648         tegra_hdmi_v2_x_mon_config(hdmi, true);
1649         msleep(SCDC_STABILIZATION_DELAY_MS);
1650
1651         tegra_hdmi_v2_x_host_config(hdmi, true);
1652
1653         return 0;
1654 #undef SCDC_STABILIZATION_DELAY_MS
1655 }
1656
1657 static int tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1658 {
1659         _tegra_hdmi_v2_x_config(hdmi);
1660
1661         return 0;
1662 }
1663
1664 static void tegra_hdmi_scdc_worker(struct work_struct *work)
1665 {
1666         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
1667                                 struct tegra_hdmi, scdc_work);
1668         u8 rd_status_flags[][2] = {
1669                 {HDMI_SCDC_STATUS_FLAGS, 0x0}
1670         };
1671
1672         if (!hdmi->enabled || hdmi->dc->mode.pclk <= 340000000)
1673                 return;
1674
1675         if (hdmi->dc->vedid)
1676                 goto skip_scdc_i2c;
1677
1678         if (!tegra_edid_is_scdc_present(hdmi->dc->edid))
1679                 return;
1680
1681         tegra_hdmi_scdc_read(hdmi, rd_status_flags,
1682                                         ARRAY_SIZE(rd_status_flags));
1683         if (!rd_status_flags[0][1]  && (hdmi->dc->mode.pclk > 340000000)) {
1684                 dev_info(&hdmi->dc->ndev->dev, "hdmi: scdc scrambling status is reset, "
1685                                                 "trying to reconfigure.\n");
1686                 _tegra_hdmi_v2_x_config(hdmi);
1687         }
1688
1689 skip_scdc_i2c:
1690         /* reschedule the worker */
1691         cancel_delayed_work(&hdmi->scdc_work);
1692         schedule_delayed_work(&hdmi->scdc_work,
1693                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1694 }
1695
1696 static void _tegra_hdmi_clock_enable(struct tegra_hdmi *hdmi)
1697 {
1698         struct tegra_dc_sor_data *sor = hdmi->sor;
1699         tegra_disp_clk_prepare_enable(sor->safe_clk);
1700         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
1701         tegra_sor_clk_enable(sor);
1702 }
1703
1704 static void _tegra_hdmi_clock_disable(struct tegra_hdmi *hdmi)
1705 {
1706         struct tegra_dc_sor_data *sor = hdmi->sor;
1707         tegra_sor_clk_disable(sor);
1708 }
1709
1710 void tegra_hdmi_get(struct tegra_dc *dc)
1711 {
1712         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1713
1714         if (atomic_inc_return(&hdmi->clock_refcount) == 1)
1715                 _tegra_hdmi_clock_enable(hdmi);
1716 }
1717
1718 void tegra_hdmi_put(struct tegra_dc *dc)
1719 {
1720         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1721
1722         if (WARN_ONCE(atomic_read(&hdmi->clock_refcount) <= 0,
1723                 "hdmi: clock refcount imbalance"))
1724                 return;
1725         if (atomic_dec_return(&hdmi->clock_refcount) == 0)
1726                 _tegra_hdmi_clock_disable(hdmi);
1727 }
1728
1729 /* TODO: add support for other deep colors */
1730 static inline u32 tegra_hdmi_get_bpp(struct tegra_hdmi *hdmi)
1731 {
1732         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1733
1734         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1735                 return 30;
1736
1737         return 24;
1738 }
1739
1740 static u32 tegra_hdmi_gcp_color_depth(struct tegra_hdmi *hdmi)
1741 {
1742         u32 gcp_cd = 0;
1743
1744         switch (tegra_hdmi_get_bpp(hdmi)) {
1745         case 0: /* fall through */
1746         case 24:
1747                 gcp_cd = TEGRA_HDMI_BPP_UNKNOWN;
1748                 break;
1749         case 30:
1750                 gcp_cd = TEGRA_HDMI_BPP_30;
1751                 break;
1752         case 36:
1753                 gcp_cd = TEGRA_HDMI_BPP_36;
1754                 break;
1755         case 48:
1756                 gcp_cd = TEGRA_HDMI_BPP_48;
1757                 break;
1758         default:
1759                 dev_WARN(&hdmi->dc->ndev->dev,
1760                         "hdmi: unknown gcp color depth\n");
1761         };
1762
1763         return gcp_cd;
1764 }
1765
1766 /* return packing phase of last pixel in preceding video data period */
1767 static u32 tegra_hdmi_gcp_packing_phase(struct tegra_hdmi *hdmi)
1768 {
1769         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1770
1771         if (!tegra_hdmi_gcp_color_depth(hdmi))
1772                 return 0;
1773
1774         /* 10P4 for yuv420 10bpc */
1775         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1776                 return 0;
1777
1778          return 0;
1779 }
1780
1781 static bool tegra_hdmi_gcp_default_phase_en(struct tegra_hdmi *hdmi)
1782 {
1783         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1784
1785         if (!tegra_hdmi_gcp_color_depth(hdmi))
1786                 return false;
1787
1788         if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
1789                 return true;
1790
1791         return false;
1792 }
1793
1794 /* general control packet */
1795 static void tegra_hdmi_gcp(struct tegra_hdmi *hdmi)
1796 {
1797 #define GCP_SB1_PP_SHIFT 4
1798
1799         struct tegra_dc_sor_data *sor = hdmi->sor;
1800         u8 sb1, sb2;
1801
1802         /* disable gcp before configuring */
1803         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL, 0);
1804
1805         sb1 = tegra_hdmi_gcp_packing_phase(hdmi) << GCP_SB1_PP_SHIFT |
1806                 tegra_hdmi_gcp_color_depth(hdmi);
1807         sb2 = !!tegra_hdmi_gcp_default_phase_en(hdmi);
1808         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_SUBPACK(0),
1809                         sb1 << NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT |
1810                         sb2 << NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT);
1811
1812         /* Send gcp every frame */
1813         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL,
1814                         NV_SOR_HDMI_GCP_CTRL_ENABLE |
1815                         NV_SOR_HDMI_GCP_CTRL_OTHER_DIS |
1816                         NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS);
1817
1818 #undef GCP_SB1_PP_SHIFT
1819 }
1820
1821 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi)
1822 {
1823         struct tegra_dc *dc = hdmi->dc;
1824         struct tegra_dc_sor_data *sor = hdmi->sor;
1825
1826         tegra_dc_get(dc);
1827         tegra_hdmi_get(dc);
1828
1829         tegra_sor_hdmi_pad_power_up(sor);
1830
1831         tegra_sor_power_lanes(sor, 4, true);
1832
1833         tegra_dc_sor_set_internal_panel(sor, false);
1834         tegra_hdmi_config(hdmi);
1835         tegra_hdmi_avi_infoframe(hdmi);
1836         tegra_hdmi_vendor_infoframe(hdmi);
1837
1838         tegra_sor_pad_cal_power(sor, true);
1839         tegra_hdmi_config_tmds(hdmi);
1840         tegra_sor_pad_cal_power(sor, false);
1841
1842         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_BRICK_CLK);
1843         tegra_dc_sor_attach(sor);
1844         tegra_nvhdcp_set_plug(hdmi->nvhdcp, tegra_dc_hpd(dc));
1845
1846         tegra_dc_setup_clk(dc, dc->clk);
1847         tegra_dc_hdmi_setup_clk(dc, hdmi->sor->sor_clk);
1848         tegra_hdmi_config(hdmi);
1849
1850         tegra_sor_config_xbar(hdmi->sor);
1851
1852         /* TODO: Confirm sequence with HW */
1853         tegra_sor_writel(sor,  NV_SOR_SEQ_INST(0), 0x8080);
1854         tegra_sor_writel(sor,  NV_SOR_PWR, 0x80000001);
1855
1856         if (hdmi->dc->mode.pclk > 340000000) {
1857                 tegra_hdmi_v2_x_config(hdmi);
1858                 schedule_delayed_work(&hdmi->scdc_work,
1859                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1860         }
1861
1862         tegra_hdmi_gcp(hdmi);
1863
1864         tegra_dc_put(dc);
1865         return 0;
1866 }
1867
1868 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1869 {
1870         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1871
1872         if (hdmi->enabled)
1873                 return;
1874
1875         tegra_hdmi_controller_enable(hdmi);
1876
1877         hdmi->enabled = true;
1878         tegra_hda_set_data(hdmi, SINK_HDMI);
1879 #ifdef CONFIG_SWITCH
1880         if (!hdmi->dvi)
1881                 switch_set_state(&hdmi->audio_switch, 1);
1882 #endif
1883 }
1884
1885 static inline u32 tegra_hdmi_get_shift_clk_div(struct tegra_hdmi *hdmi)
1886 {
1887         /*
1888          * HW does not support deep color yet
1889          * always return 0
1890          */
1891
1892         return 0;
1893 }
1894
1895 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
1896 {
1897         if (clk_type == hdmi->clk_type)
1898                 return;
1899
1900         if (tegra_platform_is_linsim())
1901                 return;
1902
1903         if (clk_type == TEGRA_HDMI_BRICK_CLK) {
1904                 u32 val;
1905                 struct tegra_dc_sor_data *sor = hdmi->sor;
1906                 int div = hdmi->dc->mode.pclk < 340000000 ? 1 : 2;
1907                 unsigned long rate = clk_get_rate(sor->src_switch_clk);
1908                 unsigned long parent_rate =
1909                         clk_get_rate(clk_get_parent(sor->src_switch_clk));
1910
1911                 /* Set sor divider */
1912                 if (rate != parent_rate / div) {
1913                         rate = parent_rate / div;
1914                         clk_set_rate(sor->src_switch_clk, rate);
1915                 }
1916
1917                 /* Select brick muxes */
1918                 val = (hdmi->dc->mode.pclk < 340000000) ?
1919                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 :
1920                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4;
1921
1922                 val |= NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1923                 tegra_sor_writel(hdmi->sor, NV_SOR_CLK_CNTRL, val);
1924                 usleep_range(250, 300); /* sor brick pll stabilization delay */
1925
1926                 /*
1927                  * Report brick configuration and rate, so that SOR clock tree
1928                  * is properly updated. No h/w changes by clock api calls below,
1929                  * just sync s/w state with brick h/w.
1930                  */
1931                 rate = rate/NV_SOR_HDMI_BRICK_DIV*NV_SOR_HDMI_BRICK_MUL(val);
1932                 if (clk_get_parent(sor->brick_clk) != sor->src_switch_clk)
1933                         clk_set_parent(sor->brick_clk, sor->src_switch_clk);
1934                 clk_set_rate(sor->brick_clk, rate);
1935
1936                 /*
1937                  * Select primary -- HDMI -- DVFS table for SOR clock (if SOR
1938                  * clock has single DVFS table for all modes, nothing changes).
1939                  */
1940                 tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, false);
1941
1942                 /* Select sor clock muxes */
1943                 tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1944
1945                 tegra_dc_writel(hdmi->dc, PIXEL_CLK_DIVIDER_PCD1 |
1946                         SHIFT_CLK_DIVIDER(tegra_hdmi_get_shift_clk_div(hdmi)),
1947                         DC_DISP_DISP_CLOCK_CONTROL);
1948
1949                 hdmi->clk_type = TEGRA_HDMI_BRICK_CLK;
1950         } else if (clk_type == TEGRA_HDMI_SAFE_CLK) {
1951                 if (!hdmi->dc->initialized) {
1952                         /* Select sor clock muxes */
1953                         tegra_clk_cfg_ex(hdmi->sor->sor_clk,
1954                                 TEGRA_CLK_SOR_CLK_SEL, 0);
1955                         hdmi->clk_type = TEGRA_HDMI_SAFE_CLK;
1956                 }
1957         } else {
1958                 dev_err(&hdmi->dc->ndev->dev, "hdmi: incorrect clk type configured\n");
1959         }
1960 }
1961
1962 /* returns exact pixel clock in Hz */
1963 static long tegra_hdmi_get_pclk(struct tegra_dc_mode *mode)
1964 {
1965         long h_total, v_total;
1966         long refresh, pclk;
1967         h_total = mode->h_active + mode->h_front_porch + mode->h_back_porch +
1968                 mode->h_sync_width;
1969         v_total = mode->v_active + mode->v_front_porch + mode->v_back_porch +
1970                 mode->v_sync_width;
1971         refresh = tegra_dc_calc_refresh(mode);
1972         refresh = DIV_ROUND_CLOSEST(refresh, 1000);
1973
1974         pclk = h_total * v_total * refresh;
1975
1976         if (mode->vmode & FB_VMODE_1000DIV1001)
1977                 pclk = pclk * 1000 / 1001;
1978
1979         return pclk;
1980 }
1981
1982 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
1983 {
1984 #ifdef CONFIG_TEGRA_NVDISPLAY
1985         struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
1986                                 dc->out->parent_clk ? : "plld2");
1987 #else
1988         struct clk *parent_clk = clk_get(NULL,
1989                                 dc->out->parent_clk ? : "pll_d2");
1990 #endif
1991         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1992
1993         dc->mode.pclk = tegra_hdmi_get_pclk(&dc->mode);
1994
1995         if (dc->mode.pclk == 370878125 &&
1996                 tegra_edid_get_quirks(hdmi->edid) &
1997                         TEGRA_EDID_QUIRK_370_BUMP_DOWN) {
1998                 dc->mode.pclk = 370875000;
1999         } else if (dc->mode.h_front_porch == 48 &&
2000                 dc->mode.h_active == 1920 &&
2001                 dc->mode.pclk == 138652800 &&
2002                 dc->mode.h_back_porch == 80 &&
2003                 dc->mode.v_sync_width == 5 &&
2004                 dc->mode.h_sync_width == 32 &&
2005                 dc->mode.stereo_mode == 0 &&
2006                 dc->mode.v_back_porch == 23 &&
2007                 dc->mode.v_active == 1080 &&
2008                 dc->mode.v_front_porch == 3 &&
2009                 dc->mode.vmode & FB_VMODE_IS_DETAILED) {
2010                 dc->mode.pclk = 138500000;
2011         } else if (dc->mode.h_front_porch == 111 &&
2012                 dc->mode.h_active == 1280 &&
2013                 dc->mode.pclk == 74349000 &&
2014                 dc->mode.h_back_porch == 219 &&
2015                 dc->mode.v_sync_width == 5 &&
2016                 dc->mode.h_sync_width == 40 &&
2017                 dc->mode.stereo_mode == 0 &&
2018                 dc->mode.v_back_porch == 21 &&
2019                 dc->mode.v_active == 720 &&
2020                 dc->mode.v_front_porch == 5 &&
2021                 dc->mode.vmode & FB_VMODE_IS_DETAILED) {
2022                 dc->mode.pclk = 74250000;
2023         }
2024
2025         if (IS_ERR_OR_NULL(parent_clk)) {
2026                 dev_err(&dc->ndev->dev, "hdmi: parent clk get failed\n");
2027                 return 0;
2028         }
2029
2030         if (!tegra_platform_is_silicon())
2031                 return dc->mode.pclk;
2032
2033 #ifdef CONFIG_TEGRA_NVDISPLAY
2034         if (clk_get_parent(clk) != parent_clk)
2035                 clk_set_parent(clk, parent_clk);
2036 #else
2037         if (clk == dc->clk) {
2038                 if (clk_get_parent(clk) != parent_clk) {
2039                         if (clk_set_parent(clk, parent_clk)) {
2040                                 dev_err(&dc->ndev->dev,
2041                                         "hdmi: set dc parent failed\n");
2042                                 return 0;
2043                         }
2044                 }
2045         } else {
2046                 struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2047                 struct tegra_dc_sor_data *sor = hdmi->sor;
2048
2049                 if (clk_get_parent(sor->src_switch_clk) != parent_clk) {
2050                         if (clk_set_parent(sor->src_switch_clk, parent_clk)) {
2051                                 dev_err(&dc->ndev->dev,
2052                                         "hdmi: set src switch parent failed\n");
2053                                 return 0;
2054                         }
2055                 }
2056         }
2057 #endif
2058         if (dc->initialized)
2059                 goto skip_setup;
2060         if (clk_get_rate(parent_clk) != dc->mode.pclk)
2061                 clk_set_rate(parent_clk, dc->mode.pclk);
2062 skip_setup:
2063         /*
2064          * DC clock divider is controlled by DC driver transparently to clock
2065          * framework -- hence, direct call to DVFS with target mode rate. SOR
2066          * clock rate in clock tree is properly updated, and can be used for
2067          * DVFS update.
2068          *
2069          * TODO: tegra_hdmi_controller_enable() procedure 1st configures SOR
2070          * clock via tegra_hdmi_config_clk(), and then calls this function
2071          * that may re-lock parent PLL. That needs to be double-checked:
2072          * in general re-locking PLL while the downstream module is already
2073          * sourced from it is not recommended. If/when the order of enabling
2074          * HDMI controller is changed, we can remove direct DVFS call for SOR
2075          * (but for DC it should be kept, anyway).
2076          */
2077         if (clk == dc->clk)
2078                 tegra_dvfs_set_rate(clk, dc->mode.pclk);
2079         else
2080                 tegra_dvfs_set_rate(clk, clk_get_rate(clk));
2081
2082         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2083 }
2084
2085 static void tegra_dc_hdmi_shutdown(struct tegra_dc *dc)
2086 {
2087         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2088
2089         hdmi->device_shutdown = true;
2090         tegra_nvhdcp_shutdown(hdmi->nvhdcp);
2091
2092         return;
2093 }
2094
2095 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2096 {
2097         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2098
2099         hdmi->enabled = false;
2100 #ifdef CONFIG_SWITCH
2101         switch_set_state(&hdmi->audio_switch, 0);
2102 #endif
2103
2104         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
2105         tegra_hdmi_controller_disable(hdmi);
2106         tegra_hda_reset_data();
2107         return;
2108 }
2109
2110 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
2111 {
2112         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2113         unsigned long delay = msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS);
2114
2115         if (tegra_platform_is_linsim())
2116                 return true;
2117
2118         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL)
2119                 delay = 0;
2120
2121         cancel_delayed_work(&hdmi->hpd_worker);
2122         schedule_delayed_work(&hdmi->hpd_worker, delay);
2123
2124         return tegra_dc_hpd(dc);
2125 }
2126
2127 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
2128 {
2129         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2130
2131         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
2132                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
2133                 int ret;
2134
2135                 ret = enable_irq_wake(wake_irq);
2136                 if (ret < 0) {
2137                         dev_err(&dc->ndev->dev,
2138                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
2139                         __func__, wake_irq, ret);
2140                 }
2141         }
2142
2143         atomic_set(&hdmi->suspended, 1);
2144 }
2145
2146 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
2147 {
2148         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2149
2150         atomic_set(&hdmi->suspended, 0);
2151
2152         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
2153                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
2154
2155         cancel_delayed_work(&hdmi->hpd_worker);
2156         schedule_delayed_work(&hdmi->hpd_worker,
2157                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS + HDMI_HPD_DROP_TIMEOUT_MS));
2158 }
2159
2160 static int tegra_dc_hdmi_set_hdr(struct tegra_dc *dc)
2161 {
2162         u16 ret = 0;
2163         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2164         ret = tegra_edid_get_ex_hdr_cap(hdmi->edid);
2165         if (ret & FB_CAP_HDR)
2166                 tegra_hdmi_hdr_infoframe(hdmi);
2167         return 0;
2168 }
2169
2170 static int tegra_dc_hdmi_ddc_enable(struct tegra_dc *dc)
2171 {
2172         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2173         _tegra_hdmi_ddc_enable(hdmi);
2174         return 0;
2175 }
2176
2177 static int tegra_dc_hdmi_ddc_disable(struct tegra_dc *dc)
2178 {
2179         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2180         _tegra_hdmi_ddc_disable(hdmi);
2181         return 0;
2182 }
2183
2184 static void tegra_dc_hdmi_modeset_notifier(struct tegra_dc *dc)
2185 {
2186         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2187
2188         tegra_hdmi_get(dc);
2189         tegra_dc_io_start(dc);
2190
2191         /* disable hdmi2.x config on host and monitor */
2192         if (dc->mode.pclk > 340000000) {
2193                 if (tegra_edid_is_scdc_present(dc->edid))
2194                         tegra_hdmi_v2_x_mon_config(hdmi, true);
2195                 tegra_hdmi_v2_x_host_config(hdmi, true);
2196         } else {
2197                 if (tegra_edid_is_scdc_present(dc->edid))
2198                         tegra_hdmi_v2_x_mon_config(hdmi, false);
2199                 tegra_hdmi_v2_x_host_config(hdmi, false);
2200         }
2201
2202         tegra_dc_io_end(dc);
2203         tegra_hdmi_put(dc);
2204 }
2205
2206 #ifdef CONFIG_DEBUG_FS
2207 /* show current hpd state */
2208 static int tegra_hdmi_hotplug_dbg_show(struct seq_file *m, void *unused)
2209 {
2210         struct tegra_hdmi *hdmi = m->private;
2211         struct tegra_dc *dc = hdmi->dc;
2212
2213         if (WARN_ON(!hdmi || !dc || !dc->out))
2214                 return -EINVAL;
2215
2216         rmb();
2217         seq_printf(m, "hdmi hpd state: %d\n", dc->out->hotplug_state);
2218
2219         return 0;
2220 }
2221
2222 int tegra_hdmi_get_hotplug_state(struct tegra_hdmi *hdmi)
2223 {
2224         rmb();
2225         return hdmi->dc->out->hotplug_state;
2226 }
2227
2228 void tegra_hdmi_set_hotplug_state(struct tegra_hdmi *hdmi, int new_hpd_state)
2229 {
2230         struct tegra_dc *dc = hdmi->dc;
2231         int hotplug_state;
2232
2233         rmb();
2234         hotplug_state = dc->out->hotplug_state;
2235
2236         if (hotplug_state == TEGRA_HPD_STATE_NORMAL &&
2237                         new_hpd_state != TEGRA_HPD_STATE_NORMAL &&
2238                         tegra_dc_hotplug_supported(dc)) {
2239                 disable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2240         } else if (hotplug_state != TEGRA_HPD_STATE_NORMAL &&
2241                         new_hpd_state == TEGRA_HPD_STATE_NORMAL &&
2242                         tegra_dc_hotplug_supported(dc)) {
2243                 enable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2244         }
2245
2246         dc->out->hotplug_state = new_hpd_state;
2247         wmb();
2248
2249         /*
2250          * sw controlled plug/unplug.
2251          * wait for any already executing hpd worker thread.
2252          * No debounce delay, schedule immedately
2253          */
2254         cancel_delayed_work_sync(&hdmi->hpd_worker);
2255         schedule_delayed_work(&hdmi->hpd_worker, 0);
2256 }
2257
2258 /*
2259  * sw control for hpd.
2260  * 0 is normal state, hw drives hpd.
2261  * -1 is force deassert, sw drives hpd.
2262  * 1 is force assert, sw drives hpd.
2263  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
2264  */
2265 static ssize_t tegra_hdmi_hotplug_dbg_write(struct file *file,
2266                                         const char __user *addr,
2267                                         size_t len, loff_t *pos)
2268 {
2269         struct seq_file *m = file->private_data;
2270         struct tegra_hdmi *hdmi = m->private;
2271         struct tegra_dc *dc = hdmi->dc;
2272         long new_hpd_state;
2273         int ret;
2274
2275         if (WARN_ON(!hdmi || !dc || !dc->out))
2276                 return -EINVAL;
2277
2278         ret = kstrtol_from_user(addr, len, 10, &new_hpd_state);
2279         if (ret < 0)
2280                 return ret;
2281
2282         tegra_hdmi_set_hotplug_state(hdmi, new_hpd_state);
2283
2284         return len;
2285 }
2286
2287 static int tegra_hdmi_hotplug_dbg_open(struct inode *inode, struct file *file)
2288 {
2289         return single_open(file, tegra_hdmi_hotplug_dbg_show, inode->i_private);
2290 }
2291
2292 static const struct file_operations tegra_hdmi_hotplug_dbg_ops = {
2293         .open = tegra_hdmi_hotplug_dbg_open,
2294         .read = seq_read,
2295         .write = tegra_hdmi_hotplug_dbg_write,
2296         .llseek = seq_lseek,
2297         .release = single_release,
2298 };
2299
2300 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2301 {
2302         struct dentry *dir, *ret;
2303
2304         dir = debugfs_create_dir("tegra_hdmi",  NULL);
2305         if (IS_ERR_OR_NULL(dir))
2306                 return;
2307
2308         ret = debugfs_create_file("hotplug", S_IRUGO, dir,
2309                                 hdmi, &tegra_hdmi_hotplug_dbg_ops);
2310         if (IS_ERR_OR_NULL(ret))
2311                 goto fail;
2312
2313         return;
2314 fail:
2315         debugfs_remove_recursive(dir);
2316         return;
2317 }
2318 #else
2319 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2320 {
2321         return;
2322 }
2323 #endif
2324
2325 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
2326                 struct kobj_attribute *attr, const char *buf, size_t count)
2327 {
2328         int value;
2329         sscanf(buf, "%du", &value);
2330         tegra_hdmi_ddc_power_toggle(value);
2331         return count;
2332 }
2333
2334 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
2335                 struct kobj_attribute *attr, char *buf)
2336 {
2337         return sprintf(buf, "%d\n", dc_hdmi->ddc_refcount);
2338 }
2339
2340 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2341 {
2342         int sense;
2343         int level;
2344         bool hpd;
2345
2346         if (WARN_ON(!dc || !dc->out))
2347                 return false;
2348
2349         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2350
2351         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2352
2353         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2354                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2355
2356         return hpd;
2357 }
2358
2359 static void tegra_dc_hdmi_vrr_enable(struct tegra_dc *dc, bool enable)
2360 {
2361         struct tegra_vrr *vrr  = dc->out->vrr;
2362
2363         if (vrr)
2364                 vrr->enable = enable;
2365 }
2366
2367 struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
2368         .init = tegra_dc_hdmi_init,
2369         .destroy = tegra_dc_hdmi_destroy,
2370         .enable = tegra_dc_hdmi_enable,
2371         .disable = tegra_dc_hdmi_disable,
2372         .setup_clk = tegra_dc_hdmi_setup_clk,
2373         .detect = tegra_dc_hdmi_detect,
2374         .shutdown = tegra_dc_hdmi_shutdown,
2375         .suspend = tegra_dc_hdmi_suspend,
2376         .resume = tegra_dc_hdmi_resume,
2377         .ddc_enable = tegra_dc_hdmi_ddc_enable,
2378         .ddc_disable = tegra_dc_hdmi_ddc_disable,
2379         .modeset_notifier = tegra_dc_hdmi_modeset_notifier,
2380         .mode_filter = tegra_hdmi_fb_mode_filter,
2381         .hpd_state = tegra_dc_hdmi_hpd_state,
2382         .vrr_enable = tegra_dc_hdmi_vrr_enable,
2383         .vrr_mode = tegra_hdmi_update_vrr_mode,
2384         .set_hdr = tegra_dc_hdmi_set_hdr,
2385 };