video: tegra: dc: set sor to sleep at vsync during dc shutdown
[linux-3.10.git] / drivers / video / tegra / dc / hdmi2.0.c
1 /*
2  * drivers/video/tegra/dc/hdmi2.0.c
3  *
4  * Copyright (c) 2014-2017, NVIDIA CORPORATION, All rights reserved.
5  * Author: Animesh Kishore <ankishore@nvidia.com>
6  *
7  * This software is licensed under the terms of the GNU General Public
8  * License version 2, as published by the Free Software Foundation, and
9  * may be copied, distributed, and modified under those terms.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/mutex.h>
23 #include <linux/device.h>
24 #include <linux/clk/tegra.h>
25 #include <linux/nvhost.h>
26 #include <linux/gpio.h>
27 #include <linux/interrupt.h>
28 #include <linux/debugfs.h>
29 #include <linux/unistd.h>
30 #ifdef CONFIG_SWITCH
31 #include <linux/switch.h>
32 #endif
33 #include <linux/of_address.h>
34 #include <linux/tegra_pm_domains.h>
35
36 #include <mach/dc.h>
37 #include <mach/fb.h>
38 #include <mach/powergate.h>
39
40 #include "dc_reg.h"
41 #include "dc_priv.h"
42 #include "sor.h"
43 #include "sor_regs.h"
44 #include "edid.h"
45 #include "hdmi2.0.h"
46 #include "hdmihdcp.h"
47 #include "dpaux.h"
48 #ifdef CONFIG_ADF_TEGRA
49 #include "tegra_adf.h"
50 #endif
51 #include "hda_dc.h"
52 #include "hdmivrr.h"
53
54 #include <linux/tegra_prod.h>
55 #include "../../../../arch/arm/mach-tegra/iomap.h"
56
57 #define TMDS_NODE       "/host1x/sor1"
58
59 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
60 static struct of_device_id tegra_sor_pd[] = {
61         { .compatible = "nvidia, tegra210-sor-pd", },
62         { .compatible = "nvidia, tegra132-sor-pd", },
63         { .compatible = "nvidia, tegra124-sor-pd", },
64         {},
65 };
66 #endif
67
68 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
69         struct kobj_attribute *attr, const char *buf, size_t count);
70
71 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
72         struct kobj_attribute *attr, char *buf);
73
74 static struct kobj_attribute hdmi_ddc_power_config =
75         __ATTR(config, 0640, hdmi_ddc_power_show, hdmi_ddc_power_toggle);
76
77 static struct kobject *hdmi_ddc;
78
79 struct tmds_prod_pair {
80         int clk;
81         const char *name;
82 };
83
84 static struct tmds_prod_pair tmds_config_modes[] = {
85         { /* 54 MHz */
86         .clk = 54000000,
87         .name = "prod_c_54M"
88         },
89         { /* 75 MHz */
90         .clk = 75000000,
91         .name = "prod_c_75M"
92         },
93         { /* 150 MHz */
94         .clk = 150000000,
95         .name = "prod_c_150M"
96         },
97         { /* 300 MHz */
98         .clk = 300000000,
99         .name = "prod_c_300M"
100         },
101         { /* HDMI 2.0 */
102         .clk = 600000000,
103         .name = "prod_c_600M"
104         }
105 };
106
107 static struct tegra_hdmi *dc_hdmi;
108
109 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi);
110 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type);
111 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk);
112 static void tegra_hdmi_scdc_worker(struct work_struct *work);
113 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi);
114 static void tegra_hdmi_hdr_worker(struct work_struct *work);
115 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable);
116 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable);
117
118 static inline bool tegra_hdmi_is_connected(struct tegra_hdmi *hdmi)
119 {
120         return (hdmi->mon_spec.misc & FB_MISC_HDMI) ||
121                 (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM);
122 }
123
124 static inline void tegra_hdmi_irq_enable(struct tegra_hdmi *hdmi)
125 {
126         if (tegra_platform_is_fpga())
127                 return;
128
129         enable_irq(hdmi->irq);
130 }
131
132 static inline void tegra_hdmi_irq_disable(struct tegra_hdmi *hdmi)
133 {
134         if (tegra_platform_is_fpga())
135                 return;
136
137         disable_irq(hdmi->irq);
138 }
139
140 static inline bool tegra_hdmi_hpd_asserted(struct tegra_hdmi *hdmi)
141 {
142         return tegra_dc_hpd(hdmi->dc);
143 }
144
145 static inline void tegra_hdmi_reset(struct tegra_hdmi *hdmi)
146 {
147         if (tegra_platform_is_linsim())
148                 return;
149
150         tegra_periph_reset_assert(hdmi->sor->sor_clk);
151         udelay(10);
152         tegra_periph_reset_deassert(hdmi->sor->sor_clk);
153         udelay(10);
154 }
155
156 static inline void _tegra_hdmi_ddc_enable(struct tegra_hdmi *hdmi)
157 {
158         mutex_lock(&hdmi->ddc_refcount_lock);
159         if (hdmi->ddc_refcount++)
160                 goto fail;
161         tegra_hdmi_get(hdmi->dc);
162         /*
163          * hdmi uses i2c lane muxed on dpaux1 pad.
164          * Enable dpaux1 pads and configure the mux.
165          */
166         tegra_dpaux_config_pad_mode(hdmi->dc, TEGRA_DPAUX_INSTANCE_1,
167                                         TEGRA_DPAUX_PAD_MODE_I2C);
168
169 fail:
170         mutex_unlock(&hdmi->ddc_refcount_lock);
171 }
172
173 static inline void _tegra_hdmi_ddc_disable(struct tegra_hdmi *hdmi)
174 {
175         mutex_lock(&hdmi->ddc_refcount_lock);
176
177         if (WARN_ONCE(hdmi->ddc_refcount <= 0, "ddc refcount imbalance"))
178                 goto fail;
179         if (--hdmi->ddc_refcount != 0)
180                 goto fail;
181
182         /*
183          * hdmi uses i2c lane muxed on dpaux1 pad.
184          * Disable dpaux1 pads.
185          */
186         tegra_dpaux_pad_power(hdmi->dc, TEGRA_DPAUX_INSTANCE_1, false);
187         tegra_hdmi_put(hdmi->dc);
188
189 fail:
190         mutex_unlock(&hdmi->ddc_refcount_lock);
191 }
192
193 static int tegra_hdmi_ddc_i2c_xfer(struct tegra_dc *dc,
194                                         struct i2c_msg *msgs, int num)
195 {
196         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
197         int ret;
198
199         _tegra_hdmi_ddc_enable(hdmi);
200         ret = i2c_transfer(hdmi->ddc_i2c_client->adapter, msgs, num);
201         _tegra_hdmi_ddc_disable(hdmi);
202         return ret;
203 }
204
205 static int tegra_hdmi_ddc_init(struct tegra_hdmi *hdmi, int edid_src)
206 {
207         struct tegra_dc *dc = hdmi->dc;
208         struct i2c_adapter *i2c_adap;
209         int err = 0;
210         struct i2c_board_info i2c_dev_info = {
211                 .type = "tegra_hdmi2.0",
212                 .addr = 0x50,
213         };
214         if (edid_src == 0)
215                 hdmi->edid = tegra_edid_create(dc, tegra_hdmi_ddc_i2c_xfer);
216         else if (edid_src == 1)
217                 hdmi->edid = tegra_edid_create(dc, tegra_dc_edid_blob);
218         if (IS_ERR_OR_NULL(hdmi->edid)) {
219                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
220                 return PTR_ERR(hdmi->edid);
221         }
222         tegra_dc_set_edid(dc, hdmi->edid);
223
224         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
225         if (!i2c_adap) {
226                 dev_err(&dc->ndev->dev,
227                         "hdmi: can't get adpater for ddc bus %d\n",
228                         dc->out->ddc_bus);
229                 err = -EBUSY;
230                 goto fail_edid_free;
231         }
232         hdmi->ddc_i2c_original_rate = i2c_get_adapter_bus_clk_rate(i2c_adap);
233
234         hdmi->ddc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
235         i2c_put_adapter(i2c_adap);
236         if (!hdmi->ddc_i2c_client) {
237                 dev_err(&dc->ndev->dev, "hdmi: can't create new i2c device\n");
238                 err = -EBUSY;
239                 goto fail_edid_free;
240         }
241
242         return 0;
243 fail_edid_free:
244         tegra_edid_destroy(hdmi->edid);
245         return err;
246 }
247
248 static int tegra_hdmi_scdc_i2c_xfer(struct tegra_dc *dc,
249                                         struct i2c_msg *msgs, int num)
250 {
251         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
252
253         return i2c_transfer(hdmi->scdc_i2c_client->adapter, msgs, num);
254 }
255
256 static int tegra_hdmi_scdc_init(struct tegra_hdmi *hdmi)
257 {
258         struct tegra_dc *dc = hdmi->dc;
259         struct i2c_adapter *i2c_adap;
260         int err = 0;
261         struct i2c_board_info i2c_dev_info = {
262                 .type = "tegra_hdmi_scdc",
263                 .addr = 0x54,
264         };
265
266         i2c_adap = i2c_get_adapter(dc->out->ddc_bus);
267         if (!i2c_adap) {
268                 dev_err(&dc->ndev->dev,
269                         "hdmi: can't get adpater for scdc bus %d\n",
270                         dc->out->ddc_bus);
271                 err = -EBUSY;
272                 goto fail;
273         }
274
275         hdmi->scdc_i2c_client = i2c_new_device(i2c_adap, &i2c_dev_info);
276         i2c_put_adapter(i2c_adap);
277         if (!hdmi->scdc_i2c_client) {
278                 dev_err(&dc->ndev->dev,
279                         "hdmi: can't create scdc i2c device\n");
280                 err = -EBUSY;
281                 goto fail;
282         }
283
284         INIT_DELAYED_WORK(&hdmi->scdc_work, tegra_hdmi_scdc_worker);
285
286         return 0;
287 fail:
288         return err;
289 }
290
291 /*  does not return precise tmds character rate */
292 static u32 tegra_hdmi_mode_min_tmds_rate(const struct fb_videomode *mode)
293 {
294         u32 tmds_csc_8bpc_khz = PICOS2KHZ(mode->pixclock);
295
296         if (mode->vmode & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
297                 tmds_csc_8bpc_khz /= 2;
298
299         return tmds_csc_8bpc_khz;
300 }
301
302 __maybe_unused
303 static bool tegra_hdmi_fb_mode_filter(const struct tegra_dc *dc,
304                                         struct fb_videomode *mode)
305 {
306         struct tegra_hdmi *hdmi = dc->out_data;
307
308         if (!mode->pixclock)
309                 return false;
310
311         if (mode->xres > 4096)
312                 return false;
313
314 #if defined(CONFIG_TEGRA_YUV_BYPASS_MODE_FILTER)
315 #if !defined(CONFIG_TEGRA_NVDISPLAY)
316         /* No support for YUV modes on T210 hardware. Filter them out */
317         if (mode->vmode & FB_VMODE_YUV_MASK)
318                 return false;
319 #else
320         /* T186 hardware supports only YUV422. Filter out YUV420 modes */
321         if ((mode->vmode & FB_VMODE_Y420_ONLY) ||
322                 (mode->vmode & FB_VMODE_Y420))
323                 return false;
324 #endif
325 #endif
326
327         /* some non-compliant edids list 420vdb modes in vdb */
328         if ((mode->vmode & FB_VMODE_Y420) &&
329                 !(tegra_edid_is_hfvsdb_present(hdmi->edid) &&
330                 tegra_edid_is_scdc_present(hdmi->edid)) &&
331                 tegra_edid_is_420db_present(hdmi->edid)) {
332                 mode->vmode &= ~FB_VMODE_Y420;
333                 mode->vmode |= FB_VMODE_Y420_ONLY;
334         }
335
336         if (mode->vmode & FB_VMODE_YUV_MASK &&
337                 tegra_edid_get_quirks(hdmi->edid) & TEGRA_EDID_QUIRK_NO_YUV)
338                 return false;
339
340         /*
341          * There are currently many TVs in the market that actually do NOT support
342          * 4k@60fps 4:4:4 (594 MHz), (especially on the HDCP 2.2 ports), but
343          * advertise it in the DTD block in their EDIDs. The workaround for this port
344          * is to disable the 594 MHz mode if no HF-VSDB is present or if no SCDC
345          * support is indicated
346          */
347         if (tegra_hdmi_mode_min_tmds_rate(mode) / 1000 >= 340 &&
348                 (!tegra_edid_is_hfvsdb_present(hdmi->edid) ||
349                 !tegra_edid_is_scdc_present(hdmi->edid)))
350                 return false;
351
352         /*
353          * Check if mode's pixel clock requirement can be satisfied. Note that
354          * the pixclock value is in pico seconds.
355          */
356         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
357                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
358                 return false;
359
360         /*
361          * Work around for modes that fail the constraint:
362          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
363          */
364         if (mode->lower_margin == 1) {
365                 mode->lower_margin++;
366                 mode->upper_margin--;
367                 mode->vmode |= FB_VMODE_ADJUSTED;
368         }
369
370         if (!check_fb_videomode_timings(dc, mode)) {
371                 trace_printk("check_fb_videomode_timings: false\n"
372                              "%u x %u @ %u Hz\n",
373                              mode->xres, mode->yres, mode->pixclock);
374                 return false;
375         }
376
377         return true;
378 }
379
380 static void tegra_hdmi_ddc_power_toggle(int value)
381 {
382         int partition_id;
383         if (dc_hdmi == NULL)
384                 return;
385
386 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
387         partition_id = tegra_pd_get_powergate_id(tegra_sor_pd);
388         if (partition_id < 0)
389                 return;
390 #else
391         partition_id = TEGRA_POWERGATE_SOR;
392 #endif
393
394         if (value == 0) {
395                 _tegra_hdmi_ddc_disable(dc_hdmi);
396                 tegra_powergate_partition(partition_id);
397         } else if (value == 1) {
398                 tegra_unpowergate_partition(partition_id);
399                 _tegra_hdmi_ddc_enable(dc_hdmi);
400         }
401
402         return;
403 }
404
405 static int tegra_hdmi_get_mon_spec(struct tegra_hdmi *hdmi)
406 {
407 #define MAX_RETRY 100
408 #define MIN_RETRY_DELAY_US 200
409 #define MAX_RETRY_DELAY_US (MIN_RETRY_DELAY_US + 200)
410
411         size_t attempt_cnt = 0;
412         int err = 0;
413         struct i2c_adapter *i2c_adap = i2c_get_adapter(hdmi->dc->out->ddc_bus);
414
415         if (IS_ERR_OR_NULL(hdmi->edid)) {
416                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid not initialized\n");
417                 return PTR_ERR(hdmi->edid);
418         }
419
420         tegra_edid_i2c_adap_change_rate(i2c_adap, hdmi->ddc_i2c_original_rate);
421
422         hdmi->mon_spec_valid = false;
423         if (hdmi->mon_spec_valid)
424                 fb_destroy_modedb(hdmi->mon_spec.modedb);
425         memset(&hdmi->mon_spec, 0, sizeof(hdmi->mon_spec));
426
427         do {
428                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
429                 if (err < 0)
430                         usleep_range(MIN_RETRY_DELAY_US, MAX_RETRY_DELAY_US);
431                 else
432                         break;
433         } while (++attempt_cnt < MAX_RETRY);
434
435         if (err < 0) {
436                 dev_err(&hdmi->dc->ndev->dev, "hdmi: edid read failed\n");
437                 /* Try to load and parse the fallback edid */
438                 hdmi->edid->errors = EDID_ERRORS_READ_FAILED;
439                 err = tegra_edid_get_monspecs(hdmi->edid, &hdmi->mon_spec);
440                 if (err < 0) {
441                         dev_err(&hdmi->dc->ndev->dev,
442                                 "hdmi: parsing fallback edid failed\n");
443                         return err;
444                 } else {
445                         dev_err(&hdmi->dc->ndev->dev,
446                                 "hdmi: using fallback edid\n");
447                 }
448         }
449
450         hdmi->mon_spec_valid = true;
451         return 0;
452
453 #undef MAX_RETRY_DELAY_US
454 #undef MIN_RETRY_DELAY_US
455 #undef MAX_RETRY
456 }
457
458 static inline int tegra_hdmi_edid_read(struct tegra_hdmi *hdmi)
459 {
460         int err;
461
462         err = tegra_hdmi_get_mon_spec(hdmi);
463
464         return err;
465 }
466
467 static int tegra_hdmi_get_eld(struct tegra_hdmi *hdmi)
468 {
469         int err;
470
471         hdmi->eld_valid = false;
472         memset(&hdmi->eld, 0, sizeof(hdmi->eld));
473
474         err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
475         if (err < 0) {
476                 dev_err(&hdmi->dc->ndev->dev, "hdmi: eld not available\n");
477                 return err;
478         }
479
480         hdmi->eld_valid = true;
481         return 0;
482 }
483
484 static inline int tegra_hdmi_eld_read(struct tegra_hdmi *hdmi)
485 {
486         return tegra_hdmi_get_eld(hdmi);
487 }
488
489 static void tegra_hdmi_edid_config(struct tegra_hdmi *hdmi)
490 {
491 #define CM_TO_MM(x) (x * 10)
492
493         struct tegra_dc *dc = hdmi->dc;
494
495         if (!hdmi->mon_spec_valid)
496                 return;
497
498         dc->out->h_size = CM_TO_MM(hdmi->mon_spec.max_x);
499         dc->out->v_size = CM_TO_MM(hdmi->mon_spec.max_y);
500
501         hdmi->dvi = !tegra_hdmi_is_connected(hdmi);
502 #undef CM_TO_MM
503 }
504
505 static void tegra_hdmi_hotplug_notify(struct tegra_hdmi *hdmi,
506                                         bool is_asserted)
507 {
508         struct tegra_dc *dc = hdmi->dc;
509         struct fb_monspecs *mon_spec;
510
511         if (is_asserted)
512                 mon_spec = &hdmi->mon_spec;
513         else
514                 mon_spec = NULL;
515
516 #ifdef CONFIG_ADF_TEGRA
517         if (dc->adf)
518                 tegra_adf_process_hotplug_connected(hdmi->dc->adf, mon_spec);
519 #else
520         if (dc->fb) {
521                 tegra_fb_update_monspecs(hdmi->dc->fb, mon_spec,
522                                         tegra_hdmi_fb_mode_filter);
523                 tegra_fb_update_fix(hdmi->dc->fb, mon_spec);
524         }
525 #endif
526
527         dc->connected = is_asserted;
528         tegra_dc_ext_process_hotplug(dc->ndev->id, is_asserted);
529
530 #ifdef CONFIG_SWITCH
531         switch_set_state(&hdmi->hpd_switch, is_asserted ? 1 : 0);
532 #endif
533 }
534
535 static int tegra_hdmi_edid_eld_setup(struct tegra_hdmi *hdmi)
536 {
537         int err;
538
539         tegra_dc_unpowergate_locked(hdmi->dc);
540
541         err = tegra_hdmi_edid_read(hdmi);
542         if (err < 0)
543                 goto fail;
544
545         err = tegra_hdmi_eld_read(hdmi);
546         if (err < 0)
547                 goto fail;
548
549         err = tegra_hdmivrr_setup(hdmi);
550         if (err < 0)
551                 dev_info(&hdmi->dc->ndev->dev, "vrr_setup failed\n");
552
553         tegra_dc_powergate_locked(hdmi->dc);
554
555         tegra_hdmi_edid_config(hdmi);
556
557         /*
558          * eld is configured when audio needs it
559          * via tegra_hdmi_edid_config()
560          */
561
562         tegra_hdmi_hotplug_notify(hdmi, true);
563         return 0;
564 fail:
565         tegra_dc_powergate_locked(hdmi->dc);
566         return err;
567 }
568
569 static int tegra_hdmi_controller_disable(struct tegra_hdmi *hdmi)
570 {
571         struct tegra_dc_sor_data *sor = hdmi->sor;
572         struct tegra_dc *dc = hdmi->dc;
573
574         tegra_dc_get(dc);
575
576         cancel_delayed_work_sync(&hdmi->scdc_work);
577         if (dc->mode.pclk > 340000000) {
578                 tegra_hdmi_v2_x_mon_config(hdmi, false);
579                 tegra_hdmi_v2_x_host_config(hdmi, false);
580         }
581
582         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
583         tegra_dc_sor_detach(sor);
584         tegra_sor_power_lanes(sor, 4, false);
585         tegra_sor_hdmi_pad_power_down(sor);
586         tegra_hdmi_reset(hdmi);
587         tegra_hdmi_put(dc);
588         cancel_delayed_work_sync(&hdmi->hdr_worker);
589         tegra_dc_put(dc);
590
591         return 0;
592 }
593
594 static int tegra_hdmi_disable(struct tegra_hdmi *hdmi)
595 {
596         struct tegra_dc *dc = hdmi->dc;
597
598         if (!hdmi->enabled) {
599                 dc->connected = false;
600                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
601 #ifdef CONFIG_SWITCH
602                 switch_set_state(&hdmi->hpd_switch, 0);
603 #endif
604                 return 0;
605         }
606
607         hdmi->enabled = false;
608         hdmi->eld_valid = false;
609         hdmi->mon_spec_valid = false;
610
611         tegra_dc_disable(hdmi->dc);
612
613         tegra_hdmi_hotplug_notify(hdmi, false);
614
615         return 0;
616 }
617
618 static int (*tegra_hdmi_state_func[])(struct tegra_hdmi *) = {
619         tegra_hdmi_disable,
620         tegra_hdmi_edid_eld_setup,
621 };
622
623 enum tegra_hdmi_plug_states {
624         TEGRA_HDMI_MONITOR_DISABLE,
625         TEGRA_HDMI_MONITOR_ENABLE,
626 };
627
628 static int read_edid_into_buffer(struct tegra_hdmi *hdmi,
629                                  u8 *edid_data, size_t edid_data_len)
630 {
631         int err, i;
632         int extension_blocks;
633         int max_ext_blocks = (edid_data_len / 128) - 1;
634
635         err = tegra_edid_read_block(hdmi->edid, 0, edid_data);
636         if (err) {
637                 dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(0) returned err %d\n",
638                         err);
639                 return err;
640         }
641         extension_blocks = edid_data[0x7e];
642         dev_info(&hdmi->dc->ndev->dev, "%s: extension_blocks = %d, max_ext_blocks = %d\n",
643                 __func__, extension_blocks, max_ext_blocks);
644         if (extension_blocks > max_ext_blocks)
645                 extension_blocks = max_ext_blocks;
646         for (i = 1; i <= extension_blocks; i++) {
647                 err = tegra_edid_read_block(hdmi->edid, i, edid_data + i * 128);
648                 if (err) {
649                         dev_info(&hdmi->dc->ndev->dev, "hdmi: tegra_edid_read_block(%d) returned err %d\n",
650                                 i, err);
651                         return err;
652                 }
653         }
654         return i * 128;
655 }
656
657 static int hdmi_recheck_edid(struct tegra_hdmi *hdmi, int *match)
658 {
659         int ret;
660         u8 tmp[HDMI_EDID_MAX_LENGTH] = {0};
661         ret = read_edid_into_buffer(hdmi, tmp, sizeof(tmp));
662         dev_info(&hdmi->dc->ndev->dev, "%s: read_edid_into_buffer() returned %d\n",
663                 __func__, ret);
664         if (ret > 0) {
665                 struct tegra_dc_edid *data = tegra_edid_get_data(hdmi->edid);
666                 dev_info(&hdmi->dc->ndev->dev, "old edid len = %ld\n",
667                         (long int)data->len);
668                 *match = ((ret == data->len) &&
669                           !memcmp(tmp, data->buf, data->len));
670                 if (*match == 0) {
671                         print_hex_dump(KERN_INFO, "tmp :", DUMP_PREFIX_ADDRESS,
672                                        16, 4, tmp, ret, true);
673                         print_hex_dump(KERN_INFO, "data:", DUMP_PREFIX_ADDRESS,
674                                        16, 4, data->buf, data->len, true);
675                 }
676                 tegra_edid_put_data(data);
677                 ret = 0;
678         }
679
680         return ret;
681 }
682 static void tegra_hdmi_hpd_worker(struct work_struct *work)
683 {
684         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
685                                 struct tegra_hdmi, hpd_worker);
686         int err;
687         bool connected;
688         enum tegra_hdmi_plug_states orig_state;
689         int match = 0;
690
691         mutex_lock(&hdmi->hpd_lock);
692
693         connected = tegra_dc_hpd(hdmi->dc);
694         orig_state = hdmi->plug_state;
695
696         if (connected) {
697                 switch (orig_state) {
698                 case TEGRA_HDMI_MONITOR_ENABLE:
699                         if (hdmi_recheck_edid(hdmi, &match)) {
700                                 dev_info(&hdmi->dc->ndev->dev, "hdmi: unable to read EDID\n");
701                                 goto fail;
702                         } else {
703                                 if (match) {
704                                         dev_info(&hdmi->dc->ndev->dev, "hdmi: No EDID change after HPD bounce, taking no action.\n");
705                                         goto fail;
706                                 } else {
707                                         dev_info(&hdmi->dc->ndev->dev, "hdmi: EDID change after HPD bounce, resetting\n");
708                                         if (hdmi->dc->out->hotplug_state !=
709                                                 TEGRA_HPD_STATE_FORCE_ASSERT)
710                                                 hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
711                                 }
712                         }
713                         break;
714                 case TEGRA_HDMI_MONITOR_DISABLE:
715                         hdmi->plug_state = TEGRA_HDMI_MONITOR_ENABLE;
716                         break;
717                 default:
718                         break;
719                 };
720         } else {
721                 switch (orig_state) {
722                 case TEGRA_HDMI_MONITOR_ENABLE:
723                         hdmi->plug_state = TEGRA_HDMI_MONITOR_DISABLE;
724                         break;
725                 case TEGRA_HDMI_MONITOR_DISABLE:
726                         goto fail;
727                 default:
728                         break;
729                 };
730         }
731
732         err = tegra_hdmi_state_func[hdmi->plug_state](hdmi);
733
734         if (err < 0) {
735                         dev_info(&hdmi->dc->ndev->dev,
736                                 "hdmi state %d failed during %splug\n",
737                                 hdmi->plug_state, connected ? "" : "un");
738                         hdmi->plug_state = orig_state;
739                         goto fail;
740                 } else {
741                         dev_info(&hdmi->dc->ndev->dev, "hdmi: %splugged\n",
742                                         connected ? "" : "un");
743                 }
744
745         if (connected && hdmi->plug_state == TEGRA_HDMI_MONITOR_DISABLE)
746                 goto reschedule_worker;
747
748 fail:
749         mutex_unlock(&hdmi->hpd_lock);
750         return;
751
752 reschedule_worker:
753         mutex_unlock(&hdmi->hpd_lock);
754         cancel_delayed_work(&hdmi->hpd_worker);
755         schedule_delayed_work(&hdmi->hpd_worker, 0);
756         return;
757
758 }
759
760 static irqreturn_t tegra_hdmi_hpd_irq_handler(int irq, void *ptr)
761 {
762         struct tegra_dc *dc = ptr;
763         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
764
765         if (atomic_read(&hdmi->suspended))
766                 return IRQ_HANDLED;
767
768         cancel_delayed_work(&hdmi->hpd_worker);
769         schedule_delayed_work(&hdmi->hpd_worker,
770                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS));
771
772         return IRQ_HANDLED;
773 }
774
775 static int tegra_hdmi_hpd_init(struct tegra_hdmi *hdmi)
776 {
777         struct tegra_dc *dc = hdmi->dc;
778         int hotplug_gpio = dc->out->hotplug_gpio;
779         int hotplug_irq;
780         int err;
781
782         if (!gpio_is_valid(hotplug_gpio)) {
783                 dev_err(&dc->ndev->dev, "hdmi: invalid hotplug gpio\n");
784                 return -EINVAL;
785         }
786
787         hotplug_irq = gpio_to_irq(hotplug_gpio);
788         if (hotplug_irq < 0) {
789                 dev_err(&dc->ndev->dev,
790                         "hdmi: hotplug gpio to irq map failed\n");
791                 return -EINVAL;
792         }
793
794         err = gpio_request(hotplug_gpio, "hdmi2.0_hpd");
795         if (err < 0)
796                 dev_err(&dc->ndev->dev,
797                         "hdmi: hpd gpio_request failed %d\n", err);
798         gpio_direction_input(hotplug_gpio);
799
800         err = request_threaded_irq(hotplug_irq,
801                                 NULL, tegra_hdmi_hpd_irq_handler,
802                                 (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING |
803                                 IRQF_ONESHOT),
804                                 dev_name(&dc->ndev->dev), dc);
805         if (err) {
806                 dev_err(&dc->ndev->dev,
807                         "hdmi: request_threaded_irq failed: %d\n", err);
808                 goto fail;
809         }
810
811
812         INIT_DELAYED_WORK(&hdmi->hpd_worker, tegra_hdmi_hpd_worker);
813
814         mutex_init(&hdmi->hpd_lock);
815         hdmi->irq = hotplug_irq;
816
817         return 0;
818 fail:
819         gpio_free(hotplug_gpio);
820         return err;
821 }
822
823 static int tegra_hdmi_tmds_init(struct tegra_hdmi *hdmi)
824 {
825         struct device_node *np_prod = of_find_node_by_path(TMDS_NODE);
826
827         if (!np_prod) {
828                 dev_warn(&hdmi->dc->ndev->dev,
829                         "hdmi: find tmds prod node failed\n");
830                 return -EINVAL;
831         }
832
833         hdmi->prod_list =
834                 tegra_prod_init((const struct device_node *)np_prod);
835         if (IS_ERR(hdmi->prod_list)) {
836                 dev_warn(&hdmi->dc->ndev->dev,
837                         "hdmi: prod list init failed with error %ld\n",
838                         PTR_ERR(hdmi->prod_list));
839                 of_node_put(np_prod);
840                 return -EINVAL;
841         }
842
843         of_node_put(np_prod);
844         return 0;
845 }
846
847 static int tegra_hdmi_config_tmds(struct tegra_hdmi *hdmi)
848 {
849         size_t tmds_len;
850         int i;
851         int err = 0;
852
853         /* Select mode with smallest clk freq > pclk */
854         tmds_len = ARRAY_SIZE(tmds_config_modes);
855         for (i = 0; i < tmds_len - 1 &&
856                 tmds_config_modes[i].clk < hdmi->dc->mode.pclk; i++);
857
858         if (tegra_platform_is_linsim())
859                 return 0;
860
861         err = tegra_prod_set_by_name(&hdmi->sor->base,
862                                 tmds_config_modes[i].name, hdmi->prod_list);
863         if (err) {
864                 dev_warn(&hdmi->dc->ndev->dev,
865                         "hdmi: tmds prod set failed\n");
866                 return -EINVAL;
867         }
868
869         return 0;
870 }
871
872 static int tegra_hdmi_hdr_init(struct tegra_hdmi *hdmi)
873 {
874         INIT_DELAYED_WORK(&hdmi->hdr_worker, tegra_hdmi_hdr_worker);
875         return 0;
876 }
877
878 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
879 {
880         struct tegra_hdmi *hdmi;
881         int err;
882         struct device_node *np = dc->ndev->dev.of_node;
883 #ifdef CONFIG_OF
884         struct device_node *np_hdmi = of_find_node_by_path(HDMI_NODE);
885 #else
886         struct device_node *np_hdmi = NULL;
887 #endif
888         struct device_node *np_panel = NULL;
889         int edid_src = 0;
890
891         hdmi = devm_kzalloc(&dc->ndev->dev, sizeof(*hdmi), GFP_KERNEL);
892         if (!hdmi) {
893                 of_node_put(np_hdmi);
894                 return -ENOMEM;
895         }
896
897         hdmi->sor = tegra_dc_sor_init(dc, NULL);
898         if (IS_ERR_OR_NULL(hdmi->sor)) {
899                 err = PTR_ERR(hdmi->sor);
900                 goto fail;
901         }
902
903         if (np) {
904                 if (np_hdmi && of_device_is_available(np_hdmi)) {
905                         np_panel = tegra_get_panel_node_out_type_check(dc,
906                                 TEGRA_DC_OUT_HDMI);
907                         if (np_panel && of_device_is_available(np_panel)) {
908                                 if (of_property_read_bool(np_panel,
909                                                         "nvidia,edid"))
910                                         edid_src = 1;
911                                 of_node_put(np_panel);
912                         }
913                 } else {
914                         err = -EINVAL;
915                         of_node_put(np_panel);
916                         goto fail;
917                 }
918         }
919
920         hdmi->pdata = dc->pdata->default_out->hdmi_out;
921         hdmi->dc = dc;
922         dc_hdmi = hdmi;
923         hdmi->ddc_refcount = 0; /* assumes this is disabled when starting */
924         mutex_init(&hdmi->ddc_refcount_lock);
925         hdmi->nvhdcp = NULL;
926         hdmi->mon_spec_valid = false;
927         hdmi->eld_valid = false;
928         hdmi->device_shutdown = false;
929         if (0) {
930                 /* TODO: seamless boot mode needs initialize the state */
931         } else {
932                 hdmi->enabled = false;
933                 atomic_set(&hdmi->clock_refcount, 0);
934         }
935         atomic_set(&hdmi->suspended, 0);
936
937 #ifdef CONFIG_TEGRA_HDMIHDCP
938         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
939                         dc->out->ddc_bus);
940         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
941                 err = PTR_ERR(hdmi->nvhdcp);
942                 goto fail;
943         }
944         tegra_nvhdcp_debugfs_init(hdmi->nvhdcp);
945 #endif
946
947         tegra_hdmi_ddc_init(hdmi, edid_src);
948
949         tegra_hdmi_scdc_init(hdmi);
950
951         tegra_hdmi_hpd_init(hdmi);
952
953         tegra_hdmi_vrr_init(hdmi);
954
955         tegra_hdmi_debugfs_init(hdmi);
956
957         tegra_hdmi_tmds_init(hdmi);
958
959         tegra_dc_set_outdata(dc, hdmi);
960
961         tegra_hdmi_hdr_init(hdmi);
962
963         /* NOTE: Below code is applicable to L4T or embedded systems and is
964          * protected accordingly. This section early enables DC with first mode
965          * from the monitor specs.
966          * In case there is no hotplug we are falling back
967          * to default VGA mode.
968          */
969         if ((config_enabled(CONFIG_FRAMEBUFFER_CONSOLE) ||
970                         ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
971                          (dc->pdata->flags & TEGRA_DC_FLAG_SET_EARLY_MODE))) &&
972                         dc->out && (dc->out->type == TEGRA_DC_OUT_HDMI)) {
973                 struct fb_monspecs specs;
974                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
975                         if (!tegra_edid_get_monspecs(hdmi->edid, &specs))
976                                 tegra_dc_set_fb_mode(dc, specs.modedb, false);
977                         else {
978                         /* if for some reason there is no edid upon hotplug */
979                                 tegra_dc_set_fb_mode(dc,
980                                                 &tegra_dc_vga_mode, false);
981                         }
982                 } else
983                         tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, false);
984         }
985
986 #ifdef CONFIG_SWITCH
987         hdmi->hpd_switch.name = "hdmi";
988         err = switch_dev_register(&hdmi->hpd_switch);
989         if (err)
990                 dev_err(&dc->ndev->dev,
991                         "hdmi: failed to register hpd switch %d\n", err);
992
993         hdmi->audio_switch.name = "hdmi_audio";
994         err = switch_dev_register(&hdmi->audio_switch);
995         if (err)
996                 dev_err(&dc->ndev->dev,
997                         "hdmi: failed to register audio switch %d\n", err);
998 #endif
999
1000         hdmi_ddc = kobject_create_and_add("hdmi_ddc_power_toggle", kernel_kobj);
1001         if (!hdmi_ddc) {
1002                 pr_warn("kobject create_and_add hdmi_ddc_power_toggle failed\n");
1003                 return 0;
1004         }
1005         err = sysfs_create_file(hdmi_ddc, &hdmi_ddc_power_config.attr);
1006         if (err) {
1007                 pr_warn("sysfs create file hdmi_ddc_power_toggle failed\n");
1008                 return 0;
1009         }
1010
1011         of_node_put(np_hdmi);
1012         return 0;
1013 fail:
1014         devm_kfree(&dc->ndev->dev, hdmi);
1015         of_node_put(np_hdmi);
1016         return err;
1017 }
1018
1019 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1020 {
1021         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1022
1023         tegra_dc_sor_destroy(hdmi->sor);
1024         tegra_edid_destroy(hdmi->edid);
1025         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1026         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1027         gpio_free(dc->out->hotplug_gpio);
1028         devm_kfree(&dc->ndev->dev, hdmi);
1029         tegra_prod_release(&hdmi->prod_list);
1030
1031 #ifdef CONFIG_SWITCH
1032         switch_dev_unregister(&hdmi->hpd_switch);
1033         switch_dev_unregister(&hdmi->audio_switch);
1034 #endif
1035 }
1036
1037 static void tegra_hdmi_config(struct tegra_hdmi *hdmi)
1038 {
1039         struct tegra_dc_sor_data *sor = hdmi->sor;
1040         struct tegra_dc *dc = hdmi->dc;
1041 #ifndef CONFIG_TEGRA_NVDISPLAY
1042         u32 h_pulse_start, h_pulse_end;
1043 #endif
1044         u32 hblank, max_ac, rekey;
1045         unsigned long val;
1046         bool rgb_limited;
1047         u32 dispclk_div_8_2;
1048
1049         if (tegra_platform_is_linsim())
1050                 return;
1051
1052         rgb_limited = (dc->mode.vmode & FB_VMODE_LIMITED_RANGE) &&
1053                       !(dc->mode.vmode & FB_VMODE_YUV_MASK);
1054
1055         tegra_sor_write_field(sor, NV_SOR_INPUT_CONTROL,
1056                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED |
1057                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB,
1058                         (rgb_limited ?
1059                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED :
1060                         NV_SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_FULL) |
1061                         NV_SOR_INPUT_CONTROL_HDMI_SRC_SELECT_DISPLAYB);
1062
1063         dispclk_div_8_2 = clk_get_rate(hdmi->sor->sor_clk) / 1000000 * 4;
1064         tegra_sor_writel(sor, NV_SOR_REFCLK,
1065                         NV_SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1066                         NV_SOR_REFCLK_DIV_FRAC(dispclk_div_8_2));
1067
1068         /*
1069          * The rekey register and corresponding eq want to operate
1070          * on "-2" of the desired rekey value
1071          */
1072         rekey = NV_SOR_HDMI_CTRL_REKEY_DEFAULT - 2;
1073         hblank = dc->mode.h_sync_width + dc->mode.h_back_porch +
1074                         dc->mode.h_front_porch;
1075         max_ac = (hblank - rekey - 18) / 32;
1076
1077         val = 0;
1078         val |= hdmi->dvi ? 0x0 : NV_SOR_HDMI_CTRL_ENABLE;
1079         /* The register wants "-2" of the required rekey val */
1080         val |= NV_SOR_HDMI_CTRL_REKEY(rekey);
1081         val |= NV_SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac);
1082         val |= NV_SOR_HDMI_CTRL_AUDIO_LAYOUT_SELECT;
1083         tegra_sor_writel(sor, NV_SOR_HDMI_CTRL, val);
1084
1085 #ifndef CONFIG_TEGRA_NVDISPLAY
1086         tegra_dc_writel(dc, 0x180, DC_DISP_H_PULSE2_CONTROL);
1087         h_pulse_start = dc->mode.h_ref_to_sync +
1088                                         dc->mode.h_sync_width +
1089                                         dc->mode.h_back_porch - 10;
1090         h_pulse_end = h_pulse_start + 8;
1091         tegra_dc_writel(dc, PULSE_START(h_pulse_start) | PULSE_END(h_pulse_end),
1092                   DC_DISP_H_PULSE2_POSITION_A);
1093
1094         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
1095         val |= H_PULSE_2_ENABLE;
1096         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
1097 #endif
1098 }
1099
1100 void tegra_hdmi_infoframe_pkt_write(struct tegra_hdmi *hdmi,
1101                                                 u32 header_reg, u8 pkt_type,
1102                                                 u8 pkt_vs, u8 pkt_len,
1103                                                 void *reg_payload,
1104                                                 u32 reg_payload_len,
1105                                                 bool sw_checksum)
1106 {
1107         struct tegra_dc_sor_data *sor = hdmi->sor;
1108         u32 val;
1109         u32 *data = reg_payload;
1110         u32 data_reg = header_reg + 1;
1111
1112         val = NV_SOR_HDMI_INFOFRAME_HEADER_TYPE(pkt_type) |
1113                 NV_SOR_HDMI_INFOFRAME_HEADER_VERSION(pkt_vs) |
1114                 NV_SOR_HDMI_INFOFRAME_HEADER_LEN(pkt_len);
1115         tegra_sor_writel(sor, header_reg, val);
1116
1117         if (sw_checksum) {
1118                 u8 checksum = pkt_type + pkt_vs + pkt_len;
1119
1120                 for (val = 1; val <= pkt_len; val++)
1121                         checksum += ((u8 *)reg_payload)[val];
1122
1123                 /* The first byte of the payload must always be the checksum
1124                  * that we are going to calculate in SW */
1125                 ((u8 *)reg_payload)[0] = (256 - checksum);
1126         }
1127
1128         for (val = 0; val < reg_payload_len; val += 4, data_reg++, data++)
1129                 tegra_sor_writel(sor, data_reg, *data);
1130 }
1131
1132 u32 tegra_hdmi_get_cea_modedb_size(struct tegra_hdmi *hdmi)
1133 {
1134         if (!tegra_hdmi_is_connected(hdmi) || !hdmi->mon_spec_valid)
1135                 return 0;
1136
1137         return (hdmi->mon_spec.misc & FB_MISC_HDMI_FORUM) ?
1138                 CEA_861_F_MODEDB_SIZE : CEA_861_D_MODEDB_SIZE;
1139 }
1140
1141 static void tegra_hdmi_get_cea_fb_videomode(struct fb_videomode *m,
1142                                                 struct tegra_hdmi *hdmi)
1143 {
1144         struct tegra_dc *dc = hdmi->dc;
1145         struct tegra_dc_mode dc_mode;
1146         int yuv_flag;
1147
1148         memcpy(&dc_mode, &dc->mode, sizeof(dc->mode));
1149
1150         /* get CEA video timings */
1151         yuv_flag = dc_mode.vmode & FB_VMODE_YUV_MASK;
1152         if (yuv_flag == (FB_VMODE_Y420      | FB_VMODE_Y24) ||
1153             yuv_flag == (FB_VMODE_Y420_ONLY | FB_VMODE_Y24)) {
1154                 dc_mode.h_back_porch *= 2;
1155                 dc_mode.h_front_porch *= 2;
1156                 dc_mode.h_sync_width *= 2;
1157                 dc_mode.h_active *= 2;
1158                 dc_mode.pclk *= 2;
1159         } else if (yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) {
1160                 dc_mode.h_back_porch = (dc_mode.h_back_porch * 8) / 5;
1161                 dc_mode.h_front_porch = (dc_mode.h_front_porch * 8) / 5;
1162                 dc_mode.h_sync_width = (dc_mode.h_sync_width * 8) / 5;
1163                 dc_mode.h_active = (dc_mode.h_active * 8) / 5;
1164                 dc_mode.pclk = (dc_mode.pclk / 5) * 8;
1165         }
1166
1167         tegra_dc_to_fb_videomode(m, &dc_mode);
1168
1169         /* only interlaced required for VIC identification */
1170         m->vmode &= FB_VMODE_INTERLACED;
1171 }
1172
1173 __maybe_unused
1174 static int tegra_hdmi_find_cea_vic(struct tegra_hdmi *hdmi)
1175 {
1176         struct fb_videomode m;
1177         struct tegra_dc *dc = hdmi->dc;
1178         unsigned i;
1179         unsigned best = 0;
1180         u32 modedb_size = tegra_hdmi_get_cea_modedb_size(hdmi);
1181
1182         if (dc->initialized) {
1183                 u32 vic = tegra_sor_readl(hdmi->sor,
1184                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH) & 0xff;
1185                 if (!vic)
1186                         dev_warn(&dc->ndev->dev, "hdmi: BL set VIC 0\n");
1187                 return vic;
1188         }
1189
1190         tegra_hdmi_get_cea_fb_videomode(&m, hdmi);
1191
1192         m.flag &= ~FB_FLAG_RATIO_MASK;
1193         m.flag |= tegra_dc_get_aspect_ratio(dc);
1194
1195         for (i = 1; i < modedb_size; i++) {
1196                 const struct fb_videomode *curr = &cea_modes[i];
1197
1198                 if (!fb_mode_is_equal_tolerance(curr, &m,
1199                         FB_MODE_TOLERANCE_DEFAULT))
1200                         continue;
1201
1202                 if (!best)
1203                         best = i;
1204                 /* if either flag is set, then match is required */
1205                 if (curr->flag &
1206                         (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9 |
1207                         FB_FLAG_RATIO_64_27 | FB_FLAG_RATIO_256_135)) {
1208                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1209                                 best = i;
1210                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1211                                 best = i;
1212                         else if (m.flag & curr->flag & FB_FLAG_RATIO_64_27)
1213                                 best = i;
1214                         else if (m.flag & curr->flag & FB_FLAG_RATIO_256_135)
1215                                 best = i;
1216                 } else {
1217                         best = i;
1218                 }
1219         }
1220         return best;
1221 }
1222
1223 static u32 tegra_hdmi_get_aspect_ratio(struct tegra_hdmi *hdmi)
1224 {
1225         u32 aspect_ratio;
1226
1227         switch (hdmi->dc->mode.avi_m) {
1228         case TEGRA_DC_MODE_AVI_M_4_3:
1229                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1230                 break;
1231         case TEGRA_DC_MODE_AVI_M_16_9:
1232                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1233                 break;
1234         /*
1235          * no avi_m field for picture aspect ratio 64:27 and 256:135.
1236          * sink detects via VIC, avi_m is 0.
1237          */
1238         case TEGRA_DC_MODE_AVI_M_64_27: /* fall through */
1239         case TEGRA_DC_MODE_AVI_M_256_135: /* fall through */
1240         default:
1241                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1242         }
1243
1244         /* For seamless HDMI, read aspect ratio parameters from bootloader
1245          * set AVI Infoframe parameters
1246          */
1247         if ((aspect_ratio == HDMI_AVI_ASPECT_RATIO_NO_DATA) &&
1248                                         (hdmi->dc->initialized)) {
1249                 u32 temp = 0;
1250                 temp = tegra_sor_readl(hdmi->sor,
1251                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1252                 temp = (temp >> 20) & 0x3;
1253                 switch (temp) {
1254                 case 1:
1255                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_4_3;
1256                 break;
1257                 case 2:
1258                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_16_9;
1259                 break;
1260                 default:
1261                 aspect_ratio = HDMI_AVI_ASPECT_RATIO_NO_DATA;
1262                 }
1263         }
1264         return aspect_ratio;
1265 }
1266
1267 static u32 tegra_hdmi_get_rgb_ycc(struct tegra_hdmi *hdmi)
1268 {
1269         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1270
1271         /*
1272          * For seamless HDMI, read YUV flag parameters from bootloader
1273          * set AVI Infoframe parameters
1274          */
1275         if (hdmi->dc->initialized) {
1276                 u32 temp = 0;
1277                 temp = tegra_sor_readl(hdmi->sor,
1278                         NV_SOR_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
1279                 temp = (temp >> 12) & 0x3;
1280                 switch (temp) {
1281                 case HDMI_AVI_RGB:
1282                         return HDMI_AVI_RGB;
1283                 case HDMI_AVI_YCC_420:
1284                         return HDMI_AVI_YCC_420;
1285                 default:
1286                         dev_warn(&hdmi->dc->ndev->dev, "hdmi: BL didn't set RGB/YUV indicator flag\n");
1287                         break;
1288                 }
1289         }
1290
1291         if (yuv_flag & (FB_VMODE_Y420 | FB_VMODE_Y420_ONLY))
1292                 return HDMI_AVI_YCC_420;
1293         else if (yuv_flag & FB_VMODE_Y422)
1294                 return HDMI_AVI_YCC_422;
1295         else if (yuv_flag & FB_VMODE_Y444)
1296                 return HDMI_AVI_YCC_444;
1297
1298         return HDMI_AVI_RGB;
1299 }
1300
1301 static bool tegra_hdmi_is_ex_colorimetry(struct tegra_hdmi *hdmi)
1302 {
1303         return !!(hdmi->dc->mode.vmode & FB_VMODE_EC_ENABLE);
1304 }
1305
1306 static u32 tegra_hdmi_get_ex_colorimetry(struct tegra_hdmi *hdmi)
1307 {
1308         u32 vmode = hdmi->dc->mode.vmode;
1309
1310         return tegra_hdmi_is_ex_colorimetry(hdmi) ?
1311                 ((vmode & FB_VMODE_EC_MASK) >> FB_VMODE_EC_SHIFT) :
1312                 HDMI_AVI_EXT_COLORIMETRY_INVALID;
1313 }
1314
1315 static u32 tegra_hdmi_get_rgb_quant(struct tegra_hdmi *hdmi)
1316 {
1317         u32 vmode = hdmi->dc->mode.vmode;
1318
1319         if (tegra_edid_get_quant_cap(hdmi->edid) & FB_CAP_RGB_QUANT_SELECTABLE)
1320                 return vmode & FB_VMODE_LIMITED_RANGE ?
1321                         HDMI_AVI_RGB_QUANT_LIMITED : HDMI_AVI_RGB_QUANT_FULL;
1322         else
1323                 /*
1324                  * The safest way to break the HDMI spec when forcing full range
1325                  * on a limited system: send full data with the QUANT_DEFAULT
1326                  * */
1327                 return HDMI_AVI_RGB_QUANT_DEFAULT;
1328 }
1329
1330 static u32 tegra_hdmi_get_ycc_quant(struct tegra_hdmi *hdmi)
1331 {
1332         u32 vmode = hdmi->dc->mode.vmode;
1333
1334         if (tegra_edid_get_quant_cap(hdmi->edid) & FB_CAP_YUV_QUANT_SELECTABLE)
1335                 return vmode & FB_VMODE_LIMITED_RANGE ?
1336                         HDMI_AVI_YCC_QUANT_LIMITED : HDMI_AVI_YCC_QUANT_FULL;
1337         else
1338                 /*
1339                  * The safest way to break the HDMI spec when forcing full range
1340                  * on a limited system: send full data with the QUANT_DEFAULT
1341                  * */
1342                 return HDMI_AVI_YCC_QUANT_NONE;
1343 }
1344
1345 static void tegra_hdmi_avi_infoframe_update(struct tegra_hdmi *hdmi)
1346 {
1347         struct hdmi_avi_infoframe *avi = &hdmi->avi;
1348
1349         memset(&hdmi->avi, 0, sizeof(hdmi->avi));
1350
1351         if (tegra_platform_is_linsim())
1352                 return;
1353
1354         avi->scan = HDMI_AVI_UNDERSCAN;
1355         avi->bar_valid = HDMI_AVI_BAR_INVALID;
1356         avi->act_fmt_valid = HDMI_AVI_ACTIVE_FORMAT_INVALID;
1357         avi->rgb_ycc = tegra_hdmi_get_rgb_ycc(hdmi);
1358
1359         avi->act_format = HDMI_AVI_ACTIVE_FORMAT_SAME;
1360         avi->aspect_ratio = tegra_hdmi_get_aspect_ratio(hdmi);
1361         avi->colorimetry = tegra_hdmi_is_ex_colorimetry(hdmi) ?
1362                         HDMI_AVI_COLORIMETRY_EXTENDED_VALID :
1363                         HDMI_AVI_COLORIMETRY_DEFAULT;
1364
1365         avi->scaling = HDMI_AVI_SCALING_UNKNOWN;
1366         avi->rgb_quant = tegra_hdmi_get_rgb_quant(hdmi);
1367         avi->ext_colorimetry = tegra_hdmi_get_ex_colorimetry(hdmi);
1368         avi->it_content = HDMI_AVI_IT_CONTENT_FALSE;
1369
1370         /* set correct vic if video format is cea defined else set 0 */
1371         avi->video_format = tegra_hdmi_find_cea_vic(hdmi);
1372
1373         avi->pix_rep = HDMI_AVI_NO_PIX_REPEAT;
1374         avi->it_content_type = HDMI_AVI_IT_CONTENT_NONE;
1375         avi->ycc_quant = tegra_hdmi_get_ycc_quant(hdmi);
1376
1377         avi->top_bar_end_line_low_byte = 0;
1378         avi->top_bar_end_line_high_byte = 0;
1379
1380         avi->bot_bar_start_line_low_byte = 0;
1381         avi->bot_bar_start_line_high_byte = 0;
1382
1383         avi->left_bar_end_pixel_low_byte = 0;
1384         avi->left_bar_end_pixel_high_byte = 0;
1385
1386         avi->right_bar_start_pixel_low_byte = 0;
1387         avi->right_bar_start_pixel_high_byte = 0;
1388 }
1389
1390 static void tegra_hdmi_avi_infoframe(struct tegra_hdmi *hdmi)
1391 {
1392         struct tegra_dc_sor_data *sor = hdmi->sor;
1393
1394         if (hdmi->dvi)
1395                 return;
1396
1397         if (tegra_platform_is_linsim())
1398                 return;
1399
1400         /* disable avi infoframe before configuring except for seamless case */
1401         if (!hdmi->dc->initialized)
1402                 tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL, 0);
1403
1404         tegra_hdmi_avi_infoframe_update(hdmi);
1405
1406         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_AVI_INFOFRAME_HEADER,
1407                                         HDMI_INFOFRAME_TYPE_AVI,
1408                                         HDMI_INFOFRAME_VS_AVI,
1409                                         HDMI_INFOFRAME_LEN_AVI,
1410                                         &hdmi->avi, sizeof(hdmi->avi),
1411                                         false);
1412
1413         /* Send infoframe every frame, checksum hw generated */
1414         tegra_sor_writel(sor, NV_SOR_HDMI_AVI_INFOFRAME_CTRL,
1415                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES |
1416                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_OTHER_DISABLE |
1417                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DISABLE |
1418                 NV_SOR_HDMI_AVI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1419 }
1420
1421 static int tegra_hdmi_get_extended_vic(const struct tegra_dc_mode *mode)
1422 {
1423         struct fb_videomode m;
1424         unsigned i;
1425
1426         tegra_dc_to_fb_videomode(&m, mode);
1427
1428         /* only interlaced required for VIC identification */
1429         m.vmode &= FB_VMODE_INTERLACED;
1430
1431         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1432                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1433
1434                 if (fb_mode_is_equal_tolerance(curr, &m,
1435                         FB_MODE_TOLERANCE_DEFAULT))
1436                         return i;
1437         }
1438         return 0;
1439 }
1440
1441 static void tegra_hdmi_vendor_infoframe_update(struct tegra_hdmi *hdmi)
1442 {
1443         struct hdmi_vendor_infoframe *vsi = &hdmi->vsi;
1444         u8 extended_vic;
1445
1446         memset(&hdmi->vsi, 0, sizeof(hdmi->vsi));
1447
1448         vsi->oui = HDMI_LICENSING_LLC_OUI;
1449
1450         extended_vic = tegra_hdmi_get_extended_vic(&hdmi->dc->mode);
1451         if (extended_vic) {
1452                 vsi->video_format =
1453                         HDMI_VENDOR_VIDEO_FORMAT_EXTENDED;
1454                 vsi->extended_vic = extended_vic;
1455         }
1456 }
1457
1458 static void tegra_hdmi_vendor_infoframe(struct tegra_hdmi *hdmi)
1459 {
1460 /* hdmi licensing, LLC vsi playload len as per hdmi1.4b  */
1461 #define HDMI_INFOFRAME_LEN_VENDOR_LLC   (6)
1462
1463         struct tegra_dc_sor_data *sor = hdmi->sor;
1464
1465         if (hdmi->dvi)
1466                 return;
1467
1468         /* disable vsi infoframe before configuring */
1469         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL, 0);
1470
1471         tegra_hdmi_vendor_infoframe_update(hdmi);
1472
1473         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_VSI_INFOFRAME_HEADER,
1474                                         HDMI_INFOFRAME_TYPE_VENDOR,
1475                                         HDMI_INFOFRAME_VS_VENDOR,
1476                                         HDMI_INFOFRAME_LEN_VENDOR_LLC,
1477                                         &hdmi->vsi, sizeof(hdmi->vsi),
1478                                         false);
1479
1480         /* Send infoframe every frame, checksum hw generated */
1481         tegra_sor_writel(sor, NV_SOR_HDMI_VSI_INFOFRAME_CTRL,
1482                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_ENABLE_YES |
1483                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_OTHER_DISABLE |
1484                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_SINGLE_DISABLE |
1485                 NV_SOR_HDMI_VSI_INFOFRAME_CTRL_CHECKSUM_ENABLE);
1486
1487 #undef HDMI_INFOFRAME_LEN_VENDOR_LLC
1488 }
1489
1490 static void tegra_hdmi_hdr_infoframe_update(struct tegra_hdmi *hdmi)
1491 {
1492         struct hdmi_hdr_infoframe *hdr = &hdmi->hdr;
1493
1494         memset(&hdmi->hdr, 0, sizeof(hdmi->hdr));
1495
1496         if (tegra_platform_is_linsim())
1497                 return;
1498
1499         hdr->eotf = hdmi->dc->hdr.eotf;
1500         hdr->static_metadata_id = hdmi->dc->hdr.static_metadata_id;
1501
1502         /* PB3-14 : Group 1 : Static Metadata*/
1503         hdr->display_primaries_x_0_lsb = hdmi->dc->hdr.static_metadata[0];
1504         hdr->display_primaries_x_0_msb = hdmi->dc->hdr.static_metadata[1];
1505         hdr->display_primaries_y_0_lsb = hdmi->dc->hdr.static_metadata[2];
1506         hdr->display_primaries_y_0_msb = hdmi->dc->hdr.static_metadata[3];
1507         hdr->display_primaries_x_1_lsb = hdmi->dc->hdr.static_metadata[4];
1508         hdr->display_primaries_x_1_msb = hdmi->dc->hdr.static_metadata[5];
1509         hdr->display_primaries_y_1_lsb = hdmi->dc->hdr.static_metadata[6];
1510         hdr->display_primaries_y_1_msb = hdmi->dc->hdr.static_metadata[7];
1511         hdr->display_primaries_x_2_lsb = hdmi->dc->hdr.static_metadata[8];
1512         hdr->display_primaries_x_2_msb = hdmi->dc->hdr.static_metadata[9];
1513         hdr->display_primaries_y_2_lsb = hdmi->dc->hdr.static_metadata[10];
1514         hdr->display_primaries_y_2_msb = hdmi->dc->hdr.static_metadata[11];
1515
1516         /* PB15-18 : Group 2 : Static Metadata*/
1517         hdr->white_point_x_lsb = hdmi->dc->hdr.static_metadata[12];
1518         hdr->white_point_x_msb = hdmi->dc->hdr.static_metadata[13];
1519         hdr->white_point_y_lsb = hdmi->dc->hdr.static_metadata[14];
1520         hdr->white_point_y_msb = hdmi->dc->hdr.static_metadata[15];
1521
1522         /* PB19-20 : Group 3 : Static Metadata*/
1523         hdr->max_display_mastering_luminance_lsb =
1524                                         hdmi->dc->hdr.static_metadata[16];
1525         hdr->max_display_mastering_luminance_msb =
1526                                         hdmi->dc->hdr.static_metadata[17];
1527
1528         /* PB21-22 : Group 4 : Static Metadata*/
1529         hdr->min_display_mastering_luminance_lsb =
1530                                         hdmi->dc->hdr.static_metadata[18];
1531         hdr->min_display_mastering_luminance_msb =
1532                                         hdmi->dc->hdr.static_metadata[19];
1533
1534         /* PB23-24 : Group 5 : Static Metadata*/
1535         hdr->max_content_light_level_lsb = hdmi->dc->hdr.static_metadata[20];
1536         hdr->max_content_light_level_msb = hdmi->dc->hdr.static_metadata[21];
1537
1538         /* PB25-26 : Group 6 : Static Metadata*/
1539         hdr->max_frame_avg_light_level_lsb = hdmi->dc->hdr.static_metadata[22];
1540         hdr->min_frame_avg_light_level_msb = hdmi->dc->hdr.static_metadata[23];
1541
1542         return;
1543 }
1544
1545 static void tegra_hdmi_hdr_infoframe(struct tegra_hdmi *hdmi)
1546 {
1547         struct tegra_dc_sor_data *sor = hdmi->sor;
1548
1549         /* set_bits = contains all the bits to be set
1550          * for NV_SOR_HDMI_GENERIC_CTRL reg */
1551         u32 set_bits = (NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES |
1552                         NV_SOR_HDMI_GENERIC_CTRL_AUDIO_ENABLE);
1553
1554         /* disable generic infoframe before configuring */
1555         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, 0);
1556
1557         tegra_hdmi_hdr_infoframe_update(hdmi);
1558
1559         tegra_hdmi_infoframe_pkt_write(hdmi, NV_SOR_HDMI_GENERIC_HEADER,
1560                                         HDMI_INFOFRAME_TYPE_HDR,
1561                                         HDMI_INFOFRAME_VS_HDR,
1562                                         HDMI_INFOFRAME_LEN_HDR,
1563                                         &hdmi->hdr, sizeof(hdmi->hdr),
1564                                         true);
1565
1566         /* set the required bits in NV_SOR_HDMI_GENERIC_CTRL*/
1567         tegra_sor_writel(sor, NV_SOR_HDMI_GENERIC_CTRL, set_bits);
1568
1569         return;
1570 }
1571
1572 __maybe_unused
1573 static int tegra_hdmi_scdc_read(struct tegra_hdmi *hdmi,
1574                                         u8 offset_data[][2], u32 n_entries)
1575 {
1576         u32 i;
1577         struct i2c_msg msg[] = {
1578                 {
1579                         .addr = 0x54,
1580                         .len = 1,
1581                         .buf = NULL,
1582                 },
1583                 {
1584                         .addr = 0x54,
1585                         .flags = I2C_M_RD,
1586                         .len = 1,
1587                         .buf = NULL,
1588                 },
1589         };
1590
1591         _tegra_hdmi_ddc_enable(hdmi);
1592
1593         for (i = 0; i < n_entries; i++) {
1594                 msg[0].buf = offset_data[i];
1595                 msg[1].buf = &offset_data[i][1];
1596                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1597         }
1598
1599         _tegra_hdmi_ddc_disable(hdmi);
1600
1601         return 0;
1602 }
1603
1604 static int tegra_hdmi_scdc_write(struct tegra_hdmi *hdmi,
1605                                         u8 offset_data[][2], u32 n_entries)
1606 {
1607         u32 i;
1608         struct i2c_msg msg[] = {
1609                 {
1610                         .addr = 0x54,
1611                         .len = 2,
1612                         .buf = NULL,
1613                 },
1614         };
1615
1616         _tegra_hdmi_ddc_enable(hdmi);
1617
1618         for (i = 0; i < n_entries; i++) {
1619                 msg[0].buf = offset_data[i];
1620                 tegra_hdmi_scdc_i2c_xfer(hdmi->dc, msg, ARRAY_SIZE(msg));
1621         }
1622
1623         _tegra_hdmi_ddc_disable(hdmi);
1624
1625         return 0;
1626 }
1627
1628 static int tegra_hdmi_v2_x_mon_config(struct tegra_hdmi *hdmi, bool enable)
1629 {
1630         u8 tmds_config_en[][2] = {
1631                 {
1632                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1633                         (HDMI_SCDC_TMDS_CONFIG_BIT_CLK_RATIO_40 |
1634                         HDMI_SCDC_TMDS_CONFIG_SCRAMBLING_EN)
1635                 },
1636         };
1637         u8 tmds_config_dis[][2] = {
1638                 {
1639                         HDMI_SCDC_TMDS_CONFIG_OFFSET,
1640                         0
1641                 },
1642         };
1643
1644         if (hdmi->dc->vedid)
1645                 goto skip_scdc_i2c;
1646
1647         tegra_hdmi_scdc_write(hdmi,
1648                         enable ? tmds_config_en : tmds_config_dis,
1649                         ARRAY_SIZE(tmds_config_en));
1650
1651 skip_scdc_i2c:
1652         return 0;
1653 }
1654
1655 static void tegra_hdmi_v2_x_host_config(struct tegra_hdmi *hdmi, bool enable)
1656 {
1657         u32 val = NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1658                 NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4;
1659
1660         tegra_sor_write_field(hdmi->sor, NV_SOR_HDMI2_CTRL,
1661                         NV_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE |
1662                         NV_SOR_HDMI2_CTRL_CLK_MODE_DIV_BY_4,
1663                         enable ? val : 0);
1664 }
1665
1666 static int _tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1667 {
1668 #define SCDC_STABILIZATION_DELAY_MS (20)
1669
1670         /* disable hdmi2.x config on host and monitor only
1671          * if bootloader didn't initialize hdmi
1672          */
1673         if (!hdmi->dc->initialized) {
1674                 tegra_hdmi_v2_x_mon_config(hdmi, false);
1675                 tegra_hdmi_v2_x_host_config(hdmi, false);
1676         }
1677
1678         /* enable hdmi2.x config on host and monitor */
1679         tegra_hdmi_v2_x_mon_config(hdmi, true);
1680         msleep(SCDC_STABILIZATION_DELAY_MS);
1681
1682         tegra_hdmi_v2_x_host_config(hdmi, true);
1683
1684         return 0;
1685 #undef SCDC_STABILIZATION_DELAY_MS
1686 }
1687
1688 static int tegra_hdmi_v2_x_config(struct tegra_hdmi *hdmi)
1689 {
1690         _tegra_hdmi_v2_x_config(hdmi);
1691
1692         return 0;
1693 }
1694
1695 static void tegra_hdmi_scdc_worker(struct work_struct *work)
1696 {
1697         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
1698                                 struct tegra_hdmi, scdc_work);
1699         u8 rd_status_flags[][2] = {
1700                 {HDMI_SCDC_STATUS_FLAGS, 0x0}
1701         };
1702
1703         if (!hdmi->enabled || hdmi->dc->mode.pclk <= 340000000)
1704                 return;
1705
1706         if (hdmi->dc->vedid)
1707                 goto skip_scdc_i2c;
1708
1709         if (!tegra_edid_is_scdc_present(hdmi->dc->edid))
1710                 return;
1711
1712         tegra_hdmi_scdc_read(hdmi, rd_status_flags,
1713                                         ARRAY_SIZE(rd_status_flags));
1714         if (!rd_status_flags[0][1]  && (hdmi->dc->mode.pclk > 340000000)) {
1715                 dev_info(&hdmi->dc->ndev->dev, "hdmi: scdc scrambling status is reset, "
1716                                                 "trying to reconfigure.\n");
1717                 _tegra_hdmi_v2_x_config(hdmi);
1718         }
1719
1720 skip_scdc_i2c:
1721         /* reschedule the worker */
1722         cancel_delayed_work(&hdmi->scdc_work);
1723         schedule_delayed_work(&hdmi->scdc_work,
1724                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1725 }
1726
1727 static void _tegra_hdmi_clock_enable(struct tegra_hdmi *hdmi)
1728 {
1729         struct tegra_dc_sor_data *sor = hdmi->sor;
1730         tegra_disp_clk_prepare_enable(sor->safe_clk);
1731         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
1732         tegra_sor_clk_enable(sor);
1733 }
1734
1735 static void _tegra_hdmi_clock_disable(struct tegra_hdmi *hdmi)
1736 {
1737         struct tegra_dc_sor_data *sor = hdmi->sor;
1738         tegra_sor_clk_disable(sor);
1739 }
1740
1741 void tegra_hdmi_get(struct tegra_dc *dc)
1742 {
1743         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1744
1745         if (atomic_inc_return(&hdmi->clock_refcount) == 1)
1746                 _tegra_hdmi_clock_enable(hdmi);
1747 }
1748
1749 void tegra_hdmi_put(struct tegra_dc *dc)
1750 {
1751         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1752
1753         if (WARN_ONCE(atomic_read(&hdmi->clock_refcount) <= 0,
1754                 "hdmi: clock refcount imbalance"))
1755                 return;
1756         if (atomic_dec_return(&hdmi->clock_refcount) == 0)
1757                 _tegra_hdmi_clock_disable(hdmi);
1758 }
1759
1760 /* TODO: add support for other deep colors */
1761 static inline u32 tegra_hdmi_get_bpp(struct tegra_hdmi *hdmi)
1762 {
1763         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1764
1765         if ((yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) ||
1766                 (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y30)))
1767                 return 30;
1768         else if (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36))
1769                 return 36;
1770         else if (yuv_flag == (FB_VMODE_Y422 | FB_VMODE_Y36))
1771                 return 24;
1772         else
1773                 return 0;
1774 }
1775
1776 static u32 tegra_hdmi_gcp_color_depth(struct tegra_hdmi *hdmi)
1777 {
1778         u32 gcp_cd = 0;
1779
1780         switch (tegra_hdmi_get_bpp(hdmi)) {
1781         case 0:
1782                 gcp_cd = TEGRA_HDMI_BPP_UNKNOWN;
1783                 break;
1784         case 24:
1785                 gcp_cd = TEGRA_HDMI_BPP_24;
1786                 break;
1787         case 30:
1788                 gcp_cd = TEGRA_HDMI_BPP_30;
1789                 break;
1790         case 36:
1791                 gcp_cd = TEGRA_HDMI_BPP_36;
1792                 break;
1793         case 48:
1794                 gcp_cd = TEGRA_HDMI_BPP_48;
1795                 break;
1796         default:
1797                 dev_WARN(&hdmi->dc->ndev->dev,
1798                         "hdmi: unknown gcp color depth\n");
1799         };
1800
1801         return gcp_cd;
1802 }
1803
1804 /* return packing phase of last pixel in preceding video data period */
1805 static u32 tegra_hdmi_gcp_packing_phase(struct tegra_hdmi *hdmi)
1806 {
1807         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1808
1809         if (!tegra_hdmi_gcp_color_depth(hdmi))
1810                 return 0;
1811
1812         if (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36))
1813                 return 2;
1814         else
1815                 return 0;
1816 }
1817
1818 static bool tegra_hdmi_gcp_default_phase_en(struct tegra_hdmi *hdmi)
1819 {
1820         int yuv_flag = hdmi->dc->mode.vmode & FB_VMODE_YUV_MASK;
1821
1822         if (!tegra_hdmi_gcp_color_depth(hdmi))
1823                 return false;
1824
1825         if ((yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30)) ||
1826                         (!(yuv_flag & YUV_MASK) && (yuv_flag == FB_VMODE_Y36)))
1827                 return true;
1828         else
1829                 return false;
1830 }
1831
1832 /* general control packet */
1833 static void tegra_hdmi_gcp(struct tegra_hdmi *hdmi)
1834 {
1835 #define GCP_SB1_PP_SHIFT 4
1836
1837         struct tegra_dc_sor_data *sor = hdmi->sor;
1838         u8 sb1, sb2;
1839
1840         /* disable gcp before configuring */
1841         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL, 0);
1842
1843         sb1 = tegra_hdmi_gcp_packing_phase(hdmi) << GCP_SB1_PP_SHIFT |
1844                 tegra_hdmi_gcp_color_depth(hdmi);
1845         sb2 = !!tegra_hdmi_gcp_default_phase_en(hdmi);
1846         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_SUBPACK(0),
1847                         sb1 << NV_SOR_HDMI_GCP_SUBPACK_SB1_SHIFT |
1848                         sb2 << NV_SOR_HDMI_GCP_SUBPACK_SB2_SHIFT);
1849
1850         /* Send gcp every frame */
1851         tegra_sor_writel(sor, NV_SOR_HDMI_GCP_CTRL,
1852                         NV_SOR_HDMI_GCP_CTRL_ENABLE |
1853                         NV_SOR_HDMI_GCP_CTRL_OTHER_DIS |
1854                         NV_SOR_HDMI_GCP_CTRL_SINGLE_DIS);
1855
1856 #undef GCP_SB1_PP_SHIFT
1857 }
1858
1859 static int tegra_hdmi_controller_enable(struct tegra_hdmi *hdmi)
1860 {
1861         struct tegra_dc *dc = hdmi->dc;
1862         struct tegra_dc_sor_data *sor = hdmi->sor;
1863
1864         tegra_dc_get(dc);
1865         tegra_hdmi_get(dc);
1866
1867         tegra_sor_hdmi_pad_power_up(sor);
1868
1869         tegra_sor_power_lanes(sor, 4, true);
1870
1871         tegra_dc_sor_set_internal_panel(sor, false);
1872         tegra_hdmi_config(hdmi);
1873         tegra_hdmi_avi_infoframe(hdmi);
1874         tegra_hdmi_vendor_infoframe(hdmi);
1875
1876         tegra_sor_pad_cal_power(sor, true);
1877         tegra_hdmi_config_tmds(hdmi);
1878         tegra_sor_pad_cal_power(sor, false);
1879
1880         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_BRICK_CLK);
1881         tegra_dc_sor_attach(sor);
1882         tegra_nvhdcp_set_plug(hdmi->nvhdcp, true);
1883
1884         tegra_dc_setup_clk(dc, dc->clk);
1885         tegra_dc_hdmi_setup_clk(dc, hdmi->sor->sor_clk);
1886         tegra_hdmi_config(hdmi);
1887
1888         tegra_sor_config_xbar(hdmi->sor);
1889
1890         /* TODO: Confirm sequence with HW */
1891         tegra_sor_writel(sor,  NV_SOR_SEQ_INST(0), 0x8080);
1892         tegra_sor_writel(sor,  NV_SOR_PWR, 0x80000001);
1893
1894         if (hdmi->dc->mode.pclk > 340000000) {
1895                 tegra_hdmi_v2_x_config(hdmi);
1896                 schedule_delayed_work(&hdmi->scdc_work,
1897                         msecs_to_jiffies(HDMI_SCDC_MONITOR_TIMEOUT_MS));
1898         }
1899
1900         tegra_hdmi_gcp(hdmi);
1901
1902         tegra_dc_put(dc);
1903         return 0;
1904 }
1905
1906 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1907 {
1908         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
1909
1910         if (hdmi->enabled)
1911                 return;
1912
1913         tegra_hdmi_controller_enable(hdmi);
1914
1915         hdmi->enabled = true;
1916         tegra_hda_set_data(hdmi, SINK_HDMI);
1917 #ifdef CONFIG_SWITCH
1918         if (!hdmi->dvi)
1919                 switch_set_state(&hdmi->audio_switch, 1);
1920 #endif
1921 }
1922
1923 static inline u32 tegra_hdmi_get_shift_clk_div(struct tegra_hdmi *hdmi)
1924 {
1925         /*
1926          * HW does not support deep color yet
1927          * always return 0
1928          */
1929
1930         return 0;
1931 }
1932
1933 static void tegra_hdmi_config_clk(struct tegra_hdmi *hdmi, u32 clk_type)
1934 {
1935         if (clk_type == hdmi->clk_type)
1936                 return;
1937
1938         if (tegra_platform_is_linsim())
1939                 return;
1940
1941         if (clk_type == TEGRA_HDMI_BRICK_CLK) {
1942                 u32 val;
1943                 struct tegra_dc_sor_data *sor = hdmi->sor;
1944                 int div = hdmi->dc->mode.pclk < 340000000 ? 1 : 2;
1945                 unsigned long rate = clk_get_rate(sor->src_switch_clk);
1946                 unsigned long parent_rate =
1947                         clk_get_rate(clk_get_parent(sor->src_switch_clk));
1948
1949                 /* Set sor divider */
1950                 if (rate != DIV_ROUND_UP(parent_rate, div)) {
1951                         rate = DIV_ROUND_UP(parent_rate, div);
1952                         clk_set_rate(sor->src_switch_clk, rate);
1953                 }
1954
1955                 /* Select brick muxes */
1956                 val = (hdmi->dc->mode.pclk < 340000000) ?
1957                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G2_7 :
1958                         NV_SOR_CLK_CNTRL_DP_LINK_SPEED_G5_4;
1959
1960                 val |= NV_SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK;
1961                 tegra_sor_writel(hdmi->sor, NV_SOR_CLK_CNTRL, val);
1962                 usleep_range(250, 300); /* sor brick pll stabilization delay */
1963
1964                 /*
1965                  * Report brick configuration and rate, so that SOR clock tree
1966                  * is properly updated. No h/w changes by clock api calls below,
1967                  * just sync s/w state with brick h/w.
1968                  */
1969                 rate = rate/NV_SOR_HDMI_BRICK_DIV*NV_SOR_HDMI_BRICK_MUL(val);
1970                 if (clk_get_parent(sor->brick_clk) != sor->src_switch_clk)
1971                         clk_set_parent(sor->brick_clk, sor->src_switch_clk);
1972                 clk_set_rate(sor->brick_clk, rate);
1973
1974                 /*
1975                  * Select primary -- HDMI -- DVFS table for SOR clock (if SOR
1976                  * clock has single DVFS table for all modes, nothing changes).
1977                  */
1978                 tegra_dvfs_use_alt_freqs_on_clk(sor->sor_clk, false);
1979
1980                 /* Select sor clock muxes */
1981                 tegra_clk_cfg_ex(sor->sor_clk, TEGRA_CLK_SOR_CLK_SEL, 3);
1982
1983                 tegra_dc_writel(hdmi->dc, PIXEL_CLK_DIVIDER_PCD1 |
1984                         SHIFT_CLK_DIVIDER(tegra_hdmi_get_shift_clk_div(hdmi)),
1985                         DC_DISP_DISP_CLOCK_CONTROL);
1986
1987                 hdmi->clk_type = TEGRA_HDMI_BRICK_CLK;
1988         } else if (clk_type == TEGRA_HDMI_SAFE_CLK) {
1989                 if (!hdmi->dc->initialized) {
1990                         /* Select sor clock muxes */
1991                         tegra_clk_cfg_ex(hdmi->sor->sor_clk,
1992                                 TEGRA_CLK_SOR_CLK_SEL, 0);
1993                         hdmi->clk_type = TEGRA_HDMI_SAFE_CLK;
1994                 }
1995         } else {
1996                 dev_err(&hdmi->dc->ndev->dev, "hdmi: incorrect clk type configured\n");
1997         }
1998 }
1999
2000 /* returns exact pixel clock in Hz */
2001 static long tegra_hdmi_get_pclk(struct tegra_dc_mode *mode)
2002 {
2003         long h_total, v_total;
2004         long refresh, pclk;
2005         h_total = mode->h_active + mode->h_front_porch + mode->h_back_porch +
2006                 mode->h_sync_width;
2007         v_total = mode->v_active + mode->v_front_porch + mode->v_back_porch +
2008                 mode->v_sync_width;
2009         refresh = tegra_dc_calc_refresh(mode);
2010         refresh = DIV_ROUND_CLOSEST(refresh, 1000);
2011
2012         pclk = h_total * v_total * refresh;
2013
2014         if (mode->vmode & FB_VMODE_1000DIV1001)
2015                 pclk = pclk * 1000 / 1001;
2016
2017         return pclk;
2018 }
2019
2020 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
2021 {
2022 #ifdef CONFIG_TEGRA_NVDISPLAY
2023         struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
2024                                 dc->out->parent_clk ? : "plld2");
2025 #else
2026         struct clk *parent_clk = clk_get(NULL,
2027                                 dc->out->parent_clk ? : "pll_d2");
2028 #endif
2029
2030         dc->mode.pclk = tegra_hdmi_get_pclk(&dc->mode);
2031
2032         if (IS_ERR_OR_NULL(parent_clk)) {
2033                 dev_err(&dc->ndev->dev, "hdmi: parent clk get failed\n");
2034                 return 0;
2035         }
2036
2037         if (!tegra_platform_is_silicon())
2038                 return dc->mode.pclk;
2039
2040 #ifdef CONFIG_TEGRA_NVDISPLAY
2041         if (clk_get_parent(clk) != parent_clk)
2042                 clk_set_parent(clk, parent_clk);
2043 #else
2044         if (clk == dc->clk) {
2045                 if (clk_get_parent(clk) != parent_clk) {
2046                         if (clk_set_parent(clk, parent_clk)) {
2047                                 dev_err(&dc->ndev->dev,
2048                                         "hdmi: set dc parent failed\n");
2049                                 return 0;
2050                         }
2051                 }
2052         } else {
2053                 struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2054                 struct tegra_dc_sor_data *sor = hdmi->sor;
2055
2056                 if (clk_get_parent(sor->src_switch_clk) != parent_clk) {
2057                         if (clk_set_parent(sor->src_switch_clk, parent_clk)) {
2058                                 dev_err(&dc->ndev->dev,
2059                                         "hdmi: set src switch parent failed\n");
2060                                 return 0;
2061                         }
2062                 }
2063         }
2064 #endif
2065         if (dc->initialized)
2066                 goto skip_setup;
2067         if (clk_get_rate(parent_clk) != dc->mode.pclk)
2068                 clk_set_rate(parent_clk, dc->mode.pclk);
2069 skip_setup:
2070         /*
2071          * DC clock divider is controlled by DC driver transparently to clock
2072          * framework -- hence, direct call to DVFS with target mode rate. SOR
2073          * clock rate in clock tree is properly updated, and can be used for
2074          * DVFS update.
2075          *
2076          * TODO: tegra_hdmi_controller_enable() procedure 1st configures SOR
2077          * clock via tegra_hdmi_config_clk(), and then calls this function
2078          * that may re-lock parent PLL. That needs to be double-checked:
2079          * in general re-locking PLL while the downstream module is already
2080          * sourced from it is not recommended. If/when the order of enabling
2081          * HDMI controller is changed, we can remove direct DVFS call for SOR
2082          * (but for DC it should be kept, anyway).
2083          */
2084         if (clk == dc->clk)
2085                 tegra_dvfs_set_rate(clk, dc->mode.pclk);
2086         else
2087                 tegra_dvfs_set_rate(clk, clk_get_rate(clk));
2088
2089         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2090 }
2091
2092 static void tegra_dc_hdmi_shutdown(struct tegra_dc *dc)
2093 {
2094         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2095
2096         _tegra_hdmivrr_activate(hdmi, false);
2097         hdmi->device_shutdown = true;
2098         tegra_nvhdcp_shutdown(hdmi->nvhdcp);
2099
2100         return;
2101 }
2102
2103 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2104 {
2105         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2106
2107         _tegra_hdmivrr_activate(hdmi, false);
2108         hdmi->enabled = false;
2109 #ifdef CONFIG_SWITCH
2110         switch_set_state(&hdmi->audio_switch, 0);
2111 #endif
2112
2113         tegra_hdmi_config_clk(hdmi, TEGRA_HDMI_SAFE_CLK);
2114         tegra_hdmi_controller_disable(hdmi);
2115         tegra_hda_reset_data();
2116         return;
2117 }
2118
2119 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
2120 {
2121         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2122         unsigned long delay = msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS);
2123
2124         if (tegra_platform_is_linsim())
2125                 return true;
2126
2127         if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL)
2128                 delay = 0;
2129
2130         cancel_delayed_work(&hdmi->hpd_worker);
2131         schedule_delayed_work(&hdmi->hpd_worker, delay);
2132
2133         return tegra_dc_hpd(dc);
2134 }
2135
2136 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
2137 {
2138         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2139
2140         _tegra_hdmivrr_activate(hdmi, false);
2141
2142         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0) {
2143                 int wake_irq = gpio_to_irq(dc->out->hotplug_gpio);
2144                 int ret;
2145
2146                 ret = enable_irq_wake(wake_irq);
2147                 if (ret < 0) {
2148                         dev_err(&dc->ndev->dev,
2149                         "%s: Couldn't enable HDMI wakeup, irq=%d, error=%d\n",
2150                         __func__, wake_irq, ret);
2151                 }
2152         }
2153
2154         atomic_set(&hdmi->suspended, 1);
2155 }
2156
2157 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
2158 {
2159         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2160
2161         atomic_set(&hdmi->suspended, 0);
2162
2163         if (dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
2164                 disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
2165
2166         cancel_delayed_work(&hdmi->hpd_worker);
2167
2168         /* If resume happens with a non-VRR monitor, the HPD
2169            worker will correct the mode based on the new EDID */
2170         _tegra_hdmivrr_activate(hdmi, true);
2171
2172         schedule_delayed_work(&hdmi->hpd_worker,
2173                                 msecs_to_jiffies(HDMI_HPD_DEBOUNCE_DELAY_MS + HDMI_HPD_DROP_TIMEOUT_MS));
2174 }
2175
2176 static int tegra_dc_hdmi_set_hdr(struct tegra_dc *dc)
2177 {
2178         u16 ret = 0;
2179         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2180
2181         /* If the sink isn't HDR capable, return */
2182         ret = tegra_edid_get_ex_hdr_cap(hdmi->edid);
2183         if (!ret)
2184                 return 0;
2185
2186         /* Cancel any pending hdr-exit work */
2187         if (dc->hdr.enabled)
2188                 cancel_delayed_work_sync(&hdmi->hdr_worker);
2189
2190         tegra_hdmi_hdr_infoframe(hdmi);
2191
2192         /*
2193          *If hdr is disabled then send HDR infoframe for
2194          *2 secs with SDR eotf and then stop
2195          */
2196         if (dc->hdr.enabled)
2197                 return 0;
2198
2199         schedule_delayed_work(&hdmi->hdr_worker,
2200                 msecs_to_jiffies(HDMI_HDR_INFOFRAME_STOP_TIMEOUT_MS));
2201
2202         return 0;
2203 }
2204
2205 static void tegra_hdmi_hdr_worker(struct work_struct *work)
2206 {
2207         u32 val = 0;
2208         struct tegra_hdmi *hdmi = container_of(to_delayed_work(work),
2209                                 struct tegra_hdmi, hdr_worker);
2210
2211         if (hdmi && hdmi->enabled) {
2212                 /* If hdr re-enabled within 2s, return.
2213                  * Note this an extra safety check since
2214                  * we should have already cancelled this work */
2215                 if (hdmi->dc->hdr.enabled)
2216                         return;
2217                 /* Read the current regsiter value to restore the bits */
2218                 val = tegra_sor_readl(hdmi->sor, NV_SOR_HDMI_GENERIC_CTRL);
2219
2220                 /* Set val to disable generic infoframe */
2221                 val &= ~NV_SOR_HDMI_GENERIC_CTRL_ENABLE_YES;
2222
2223                 tegra_sor_writel(hdmi->sor, NV_SOR_HDMI_GENERIC_CTRL, val);
2224         }
2225         return;
2226 }
2227
2228 static int tegra_dc_hdmi_ddc_enable(struct tegra_dc *dc)
2229 {
2230         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2231         _tegra_hdmi_ddc_enable(hdmi);
2232         return 0;
2233 }
2234
2235 static int tegra_dc_hdmi_ddc_disable(struct tegra_dc *dc)
2236 {
2237         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2238         _tegra_hdmi_ddc_disable(hdmi);
2239         return 0;
2240 }
2241
2242 static void tegra_dc_hdmi_modeset_notifier(struct tegra_dc *dc)
2243 {
2244         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2245
2246         tegra_hdmi_get(dc);
2247         tegra_dc_io_start(dc);
2248
2249         /* disable hdmi2.x config on host and monitor */
2250         if (dc->mode.pclk > 340000000) {
2251                 if (tegra_edid_is_scdc_present(dc->edid))
2252                         tegra_hdmi_v2_x_mon_config(hdmi, true);
2253                 tegra_hdmi_v2_x_host_config(hdmi, true);
2254         } else {
2255                 if (tegra_edid_is_scdc_present(dc->edid))
2256                         tegra_hdmi_v2_x_mon_config(hdmi, false);
2257                 tegra_hdmi_v2_x_host_config(hdmi, false);
2258         }
2259
2260         if (!(dc->mode.vmode & FB_VMODE_SET_YUV_MASK))
2261                 _tegra_dc_cmu_enable(dc,
2262                         dc->mode.vmode & FB_VMODE_LIMITED_RANGE);
2263
2264         tegra_dc_io_end(dc);
2265         tegra_hdmi_put(dc);
2266 }
2267
2268 #ifdef CONFIG_DEBUG_FS
2269 /* show current hpd state */
2270 static int tegra_hdmi_hotplug_dbg_show(struct seq_file *m, void *unused)
2271 {
2272         struct tegra_hdmi *hdmi = m->private;
2273         struct tegra_dc *dc = hdmi->dc;
2274
2275         if (WARN_ON(!hdmi || !dc || !dc->out))
2276                 return -EINVAL;
2277
2278         rmb();
2279         seq_printf(m, "hdmi hpd state: %d\n", dc->out->hotplug_state);
2280
2281         return 0;
2282 }
2283
2284 int tegra_hdmi_get_hotplug_state(struct tegra_hdmi *hdmi)
2285 {
2286         rmb();
2287         return hdmi->dc->out->hotplug_state;
2288 }
2289
2290 void tegra_hdmi_set_hotplug_state(struct tegra_hdmi *hdmi, int new_hpd_state)
2291 {
2292         struct tegra_dc *dc = hdmi->dc;
2293         int hotplug_state;
2294
2295         rmb();
2296         hotplug_state = dc->out->hotplug_state;
2297
2298         if (hotplug_state == TEGRA_HPD_STATE_NORMAL &&
2299                         new_hpd_state != TEGRA_HPD_STATE_NORMAL &&
2300                         tegra_dc_hotplug_supported(dc)) {
2301                 disable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2302         } else if (hotplug_state != TEGRA_HPD_STATE_NORMAL &&
2303                         new_hpd_state == TEGRA_HPD_STATE_NORMAL &&
2304                         tegra_dc_hotplug_supported(dc)) {
2305                 enable_irq(gpio_to_irq(dc->out->hotplug_gpio));
2306         }
2307
2308         dc->out->hotplug_state = new_hpd_state;
2309         wmb();
2310
2311         /*
2312          * sw controlled plug/unplug.
2313          * wait for any already executing hpd worker thread.
2314          * No debounce delay, schedule immedately
2315          */
2316         cancel_delayed_work_sync(&hdmi->hpd_worker);
2317         schedule_delayed_work(&hdmi->hpd_worker, 0);
2318 }
2319
2320 /*
2321  * sw control for hpd.
2322  * 0 is normal state, hw drives hpd.
2323  * -1 is force deassert, sw drives hpd.
2324  * 1 is force assert, sw drives hpd.
2325  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
2326  */
2327 static ssize_t tegra_hdmi_hotplug_dbg_write(struct file *file,
2328                                         const char __user *addr,
2329                                         size_t len, loff_t *pos)
2330 {
2331         struct seq_file *m = file->private_data;
2332         struct tegra_hdmi *hdmi = m->private;
2333         struct tegra_dc *dc = hdmi->dc;
2334         long new_hpd_state;
2335         int ret;
2336
2337         if (WARN_ON(!hdmi || !dc || !dc->out))
2338                 return -EINVAL;
2339
2340         ret = kstrtol_from_user(addr, len, 10, &new_hpd_state);
2341         if (ret < 0)
2342                 return ret;
2343
2344         tegra_hdmi_set_hotplug_state(hdmi, new_hpd_state);
2345
2346         return len;
2347 }
2348
2349 static int tegra_hdmi_hotplug_dbg_open(struct inode *inode, struct file *file)
2350 {
2351         return single_open(file, tegra_hdmi_hotplug_dbg_show, inode->i_private);
2352 }
2353
2354 static const struct file_operations tegra_hdmi_hotplug_dbg_ops = {
2355         .open = tegra_hdmi_hotplug_dbg_open,
2356         .read = seq_read,
2357         .write = tegra_hdmi_hotplug_dbg_write,
2358         .llseek = seq_lseek,
2359         .release = single_release,
2360 };
2361
2362 static int tegra_hdmi_status_dbg_show(struct seq_file *m, void *unused)
2363 {
2364         struct tegra_hdmi *hdmi = m->private;
2365         struct tegra_dc *dc;
2366
2367         if (WARN_ON(!hdmi))
2368                 return -EINVAL;
2369
2370         dc = hdmi->dc;
2371
2372         if (WARN_ON(!dc || !dc->out))
2373                 return -EINVAL;
2374
2375         seq_printf(m, "hotplug state: %d\n", tegra_dc_hpd(dc));
2376         seq_printf(m, "SCDC present: %d\n",
2377                 tegra_edid_is_scdc_present(hdmi->edid));
2378         seq_printf(m, "Forum VSDB present: %d\n",
2379                 tegra_edid_is_hfvsdb_present(hdmi->edid));
2380         seq_printf(m, "YCbCr4:2:0 VDB present: %d\n",
2381                 tegra_edid_is_420db_present(hdmi->edid));
2382
2383         return 0;
2384 }
2385
2386 static int tegra_hdmi_status_dbg_open(struct inode *inode, struct file *file)
2387 {
2388         return single_open(file, tegra_hdmi_status_dbg_show,
2389                 inode->i_private);
2390 }
2391
2392 static const struct file_operations tegra_hdmi_status_dbg_ops = {
2393         .open = tegra_hdmi_status_dbg_open,
2394         .read = seq_read,
2395         .release = single_release,
2396 };
2397
2398 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2399 {
2400         struct dentry *dir, *ret;
2401
2402         dir = debugfs_create_dir("tegra_hdmi",  NULL);
2403         if (IS_ERR_OR_NULL(dir))
2404                 return;
2405
2406         ret = debugfs_create_file("hotplug", S_IRUGO, dir,
2407                                 hdmi, &tegra_hdmi_hotplug_dbg_ops);
2408         if (IS_ERR_OR_NULL(ret))
2409                 goto fail;
2410         ret = debugfs_create_file("hdmi_status", S_IRUGO, dir,
2411                                 hdmi, &tegra_hdmi_status_dbg_ops);
2412         if (IS_ERR_OR_NULL(ret))
2413                 goto fail;
2414         return;
2415 fail:
2416         debugfs_remove_recursive(dir);
2417         return;
2418 }
2419 #else
2420 static void tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi)
2421 {
2422         return;
2423 }
2424 #endif
2425
2426 static ssize_t hdmi_ddc_power_toggle(struct kobject *kobj,
2427                 struct kobj_attribute *attr, const char *buf, size_t count)
2428 {
2429         int value;
2430         sscanf(buf, "%du", &value);
2431         tegra_hdmi_ddc_power_toggle(value);
2432         return count;
2433 }
2434
2435 static ssize_t hdmi_ddc_power_show(struct kobject *kobj,
2436                 struct kobj_attribute *attr, char *buf)
2437 {
2438         return sprintf(buf, "%d\n", dc_hdmi->ddc_refcount);
2439 }
2440
2441 static bool tegra_dc_hdmi_hpd_state(struct tegra_dc *dc)
2442 {
2443         int sense;
2444         int level;
2445         bool hpd;
2446
2447         if (WARN_ON(!dc || !dc->out))
2448                 return false;
2449
2450         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
2451
2452         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
2453
2454         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
2455                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
2456
2457         return hpd;
2458 }
2459
2460 static void tegra_dc_hdmi_vrr_enable(struct tegra_dc *dc, bool enable)
2461 {
2462         struct tegra_vrr *vrr  = dc->out->vrr;
2463
2464         if (!vrr)
2465                 return;
2466
2467         if (!(dc->mode.vmode & FB_VMODE_VRR)) {
2468                 WARN(enable, "VRR enable request in non-VRR mode\n");
2469                 return;
2470         }
2471
2472         vrr->enable = enable;
2473 }
2474
2475 static void tegra_dc_hdmi_postpoweron(struct tegra_dc *dc)
2476 {
2477         _tegra_hdmivrr_activate(tegra_dc_get_outdata(dc), true);
2478 }
2479
2480 static void tegra_dc_hdmi_sor_sleep(struct tegra_dc *dc)
2481 {
2482         struct tegra_hdmi *hdmi = tegra_dc_get_outdata(dc);
2483
2484         if (hdmi->sor->sor_state == SOR_ATTACHED)
2485                 tegra_dc_sor_sleep(hdmi->sor);
2486 }
2487
2488 struct tegra_dc_out_ops tegra_dc_hdmi2_0_ops = {
2489         .init = tegra_dc_hdmi_init,
2490         .destroy = tegra_dc_hdmi_destroy,
2491         .enable = tegra_dc_hdmi_enable,
2492         .disable = tegra_dc_hdmi_disable,
2493         .setup_clk = tegra_dc_hdmi_setup_clk,
2494         .detect = tegra_dc_hdmi_detect,
2495         .shutdown = tegra_dc_hdmi_shutdown,
2496         .suspend = tegra_dc_hdmi_suspend,
2497         .resume = tegra_dc_hdmi_resume,
2498         .ddc_enable = tegra_dc_hdmi_ddc_enable,
2499         .ddc_disable = tegra_dc_hdmi_ddc_disable,
2500         .modeset_notifier = tegra_dc_hdmi_modeset_notifier,
2501         .mode_filter = tegra_hdmi_fb_mode_filter,
2502         .hpd_state = tegra_dc_hdmi_hpd_state,
2503         .vrr_enable = tegra_dc_hdmi_vrr_enable,
2504         .vrr_update_monspecs = tegra_hdmivrr_update_monspecs,
2505         .set_hdr = tegra_dc_hdmi_set_hdr,
2506         .postpoweron = tegra_dc_hdmi_postpoweron,
2507         .shutdown_interface = tegra_dc_hdmi_sor_sleep,
2508 };