video: tegra: dc: Add new blender support
[linux-3.10.git] / drivers / video / tegra / dc / hdmi.c
1 /*
2  * drivers/video/tegra/dc/hdmi.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2013, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/clk.h>
21 #include <linux/delay.h>
22 #include <linux/err.h>
23 #include <linux/fb.h>
24 #include <linux/gpio.h>
25 #include <linux/interrupt.h>
26 #include <linux/kernel.h>
27 #include <linux/slab.h>
28 #include <linux/mutex.h>
29 #ifdef CONFIG_SWITCH
30 #include <linux/switch.h>
31 #endif
32 #include <linux/workqueue.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/device.h>
36 #include <linux/export.h>
37
38 #include <mach/clk.h>
39 #include <mach/dc.h>
40 #include <mach/fb.h>
41 #include <linux/nvhost.h>
42 #include <mach/hdmi-audio.h>
43
44 #include <video/tegrafb.h>
45
46 #include "dc_reg.h"
47 #include "dc_priv.h"
48 #include "hdmi_reg.h"
49 #include "hdmi.h"
50 #include "edid.h"
51 #include "nvhdcp.h"
52
53 /* datasheet claims this will always be 216MHz */
54 #define HDMI_AUDIOCLK_FREQ              216000000
55
56 #define HDMI_REKEY_DEFAULT              56
57
58 #define HDMI_ELD_RESERVED1_INDEX                1
59 #define HDMI_ELD_RESERVED2_INDEX                3
60 #define HDMI_ELD_VER_INDEX                      0
61 #define HDMI_ELD_BASELINE_LEN_INDEX             2
62 #define HDMI_ELD_CEA_VER_MNL_INDEX              4
63 #define HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX         5
64 #define HDMI_ELD_AUD_SYNC_DELAY_INDEX   6
65 #define HDMI_ELD_SPK_ALLOC_INDEX                7
66 #define HDMI_ELD_PORT_ID_INDEX          8
67 #define HDMI_ELD_MANF_NAME_INDEX                16
68 #define HDMI_ELD_PRODUCT_CODE_INDEX             18
69 #define HDMI_ELD_MONITOR_NAME_INDEX             20
70
71 /* These two values need to be cross checked in case of
72      addition/removal from tegra_dc_hdmi_aspect_ratios[] */
73 #define TEGRA_DC_HDMI_MIN_ASPECT_RATIO_PERCENT  80
74 #define TEGRA_DC_HDMI_MAX_ASPECT_RATIO_PERCENT  320
75
76 struct tegra_dc_hdmi_data {
77         struct tegra_dc                 *dc;
78         struct tegra_edid               *edid;
79         struct tegra_edid_hdmi_eld              eld;
80         struct tegra_nvhdcp             *nvhdcp;
81         struct delayed_work             work;
82
83         struct resource                 *base_res;
84         void __iomem                    *base;
85         struct clk                      *clk;
86
87         struct clk                      *disp1_clk;
88         struct clk                      *disp2_clk;
89         struct clk                      *hda_clk;
90         struct clk                      *hda2codec_clk;
91         struct clk                      *hda2hdmi_clk;
92
93 #ifdef CONFIG_SWITCH
94         struct switch_dev               hpd_switch;
95 #endif
96         struct tegra_hdmi_out           info;
97
98         struct rt_mutex                 suspend_lock;
99         bool                            suspended;
100         bool                            eld_retrieved;
101         bool                            clk_enabled;
102         unsigned                        audio_freq;
103         unsigned                        audio_source;
104         bool                            audio_inject_null;
105
106         bool                            dvi;
107 };
108
109 struct tegra_dc_hdmi_data *dc_hdmi;
110
111 #if defined(CONFIG_ARCH_TEGRA_3x_SOC)
112 const struct tmds_config tmds_config[] = {
113         { /* 480p modes */
114         .pclk = 27000000,
115         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
116                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
117                 SOR_PLL_TX_REG_LOAD(0),
118         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
119         .pe_current = 0x00000000,
120         .drive_current = 0x0a0a0a0a,
121         },
122         { /* 720p modes */
123         .pclk = 74250000,
124         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
125                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
126                 SOR_PLL_TX_REG_LOAD(0),
127         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
128         .pe_current = 0x0a0a0a0a,
129         .drive_current = 0x0a0a0a0a,
130         },
131         { /* 1080p modes */
132         .pclk = INT_MAX,
133         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
134                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(3) |
135                 SOR_PLL_TX_REG_LOAD(0),
136         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
137         .pe_current = 0x0a0a0a0a,
138         .drive_current = 0x0a0a0a0a,
139         },
140 };
141 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC)
142 const struct tmds_config tmds_config[] = {
143         { /* 480p modes */
144         .pclk = 27000000,
145         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
146                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(0) |
147                 SOR_PLL_TX_REG_LOAD(3),
148         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
149         .pe_current = 0x00000000,
150         .drive_current = 0x0f0f0f0f,
151         },
152         { /* 720p modes */
153         .pclk = 74250000,
154         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
156                 SOR_PLL_TX_REG_LOAD(3),
157         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
158         .pe_current = 0x0c0c0c0c,
159         .drive_current = 0x0f0f0f0f,
160         },
161         { /* 1080p modes */
162         .pclk = INT_MAX,
163         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
164                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(1) |
165                 SOR_PLL_TX_REG_LOAD(3),
166         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
167         .pe_current = 0x0c0c0c0c,
168         .drive_current = 0x0f0f0f0f,
169         },
170 };
171 #elif defined(CONFIG_ARCH_TEGRA_11x_SOC)
172 const struct tmds_config tmds_config[] = {
173         { /* 480p/576p / 25.2MHz/27MHz modes */
174         .pclk = 27000000,
175         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
176                 SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL_EXT,
177         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
178         .pe_current = 0x00000000,
179         .drive_current = 0x1a1a1a1a,
180         .peak_current = 0x00000000,
181         },
182         { /* 720p / 74.25MHz modes */
183         .pclk = 74250000,
184         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
185                 SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL_EXT,
186         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
187         .pe_current = 0x0f0f0f0f,
188         .drive_current = 0x1a1a1a1a,
189         .peak_current = 0x00000000,
190         },
191         { /* 1080p / 148.5MHz modes */
192         .pclk = 148500000,
193         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
194                 SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL_EXT,
195         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
196         .pe_current = 0x0a0a0a0a,
197         .drive_current = 0x1f1f1f1f,
198         .peak_current = 0x00000000,
199         },
200         { /* 225/297MHz modes */
201         .pclk = INT_MAX,
202         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
203                 SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL_EXT,
204         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
205                 | SOR_PLL_TMDS_TERM_ENABLE,
206         .pe_current = 0x00000000,
207         .drive_current = 0x303f3f3f, /* lane3 needs a slightly lower current */
208         .peak_current = 0x040f0f0f,
209         /* Alternative settings:
210         .drive_current = 0x2c333333,
211         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(6)
212                 | SOR_PLL_TMDS_TERM_ENABLE,
213         */
214         },
215 };
216 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
217 const struct tmds_config tmds_config[] = {
218         /* TODO: 480p modes */
219         /* TODO: 720p modes */
220         { /* 1080p modes */
221         .pclk = INT_MAX,
222         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
223                 SOR_PLL_RESISTORSEL_EXT | SOR_PLL_VCOCAP(3) |
224                 SOR_PLL_TX_REG_LOAD(0),
225         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN |
226                 SOR_PLL_TMDS_TERMADJ(0x6),
227         .pe_current = 0x08080808,
228         .drive_current = 0x18181818,
229         },
230 };
231 #else
232 #warning tmds_config needs to be defined for your arch
233 #endif
234
235 struct tegra_hdmi_audio_config {
236         unsigned pix_clock;
237         unsigned n;
238         unsigned cts;
239         unsigned aval;
240 };
241
242
243 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
244         {25200000,      4096,   25200,  24000},
245         {27000000,      4096,   27000,  24000},
246         {74250000,      4096,   74250,  24000},
247         {148500000,     4096,   148500, 24000},
248         {297000000,     3072,   222750, 24000},
249         {0,             0,      0},
250 };
251
252 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
253         {25200000,      5880,   26250,  25000},
254         {27000000,      5880,   28125,  25000},
255         {74250000,      4704,   61875,  20000},
256         {148500000,     4704,   123750, 20000},
257         {297000000,     4704,   247500, 20000},
258         {0,             0,      0},
259 };
260
261 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
262         {25200000,      6144,   25200,  24000},
263         {27000000,      6144,   27000,  24000},
264         {74250000,      6144,   74250,  24000},
265         {148500000,     6144,   148500, 24000},
266         {297000000,     5120,   247500, 24000},
267         {0,             0,      0},
268 };
269
270 const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
271         {25200000,      11760,  26250,  25000},
272         {27000000,      11760,  28125,  25000},
273         {74250000,      9408,   61875,  20000},
274         {148500000,     9408,   123750, 20000},
275         {297000000,     9408,   247500, 20000},
276         {0,             0,      0},
277 };
278
279 const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
280         {25200000,      12288,  25200,  24000},
281         {27000000,      12288,  27000,  24000},
282         {74250000,      12288,  74250,  24000},
283         {148500000,     12288,  148500, 24000},
284         {297000000,     10240,  247500, 24000},
285         {0,             0,      0},
286 };
287
288 const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
289         {25200000,      23520,  26250,  25000},
290         {27000000,      23520,  28125,  25000},
291         {74250000,      18816,  61875,  20000},
292         {148500000,     18816,  123750, 20000},
293         {297000000,     18816,  247500, 20000},
294         {0,             0,      0},
295 };
296
297 const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
298         {25200000,      24576,  25200,  24000},
299         {27000000,      24576,  27000,  24000},
300         {74250000,      24576,  74250,  24000},
301         {148500000,     24576,  148500, 24000},
302         {297000000,     20480,  247500, 24000},
303         {0,             0,      0},
304 };
305
306 static const struct tegra_hdmi_audio_config
307 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
308 {
309         const struct tegra_hdmi_audio_config *table;
310
311         switch (audio_freq) {
312         case AUDIO_FREQ_32K:
313                 table = tegra_hdmi_audio_32k;
314                 break;
315         case AUDIO_FREQ_44_1K:
316                 table = tegra_hdmi_audio_44_1k;
317                 break;
318         case AUDIO_FREQ_48K:
319                 table = tegra_hdmi_audio_48k;
320                 break;
321         case AUDIO_FREQ_88_2K:
322                 table = tegra_hdmi_audio_88_2k;
323                 break;
324         case AUDIO_FREQ_96K:
325                 table = tegra_hdmi_audio_96k;
326                 break;
327         case AUDIO_FREQ_176_4K:
328                 table = tegra_hdmi_audio_176_4k;
329                 break;
330         case AUDIO_FREQ_192K:
331                 table = tegra_hdmi_audio_192k;
332                 break;
333         default:
334                 return NULL;
335         }
336
337         while (table->pix_clock) {
338                 if (table->pix_clock == pix_clock)
339                         return table;
340                 table++;
341         }
342
343         return NULL;
344 }
345
346
347 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
348                                              unsigned long reg)
349 {
350         unsigned long ret;
351         ret = readl(hdmi->base + reg * 4);
352         trace_display_readl(hdmi->dc, ret, hdmi->base + reg * 4);
353         return ret;
354 }
355
356 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
357                                      unsigned long val, unsigned long reg)
358 {
359         trace_display_writel(hdmi->dc, val, hdmi->base + reg * 4);
360         writel(val, hdmi->base + reg * 4);
361 }
362
363 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
364                                          unsigned long reg, unsigned long clr,
365                                          unsigned long set)
366 {
367         unsigned long val = tegra_hdmi_readl(hdmi, reg);
368         val &= ~clr;
369         val |= set;
370         tegra_hdmi_writel(hdmi, val, reg);
371 }
372
373 #ifdef CONFIG_DEBUG_FS
374 static int dbg_hdmi_show(struct seq_file *m, void *unused)
375 {
376         struct tegra_dc_hdmi_data *hdmi = m->private;
377
378 #define DUMP_REG(a) do {                                                \
379                 seq_printf(m, "%-32s\t%03x\t%08lx\n",                   \
380                        #a, a, tegra_hdmi_readl(hdmi, a));               \
381         } while (0)
382
383         tegra_dc_io_start(hdmi->dc);
384         clk_prepare_enable(hdmi->clk);
385
386         DUMP_REG(HDMI_CTXSW);
387         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
388         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
389         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
390         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
391         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
392         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
393         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
394         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
395         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
396         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
397         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
398         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
399         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
400         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
401         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
402         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
403         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
404         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
405         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
406         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
407         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
408         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
409         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
410         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
411         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
412         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
413         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
414         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
415         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
416         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
417         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
418         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
419         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
420         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
421         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
422         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
423         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
424         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
425         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
426         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
427         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
428         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
429         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
430         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
431         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
432         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
433         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
434         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
435         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
436         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
437         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
438         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
439         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
440         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
441         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
442         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
443         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
444         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
445         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
446         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
447         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
448         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
449         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
450         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
451         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
452         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
453         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
454         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
455         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
456         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
457         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
458         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
459         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
460         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
461         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
462         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
463         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
464         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
465         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
466         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
467         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
468         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
469         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
470         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
471         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
472         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
473         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
474         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
475         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
476         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
477         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
478         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
479         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
480         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
481         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
482         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
483         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
484         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
485         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
486         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
487         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
488         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
489         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
490         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
491         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
492         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
493         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
494         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
495         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
496         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
497         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
498         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
499         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
500         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
501         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
502         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
503         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
504         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
505         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
506         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
507         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
508         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
509         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
510         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
511         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
512         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
513         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
514         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
515         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
516         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
517         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
518         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
519         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
520         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
521         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
522         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
523         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
524         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
525         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
526         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
527         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
528         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
529         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
530         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
531         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
532         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
533         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
534         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
535         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
536         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
537         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
538         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
539         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
540 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
541         DUMP_REG(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
542 #endif
543 #undef DUMP_REG
544
545         clk_disable_unprepare(hdmi->clk);
546         tegra_dc_io_end(hdmi->dc);
547
548         return 0;
549 }
550
551 static int dbg_hdmi_show_open(struct inode *inode, struct file *file)
552 {
553         return single_open(file, dbg_hdmi_show, inode->i_private);
554 }
555
556 static const struct file_operations dbg_hdmi_show_fops = {
557         .open           = dbg_hdmi_show_open,
558         .read           = seq_read,
559         .llseek         = seq_lseek,
560         .release        = single_release,
561 };
562
563 static int dbg_hotplug_show(struct seq_file *m, void *unused)
564 {
565         struct tegra_dc_hdmi_data *hdmi = m->private;
566         struct tegra_dc *dc = hdmi->dc;
567
568         if (WARN_ON(!hdmi || !dc || !dc->out))
569                 return -EINVAL;
570
571         seq_put_decimal_ll(m, '\0', dc->out->hotplug_state);
572         seq_putc(m, '\n');
573         return 0;
574 }
575
576 static int dbg_hotplug_open(struct inode *inode, struct file *file)
577 {
578         return single_open(file, dbg_hotplug_show, inode->i_private);
579 }
580
581 static int dbg_hotplug_write(struct file *file, const char __user *addr,
582         size_t len, loff_t *pos)
583 {
584         struct seq_file *m = file->private_data; /* single_open() initialized */
585         struct tegra_dc_hdmi_data *hdmi = m->private;
586         struct tegra_dc *dc = hdmi->dc;
587         int ret;
588         long new_state;
589
590         if (WARN_ON(!hdmi || !dc || !dc->out))
591                 return -EINVAL;
592
593         ret = kstrtol_from_user(addr, len, 10, &new_state);
594         if (ret < 0)
595                 return ret;
596
597         if (dc->out->hotplug_state == 0 && new_state != 0) {
598                 /* was 0, now -1 or 1.
599                  * we are overriding the hpd GPIO, so ignore the interrupt. */
600                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
601
602                 disable_irq(gpio_irq);
603         } else if (dc->out->hotplug_state != 0 && new_state == 0) {
604                 /* was -1 or 1, and now 0
605                  * restore the interrupt for hpd GPIO. */
606                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
607
608                 enable_irq(gpio_irq);
609         }
610
611         dc->out->hotplug_state = new_state;
612
613         queue_delayed_work(system_nrt_wq, &hdmi->work,
614                 msecs_to_jiffies(100));
615
616         return len;
617 }
618
619 static const struct file_operations dbg_hotplug_fops = {
620         .open           = dbg_hotplug_open,
621         .read           = seq_read,
622         .write          = dbg_hotplug_write,
623         .llseek         = seq_lseek,
624         .release        = single_release,
625 };
626
627 static struct dentry *hdmidir;
628
629 static void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
630 {
631         struct dentry *retval;
632
633         hdmidir = debugfs_create_dir("tegra_hdmi", NULL);
634         if (!hdmidir)
635                 return;
636         retval = debugfs_create_file("regs", S_IRUGO, hdmidir, hdmi,
637                 &dbg_hdmi_show_fops);
638         if (!retval)
639                 goto free_out;
640         retval = debugfs_create_file("hotplug", S_IRUGO, hdmidir, hdmi,
641                 &dbg_hotplug_fops);
642         if (!retval)
643                 goto free_out;
644         return;
645 free_out:
646         debugfs_remove_recursive(hdmidir);
647         hdmidir = NULL;
648         return;
649 }
650 #else
651 static inline void tegra_dc_hdmi_debug_create(struct tegra_dc_hdmi_data *hdmi)
652 { }
653 #endif
654
655 #define PIXCLOCK_TOLERANCE      200
656
657 static int tegra_dc_calc_clock_per_frame(const struct fb_videomode *mode)
658 {
659         return (mode->left_margin + mode->xres +
660                 mode->right_margin + mode->hsync_len) *
661                (mode->upper_margin + mode->yres +
662                 mode->lower_margin + mode->vsync_len);
663 }
664
665 static bool tegra_dc_hdmi_valid_pixclock(const struct tegra_dc *dc,
666                                         const struct fb_videomode *mode)
667 {
668         unsigned max_pixclock = tegra_dc_get_out_max_pixclock(dc);
669         if (max_pixclock) {
670                 /* this might look counter-intuitive,
671                  * but pixclock's unit is picos(not Khz)
672                  */
673                 return mode->pixclock >= max_pixclock;
674         } else {
675                 return true;
676         }
677 }
678
679 static bool tegra_dc_check_constraint(const struct fb_videomode *mode)
680 {
681         return mode->hsync_len > 1 && mode->vsync_len > 1 &&
682                 mode->lower_margin + mode->vsync_len + mode->upper_margin > 1 &&
683                 mode->xres >= 16 && mode->yres >= 16;
684 }
685
686 /* adjusts pixclock to fit audio table */
687 static bool tegra_dc_hdmi_adjust_pixclock(const struct tegra_dc *dc,
688                                         struct fb_videomode *mode)
689 {
690         const struct tegra_hdmi_audio_config *cfg = tegra_hdmi_audio_44_1k;
691         unsigned pclk;
692
693         if (!mode->pixclock)
694                 return false;
695
696         pclk = PICOS2KHZ(mode->pixclock) * 1000;
697
698         /* look on 44.1k audio table, if mode's pixel clock is within 1%, then
699          * use the pixel clock from the audio table.*/
700         while (cfg->pix_clock) {
701                 if (cfg->pix_clock > (pclk / 100 * 99) &&
702                         cfg->pix_clock < (pclk / 100 * 101) &&
703                         cfg->pix_clock >= 1000) {
704                         mode->pixclock = KHZ2PICOS(cfg->pix_clock / 1000);
705                         return true;
706                 }
707                 cfg++;
708         }
709         return false;
710 }
711
712 static bool tegra_dc_hdmi_mode_filter(const struct tegra_dc *dc,
713                                         struct fb_videomode *mode)
714 {
715         if (mode->vmode & FB_VMODE_INTERLACED)
716                 return false;
717
718         /* Ignore modes with a 0 pixel clock */
719         if (!mode->pixclock)
720                 return false;
721
722 #ifdef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
723                 if (PICOS2KHZ(mode->pixclock) > 74250)
724                         return false;
725 #endif
726
727 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
728         /* Display B max is 4096 */
729         if (mode->xres > 4096)
730                 return false;
731 #elif defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
732         if (mode->xres > 2560)
733                 return false;
734 #else
735         /* don't filter any modes due to width - probably not what you want */
736 #endif
737
738         tegra_dc_hdmi_adjust_pixclock(dc, mode);
739
740         /* Check if the mode's pixel clock is more than the max rate*/
741         if (!tegra_dc_hdmi_valid_pixclock(dc, mode))
742                 return false;
743
744         /* Work around for modes that fail the constrait:
745          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1 */
746         if (mode->lower_margin == 1) {
747                 mode->lower_margin++;
748                 mode->upper_margin--;
749         }
750
751         /* even after fix-ups the mode still isn't supported */
752         if (!tegra_dc_check_constraint(mode))
753                 return false;
754
755         mode->flag |= FB_MODE_IS_DETAILED;
756         mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) /
757                                 tegra_dc_calc_clock_per_frame(mode);
758         return true;
759 }
760
761 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
762 {
763         return tegra_dc_hpd(dc);
764 }
765
766
767 void tegra_dc_hdmi_detect_config(struct tegra_dc *dc,
768                                                 struct fb_monspecs *specs)
769 {
770         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
771
772         /* monitors like to lie about these but they are still useful for
773          * detecting aspect ratios
774          */
775         dc->out->h_size = specs->max_x * 1000;
776         dc->out->v_size = specs->max_y * 1000;
777
778         hdmi->dvi = !(specs->misc & FB_MISC_HDMI);
779
780         tegra_fb_update_monspecs(dc->fb, specs, tegra_dc_hdmi_mode_filter);
781 #ifdef CONFIG_SWITCH
782         hdmi->hpd_switch.state = 0;
783         switch_set_state(&hdmi->hpd_switch, 1);
784 #endif
785         dev_info(&dc->ndev->dev, "display detected\n");
786
787         dc->connected = true;
788         tegra_dc_ext_process_hotplug(dc->ndev->id);
789 }
790
791 /* This function is used to enable DC1 and HDMI for the purpose of testing. */
792 bool tegra_dc_hdmi_detect_test(struct tegra_dc *dc, unsigned char *edid_ptr)
793 {
794         int err;
795         struct fb_monspecs specs;
796         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
797
798         if (!hdmi || !edid_ptr) {
799                 dev_err(&dc->ndev->dev, "HDMI test failed to get arguments.\n");
800                 return false;
801         }
802
803         err = tegra_edid_get_monspecs_test(hdmi->edid, &specs, edid_ptr);
804         if (err < 0) {
805                 /* Check if there's a hard-wired mode, if so, enable it */
806                 if (dc->out->n_modes)
807                         tegra_dc_enable(dc);
808                 else {
809                         dev_err(&dc->ndev->dev, "error reading edid\n");
810                         goto fail;
811                 }
812 #ifdef CONFIG_SWITCH
813                 hdmi->hpd_switch.state = 0;
814                 switch_set_state(&hdmi->hpd_switch, 1);
815 #endif
816                 dev_info(&dc->ndev->dev, "display detected\n");
817
818                 dc->connected = true;
819                 tegra_dc_ext_process_hotplug(dc->ndev->id);
820         } else {
821                 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
822                 if (err < 0) {
823                         dev_err(&dc->ndev->dev, "error populating eld\n");
824                         goto fail;
825                 }
826                 hdmi->eld_retrieved = true;
827
828                 tegra_dc_hdmi_detect_config(dc, &specs);
829         }
830
831         return true;
832
833 fail:
834         hdmi->eld_retrieved = false;
835 #ifdef CONFIG_SWITCH
836         switch_set_state(&hdmi->hpd_switch, 0);
837 #endif
838         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
839         return false;
840 }
841 EXPORT_SYMBOL(tegra_dc_hdmi_detect_test);
842
843 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
844 {
845         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
846         struct fb_monspecs specs;
847         int err;
848
849         mutex_lock(&dc->lock);
850
851         if (!tegra_dc_hdmi_hpd(dc))
852                 goto fail;
853
854         if (dc->connected)
855                 goto success;
856
857         err = tegra_edid_get_monspecs(hdmi->edid, &specs);
858         if (err < 0) {
859                 if (dc->out->n_modes)
860                         tegra_dc_enable(dc);
861                 else {
862                         dev_err(&dc->ndev->dev, "error reading edid\n");
863                         goto fail;
864                 }
865 #ifdef CONFIG_SWITCH
866                 hdmi->hpd_switch.state = 0;
867                 switch_set_state(&hdmi->hpd_switch, 1);
868 #endif
869                 dev_info(&dc->ndev->dev, "display detected\n");
870
871                 dc->connected = true;
872                 tegra_dc_ext_process_hotplug(dc->ndev->id);
873         } else {
874                 err = tegra_edid_get_eld(hdmi->edid, &hdmi->eld);
875                 if (err < 0) {
876                         dev_err(&dc->ndev->dev, "error populating eld\n");
877                         goto fail;
878                 }
879                 hdmi->eld_retrieved = true;
880
881                 tegra_dc_hdmi_detect_config(dc, &specs);
882         }
883
884 success:
885         mutex_unlock(&dc->lock);
886
887         return true;
888
889 fail:
890         mutex_unlock(&dc->lock);
891
892         hdmi->eld_retrieved = false;
893 #ifdef CONFIG_SWITCH
894         switch_set_state(&hdmi->hpd_switch, 0);
895 #endif
896         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
897         return false;
898 }
899
900
901 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
902 {
903         struct tegra_dc_hdmi_data *hdmi =
904                 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
905         struct tegra_dc *dc = hdmi->dc;
906
907 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
908         /* Set default videomode on dc before enabling it*/
909         tegra_dc_set_default_videomode(dc);
910 #endif
911         if (!tegra_dc_hdmi_detect(dc) && dc->connected) {
912                 dev_dbg(&dc->ndev->dev, "HDMI disconnect\n");
913                 dc->connected = false;
914                 tegra_dc_disable(dc);
915
916                 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
917
918                 tegra_dc_ext_process_hotplug(dc->ndev->id);
919         }
920 }
921
922 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
923 {
924         struct tegra_dc *dc = ptr;
925         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
926
927         rt_mutex_lock(&hdmi->suspend_lock);
928
929         if (!hdmi->suspended) {
930                 cancel_delayed_work(&hdmi->work);
931                 queue_delayed_work(system_nrt_wq, &hdmi->work,
932                                    msecs_to_jiffies(100));
933         }
934
935         rt_mutex_unlock(&hdmi->suspend_lock);
936         return IRQ_HANDLED;
937 }
938
939 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
940 {
941         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
942
943         tegra_nvhdcp_suspend(hdmi->nvhdcp);
944         rt_mutex_lock(&hdmi->suspend_lock);
945         hdmi->suspended = true;
946         rt_mutex_unlock(&hdmi->suspend_lock);
947
948 }
949
950 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
951 {
952         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
953         bool hpd = tegra_dc_hdmi_hpd(dc);
954
955         rt_mutex_lock(&hdmi->suspend_lock);
956         hdmi->suspended = false;
957
958         queue_delayed_work(system_nrt_wq, &hdmi->work,
959                            msecs_to_jiffies(hpd ? 100 : 30));
960
961         rt_mutex_unlock(&hdmi->suspend_lock);
962
963         tegra_nvhdcp_resume(hdmi->nvhdcp);
964 }
965
966 #ifdef CONFIG_SWITCH
967 static ssize_t underscan_show(struct device *dev,
968                                 struct device_attribute *attr, char *buf)
969 {
970         struct tegra_dc_hdmi_data *hdmi =
971                         container_of(dev_get_drvdata(dev), struct tegra_dc_hdmi_data, hpd_switch);
972
973         if (hdmi->edid)
974                 return sprintf(buf, "%d\n", tegra_edid_underscan_supported(hdmi->edid));
975         else
976                 return 0;
977 }
978
979 static DEVICE_ATTR(underscan, S_IRUGO | S_IWUSR, underscan_show, NULL);
980 #endif
981
982 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
983 {
984         struct tegra_dc_hdmi_data *hdmi;
985         struct resource *res;
986         struct resource *base_res;
987 #ifdef CONFIG_SWITCH
988         int ret;
989 #endif
990         void __iomem *base;
991         struct clk *clk = NULL;
992         struct clk *disp1_clk = NULL;
993         struct clk *disp2_clk = NULL;
994         struct tegra_hdmi_out *hdmi_out = NULL;
995         int err;
996
997         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
998         if (!hdmi)
999                 return -ENOMEM;
1000
1001         res = platform_get_resource_byname(dc->ndev,
1002                 IORESOURCE_MEM, "hdmi_regs");
1003         if (!res) {
1004                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
1005                 err = -ENOENT;
1006                 goto err_free_hdmi;
1007         }
1008
1009         base_res = request_mem_region(res->start,
1010                 resource_size(res), dc->ndev->name);
1011         if (!base_res) {
1012                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
1013                 err = -EBUSY;
1014                 goto err_free_hdmi;
1015         }
1016
1017         base = ioremap(res->start, resource_size(res));
1018         if (!base) {
1019                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
1020                 err = -EBUSY;
1021                 goto err_release_resource_reg;
1022         }
1023
1024         clk = clk_get(&dc->ndev->dev, "hdmi");
1025         if (IS_ERR_OR_NULL(clk)) {
1026                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
1027                 err = -ENOENT;
1028                 goto err_iounmap_reg;
1029         }
1030
1031         disp1_clk = clk_get_sys("tegradc.0", NULL);
1032         if (IS_ERR_OR_NULL(disp1_clk)) {
1033                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
1034                 err = -ENOENT;
1035                 goto err_put_clock;
1036         }
1037
1038         disp2_clk = clk_get_sys("tegradc.1", NULL);
1039         if (IS_ERR_OR_NULL(disp2_clk)) {
1040                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
1041                 err = -ENOENT;
1042                 goto err_put_clock;
1043         }
1044
1045 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1046         hdmi->hda_clk = clk_get_sys("tegra30-hda", "hda");
1047         if (IS_ERR_OR_NULL(hdmi->hda_clk)) {
1048                 dev_err(&dc->ndev->dev, "hdmi: can't get hda clock\n");
1049                 err = -ENOENT;
1050                 goto err_put_clock;
1051         }
1052
1053         hdmi->hda2codec_clk = clk_get_sys("tegra30-hda", "hda2codec");
1054         if (IS_ERR_OR_NULL(hdmi->hda2codec_clk)) {
1055                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2codec clock\n");
1056                 err = -ENOENT;
1057                 goto err_put_clock;
1058         }
1059
1060         hdmi->hda2hdmi_clk = clk_get_sys("tegra30-hda", "hda2hdmi");
1061         if (IS_ERR_OR_NULL(hdmi->hda2hdmi_clk)) {
1062                 dev_err(&dc->ndev->dev, "hdmi: can't get hda2hdmi clock\n");
1063                 err = -ENOENT;
1064                 goto err_put_clock;
1065         }
1066 #endif
1067
1068         /* Get the pointer of board file settings */
1069         hdmi_out = dc->pdata->default_out->hdmi_out;
1070         if (hdmi_out)
1071                 memcpy(&hdmi->info, hdmi_out, sizeof(hdmi->info));
1072
1073         hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
1074         if (IS_ERR_OR_NULL(hdmi->edid)) {
1075                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
1076                 err = PTR_ERR(hdmi->edid);
1077                 goto err_put_clock;
1078         }
1079
1080 #ifdef CONFIG_TEGRA_NVHDCP
1081         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
1082                         dc->out->dcc_bus);
1083         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
1084                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
1085                 err = PTR_ERR(hdmi->nvhdcp);
1086                 goto err_edid_destroy;
1087         }
1088 #else
1089         hdmi->nvhdcp = NULL;
1090 #endif
1091
1092         INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
1093
1094         hdmi->dc = dc;
1095         hdmi->base = base;
1096         hdmi->base_res = base_res;
1097         hdmi->clk = clk;
1098         hdmi->disp1_clk = disp1_clk;
1099         hdmi->disp2_clk = disp2_clk;
1100         hdmi->suspended = false;
1101         hdmi->eld_retrieved= false;
1102         hdmi->clk_enabled = false;
1103         hdmi->audio_freq = 44100;
1104         hdmi->audio_source = AUTO;
1105         rt_mutex_init(&hdmi->suspend_lock);
1106
1107 #ifdef CONFIG_SWITCH
1108         hdmi->hpd_switch.name = "hdmi";
1109         ret = switch_dev_register(&hdmi->hpd_switch);
1110
1111         if (!ret)
1112                 ret = device_create_file(hdmi->hpd_switch.dev,
1113                         &dev_attr_underscan);
1114         BUG_ON(ret != 0);
1115 #endif
1116
1117         dc->out->depth = 24;
1118
1119         tegra_dc_set_outdata(dc, hdmi);
1120
1121         dc_hdmi = hdmi;
1122         /* boards can select default content protection policy */
1123         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND)
1124                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1125                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
1126         else
1127                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
1128                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
1129
1130         tegra_dc_hdmi_debug_create(hdmi);
1131
1132         err = gpio_request(dc->out->hotplug_gpio, "hdmi_hpd");
1133         if (err < 0) {
1134                 dev_err(&dc->ndev->dev, "hdmi: hpd gpio_request failed\n");
1135                 goto err_nvhdcp_destroy;
1136         }
1137
1138         gpio_direction_input(dc->out->hotplug_gpio);
1139
1140         /* TODO: support non-hotplug */
1141         ret = request_threaded_irq(gpio_to_irq(dc->out->hotplug_gpio),
1142                 NULL, tegra_dc_hdmi_irq,
1143                 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
1144                 dev_name(&dc->ndev->dev), dc);
1145
1146         if (ret) {
1147                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed - %d\n",
1148                         gpio_to_irq(dc->out->hotplug_gpio), ret);
1149                 err = -EBUSY;
1150                 goto err_gpio_free;
1151         }
1152
1153         return 0;
1154
1155 err_gpio_free:
1156         gpio_free(dc->out->hotplug_gpio);
1157 err_nvhdcp_destroy:
1158         if (hdmi->nvhdcp)
1159                 tegra_nvhdcp_destroy(hdmi->nvhdcp);
1160 #ifdef CONFIG_TEGRA_NVHDCP
1161 err_edid_destroy:
1162 #endif
1163         tegra_edid_destroy(hdmi->edid);
1164 err_put_clock:
1165 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1166         if (!IS_ERR_OR_NULL(hdmi->hda2hdmi_clk))
1167                 clk_put(hdmi->hda2hdmi_clk);
1168         if (!IS_ERR_OR_NULL(hdmi->hda2codec_clk))
1169                 clk_put(hdmi->hda2codec_clk);
1170         if (!IS_ERR_OR_NULL(hdmi->hda_clk))
1171                 clk_put(hdmi->hda_clk);
1172 #endif
1173         if (!IS_ERR_OR_NULL(disp2_clk))
1174                 clk_put(disp2_clk);
1175         if (!IS_ERR_OR_NULL(disp1_clk))
1176                 clk_put(disp1_clk);
1177         if (!IS_ERR_OR_NULL(clk))
1178                 clk_put(clk);
1179 err_iounmap_reg:
1180         iounmap(base);
1181 err_release_resource_reg:
1182         release_resource(base_res);
1183 err_free_hdmi:
1184         kfree(hdmi);
1185         return err;
1186 }
1187
1188 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
1189 {
1190         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1191
1192         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
1193         cancel_delayed_work_sync(&hdmi->work);
1194 #ifdef CONFIG_SWITCH
1195         switch_dev_unregister(&hdmi->hpd_switch);
1196 #endif
1197         iounmap(hdmi->base);
1198         release_resource(hdmi->base_res);
1199 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1200         clk_put(hdmi->hda2hdmi_clk);
1201         clk_put(hdmi->hda2codec_clk);
1202         clk_put(hdmi->hda_clk);
1203 #endif
1204         clk_put(hdmi->clk);
1205         clk_put(hdmi->disp1_clk);
1206         clk_put(hdmi->disp2_clk);
1207         tegra_edid_destroy(hdmi->edid);
1208         tegra_nvhdcp_destroy(hdmi->nvhdcp);
1209
1210         kfree(hdmi);
1211
1212 }
1213
1214 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
1215 {
1216         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1217         int i;
1218         unsigned freqs[] = {
1219                 32000,
1220                 44100,
1221                 48000,
1222                 88200,
1223                 96000,
1224                 176400,
1225                 192000,
1226         };
1227
1228         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
1229                 unsigned f = freqs[i];
1230                 unsigned eight_half;
1231                 unsigned delta;;
1232
1233                 if (f > 96000)
1234                         delta = 2;
1235                 else if (f > 48000)
1236                         delta = 6;
1237                 else
1238                         delta = 9;
1239
1240                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
1241                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
1242                                   AUDIO_FS_HIGH(eight_half + delta),
1243                                   HDMI_NV_PDISP_AUDIO_FS(i));
1244         }
1245 }
1246
1247 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1248 static void tegra_dc_hdmi_setup_eld_buff(struct tegra_dc *dc)
1249 {
1250         int i;
1251         int j;
1252         u8 tmp;
1253
1254         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1255
1256         /* program ELD stuff */
1257         for (i = 0; i < HDMI_ELD_MONITOR_NAME_INDEX; i++) {
1258                 switch (i) {
1259                 case HDMI_ELD_VER_INDEX:
1260                         tmp = (hdmi->eld.eld_ver << 3);
1261                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1262                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1263                         break;
1264                 case HDMI_ELD_BASELINE_LEN_INDEX:
1265                         break;
1266                 case HDMI_ELD_CEA_VER_MNL_INDEX:
1267                         tmp = (hdmi->eld.cea_edid_ver << 5);
1268                         tmp |= (hdmi->eld.mnl & 0x1f);
1269                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1270                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1271                         break;
1272                 case HDMI_ELD_SAD_CNT_CON_TYP_SAI_HDCP_INDEX:
1273                         tmp = (hdmi->eld.sad_count << 4);
1274                         tmp |= (hdmi->eld.conn_type & 0xC);
1275                         tmp |= (hdmi->eld.support_ai & 0x2);
1276                         tmp |= (hdmi->eld.support_hdcp & 0x1);
1277                         tegra_hdmi_writel(hdmi, (i << 8) | tmp,
1278                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1279                         break;
1280                 case HDMI_ELD_AUD_SYNC_DELAY_INDEX:
1281                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.aud_synch_delay),
1282                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1283                         break;
1284                 case HDMI_ELD_SPK_ALLOC_INDEX:
1285                         tegra_hdmi_writel(hdmi, (i << 8) | (hdmi->eld.spk_alloc),
1286                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1287                         break;
1288                 case HDMI_ELD_PORT_ID_INDEX:
1289                         for (j = 0; j < 8;j++) {
1290                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.port_id[j]),
1291                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1292                         }
1293                         break;
1294                 case HDMI_ELD_MANF_NAME_INDEX:
1295                         for (j = 0; j < 2;j++) {
1296                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.manufacture_id[j]),
1297                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1298                         }
1299                         break;
1300                 case HDMI_ELD_PRODUCT_CODE_INDEX:
1301                         for (j = 0; j < 2;j++) {
1302                                 tegra_hdmi_writel(hdmi, ((i +j) << 8) | (hdmi->eld.product_id[j]),
1303                                           HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1304                         }
1305                         break;
1306                 }
1307         }
1308         for (j = 0; j < hdmi->eld.mnl;j++) {
1309                 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX) << 8) |
1310                                   (hdmi->eld.monitor_name[j]),
1311                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1312         }
1313         for (j = 0; j < hdmi->eld.sad_count;j++) {
1314                 tegra_hdmi_writel(hdmi, ((j + HDMI_ELD_MONITOR_NAME_INDEX + hdmi->eld.mnl) << 8) |
1315                                   (hdmi->eld.sad[j]),
1316                                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR_0);
1317         }
1318                 /* set presence andvalid bit  */
1319         tegra_hdmi_writel(hdmi, 3, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1320 }
1321 #endif
1322
1323 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc, unsigned audio_freq,
1324                                         unsigned audio_source)
1325 {
1326         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1327         const struct tegra_hdmi_audio_config *config;
1328         unsigned long audio_n;
1329 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1330         unsigned long reg_addr = 0;
1331 #endif
1332         unsigned a_source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
1333
1334         if (HDA == audio_source)
1335                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
1336         else if (SPDIF == audio_source)
1337                 a_source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
1338
1339 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1340         if (hdmi->audio_inject_null)
1341                 a_source |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1342
1343         tegra_hdmi_writel(hdmi,a_source,
1344                           HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1345         tegra_hdmi_writel(hdmi,
1346                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1347                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0),
1348                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1349 #if !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1350         tegra_hdmi_writel(hdmi, (1 << HDMI_AUDIO_HBR_ENABLE_SHIFT) |
1351            tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0),
1352            HDMI_NV_PDISP_SOR_AUDIO_SPARE0_0);
1353 #endif
1354 #else
1355         tegra_hdmi_writel(hdmi,
1356                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
1357                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
1358                           a_source,
1359                           HDMI_NV_PDISP_AUDIO_CNTRL0);
1360 #endif
1361         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
1362         if (!config) {
1363                 dev_err(&dc->ndev->dev,
1364                         "hdmi: can't set audio to %d at %d pix_clock",
1365                         audio_freq, dc->mode.pclk);
1366                 return -EINVAL;
1367         }
1368
1369         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
1370
1371         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
1372                 AUDIO_N_VALUE(config->n - 1);
1373         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1374
1375         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
1376                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
1377
1378         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
1379                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
1380
1381         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
1382                           SPARE_CTS_RESET_VAL(1),
1383                           HDMI_NV_PDISP_HDMI_SPARE);
1384
1385         audio_n &= ~AUDIO_N_RESETF;
1386         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
1387
1388 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1389         switch (audio_freq) {
1390         case AUDIO_FREQ_32K:
1391                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320_0;
1392                 break;
1393         case AUDIO_FREQ_44_1K:
1394                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441_0;
1395                 break;
1396         case AUDIO_FREQ_48K:
1397                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480_0;
1398                 break;
1399         case AUDIO_FREQ_88_2K:
1400                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882_0;
1401                 break;
1402         case AUDIO_FREQ_96K:
1403                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960_0;
1404                 break;
1405         case AUDIO_FREQ_176_4K:
1406                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764_0;
1407                 break;
1408         case AUDIO_FREQ_192K:
1409                 reg_addr = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920_0;
1410                 break;
1411         }
1412
1413         tegra_hdmi_writel(hdmi, config->aval, reg_addr);
1414 #endif
1415         tegra_dc_hdmi_setup_audio_fs_tables(dc);
1416
1417         return 0;
1418 }
1419
1420 int tegra_hdmi_setup_audio_freq_source(unsigned audio_freq, unsigned audio_source)
1421 {
1422         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1423
1424         if (!hdmi)
1425                 return -EAGAIN;
1426
1427         /* check for know freq */
1428         if (AUDIO_FREQ_32K == audio_freq ||
1429                 AUDIO_FREQ_44_1K== audio_freq ||
1430                 AUDIO_FREQ_48K== audio_freq ||
1431                 AUDIO_FREQ_88_2K== audio_freq ||
1432                 AUDIO_FREQ_96K== audio_freq ||
1433                 AUDIO_FREQ_176_4K== audio_freq ||
1434                 AUDIO_FREQ_192K== audio_freq) {
1435                 /* If we can program HDMI, then proceed */
1436                 if (hdmi->clk_enabled)
1437                         tegra_dc_hdmi_setup_audio(hdmi->dc, audio_freq,audio_source);
1438
1439                 /* Store it for using it in enable */
1440                 hdmi->audio_freq = audio_freq;
1441                 hdmi->audio_source = audio_source;
1442         }
1443         else
1444                 return -EINVAL;
1445
1446         return 0;
1447 }
1448 EXPORT_SYMBOL(tegra_hdmi_setup_audio_freq_source);
1449
1450 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1451 int tegra_hdmi_audio_null_sample_inject(bool on)
1452 {
1453         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1454         unsigned int val = 0;
1455
1456         if (!hdmi)
1457                 return -EAGAIN;
1458
1459         if (hdmi->audio_inject_null != on) {
1460                 hdmi->audio_inject_null = on;
1461                 if (hdmi->clk_enabled) {
1462                         val = tegra_hdmi_readl(hdmi,
1463                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1464                         val &= ~AUDIO_CNTRL0_INJECT_NULLSMPL;
1465                         if (on)
1466                                 val |= AUDIO_CNTRL0_INJECT_NULLSMPL;
1467                         tegra_hdmi_writel(hdmi,val,
1468                                 HDMI_NV_PDISP_SOR_AUDIO_CNTRL0_0);
1469                 }
1470         }
1471
1472         return 0;
1473 }
1474 EXPORT_SYMBOL(tegra_hdmi_audio_null_sample_inject);
1475
1476 int tegra_hdmi_setup_hda_presence()
1477 {
1478         struct tegra_dc_hdmi_data *hdmi = dc_hdmi;
1479
1480         if (!hdmi)
1481                 return -EAGAIN;
1482
1483         if (hdmi->clk_enabled && hdmi->eld_retrieved) {
1484                 /* If HDA_PRESENCE is already set reset it */
1485                 tegra_dc_unpowergate_locked(hdmi->dc);
1486                 if (tegra_hdmi_readl(hdmi,
1487                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0))
1488                         tegra_hdmi_writel(hdmi, 0,
1489                                      HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
1490
1491                 tegra_dc_hdmi_setup_eld_buff(hdmi->dc);
1492                 tegra_dc_powergate_locked(hdmi->dc);
1493                 return 0;
1494         }
1495         return -ENODEV;
1496
1497 }
1498 EXPORT_SYMBOL(tegra_hdmi_setup_hda_presence);
1499 #endif
1500
1501 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
1502                                          u8 type, u8 version, void *data, int len)
1503 {
1504         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1505         u32 subpack[2];  /* extra byte for zero padding of subpack */
1506         int i;
1507         u8 csum;
1508
1509         /* first byte of data is the checksum */
1510         csum = type + version + len - 1;
1511         for (i = 1; i < len; i++)
1512                 csum +=((u8 *)data)[i];
1513         ((u8 *)data)[0] = 0x100 - csum;
1514
1515         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
1516                           INFOFRAME_HEADER_VERSION(version) |
1517                           INFOFRAME_HEADER_LEN(len - 1),
1518                           header_reg);
1519
1520         /* The audio inforame only has one set of subpack registers.  The hdmi
1521          * block pads the rest of the data as per the spec so we have to fixup
1522          * the length before filling in the subpacks.
1523          */
1524         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
1525                 len = 6;
1526
1527         /* each subpack 7 bytes devided into:
1528          *   subpack_low - bytes 0 - 3
1529          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
1530          */
1531         for (i = 0; i < len; i++) {
1532                 int subpack_idx = i % 7;
1533
1534                 if (subpack_idx == 0)
1535                         memset(subpack, 0x0, sizeof(subpack));
1536
1537                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
1538
1539                 if (subpack_idx == 6 || (i + 1 == len)) {
1540                         int reg = header_reg + 1 + (i / 7) * 2;
1541
1542                         tegra_hdmi_writel(hdmi, subpack[0], reg);
1543                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
1544                 }
1545         }
1546 }
1547
1548 static int tegra_dc_find_cea_vic(const struct tegra_dc_mode *mode)
1549 {
1550         struct fb_videomode m;
1551         unsigned i;
1552         unsigned best = 0;
1553
1554         tegra_dc_to_fb_videomode(&m, mode);
1555
1556         m.vmode &= ~FB_VMODE_STEREO_MASK; /* stereo modes have the same VICs */
1557
1558         for (i = 1; i < CEA_MODEDB_SIZE; i++) {
1559                 const struct fb_videomode *curr = &cea_modes[i];
1560
1561                 if (!fb_mode_is_equal(&m, curr))
1562                         continue;
1563
1564                 /* if either flag is set, then match is required */
1565                 if (curr->flag & (FB_FLAG_RATIO_4_3 | FB_FLAG_RATIO_16_9)) {
1566                         if (m.flag & curr->flag & FB_FLAG_RATIO_4_3)
1567                                 best = i;
1568                         else if (m.flag & curr->flag & FB_FLAG_RATIO_16_9)
1569                                 best = i;
1570                 } else {
1571                         best = i;
1572                 }
1573         }
1574         return best;
1575 }
1576
1577 static int tegra_dc_find_hdmi_vic(const struct tegra_dc_mode *mode)
1578 {
1579         struct fb_videomode m;
1580         unsigned i;
1581
1582         tegra_dc_to_fb_videomode(&m, mode);
1583
1584         for (i = 1; i < HDMI_EXT_MODEDB_SIZE; i++) {
1585                 const struct fb_videomode *curr = &hdmi_ext_modes[i];
1586
1587                 if (fb_mode_is_equal(&m, curr))
1588                         return i;
1589         }
1590         return 0;
1591 }
1592
1593 static void tegra_dc_hdmi_disable_generic_infoframe(struct tegra_dc *dc)
1594 {
1595         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1596         u32 val;
1597
1598         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1599         val &= ~GENERIC_CTRL_ENABLE;
1600         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1601 }
1602
1603 /* return 1 if generic infoframe is used, 0 if not used */
1604 static int tegra_dc_hdmi_setup_hdmi_vic_infoframe(struct tegra_dc *dc, bool dvi)
1605 {
1606         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1607         struct hdmi_extres_infoframe extres;
1608         int hdmi_vic;
1609         u32 val;
1610
1611         if (dvi)
1612                 return 0;
1613         hdmi_vic = tegra_dc_find_hdmi_vic(&dc->mode);
1614         if (hdmi_vic <= 0)
1615                 return 0;
1616
1617         memset(&extres, 0x0, sizeof(extres));
1618
1619         extres.csum = 0;
1620         extres.regid0 = 0x03;
1621         extres.regid1 = 0x0c;
1622         extres.regid2 = 0x00;
1623         extres.hdmi_video_format = 1; /* Extended Resolution Format */
1624         extres.hdmi_vic = hdmi_vic;
1625
1626         tegra_dc_hdmi_write_infopack(dc,
1627                 HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1628                 HDMI_INFOFRAME_TYPE_VENDOR, HDMI_VENDOR_VERSION,
1629                 &extres, 6);
1630         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1631         val |= GENERIC_CTRL_ENABLE;
1632         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1633         return 1;
1634 }
1635
1636 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
1637 {
1638         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1639         struct hdmi_avi_infoframe avi;
1640         unsigned int blender_reg;
1641
1642         if (dvi) {
1643                 tegra_hdmi_writel(hdmi, 0x0,
1644                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1645                 return;
1646         }
1647
1648         memset(&avi, 0x0, sizeof(avi));
1649
1650         /* Indicate active format info is valid. */
1651         avi.a = 1;
1652         avi.r = HDMI_AVI_R_SAME;
1653
1654 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
1655         blender_reg = DC_DISP_BORDER_COLOR;
1656 #else
1657         blender_reg = DC_DISP_BLEND_BACKGROUND_COLOR;
1658 #endif
1659
1660         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
1661                 tegra_dc_writel(dc, 0x00101010, blender_reg);
1662         else
1663                 tegra_dc_writel(dc, 0x00000000, blender_reg);
1664
1665         avi.vic = tegra_dc_find_cea_vic(&dc->mode);
1666         avi.m = dc->mode.avi_m;
1667         if (tegra_edid_underscan_supported(hdmi->edid))
1668                 avi.s = HDMI_AVI_S_UNDERSCAN;
1669         dev_dbg(&dc->ndev->dev, "HDMI AVI vic=%d m=%d\n", avi.vic, avi.m);
1670
1671         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
1672                                      HDMI_INFOFRAME_TYPE_AVI,
1673                                      HDMI_AVI_VERSION,
1674                                      &avi, sizeof(avi));
1675
1676         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1677                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
1678 }
1679
1680 static void tegra_dc_hdmi_setup_stereo_infoframe(struct tegra_dc *dc)
1681 {
1682         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1683         struct hdmi_stereo_infoframe stereo;
1684         u32 val;
1685
1686         WARN(!dc->mode.stereo_mode,
1687                 "function assumes 3D/stereo mode is disabled\n");
1688
1689         memset(&stereo, 0x0, sizeof(stereo));
1690
1691         stereo.regid0 = 0x03;
1692         stereo.regid1 = 0x0c;
1693         stereo.regid2 = 0x00;
1694         stereo.hdmi_video_format = 2; /* 3D_Structure present */
1695 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1696         stereo._3d_structure = 0; /* frame packing */
1697 #else
1698         stereo._3d_structure = 8; /* side-by-side (half) */
1699         stereo._3d_ext_data = 0; /* something which fits into 00XX bit req */
1700 #endif
1701
1702         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
1703                                         HDMI_INFOFRAME_TYPE_VENDOR,
1704                                         HDMI_VENDOR_VERSION,
1705                                         &stereo, 6);
1706
1707         val  = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1708         val |= GENERIC_CTRL_ENABLE;
1709
1710         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1711 }
1712
1713 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
1714 {
1715         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1716         struct hdmi_audio_infoframe audio;
1717
1718         if (dvi) {
1719                 tegra_hdmi_writel(hdmi, 0x0,
1720                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1721                 return;
1722         }
1723
1724         memset(&audio, 0x0, sizeof(audio));
1725
1726         audio.cc = HDMI_AUDIO_CC_2;
1727         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
1728                                      HDMI_INFOFRAME_TYPE_AUDIO,
1729                                      HDMI_AUDIO_VERSION,
1730                                      &audio, sizeof(audio));
1731
1732         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
1733                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
1734 }
1735
1736 static void tegra_dc_hdmi_setup_tmds(struct tegra_dc_hdmi_data *hdmi,
1737                 const struct tmds_config *tc)
1738 {
1739 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
1740         u32 val;
1741 #endif
1742
1743         tegra_hdmi_writel(hdmi, tc->pll0, HDMI_NV_PDISP_SOR_PLL0);
1744         tegra_hdmi_writel(hdmi, tc->pll1, HDMI_NV_PDISP_SOR_PLL1);
1745
1746         tegra_hdmi_writel(hdmi, tc->pe_current, HDMI_NV_PDISP_PE_CURRENT);
1747
1748 #if defined(CONFIG_ARCH_TEGRA_11x_SOC)
1749         tegra_hdmi_writel(hdmi, tc->drive_current,
1750                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1751         val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1752         val |= DRIVE_CURRENT_FUSE_OVERRIDE_T11x;
1753         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1754
1755         tegra_hdmi_writel(hdmi, tc->peak_current,
1756                 HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
1757 #elif defined(CONFIG_ARCH_TEGRA_14x_SOC)
1758         tegra_hdmi_writel(hdmi, tc->drive_current,
1759                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1760         tegra_hdmi_writel(hdmi, 0x800034bb, HDMI_NV_PDISP_SOR_PAD_CTLS0);
1761 #else
1762         tegra_hdmi_writel(hdmi, tc->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE,
1763                 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1764 #endif
1765 }
1766
1767 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
1768 {
1769         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1770         int pulse_start;
1771         int dispclk_div_8_2;
1772         int retries;
1773         int rekey;
1774         int err;
1775         unsigned long val;
1776         unsigned i;
1777         const struct tmds_config *tmds_ptr;
1778         size_t tmds_len;
1779
1780         /* enbale power, clocks, resets, etc. */
1781
1782         /* The upstream DC needs to be clocked for accesses to HDMI to not
1783          * hard lock the system.  Because we don't know if HDMI is conencted
1784          * to disp1 or disp2 we need to enable both until we set the DC mux.
1785          */
1786         clk_prepare_enable(hdmi->disp1_clk);
1787         clk_prepare_enable(hdmi->disp2_clk);
1788
1789 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1790         /* Enabling HDA clocks before asserting HDA PD and ELDV bits */
1791         clk_prepare_enable(hdmi->hda_clk);
1792         clk_prepare_enable(hdmi->hda2codec_clk);
1793         clk_prepare_enable(hdmi->hda2hdmi_clk);
1794 #endif
1795
1796         tegra_dc_setup_clk(dc, hdmi->clk);
1797         clk_set_rate(hdmi->clk, dc->mode.pclk);
1798
1799         clk_prepare_enable(hdmi->clk);
1800         tegra_periph_reset_assert(hdmi->clk);
1801         mdelay(1);
1802         tegra_periph_reset_deassert(hdmi->clk);
1803
1804         /* TODO: copy HDCP keys from KFUSE to HDMI */
1805
1806         /* Program display timing registers: handled by dc */
1807
1808         /* program HDMI registers and SOR sequencer */
1809
1810         tegra_dc_io_start(dc);
1811         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
1812
1813         dc->out->depth = 24;
1814         dc->out->dither = TEGRA_DC_DISABLE_DITHER;
1815         tegra_dc_set_color_control(dc);
1816
1817         /* video_preamble uses h_pulse2 */
1818         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
1819                 dc->mode.h_back_porch - 10;
1820         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1821         tegra_dc_writel(dc,
1822                         PULSE_MODE_NORMAL |
1823                         PULSE_POLARITY_HIGH |
1824                         PULSE_QUAL_VACTIVE |
1825                         PULSE_LAST_END_A,
1826                         DC_DISP_H_PULSE2_CONTROL);
1827         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
1828                   DC_DISP_H_PULSE2_POSITION_A);
1829
1830         tegra_hdmi_writel(hdmi,
1831                           VSYNC_WINDOW_END(0x210) |
1832                           VSYNC_WINDOW_START(0x200) |
1833                           VSYNC_WINDOW_ENABLE,
1834                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1835
1836         if ((dc->mode.h_active == 720) && ((dc->mode.v_active == 480) || (dc->mode.v_active == 576)))
1837                 tegra_hdmi_writel(hdmi,
1838                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
1839                                   ARM_VIDEO_RANGE_FULL,
1840                                   HDMI_NV_PDISP_INPUT_CONTROL);
1841         else
1842                 tegra_hdmi_writel(hdmi,
1843                                   (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
1844                                   ARM_VIDEO_RANGE_LIMITED,
1845                                   HDMI_NV_PDISP_INPUT_CONTROL);
1846
1847         clk_disable_unprepare(hdmi->disp1_clk);
1848         clk_disable_unprepare(hdmi->disp2_clk);
1849
1850         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1851         tegra_hdmi_writel(hdmi,
1852                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
1853                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
1854                           HDMI_NV_PDISP_SOR_REFCLK);
1855
1856         hdmi->clk_enabled = true;
1857
1858         if (!hdmi->dvi) {
1859                 err = tegra_dc_hdmi_setup_audio(dc, hdmi->audio_freq,
1860                         hdmi->audio_source);
1861
1862                 if (err < 0)
1863                         hdmi->dvi = true;
1864         }
1865
1866 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
1867         if (hdmi->eld_retrieved)
1868                 tegra_dc_hdmi_setup_eld_buff(dc);
1869 #endif
1870
1871         rekey = HDMI_REKEY_DEFAULT;
1872         val = HDMI_CTRL_REKEY(rekey);
1873         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
1874                                         dc->mode.h_back_porch +
1875                                         dc->mode.h_front_porch -
1876                                         rekey - 18) / 32);
1877         if (!hdmi->dvi)
1878                 val |= HDMI_CTRL_ENABLE;
1879         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
1880
1881         if (hdmi->dvi)
1882                 tegra_hdmi_writel(hdmi, 0x0,
1883                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1884         else
1885                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
1886                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1887
1888         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
1889
1890         if (dc->mode.stereo_mode)
1891                 tegra_dc_hdmi_setup_stereo_infoframe(dc);
1892         else if (!tegra_dc_hdmi_setup_hdmi_vic_infoframe(dc, hdmi->dvi))
1893                 tegra_dc_hdmi_disable_generic_infoframe(dc);
1894
1895         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
1896
1897         /* Set tmds config. Set it to custom values provided in board file;
1898          * otherwise, set it to default values. */
1899         if (hdmi->info.tmds_config && hdmi->info.n_tmds_config) {
1900                 tmds_ptr = hdmi->info.tmds_config;
1901                 tmds_len = hdmi->info.n_tmds_config;
1902         } else {
1903                 tmds_ptr = tmds_config;
1904                 tmds_len = ARRAY_SIZE(tmds_config);
1905         }
1906
1907         for (i = 0; i < tmds_len && tmds_ptr[i].pclk < dc->mode.pclk; i++)
1908                 ;
1909         if (i < tmds_len) {
1910                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[i]);
1911         } else {
1912                 dev_warn(&dc->ndev->dev,
1913                         "pixel clock %u not present on TMDS table.\n",
1914                         dc->mode.pclk);
1915                 tegra_dc_hdmi_setup_tmds(hdmi, &tmds_ptr[tmds_len - 1]);
1916         }
1917
1918         tegra_hdmi_writel(hdmi,
1919                           SOR_SEQ_CTL_PU_PC(0) |
1920                           SOR_SEQ_PU_PC_ALT(0) |
1921                           SOR_SEQ_PD_PC(8) |
1922                           SOR_SEQ_PD_PC_ALT(8),
1923                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1924
1925         val = SOR_SEQ_INST_WAIT_TIME(1) |
1926                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1927                 SOR_SEQ_INST_HALT |
1928                 SOR_SEQ_INST_PIN_A_LOW |
1929                 SOR_SEQ_INST_PIN_B_LOW |
1930                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1931
1932         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
1933         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
1934
1935         val = 0x1c800;
1936         val &= ~SOR_CSTM_ROTCLK(~0);
1937         val |= SOR_CSTM_ROTCLK(2);
1938         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
1939
1940
1941         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1942         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1943         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1944
1945
1946         /* start SOR */
1947         tegra_hdmi_writel(hdmi,
1948                           SOR_PWR_NORMAL_STATE_PU |
1949                           SOR_PWR_NORMAL_START_NORMAL |
1950                           SOR_PWR_SAFE_STATE_PD |
1951                           SOR_PWR_SETTING_NEW_TRIGGER,
1952                           HDMI_NV_PDISP_SOR_PWR);
1953         tegra_hdmi_writel(hdmi,
1954                           SOR_PWR_NORMAL_STATE_PU |
1955                           SOR_PWR_NORMAL_START_NORMAL |
1956                           SOR_PWR_SAFE_STATE_PD |
1957                           SOR_PWR_SETTING_NEW_DONE,
1958                           HDMI_NV_PDISP_SOR_PWR);
1959
1960         retries = 1000;
1961         do {
1962                 BUG_ON(--retries < 0);
1963                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1964         } while (val & SOR_PWR_SETTING_NEW_PENDING);
1965
1966         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
1967                 SOR_STATE_ASY_OWNER_HEAD0 |
1968                 SOR_STATE_ASY_SUBOWNER_BOTH |
1969                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1970                 SOR_STATE_ASY_DEPOL_POS;
1971
1972         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1973                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
1974         else
1975                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
1976
1977         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1978                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
1979         else
1980                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
1981
1982         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
1983
1984         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1985         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
1986
1987         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1988         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1989         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
1990                           HDMI_NV_PDISP_SOR_STATE1);
1991         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1992
1993         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1994
1995         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1996                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1997                         DC_CMD_DISPLAY_POWER_CONTROL);
1998
1999         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
2000         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
2001         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2002
2003         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
2004         tegra_dc_io_end(dc);
2005 }
2006
2007 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
2008 {
2009         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
2010
2011         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
2012
2013 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC)
2014         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE_0);
2015         /* sleep 1ms before disabling clocks to ensure HDA gets the interrupt */
2016         msleep(1);
2017         clk_disable_unprepare(hdmi->hda2hdmi_clk);
2018         clk_disable_unprepare(hdmi->hda2codec_clk);
2019         clk_disable_unprepare(hdmi->hda_clk);
2020 #endif
2021         tegra_periph_reset_assert(hdmi->clk);
2022         hdmi->clk_enabled = false;
2023         clk_disable_unprepare(hdmi->clk);
2024         tegra_dvfs_set_rate(hdmi->clk, 0);
2025 }
2026
2027 static long tegra_dc_hdmi_setup_clk(struct tegra_dc *dc, struct clk *clk)
2028 {
2029         unsigned long rate;
2030         struct clk *parent_clk = clk_get_sys(NULL,
2031                 dc->out->parent_clk ? : "pll_d_out0");
2032         struct clk *base_clk = clk_get_parent(parent_clk);
2033
2034         if (clk != dc->clk) {
2035                 clk_set_rate(base_clk, dc->mode.pclk);
2036
2037                 if (clk_get_parent(clk) != parent_clk)
2038                         clk_set_parent(clk, parent_clk);
2039
2040                 clk_set_rate(clk, dc->mode.pclk / 4);
2041         }
2042
2043         /*
2044          * Providing dynamic frequency rate setting for T20/T30 HDMI.
2045          * The required rate needs to be setup at 4x multiplier,
2046          * as out0 is 1/2 of the actual PLL output.
2047          */
2048         rate = dc->mode.pclk * 2;
2049         while (rate < 500000000)
2050                 rate *= 2;
2051
2052         if (rate != clk_get_rate(base_clk))
2053                 clk_set_rate(base_clk, rate);
2054
2055         if (clk_get_parent(clk) != parent_clk)
2056                 clk_set_parent(clk, parent_clk);
2057
2058         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2059 }
2060
2061 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
2062         .init = tegra_dc_hdmi_init,
2063         .destroy = tegra_dc_hdmi_destroy,
2064         .enable = tegra_dc_hdmi_enable,
2065         .disable = tegra_dc_hdmi_disable,
2066         .detect = tegra_dc_hdmi_detect,
2067         .suspend = tegra_dc_hdmi_suspend,
2068         .resume = tegra_dc_hdmi_resume,
2069         .mode_filter = tegra_dc_hdmi_mode_filter,
2070         .setup_clk = tegra_dc_hdmi_setup_clk,
2071 };
2072
2073 struct tegra_dc_edid *tegra_dc_get_edid(struct tegra_dc *dc)
2074 {
2075         struct tegra_dc_hdmi_data *hdmi;
2076
2077         /* TODO: Support EDID on non-HDMI devices */
2078         if (dc->out->type != TEGRA_DC_OUT_HDMI)
2079                 return ERR_PTR(-ENODEV);
2080
2081         hdmi = tegra_dc_get_outdata(dc);
2082
2083         return tegra_edid_get_data(hdmi->edid);
2084 }
2085 EXPORT_SYMBOL(tegra_dc_get_edid);
2086
2087 void tegra_dc_put_edid(struct tegra_dc_edid *edid)
2088 {
2089         tegra_edid_put_data(edid);
2090 }
2091 EXPORT_SYMBOL(tegra_dc_put_edid);
2092
2093 struct tegra_dc *tegra_dc_hdmi_get_dc(struct tegra_dc_hdmi_data *hdmi)
2094 {
2095         return hdmi ? hdmi->dc : NULL;
2096 }