drivers/video/tegra/dc/dsi.c

   1 /*
   2  * drivers/video/tegra/dc/dsi.c
   3  *
   4  * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved.
   5  *
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/workqueue.h>
  27 #include <linux/moduleparam.h>
  28 #include <linux/export.h>
  29 #include <linux/debugfs.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/nvhost.h>
  32 #include <linux/lcm.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 #include <mach/clk.h>
  36 #include <mach/dc.h>
  37 #include <mach/fb.h>
  38 #include <mach/csi.h>
  39 #include <linux/nvhost.h>
  40
  41 #include "dc_reg.h"
  42 #include "dc_priv.h"
  43 #include "dev.h"
  44 #include "dsi_regs.h"
  45 #include "dsi.h"
  46 #include "mipi_cal.h"
  47
  48 /* HACK! This needs to come from DT */
  49 #include "../../../../arch/arm/mach-tegra/iomap.h"
  50
  51 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
  52 #define DSIB_MODE_ENABLE                0x2
  53
  54 #define DSI_USE_SYNC_POINTS             0
  55 #define S_TO_MS(x)                      (1000 * (x))
  56 #define MS_TO_US(x)                     (1000 * (x))
  57
  58 #define DSI_MODULE_NOT_INIT             0x0
  59 #define DSI_MODULE_INIT                 0x1
  60
  61 #define DSI_LPHS_NOT_INIT               0x0
  62 #define DSI_LPHS_IN_LP_MODE             0x1
  63 #define DSI_LPHS_IN_HS_MODE             0x2
  64
  65 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
  66 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
  67 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
  68
  69 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
  70 #define DSI_DRIVEN_MODE_DC              0x1
  71 #define DSI_DRIVEN_MODE_HOST            0x2
  72
  73 #define DSI_PHYCLK_OUT_DIS              0x0
  74 #define DSI_PHYCLK_OUT_EN               0x1
  75
  76 #define DSI_PHYCLK_NOT_INIT             0x0
  77 #define DSI_PHYCLK_CONTINUOUS           0x1
  78 #define DSI_PHYCLK_TX_ONLY              0x2
  79
  80 #define DSI_CLK_BURST_NOT_INIT          0x0
  81 #define DSI_CLK_BURST_NONE_BURST        0x1
  82 #define DSI_CLK_BURST_BURST_MODE        0x2
  83
  84 #define DSI_DC_STREAM_DISABLE           0x0
  85 #define DSI_DC_STREAM_ENABLE            0x1
  86
  87 #define DSI_LP_OP_NOT_INIT              0x0
  88 #define DSI_LP_OP_WRITE                 0x1
  89 #define DSI_LP_OP_READ                  0x2
  90
  91 #define DSI_HOST_IDLE_PERIOD            1000
  92 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
  93
  94 static bool enable_read_debug;
  95 module_param(enable_read_debug, bool, 0644);
  96 MODULE_PARM_DESC(enable_read_debug,
  97                 "Enable to print read fifo and return packet type");
  98
  99 /* source of video data */
 100 enum {
 101         TEGRA_DSI_DRIVEN_BY_DC,
 102         TEGRA_DSI_DRIVEN_BY_HOST,
 103 };
 104
 105 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
 106
 107 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
 108         DSI_PKT_SEQ_0_LO,
 109         DSI_PKT_SEQ_0_HI,
 110         DSI_PKT_SEQ_1_LO,
 111         DSI_PKT_SEQ_1_HI,
 112         DSI_PKT_SEQ_2_LO,
 113         DSI_PKT_SEQ_2_HI,
 114         DSI_PKT_SEQ_3_LO,
 115         DSI_PKT_SEQ_3_HI,
 116         DSI_PKT_SEQ_4_LO,
 117         DSI_PKT_SEQ_4_HI,
 118         DSI_PKT_SEQ_5_LO,
 119         DSI_PKT_SEQ_5_HI,
 120 };
 121
 122 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
 123         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 124         0,
 125         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 126         0,
 127         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 128         0,
 129         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 130         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 131         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 132         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 133         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 134         0,
 135         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
 136         PKT_ID2(CMD_HE) | PKT_LEN2(0),
 137         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
 138         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
 139 };
 140
 141 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
 142         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 143         0,
 144         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 145         0,
 146         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 147         0,
 148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 149         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 150         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 151         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 152         0,
 153         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
 154         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
 155         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
 156 };
 157
 158 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
 159         PKT_ID0(CMD_VS) | PKT_LEN0(0),
 160         0,
 161         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 162         0,
 163         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 164         0,
 165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 166         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 167         0,
 168         PKT_ID0(CMD_HS) | PKT_LEN0(0),
 169         0,
 170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
 171         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
 172         0,
 173 };
 174
 175 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
 176         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 177         0,
 178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 179         0,
 180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 181         0,
 182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 183         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 184         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 185         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
 186         0,
 187         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 188         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 189         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
 190 };
 191
 192 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
 193         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
 194         0,
 195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 196         0,
 197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 198         0,
 199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 200         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 201         0,
 202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
 203         0,
 204         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
 205         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
 206         0,
 207 };
 208
 209 /* TODO: verify with hw about this format */
 210 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
 211         0,
 212         0,
 213         0,
 214         0,
 215         0,
 216         0,
 217         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
 218         0,
 219         0,
 220         0,
 221         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
 222         0,
 223 };
 224
 225 const u32 init_reg[] = {
 226         DSI_INT_ENABLE,
 227         DSI_INT_STATUS,
 228         DSI_INT_MASK,
 229         DSI_INIT_SEQ_DATA_0,
 230         DSI_INIT_SEQ_DATA_1,
 231         DSI_INIT_SEQ_DATA_2,
 232         DSI_INIT_SEQ_DATA_3,
 233         DSI_INIT_SEQ_DATA_4,
 234         DSI_INIT_SEQ_DATA_5,
 235         DSI_INIT_SEQ_DATA_6,
 236         DSI_INIT_SEQ_DATA_7,
 237         DSI_DCS_CMDS,
 238         DSI_PKT_SEQ_0_LO,
 239         DSI_PKT_SEQ_1_LO,
 240         DSI_PKT_SEQ_2_LO,
 241         DSI_PKT_SEQ_3_LO,
 242         DSI_PKT_SEQ_4_LO,
 243         DSI_PKT_SEQ_5_LO,
 244         DSI_PKT_SEQ_0_HI,
 245         DSI_PKT_SEQ_1_HI,
 246         DSI_PKT_SEQ_2_HI,
 247         DSI_PKT_SEQ_3_HI,
 248         DSI_PKT_SEQ_4_HI,
 249         DSI_PKT_SEQ_5_HI,
 250         DSI_CONTROL,
 251         DSI_HOST_DSI_CONTROL,
 252         DSI_PAD_CONTROL,
 253         DSI_PAD_CONTROL_CD,
 254         DSI_SOL_DELAY,
 255         DSI_MAX_THRESHOLD,
 256         DSI_TRIGGER,
 257         DSI_TX_CRC,
 258         DSI_INIT_SEQ_CONTROL,
 259         DSI_PKT_LEN_0_1,
 260         DSI_PKT_LEN_2_3,
 261         DSI_PKT_LEN_4_5,
 262         DSI_PKT_LEN_6_7,
 263 };
 264
 265 const u32 init_reg_vs1_ext[] = {
 266         DSI_PAD_CONTROL_0_VS1,
 267         DSI_PAD_CONTROL_CD_VS1,
 268         DSI_PAD_CD_STATUS_VS1,
 269         DSI_PAD_CONTROL_1_VS1,
 270         DSI_PAD_CONTROL_2_VS1,
 271         DSI_PAD_CONTROL_3_VS1,
 272         DSI_PAD_CONTROL_4_VS1,
 273         DSI_GANGED_MODE_CONTROL,
 274         DSI_GANGED_MODE_START,
 275         DSI_GANGED_MODE_SIZE,
 276 };
 277
 278 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
 279 static int tegra_dsi_host_resume(struct tegra_dc *dc);
 280 static void tegra_dc_dsi_idle_work(struct work_struct *work);
 281 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
 282                                      struct tegra_dc_dsi_data *dsi,
 283                                      int no_of_frames);
 284
 285 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
 286 {
 287         unsigned long ret;
 288
 289         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 290         ret = readl(dsi->base + reg * 4);
 291         trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
 292         return ret;
 293 }
 294 EXPORT_SYMBOL(tegra_dsi_readl);
 295
 296 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
 297 {
 298         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
 299         trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
 300         writel(val, dsi->base + reg * 4);
 301 }
 302 EXPORT_SYMBOL(tegra_dsi_writel);
 303
 304 #ifdef CONFIG_DEBUG_FS
 305 static int dbg_dsi_show(struct seq_file *s, void *unused)
 306 {
 307         struct tegra_dc_dsi_data *dsi = s->private;
 308
 309 #define DUMP_REG(a) do {                                                \
 310                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
 311                        #a, a, tegra_dsi_readl(dsi, a));         \
 312         } while (0)
 313
 314         tegra_dc_io_start(dsi->dc);
 315         clk_prepare_enable(dsi->dsi_clk);
 316
 317         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
 318         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
 319         DUMP_REG(DSI_CTXSW);
 320         DUMP_REG(DSI_POWER_CONTROL);
 321         DUMP_REG(DSI_INT_ENABLE);
 322         DUMP_REG(DSI_HOST_DSI_CONTROL);
 323         DUMP_REG(DSI_CONTROL);
 324         DUMP_REG(DSI_SOL_DELAY);
 325         DUMP_REG(DSI_MAX_THRESHOLD);
 326         DUMP_REG(DSI_TRIGGER);
 327         DUMP_REG(DSI_TX_CRC);
 328         DUMP_REG(DSI_STATUS);
 329         DUMP_REG(DSI_INIT_SEQ_CONTROL);
 330         DUMP_REG(DSI_INIT_SEQ_DATA_0);
 331         DUMP_REG(DSI_INIT_SEQ_DATA_1);
 332         DUMP_REG(DSI_INIT_SEQ_DATA_2);
 333         DUMP_REG(DSI_INIT_SEQ_DATA_3);
 334         DUMP_REG(DSI_INIT_SEQ_DATA_4);
 335         DUMP_REG(DSI_INIT_SEQ_DATA_5);
 336         DUMP_REG(DSI_INIT_SEQ_DATA_6);
 337         DUMP_REG(DSI_INIT_SEQ_DATA_7);
 338         DUMP_REG(DSI_PKT_SEQ_0_LO);
 339         DUMP_REG(DSI_PKT_SEQ_0_HI);
 340         DUMP_REG(DSI_PKT_SEQ_1_LO);
 341         DUMP_REG(DSI_PKT_SEQ_1_HI);
 342         DUMP_REG(DSI_PKT_SEQ_2_LO);
 343         DUMP_REG(DSI_PKT_SEQ_2_HI);
 344         DUMP_REG(DSI_PKT_SEQ_3_LO);
 345         DUMP_REG(DSI_PKT_SEQ_3_HI);
 346         DUMP_REG(DSI_PKT_SEQ_4_LO);
 347         DUMP_REG(DSI_PKT_SEQ_4_HI);
 348         DUMP_REG(DSI_PKT_SEQ_5_LO);
 349         DUMP_REG(DSI_PKT_SEQ_5_HI);
 350         DUMP_REG(DSI_DCS_CMDS);
 351         DUMP_REG(DSI_PKT_LEN_0_1);
 352         DUMP_REG(DSI_PKT_LEN_2_3);
 353         DUMP_REG(DSI_PKT_LEN_4_5);
 354         DUMP_REG(DSI_PKT_LEN_6_7);
 355         DUMP_REG(DSI_PHY_TIMING_0);
 356         DUMP_REG(DSI_PHY_TIMING_1);
 357         DUMP_REG(DSI_PHY_TIMING_2);
 358         DUMP_REG(DSI_BTA_TIMING);
 359         DUMP_REG(DSI_TIMEOUT_0);
 360         DUMP_REG(DSI_TIMEOUT_1);
 361         DUMP_REG(DSI_TO_TALLY);
 362         DUMP_REG(DSI_PAD_CONTROL);
 363         DUMP_REG(DSI_PAD_CONTROL_CD);
 364         DUMP_REG(DSI_PAD_CD_STATUS);
 365         DUMP_REG(DSI_VID_MODE_CONTROL);
 366 #undef DUMP_REG
 367
 368         clk_disable_unprepare(dsi->dsi_clk);
 369         tegra_dc_io_end(dsi->dc);
 370
 371         return 0;
 372 }
 373
 374 static int dbg_dsi_open(struct inode *inode, struct file *file)
 375 {
 376         return single_open(file, dbg_dsi_show, inode->i_private);
 377 }
 378
 379 static const struct file_operations dbg_fops = {
 380         .open           = dbg_dsi_open,
 381         .read           = seq_read,
 382         .llseek         = seq_lseek,
 383         .release        = single_release,
 384 };
 385
 386 static struct dentry *dsidir;
 387
 388 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
 389 {
 390         struct dentry *retval;
 391
 392         dsidir = debugfs_create_dir("tegra_dsi", NULL);
 393         if (!dsidir)
 394                 return;
 395         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
 396                 &dbg_fops);
 397         if (!retval)
 398                 goto free_out;
 399         return;
 400 free_out:
 401         debugfs_remove_recursive(dsidir);
 402         dsidir = NULL;
 403         return;
 404 }
 405 #else
 406 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
 407 { }
 408 #endif
 409
 410 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
 411 {
 412         if (!tegra_is_clk_enabled(dsi->dsi_clk))
 413                 clk_prepare_enable(dsi->dsi_clk);
 414 }
 415
 416 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
 417 {
 418         if (tegra_is_clk_enabled(dsi->dsi_clk))
 419                 clk_disable_unprepare(dsi->dsi_clk);
 420 }
 421
 422 static void __maybe_unused tegra_dsi_syncpt_reset(
 423                                 struct tegra_dc_dsi_data *dsi)
 424 {
 425         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
 426         /* stabilization delay */
 427         udelay(300);
 428         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
 429         /* stabilization delay */
 430         udelay(300);
 431 }
 432
 433 static int __maybe_unused tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
 434 {
 435         u32 val;
 436         int ret = 0;
 437
 438         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
 439
 440         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
 441                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
 442         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
 443
 444         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
 445                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
 446         if (ret < 0) {
 447                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
 448                 goto fail;
 449         }
 450
 451         (dsi->syncpt_val)++;
 452         return 0;
 453 fail:
 454         return ret;
 455 }
 456
 457 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
 458 {
 459         u32 dsi_clock_rate_khz;
 460
 461         switch (dsi->info.video_burst_mode) {
 462         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
 463         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
 464         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
 465         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
 466                 /* Calculate DSI HS clock rate for DSI burst mode */
 467                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
 468                                         dsi->shift_clk_div.mul /
 469                                         dsi->shift_clk_div.div;
 470                 break;
 471         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
 472         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
 473         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
 474         default:
 475                 /* Clock rate is default DSI clock rate for non-burst mode */
 476                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
 477                 break;
 478         }
 479
 480         return dsi_clock_rate_khz;
 481 }
 482
 483 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
 484 {
 485         u32 dsi_clock_rate_khz;
 486
 487         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 488                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
 489                         dsi_clock_rate_khz =
 490                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
 491                 else
 492                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
 493         else
 494                 if (lp_op == DSI_LP_OP_READ)
 495                         dsi_clock_rate_khz =
 496                                 dsi->info.lp_read_cmd_mode_freq_khz;
 497                 else
 498                         dsi_clock_rate_khz =
 499                                 dsi->info.lp_cmd_mode_freq_khz;
 500
 501         return dsi_clock_rate_khz;
 502 }
 503
 504 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
 505                                                 struct tegra_dc_dsi_data *dsi)
 506 {
 507         struct tegra_dc_shift_clk_div shift_clk_div;
 508         struct tegra_dc_shift_clk_div max_shift_clk_div;
 509         u32 temp_lcm;
 510         u32 burst_width;
 511         u32 burst_width_max;
 512
 513         /* Get the real value of default shift_clk_div. default_shift_clk_div
 514          * holds the real value of shift_clk_div.
 515          */
 516         shift_clk_div = dsi->default_shift_clk_div;
 517
 518         /* Calculate shift_clk_div which can match the video_burst_mode. */
 519         if (dsi->info.video_burst_mode >=
 520                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
 521                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz) {
 522                         /* formula:
 523                          * dsi->info.max_panel_freq_khz * shift_clk_div /
 524                          * dsi->default_hs_clk_khz
 525                          */
 526                         max_shift_clk_div.mul = dsi->info.max_panel_freq_khz *
 527                                                 shift_clk_div.mul;
 528                         max_shift_clk_div.div = dsi->default_hs_clk_khz *
 529                                                 dsi->default_shift_clk_div.div;
 530                 } else {
 531                         max_shift_clk_div = shift_clk_div;
 532                 }
 533
 534                 burst_width = dsi->info.video_burst_mode
 535                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 536                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
 537                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
 538
 539                 /* formula:
 540                  * (max_shift_clk_div - shift_clk_div) *
 541                  * burst_width / burst_width_max
 542                  */
 543                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
 544                 shift_clk_div.mul = (max_shift_clk_div.mul * temp_lcm /
 545                                         max_shift_clk_div.div -
 546                                         shift_clk_div.mul * temp_lcm /
 547                                         shift_clk_div.div)*
 548                                         burst_width;
 549                 shift_clk_div.div = temp_lcm * burst_width_max;
 550         }
 551
 552         return shift_clk_div;
 553 }
 554
 555 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
 556                                         struct tegra_dc_dsi_data *dsi)
 557 {
 558         u32 h_width_pixels;
 559         u32 h_act_corr = 0;
 560         u32 hfp_corr = 0;
 561         u32 temp = 0;
 562
 563         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 564                         dc->mode.h_sync_width + dc->mode.h_active;
 565
 566         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
 567                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
 568                 if (temp) {
 569                         h_act_corr = dsi->info.n_data_lanes - temp;
 570                         h_width_pixels += h_act_corr;
 571                 }
 572         }
 573
 574         temp = h_width_pixels % dsi->info.n_data_lanes;
 575         if (temp) {
 576                 hfp_corr = dsi->info.n_data_lanes - temp;
 577                 h_width_pixels += hfp_corr;
 578         }
 579
 580         while (1) {
 581                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
 582                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
 583                 if (temp) {
 584                         hfp_corr += dsi->info.n_data_lanes;
 585                         h_width_pixels += dsi->info.n_data_lanes;
 586                 }
 587                 else
 588                         break;
 589         }
 590
 591         dc->mode.h_front_porch += hfp_corr;
 592         dc->mode.h_active += h_act_corr;
 593 }
 594
 595 static void tegra_dsi_init_sw(struct tegra_dc *dc,
 596                         struct tegra_dc_dsi_data *dsi)
 597 {
 598         u32 h_width_pixels;
 599         u32 v_width_lines;
 600         u32 pixel_clk_hz;
 601         u32 byte_clk_hz;
 602         u32 plld_clk_mhz;
 603         u8 n_data_lanes;
 604
 605         switch (dsi->info.pixel_format) {
 606         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
 607                 /* 2 bytes per pixel */
 608                 dsi->pixel_scaler_mul = 2;
 609                 dsi->pixel_scaler_div = 1;
 610                 break;
 611         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
 612                 /* 2.25 bytes per pixel */
 613                 dsi->pixel_scaler_mul = 9;
 614                 dsi->pixel_scaler_div = 4;
 615                 break;
 616         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
 617         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
 618                 /* 3 bytes per pixel */
 619                 dsi->pixel_scaler_mul = 3;
 620                 dsi->pixel_scaler_div = 1;
 621                 break;
 622         default:
 623                 break;
 624         }
 625
 626         dsi->ulpm = false;
 627         dsi->enabled = false;
 628         dsi->clk_ref = false;
 629
 630         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
 631                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
 632                 n_data_lanes = dsi->info.n_data_lanes / 2;
 633
 634         dsi->dsi_control_val =
 635                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
 636                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
 637                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
 638                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
 639
 640         if (dsi->info.ganged_type)
 641                 tegra_dsi_pix_correction(dc, dsi);
 642
 643         /* Below we are going to calculate dsi and dc clock rate.
 644          * Calcuate the horizontal and vertical width.
 645          */
 646         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
 647                         dc->mode.h_sync_width + dc->mode.h_active;
 648
 649         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
 650                         dc->mode.v_sync_width + dc->mode.v_active;
 651
 652         /* Calculate minimum required pixel rate. */
 653         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
 654         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
 655                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
 656                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
 657                                 "should be larger than rated refresh rate.\n");
 658                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
 659                                                 dsi->info.rated_refresh_rate;
 660         }
 661
 662         /* Calculate minimum byte rate on DSI interface. */
 663         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
 664                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
 665
 666         /* Round up to multiple of mega hz. */
 667         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
 668                                                                 1000000);
 669
 670         /* Calculate default real shift_clk_div. */
 671         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
 672                                         dsi->pixel_scaler_mul;
 673         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
 674                                         dsi->info.n_data_lanes;
 675
 676         /* Calculate default DSI hs clock. DSI interface is double data rate.
 677          * Data is transferred on both rising and falling edge of clk, div by 2
 678          * to get the actual clock rate.
 679          */
 680         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
 681
 682         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
 683                                         dsi->default_shift_clk_div.div) /
 684                                         (2 * dsi->default_shift_clk_div.mul);
 685
 686         /* Get the actual shift_clk_div and clock rates. */
 687         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
 688         dsi->target_lp_clk_khz =
 689                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
 690         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
 691
 692         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
 693                                         dsi->target_hs_clk_khz);
 694
 695 #if DSI_USE_SYNC_POINTS
 696         dsi->syncpt_id = NVSYNCPT_DSI;
 697 #endif
 698
 699         /*
 700          * Force video clock to be continuous mode if
 701          * enable_hs_clock_on_lp_cmd_mode is set
 702          */
 703         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 704                 if (dsi->info.video_clock_mode !=
 705                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
 706                         dev_warn(&dc->ndev->dev,
 707                                 "Force clock continuous mode\n");
 708
 709                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
 710         }
 711
 712         atomic_set(&dsi->host_ref, 0);
 713         dsi->host_suspended = false;
 714         mutex_init(&dsi->host_lock);
 715         init_completion(&dc->out->user_vblank_comp);
 716         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
 717         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
 718 }
 719
 720 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
 721 (platform_t_phy_ns) ? ( \
 722 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
 723 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
 724 ((default_phy) < 0 ? 0 : (default_phy)))
 725
 726 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
 727                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
 728 {
 729         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 730                 dsi->info.phy_timing.t_tlpx_ns,
 731                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
 732
 733         phy_timing_clk->t_clktrail = SELECT_T_PHY(
 734                 dsi->info.phy_timing.t_clktrail_ns,
 735                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
 736
 737         phy_timing_clk->t_clkpost = SELECT_T_PHY(
 738                 dsi->info.phy_timing.t_clkpost_ns,
 739                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
 740
 741         phy_timing_clk->t_clkzero = SELECT_T_PHY(
 742                 dsi->info.phy_timing.t_clkzero_ns,
 743                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
 744
 745         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
 746                 dsi->info.phy_timing.t_clkprepare_ns,
 747                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
 748
 749         phy_timing_clk->t_clkpre = SELECT_T_PHY(
 750                 dsi->info.phy_timing.t_clkpre_ns,
 751                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
 752 }
 753
 754 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
 755                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
 756 {
 757         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 758                 dsi->info.phy_timing.t_tlpx_ns,
 759                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
 760
 761         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
 762                 dsi->info.phy_timing.t_hsdexit_ns,
 763                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
 764
 765         phy_timing_clk->t_hstrail = SELECT_T_PHY(
 766                 dsi->info.phy_timing.t_hstrail_ns,
 767                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
 768
 769         phy_timing_clk->t_datzero = SELECT_T_PHY(
 770                 dsi->info.phy_timing.t_datzero_ns,
 771                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
 772
 773         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
 774                 dsi->info.phy_timing.t_hsprepare_ns,
 775                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
 776 }
 777
 778 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
 779                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
 780 {
 781         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 782                 dsi->info.phy_timing.t_tlpx_ns,
 783                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
 784 }
 785
 786 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
 787                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
 788 {
 789         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 790                 dsi->info.phy_timing.t_tlpx_ns,
 791                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
 792
 793         phy_timing_clk->t_taget = SELECT_T_PHY(
 794                 dsi->info.phy_timing.t_taget_ns,
 795                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
 796
 797         phy_timing_clk->t_tasure = SELECT_T_PHY(
 798                 dsi->info.phy_timing.t_tasure_ns,
 799                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
 800
 801         phy_timing_clk->t_tago = SELECT_T_PHY(
 802                 dsi->info.phy_timing.t_tago_ns,
 803                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
 804 }
 805
 806 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
 807                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
 808 {
 809         phy_timing_clk->t_tlpx = SELECT_T_PHY(
 810                 dsi->info.phy_timing.t_tlpx_ns,
 811                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
 812
 813         phy_timing_clk->t_wakeup = SELECT_T_PHY(
 814                 dsi->info.phy_timing.t_wakeup_ns,
 815                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
 816 }
 817
 818 #undef SELECT_T_PHY
 819
 820 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
 821                                 struct dsi_phy_timing_inclk *phy_timing_clk,
 822                                 u32 clk_ns, u8 lphs)
 823 {
 824         if (!(dsi->info.ganged_type)) {
 825 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
 826                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
 827                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
 828 #endif
 829         }
 830
 831         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
 832                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
 833                         (T_HSEXIT_DEFAULT(clk_ns));
 834
 835         if (lphs == DSI_LPHS_IN_HS_MODE) {
 836                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
 837                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
 838         } else {
 839                 /* default is LP mode */
 840                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
 841                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
 842                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
 843                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
 844                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
 845         }
 846 }
 847
 848 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
 849                                 struct dsi_phy_timing_inclk *phy_timing,
 850                                 u32 clk_ns, u8 lphs)
 851 {
 852         int err = 0;
 853
 854 #define CHECK_RANGE(val, min, max) ( \
 855                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
 856                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
 857
 858 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
 859         clk_ns = dsi->info.fpga_freq_khz ?
 860                 ((1000 * 1000) / dsi->info.fpga_freq_khz) :
 861                 DEFAULT_FPGA_FREQ_KHZ;
 862 #endif
 863
 864         err = CHECK_RANGE(
 865         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 866                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
 867                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
 868         if (err < 0) {
 869                 dev_warn(&dsi->dc->ndev->dev,
 870                         "dsi: Tlpx mipi range violated\n");
 871                 goto fail;
 872         }
 873
 874         if (lphs == DSI_LPHS_IN_HS_MODE) {
 875                 err = CHECK_RANGE(
 876                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 877                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
 878                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
 879                 if (err < 0) {
 880                         dev_warn(&dsi->dc->ndev->dev,
 881                                 "dsi: HsExit mipi range violated\n");
 882                         goto fail;
 883                 }
 884
 885                 err = CHECK_RANGE(
 886                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 887                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
 888                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
 889                 if (err < 0) {
 890                         dev_warn(&dsi->dc->ndev->dev,
 891                                 "dsi: HsTrail mipi range violated\n");
 892                         goto fail;
 893                 }
 894
 895                 err = CHECK_RANGE(
 896                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 897                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
 898                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
 899                 if (err < 0) {
 900                         dev_warn(&dsi->dc->ndev->dev,
 901                                 "dsi: HsZero mipi range violated\n");
 902                         goto fail;
 903                 }
 904
 905                 err = CHECK_RANGE(
 906                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 907                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
 908                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
 909                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
 910                 if (err < 0) {
 911                         dev_warn(&dsi->dc->ndev->dev,
 912                                 "dsi: HsPrepare mipi range violated\n");
 913                         goto fail;
 914                 }
 915
 916                 err = CHECK_RANGE(
 917                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 918                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
 919                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 920                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
 921                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
 922                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
 923                 if (err < 0) {
 924                         dev_warn(&dsi->dc->ndev->dev,
 925                         "dsi: HsPrepare + HsZero mipi range violated\n");
 926                         goto fail;
 927                 }
 928         } else {
 929                 /* default is LP mode */
 930                 err = CHECK_RANGE(
 931                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 932                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
 933                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
 934                 if (err < 0) {
 935                         dev_warn(&dsi->dc->ndev->dev,
 936                                 "dsi: WakeUp mipi range violated\n");
 937                         goto fail;
 938                 }
 939
 940                 err = CHECK_RANGE(
 941                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 942                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
 943                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 944                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
 945                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 946                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
 947                 if (err < 0) {
 948                         dev_warn(&dsi->dc->ndev->dev,
 949                                 "dsi: TaSure mipi range violated\n");
 950                         goto fail;
 951                 }
 952         }
 953
 954         if (lphs == DSI_LPHS_IN_HS_MODE ||
 955                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
 956                 err = CHECK_RANGE(
 957                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 958                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
 959                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
 960                 if (err < 0) {
 961                         dev_warn(&dsi->dc->ndev->dev,
 962                                 "dsi: ClkTrail mipi range violated\n");
 963                         goto fail;
 964                 }
 965
 966                 err = CHECK_RANGE(
 967                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 968                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
 969                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
 970                 if (err < 0) {
 971                         dev_warn(&dsi->dc->ndev->dev,
 972                                 "dsi: ClkPost mipi range violated\n");
 973                         goto fail;
 974                 }
 975
 976                 err = CHECK_RANGE(
 977                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 978                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
 979                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
 980                 if (err < 0) {
 981                         dev_warn(&dsi->dc->ndev->dev,
 982                                 "dsi: ClkZero mipi range violated\n");
 983                         goto fail;
 984                 }
 985
 986                 err = CHECK_RANGE(
 987                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 988                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
 989                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
 990                 if (err < 0) {
 991                         dev_warn(&dsi->dc->ndev->dev,
 992                                 "dsi: ClkPrepare mipi range violated\n");
 993                         goto fail;
 994                 }
 995
 996                 err = CHECK_RANGE(
 997                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
 998                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
 999                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
1000                 if (err < 0) {
1001                         dev_warn(&dsi->dc->ndev->dev,
1002                                 "dsi: ClkPre mipi range violated\n");
1003                         goto fail;
1004                 }
1005
1006                 err = CHECK_RANGE(
1007                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1008                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1009                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1010                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
1011                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
1012                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
1013                 if (err < 0) {
1014                         dev_warn(&dsi->dc->ndev->dev,
1015                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1016                         goto fail;
1017                 }
1018         }
1019 fail:
1020 #undef CHECK_RANGE
1021         return err;
1022 }
1023
1024 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1025                                 struct dsi_phy_timing_inclk *phy_timing,
1026                                 u32 clk_ns, u8 lphs)
1027 {
1028         u32 hs_t_phy_ns;
1029         u32 clk_t_phy_ns;
1030         u32 t_phy_ns;
1031         u32 h_blank_ns;
1032         struct tegra_dc_mode *modes;
1033         u32 t_pix_ns;
1034         int err = 0;
1035
1036         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1037                 goto fail;
1038
1039         modes = dsi->dc->out->modes;
1040         t_pix_ns = clk_ns * BITS_PER_BYTE *
1041                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1042
1043         hs_t_phy_ns =
1044                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1045                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1046                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1047                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1048                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1049                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1050                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1051                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1052                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1053                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1054
1055         clk_t_phy_ns =
1056                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1057                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1058                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1059                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1060                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1061                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1062                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1063                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1064                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1065                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1066                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1067                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1068                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1069                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1070
1071         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1072                                                 modes->h_front_porch);
1073
1074         /* Extra tlpx and byte cycle required by dsi HW */
1075         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1076                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1077                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1078                 clk_ns * BITS_PER_BYTE);
1079
1080         if (h_blank_ns < t_phy_ns) {
1081                 err = -EINVAL;
1082                 dev_err(&dsi->dc->ndev->dev,
1083                         "dsi: Hblank is smaller than HS trans phy timing\n");
1084                 goto fail;
1085         }
1086
1087         return 0;
1088 fail:
1089         return err;
1090 }
1091
1092 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1093                                 struct dsi_phy_timing_inclk *phy_timing,
1094                                 u32 clk_ns, u8 lphs)
1095 {
1096         int err = 0;
1097
1098         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1099         if (err < 0) {
1100                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1101                 goto fail;
1102         }
1103
1104         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1105         if (err < 0) {
1106                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1107                 goto fail;
1108         }
1109
1110         /* TODO: add more contraints */
1111 fail:
1112         return err;
1113 }
1114
1115 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1116 {
1117         u32 val;
1118         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1119
1120         tegra_dsi_get_phy_timing
1121                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1122
1123         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1124                                         dsi->current_bit_clk_ns, lphs);
1125
1126         if (dsi->info.ganged_type) {
1127 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1128                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1129                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1130                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1131                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1132
1133                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1134                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1135                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1136                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1137
1138                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1139                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1140                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1141
1142                 phy_timing.t_taget += T_TAGET_HW_INC;
1143                 phy_timing.t_tasure += T_TASURE_HW_INC;
1144                 phy_timing.t_tago += T_TAGO_HW_INC;
1145 #endif
1146         }
1147         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1148                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1149                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1150                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1151         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1152
1153         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1154                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1155                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1156                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1157         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1158
1159         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1160                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1161                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1162         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1163
1164         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1165                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1166                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1167         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1168
1169         dsi->phy_timing = phy_timing;
1170 }
1171
1172 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1173                                 struct tegra_dc_dsi_data *dsi)
1174 {
1175         u32 dsi_to_pixel_clk_ratio;
1176         u32 temp;
1177         u32 temp1;
1178         u32 mipi_clk_adj_kHz = 0;
1179         u32 sol_delay;
1180         struct tegra_dc_mode *dc_modes = &dc->mode;
1181
1182         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1183         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1184                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1185
1186         /* Convert Fdsi to byte format */
1187         dsi_to_pixel_clk_ratio *= 1000/8;
1188
1189         /* Multiplying by 1000 so that we don't loose the fraction part */
1190         temp = dc_modes->h_active * 1000;
1191         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1192                         dc_modes->h_sync_width;
1193
1194         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1195                         temp * dsi->pixel_scaler_mul /
1196                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1197
1198         /* Do rounding on sol delay */
1199         sol_delay = (sol_delay + 1000 - 1)/1000;
1200
1201         /* TODO:
1202          * 1. find out the correct sol fifo depth to use
1203          * 2. verify with hw about the clamping function
1204          */
1205         if (sol_delay > (480 * 4)) {
1206                 sol_delay = (480 * 4);
1207                 mipi_clk_adj_kHz = sol_delay +
1208                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1209                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1210
1211                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1212
1213                 mipi_clk_adj_kHz *= 4;
1214         }
1215
1216         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1217
1218         return sol_delay;
1219 }
1220
1221 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1222                                 struct tegra_dc_dsi_data *dsi)
1223 {
1224         u32 sol_delay;
1225         u32 internal_delay;
1226         u32 h_width_byte_clk;
1227         u32 h_width_pixels;
1228         u32 h_width_ganged_byte_clk;
1229         u8 n_data_lanes_this_cont = 0;
1230         u8 n_data_lanes_ganged = 0;
1231
1232         if (!(dsi->info.ganged_type)) {
1233                 if (dsi->info.video_burst_mode ==
1234                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1235                         dsi->info.video_burst_mode ==
1236                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1237 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1238                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1239                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1240 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1241                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1242                 } else {
1243                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1244                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1245                 }
1246         } else {
1247 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1248 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1249 #define FIFO_WR_PIX_CLK_DELAY 2
1250 #define FIFO_RD_BYTE_CLK_DELAY 6
1251 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1252                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1253                                 FIFO_WR_PIX_CLK_DELAY)
1254
1255                 internal_delay = DIV_ROUND_UP(
1256                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1257                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1258                                 + FIFO_RD_BYTE_CLK_DELAY;
1259
1260                 h_width_pixels = dc->mode.h_sync_width +
1261                                         dc->mode.h_back_porch +
1262                                         dc->mode.h_active +
1263                                         dc->mode.h_front_porch;
1264
1265                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1266                                         dsi->pixel_scaler_mul,
1267                                         dsi->pixel_scaler_div *
1268                                         dsi->info.n_data_lanes);
1269
1270                 if (dsi->info.ganged_type ==
1271                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1272                         dsi->info.ganged_type ==
1273                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1274                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1275                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1276                 }
1277
1278                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1279                                         n_data_lanes_this_cont *
1280                                         h_width_byte_clk,
1281                                         n_data_lanes_ganged);
1282
1283                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1284                                                         internal_delay;
1285                 sol_delay = (dsi->info.video_data_type ==
1286                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1287                                 sol_delay + 20: sol_delay;
1288
1289 #undef SOL_TO_VALID_PIX_CLK_DELAY
1290 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1291 #undef FIFO_WR_PIX_CLK_DELAY
1292 #undef FIFO_RD_BYTE_CLK_DELAY
1293 #undef TOT_INTERNAL_PIX_DELAY
1294         }
1295
1296         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1297                                                 DSI_SOL_DELAY);
1298 }
1299
1300 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1301 {
1302         u32 val;
1303         u32 bytes_per_frame;
1304         u32 timeout = 0;
1305
1306         /* TODO: verify the following equation */
1307         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1308                                                 (dsi->info.refresh_rate * 8);
1309         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1310         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1311
1312         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1313                         DSI_TIMEOUT_0_HTX_TO(timeout);
1314         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1315
1316         if (dsi->info.panel_reset_timeout_msec)
1317                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1318                                         / dsi->current_bit_clk_ns;
1319         else
1320                 timeout = DSI_PR_TO_VALUE;
1321
1322         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1323                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1324         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1325
1326         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1327                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1328                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1329                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1330         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1331 }
1332
1333 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1334                                                 struct tegra_dc_dsi_data *dsi)
1335 {
1336         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1337         u32 hact_pkt_len_pix = 0;
1338         u32 hact_pkt_len_bytes = 0;
1339         u32 hfp_pkt_len_bytes = 0;
1340         u32 pix_per_line_orig = 0;
1341         u32 pix_per_line = 0;
1342         u32 val = 0;
1343
1344 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1345 #define HEADER_OVERHEAD 16
1346
1347         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1348                         dc->mode.h_active + dc->mode.h_front_porch;
1349
1350         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1351                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1352                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1353                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1354                 if (dsi->controller_index) {
1355                         hact_pkt_len_pix =
1356                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1357                         pix_per_line = pix_per_line_orig - pix_per_line;
1358                 }
1359                 hact_pkt_len_bytes = hact_pkt_len_pix *
1360                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1361                 hfp_pkt_len_bytes = pix_per_line *
1362                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1363                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1364         }
1365
1366         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1367                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1368         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1369
1370         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1371                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1372         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1373
1374         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1375                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1376         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1377
1378         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1379                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1380         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1381
1382 #undef HEADER_OVERHEAD
1383 }
1384
1385 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1386                                                 struct tegra_dc_dsi_data *dsi)
1387 {
1388         u32 val;
1389         u32 hact_pkt_len;
1390         u32 hsa_pkt_len;
1391         u32 hbp_pkt_len;
1392         u32 hfp_pkt_len;
1393
1394         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1395                                                         dsi->pixel_scaler_div;
1396         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1397                                                         dsi->pixel_scaler_div;
1398         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1399                                                         dsi->pixel_scaler_div;
1400         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1401                                                         dsi->pixel_scaler_div;
1402
1403         if (dsi->info.video_burst_mode !=
1404                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1405                 hbp_pkt_len += hsa_pkt_len;
1406
1407         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1408         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1409         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1410
1411         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1412                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1413         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1414
1415         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1416                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1417         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1418
1419         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1420                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1421         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1422
1423         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1424         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1425 }
1426
1427 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1428                                                 struct tegra_dc_dsi_data *dsi)
1429 {
1430         unsigned long   val;
1431         unsigned long   act_bytes;
1432
1433         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1434                         dsi->pixel_scaler_div + 1;
1435
1436         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1437         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1438
1439         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1440         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1441
1442         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1443         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1444
1445         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1446         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1447 }
1448
1449 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1450                                 struct tegra_dc_dsi_data *dsi)
1451 {
1452         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1453                 return;
1454
1455         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1456                 if (dsi->info.ganged_type)
1457                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1458                 else
1459                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1460         } else {
1461                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1462         }
1463 }
1464
1465 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1466                                 struct tegra_dc_dsi_data *dsi)
1467 {
1468         const u32 *pkt_seq;
1469         u32 rgb_info;
1470         u32 pkt_seq_3_5_rgb_lo;
1471         u32 pkt_seq_3_5_rgb_hi;
1472         u32     val;
1473         u32 reg;
1474         u8  i;
1475
1476         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1477                 return;
1478
1479         switch (dsi->info.pixel_format) {
1480         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1481                 rgb_info = CMD_RGB_16BPP;
1482                 break;
1483         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1484                 rgb_info = CMD_RGB_18BPP;
1485                 break;
1486         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1487                 rgb_info = CMD_RGB_18BPPNP;
1488                 break;
1489         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1490         default:
1491                 rgb_info = CMD_RGB_24BPP;
1492                 break;
1493         }
1494
1495         pkt_seq_3_5_rgb_lo = 0;
1496         pkt_seq_3_5_rgb_hi = 0;
1497         if (dsi->info.pkt_seq)
1498                 pkt_seq = dsi->info.pkt_seq;
1499         else if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1500                 pkt_seq = dsi_pkt_seq_cmd_mode;
1501         else {
1502                 switch (dsi->info.video_burst_mode) {
1503                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1504                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1505                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1506                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1507                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1508                         pkt_seq_3_5_rgb_lo =
1509                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1510                         if (!dsi->info.no_pkt_seq_eot)
1511                                 pkt_seq = dsi_pkt_seq_video_burst;
1512                         else
1513                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1514                         break;
1515                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1516                         pkt_seq_3_5_rgb_hi =
1517                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1518                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1519                         break;
1520                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1521                 default:
1522                         if (dsi->info.ganged_type) {
1523                                 pkt_seq_3_5_rgb_lo =
1524                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1525                                 pkt_seq =
1526                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1527                         } else {
1528                                 pkt_seq_3_5_rgb_lo =
1529                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1530                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1531                         }
1532                         break;
1533                 }
1534         }
1535
1536         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1537                 val = pkt_seq[i];
1538                 reg = dsi_pkt_seq_reg[i];
1539                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1540                         val |= pkt_seq_3_5_rgb_lo;
1541                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1542                         val |= pkt_seq_3_5_rgb_hi;
1543                 tegra_dsi_writel(dsi, val, reg);
1544         }
1545 }
1546
1547 static void tegra_dsi_reset_underflow_overflow
1548                                 (struct tegra_dc_dsi_data *dsi)
1549 {
1550         u32 val;
1551
1552         val = tegra_dsi_readl(dsi, DSI_STATUS);
1553         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1554         if (val) {
1555                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1556                         dev_warn(&dsi->dc->ndev->dev,
1557                                 "dsi: video fifo overflow. Resetting flag\n");
1558                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1559                         dev_warn(&dsi->dc->ndev->dev,
1560                                 "dsi: video fifo underflow. Resetting flag\n");
1561                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1562                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1563                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1564                 udelay(5);
1565         }
1566 }
1567
1568 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1569 {
1570         u32 trigger;
1571         u32 val;
1572         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1573         struct tegra_dc_mode mode = dsi->dc->mode;
1574         u32 line_period = DIV_ROUND_UP(
1575                                 MS_TO_US(frame_period),
1576                                 mode.v_sync_width + mode.v_back_porch +
1577                                 mode.v_active + mode.v_front_porch);
1578         u32 timeout_cnt = 0;
1579
1580 #define DSI_IDLE_TIMEOUT        1000
1581
1582         val = tegra_dsi_readl(dsi, DSI_STATUS);
1583         while (!(val & DSI_STATUS_IDLE(0x1))) {
1584                 cpu_relax();
1585                 udelay(line_period);
1586                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1587                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1588                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1589                         break;
1590                 }
1591         }
1592
1593         tegra_dsi_writel(dsi,
1594                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1595                 DSI_POWER_CONTROL);
1596         /* stabilization delay */
1597         udelay(300);
1598
1599         tegra_dsi_writel(dsi,
1600                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1601                 DSI_POWER_CONTROL);
1602         /* stabilization delay */
1603         udelay(300);
1604
1605         /* dsi HW does not clear host trigger bit automatically
1606          * on dsi interface disable if host fifo is empty or in mid
1607          * of host transmission
1608          */
1609         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1610         if (trigger)
1611                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1612
1613 #undef DSI_IDLE_TIMEOUT
1614 }
1615
1616 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1617                                         struct tegra_dc_dsi_data *dsi)
1618 {
1619         /* extra reference to dc clk */
1620         clk_prepare_enable(dc->clk);
1621
1622         /* Mask the MSF interrupt. */
1623         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1624                 tegra_dc_mask_interrupt(dc, MSF_INT);
1625
1626         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1627         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1628         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1629         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1630
1631         /* balance extra dc clk reference */
1632         clk_disable_unprepare(dc->clk);
1633
1634         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1635 }
1636
1637 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1638                                 struct tegra_dc_dsi_data *dsi,
1639                                 u32 timeout_n_frames)
1640 {
1641         int val;
1642         long timeout;
1643         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1644         struct tegra_dc_mode mode = dc->mode;
1645         u32 line_period = DIV_ROUND_UP(
1646                                 MS_TO_US(frame_period),
1647                                 mode.v_sync_width + mode.v_back_porch +
1648                                 mode.v_active + mode.v_front_porch);
1649
1650         if (timeout_n_frames < 2)
1651                 dev_WARN(&dc->ndev->dev,
1652                 "dsi: to stop at next frame give at least 2 frame delay\n");
1653
1654         INIT_COMPLETION(dc->frame_end_complete);
1655
1656         /* unmask frame end interrupt */
1657         val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1658
1659         timeout = wait_for_completion_interruptible_timeout(
1660                         &dc->frame_end_complete,
1661                         msecs_to_jiffies(timeout_n_frames * frame_period));
1662
1663         /* reinstate interrupt mask */
1664         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1665
1666         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1667         udelay(mode.v_ref_to_sync * line_period);
1668
1669         return timeout;
1670 }
1671
1672 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1673                                                 struct tegra_dc_dsi_data *dsi,
1674                                                 u32 timeout_n_frames)
1675 {
1676         long timeout;
1677
1678         tegra_dsi_stop_dc_stream(dc, dsi);
1679
1680         timeout = tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1681
1682         tegra_dsi_soft_reset(dsi);
1683
1684         if (timeout == 0)
1685                 dev_warn(&dc->ndev->dev,
1686                         "DC doesn't stop at end of frame.\n");
1687
1688         tegra_dsi_reset_underflow_overflow(dsi);
1689 }
1690
1691 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1692                                         struct tegra_dc_dsi_data *dsi)
1693 {
1694         u32 val;
1695
1696         /* take extra reference to dc clk */
1697         clk_prepare_enable(dc->clk);
1698
1699         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1700
1701         /* TODO: clean up */
1702         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1703                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1704                         DC_CMD_DISPLAY_POWER_CONTROL);
1705
1706         /* Configure one-shot mode or continuous mode */
1707         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1708                 /* disable LSPI/LCD_DE output */
1709                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1710                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1711
1712                 /* enable MSF & set MSF polarity */
1713                 val = MSF_ENABLE | MSF_LSPI;
1714                 if (!dsi->info.te_polarity_low)
1715                         val |= MSF_POLARITY_HIGH;
1716                 else
1717                         val |= MSF_POLARITY_LOW;
1718                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1719
1720                 /* set non-continuous mode */
1721                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1722                                                 DC_CMD_DISPLAY_COMMAND);
1723                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1724                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1725                                                 DC_CMD_STATE_CONTROL);
1726
1727                 /* Unmask the MSF interrupt. */
1728                 tegra_dc_unmask_interrupt(dc, MSF_INT);
1729         } else {
1730                 /* set continuous mode */
1731                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1732                                                 DC_CMD_DISPLAY_COMMAND);
1733                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1734                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1735         }
1736
1737         /* balance extra dc clk reference */
1738         clk_disable_unprepare(dc->clk);
1739
1740         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1741 }
1742
1743 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1744                                 struct tegra_dc_dsi_data *dsi)
1745 {
1746         u32 shift_clk_div_register;
1747         u32 val;
1748
1749         /* formula: (dsi->shift_clk_div - 1) * 2 */
1750         shift_clk_div_register = (dsi->shift_clk_div.mul -
1751                                 dsi->shift_clk_div.div) * 2 /
1752                                 dsi->shift_clk_div.div;
1753
1754 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1755         shift_clk_div_register = 1;
1756         if (dsi->info.ganged_type)
1757                 shift_clk_div_register = 0;
1758 #endif
1759
1760         val = PIXEL_CLK_DIVIDER_PCD1 |
1761                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1762
1763         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1764          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1765          * After 2us delay, write the target values to it. */
1766 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1767         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1768         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1769         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1770
1771         udelay(2);
1772 #endif
1773
1774         /* TODO: find out if PCD3 option is required */
1775         val = PIXEL_CLK_DIVIDER_PCD1 |
1776                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1777
1778         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1779 }
1780
1781 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1782                         struct tegra_dc_dsi_data *dsi, u32 clk)
1783 {
1784         u32 rm;
1785         u32 pclk_khz;
1786
1787         /* Round up to MHz */
1788         rm = clk % 1000;
1789         if (rm != 0)
1790                 clk -= rm;
1791
1792         /* Set up pixel clock */
1793         pclk_khz = (clk * dsi->shift_clk_div.div) /
1794                                 dsi->shift_clk_div.mul;
1795
1796         dc->mode.pclk = pclk_khz * 1000;
1797
1798         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1799         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1800
1801         /* TODO: Define one shot work delay in board file. */
1802         /* Since for one-shot mode, refresh rate is usually set larger than
1803          * expected refresh rate, it needs at least 3 frame period. Less
1804          * delay one shot work is, more powering saving we have. */
1805         dc->one_shot_delay_ms = 4 *
1806                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1807
1808         /* Enable DSI clock */
1809         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1810         tegra_dsi_clk_enable(dsi);
1811         tegra_periph_reset_deassert(dsi->dsi_clk);
1812
1813         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1814         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1815 }
1816
1817 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1818 {
1819         u32 val;
1820
1821         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1822         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1823
1824         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1825                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1826                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1827         } else {
1828                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1829                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1830         }
1831         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1832
1833         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1834         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1835         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1836         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1837
1838         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1839 }
1840
1841 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1842 {
1843         u32 val;
1844         tegra_dsi_hs_clk_out_enable(dsi);
1845
1846         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1847         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1848         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1849         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1850 }
1851
1852 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1853                                                 struct tegra_dc_dsi_data *dsi)
1854 {
1855         u32 val;
1856
1857         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1858                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1859
1860         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1861         /* stabilization delay */
1862         udelay(300);
1863
1864         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1865         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1866         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1867         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1868
1869         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1870         /* stabilization delay */
1871         udelay(300);
1872
1873         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1874         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1875 }
1876
1877 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1878 {
1879         u32 dsi_control;
1880         u32 host_dsi_control;
1881         u32 max_threshold;
1882
1883         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1884         host_dsi_control = HOST_DSI_CTRL_COMMON |
1885                         HOST_DSI_CTRL_HOST_DRIVEN |
1886                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1887         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1888
1889         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1890         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1891         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1892
1893         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1894         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1895         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1896 }
1897
1898 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1899                                                 u8 driven_mode)
1900 {
1901         u32 dsi_control;
1902         u32 host_dsi_control;
1903         u32 max_threshold;
1904         u32 dcs_cmd;
1905
1906         dsi_control = dsi->dsi_control_val;
1907         host_dsi_control = HOST_DSI_CTRL_COMMON;
1908         max_threshold = 0;
1909         dcs_cmd = 0;
1910
1911         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1912                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1913                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1914                 max_threshold =
1915                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1916                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1917         } else {
1918                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1919                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1920                 max_threshold =
1921                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1922                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1923
1924                 if (dsi->info.video_data_type ==
1925                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1926                         dsi_control |= DSI_CTRL_CMD_MODE;
1927                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1928                                 DSI_WRITE_MEMORY_START)|
1929                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1930                                 DSI_WRITE_MEMORY_CONTINUE);
1931                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1932                 } else {
1933                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1934                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1935                 }
1936         }
1937
1938         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1939         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1940         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1941         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1942 }
1943
1944 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1945 {
1946         u32 val;
1947
1948         if (dsi->info.controller_vs == DSI_VS_1) {
1949                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1950                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1951                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1952                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1953                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1954                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1955                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1956                                                 (TEGRA_DSI_PAD_DISABLE) |
1957                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1958                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1959                                                 (TEGRA_DSI_PAD_DISABLE);
1960                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1961         } else {
1962                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1963                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1964                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1965                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1966                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1967                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1968                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1969                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1970         }
1971 }
1972
1973 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1974 {
1975         u32 val;
1976
1977         if (dsi->info.controller_vs == DSI_VS_1) {
1978                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1979                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1980                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1981                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1982                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1983                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1984                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
1985                                                 TEGRA_DSI_PAD_ENABLE) |
1986                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
1987                                                 TEGRA_DSI_PAD_ENABLE) |
1988                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
1989                                                 TEGRA_DSI_PAD_ENABLE);
1990                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1991         } else {
1992                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1993                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1994                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1995                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1996                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1997                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
1998                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
1999                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2000         }
2001 }
2002
2003 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2004 {
2005         u32 val;
2006
2007         if (!dsi->ulpm)
2008                 tegra_dsi_pad_enable(dsi);
2009         else
2010                 tegra_dsi_pad_disable(dsi);
2011
2012         if (dsi->info.controller_vs == DSI_VS_1) {
2013                 /* TODO: characterization parameters */
2014                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2015
2016                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2017
2018                 tegra_mipi_cal_write(dsi->mipi_cal,
2019                                 MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2020                                 MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2021                 tegra_mipi_cal_write(dsi->mipi_cal,
2022                                 PAD_PDVREG(0x0),
2023                                 MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2024
2025                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2026         } else {
2027                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2028                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2029                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2030                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2031                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2032                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2033
2034                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2035                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2036                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2037                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2038                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2039
2040                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2041
2042                 val = MIPI_CAL_TERMOSA(0x4);
2043                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2044
2045                 val = MIPI_CAL_TERMOSB(0x4);
2046                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2047
2048                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2049                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2050
2051                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2052                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2053         }
2054
2055         val = PAD_CIL_PDVREG(0x0);
2056         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2057 }
2058
2059 static void tegra_dsi_panelB_enable(void)
2060 {
2061         unsigned int val;
2062
2063         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2064         val |= DSIB_MODE_ENABLE;
2065         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2066 }
2067
2068 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2069                                 struct tegra_dc_dsi_data *dsi)
2070 {
2071         u32 i;
2072
2073         regulator_enable(dsi->avdd_dsi_csi);
2074         /* stablization delay */
2075         mdelay(50);
2076
2077         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2078
2079         /* Stop DC stream before configuring DSI registers
2080          * to avoid visible glitches on panel during transition
2081          * from bootloader to kernel driver
2082          */
2083         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2084
2085         tegra_dsi_writel(dsi,
2086                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2087                 DSI_POWER_CONTROL);
2088         /* stabilization delay */
2089         udelay(300);
2090
2091         if (dsi->info.dsi_instance)
2092                 tegra_dsi_panelB_enable();
2093
2094         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2095
2096         /* Initialize DSI registers */
2097         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2098                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2099         if (dsi->info.controller_vs == DSI_VS_1) {
2100                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2101                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2102         }
2103
2104         tegra_dsi_pad_calibration(dsi);
2105
2106         tegra_dsi_writel(dsi,
2107                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2108                 DSI_POWER_CONTROL);
2109         /* stabilization delay */
2110         udelay(300);
2111
2112         dsi->status.init = DSI_MODULE_INIT;
2113         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2114         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2115         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2116         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2117         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2118         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2119         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2120         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2121
2122         return 0;
2123 }
2124
2125 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2126                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2127 {
2128         int err;
2129
2130         if (dsi->status.init != DSI_MODULE_INIT) {
2131                 err = -EPERM;
2132                 goto fail;
2133         }
2134
2135         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2136                         dsi->status.lp_op == lp_op)
2137                 goto success;
2138
2139         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2140                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2141
2142         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2143         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2144                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2145                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2146
2147         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2148         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2149                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2150                 tegra_dsi_set_timeout(dsi);
2151         }
2152
2153         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2154
2155         tegra_dsi_set_control_reg_lp(dsi);
2156
2157         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2158                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2159                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2160
2161         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2162         dsi->status.lp_op = lp_op;
2163         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2164 success:
2165         err = 0;
2166 fail:
2167         return err;
2168 }
2169
2170 static void tegra_dsi_ganged(struct tegra_dc *dc,
2171                                 struct tegra_dc_dsi_data *dsi)
2172 {
2173         u32 start = 0;
2174         u32 low_width = 0;
2175         u32 high_width = 0;
2176         u32 h_active = dc->out->modes->h_active;
2177         u32 val = 0;
2178
2179         if (dsi->info.controller_vs < DSI_VS_1) {
2180                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2181                 "supported with current controller version\n");
2182                 return;
2183         }
2184
2185         if (dsi->info.ganged_type ==
2186                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2187                 low_width = DIV_ROUND_UP(h_active, 2);
2188                 high_width = h_active - low_width;
2189                 if (dsi->controller_index)
2190                         start = h_active / 2;
2191                 else
2192                         start = 0;
2193         } else if (dsi->info.ganged_type ==
2194                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2195                 low_width = 0x1;
2196                 high_width = 0x1;
2197                 if (dsi->controller_index)
2198                         start = 1;
2199                 else
2200                         start = 0;
2201         }
2202
2203         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2204                                                 DSI_GANGED_MODE_START);
2205
2206         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2207                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2208         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2209
2210         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2211                                                 DSI_GANGED_MODE_CONTROL);
2212 }
2213
2214 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2215                                         struct tegra_dc_dsi_data *dsi,
2216                                         u8 driven_mode)
2217 {
2218         int err;
2219
2220         if (dsi->status.init != DSI_MODULE_INIT) {
2221                 err = -EPERM;
2222                 goto fail;
2223         }
2224
2225         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2226                 dsi->driven_mode == driven_mode)
2227                 goto success;
2228
2229         dsi->driven_mode = driven_mode;
2230
2231         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2232                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2233
2234         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2235                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2236                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2237
2238         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2239                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2240                 tegra_dsi_set_timeout(dsi);
2241         }
2242
2243         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2244
2245         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2246                 tegra_dsi_set_pkt_seq(dc, dsi);
2247                 tegra_dsi_set_pkt_length(dc, dsi);
2248                 tegra_dsi_set_sol_delay(dc, dsi);
2249                 tegra_dsi_set_dc_clk(dc, dsi);
2250         }
2251
2252         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2253
2254         if (dsi->info.ganged_type)
2255                 tegra_dsi_ganged(dc, dsi);
2256
2257         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2258                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2259                 tegra_dsi_hs_clk_out_enable(dsi);
2260
2261         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2262 success:
2263         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2264         err = 0;
2265 fail:
2266         return err;
2267 }
2268
2269 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2270 {
2271         u32 timeout = 0;
2272         bool retVal = true;
2273
2274         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2275                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2276                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2277                         retVal = false;
2278                         break;
2279                 }
2280                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2281                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2282         }
2283
2284         return retVal;
2285 }
2286
2287 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2288 {
2289         u32 timeout = 0;
2290         bool retVal = true;
2291
2292         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2293                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2294                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2295                         retVal = false;
2296                         break;
2297                 }
2298                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2299                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2300         }
2301
2302         return retVal;
2303 }
2304
2305 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2306 {
2307         int err = 0;
2308
2309         if (tegra_dsi_write_busy(dsi)) {
2310                 err = -EBUSY;
2311                 dev_err(&dsi->dc->ndev->dev,
2312                         "DSI trigger bit already set\n");
2313                 goto fail;
2314         }
2315
2316         if (tegra_dsi_read_busy(dsi)) {
2317                 err = -EBUSY;
2318                 dev_err(&dsi->dc->ndev->dev,
2319                         "DSI immediate bta bit already set\n");
2320                 goto fail;
2321         }
2322 fail:
2323         return (err < 0 ? true : false);
2324 }
2325
2326 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2327 {
2328         u32 val;
2329
2330         val = tegra_dsi_readl(dsi, DSI_STATUS);
2331         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2332         if (val) {
2333                 dev_warn(&dsi->dc->ndev->dev,
2334                         "DSI read count not zero, resetting\n");
2335                 tegra_dsi_soft_reset(dsi);
2336         }
2337 }
2338
2339 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2340                                                 struct tegra_dc_dsi_data *dsi,
2341                                                 struct tegra_dc *dc,
2342                                                 u8 lp_op)
2343 {
2344         struct dsi_status *init_status = NULL;
2345         int err;
2346
2347         if (dsi->status.init != DSI_MODULE_INIT ||
2348                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2349                 err = -EPERM;
2350                 goto fail;
2351         }
2352
2353         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2354         if (!init_status)
2355                 return ERR_PTR(-ENOMEM);
2356
2357         *init_status = dsi->status;
2358
2359         if (dsi->info.hs_cmd_mode_supported) {
2360                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2361                                 TEGRA_DSI_DRIVEN_BY_HOST);
2362                 if (err < 0) {
2363                         dev_err(&dc->ndev->dev,
2364                         "Switch to HS host mode failed\n");
2365                         goto fail;
2366                 }
2367
2368                 goto success;
2369         }
2370
2371         if (dsi->status.lp_op != lp_op) {
2372                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2373                 if (err < 0) {
2374                         dev_err(&dc->ndev->dev,
2375                         "DSI failed to go to LP mode\n");
2376                         goto fail;
2377                 }
2378         }
2379 success:
2380         return init_status;
2381 fail:
2382         kfree(init_status);
2383         return ERR_PTR(err);
2384 }
2385
2386 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2387                                 struct tegra_dc *dc,
2388                                 struct tegra_dc_dsi_data *dsi,
2389                                 u8 lp_op)
2390 {
2391         int err = 0;
2392         struct dsi_status *init_status;
2393         bool restart_dc_stream = false;
2394
2395         if (dsi->status.init != DSI_MODULE_INIT ||
2396                 dsi->ulpm) {
2397                 err = -EPERM;
2398                 goto fail;
2399         }
2400
2401         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2402                 restart_dc_stream = true;
2403                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2404         }
2405
2406         if (tegra_dsi_host_busy(dsi)) {
2407                 tegra_dsi_soft_reset(dsi);
2408                 if (tegra_dsi_host_busy(dsi)) {
2409                         err = -EBUSY;
2410                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2411                         goto fail;
2412                 }
2413         }
2414
2415         if (lp_op == DSI_LP_OP_READ)
2416                 tegra_dsi_reset_read_count(dsi);
2417
2418         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2419                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2420                 if (err < 0) {
2421                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2422                         goto fail;
2423                 }
2424         }
2425
2426         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2427                                         (dsi, dc, lp_op);
2428         if (IS_ERR_OR_NULL(init_status)) {
2429                 err = PTR_ERR(init_status);
2430                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2431                 goto fail;
2432         }
2433
2434         if (restart_dc_stream)
2435                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2436
2437         if (atomic_read(&dsi_syncpt_rst))
2438                 tegra_dsi_syncpt_reset(dsi);
2439
2440         return init_status;
2441 fail:
2442         return ERR_PTR(err);
2443 }
2444
2445 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2446                                 struct tegra_dc_dsi_data *dsi,
2447                                 struct dsi_status *init_status)
2448 {
2449         int err = 0;
2450
2451         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2452                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2453                 if (err < 0) {
2454                         dev_err(&dc->ndev->dev,
2455                                 "Failed to config LP mode\n");
2456                         goto fail;
2457                 }
2458                 goto success;
2459         }
2460
2461         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2462                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2463                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2464                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2465                 if (err < 0) {
2466                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2467                         goto fail;
2468                 }
2469         }
2470
2471         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2472                 tegra_dsi_start_dc_stream(dc, dsi);
2473 success:
2474 fail:
2475         kfree(init_status);
2476         return err;
2477 }
2478
2479 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2480 {
2481         int status = 0;
2482
2483         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2484                 status = -EBUSY;
2485                 goto fail;
2486         }
2487
2488         tegra_dsi_writel(dsi,
2489                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2490
2491 #if DSI_USE_SYNC_POINTS
2492         status = tegra_dsi_syncpt(dsi);
2493         if (status < 0) {
2494                 dev_err(&dsi->dc->ndev->dev,
2495                         "DSI syncpt for host trigger failed\n");
2496                 goto fail;
2497         }
2498 #else
2499         if (tegra_dsi_write_busy(dsi)) {
2500                 status = -EBUSY;
2501                 dev_err(&dsi->dc->ndev->dev,
2502                         "Timeout waiting on write completion\n");
2503         }
2504 #endif
2505
2506 fail:
2507         return status;
2508 }
2509
2510 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2511                                         u8 *pdata, u8 data_id, u16 data_len)
2512 {
2513         u8 virtual_channel;
2514         u32 val;
2515         int err;
2516
2517         err = 0;
2518
2519         virtual_channel = dsi->info.virtual_channel <<
2520                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2521
2522         /* always use hw for ecc */
2523         val = (virtual_channel | data_id) << 0 |
2524                         data_len << 8;
2525         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2526
2527         /* if pdata != NULL, pkt type is long pkt */
2528         if (pdata != NULL) {
2529                 while (data_len) {
2530                         if (data_len >= 4) {
2531                                 val = ((u32 *) pdata)[0];
2532                                 data_len -= 4;
2533                                 pdata += 4;
2534                         } else {
2535                                 val = 0;
2536                                 memcpy(&val, pdata, data_len);
2537                                 pdata += data_len;
2538                                 data_len = 0;
2539                         }
2540                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2541                 }
2542         }
2543
2544         err = tegra_dsi_host_trigger(dsi);
2545         if (err < 0)
2546                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2547
2548         return err;
2549 }
2550
2551 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2552 {
2553         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2554
2555         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2556                 /* extra reference to dsi clk */
2557                 clk_prepare_enable(dsi->dsi_clk);
2558                 atomic_inc(&dsi->host_ref);
2559                 tegra_dsi_host_resume(dc);
2560         }
2561 }
2562
2563 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2564 {
2565         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2566
2567         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2568                 atomic_dec(&dsi->host_ref);
2569
2570                 if (!atomic_read(&dsi->host_ref) &&
2571                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2572                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2573
2574                 /* balance extra dsi clk reference */
2575                 clk_disable_unprepare(dsi->dsi_clk);
2576         }
2577 }
2578
2579 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2580 {
2581         struct tegra_dc_dsi_data *dsi = container_of(
2582                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2583
2584         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2585                 tegra_dsi_host_suspend(dsi->dc);
2586 }
2587
2588 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2589                         struct tegra_dc_dsi_data *dsi,
2590                         u8 *pdata, u8 data_id, u16 data_len)
2591 {
2592         int err = 0;
2593         struct dsi_status *init_status;
2594
2595         init_status = tegra_dsi_prepare_host_transmission(
2596                                 dc, dsi, DSI_LP_OP_WRITE);
2597         if (IS_ERR_OR_NULL(init_status)) {
2598                 err = PTR_ERR(init_status);
2599                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2600                 goto fail;
2601         }
2602
2603         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2604 fail:
2605         err = tegra_dsi_restore_state(dc, dsi, init_status);
2606         if (err < 0)
2607                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2608
2609         return err;
2610 }
2611
2612 int tegra_dsi_write_data(struct tegra_dc *dc,
2613                         struct tegra_dc_dsi_data *dsi,
2614                         u8 *pdata, u8 data_id, u16 data_len)
2615 {
2616         int err;
2617
2618         tegra_dc_io_start(dc);
2619         tegra_dc_dsi_hold_host(dc);
2620
2621         err = tegra_dsi_write_data_nosync(dc, dsi, pdata, data_id, data_len);
2622
2623         tegra_dc_dsi_release_host(dc);
2624         tegra_dc_io_end(dc);
2625
2626         return err;
2627 }
2628
2629 EXPORT_SYMBOL(tegra_dsi_write_data);
2630
2631 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2632                                         struct tegra_dc_dsi_data *dsi,
2633                                         struct tegra_dsi_cmd *cmd,
2634                                         u32 n_cmd)
2635 {
2636         u32 i;
2637         int err;
2638
2639         err = 0;
2640         for (i = 0; i < n_cmd; i++) {
2641                 struct tegra_dsi_cmd *cur_cmd;
2642                 cur_cmd = &cmd[i];
2643
2644                 /*
2645                  * Some Panels need reset midway in the command sequence.
2646                  */
2647                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
2648                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
2649                                        cur_cmd->data_id);
2650                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
2651                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2652                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
2653                                 tegra_dsi_send_dc_frames(dc,
2654                                                 dsi,
2655                                                 cur_cmd->sp_len_dly.frame_cnt);
2656                 } else {
2657                         err = tegra_dsi_write_data_nosync(dc, dsi,
2658                                                 cur_cmd->pdata,
2659                                                 cur_cmd->data_id,
2660                                                 cur_cmd->sp_len_dly.data_len);
2661                         mdelay(1);
2662                         if (err < 0)
2663                                 break;
2664                 }
2665         }
2666         return err;
2667 }
2668
2669 static u8 tegra_dsi_ecc(u32 header)
2670 {
2671         char ecc_parity[24] = {
2672                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2673                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2674                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2675         };
2676         u8 ecc_byte;
2677         int i;
2678
2679         ecc_byte = 0;
2680         for (i = 0; i < 24; i++)
2681                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2682
2683         return ecc_byte;
2684 }
2685
2686 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2687 {
2688         u16 byte_cnt;
2689         u8 bit_cnt;
2690         char curr_byte;
2691         u16 crc = 0xFFFF;
2692         u16 poly = 0x8408;
2693
2694         if (data_len > 0) {
2695                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2696                         curr_byte = pdata[byte_cnt];
2697                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2698                                 if (((crc & 0x0001 ) ^
2699                                         (curr_byte & 0x0001)) > 0)
2700                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2701                                 else
2702                                         crc = (crc >> 1) & 0x7FFF;
2703
2704                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2705                         }
2706                 }
2707         }
2708         return crc;
2709 }
2710
2711 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2712                                                 struct tegra_dsi_cmd *cmd)
2713 {
2714         u8 virtual_channel;
2715         u32 val;
2716         u16 data_len = cmd->sp_len_dly.data_len;
2717         u8 seq_ctrl_reg = 0;
2718
2719         virtual_channel = dsi->info.virtual_channel <<
2720                                 DSI_VIR_CHANNEL_BIT_POSITION;
2721
2722         val = (virtual_channel | cmd->data_id) << 0 |
2723                 data_len << 8;
2724
2725         val |= tegra_dsi_ecc(val) << 24;
2726
2727         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2728
2729         /* if pdata != NULL, pkt type is long pkt */
2730         if (cmd->pdata != NULL) {
2731                 u8 *pdata;
2732                 u8 *pdata_mem;
2733                 /* allocate memory for pdata + 2 bytes checksum */
2734                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2735                 if (!pdata_mem) {
2736                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2737                         tegra_dsi_soft_reset(dsi);
2738                         return -ENOMEM;
2739                 }
2740
2741                 memcpy(pdata_mem, cmd->pdata, data_len);
2742                 pdata = pdata_mem;
2743                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2744
2745                 /* data_len = length of pdata + 2 byte checksum */
2746                 data_len += 2;
2747
2748                 while (data_len) {
2749                         if (data_len >= 4) {
2750                                 val = ((u32 *) pdata)[0];
2751                                 data_len -= 4;
2752                                 pdata += 4;
2753                         } else {
2754                                 val = 0;
2755                                 memcpy(&val, pdata, data_len);
2756                                 pdata += data_len;
2757                                 data_len = 0;
2758                         }
2759                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2760                                                         seq_ctrl_reg++);
2761                 }
2762                 kfree(pdata_mem);
2763         }
2764
2765         return 0;
2766 }
2767
2768 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2769                                                 struct tegra_dsi_cmd *cmd)
2770 {
2771 #define PKT_HEADER_LEN_BYTE     4
2772 #define CHECKSUM_LEN_BYTE       2
2773
2774         int err = 0;
2775         u32 val;
2776         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2777         struct tegra_dc *dc = dsi->dc;
2778
2779         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2780                 return -EINVAL;
2781
2782         mutex_lock(&dsi->lock);
2783         tegra_dc_io_start(dc);
2784         tegra_dc_dsi_hold_host(dc);
2785
2786 #if DSI_USE_SYNC_POINTS
2787         atomic_set(&dsi_syncpt_rst, 1);
2788 #endif
2789
2790         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2791         if (err < 0) {
2792                 dev_err(&dsi->dc->ndev->dev,
2793                         "dsi: dcs pkt seq ctrl init failed\n");
2794                 goto fail;
2795         }
2796
2797         if (cmd->pdata) {
2798                 u16 data_len = cmd->sp_len_dly.data_len;
2799                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2800         }
2801
2802         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2803                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2804                                                 TEGRA_DSI_ENABLE);
2805         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2806
2807 fail:
2808         tegra_dc_dsi_release_host(dc);
2809         tegra_dc_io_end(dc);
2810         mutex_unlock(&dsi->lock);
2811         return err;
2812
2813 #undef PKT_HEADER_LEN_BYTE
2814 #undef CHECKSUM_LEN_BYTE
2815 }
2816 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2817
2818 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2819 {
2820         struct tegra_dc *dc = dsi->dc;
2821         u32 cnt;
2822
2823         mutex_lock(&dsi->lock);
2824         tegra_dc_io_start(dc);
2825         tegra_dc_dsi_hold_host(dc);
2826
2827         if (atomic_read(&dsi_syncpt_rst)) {
2828                 tegra_dsi_wait_frame_end(dc, dsi, 2);
2829                 tegra_dsi_syncpt_reset(dsi);
2830                 atomic_set(&dsi_syncpt_rst, 0);
2831         }
2832
2833         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2834
2835         /* clear seq data registers */
2836         for (cnt = 0; cnt < 8; cnt++)
2837                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2838
2839         tegra_dc_dsi_release_host(dc);
2840         tegra_dc_io_end(dc);
2841
2842         mutex_unlock(&dsi->lock);
2843 }
2844 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2845
2846 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2847 {
2848         u32 val;
2849         int err = 0;
2850
2851         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2852         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2853         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2854
2855 #if DSI_USE_SYNC_POINTS
2856         err = tegra_dsi_syncpt(dsi);
2857         if (err < 0) {
2858                 dev_err(&dsi->dc->ndev->dev,
2859                         "DSI syncpt for bta failed\n");
2860         }
2861 #else
2862         if (tegra_dsi_read_busy(dsi)) {
2863                 err = -EBUSY;
2864                 dev_err(&dsi->dc->ndev->dev,
2865                         "Timeout wating on read completion\n");
2866         }
2867 #endif
2868
2869         return err;
2870 }
2871
2872 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2873                                         u32 rd_fifo_cnt, u8 *read_fifo)
2874 {
2875         int err;
2876         u32 payload_size;
2877
2878         payload_size = 0;
2879         err = 0;
2880
2881         switch (read_fifo[0]) {
2882         case DSI_ESCAPE_CMD:
2883                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2884                 break;
2885         case DSI_ACK_NO_ERR:
2886                 dev_info(&dc->ndev->dev,
2887                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2888                 return err;
2889         default:
2890                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2891                 break;
2892         }
2893
2894         switch (read_fifo[4] & 0xff) {
2895         case GEN_LONG_RD_RES:
2896                 /* Fall through */
2897         case DCS_LONG_RD_RES:
2898                 payload_size = (read_fifo[5] |
2899                                 (read_fifo[6] << 8)) & 0xFFFF;
2900                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2901                                 "payload_size[0x%x]\n", payload_size);
2902                 break;
2903         case GEN_1_BYTE_SHORT_RD_RES:
2904                 /* Fall through */
2905         case DCS_1_BYTE_SHORT_RD_RES:
2906                 payload_size = 1;
2907                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2908                         "payload_size[0x%x]\n", payload_size);
2909                 break;
2910         case GEN_2_BYTE_SHORT_RD_RES:
2911                 /* Fall through */
2912         case DCS_2_BYTE_SHORT_RD_RES:
2913                 payload_size = 2;
2914                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2915                         "payload_size[0x%x]\n", payload_size);
2916                 break;
2917         case ACK_ERR_RES:
2918                 payload_size = 2;
2919                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2920                         "Packet payload_size[0x%x]\n", payload_size);
2921                 break;
2922         default:
2923                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2924                 err = -EINVAL;
2925                 break;
2926         }
2927         return err;
2928 }
2929
2930 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2931                         struct tegra_dc_dsi_data *dsi,
2932                         u8 *read_fifo)
2933 {
2934         u32 val;
2935         u32 i;
2936         u32 poll_time = 0;
2937         u32 rd_fifo_cnt;
2938         int err = 0;
2939         u8 *read_fifo_cp = read_fifo;
2940
2941         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2942                 mdelay(1);
2943                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2944                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2945                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
2946                         dev_err(&dc->ndev->dev,
2947                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2948                         break;
2949                 }
2950                 poll_time++;
2951         }
2952
2953         if (rd_fifo_cnt == 0) {
2954                 dev_info(&dc->ndev->dev,
2955                         "DSI RD_FIFO_CNT is zero\n");
2956                 err = -EINVAL;
2957                 goto fail;
2958         }
2959
2960         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2961                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2962                 dev_warn(&dc->ndev->dev,
2963                         "DSI overflow/underflow error\n");
2964         }
2965
2966         /* Read data from FIFO */
2967         for (i = 0; i < rd_fifo_cnt; i++) {
2968                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2969                 if (enable_read_debug)
2970                         dev_info(&dc->ndev->dev,
2971                         "Read data[%d]: 0x%x\n", i, val);
2972                 memcpy(read_fifo, &val, 4);
2973                 read_fifo += 4;
2974         }
2975
2976         /* Make sure all the data is read from the FIFO */
2977         val = tegra_dsi_readl(dsi, DSI_STATUS);
2978         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2979         if (val)
2980                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2981                 " even after reading FIFO_RD_CNT words from read fifo\n");
2982
2983         if (enable_read_debug) {
2984                 err =
2985                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2986                 if (err < 0)
2987                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2988         }
2989 fail:
2990         return err;
2991 }
2992
2993 int tegra_dsi_read_data(struct tegra_dc *dc,
2994                                 struct tegra_dc_dsi_data *dsi,
2995                                 u32 max_ret_payload_size,
2996                                 u32 panel_reg_addr, u8 *read_data)
2997 {
2998         int err = 0;
2999         struct dsi_status *init_status;
3000
3001         mutex_lock(&dsi->lock);
3002         tegra_dc_io_start(dc);
3003         clk_prepare_enable(dsi->dsi_fixed_clk);
3004
3005         init_status = tegra_dsi_prepare_host_transmission(
3006                                 dc, dsi, DSI_LP_OP_WRITE);
3007         if (IS_ERR_OR_NULL(init_status)) {
3008                 err = PTR_ERR(init_status);
3009                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3010                 goto fail;
3011         }
3012
3013         /* Set max return payload size in words */
3014         err = _tegra_dsi_write_data(dsi, NULL,
3015                 dsi_command_max_return_pkt_size,
3016                 max_ret_payload_size);
3017         if (err < 0) {
3018                 dev_err(&dc->ndev->dev,
3019                                 "DSI write failed\n");
3020                 goto fail;
3021         }
3022
3023         /* DCS to read given panel register */
3024         err = _tegra_dsi_write_data(dsi, NULL,
3025                 dsi_command_dcs_read_with_no_params,
3026                 panel_reg_addr);
3027         if (err < 0) {
3028                 dev_err(&dc->ndev->dev,
3029                                 "DSI write failed\n");
3030                 goto fail;
3031         }
3032
3033         tegra_dsi_reset_read_count(dsi);
3034
3035         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3036                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3037                 if (err < 0) {
3038                         dev_err(&dc->ndev->dev,
3039                         "DSI failed to go to LP read mode\n");
3040                         goto fail;
3041                 }
3042         }
3043
3044         err = tegra_dsi_bta(dsi);
3045         if (err < 0) {
3046                 dev_err(&dc->ndev->dev,
3047                         "DSI IMM BTA timeout\n");
3048                 goto fail;
3049         }
3050
3051         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3052         if (err < 0) {
3053                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3054                 goto fail;
3055         }
3056 fail:
3057         err = tegra_dsi_restore_state(dc, dsi, init_status);
3058         if (err < 0)
3059                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3060         clk_disable_unprepare(dsi->dsi_fixed_clk);
3061         tegra_dc_io_end(dc);
3062         mutex_unlock(&dsi->lock);
3063         return err;
3064 }
3065 EXPORT_SYMBOL(tegra_dsi_read_data);
3066
3067 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3068                                 struct tegra_dc_dsi_data *dsi)
3069 {
3070         int err = 0;
3071         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3072         struct dsi_status *init_status;
3073         static struct tegra_dsi_cmd dsi_nop_cmd =
3074                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3075
3076         tegra_dc_io_start(dc);
3077         clk_prepare_enable(dsi->dsi_fixed_clk);
3078
3079         init_status = tegra_dsi_prepare_host_transmission(
3080                                         dc, dsi, DSI_LP_OP_WRITE);
3081         if (IS_ERR_OR_NULL(init_status)) {
3082                 err = PTR_ERR(init_status);
3083                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3084                 goto fail;
3085         }
3086
3087         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
3088         if (err < 0) {
3089                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3090                 goto fail;
3091         }
3092
3093         tegra_dsi_reset_read_count(dsi);
3094
3095         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3096                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3097                 if (err < 0) {
3098                         dev_err(&dc->ndev->dev,
3099                         "DSI failed to go to LP read mode\n");
3100                         goto fail;
3101                 }
3102         }
3103
3104         err = tegra_dsi_bta(dsi);
3105         if (err < 0) {
3106                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3107                 goto fail;
3108         }
3109
3110         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3111         if (err < 0) {
3112                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3113                 goto fail;
3114         }
3115
3116         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3117                 dev_warn(&dc->ndev->dev,
3118                         "Ack no error trigger message not received\n");
3119                 err = -EAGAIN;
3120         }
3121 fail:
3122         err = tegra_dsi_restore_state(dc, dsi, init_status);
3123         if (err < 0)
3124                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3125         clk_disable_unprepare(dsi->dsi_fixed_clk);
3126         tegra_dc_io_end(dc);
3127         return err;
3128 }
3129 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3130
3131 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3132 {
3133         u32 val;
3134         int ret = 0;
3135
3136         if (atomic_read(&dsi_syncpt_rst))
3137                 tegra_dsi_syncpt_reset(dsi);
3138
3139         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3140         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3141         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3142         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3143
3144 #if DSI_USE_SYNC_POINTS
3145         ret = tegra_dsi_syncpt(dsi);
3146         if (ret < 0) {
3147                 dev_err(&dsi->dc->ndev->dev,
3148                         "DSI syncpt for ulpm enter failed\n");
3149                 return ret;
3150         }
3151 #else
3152         /* TODO: Find exact delay required */
3153         mdelay(10);
3154 #endif
3155         dsi->ulpm = true;
3156
3157         return ret;
3158 }
3159
3160 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3161 {
3162         u32 val;
3163         int ret = 0;
3164
3165         if (atomic_read(&dsi_syncpt_rst))
3166                 tegra_dsi_syncpt_reset(dsi);
3167
3168         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3169         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3170         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3171         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3172
3173 #if DSI_USE_SYNC_POINTS
3174         ret = tegra_dsi_syncpt(dsi);
3175         if (ret < 0) {
3176                 dev_err(&dsi->dc->ndev->dev,
3177                         "DSI syncpt for ulpm exit failed\n");
3178                 return ret;
3179         }
3180 #else
3181         /* TODO: Find exact delay required */
3182         mdelay(10);
3183 #endif
3184         dsi->ulpm = false;
3185
3186         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3187         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3188         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3189         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3190
3191         return ret;
3192 }
3193
3194 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3195                                      struct tegra_dc_dsi_data *dsi,
3196                                      int no_of_frames)
3197 {
3198         int err;
3199         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3200         u8 lp_op = dsi->status.lp_op;
3201         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3202
3203         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3204                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3205                                 TEGRA_DSI_DRIVEN_BY_DC);
3206                 if (err < 0) {
3207                         dev_err(&dc->ndev->dev,
3208                                 "Switch to HS host mode failed\n");
3209                         return;
3210                 }
3211         }
3212
3213         /*
3214          * Some panels need DC frames be sent under certain
3215          * conditions. We are working on the right fix for this
3216          * requirement, while using this current fix.
3217          */
3218         tegra_dsi_start_dc_stream(dc, dsi);
3219
3220         /*
3221          * Send frames in Continuous or One-shot mode.
3222          */
3223         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3224                 while (no_of_frames--) {
3225                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3226                                         DC_CMD_STATE_CONTROL);
3227                         mdelay(frame_period);
3228                 }
3229         } else
3230                 mdelay(no_of_frames * frame_period);
3231
3232         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3233
3234         if (switch_to_lp) {
3235                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3236                 if (err < 0)
3237                         dev_err(&dc->ndev->dev,
3238                                 "DSI failed to go to LP mode\n");
3239         }
3240 }
3241
3242 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3243 {
3244         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3245         int err = 0;
3246
3247         mutex_lock(&dsi->lock);
3248         tegra_dc_io_start(dc);
3249
3250         /* Stop DC stream before configuring DSI registers
3251          * to avoid visible glitches on panel during transition
3252          * from bootloader to kernel driver
3253          */
3254         tegra_dsi_stop_dc_stream(dc, dsi);
3255
3256         if (dsi->enabled) {
3257                 if (dsi->ulpm) {
3258                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3259                                 dev_err(&dc->ndev->dev,
3260                                         "DSI failed to exit ulpm\n");
3261                                 goto fail;
3262                         }
3263                 }
3264
3265                 if (dsi->info.panel_reset) {
3266                         /*
3267                          * Certain panels need dc frames be sent before
3268                          * waking panel.
3269                          */
3270                         if (dsi->info.panel_send_dc_frames)
3271                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3272
3273                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3274                                                         dsi->info.dsi_init_cmd,
3275                                                         dsi->info.n_init_cmd);
3276                         if (err < 0) {
3277                                 dev_err(&dc->ndev->dev,
3278                                 "dsi: error sending dsi init cmd\n");
3279                                 goto fail;
3280                         }
3281                 } else if (dsi->info.dsi_late_resume_cmd) {
3282                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3283                                                 dsi->info.dsi_late_resume_cmd,
3284                                                 dsi->info.n_late_resume_cmd);
3285                         if (err < 0) {
3286                                 dev_err(&dc->ndev->dev,
3287                                 "dsi: error sending late resume cmd\n");
3288                                 goto fail;
3289                         }
3290                 }
3291         } else {
3292                 err = tegra_dsi_init_hw(dc, dsi);
3293                 if (err < 0) {
3294                         dev_err(&dc->ndev->dev,
3295                                 "dsi: not able to init dsi hardware\n");
3296                         goto fail;
3297                 }
3298
3299                 if (dsi->ulpm) {
3300                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3301                                 dev_err(&dc->ndev->dev,
3302                                         "DSI failed to enter ulpm\n");
3303                                 goto fail;
3304                         }
3305
3306                         tegra_dsi_pad_enable(dsi);
3307
3308                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3309                                 dev_err(&dc->ndev->dev,
3310                                         "DSI failed to exit ulpm\n");
3311                                 goto fail;
3312                         }
3313                 }
3314
3315                 /*
3316                  * Certain panels need dc frames be sent before
3317                  * waking panel.
3318                  */
3319                 if (dsi->info.panel_send_dc_frames)
3320                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3321
3322                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3323                 if (err < 0) {
3324                         dev_err(&dc->ndev->dev,
3325                                 "dsi: not able to set to lp mode\n");
3326                         goto fail;
3327                 }
3328
3329                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3330                                                 dsi->info.n_init_cmd);
3331                 if (err < 0) {
3332                         dev_err(&dc->ndev->dev,
3333                                 "dsi: error while sending dsi init cmd\n");
3334                         goto fail;
3335                 }
3336
3337                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3338                                 TEGRA_DSI_DRIVEN_BY_DC);
3339                 if (err < 0) {
3340                         dev_err(&dc->ndev->dev,
3341                                 "dsi: not able to set to hs mode\n");
3342                         goto fail;
3343                 }
3344
3345                 dsi->enabled = true;
3346         }
3347
3348         if (dsi->out_ops && dsi->out_ops->enable)
3349                 dsi->out_ops->enable(dsi);
3350
3351         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3352                 tegra_dsi_start_dc_stream(dc, dsi);
3353 fail:
3354         tegra_dc_io_end(dc);
3355         mutex_unlock(&dsi->lock);
3356 }
3357
3358 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3359 {
3360         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3361
3362         tegra_dc_dsi_debug_create(dsi);
3363
3364         if (dsi->info.dsi2lvds_bridge_enable)
3365                 dsi->out_ops = &tegra_dsi2lvds_ops;
3366         else if (dsi->info.dsi2edp_bridge_enable)
3367                 dsi->out_ops = &tegra_dsi2edp_ops;
3368         else
3369                 dsi->out_ops = NULL;
3370
3371         if (dsi->out_ops && dsi->out_ops->init)
3372                 dsi->out_ops->init(dsi);
3373
3374         tegra_dsi_init_sw(dc, dsi);
3375 }
3376
3377 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3378                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3379 {
3380         u16 i;
3381         u16 len;
3382
3383         memcpy(dst, src, sizeof(*dst) * n_cmd);
3384
3385         for (i = 0; i < n_cmd; i++)
3386                 if (src[i].pdata) {
3387                         len = sizeof(*src[i].pdata) *
3388                                         src[i].sp_len_dly.data_len;
3389                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3390                         if (!dst[i].pdata)
3391                                 goto free_cmd_pdata;
3392                         memcpy(dst[i].pdata, src[i].pdata, len);
3393                 }
3394
3395         return 0;
3396
3397 free_cmd_pdata:
3398         while (i--)
3399                 if (dst[i].pdata)
3400                         kfree(dst[i].pdata);
3401         return -ENOMEM;
3402 }
3403
3404 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3405                                         struct tegra_dsi_out *p_dsi)
3406 {
3407         struct tegra_dsi_cmd *p_init_cmd;
3408         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3409         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3410         struct tegra_dsi_cmd *p_suspend_cmd;
3411         int err;
3412
3413         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3414                 return -EINVAL;
3415
3416         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3417                                 p_dsi->n_init_cmd, GFP_KERNEL);
3418         if (!p_init_cmd)
3419                 return -ENOMEM;
3420
3421         if (p_dsi->dsi_early_suspend_cmd) {
3422                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3423                                         p_dsi->n_early_suspend_cmd,
3424                                         GFP_KERNEL);
3425                 if (!p_early_suspend_cmd) {
3426                         err = -ENOMEM;
3427                         goto err_free_init_cmd;
3428                 }
3429         }
3430
3431         if (p_dsi->dsi_late_resume_cmd) {
3432                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3433                                         p_dsi->n_late_resume_cmd,
3434                                         GFP_KERNEL);
3435                 if (!p_late_resume_cmd) {
3436                         err = -ENOMEM;
3437                         goto err_free_p_early_suspend_cmd;
3438                 }
3439         }
3440
3441         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3442                                 GFP_KERNEL);
3443         if (!p_suspend_cmd) {
3444                 err = -ENOMEM;
3445                 goto err_free_p_late_resume_cmd;
3446         }
3447
3448         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3449
3450         /* Copy panel init cmd */
3451         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3452                                                 p_init_cmd, p_dsi->n_init_cmd);
3453         if (err < 0)
3454                 goto err_free;
3455         dsi->info.dsi_init_cmd = p_init_cmd;
3456
3457         /* Copy panel early suspend cmd */
3458         if (p_dsi->dsi_early_suspend_cmd) {
3459                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3460                                         p_early_suspend_cmd,
3461                                         p_dsi->n_early_suspend_cmd);
3462                 if (err < 0)
3463                         goto err_free;
3464                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3465         }
3466
3467         /* Copy panel late resume cmd */
3468         if (p_dsi->dsi_late_resume_cmd) {
3469                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3470                                                 p_late_resume_cmd,
3471                                                 p_dsi->n_late_resume_cmd);
3472                 if (err < 0)
3473                         goto err_free;
3474                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3475         }
3476
3477         /* Copy panel suspend cmd */
3478         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3479                                         p_dsi->n_suspend_cmd);
3480         if (err < 0)
3481                 goto err_free;
3482         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3483
3484         if (!dsi->info.panel_reset_timeout_msec)
3485                 dsi->info.panel_reset_timeout_msec =
3486                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3487
3488         if (!dsi->info.panel_buffer_size_byte)
3489                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3490
3491         if (!dsi->info.max_panel_freq_khz) {
3492                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3493
3494                 if (dsi->info.video_burst_mode >
3495                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3496                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3497                                         "is not set for DSI burst mode.\n");
3498                         dsi->info.video_burst_mode =
3499                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3500                 }
3501         }
3502
3503         if (!dsi->info.lp_cmd_mode_freq_khz)
3504                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3505
3506         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3507                 dev_warn(&dsi->dc->ndev->dev,
3508                         "DSI: Failed to get chip info\n");
3509
3510         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3511                 dsi->info.lp_read_cmd_mode_freq_khz =
3512                         dsi->info.lp_cmd_mode_freq_khz;
3513
3514         /* host mode is for testing only */
3515         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3516         return 0;
3517
3518 err_free:
3519         kfree(p_suspend_cmd);
3520 err_free_p_late_resume_cmd:
3521         kfree(p_late_resume_cmd);
3522 err_free_p_early_suspend_cmd:
3523         kfree(p_early_suspend_cmd);
3524 err_free_init_cmd:
3525         kfree(p_init_cmd);
3526         return err;
3527 }
3528
3529 /* returns next null enumeration from  tegra_dsi_instance */
3530 static inline int tegra_dsi_get_enumeration(void)
3531 {
3532         int i = 0;
3533         for (; i < MAX_DSI_INSTANCE; i++) {
3534                 if (!tegra_dsi_instance[i])
3535                         return i;
3536         }
3537         return -EINVAL;
3538 }
3539
3540 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3541 {
3542         struct tegra_dc_dsi_data *dsi;
3543         struct resource *res;
3544         struct resource *base_res;
3545         void __iomem *base;
3546         struct clk *dc_clk = NULL;
3547         struct clk *dsi_clk = NULL;
3548         struct clk *dsi_fixed_clk = NULL;
3549         struct tegra_dsi_out *dsi_pdata;
3550         int err = 0;
3551         int dsi_enum = -1;
3552
3553         if (dc->pdata->default_out->dsi->dsi_instance)
3554                 dsi_enum = 1;
3555         else
3556                 dsi_enum = tegra_dsi_get_enumeration();
3557         if (dsi_enum < 0) {
3558                 err = -EINVAL;
3559                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3560                 return err;
3561         }
3562
3563         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3564         if (!dsi) {
3565                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3566                 return -ENOMEM;
3567         }
3568         tegra_dsi_instance[dsi_enum] = dsi;
3569
3570         if (dc->out->dsi->ganged_type) {
3571                 if (dsi_enum)
3572                         res = platform_get_resource_byname(dc->ndev,
3573                                                 IORESOURCE_MEM,
3574                                                 "ganged_dsib_regs");
3575                 else
3576                         res = platform_get_resource_byname(dc->ndev,
3577                                                 IORESOURCE_MEM,
3578                                                 "ganged_dsia_regs");
3579         } else {
3580                 res = platform_get_resource_byname(dc->ndev,
3581                                         IORESOURCE_MEM,
3582                                         "dsi_regs");
3583         }
3584
3585         if (!res) {
3586                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3587                 err = -ENOENT;
3588                 goto err_free_dsi;
3589         }
3590
3591         base_res = request_mem_region(res->start, resource_size(res),
3592                                 dc->ndev->name);
3593         if (!base_res) {
3594                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3595                 err = -EBUSY;
3596                 goto err_free_dsi;
3597         }
3598
3599         base = ioremap(res->start, resource_size(res));
3600         if (!base) {
3601                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3602                 err = -EBUSY;
3603                 goto err_release_regs;
3604         }
3605
3606         dsi_pdata = dc->pdata->default_out->dsi;
3607         if (!dsi_pdata) {
3608                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3609                 goto err_release_regs;
3610         }
3611
3612         if (dsi_enum)
3613                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3614         else
3615                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3616
3617         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3618
3619         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3620                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3621                 err = -EBUSY;
3622                 goto err_release_regs;
3623         }
3624
3625         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3626         if (IS_ERR_OR_NULL(dc_clk)) {
3627                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3628                         dev_name(&dc->ndev->dev));
3629                 err = -EBUSY;
3630                 goto err_dsi_clk_put;
3631         }
3632
3633         mutex_init(&dsi->lock);
3634         dsi->controller_index = dsi_enum;
3635         dsi->dc = dc;
3636         dsi->base = base;
3637         dsi->base_res = base_res;
3638         dsi->dc_clk = dc_clk;
3639         dsi->dsi_clk = dsi_clk;
3640         dsi->dsi_fixed_clk = dsi_fixed_clk;
3641
3642         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3643         if (err < 0)
3644                 goto err_dc_clk_put;
3645
3646         tegra_dc_set_outdata(dc, dsi);
3647         __tegra_dc_dsi_init(dc);
3648
3649         return 0;
3650
3651 err_dc_clk_put:
3652         clk_put(dc_clk);
3653 err_dsi_clk_put:
3654         clk_put(dsi_clk);
3655         clk_put(dsi_fixed_clk);
3656 err_release_regs:
3657         release_resource(base_res);
3658 err_free_dsi:
3659         kfree(dsi);
3660
3661         return err;
3662 }
3663
3664 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3665 {
3666         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3667         u16 i;
3668         u32 val;
3669
3670         mutex_lock(&dsi->lock);
3671
3672         if (dsi->out_ops && dsi->out_ops->destroy)
3673                 dsi->out_ops->destroy(dsi);
3674
3675         /* free up the pdata */
3676         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3677                 if (dsi->info.dsi_init_cmd[i].pdata)
3678                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3679         }
3680         kfree(dsi->info.dsi_init_cmd);
3681
3682         /* Disable dc stream */
3683         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3684                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3685
3686         /* Disable dsi phy clock */
3687         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3688                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3689
3690         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3691         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3692
3693         iounmap(dsi->base);
3694         release_resource(dsi->base_res);
3695
3696         clk_put(dsi->dc_clk);
3697         clk_put(dsi->dsi_clk);
3698
3699         mutex_unlock(&dsi->lock);
3700
3701         mutex_destroy(&dsi->lock);
3702         kfree(dsi);
3703 }
3704
3705 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3706                                                         u32 settings)
3707 {
3708         struct clk *parent_clk = NULL;
3709         struct clk *base_clk = NULL;
3710
3711         parent_clk = clk_get_parent(dsi->dsi_clk);
3712         base_clk = clk_get_parent(parent_clk);
3713         if (dsi->info.dsi_instance)
3714                 tegra_clk_cfg_ex(base_clk,
3715                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3716                                 settings);
3717         else
3718                 tegra_clk_cfg_ex(base_clk,
3719                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3720                                 settings);
3721 }
3722
3723 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
3724                                         struct tegra_dc_dsi_data *dsi,
3725                                         u32 suspend_aggr)
3726 {
3727         u32 val = 0;
3728         int err = 0;
3729
3730         switch (suspend_aggr) {
3731         case DSI_HOST_SUSPEND_LV2:
3732                 if (!dsi->ulpm) {
3733                         err = tegra_dsi_enter_ulpm(dsi);
3734                         if (err < 0) {
3735                                 dev_err(&dc->ndev->dev,
3736                                         "DSI failed to enter ulpm\n");
3737                                 goto fail;
3738                         }
3739                 }
3740
3741                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3742                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3743                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3744                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1);
3745                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3746
3747                 /* Suspend core-logic */
3748                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3749                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3750                 /* fall through */
3751         case DSI_HOST_SUSPEND_LV1:
3752                 /* Disable dsi fast and slow clock */
3753                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3754                 /* fall through */
3755         case DSI_HOST_SUSPEND_LV0:
3756                 /* Disable dsi source clock */
3757                 tegra_dsi_clk_disable(dsi);
3758                 break;
3759         case DSI_NO_SUSPEND:
3760                 break;
3761         default:
3762                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3763                                                 "is not supported.\n");
3764         }
3765
3766         return 0;
3767 fail:
3768         return err;
3769 }
3770
3771 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
3772                                         struct tegra_dc_dsi_data *dsi,
3773                                         u32 suspend_aggr)
3774 {
3775         u32 val;
3776         int err;
3777
3778         switch (dsi->info.suspend_aggr) {
3779         case DSI_HOST_SUSPEND_LV0:
3780                 tegra_dsi_clk_enable(dsi);
3781                 break;
3782         case DSI_HOST_SUSPEND_LV1:
3783                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3784                 tegra_dsi_clk_enable(dsi);
3785                 break;
3786         case DSI_HOST_SUSPEND_LV2:
3787                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3788                 tegra_dsi_clk_enable(dsi);
3789
3790                 tegra_dsi_writel(dsi,
3791                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3792                         DSI_POWER_CONTROL);
3793
3794                 if (dsi->ulpm) {
3795                         err = tegra_dsi_enter_ulpm(dsi);
3796                         if (err < 0) {
3797                                 dev_err(&dc->ndev->dev,
3798                                         "DSI failed to enter ulpm\n");
3799                                 goto fail;
3800                         }
3801
3802                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3803                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3804                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3805                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3806                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3807
3808                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3809                                 dev_err(&dc->ndev->dev,
3810                                         "DSI failed to exit ulpm\n");
3811                                 goto fail;
3812                         }
3813                 }
3814                 break;
3815         case DSI_NO_SUSPEND:
3816                 break;
3817         default:
3818                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3819                                                 "is not supported.\n");
3820         }
3821
3822         return 0;
3823 fail:
3824         return err;
3825 }
3826
3827 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3828 {
3829         int err = 0;
3830         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3831
3832         if (!dsi->enabled)
3833                 return -EINVAL;
3834
3835         if (dsi->host_suspended)
3836                 return 0;
3837
3838         mutex_lock(&dsi->host_lock);
3839         tegra_dc_io_start(dc);
3840         dsi->host_suspended = true;
3841
3842         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3843
3844         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
3845         if (err < 0)
3846                 dev_err(&dc->ndev->dev,
3847                         "DSI host suspend failed\n");
3848
3849         tegra_dc_io_end(dc);
3850         mutex_unlock(&dsi->host_lock);
3851         return err;
3852 }
3853
3854 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3855                                 struct tegra_dc_dsi_data *dsi)
3856 {
3857         int val = 0;
3858         int err = 0;
3859
3860         if (!dsi->enabled)
3861                 return 0;
3862
3863         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3864         if (err < 0) {
3865                 dev_err(&dc->ndev->dev,
3866                 "DSI failed to go to LP mode\n");
3867                 goto fail;
3868         }
3869
3870         /* Suspend DSI panel */
3871         err = tegra_dsi_send_panel_cmd(dc, dsi,
3872                         dsi->info.dsi_suspend_cmd,
3873                         dsi->info.n_suspend_cmd);
3874
3875         /*
3876          * Certain panels need dc frames be sent after
3877          * putting panel to sleep.
3878          */
3879         if (dsi->info.panel_send_dc_frames)
3880                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3881
3882         if (err < 0) {
3883                 dev_err(&dc->ndev->dev,
3884                         "dsi: Error sending suspend cmd\n");
3885                 goto fail;
3886         }
3887
3888         if (!dsi->ulpm) {
3889                 err = tegra_dsi_enter_ulpm(dsi);
3890                 if (err < 0) {
3891                         dev_err(&dc->ndev->dev,
3892                                 "DSI failed to enter ulpm\n");
3893                         goto fail;
3894                 }
3895         }
3896
3897         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3898                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3899                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3900         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3901
3902         /* Suspend core-logic */
3903         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3904         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3905
3906         /* Disable dsi fast and slow clock */
3907         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3908
3909         /* Disable dsi source clock */
3910         tegra_dsi_clk_disable(dsi);
3911
3912         regulator_disable(dsi->avdd_dsi_csi);
3913
3914         dsi->enabled = false;
3915         dsi->host_suspended = true;
3916
3917         return 0;
3918 fail:
3919         return err;
3920 }
3921
3922 static int tegra_dsi_host_resume(struct tegra_dc *dc)
3923 {
3924         int err = 0;
3925         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3926
3927         if (!dsi->enabled)
3928                 return -EINVAL;
3929
3930         mutex_lock(&dsi->host_lock);
3931         cancel_delayed_work_sync(&dsi->idle_work);
3932         if (!dsi->host_suspended) {
3933                 mutex_unlock(&dsi->host_lock);
3934                 return 0;
3935         }
3936
3937         tegra_dc_io_start(dc);
3938
3939         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
3940         if (err < 0) {
3941                 dev_err(&dc->ndev->dev,
3942                         "DSI host resume failed\n");
3943                 goto fail;
3944         }
3945
3946         tegra_dsi_start_dc_stream(dc, dsi);
3947         dsi->host_suspended = false;
3948 fail:
3949         tegra_dc_io_end(dc);
3950         mutex_unlock(&dsi->host_lock);
3951         return err;
3952 }
3953
3954 static void _tegra_dc_dsi_disable(struct tegra_dc *dc)
3955 {
3956         int err;
3957         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3958
3959         if (dsi->host_suspended)
3960                 tegra_dsi_host_resume(dc);
3961
3962         mutex_lock(&dsi->lock);
3963         tegra_dc_io_start(dc);
3964
3965         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3966                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3967
3968         if (dsi->out_ops && dsi->out_ops->disable)
3969                 dsi->out_ops->disable(dsi);
3970
3971         if (dsi->info.power_saving_suspend) {
3972                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
3973                         dev_err(&dc->ndev->dev,
3974                                 "DSI failed to enter deep sleep\n");
3975                         goto fail;
3976                 }
3977         } else {
3978                 if (dsi->info.dsi_early_suspend_cmd) {
3979                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3980                                 dsi->info.dsi_early_suspend_cmd,
3981                                 dsi->info.n_early_suspend_cmd);
3982                         if (err < 0) {
3983                                 dev_err(&dc->ndev->dev,
3984                                 "dsi: Error sending early suspend cmd\n");
3985                                 goto fail;
3986                         }
3987                 }
3988
3989                 if (!dsi->ulpm) {
3990                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3991                                 dev_err(&dc->ndev->dev,
3992                                         "DSI failed to enter ulpm\n");
3993                                 goto fail;
3994                         }
3995                 }
3996         }
3997 fail:
3998         mutex_unlock(&dsi->lock);
3999         tegra_dc_io_end(dc);
4000 }
4001
4002 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4003 {
4004         _tegra_dc_dsi_disable(dc);
4005
4006         if (dc->out->dsi->ganged_type) {
4007                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4008                 _tegra_dc_dsi_disable(dc);
4009                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4010         }
4011 }
4012
4013
4014 #ifdef CONFIG_PM
4015 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
4016 {
4017         struct tegra_dc_dsi_data *dsi;
4018
4019         dsi = tegra_dc_get_outdata(dc);
4020
4021         if (!dsi->enabled)
4022                 return;
4023
4024         if (dsi->host_suspended)
4025                 tegra_dsi_host_resume(dc);
4026
4027         tegra_dc_io_start(dc);
4028         mutex_lock(&dsi->lock);
4029
4030         if (dsi->out_ops && dsi->out_ops->suspend)
4031                 dsi->out_ops->suspend(dsi);
4032
4033         if (!dsi->info.power_saving_suspend) {
4034                 if (dsi->ulpm) {
4035                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4036                                 dev_err(&dc->ndev->dev,
4037                                         "DSI failed to exit ulpm");
4038                                 goto fail;
4039                         }
4040                 }
4041
4042                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4043                         dev_err(&dc->ndev->dev,
4044                                 "DSI failed to enter deep sleep\n");
4045                         goto fail;
4046                 }
4047         }
4048 fail:
4049         mutex_unlock(&dsi->lock);
4050         tegra_dc_io_end(dc);
4051 }
4052
4053 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
4054 {
4055         struct tegra_dc_dsi_data *dsi;
4056
4057         dsi = tegra_dc_get_outdata(dc);
4058
4059         /* No dsi config required since tegra_dc_dsi_enable
4060          * will reconfigure the controller from scratch
4061          */
4062
4063          if (dsi->out_ops && dsi->out_ops->resume)
4064                 dsi->out_ops->resume(dsi);
4065 }
4066
4067 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4068 {
4069         _tegra_dc_dsi_suspend(dc);
4070
4071         if (dc->out->dsi->ganged_type) {
4072                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4073                 _tegra_dc_dsi_suspend(dc);
4074                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4075         }
4076 }
4077
4078 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
4079 {
4080         _tegra_dc_dsi_resume(dc);
4081
4082         if (dc->out->dsi->ganged_type) {
4083                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4084                 _tegra_dc_dsi_resume(dc);
4085                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4086         }
4087 }
4088 #endif
4089
4090 static int tegra_dc_dsi_init(struct tegra_dc *dc)
4091 {
4092         struct tegra_dc_dsi_data *dsi;
4093         int err = 0;
4094
4095         err = _tegra_dc_dsi_init(dc);
4096         if (err < 0) {
4097                 dev_err(&dc->ndev->dev,
4098                         "dsi: Instance A init failed\n");
4099                 goto err;
4100         }
4101
4102         dsi = tegra_dc_get_outdata(dc);
4103
4104         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
4105         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
4106                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
4107                 err = PTR_ERR(dsi->avdd_dsi_csi);
4108                 goto err_reg;
4109         }
4110
4111         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
4112         if (IS_ERR(dsi->mipi_cal)) {
4113                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
4114                 err = PTR_ERR(dsi->mipi_cal);
4115                 goto err_mipi;
4116         }
4117
4118         if (dc->out->dsi->ganged_type) {
4119                 err = _tegra_dc_dsi_init(dc);
4120                 if (err < 0) {
4121                         dev_err(&dc->ndev->dev,
4122                                 "dsi: Instance B init failed\n");
4123                         goto err_ganged;
4124                 }
4125                 tegra_dsi_instance[DSI_INSTANCE_1]->avdd_dsi_csi =
4126                                                         dsi->avdd_dsi_csi;
4127                 tegra_dsi_instance[DSI_INSTANCE_1]->mipi_cal =
4128                                                         dsi->mipi_cal;
4129                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4130         }
4131         return 0;
4132 err_ganged:
4133         tegra_mipi_cal_destroy(dc);
4134 err_mipi:
4135         regulator_put(dsi->avdd_dsi_csi);
4136 err_reg:
4137         _tegra_dc_dsi_destroy(dc);
4138 err:
4139         return err;
4140 }
4141
4142 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4143 {
4144         struct regulator *avdd_dsi_csi;
4145         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4146
4147         avdd_dsi_csi = dsi->avdd_dsi_csi;
4148
4149         _tegra_dc_dsi_destroy(dc);
4150
4151         if (dc->out->dsi->ganged_type) {
4152                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4153                 _tegra_dc_dsi_destroy(dc);
4154                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4155         }
4156
4157         regulator_put(avdd_dsi_csi);
4158         tegra_mipi_cal_destroy(dc);
4159 }
4160
4161 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4162 {
4163         _tegra_dc_dsi_enable(dc);
4164
4165         if (dc->out->dsi->ganged_type) {
4166                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4167                 _tegra_dc_dsi_enable(dc);
4168                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4169         }
4170 }
4171
4172 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
4173 {
4174         unsigned long rate;
4175         struct clk *parent_clk;
4176         struct clk *base_clk;
4177
4178         if (clk == dc->clk) {
4179                 parent_clk = clk_get_sys(NULL,
4180                                 dc->out->parent_clk ? : "pll_d_out0");
4181                 base_clk = clk_get_parent(parent_clk);
4182                 tegra_clk_cfg_ex(base_clk,
4183                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
4184         } else {
4185                 if (dc->pdata->default_out->dsi->dsi_instance) {
4186                         parent_clk = clk_get_sys(NULL,
4187                                 dc->out->parent_clk ? : "pll_d2_out0");
4188                         base_clk = clk_get_parent(parent_clk);
4189                         tegra_clk_cfg_ex(base_clk,
4190                                         TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
4191                 } else {
4192                         parent_clk = clk_get_sys(NULL,
4193                                 dc->out->parent_clk ? : "pll_d_out0");
4194                         base_clk = clk_get_parent(parent_clk);
4195                         tegra_clk_cfg_ex(base_clk,
4196                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
4197                 }
4198         }
4199
4200         /* divide by 1000 to avoid overflow */
4201         dc->mode.pclk /= 1000;
4202         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
4203                                 / dc->shift_clk_div.div;
4204         rate *= 1000;
4205         dc->mode.pclk *= 1000;
4206
4207         if (rate != clk_get_rate(base_clk))
4208                 clk_set_rate(base_clk, rate);
4209
4210         if (clk_get_parent(clk) != parent_clk)
4211                 clk_set_parent(clk, parent_clk);
4212
4213         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
4214 }
4215
4216 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4217         .init = tegra_dc_dsi_init,
4218         .destroy = tegra_dc_dsi_destroy,
4219         .enable = tegra_dc_dsi_enable,
4220         .disable = tegra_dc_dsi_disable,
4221         .hold = tegra_dc_dsi_hold_host,
4222         .release = tegra_dc_dsi_release_host,
4223 #ifdef CONFIG_PM
4224         .suspend = tegra_dc_dsi_suspend,
4225         .resume = tegra_dc_dsi_resume,
4226 #endif
4227         .setup_clk = tegra_dc_dsi_setup_clk,
4228 };