bcc4a03470bf3cd76e516eedc8ccc7354df5cd42
[linux-3.10.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2012, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32
33 #include <mach/clk.h>
34 #include <mach/dc.h>
35 #include <mach/fb.h>
36 #include <mach/csi.h>
37 #include <mach/iomap.h>
38 #include <linux/nvhost.h>
39
40 #include "dc_reg.h"
41 #include "dc_priv.h"
42 #include "dev.h"
43 #include "dsi_regs.h"
44 #include "dsi.h"
45 #include "mipi_cal.h"
46
47 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
48 #define DSIB_MODE_ENABLE                0x2
49
50 #define DSI_USE_SYNC_POINTS             0
51 #define S_TO_MS(x)                      (1000 * (x))
52 #define MS_TO_US(x)                     (1000 * (x))
53
54 #define DSI_MODULE_NOT_INIT             0x0
55 #define DSI_MODULE_INIT                 0x1
56
57 #define DSI_LPHS_NOT_INIT               0x0
58 #define DSI_LPHS_IN_LP_MODE             0x1
59 #define DSI_LPHS_IN_HS_MODE             0x2
60
61 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
62 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
63 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
64
65 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
66 #define DSI_DRIVEN_MODE_DC              0x1
67 #define DSI_DRIVEN_MODE_HOST            0x2
68
69 #define DSI_PHYCLK_OUT_DIS              0x0
70 #define DSI_PHYCLK_OUT_EN               0x1
71
72 #define DSI_PHYCLK_NOT_INIT             0x0
73 #define DSI_PHYCLK_CONTINUOUS           0x1
74 #define DSI_PHYCLK_TX_ONLY              0x2
75
76 #define DSI_CLK_BURST_NOT_INIT          0x0
77 #define DSI_CLK_BURST_NONE_BURST        0x1
78 #define DSI_CLK_BURST_BURST_MODE        0x2
79
80 #define DSI_DC_STREAM_DISABLE           0x0
81 #define DSI_DC_STREAM_ENABLE            0x1
82
83 #define DSI_LP_OP_NOT_INIT              0x0
84 #define DSI_LP_OP_WRITE                 0x1
85 #define DSI_LP_OP_READ                  0x2
86
87 #define DSI_HOST_IDLE_PERIOD            1000
88 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
89
90 static bool enable_read_debug;
91 module_param(enable_read_debug, bool, 0644);
92 MODULE_PARM_DESC(enable_read_debug,
93                 "Enable to print read fifo and return packet type");
94
95 /* source of video data */
96 enum {
97         TEGRA_DSI_DRIVEN_BY_DC,
98         TEGRA_DSI_DRIVEN_BY_HOST,
99 };
100
101 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
102
103 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
104         DSI_PKT_SEQ_0_LO,
105         DSI_PKT_SEQ_0_HI,
106         DSI_PKT_SEQ_1_LO,
107         DSI_PKT_SEQ_1_HI,
108         DSI_PKT_SEQ_2_LO,
109         DSI_PKT_SEQ_2_HI,
110         DSI_PKT_SEQ_3_LO,
111         DSI_PKT_SEQ_3_HI,
112         DSI_PKT_SEQ_4_LO,
113         DSI_PKT_SEQ_4_HI,
114         DSI_PKT_SEQ_5_LO,
115         DSI_PKT_SEQ_5_HI,
116 };
117
118 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
119         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
120         0,
121         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
122         0,
123         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
124         0,
125         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
126         PKT_ID2(CMD_HE) | PKT_LEN2(0),
127         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
128         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
129         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
130         0,
131         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
132         PKT_ID2(CMD_HE) | PKT_LEN2(0),
133         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
134         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
135 };
136
137 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
138         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
139         0,
140         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
141         0,
142         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
143         0,
144         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
145         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
146         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
147         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
148         0,
149         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
150         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
151         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
152 };
153
154 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
155         PKT_ID0(CMD_VS) | PKT_LEN0(0),
156         0,
157         PKT_ID0(CMD_HS) | PKT_LEN0(0),
158         0,
159         PKT_ID0(CMD_HS) | PKT_LEN0(0),
160         0,
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
162         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
163         0,
164         PKT_ID0(CMD_HS) | PKT_LEN0(0),
165         0,
166         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
167         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
168         0,
169 };
170
171 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
172         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
173         0,
174         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
175         0,
176         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
179         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
180         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
181         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
182         0,
183         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
184         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
185         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
186 };
187
188 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
189         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
190         0,
191         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
192         0,
193         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
194         0,
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
196         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
197         0,
198         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
199         0,
200         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
201         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
202         0,
203 };
204
205 /* TODO: verify with hw about this format */
206 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
207         0,
208         0,
209         0,
210         0,
211         0,
212         0,
213         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
214         0,
215         0,
216         0,
217         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
218         0,
219 };
220
221 const u32 init_reg[] = {
222         DSI_INT_ENABLE,
223         DSI_INT_STATUS,
224         DSI_INT_MASK,
225         DSI_INIT_SEQ_DATA_0,
226         DSI_INIT_SEQ_DATA_1,
227         DSI_INIT_SEQ_DATA_2,
228         DSI_INIT_SEQ_DATA_3,
229         DSI_INIT_SEQ_DATA_4,
230         DSI_INIT_SEQ_DATA_5,
231         DSI_INIT_SEQ_DATA_6,
232         DSI_INIT_SEQ_DATA_7,
233         DSI_DCS_CMDS,
234         DSI_PKT_SEQ_0_LO,
235         DSI_PKT_SEQ_1_LO,
236         DSI_PKT_SEQ_2_LO,
237         DSI_PKT_SEQ_3_LO,
238         DSI_PKT_SEQ_4_LO,
239         DSI_PKT_SEQ_5_LO,
240         DSI_PKT_SEQ_0_HI,
241         DSI_PKT_SEQ_1_HI,
242         DSI_PKT_SEQ_2_HI,
243         DSI_PKT_SEQ_3_HI,
244         DSI_PKT_SEQ_4_HI,
245         DSI_PKT_SEQ_5_HI,
246         DSI_CONTROL,
247         DSI_HOST_DSI_CONTROL,
248         DSI_PAD_CONTROL,
249         DSI_PAD_CONTROL_CD,
250         DSI_SOL_DELAY,
251         DSI_MAX_THRESHOLD,
252         DSI_TRIGGER,
253         DSI_TX_CRC,
254         DSI_INIT_SEQ_CONTROL,
255         DSI_PKT_LEN_0_1,
256         DSI_PKT_LEN_2_3,
257         DSI_PKT_LEN_4_5,
258         DSI_PKT_LEN_6_7,
259 };
260
261 const u32 init_reg_vs1_ext[] = {
262         DSI_PAD_CONTROL_0_VS1,
263         DSI_PAD_CONTROL_CD_VS1,
264         DSI_PAD_CD_STATUS_VS1,
265         DSI_PAD_CONTROL_1_VS1,
266         DSI_PAD_CONTROL_2_VS1,
267         DSI_PAD_CONTROL_3_VS1,
268         DSI_PAD_CONTROL_4_VS1,
269         DSI_GANGED_MODE_CONTROL,
270         DSI_GANGED_MODE_START,
271         DSI_GANGED_MODE_SIZE,
272 };
273
274 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
275 static int tegra_dsi_host_resume(struct tegra_dc *dc);
276 static void tegra_dc_dsi_idle_work(struct work_struct *work);
277
278 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
279 {
280         unsigned long ret;
281
282         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
283         ret = readl(dsi->base + reg * 4);
284         trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
285         return ret;
286 }
287 EXPORT_SYMBOL(tegra_dsi_readl);
288
289 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
290 {
291         BUG_ON(!nvhost_module_powered_ext(nvhost_get_parent(dsi->dc->ndev)));
292         trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
293         writel(val, dsi->base + reg * 4);
294 }
295 EXPORT_SYMBOL(tegra_dsi_writel);
296
297 #ifdef CONFIG_DEBUG_FS
298 static int dbg_dsi_show(struct seq_file *s, void *unused)
299 {
300         struct tegra_dc_dsi_data *dsi = s->private;
301
302 #define DUMP_REG(a) do {                                                \
303                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
304                        #a, a, tegra_dsi_readl(dsi, a));         \
305         } while (0)
306
307         tegra_dc_io_start(dsi->dc);
308         clk_prepare_enable(dsi->dsi_clk);
309
310         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
311         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
312         DUMP_REG(DSI_CTXSW);
313         DUMP_REG(DSI_POWER_CONTROL);
314         DUMP_REG(DSI_INT_ENABLE);
315         DUMP_REG(DSI_HOST_DSI_CONTROL);
316         DUMP_REG(DSI_CONTROL);
317         DUMP_REG(DSI_SOL_DELAY);
318         DUMP_REG(DSI_MAX_THRESHOLD);
319         DUMP_REG(DSI_TRIGGER);
320         DUMP_REG(DSI_TX_CRC);
321         DUMP_REG(DSI_STATUS);
322         DUMP_REG(DSI_INIT_SEQ_CONTROL);
323         DUMP_REG(DSI_INIT_SEQ_DATA_0);
324         DUMP_REG(DSI_INIT_SEQ_DATA_1);
325         DUMP_REG(DSI_INIT_SEQ_DATA_2);
326         DUMP_REG(DSI_INIT_SEQ_DATA_3);
327         DUMP_REG(DSI_INIT_SEQ_DATA_4);
328         DUMP_REG(DSI_INIT_SEQ_DATA_5);
329         DUMP_REG(DSI_INIT_SEQ_DATA_6);
330         DUMP_REG(DSI_INIT_SEQ_DATA_7);
331         DUMP_REG(DSI_PKT_SEQ_0_LO);
332         DUMP_REG(DSI_PKT_SEQ_0_HI);
333         DUMP_REG(DSI_PKT_SEQ_1_LO);
334         DUMP_REG(DSI_PKT_SEQ_1_HI);
335         DUMP_REG(DSI_PKT_SEQ_2_LO);
336         DUMP_REG(DSI_PKT_SEQ_2_HI);
337         DUMP_REG(DSI_PKT_SEQ_3_LO);
338         DUMP_REG(DSI_PKT_SEQ_3_HI);
339         DUMP_REG(DSI_PKT_SEQ_4_LO);
340         DUMP_REG(DSI_PKT_SEQ_4_HI);
341         DUMP_REG(DSI_PKT_SEQ_5_LO);
342         DUMP_REG(DSI_PKT_SEQ_5_HI);
343         DUMP_REG(DSI_DCS_CMDS);
344         DUMP_REG(DSI_PKT_LEN_0_1);
345         DUMP_REG(DSI_PKT_LEN_2_3);
346         DUMP_REG(DSI_PKT_LEN_4_5);
347         DUMP_REG(DSI_PKT_LEN_6_7);
348         DUMP_REG(DSI_PHY_TIMING_0);
349         DUMP_REG(DSI_PHY_TIMING_1);
350         DUMP_REG(DSI_PHY_TIMING_2);
351         DUMP_REG(DSI_BTA_TIMING);
352         DUMP_REG(DSI_TIMEOUT_0);
353         DUMP_REG(DSI_TIMEOUT_1);
354         DUMP_REG(DSI_TO_TALLY);
355         DUMP_REG(DSI_PAD_CONTROL);
356         DUMP_REG(DSI_PAD_CONTROL_CD);
357         DUMP_REG(DSI_PAD_CD_STATUS);
358         DUMP_REG(DSI_VID_MODE_CONTROL);
359 #undef DUMP_REG
360
361         clk_disable_unprepare(dsi->dsi_clk);
362         tegra_dc_io_end(dsi->dc);
363
364         return 0;
365 }
366
367 static int dbg_dsi_open(struct inode *inode, struct file *file)
368 {
369         return single_open(file, dbg_dsi_show, inode->i_private);
370 }
371
372 static const struct file_operations dbg_fops = {
373         .open           = dbg_dsi_open,
374         .read           = seq_read,
375         .llseek         = seq_lseek,
376         .release        = single_release,
377 };
378
379 static struct dentry *dsidir;
380
381 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
382 {
383         struct dentry *retval;
384
385         dsidir = debugfs_create_dir("tegra_dsi", NULL);
386         if (!dsidir)
387                 return;
388         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
389                 &dbg_fops);
390         if (!retval)
391                 goto free_out;
392         return;
393 free_out:
394         debugfs_remove_recursive(dsidir);
395         dsidir = NULL;
396         return;
397 }
398 #else
399 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
400 { }
401 #endif
402
403 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
404 {
405         if (!tegra_is_clk_enabled(dsi->dsi_clk)) {
406                 clk_prepare_enable(dsi->dsi_clk);
407                 clk_prepare_enable(dsi->dsi_fixed_clk);
408         }
409         tegra_mipi_cal_clk_enable(dsi->mipi_cal);
410 }
411
412 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
413 {
414         if (tegra_is_clk_enabled(dsi->dsi_clk)) {
415                 clk_disable_unprepare(dsi->dsi_clk);
416                 clk_disable_unprepare(dsi->dsi_fixed_clk);
417         }
418         tegra_mipi_cal_clk_disable(dsi->mipi_cal);
419 }
420
421 static void __maybe_unused tegra_dsi_syncpt_reset(
422                                 struct tegra_dc_dsi_data *dsi)
423 {
424         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
425         /* stabilization delay */
426         udelay(300);
427         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
428         /* stabilization delay */
429         udelay(300);
430 }
431
432 static int __maybe_unused tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
433 {
434         u32 val;
435         int ret = 0;
436
437         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
438
439         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
440                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
441         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
442
443         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
444                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL);
445         if (ret < 0) {
446                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
447                 goto fail;
448         }
449
450         (dsi->syncpt_val)++;
451         return 0;
452 fail:
453         return ret;
454 }
455
456 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
457 {
458         u32 dsi_clock_rate_khz;
459
460         switch (dsi->info.video_burst_mode) {
461         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
462         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
463         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
464         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
465                 /* Calculate DSI HS clock rate for DSI burst mode */
466                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
467                                                         dsi->shift_clk_div;
468                 break;
469         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
470         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
471         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
472         default:
473                 /* Clock rate is default DSI clock rate for non-burst mode */
474                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
475                 break;
476         }
477
478         return dsi_clock_rate_khz;
479 }
480
481 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
482 {
483         u32 dsi_clock_rate_khz;
484
485         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
486                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
487                         dsi_clock_rate_khz =
488                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
489                 else
490                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
491         else
492                 if (lp_op == DSI_LP_OP_READ)
493                         dsi_clock_rate_khz =
494                                 dsi->info.lp_read_cmd_mode_freq_khz;
495                 else
496                         dsi_clock_rate_khz =
497                                 dsi->info.lp_cmd_mode_freq_khz;
498
499         return dsi_clock_rate_khz;
500 }
501
502 static u32 tegra_dsi_get_shift_clk_div(struct tegra_dc_dsi_data *dsi)
503 {
504         u32 shift_clk_div;
505         u32 max_shift_clk_div;
506         u32 burst_width;
507         u32 burst_width_max;
508
509         /* Get the real value of default shift_clk_div. default_shift_clk_div
510          * holds the real value of shift_clk_div.
511          */
512         shift_clk_div = dsi->default_shift_clk_div;
513
514         /* Calculate shift_clk_div which can matche the video_burst_mode. */
515         if (dsi->info.video_burst_mode >=
516                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
517                 /* The max_shift_clk_div is multiplied by 10 to save the
518                  * fraction
519                  */
520                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz)
521                         max_shift_clk_div = dsi->info.max_panel_freq_khz
522                                 * shift_clk_div * 10 / dsi->default_hs_clk_khz;
523                 else
524                         max_shift_clk_div = shift_clk_div * 10;
525
526                 burst_width = dsi->info.video_burst_mode
527                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
528                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
529                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
530
531                 shift_clk_div = (max_shift_clk_div - shift_clk_div * 10) *
532                         burst_width / (burst_width_max * 10) + shift_clk_div;
533         }
534
535         return shift_clk_div;
536 }
537
538 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
539                                         struct tegra_dc_dsi_data *dsi)
540 {
541         u32 h_width_pixels;
542         u32 h_act_corr = 0;
543         u32 hfp_corr = 0;
544         u32 temp = 0;
545
546         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
547                         dc->mode.h_sync_width + dc->mode.h_active;
548
549         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
550                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
551                 if (temp) {
552                         h_act_corr = dsi->info.n_data_lanes - temp;
553                         h_width_pixels += h_act_corr;
554                 }
555         }
556
557         temp = h_width_pixels % dsi->info.n_data_lanes;
558         if (temp) {
559                 hfp_corr = dsi->info.n_data_lanes - temp;
560                 h_width_pixels += hfp_corr;
561         }
562
563         while (1) {
564                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
565                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
566                 if (temp) {
567                         hfp_corr += dsi->info.n_data_lanes;
568                         h_width_pixels += dsi->info.n_data_lanes;
569                 }
570                 else
571                         break;
572         }
573
574         dc->mode.h_front_porch += hfp_corr;
575         dc->mode.h_active += h_act_corr;
576 }
577
578 static void tegra_dsi_init_sw(struct tegra_dc *dc,
579                         struct tegra_dc_dsi_data *dsi)
580 {
581         u32 h_width_pixels;
582         u32 v_width_lines;
583         u32 pixel_clk_hz;
584         u32 byte_clk_hz;
585         u32 plld_clk_mhz;
586         u8 n_data_lanes;
587
588         switch (dsi->info.pixel_format) {
589         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
590                 /* 2 bytes per pixel */
591                 dsi->pixel_scaler_mul = 2;
592                 dsi->pixel_scaler_div = 1;
593                 break;
594         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
595                 /* 2.25 bytes per pixel */
596                 dsi->pixel_scaler_mul = 9;
597                 dsi->pixel_scaler_div = 4;
598                 break;
599         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
600         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
601                 /* 3 bytes per pixel */
602                 dsi->pixel_scaler_mul = 3;
603                 dsi->pixel_scaler_div = 1;
604                 break;
605         default:
606                 break;
607         }
608
609         dsi->ulpm = false;
610         dsi->enabled = false;
611         dsi->clk_ref = false;
612
613         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
614                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
615                 n_data_lanes = dsi->info.n_data_lanes / 2;
616
617         dsi->dsi_control_val =
618                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
619                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
620                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
621                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
622
623         if (dsi->info.ganged_type)
624                 tegra_dsi_pix_correction(dc, dsi);
625
626         /* Below we are going to calculate dsi and dc clock rate.
627          * Calcuate the horizontal and vertical width.
628          */
629         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
630                         dc->mode.h_sync_width + dc->mode.h_active;
631
632         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
633                         dc->mode.v_sync_width + dc->mode.v_active;
634
635         /* Calculate minimum required pixel rate. */
636         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
637         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
638                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
639                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
640                                 "should be larger than rated refresh rate.\n");
641                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
642                                                 dsi->info.rated_refresh_rate;
643         }
644
645         /* Calculate minimum byte rate on DSI interface. */
646         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
647                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
648
649         /* Round up to multiple of mega hz. */
650         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
651                                                                 1000000);
652
653         /* Calculate default real shift_clk_div. */
654         dsi->default_shift_clk_div = (NUMOF_BIT_PER_BYTE / 2) *
655                 dsi->pixel_scaler_mul / (dsi->pixel_scaler_div *
656                 dsi->info.n_data_lanes);
657         /* Calculate default DSI hs clock. DSI interface is double data rate.
658          * Data is transferred on both rising and falling edge of clk, div by 2
659          * to get the actual clock rate.
660          */
661         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
662         dsi->default_pixel_clk_khz = plld_clk_mhz * 1000 / 2
663                                                 / dsi->default_shift_clk_div;
664
665         /* Get the actual shift_clk_div and clock rates. */
666         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
667         dsi->target_lp_clk_khz =
668                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
669         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
670
671         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
672                                                         dsi->target_hs_clk_khz);
673
674 #if DSI_USE_SYNC_POINTS
675         dsi->syncpt_id = NVSYNCPT_DSI;
676 #endif
677
678         /*
679          * Force video clock to be continuous mode if
680          * enable_hs_clock_on_lp_cmd_mode is set
681          */
682         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
683                 if (dsi->info.video_clock_mode !=
684                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
685                         dev_warn(&dc->ndev->dev,
686                                 "Force clock continuous mode\n");
687
688                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
689         }
690
691         dsi->host_ref = 0;
692         dsi->host_suspended = false;
693         spin_lock_init(&dsi->host_ref_lock);
694         mutex_init(&dsi->host_resume_lock);
695         init_completion(&dc->out->user_vblank_comp);
696         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
697         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
698 }
699
700 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
701 (platform_t_phy_ns) ? ( \
702 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
703 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
704 ((default_phy) < 0 ? 0 : (default_phy)))
705
706 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
707                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
708 {
709         phy_timing_clk->t_tlpx = SELECT_T_PHY(
710                 dsi->info.phy_timing.t_tlpx_ns,
711                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
712
713         phy_timing_clk->t_clktrail = SELECT_T_PHY(
714                 dsi->info.phy_timing.t_clktrail_ns,
715                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
716
717         phy_timing_clk->t_clkpost = SELECT_T_PHY(
718                 dsi->info.phy_timing.t_clkpost_ns,
719                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
720
721         phy_timing_clk->t_clkzero = SELECT_T_PHY(
722                 dsi->info.phy_timing.t_clkzero_ns,
723                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
724
725         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
726                 dsi->info.phy_timing.t_clkprepare_ns,
727                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
728
729         phy_timing_clk->t_clkpre = SELECT_T_PHY(
730                 dsi->info.phy_timing.t_clkpre_ns,
731                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
732 }
733
734 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
735                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
736 {
737         phy_timing_clk->t_tlpx = SELECT_T_PHY(
738                 dsi->info.phy_timing.t_tlpx_ns,
739                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
740
741         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
742                 dsi->info.phy_timing.t_hsdexit_ns,
743                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
744
745         phy_timing_clk->t_hstrail = SELECT_T_PHY(
746                 dsi->info.phy_timing.t_hstrail_ns,
747                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
748
749         phy_timing_clk->t_datzero = SELECT_T_PHY(
750                 dsi->info.phy_timing.t_datzero_ns,
751                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
752
753         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
754                 dsi->info.phy_timing.t_hsprepare_ns,
755                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
756 }
757
758 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
759                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
760 {
761         phy_timing_clk->t_tlpx = SELECT_T_PHY(
762                 dsi->info.phy_timing.t_tlpx_ns,
763                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
764 }
765
766 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
767                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
768 {
769         phy_timing_clk->t_tlpx = SELECT_T_PHY(
770                 dsi->info.phy_timing.t_tlpx_ns,
771                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
772
773         phy_timing_clk->t_taget = SELECT_T_PHY(
774                 dsi->info.phy_timing.t_taget_ns,
775                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
776
777         phy_timing_clk->t_tasure = SELECT_T_PHY(
778                 dsi->info.phy_timing.t_tasure_ns,
779                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
780
781         phy_timing_clk->t_tago = SELECT_T_PHY(
782                 dsi->info.phy_timing.t_tago_ns,
783                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
784 }
785
786 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
787                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
788 {
789         phy_timing_clk->t_tlpx = SELECT_T_PHY(
790                 dsi->info.phy_timing.t_tlpx_ns,
791                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
792
793         phy_timing_clk->t_wakeup = SELECT_T_PHY(
794                 dsi->info.phy_timing.t_wakeup_ns,
795                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
796 }
797
798 #undef SELECT_T_PHY
799
800 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
801                                 struct dsi_phy_timing_inclk *phy_timing_clk,
802                                 u32 clk_ns, u8 lphs)
803 {
804         if (!(dsi->info.ganged_type)) {
805 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
806                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
807                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
808 #endif
809         }
810
811         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
812                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
813                         (T_HSEXIT_DEFAULT(clk_ns));
814
815         if (lphs == DSI_LPHS_IN_HS_MODE) {
816                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
817                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
818         } else {
819                 /* default is LP mode */
820                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
821                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
822                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
823                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
824                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
825         }
826 }
827
828 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
829                                 struct dsi_phy_timing_inclk *phy_timing,
830                                 u32 clk_ns, u8 lphs)
831 {
832         int err = 0;
833
834 #define CHECK_RANGE(val, min, max) ( \
835                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
836                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
837
838 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
839         clk_ns = dsi->info.fpga_freq_khz ?
840                 ((1000 * 1000) / dsi->info.fpga_freq_khz) :
841                 DEFAULT_FPGA_FREQ_KHZ;
842 #endif
843
844         err = CHECK_RANGE(
845         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
846                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
847                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
848         if (err < 0) {
849                 dev_warn(&dsi->dc->ndev->dev,
850                         "dsi: Tlpx mipi range violated\n");
851                 goto fail;
852         }
853
854         if (lphs == DSI_LPHS_IN_HS_MODE) {
855                 err = CHECK_RANGE(
856                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
857                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
858                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
859                 if (err < 0) {
860                         dev_warn(&dsi->dc->ndev->dev,
861                                 "dsi: HsExit mipi range violated\n");
862                         goto fail;
863                 }
864
865                 err = CHECK_RANGE(
866                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
867                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
868                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
869                 if (err < 0) {
870                         dev_warn(&dsi->dc->ndev->dev,
871                                 "dsi: HsTrail mipi range violated\n");
872                         goto fail;
873                 }
874
875                 err = CHECK_RANGE(
876                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
877                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
878                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
879                 if (err < 0) {
880                         dev_warn(&dsi->dc->ndev->dev,
881                                 "dsi: HsZero mipi range violated\n");
882                         goto fail;
883                 }
884
885                 err = CHECK_RANGE(
886                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
887                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
888                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
889                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
890                 if (err < 0) {
891                         dev_warn(&dsi->dc->ndev->dev,
892                                 "dsi: HsPrepare mipi range violated\n");
893                         goto fail;
894                 }
895
896                 err = CHECK_RANGE(
897                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
898                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
899                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
900                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
901                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
902                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
903                 if (err < 0) {
904                         dev_warn(&dsi->dc->ndev->dev,
905                         "dsi: HsPrepare + HsZero mipi range violated\n");
906                         goto fail;
907                 }
908         } else {
909                 /* default is LP mode */
910                 err = CHECK_RANGE(
911                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
912                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
913                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
914                 if (err < 0) {
915                         dev_warn(&dsi->dc->ndev->dev,
916                                 "dsi: WakeUp mipi range violated\n");
917                         goto fail;
918                 }
919
920                 err = CHECK_RANGE(
921                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
922                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
923                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
924                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
925                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
926                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
927                 if (err < 0) {
928                         dev_warn(&dsi->dc->ndev->dev,
929                                 "dsi: TaSure mipi range violated\n");
930                         goto fail;
931                 }
932         }
933
934         if (lphs == DSI_LPHS_IN_HS_MODE ||
935                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
936                 err = CHECK_RANGE(
937                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
938                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
939                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
940                 if (err < 0) {
941                         dev_warn(&dsi->dc->ndev->dev,
942                                 "dsi: ClkTrail mipi range violated\n");
943                         goto fail;
944                 }
945
946                 err = CHECK_RANGE(
947                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
948                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
949                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
950                 if (err < 0) {
951                         dev_warn(&dsi->dc->ndev->dev,
952                                 "dsi: ClkPost mipi range violated\n");
953                         goto fail;
954                 }
955
956                 err = CHECK_RANGE(
957                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
958                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
959                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
960                 if (err < 0) {
961                         dev_warn(&dsi->dc->ndev->dev,
962                                 "dsi: ClkZero mipi range violated\n");
963                         goto fail;
964                 }
965
966                 err = CHECK_RANGE(
967                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
968                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
969                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
970                 if (err < 0) {
971                         dev_warn(&dsi->dc->ndev->dev,
972                                 "dsi: ClkPrepare mipi range violated\n");
973                         goto fail;
974                 }
975
976                 err = CHECK_RANGE(
977                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
978                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
979                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
980                 if (err < 0) {
981                         dev_warn(&dsi->dc->ndev->dev,
982                                 "dsi: ClkPre mipi range violated\n");
983                         goto fail;
984                 }
985
986                 err = CHECK_RANGE(
987                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
988                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
989                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
990                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
991                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
992                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
993                 if (err < 0) {
994                         dev_warn(&dsi->dc->ndev->dev,
995                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
996                         goto fail;
997                 }
998         }
999 fail:
1000 #undef CHECK_RANGE
1001         return err;
1002 }
1003
1004 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1005                                 struct dsi_phy_timing_inclk *phy_timing,
1006                                 u32 clk_ns, u8 lphs)
1007 {
1008         u32 hs_t_phy_ns;
1009         u32 clk_t_phy_ns;
1010         u32 t_phy_ns;
1011         u32 h_blank_ns;
1012         struct tegra_dc_mode *modes;
1013         u32 t_pix_ns;
1014         int err = 0;
1015
1016         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1017                 goto fail;
1018
1019         modes = dsi->dc->out->modes;
1020         t_pix_ns = clk_ns * BITS_PER_BYTE *
1021                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1022
1023         hs_t_phy_ns =
1024                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1025                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1026                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1027                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1028                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1029                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1030                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1031                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1032                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1033                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1034
1035         clk_t_phy_ns =
1036                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1037                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1038                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1039                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1040                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1041                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1042                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1043                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1044                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1045                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1046                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1047                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1048                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1049                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1050
1051         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1052                                                 modes->h_front_porch);
1053
1054         /* Extra tlpx and byte cycle required by dsi HW */
1055         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1056                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1057                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1058                 clk_ns * BITS_PER_BYTE);
1059
1060         if (h_blank_ns < t_phy_ns) {
1061                 err = -EINVAL;
1062                 dev_err(&dsi->dc->ndev->dev,
1063                         "dsi: Hblank is smaller than HS trans phy timing\n");
1064                 goto fail;
1065         }
1066
1067         return 0;
1068 fail:
1069         return err;
1070 }
1071
1072 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1073                                 struct dsi_phy_timing_inclk *phy_timing,
1074                                 u32 clk_ns, u8 lphs)
1075 {
1076         int err = 0;
1077
1078         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1079         if (err < 0) {
1080                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1081                 goto fail;
1082         }
1083
1084         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1085         if (err < 0) {
1086                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1087                 goto fail;
1088         }
1089
1090         /* TODO: add more contraints */
1091 fail:
1092         return err;
1093 }
1094
1095 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1096 {
1097         u32 val;
1098         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1099
1100         tegra_dsi_get_phy_timing
1101                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1102
1103         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1104                                         dsi->current_bit_clk_ns, lphs);
1105
1106         if (dsi->info.ganged_type) {
1107 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1108                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1109                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1110                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1111                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1112
1113                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1114                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1115                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1116                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1117
1118                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1119                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1120                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1121
1122                 phy_timing.t_taget += T_TAGET_HW_INC;
1123                 phy_timing.t_tasure += T_TASURE_HW_INC;
1124                 phy_timing.t_tago += T_TAGO_HW_INC;
1125 #endif
1126         }
1127         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1128                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1129                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1130                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1131         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1132
1133         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1134                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1135                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1136                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1137         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1138
1139         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1140                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1141                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1142         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1143
1144         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1145                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1146                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1147         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1148
1149         dsi->phy_timing = phy_timing;
1150 }
1151
1152 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1153                                 struct tegra_dc_dsi_data *dsi)
1154 {
1155         u32 dsi_to_pixel_clk_ratio;
1156         u32 temp;
1157         u32 temp1;
1158         u32 mipi_clk_adj_kHz = 0;
1159         u32 sol_delay;
1160         struct tegra_dc_mode *dc_modes = &dc->mode;
1161
1162         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1163         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1164                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1165
1166         /* Convert Fdsi to byte format */
1167         dsi_to_pixel_clk_ratio *= 1000/8;
1168
1169         /* Multiplying by 1000 so that we don't loose the fraction part */
1170         temp = dc_modes->h_active * 1000;
1171         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1172                         dc_modes->h_sync_width;
1173
1174         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1175                         temp * dsi->pixel_scaler_mul /
1176                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1177
1178         /* Do rounding on sol delay */
1179         sol_delay = (sol_delay + 1000 - 1)/1000;
1180
1181         /* TODO:
1182          * 1. find out the correct sol fifo depth to use
1183          * 2. verify with hw about the clamping function
1184          */
1185         if (sol_delay > (480 * 4)) {
1186                 sol_delay = (480 * 4);
1187                 mipi_clk_adj_kHz = sol_delay +
1188                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1189                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1190
1191                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1192
1193                 mipi_clk_adj_kHz *= 4;
1194         }
1195
1196         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1197
1198         return sol_delay;
1199 }
1200
1201 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1202                                 struct tegra_dc_dsi_data *dsi)
1203 {
1204         u32 sol_delay;
1205         u32 internal_delay;
1206         u32 h_width_byte_clk;
1207         u32 h_width_pixels;
1208         u32 h_width_ganged_byte_clk;
1209         u8 n_data_lanes_this_cont = 0;
1210         u8 n_data_lanes_ganged = 0;
1211
1212         if (!(dsi->info.ganged_type)) {
1213                 if (dsi->info.video_burst_mode ==
1214                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1215                         dsi->info.video_burst_mode ==
1216                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1217 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1218                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1219                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1220 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1221                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1222                 } else {
1223                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1224                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1225                 }
1226         } else {
1227 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1228 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1229 #define FIFO_WR_PIX_CLK_DELAY 2
1230 #define FIFO_RD_BYTE_CLK_DELAY 6
1231 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1232                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1233                                 FIFO_WR_PIX_CLK_DELAY)
1234
1235                 internal_delay = DIV_ROUND_UP(
1236                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1237                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1238                                 + FIFO_RD_BYTE_CLK_DELAY;
1239
1240                 h_width_pixels = dc->mode.h_sync_width +
1241                                         dc->mode.h_back_porch +
1242                                         dc->mode.h_active +
1243                                         dc->mode.h_front_porch;
1244
1245                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1246                                         dsi->pixel_scaler_mul,
1247                                         dsi->pixel_scaler_div *
1248                                         dsi->info.n_data_lanes);
1249
1250                 if (dsi->info.ganged_type ==
1251                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1252                         dsi->info.ganged_type ==
1253                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1254                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1255                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1256                 }
1257
1258                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1259                                         n_data_lanes_this_cont *
1260                                         h_width_byte_clk,
1261                                         n_data_lanes_ganged);
1262
1263                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1264                                                         internal_delay;
1265                 sol_delay = (dsi->info.video_data_type ==
1266                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1267                                 sol_delay + 20: sol_delay;
1268
1269 #undef SOL_TO_VALID_PIX_CLK_DELAY
1270 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1271 #undef FIFO_WR_PIX_CLK_DELAY
1272 #undef FIFO_RD_BYTE_CLK_DELAY
1273 #undef TOT_INTERNAL_PIX_DELAY
1274         }
1275
1276         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1277                                                 DSI_SOL_DELAY);
1278 }
1279
1280 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1281 {
1282         u32 val;
1283         u32 bytes_per_frame;
1284         u32 timeout = 0;
1285
1286         /* TODO: verify the following equation */
1287         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1288                                                 (dsi->info.refresh_rate * 8);
1289         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1290         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1291
1292         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1293                         DSI_TIMEOUT_0_HTX_TO(timeout);
1294         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1295
1296         if (dsi->info.panel_reset_timeout_msec)
1297                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1298                                         / dsi->current_bit_clk_ns;
1299         else
1300                 timeout = DSI_PR_TO_VALUE;
1301
1302         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1303                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1304         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1305
1306         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1307                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1308                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1309                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1310         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1311 }
1312
1313 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1314                                                 struct tegra_dc_dsi_data *dsi)
1315 {
1316         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1317         u32 hact_pkt_len_pix = 0;
1318         u32 hact_pkt_len_bytes = 0;
1319         u32 hfp_pkt_len_bytes = 0;
1320         u32 pix_per_line_orig = 0;
1321         u32 pix_per_line = 0;
1322         u32 val = 0;
1323
1324 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1325 #define HEADER_OVERHEAD 16
1326
1327         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1328                         dc->mode.h_active + dc->mode.h_front_porch;
1329
1330         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1331                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1332                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1333                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1334                 if (dsi->controller_index) {
1335                         hact_pkt_len_pix =
1336                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1337                         pix_per_line = pix_per_line_orig - pix_per_line;
1338                 }
1339                 hact_pkt_len_bytes = hact_pkt_len_pix *
1340                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1341                 hfp_pkt_len_bytes = pix_per_line *
1342                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1343                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1344         }
1345
1346         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1347                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1348         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1349
1350         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1351                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1352         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1353
1354         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1355                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1356         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1357
1358         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1359                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1360         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1361
1362 #undef HEADER_OVERHEAD
1363 }
1364
1365 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1366                                                 struct tegra_dc_dsi_data *dsi)
1367 {
1368         u32 val;
1369         u32 hact_pkt_len;
1370         u32 hsa_pkt_len;
1371         u32 hbp_pkt_len;
1372         u32 hfp_pkt_len;
1373
1374         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1375                                                         dsi->pixel_scaler_div;
1376         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1377                                                         dsi->pixel_scaler_div;
1378         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1379                                                         dsi->pixel_scaler_div;
1380         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1381                                                         dsi->pixel_scaler_div;
1382
1383         if (dsi->info.video_burst_mode !=
1384                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1385                 hbp_pkt_len += hsa_pkt_len;
1386
1387         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1388         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1389         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1390
1391         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1392                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1393         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1394
1395         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1396                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1397         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1398
1399         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1400                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1401         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1402
1403         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1404         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1405 }
1406
1407 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1408                                                 struct tegra_dc_dsi_data *dsi)
1409 {
1410         unsigned long   val;
1411         unsigned long   act_bytes;
1412
1413         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1414                         dsi->pixel_scaler_div + 1;
1415
1416         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1417         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1418
1419         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1420         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1421
1422         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1423         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1424
1425         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1426         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1427 }
1428
1429 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1430                                 struct tegra_dc_dsi_data *dsi)
1431 {
1432         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1433                 return;
1434
1435         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1436                 if (dsi->info.ganged_type)
1437                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1438                 else
1439                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1440         } else {
1441                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1442         }
1443 }
1444
1445 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1446                                 struct tegra_dc_dsi_data *dsi)
1447 {
1448         const u32 *pkt_seq;
1449         u32 rgb_info;
1450         u32 pkt_seq_3_5_rgb_lo;
1451         u32 pkt_seq_3_5_rgb_hi;
1452         u32     val;
1453         u32 reg;
1454         u8  i;
1455
1456         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1457                 return;
1458
1459         switch (dsi->info.pixel_format) {
1460         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1461                 rgb_info = CMD_RGB_16BPP;
1462                 break;
1463         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1464                 rgb_info = CMD_RGB_18BPP;
1465                 break;
1466         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1467                 rgb_info = CMD_RGB_18BPPNP;
1468                 break;
1469         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1470         default:
1471                 rgb_info = CMD_RGB_24BPP;
1472                 break;
1473         }
1474
1475         pkt_seq_3_5_rgb_lo = 0;
1476         pkt_seq_3_5_rgb_hi = 0;
1477         if (dsi->info.pkt_seq)
1478                 pkt_seq = dsi->info.pkt_seq;
1479         else if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1480                 pkt_seq = dsi_pkt_seq_cmd_mode;
1481         else {
1482                 switch (dsi->info.video_burst_mode) {
1483                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1484                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1485                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1486                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1487                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1488                         pkt_seq_3_5_rgb_lo =
1489                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1490                         if (!dsi->info.no_pkt_seq_eot)
1491                                 pkt_seq = dsi_pkt_seq_video_burst;
1492                         else
1493                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1494                         break;
1495                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1496                         pkt_seq_3_5_rgb_hi =
1497                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1498                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1499                         break;
1500                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1501                 default:
1502                         if (dsi->info.ganged_type) {
1503                                 pkt_seq_3_5_rgb_lo =
1504                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1505                                 pkt_seq =
1506                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1507                         } else {
1508                                 pkt_seq_3_5_rgb_lo =
1509                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1510                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1511                         }
1512                         break;
1513                 }
1514         }
1515
1516         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1517                 val = pkt_seq[i];
1518                 reg = dsi_pkt_seq_reg[i];
1519                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1520                         val |= pkt_seq_3_5_rgb_lo;
1521                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1522                         val |= pkt_seq_3_5_rgb_hi;
1523                 tegra_dsi_writel(dsi, val, reg);
1524         }
1525 }
1526
1527 static void tegra_dsi_reset_underflow_overflow
1528                                 (struct tegra_dc_dsi_data *dsi)
1529 {
1530         u32 val;
1531
1532         val = tegra_dsi_readl(dsi, DSI_STATUS);
1533         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1534         if (val) {
1535                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1536                         dev_warn(&dsi->dc->ndev->dev,
1537                                 "dsi: video fifo overflow. Resetting flag\n");
1538                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1539                         dev_warn(&dsi->dc->ndev->dev,
1540                                 "dsi: video fifo underflow. Resetting flag\n");
1541                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1542                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1543                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1544                 udelay(5);
1545         }
1546 }
1547
1548 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1549 {
1550         u32 trigger;
1551         u32 val;
1552         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1553         struct tegra_dc_mode mode = dsi->dc->mode;
1554         u32 line_period = DIV_ROUND_UP(
1555                                 MS_TO_US(frame_period),
1556                                 mode.v_sync_width + mode.v_back_porch +
1557                                 mode.v_active + mode.v_front_porch);
1558         u32 timeout_cnt = 0;
1559
1560 #define DSI_IDLE_TIMEOUT        1000
1561
1562         val = tegra_dsi_readl(dsi, DSI_STATUS);
1563         while (!(val & DSI_STATUS_IDLE(0x1))) {
1564                 cpu_relax();
1565                 udelay(line_period);
1566                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1567                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1568                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1569                         break;
1570                 }
1571         }
1572
1573         tegra_dsi_writel(dsi,
1574                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1575                 DSI_POWER_CONTROL);
1576         /* stabilization delay */
1577         udelay(300);
1578
1579         tegra_dsi_writel(dsi,
1580                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1581                 DSI_POWER_CONTROL);
1582         /* stabilization delay */
1583         udelay(300);
1584
1585         /* dsi HW does not clear host trigger bit automatically
1586          * on dsi interface disable if host fifo is empty or in mid
1587          * of host transmission
1588          */
1589         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1590         if (trigger)
1591                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1592
1593 #undef DSI_IDLE_TIMEOUT
1594 }
1595
1596 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1597                                         struct tegra_dc_dsi_data *dsi)
1598 {
1599         /* Mask the MSF interrupt. */
1600         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1601                 tegra_dc_mask_interrupt(dc, MSF_INT);
1602
1603         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1604         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1605         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1606         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1607
1608         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1609 }
1610
1611 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1612                                 struct tegra_dc_dsi_data *dsi,
1613                                 u32 timeout_n_frames)
1614 {
1615         int val;
1616         long timeout;
1617         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1618         struct tegra_dc_mode mode = dc->mode;
1619         u32 line_period = DIV_ROUND_UP(
1620                                 MS_TO_US(frame_period),
1621                                 mode.v_sync_width + mode.v_back_porch +
1622                                 mode.v_active + mode.v_front_porch);
1623
1624         if (timeout_n_frames < 2)
1625                 dev_WARN(&dc->ndev->dev,
1626                 "dsi: to stop at next frame give at least 2 frame delay\n");
1627
1628         if (timeout_n_frames < 2)
1629                 dev_WARN(&dc->ndev->dev,
1630                 "dsi: to stop at next frame give at least 2 frame delay\n");
1631
1632         INIT_COMPLETION(dc->frame_end_complete);
1633
1634         /* unmask frame end interrupt */
1635         val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1636
1637         timeout = wait_for_completion_interruptible_timeout(
1638                         &dc->frame_end_complete,
1639                         msecs_to_jiffies(timeout_n_frames * frame_period));
1640
1641         /* reinstate interrupt mask */
1642         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1643
1644         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1645         udelay(mode.v_ref_to_sync * line_period);
1646
1647         return timeout;
1648 }
1649
1650 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1651                                                 struct tegra_dc_dsi_data *dsi,
1652                                                 u32 timeout_n_frames)
1653 {
1654         long timeout;
1655
1656         tegra_dsi_stop_dc_stream(dc, dsi);
1657
1658         timeout = tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1659
1660         tegra_dsi_soft_reset(dsi);
1661
1662         if (timeout == 0)
1663                 dev_warn(&dc->ndev->dev,
1664                         "DC doesn't stop at end of frame.\n");
1665
1666         tegra_dsi_reset_underflow_overflow(dsi);
1667 }
1668
1669 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1670                                         struct tegra_dc_dsi_data *dsi)
1671 {
1672         u32 val;
1673
1674         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1675
1676         /* TODO: clean up */
1677         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1678                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1679                         DC_CMD_DISPLAY_POWER_CONTROL);
1680
1681         /* Configure one-shot mode or continuous mode */
1682         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1683                 /* disable LSPI/LCD_DE output */
1684                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1685                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1686
1687                 /* enable MSF & set MSF polarity */
1688                 val = MSF_ENABLE | MSF_LSPI;
1689                 if (!dsi->info.te_polarity_low)
1690                         val |= MSF_POLARITY_HIGH;
1691                 else
1692                         val |= MSF_POLARITY_LOW;
1693                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1694
1695                 /* set non-continuous mode */
1696                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1697                                                 DC_CMD_DISPLAY_COMMAND);
1698                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1699                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1700                                                 DC_CMD_STATE_CONTROL);
1701
1702                 /* Unmask the MSF interrupt. */
1703                 tegra_dc_unmask_interrupt(dc, MSF_INT);
1704         } else {
1705                 /* set continuous mode */
1706                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1707                                                 DC_CMD_DISPLAY_COMMAND);
1708                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1709                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1710         }
1711
1712         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1713 }
1714
1715 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1716                                 struct tegra_dc_dsi_data *dsi)
1717 {
1718         u32 shift_clk_div_register;
1719         u32 val;
1720
1721         /* Get the corresponding register value of shift_clk_div. */
1722         shift_clk_div_register = dsi->shift_clk_div * 2 - 2;
1723
1724 #ifndef CONFIG_TEGRA_SILICON_PLATFORM
1725         shift_clk_div_register = 1;
1726         if (dsi->info.ganged_type)
1727                 shift_clk_div_register = 0;
1728 #endif
1729
1730         /* TODO: find out if PCD3 option is required */
1731         val = PIXEL_CLK_DIVIDER_PCD1 |
1732                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1733         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1734 }
1735
1736 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1737                         struct tegra_dc_dsi_data *dsi, u32 clk)
1738 {
1739         u32 rm;
1740
1741         /* Round up to MHz */
1742         rm = clk % 1000;
1743         if (rm != 0)
1744                 clk -= rm;
1745
1746         /* Set up pixel clock */
1747         dc->shift_clk_div = dsi->shift_clk_div;
1748         dc->mode.pclk = (clk * 1000) / dsi->shift_clk_div;
1749         /* TODO: Define one shot work delay in board file. */
1750         /* Since for one-shot mode, refresh rate is usually set larger than
1751          * expected refresh rate, it needs at least 3 frame period. Less
1752          * delay one shot work is, more powering saving we have. */
1753         dc->one_shot_delay_ms = 4 *
1754                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1755
1756         /* Enable DSI clock */
1757         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1758         tegra_dsi_clk_enable(dsi);
1759         tegra_periph_reset_deassert(dsi->dsi_clk);
1760
1761         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1762         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1763 }
1764
1765 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1766 {
1767         u32 val;
1768
1769         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1770         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1771
1772         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1773                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1774                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1775         } else {
1776                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1777                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1778         }
1779         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1780
1781         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1782         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1783         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1784         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1785
1786         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1787 }
1788
1789 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1790 {
1791         u32 val;
1792         tegra_dsi_hs_clk_out_enable(dsi);
1793
1794         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1795         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1796         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1797         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1798 }
1799
1800 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1801                                                 struct tegra_dc_dsi_data *dsi)
1802 {
1803         u32 val;
1804
1805         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1806                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1807
1808         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1809         /* stabilization delay */
1810         udelay(300);
1811
1812         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1813         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1814         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1815         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1816
1817         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1818         /* stabilization delay */
1819         udelay(300);
1820
1821         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1822         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1823 }
1824
1825 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1826 {
1827         u32 dsi_control;
1828         u32 host_dsi_control;
1829         u32 max_threshold;
1830
1831         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1832         host_dsi_control = HOST_DSI_CTRL_COMMON |
1833                         HOST_DSI_CTRL_HOST_DRIVEN |
1834                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1835         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1836
1837         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1838         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1839         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1840
1841         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1842         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1843         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1844 }
1845
1846 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1847                                                 u8 driven_mode)
1848 {
1849         u32 dsi_control;
1850         u32 host_dsi_control;
1851         u32 max_threshold;
1852         u32 dcs_cmd;
1853
1854         dsi_control = dsi->dsi_control_val;
1855         host_dsi_control = HOST_DSI_CTRL_COMMON;
1856         max_threshold = 0;
1857         dcs_cmd = 0;
1858
1859         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1860                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1861                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1862                 max_threshold =
1863                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1864                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1865         } else {
1866                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1867                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1868                 max_threshold =
1869                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1870                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1871
1872                 if (dsi->info.video_data_type ==
1873                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1874                         dsi_control |= DSI_CTRL_CMD_MODE;
1875                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1876                                 DSI_WRITE_MEMORY_START)|
1877                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1878                                 DSI_WRITE_MEMORY_CONTINUE);
1879                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1880                 } else {
1881                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1882                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1883                 }
1884         }
1885
1886         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1887         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1888         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1889         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1890 }
1891
1892 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1893 {
1894         u32 val;
1895
1896         if (dsi->info.controller_vs == DSI_VS_1) {
1897                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1898                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1899                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1900                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1901                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1902                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1903                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1904                                                 (TEGRA_DSI_PAD_DISABLE) |
1905                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1906                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1907                                                 (TEGRA_DSI_PAD_DISABLE);
1908                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1909         } else {
1910                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1911                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1912                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1913                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1914                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1915                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1916                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1917                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1918         }
1919 }
1920
1921 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1922 {
1923         u32 val;
1924
1925         if (dsi->info.controller_vs == DSI_VS_1) {
1926                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1927                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1928                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1929                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1930                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1931                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1932                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
1933                                                 TEGRA_DSI_PAD_ENABLE) |
1934                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
1935                                                 TEGRA_DSI_PAD_ENABLE) |
1936                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
1937                                                 TEGRA_DSI_PAD_ENABLE);
1938                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1939         } else {
1940                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1941                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1942                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1943                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1944                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
1945                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
1946                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
1947                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1948         }
1949 }
1950
1951 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
1952 {
1953         u32 val;
1954
1955         if (!dsi->ulpm)
1956                 tegra_dsi_pad_enable(dsi);
1957         else
1958                 tegra_dsi_pad_disable(dsi);
1959
1960         if (dsi->info.controller_vs == DSI_VS_1) {
1961                 /* TODO: characterization parameters */
1962         } else {
1963                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1964                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
1965                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
1966                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1967                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
1968                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
1969
1970                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
1971                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
1972                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
1973                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
1974                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
1975
1976                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1977
1978                 val = MIPI_CAL_TERMOSA(0x4);
1979                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
1980
1981                 val = MIPI_CAL_TERMOSB(0x4);
1982                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
1983
1984                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
1985                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
1986
1987                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
1988                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
1989         }
1990
1991         val = PAD_CIL_PDVREG(0x0);
1992         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
1993 }
1994
1995 static void tegra_dsi_panelB_enable(void)
1996 {
1997         unsigned int val;
1998
1999         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2000         val |= DSIB_MODE_ENABLE;
2001         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2002 }
2003
2004 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2005                                 struct tegra_dc_dsi_data *dsi)
2006 {
2007         u32 i;
2008
2009         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2010
2011         /* Stop DC stream before configuring DSI registers
2012          * to avoid visible glitches on panel during transition
2013          * from bootloader to kernel driver
2014          * TODO: Delayed frame end interrupt from bootloader
2015          */
2016         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 50);
2017
2018         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2019
2020         /* Stop DC stream before configuring DSI registers
2021          * to avoid visible glitches on panel during transition
2022          * from bootloader to kernel driver
2023          * TODO: Delayed frame end interrupt from bootloader
2024          */
2025         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 50);
2026
2027         tegra_dsi_writel(dsi,
2028                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2029                 DSI_POWER_CONTROL);
2030         /* stabilization delay */
2031         udelay(300);
2032
2033         if (dsi->info.dsi_instance) {
2034                 tegra_dsi_panelB_enable();
2035                 /* TODO:Set the misc register */
2036         }
2037
2038         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2039
2040         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2041                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2042
2043         /* Initialize DSI registers */
2044         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2045                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2046         if (dsi->info.controller_vs == DSI_VS_1) {
2047                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2048                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2049         }
2050
2051         tegra_dsi_writel(dsi, dsi->dsi_control_val, DSI_CONTROL);
2052
2053         tegra_dsi_pad_calibration(dsi);
2054
2055         tegra_mipi_cal_init_hw(dsi->mipi_cal);
2056
2057         tegra_mipi_cal_write(dsi->mipi_cal, MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2058                                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2059         tegra_mipi_cal_write(dsi->mipi_cal, PAD_PDVREG(0x0),
2060                                 MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2061
2062         tegra_dsi_writel(dsi,
2063                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2064                 DSI_POWER_CONTROL);
2065         /* stabilization delay */
2066         udelay(300);
2067
2068         dsi->status.init = DSI_MODULE_INIT;
2069         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2070         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2071         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2072         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2073         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2074         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2075         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2076         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2077
2078         return 0;
2079 }
2080
2081 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2082                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2083 {
2084         int err;
2085
2086         if (dsi->status.init != DSI_MODULE_INIT) {
2087                 err = -EPERM;
2088                 goto fail;
2089         }
2090
2091         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2092                         dsi->status.lp_op == lp_op)
2093                 goto success;
2094
2095         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2096                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2097
2098         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2099         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2100                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2101                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2102
2103         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2104         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2105                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2106                 tegra_dsi_set_timeout(dsi);
2107         }
2108
2109         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2110
2111         tegra_dsi_set_control_reg_lp(dsi);
2112
2113         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2114                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2115                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2116
2117         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2118         dsi->status.lp_op = lp_op;
2119         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2120 success:
2121         err = 0;
2122 fail:
2123         return err;
2124 }
2125
2126 static void tegra_dsi_ganged(struct tegra_dc *dc,
2127                                 struct tegra_dc_dsi_data *dsi)
2128 {
2129         u32 start = 0;
2130         u32 low_width = 0;
2131         u32 high_width = 0;
2132         u32 h_active = dc->out->modes->h_active;
2133         u32 val = 0;
2134
2135         if (dsi->info.controller_vs < DSI_VS_1) {
2136                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2137                 "supported with current controller version\n");
2138                 return;
2139         }
2140
2141         if (dsi->info.ganged_type ==
2142                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2143                 low_width = DIV_ROUND_UP(h_active, 2);
2144                 high_width = h_active - low_width;
2145                 if (dsi->controller_index)
2146                         start = h_active / 2;
2147                 else
2148                         start = 0;
2149         } else if (dsi->info.ganged_type ==
2150                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2151                 low_width = 0x1;
2152                 high_width = 0x1;
2153                 if (dsi->controller_index)
2154                         start = 1;
2155                 else
2156                         start = 0;
2157         }
2158
2159         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2160                                                 DSI_GANGED_MODE_START);
2161
2162         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2163                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2164         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2165
2166         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2167                                                 DSI_GANGED_MODE_CONTROL);
2168 }
2169
2170 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2171                                         struct tegra_dc_dsi_data *dsi,
2172                                         u8 driven_mode)
2173 {
2174         int err;
2175
2176         if (dsi->status.init != DSI_MODULE_INIT) {
2177                 err = -EPERM;
2178                 goto fail;
2179         }
2180
2181         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2182                 dsi->driven_mode == driven_mode)
2183                 goto success;
2184
2185         dsi->driven_mode = driven_mode;
2186
2187         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2188                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2189
2190         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2191                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2192                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2193
2194         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2195                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2196                 tegra_dsi_set_timeout(dsi);
2197         }
2198
2199         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2200
2201         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2202                 tegra_dsi_set_pkt_seq(dc, dsi);
2203                 tegra_dsi_set_pkt_length(dc, dsi);
2204                 tegra_dsi_set_sol_delay(dc, dsi);
2205                 tegra_dsi_set_dc_clk(dc, dsi);
2206         }
2207
2208         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2209
2210         if (dsi->info.ganged_type)
2211                 tegra_dsi_ganged(dc, dsi);
2212
2213         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2214                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2215                 tegra_dsi_hs_clk_out_enable(dsi);
2216
2217         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2218 success:
2219         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2220         err = 0;
2221 fail:
2222         return err;
2223 }
2224
2225 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2226 {
2227         u32 timeout = 0;
2228         bool retVal = true;
2229
2230         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2231                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2232                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2233                         retVal = false;
2234                         break;
2235                 }
2236                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2237                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2238         }
2239
2240         return retVal;
2241 }
2242
2243 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2244 {
2245         u32 timeout = 0;
2246         bool retVal = true;
2247
2248         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2249                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2250                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2251                         retVal = false;
2252                         break;
2253                 }
2254                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2255                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2256         }
2257
2258         return retVal;
2259 }
2260
2261 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2262 {
2263         int err = 0;
2264
2265         if (tegra_dsi_write_busy(dsi)) {
2266                 err = -EBUSY;
2267                 dev_err(&dsi->dc->ndev->dev,
2268                         "DSI trigger bit already set\n");
2269                 goto fail;
2270         }
2271
2272         if (tegra_dsi_read_busy(dsi)) {
2273                 err = -EBUSY;
2274                 dev_err(&dsi->dc->ndev->dev,
2275                         "DSI immediate bta bit already set\n");
2276                 goto fail;
2277         }
2278 fail:
2279         return (err < 0 ? true : false);
2280 }
2281
2282 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2283 {
2284         u32 val;
2285
2286         val = tegra_dsi_readl(dsi, DSI_STATUS);
2287         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2288         if (val) {
2289                 dev_warn(&dsi->dc->ndev->dev,
2290                         "DSI read count not zero, resetting\n");
2291                 tegra_dsi_soft_reset(dsi);
2292         }
2293 }
2294
2295 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2296                                                 struct tegra_dc_dsi_data *dsi,
2297                                                 struct tegra_dc *dc,
2298                                                 u8 lp_op)
2299 {
2300         struct dsi_status *init_status = NULL;
2301         int err;
2302
2303         if (dsi->status.init != DSI_MODULE_INIT ||
2304                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2305                 err = -EPERM;
2306                 goto fail;
2307         }
2308
2309         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2310         if (!init_status)
2311                 return ERR_PTR(-ENOMEM);
2312
2313         *init_status = dsi->status;
2314
2315         if (dsi->info.hs_cmd_mode_supported) {
2316                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2317                                 TEGRA_DSI_DRIVEN_BY_HOST);
2318                 if (err < 0) {
2319                         dev_err(&dc->ndev->dev,
2320                         "Switch to HS host mode failed\n");
2321                         goto fail;
2322                 }
2323
2324                 goto success;
2325         }
2326
2327         if (dsi->status.lp_op != lp_op) {
2328                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2329                 if (err < 0) {
2330                         dev_err(&dc->ndev->dev,
2331                         "DSI failed to go to LP mode\n");
2332                         goto fail;
2333                 }
2334         }
2335 success:
2336         return init_status;
2337 fail:
2338         kfree(init_status);
2339         return ERR_PTR(err);
2340 }
2341
2342 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2343                                 struct tegra_dc *dc,
2344                                 struct tegra_dc_dsi_data *dsi,
2345                                 u8 lp_op)
2346 {
2347         int err = 0;
2348         struct dsi_status *init_status;
2349         bool restart_dc_stream = false;
2350
2351         if (dsi->status.init != DSI_MODULE_INIT ||
2352                 dsi->ulpm) {
2353                 err = -EPERM;
2354                 goto fail;
2355         }
2356
2357         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2358                 restart_dc_stream = true;
2359                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2360         }
2361
2362         if (tegra_dsi_host_busy(dsi)) {
2363                 tegra_dsi_soft_reset(dsi);
2364                 if (tegra_dsi_host_busy(dsi)) {
2365                         err = -EBUSY;
2366                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2367                         goto fail;
2368                 }
2369         }
2370
2371         if (lp_op == DSI_LP_OP_READ)
2372                 tegra_dsi_reset_read_count(dsi);
2373
2374         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2375                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2376                 if (err < 0) {
2377                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2378                         goto fail;
2379                 }
2380         }
2381
2382         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2383                                         (dsi, dc, lp_op);
2384         if (IS_ERR_OR_NULL(init_status)) {
2385                 err = PTR_ERR(init_status);
2386                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2387                 goto fail;
2388         }
2389
2390         if (restart_dc_stream)
2391                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2392
2393         if (atomic_read(&dsi_syncpt_rst))
2394                 tegra_dsi_syncpt_reset(dsi);
2395
2396         return init_status;
2397 fail:
2398         return ERR_PTR(err);
2399 }
2400
2401 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2402                                 struct tegra_dc_dsi_data *dsi,
2403                                 struct dsi_status *init_status)
2404 {
2405         int err = 0;
2406
2407         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2408                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2409                 if (err < 0) {
2410                         dev_err(&dc->ndev->dev,
2411                                 "Failed to config LP mode\n");
2412                         goto fail;
2413                 }
2414                 goto success;
2415         }
2416
2417         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2418                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2419                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2420                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2421                 if (err < 0) {
2422                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2423                         goto fail;
2424                 }
2425         }
2426
2427         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2428                 tegra_dsi_start_dc_stream(dc, dsi);
2429 success:
2430 fail:
2431         kfree(init_status);
2432         return err;
2433 }
2434
2435 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2436 {
2437         int status = 0;
2438
2439         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2440                 status = -EBUSY;
2441                 goto fail;
2442         }
2443
2444         tegra_dsi_writel(dsi,
2445                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2446
2447 #if DSI_USE_SYNC_POINTS
2448         status = tegra_dsi_syncpt(dsi);
2449         if (status < 0) {
2450                 dev_err(&dsi->dc->ndev->dev,
2451                         "DSI syncpt for host trigger failed\n");
2452                 goto fail;
2453         }
2454 #else
2455         if (tegra_dsi_write_busy(dsi)) {
2456                 status = -EBUSY;
2457                 dev_err(&dsi->dc->ndev->dev,
2458                         "Timeout waiting on write completion\n");
2459         }
2460 #endif
2461
2462 fail:
2463         return status;
2464 }
2465
2466 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2467                                         u8 *pdata, u8 data_id, u16 data_len)
2468 {
2469         u8 virtual_channel;
2470         u32 val;
2471         int err;
2472
2473         err = 0;
2474
2475         virtual_channel = dsi->info.virtual_channel <<
2476                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2477
2478         /* always use hw for ecc */
2479         val = (virtual_channel | data_id) << 0 |
2480                         data_len << 8;
2481         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2482
2483         /* if pdata != NULL, pkt type is long pkt */
2484         if (pdata != NULL) {
2485                 while (data_len) {
2486                         if (data_len >= 4) {
2487                                 val = ((u32 *) pdata)[0];
2488                                 data_len -= 4;
2489                                 pdata += 4;
2490                         } else {
2491                                 val = 0;
2492                                 memcpy(&val, pdata, data_len);
2493                                 pdata += data_len;
2494                                 data_len = 0;
2495                         }
2496                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2497                 }
2498         }
2499
2500         err = tegra_dsi_host_trigger(dsi);
2501         if (err < 0)
2502                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2503
2504         return err;
2505 }
2506
2507 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2508 {
2509         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2510
2511         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2512                 spin_lock(&dsi->host_ref_lock);
2513                 dsi->host_ref++;
2514                 spin_unlock(&dsi->host_ref_lock);
2515                 tegra_dsi_host_resume(dc);
2516
2517                 /*
2518                  * Take an extra refrence to count for the clk_disable in
2519                  * tegra_dc_release_host.
2520                  */
2521                 clk_prepare_enable(dc->clk);
2522         }
2523 }
2524
2525 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2526 {
2527         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2528         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2529                 clk_disable_unprepare(dc->clk);
2530                 spin_lock(&dsi->host_ref_lock);
2531                 dsi->host_ref--;
2532
2533                 if (!dsi->host_ref &&
2534                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2535                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2536
2537                 spin_unlock(&dsi->host_ref_lock);
2538         }
2539 }
2540
2541 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2542 {
2543         struct tegra_dc_dsi_data *dsi = container_of(
2544                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2545
2546         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2547                 tegra_dsi_host_suspend(dsi->dc);
2548 }
2549
2550 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2551                         struct tegra_dc_dsi_data *dsi,
2552                         u8 *pdata, u8 data_id, u16 data_len)
2553 {
2554         int err = 0;
2555         struct dsi_status *init_status;
2556
2557         init_status = tegra_dsi_prepare_host_transmission(
2558                                 dc, dsi, DSI_LP_OP_WRITE);
2559         if (IS_ERR_OR_NULL(init_status)) {
2560                 err = PTR_ERR(init_status);
2561                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2562                 goto fail;
2563         }
2564
2565         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2566 fail:
2567         err = tegra_dsi_restore_state(dc, dsi, init_status);
2568         if (err < 0)
2569                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2570
2571         return err;
2572 }
2573
2574 int tegra_dsi_write_data(struct tegra_dc *dc,
2575                         struct tegra_dc_dsi_data *dsi,
2576                         u8 *pdata, u8 data_id, u16 data_len)
2577 {
2578         int err;
2579
2580         tegra_dc_io_start(dc);
2581         tegra_dc_dsi_hold_host(dc);
2582
2583         err = tegra_dsi_write_data_nosync(dc, dsi, pdata, data_id, data_len);
2584
2585         tegra_dc_dsi_release_host(dc);
2586         tegra_dc_io_end(dc);
2587
2588         return err;
2589 }
2590
2591 EXPORT_SYMBOL(tegra_dsi_write_data);
2592
2593 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2594                                         struct tegra_dc_dsi_data *dsi,
2595                                         struct tegra_dsi_cmd *cmd,
2596                                         u32 n_cmd)
2597 {
2598         u32 i;
2599         int err;
2600
2601         err = 0;
2602         for (i = 0; i < n_cmd; i++) {
2603                 struct tegra_dsi_cmd *cur_cmd;
2604                 cur_cmd = &cmd[i];
2605
2606                 /*
2607                  * Some Panels need reset midway in the command sequence.
2608                  */
2609                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
2610                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
2611                                        cur_cmd->data_id);
2612                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
2613                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2614                 } else {
2615                         err = tegra_dsi_write_data_nosync(dc, dsi,
2616                                                 cur_cmd->pdata,
2617                                                 cur_cmd->data_id,
2618                                                 cur_cmd->sp_len_dly.data_len);
2619                         mdelay(1);
2620                         if (err < 0)
2621                                 break;
2622                 }
2623         }
2624         return err;
2625 }
2626
2627 static u8 tegra_dsi_ecc(u32 header)
2628 {
2629         char ecc_parity[24] = {
2630                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2631                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2632                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2633         };
2634         u8 ecc_byte;
2635         int i;
2636
2637         ecc_byte = 0;
2638         for (i = 0; i < 24; i++)
2639                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2640
2641         return ecc_byte;
2642 }
2643
2644 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2645 {
2646         u16 byte_cnt;
2647         u8 bit_cnt;
2648         char curr_byte;
2649         u16 crc = 0xFFFF;
2650         u16 poly = 0x8408;
2651
2652         if (data_len > 0) {
2653                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2654                         curr_byte = pdata[byte_cnt];
2655                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2656                                 if (((crc & 0x0001 ) ^
2657                                         (curr_byte & 0x0001)) > 0)
2658                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2659                                 else
2660                                         crc = (crc >> 1) & 0x7FFF;
2661
2662                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2663                         }
2664                 }
2665         }
2666         return crc;
2667 }
2668
2669 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2670                                                 struct tegra_dsi_cmd *cmd)
2671 {
2672         u8 virtual_channel;
2673         u32 val;
2674         u16 data_len = cmd->sp_len_dly.data_len;
2675         u8 seq_ctrl_reg = 0;
2676
2677         virtual_channel = dsi->info.virtual_channel <<
2678                                 DSI_VIR_CHANNEL_BIT_POSITION;
2679
2680         val = (virtual_channel | cmd->data_id) << 0 |
2681                 data_len << 8;
2682
2683         val |= tegra_dsi_ecc(val) << 24;
2684
2685         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2686
2687         /* if pdata != NULL, pkt type is long pkt */
2688         if (cmd->pdata != NULL) {
2689                 u8 *pdata;
2690                 u8 *pdata_mem;
2691                 /* allocate memory for pdata + 2 bytes checksum */
2692                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2693                 if (!pdata_mem) {
2694                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2695                         tegra_dsi_soft_reset(dsi);
2696                         return -ENOMEM;
2697                 }
2698
2699                 memcpy(pdata_mem, cmd->pdata, data_len);
2700                 pdata = pdata_mem;
2701                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2702
2703                 /* data_len = length of pdata + 2 byte checksum */
2704                 data_len += 2;
2705
2706                 while (data_len) {
2707                         if (data_len >= 4) {
2708                                 val = ((u32 *) pdata)[0];
2709                                 data_len -= 4;
2710                                 pdata += 4;
2711                         } else {
2712                                 val = 0;
2713                                 memcpy(&val, pdata, data_len);
2714                                 pdata += data_len;
2715                                 data_len = 0;
2716                         }
2717                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2718                                                         seq_ctrl_reg++);
2719                 }
2720                 kfree(pdata_mem);
2721         }
2722
2723         return 0;
2724 }
2725
2726 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2727                                                 struct tegra_dsi_cmd *cmd)
2728 {
2729 #define PKT_HEADER_LEN_BYTE     4
2730 #define CHECKSUM_LEN_BYTE       2
2731
2732         int err = 0;
2733         u32 val;
2734         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2735         struct tegra_dc *dc = dsi->dc;
2736
2737         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2738                 return -EINVAL;
2739
2740         mutex_lock(&dsi->lock);
2741         tegra_dc_io_start(dc);
2742         tegra_dc_dsi_hold_host(dc);
2743
2744 #if DSI_USE_SYNC_POINTS
2745         atomic_set(&dsi_syncpt_rst, 1);
2746 #endif
2747
2748         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2749         if (err < 0) {
2750                 dev_err(&dsi->dc->ndev->dev,
2751                         "dsi: dcs pkt seq ctrl init failed\n");
2752                 goto fail;
2753         }
2754
2755         if (cmd->pdata) {
2756                 u16 data_len = cmd->sp_len_dly.data_len;
2757                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2758         }
2759
2760         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2761                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2762                                                 TEGRA_DSI_ENABLE);
2763         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2764
2765 fail:
2766         tegra_dc_dsi_release_host(dc);
2767         tegra_dc_io_end(dc);
2768         mutex_unlock(&dsi->lock);
2769         return err;
2770
2771 #undef PKT_HEADER_LEN_BYTE
2772 #undef CHECKSUM_LEN_BYTE
2773 }
2774 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2775
2776 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2777 {
2778         struct tegra_dc *dc = dsi->dc;
2779         u32 cnt;
2780
2781         mutex_lock(&dsi->lock);
2782         tegra_dc_io_start(dc);
2783         tegra_dc_dsi_hold_host(dc);
2784
2785         if (atomic_read(&dsi_syncpt_rst)) {
2786                 tegra_dsi_wait_frame_end(dc, dsi, 2);
2787                 tegra_dsi_syncpt_reset(dsi);
2788                 atomic_set(&dsi_syncpt_rst, 0);
2789         }
2790
2791         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2792
2793         /* clear seq data registers */
2794         for (cnt = 0; cnt < 8; cnt++)
2795                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2796
2797         tegra_dc_dsi_release_host(dc);
2798         tegra_dc_io_end(dc);
2799
2800         mutex_unlock(&dsi->lock);
2801 }
2802 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2803
2804 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2805 {
2806         u32 val;
2807         int err = 0;
2808
2809         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2810         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2811         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2812
2813 #if DSI_USE_SYNC_POINTS
2814         err = tegra_dsi_syncpt(dsi);
2815         if (err < 0) {
2816                 dev_err(&dsi->dc->ndev->dev,
2817                         "DSI syncpt for bta failed\n");
2818         }
2819 #else
2820         if (tegra_dsi_read_busy(dsi)) {
2821                 err = -EBUSY;
2822                 dev_err(&dsi->dc->ndev->dev,
2823                         "Timeout wating on read completion\n");
2824         }
2825 #endif
2826
2827         return err;
2828 }
2829
2830 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2831                                         u32 rd_fifo_cnt, u8 *read_fifo)
2832 {
2833         int err;
2834         u32 payload_size;
2835
2836         payload_size = 0;
2837         err = 0;
2838
2839         switch (read_fifo[0]) {
2840         case DSI_ESCAPE_CMD:
2841                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2842                 break;
2843         case DSI_ACK_NO_ERR:
2844                 dev_info(&dc->ndev->dev,
2845                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2846                 return err;
2847         default:
2848                 dev_info(&dc->ndev->dev, "Invalid read response\n");
2849                 break;
2850         }
2851
2852         switch (read_fifo[4] & 0xff) {
2853         case GEN_LONG_RD_RES:
2854                 /* Fall through */
2855         case DCS_LONG_RD_RES:
2856                 payload_size = (read_fifo[5] |
2857                                 (read_fifo[6] << 8)) & 0xFFFF;
2858                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
2859                                 "payload_size[0x%x]\n", payload_size);
2860                 break;
2861         case GEN_1_BYTE_SHORT_RD_RES:
2862                 /* Fall through */
2863         case DCS_1_BYTE_SHORT_RD_RES:
2864                 payload_size = 1;
2865                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2866                         "payload_size[0x%x]\n", payload_size);
2867                 break;
2868         case GEN_2_BYTE_SHORT_RD_RES:
2869                 /* Fall through */
2870         case DCS_2_BYTE_SHORT_RD_RES:
2871                 payload_size = 2;
2872                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
2873                         "payload_size[0x%x]\n", payload_size);
2874                 break;
2875         case ACK_ERR_RES:
2876                 payload_size = 2;
2877                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
2878                         "Packet payload_size[0x%x]\n", payload_size);
2879                 break;
2880         default:
2881                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
2882                 err = -EINVAL;
2883                 break;
2884         }
2885         return err;
2886 }
2887
2888 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
2889                         struct tegra_dc_dsi_data *dsi,
2890                         u8 *read_fifo)
2891 {
2892         u32 val;
2893         u32 i;
2894         u32 poll_time = 0;
2895         u32 rd_fifo_cnt;
2896         int err = 0;
2897         u8 *read_fifo_cp = read_fifo;
2898
2899         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
2900                 mdelay(1);
2901                 val = tegra_dsi_readl(dsi, DSI_STATUS);
2902                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
2903                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
2904                         dev_err(&dc->ndev->dev,
2905                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
2906                         break;
2907                 }
2908                 poll_time++;
2909         }
2910
2911         if (rd_fifo_cnt == 0) {
2912                 dev_info(&dc->ndev->dev,
2913                         "DSI RD_FIFO_CNT is zero\n");
2914                 err = -EINVAL;
2915                 goto fail;
2916         }
2917
2918         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
2919                 DSI_STATUS_LB_OVERFLOW(0x1))) {
2920                 dev_warn(&dc->ndev->dev,
2921                         "DSI overflow/underflow error\n");
2922         }
2923
2924         /* Read data from FIFO */
2925         for (i = 0; i < rd_fifo_cnt; i++) {
2926                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
2927                 if (enable_read_debug)
2928                         dev_info(&dc->ndev->dev,
2929                         "Read data[%d]: 0x%x\n", i, val);
2930                 memcpy(read_fifo, &val, 4);
2931                 read_fifo += 4;
2932         }
2933
2934         /* Make sure all the data is read from the FIFO */
2935         val = tegra_dsi_readl(dsi, DSI_STATUS);
2936         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2937         if (val)
2938                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
2939                 " even after reading FIFO_RD_CNT words from read fifo\n");
2940
2941         if (enable_read_debug) {
2942                 err =
2943                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
2944                 if (err < 0)
2945                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
2946         }
2947 fail:
2948         return err;
2949 }
2950
2951 int tegra_dsi_read_data(struct tegra_dc *dc,
2952                                 struct tegra_dc_dsi_data *dsi,
2953                                 u32 max_ret_payload_size,
2954                                 u32 panel_reg_addr, u8 *read_data)
2955 {
2956         int err = 0;
2957         struct dsi_status *init_status;
2958
2959         mutex_lock(&dsi->lock);
2960         tegra_dc_io_start(dc);
2961
2962         init_status = tegra_dsi_prepare_host_transmission(
2963                                 dc, dsi, DSI_LP_OP_WRITE);
2964         if (IS_ERR_OR_NULL(init_status)) {
2965                 err = PTR_ERR(init_status);
2966                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2967                 goto fail;
2968         }
2969
2970         /* Set max return payload size in words */
2971         err = _tegra_dsi_write_data(dsi, NULL,
2972                 dsi_command_max_return_pkt_size,
2973                 max_ret_payload_size);
2974         if (err < 0) {
2975                 dev_err(&dc->ndev->dev,
2976                                 "DSI write failed\n");
2977                 goto fail;
2978         }
2979
2980         /* DCS to read given panel register */
2981         err = _tegra_dsi_write_data(dsi, NULL,
2982                 dsi_command_dcs_read_with_no_params,
2983                 panel_reg_addr);
2984         if (err < 0) {
2985                 dev_err(&dc->ndev->dev,
2986                                 "DSI write failed\n");
2987                 goto fail;
2988         }
2989
2990         tegra_dsi_reset_read_count(dsi);
2991
2992         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
2993                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
2994                 if (err < 0) {
2995                         dev_err(&dc->ndev->dev,
2996                         "DSI failed to go to LP read mode\n");
2997                         goto fail;
2998                 }
2999         }
3000
3001         err = tegra_dsi_bta(dsi);
3002         if (err < 0) {
3003                 dev_err(&dc->ndev->dev,
3004                         "DSI IMM BTA timeout\n");
3005                 goto fail;
3006         }
3007
3008         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3009         if (err < 0) {
3010                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3011                 goto fail;
3012         }
3013 fail:
3014         err = tegra_dsi_restore_state(dc, dsi, init_status);
3015         if (err < 0)
3016                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3017         tegra_dc_io_end(dc);
3018         mutex_unlock(&dsi->lock);
3019         return err;
3020 }
3021 EXPORT_SYMBOL(tegra_dsi_read_data);
3022
3023 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3024                                 struct tegra_dc_dsi_data *dsi)
3025 {
3026         int err = 0;
3027         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3028         struct dsi_status *init_status;
3029         static struct tegra_dsi_cmd dsi_nop_cmd =
3030                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3031
3032         tegra_dc_io_start(dc);
3033
3034         init_status = tegra_dsi_prepare_host_transmission(
3035                                         dc, dsi, DSI_LP_OP_WRITE);
3036         if (IS_ERR_OR_NULL(init_status)) {
3037                 err = PTR_ERR(init_status);
3038                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3039                 goto fail;
3040         }
3041
3042         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
3043         if (err < 0) {
3044                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3045                 goto fail;
3046         }
3047
3048         tegra_dsi_reset_read_count(dsi);
3049
3050         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3051                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3052                 if (err < 0) {
3053                         dev_err(&dc->ndev->dev,
3054                         "DSI failed to go to LP read mode\n");
3055                         goto fail;
3056                 }
3057         }
3058
3059         err = tegra_dsi_bta(dsi);
3060         if (err < 0) {
3061                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3062                 goto fail;
3063         }
3064
3065         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3066         if (err < 0) {
3067                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3068                 goto fail;
3069         }
3070
3071         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3072                 dev_warn(&dc->ndev->dev,
3073                         "Ack no error trigger message not received\n");
3074                 err = -EAGAIN;
3075         }
3076 fail:
3077         err = tegra_dsi_restore_state(dc, dsi, init_status);
3078         if (err < 0)
3079                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3080         tegra_dc_io_end(dc);
3081         return err;
3082 }
3083 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3084
3085 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3086 {
3087         u32 val;
3088         int ret = 0;
3089
3090         if (atomic_read(&dsi_syncpt_rst))
3091                 tegra_dsi_syncpt_reset(dsi);
3092
3093         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3094         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3095         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3096         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3097
3098 #if DSI_USE_SYNC_POINTS
3099         ret = tegra_dsi_syncpt(dsi);
3100         if (ret < 0) {
3101                 dev_err(&dsi->dc->ndev->dev,
3102                         "DSI syncpt for ulpm enter failed\n");
3103                 return ret;
3104         }
3105 #else
3106         /* TODO: Find exact delay required */
3107         mdelay(10);
3108 #endif
3109         dsi->ulpm = true;
3110
3111         return ret;
3112 }
3113
3114 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3115 {
3116         u32 val;
3117         int ret = 0;
3118
3119         if (atomic_read(&dsi_syncpt_rst))
3120                 tegra_dsi_syncpt_reset(dsi);
3121
3122         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3123         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3124         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3125         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3126
3127 #if DSI_USE_SYNC_POINTS
3128         ret = tegra_dsi_syncpt(dsi);
3129         if (ret < 0) {
3130                 dev_err(&dsi->dc->ndev->dev,
3131                         "DSI syncpt for ulpm exit failed\n");
3132                 return ret;
3133         }
3134 #else
3135         /* TODO: Find exact delay required */
3136         mdelay(10);
3137 #endif
3138         dsi->ulpm = false;
3139
3140         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3141         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3142         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3143         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3144
3145         return ret;
3146 }
3147
3148 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3149                                      struct tegra_dc_dsi_data *dsi,
3150                                      int no_of_frames)
3151 {
3152         int err;
3153         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3154         u8 lp_op = dsi->status.lp_op;
3155         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3156
3157         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3158                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3159                                 TEGRA_DSI_DRIVEN_BY_DC);
3160                 if (err < 0) {
3161                         dev_err(&dc->ndev->dev,
3162                                 "Switch to HS host mode failed\n");
3163                         return;
3164                 }
3165         }
3166
3167         /*
3168          * Some panels need DC frames be sent under certain
3169          * conditions. We are working on the right fix for this
3170          * requirement, while using this current fix.
3171          */
3172         tegra_dsi_start_dc_stream(dc, dsi);
3173
3174         /*
3175          * Send frames in Continuous or One-shot mode.
3176          */
3177         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3178                 while (no_of_frames--) {
3179                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3180                                         DC_CMD_STATE_CONTROL);
3181                         mdelay(frame_period);
3182                 }
3183         } else
3184                 mdelay(no_of_frames * frame_period);
3185
3186         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3187
3188         if (switch_to_lp) {
3189                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3190                 if (err < 0)
3191                         dev_err(&dc->ndev->dev,
3192                                 "DSI failed to go to LP mode\n");
3193         }
3194 }
3195
3196 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3197 {
3198         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3199         int err = 0;
3200         u32 val;
3201         u32 i;
3202
3203         mutex_lock(&dsi->lock);
3204         tegra_dc_io_start(dc);
3205         tegra_dc_dsi_hold_host(dc);
3206
3207         /* Stop DC stream before configuring DSI registers
3208          * to avoid visible glitches on panel during transition
3209          * from bootloader to kernel driver
3210          */
3211         tegra_dsi_stop_dc_stream(dc, dsi);
3212
3213         if (dsi->enabled) {
3214                 if (dsi->ulpm) {
3215                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3216                                 dev_err(&dc->ndev->dev,
3217                                         "DSI failed to exit ulpm\n");
3218                                 goto fail;
3219                         }
3220                 }
3221
3222                 if (dsi->info.panel_reset) {
3223                         /*
3224                          * Certain panels need dc frames be sent before
3225                          * waking panel.
3226                          */
3227                         if (dsi->info.panel_send_dc_frames)
3228                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3229
3230                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3231                                                         dsi->info.dsi_init_cmd,
3232                                                         dsi->info.n_init_cmd);
3233                         if (err < 0) {
3234                                 dev_err(&dc->ndev->dev,
3235                                 "dsi: error sending dsi init cmd\n");
3236                                 goto fail;
3237                         }
3238                 } else if (dsi->info.dsi_late_resume_cmd) {
3239                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3240                                                 dsi->info.dsi_late_resume_cmd,
3241                                                 dsi->info.n_late_resume_cmd);
3242                         if (err < 0) {
3243                                 dev_err(&dc->ndev->dev,
3244                                 "dsi: error sending late resume cmd\n");
3245                                 goto fail;
3246                         }
3247                 }
3248         } else {
3249                 err = tegra_dsi_init_hw(dc, dsi);
3250                 if (err < 0) {
3251                         dev_err(&dc->ndev->dev,
3252                                 "dsi: not able to init dsi hardware\n");
3253                         goto fail;
3254                 }
3255
3256                 if (dsi->ulpm) {
3257                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3258                                 dev_err(&dc->ndev->dev,
3259                                         "DSI failed to enter ulpm\n");
3260                                 goto fail;
3261                         }
3262
3263                         tegra_dsi_pad_enable(dsi);
3264
3265                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3266                                 dev_err(&dc->ndev->dev,
3267                                         "DSI failed to exit ulpm\n");
3268                                 goto fail;
3269                         }
3270                 }
3271
3272                 /*
3273                  * Certain panels need dc frames be sent before
3274                  * waking panel.
3275                  */
3276                 if (dsi->info.panel_send_dc_frames)
3277                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3278
3279                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3280                 if (err < 0) {
3281                         dev_err(&dc->ndev->dev,
3282                                 "dsi: not able to set to lp mode\n");
3283                         goto fail;
3284                 }
3285
3286                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3287                                                 dsi->info.n_init_cmd);
3288                 if (err < 0) {
3289                         dev_err(&dc->ndev->dev,
3290                                 "dsi: error while sending dsi init cmd\n");
3291                         goto fail;
3292                 }
3293
3294                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3295                                 TEGRA_DSI_DRIVEN_BY_DC);
3296                 if (err < 0) {
3297                         dev_err(&dc->ndev->dev,
3298                                 "dsi: not able to set to hs mode\n");
3299                         goto fail;
3300                 }
3301
3302                 dsi->enabled = true;
3303         }
3304
3305         if (dsi->out_ops && dsi->out_ops->enable)
3306                 dsi->out_ops->enable(dsi);
3307
3308         //enable clk to mipi_cal block
3309         val = readl(IO_ADDRESS(0x60006000 + 0x14));
3310         val |= (1<<24);
3311         writel(val, IO_ADDRESS(0x60006000 + 0x14));
3312
3313         //zero out mipi cal
3314         for (i = 0; i <= 0x60; i += 4) {
3315                 writel(0x0, IO_ADDRESS(0x700e3000 + i));
3316         }
3317
3318         //enable vclamp ref voltage
3319         writel(0x1, IO_ADDRESS(0x700e3058));
3320         writel(0x0, IO_ADDRESS(0x700e3000 + 0x60));
3321
3322         tegra_dsi_writel(dsi, 20, DSI_SOL_DELAY);
3323
3324         tegra_dsi_writel(dsi, 0x0, DSI_MAX_THRESHOLD);
3325
3326         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3327                 tegra_dsi_start_dc_stream(dc, dsi);
3328 fail:
3329         tegra_dc_dsi_release_host(dc);
3330         tegra_dc_io_end(dc);
3331         mutex_unlock(&dsi->lock);
3332 }
3333
3334 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3335 {
3336         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3337
3338         tegra_dc_dsi_debug_create(dsi);
3339
3340         if (dsi->info.dsi2lvds_bridge_enable)
3341                 dsi->out_ops = &tegra_dsi2lvds_ops;
3342         else if (dsi->info.dsi2edp_bridge_enable)
3343                 dsi->out_ops = &tegra_dsi2edp_ops;
3344         else
3345                 dsi->out_ops = NULL;
3346
3347         if (dsi->out_ops && dsi->out_ops->init)
3348                 dsi->out_ops->init(dsi);
3349
3350         tegra_dsi_init_sw(dc, dsi);
3351
3352         if (!dsi->mipi_cal)
3353                 dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
3354 }
3355
3356 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3357                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3358 {
3359         u16 i;
3360         u16 len;
3361
3362         memcpy(dst, src, sizeof(*dst) * n_cmd);
3363
3364         for (i = 0; i < n_cmd; i++)
3365                 if (src[i].pdata) {
3366                         len = sizeof(*src[i].pdata) *
3367                                         src[i].sp_len_dly.data_len;
3368                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3369                         if (!dst[i].pdata)
3370                                 goto free_cmd_pdata;
3371                         memcpy(dst[i].pdata, src[i].pdata, len);
3372                 }
3373
3374         return 0;
3375
3376 free_cmd_pdata:
3377         while (i--)
3378                 if (dst[i].pdata)
3379                         kfree(dst[i].pdata);
3380         return -ENOMEM;
3381 }
3382
3383 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3384                                         struct tegra_dsi_out *p_dsi)
3385 {
3386         struct tegra_dsi_cmd *p_init_cmd;
3387         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3388         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3389         struct tegra_dsi_cmd *p_suspend_cmd;
3390         int err;
3391
3392         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3393                 return -EINVAL;
3394
3395         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3396                                 p_dsi->n_init_cmd, GFP_KERNEL);
3397         if (!p_init_cmd)
3398                 return -ENOMEM;
3399
3400         if (p_dsi->dsi_early_suspend_cmd) {
3401                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3402                                         p_dsi->n_early_suspend_cmd,
3403                                         GFP_KERNEL);
3404                 if (!p_early_suspend_cmd) {
3405                         err = -ENOMEM;
3406                         goto err_free_init_cmd;
3407                 }
3408         }
3409
3410         if (p_dsi->dsi_late_resume_cmd) {
3411                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3412                                         p_dsi->n_late_resume_cmd,
3413                                         GFP_KERNEL);
3414                 if (!p_late_resume_cmd) {
3415                         err = -ENOMEM;
3416                         goto err_free_p_early_suspend_cmd;
3417                 }
3418         }
3419
3420         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3421                                 GFP_KERNEL);
3422         if (!p_suspend_cmd) {
3423                 err = -ENOMEM;
3424                 goto err_free_p_late_resume_cmd;
3425         }
3426
3427         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3428
3429         /* Copy panel init cmd */
3430         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3431                                                 p_init_cmd, p_dsi->n_init_cmd);
3432         if (err < 0)
3433                 goto err_free;
3434         dsi->info.dsi_init_cmd = p_init_cmd;
3435
3436         /* Copy panel early suspend cmd */
3437         if (p_dsi->dsi_early_suspend_cmd) {
3438                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3439                                         p_early_suspend_cmd,
3440                                         p_dsi->n_early_suspend_cmd);
3441                 if (err < 0)
3442                         goto err_free;
3443                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3444         }
3445
3446         /* Copy panel late resume cmd */
3447         if (p_dsi->dsi_late_resume_cmd) {
3448                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3449                                                 p_late_resume_cmd,
3450                                                 p_dsi->n_late_resume_cmd);
3451                 if (err < 0)
3452                         goto err_free;
3453                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3454         }
3455
3456         /* Copy panel suspend cmd */
3457         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3458                                         p_dsi->n_suspend_cmd);
3459         if (err < 0)
3460                 goto err_free;
3461         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3462
3463         if (!dsi->info.panel_reset_timeout_msec)
3464                 dsi->info.panel_reset_timeout_msec =
3465                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3466
3467         if (!dsi->info.panel_buffer_size_byte)
3468                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3469
3470         if (!dsi->info.max_panel_freq_khz) {
3471                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3472
3473                 if (dsi->info.video_burst_mode >
3474                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3475                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3476                                         "is not set for DSI burst mode.\n");
3477                         dsi->info.video_burst_mode =
3478                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3479                 }
3480         }
3481
3482         if (!dsi->info.lp_cmd_mode_freq_khz)
3483                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3484
3485         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3486                 dev_warn(&dsi->dc->ndev->dev,
3487                         "DSI: Failed to get chip info\n");
3488
3489         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3490                 dsi->info.lp_read_cmd_mode_freq_khz =
3491                         dsi->info.lp_cmd_mode_freq_khz;
3492
3493         /* host mode is for testing only */
3494         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3495         return 0;
3496
3497 err_free:
3498         kfree(p_suspend_cmd);
3499 err_free_p_late_resume_cmd:
3500         kfree(p_late_resume_cmd);
3501 err_free_p_early_suspend_cmd:
3502         kfree(p_early_suspend_cmd);
3503 err_free_init_cmd:
3504         kfree(p_init_cmd);
3505         return err;
3506 }
3507
3508 /* returns next null enumeration from  tegra_dsi_instance */
3509 static inline int tegra_dsi_get_enumeration(void)
3510 {
3511         int i = 0;
3512         for (; i < MAX_DSI_INSTANCE; i++) {
3513                 if (!tegra_dsi_instance[i])
3514                         return i;
3515         }
3516         return -EINVAL;
3517 }
3518
3519 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3520 {
3521         struct tegra_dc_dsi_data *dsi;
3522         struct resource *res;
3523         struct resource *base_res;
3524         void __iomem *base;
3525         struct clk *dc_clk = NULL;
3526         struct clk *dsi_clk = NULL;
3527         struct clk *dsi_fixed_clk = NULL;
3528         struct tegra_dsi_out *dsi_pdata;
3529         int err = 0;
3530         int dsi_enum = -1;
3531
3532         if (dc->pdata->default_out->dsi->dsi_instance)
3533                 dsi_enum = 1;
3534         else
3535                 dsi_enum = tegra_dsi_get_enumeration();
3536         if (dsi_enum < 0) {
3537                 err = -EINVAL;
3538                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3539                 return err;
3540         }
3541
3542         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3543         if (!dsi) {
3544                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3545                 return -ENOMEM;
3546         }
3547         tegra_dsi_instance[dsi_enum] = dsi;
3548
3549         if (dc->out->dsi->ganged_type) {
3550                 if (dsi_enum)
3551                         res = nvhost_get_resource_byname(dc->ndev,
3552                                                 IORESOURCE_MEM,
3553                                                 "ganged_dsib_regs");
3554                 else
3555                         res = nvhost_get_resource_byname(dc->ndev,
3556                                                 IORESOURCE_MEM,
3557                                                 "ganged_dsia_regs");
3558         } else {
3559                 res = nvhost_get_resource_byname(dc->ndev,
3560                                         IORESOURCE_MEM,
3561                                         "dsi_regs");
3562         }
3563
3564         if (!res) {
3565                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3566                 err = -ENOENT;
3567                 goto err_free_dsi;
3568         }
3569
3570         base_res = request_mem_region(res->start, resource_size(res),
3571                                 dc->ndev->name);
3572         if (!base_res) {
3573                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3574                 err = -EBUSY;
3575                 goto err_free_dsi;
3576         }
3577
3578         base = ioremap(res->start, resource_size(res));
3579         if (!base) {
3580                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3581                 err = -EBUSY;
3582                 goto err_release_regs;
3583         }
3584
3585         dsi_pdata = dc->pdata->default_out->dsi;
3586         if (!dsi_pdata) {
3587                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3588                 goto err_release_regs;
3589         }
3590
3591         if (dsi_enum)
3592                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3593         else
3594                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3595
3596         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3597
3598         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3599                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3600                 err = -EBUSY;
3601                 goto err_release_regs;
3602         }
3603
3604         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3605         if (IS_ERR_OR_NULL(dc_clk)) {
3606                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3607                         dev_name(&dc->ndev->dev));
3608                 err = -EBUSY;
3609                 goto err_clk_put;
3610         }
3611
3612         mutex_init(&dsi->lock);
3613         dsi->controller_index = dsi_enum;
3614         dsi->dc = dc;
3615         dsi->base = base;
3616         dsi->base_res = base_res;
3617         dsi->dc_clk = dc_clk;
3618         dsi->dsi_clk = dsi_clk;
3619         dsi->dsi_fixed_clk = dsi_fixed_clk;
3620
3621         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3622         if (err < 0)
3623                 goto err_dsi_data;
3624
3625         tegra_dc_set_outdata(dc, dsi);
3626         __tegra_dc_dsi_init(dc);
3627
3628         return 0;
3629
3630 err_dsi_data:
3631 err_clk_put:
3632         clk_put(dsi_clk);
3633         clk_put(dsi_fixed_clk);
3634 err_release_regs:
3635         release_resource(base_res);
3636 err_free_dsi:
3637         kfree(dsi);
3638
3639         return err;
3640 }
3641
3642 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3643 {
3644         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3645         u16 i;
3646         u32 val;
3647
3648         mutex_lock(&dsi->lock);
3649
3650         if (dsi->out_ops && dsi->out_ops->destroy)
3651                 dsi->out_ops->destroy(dsi);
3652
3653         /* free up the pdata */
3654         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3655                 if (dsi->info.dsi_init_cmd[i].pdata)
3656                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3657         }
3658         kfree(dsi->info.dsi_init_cmd);
3659
3660         /* Disable dc stream */
3661         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3662                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3663
3664         /* Disable dsi phy clock */
3665         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3666                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3667
3668         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3669         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3670
3671         iounmap(dsi->base);
3672         release_resource(dsi->base_res);
3673
3674         clk_put(dsi->dc_clk);
3675         clk_put(dsi->dsi_clk);
3676
3677         mutex_unlock(&dsi->lock);
3678
3679         mutex_destroy(&dsi->lock);
3680         kfree(dsi);
3681 }
3682
3683 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3684                                                         u32 settings)
3685 {
3686         struct clk *parent_clk = NULL;
3687         struct clk *base_clk = NULL;
3688
3689         /* Disable dsi fast and slow clock */
3690         parent_clk = clk_get_parent(dsi->dsi_clk);
3691         base_clk = clk_get_parent(parent_clk);
3692         if (dsi->info.dsi_instance)
3693                 tegra_clk_cfg_ex(base_clk,
3694                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3695                                 settings);
3696         else
3697                 tegra_clk_cfg_ex(base_clk,
3698                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3699                                 settings);
3700 }
3701
3702 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
3703                                 struct tegra_dc_dsi_data *dsi, u32 suspend_aggr)
3704 {
3705         int val = 0;
3706         int err = 0;
3707
3708         if (!dsi->enabled) {
3709                 err = -EPERM;
3710                 goto fail;
3711         }
3712
3713         switch (suspend_aggr) {
3714         case DSI_SUSPEND_FULL:
3715                 /* Suspend DSI panel */
3716                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3717                 if (err < 0) {
3718                         dev_err(&dc->ndev->dev,
3719                         "DSI failed to go to LP mode\n");
3720                         goto fail;
3721                 }
3722
3723                 err = tegra_dsi_send_panel_cmd(dc, dsi,
3724                                 dsi->info.dsi_suspend_cmd,
3725                                 dsi->info.n_suspend_cmd);
3726                 /*
3727                  * Certain panels need dc frames be sent after
3728                  * putting panel to sleep.
3729                  */
3730                 if (dsi->info.panel_send_dc_frames)
3731                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3732
3733                 if (err < 0) {
3734                         dev_err(&dc->ndev->dev,
3735                                 "dsi: Error sending suspend cmd\n");
3736                         goto fail;
3737                 }
3738         case DSI_HOST_SUSPEND_LV2:
3739                 /* Set DSI to ULPM and suspend pads. DSI will be set to the
3740                  * lowest power state in this level. */
3741                 if (!dsi->ulpm) {
3742                         err = tegra_dsi_enter_ulpm(dsi);
3743                         if (err < 0) {
3744                                 dev_err(&dc->ndev->dev,
3745                                         "DSI failed to enter ulpm\n");
3746                                 goto fail;
3747                         }
3748                 }
3749
3750                 val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3751                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3752                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
3753                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3754
3755                 /* Suspend core-logic */
3756                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3757                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3758         case DSI_HOST_SUSPEND_LV1:
3759                 /* Disable dsi fast and slow clock */
3760                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3761         case DSI_HOST_SUSPEND_LV0:
3762                 /* Disable dsi source clock */
3763                 tegra_dsi_clk_disable(dsi);
3764                 break;
3765         case DSI_NO_SUSPEND:
3766                 break;
3767         default:
3768                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3769                                                 "is not supported.\n");
3770         }
3771
3772         dsi->enabled = false;
3773
3774         return 0;
3775 fail:
3776         return err;
3777 }
3778
3779 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3780 {
3781         int err = 0;
3782         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3783
3784         if (dsi->host_suspended)
3785                 return 0;
3786
3787         BUG_ON(!tegra_is_clk_enabled(dc->clk));
3788         tegra_dc_io_start(dc);
3789         dsi->host_suspended = true;
3790
3791         tegra_dsi_stop_dc_stream(dc, dsi);
3792
3793         err = tegra_dsi_deep_sleep(dc, dsi, dsi->info.suspend_aggr);
3794         if (err < 0)
3795                 dev_err(&dc->ndev->dev,
3796                         "DSI failed to enter deep sleep\n");
3797
3798         tegra_dc_clk_disable(dc);
3799
3800         tegra_dc_io_end(dc);
3801         return err;
3802 }
3803
3804 static int tegra_dsi_host_resume(struct tegra_dc *dc)
3805 {
3806         int val = 0;
3807         int err = 0;
3808         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3809
3810         mutex_lock(&dsi->host_resume_lock);
3811         cancel_delayed_work_sync(&dsi->idle_work);
3812         if (!dsi->host_suspended) {
3813                 mutex_unlock(&dsi->host_resume_lock);
3814                 return 0;
3815         }
3816
3817         tegra_dc_clk_enable(dc);
3818         switch (dsi->info.suspend_aggr) {
3819         case DSI_HOST_SUSPEND_LV0:
3820                 tegra_dsi_clk_enable(dsi);
3821                 break;
3822         case DSI_HOST_SUSPEND_LV1:
3823                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3824                 tegra_dsi_clk_enable(dsi);
3825                 break;
3826         case DSI_HOST_SUSPEND_LV2:
3827                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3828                 tegra_dsi_clk_enable(dsi);
3829
3830                 tegra_dsi_writel(dsi,
3831                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3832                         DSI_POWER_CONTROL);
3833
3834                 if (dsi->ulpm) {
3835                         err = tegra_dsi_enter_ulpm(dsi);
3836                         if (err < 0) {
3837                                 dev_err(&dc->ndev->dev,
3838                                         "DSI failed to enter ulpm\n");
3839                                 goto fail;
3840                         }
3841
3842                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3843                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3844                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3845                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3846                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3847
3848                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3849                                 dev_err(&dc->ndev->dev,
3850                                         "DSI failed to exit ulpm\n");
3851                                 goto fail;
3852                         }
3853                 }
3854                 break;
3855         case DSI_NO_SUSPEND:
3856                 break;
3857         default:
3858                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3859                                                 "is not supported.\n");
3860         }
3861
3862         tegra_dsi_start_dc_stream(dc, dsi);
3863
3864         dsi->enabled = true;
3865         dsi->host_suspended = false;
3866         mutex_unlock(&dsi->host_resume_lock);
3867 fail:
3868         return err;
3869 }
3870
3871 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
3872 {
3873         int err;
3874         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3875
3876         mutex_lock(&dsi->lock);
3877         tegra_dc_io_start(dc);
3878
3879         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3880                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3881
3882         if (dsi->out_ops && dsi->out_ops->disable)
3883                 dsi->out_ops->disable(dsi);
3884
3885         if (dsi->info.power_saving_suspend) {
3886                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3887                         dev_err(&dc->ndev->dev,
3888                                 "DSI failed to enter deep sleep\n");
3889                         goto fail;
3890                 }
3891         } else {
3892                 if (dsi->info.dsi_early_suspend_cmd) {
3893                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3894                                 dsi->info.dsi_early_suspend_cmd,
3895                                 dsi->info.n_early_suspend_cmd);
3896                         if (err < 0) {
3897                                 dev_err(&dc->ndev->dev,
3898                                 "dsi: Error sending early suspend cmd\n");
3899                                 goto fail;
3900                         }
3901                 }
3902
3903                 if (!dsi->ulpm) {
3904                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3905                                 dev_err(&dc->ndev->dev,
3906                                         "DSI failed to enter ulpm\n");
3907                                 goto fail;
3908                         }
3909                 }
3910         }
3911 fail:
3912         mutex_unlock(&dsi->lock);
3913         tegra_dc_io_end(dc);
3914 }
3915
3916 #ifdef CONFIG_PM
3917 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
3918 {
3919         struct tegra_dc_dsi_data *dsi;
3920
3921         dsi = tegra_dc_get_outdata(dc);
3922
3923         if (!dsi->enabled)
3924                 return;
3925
3926         tegra_dc_io_start(dc);
3927         mutex_lock(&dsi->lock);
3928
3929         if (dsi->out_ops && dsi->out_ops->suspend)
3930                 dsi->out_ops->suspend(dsi);
3931
3932         if (!dsi->info.power_saving_suspend) {
3933                 if (dsi->ulpm) {
3934                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3935                                 dev_err(&dc->ndev->dev,
3936                                         "DSI failed to exit ulpm");
3937                                 goto fail;
3938                         }
3939                 }
3940
3941                 if (tegra_dsi_deep_sleep(dc, dsi, DSI_SUSPEND_FULL) < 0) {
3942                         dev_err(&dc->ndev->dev,
3943                                 "DSI failed to enter deep sleep\n");
3944                         goto fail;
3945                 }
3946         }
3947 fail:
3948         mutex_unlock(&dsi->lock);
3949         tegra_dc_io_end(dc);
3950 }
3951
3952 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
3953 {
3954         struct tegra_dc_dsi_data *dsi;
3955
3956         dsi = tegra_dc_get_outdata(dc);
3957
3958         /* No dsi config required since tegra_dc_dsi_enable
3959          * will reconfigure the controller from scratch
3960          */
3961
3962          if (dsi->out_ops && dsi->out_ops->resume)
3963                 dsi->out_ops->resume(dsi);
3964 }
3965
3966 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
3967 {
3968         _tegra_dc_dsi_suspend(dc);
3969
3970         if (dc->out->dsi->ganged_type) {
3971                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3972                 _tegra_dc_dsi_suspend(dc);
3973                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3974         }
3975 }
3976
3977 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
3978 {
3979         _tegra_dc_dsi_resume(dc);
3980
3981         if (dc->out->dsi->ganged_type) {
3982                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
3983                 _tegra_dc_dsi_resume(dc);
3984                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
3985         }
3986 }
3987 #endif
3988
3989 static int tegra_dc_dsi_init(struct tegra_dc *dc)
3990 {
3991         int err = 0;
3992
3993         err = _tegra_dc_dsi_init(dc);
3994         if (err < 0) {
3995                 dev_err(&dc->ndev->dev,
3996                         "dsi: Instance A init failed\n");
3997                 goto fail;
3998         }
3999
4000         if (dc->out->dsi->ganged_type) {
4001                 err = _tegra_dc_dsi_init(dc);
4002                 if (err < 0) {
4003                         dev_err(&dc->ndev->dev,
4004                                 "dsi: Instance B init failed\n");
4005                         goto fail;
4006                 }
4007                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4008         }
4009 fail:
4010         return err;
4011 }
4012
4013 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4014 {
4015         _tegra_dc_dsi_destroy(dc);
4016
4017         if (dc->out->dsi->ganged_type) {
4018                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4019                 _tegra_dc_dsi_destroy(dc);
4020                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4021         }
4022 }
4023
4024 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4025 {
4026         _tegra_dc_dsi_enable(dc);
4027
4028         if (dc->out->dsi->ganged_type) {
4029                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4030                 _tegra_dc_dsi_enable(dc);
4031                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4032         }
4033 }
4034
4035 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4036         .init = tegra_dc_dsi_init,
4037         .destroy = tegra_dc_dsi_destroy,
4038         .enable = tegra_dc_dsi_enable,
4039         .disable = tegra_dc_dsi_disable,
4040         .hold = tegra_dc_dsi_hold_host,
4041         .release = tegra_dc_dsi_release_host,
4042 #ifdef CONFIG_PM
4043         .suspend = tegra_dc_dsi_suspend,
4044         .resume = tegra_dc_dsi_resume,
4045 #endif
4046 };