video: tegra: dsi: Enable MIPI auto calibration
[linux-3.10.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32 #include <linux/lcm.h>
33 #include <linux/regulator/consumer.h>
34
35 #include <mach/clk.h>
36 #include <mach/dc.h>
37 #include <mach/fb.h>
38 #include <mach/csi.h>
39 #include <linux/nvhost.h>
40
41 #include "dc_reg.h"
42 #include "dc_priv.h"
43 #include "dev.h"
44 #include "dsi_regs.h"
45 #include "dsi.h"
46 #include "mipi_cal.h"
47
48 /* HACK! This needs to come from DT */
49 #include "../../../../arch/arm/mach-tegra/iomap.h"
50
51 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
52 #define DSIB_MODE_ENABLE                0x2
53
54 #define DSI_USE_SYNC_POINTS             0
55 #define S_TO_MS(x)                      (1000 * (x))
56 #define MS_TO_US(x)                     (1000 * (x))
57
58 #define DSI_MODULE_NOT_INIT             0x0
59 #define DSI_MODULE_INIT                 0x1
60
61 #define DSI_LPHS_NOT_INIT               0x0
62 #define DSI_LPHS_IN_LP_MODE             0x1
63 #define DSI_LPHS_IN_HS_MODE             0x2
64
65 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
66 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
67 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
68
69 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
70 #define DSI_DRIVEN_MODE_DC              0x1
71 #define DSI_DRIVEN_MODE_HOST            0x2
72
73 #define DSI_PHYCLK_OUT_DIS              0x0
74 #define DSI_PHYCLK_OUT_EN               0x1
75
76 #define DSI_PHYCLK_NOT_INIT             0x0
77 #define DSI_PHYCLK_CONTINUOUS           0x1
78 #define DSI_PHYCLK_TX_ONLY              0x2
79
80 #define DSI_CLK_BURST_NOT_INIT          0x0
81 #define DSI_CLK_BURST_NONE_BURST        0x1
82 #define DSI_CLK_BURST_BURST_MODE        0x2
83
84 #define DSI_DC_STREAM_DISABLE           0x0
85 #define DSI_DC_STREAM_ENABLE            0x1
86
87 #define DSI_LP_OP_NOT_INIT              0x0
88 #define DSI_LP_OP_WRITE                 0x1
89 #define DSI_LP_OP_READ                  0x2
90
91 #define DSI_HOST_IDLE_PERIOD            1000
92 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
93
94 static bool enable_read_debug;
95 module_param(enable_read_debug, bool, 0644);
96 MODULE_PARM_DESC(enable_read_debug,
97                 "Enable to print read fifo and return packet type");
98
99 /* source of video data */
100 enum {
101         TEGRA_DSI_DRIVEN_BY_DC,
102         TEGRA_DSI_DRIVEN_BY_HOST,
103 };
104
105 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
106
107 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
108         DSI_PKT_SEQ_0_LO,
109         DSI_PKT_SEQ_0_HI,
110         DSI_PKT_SEQ_1_LO,
111         DSI_PKT_SEQ_1_HI,
112         DSI_PKT_SEQ_2_LO,
113         DSI_PKT_SEQ_2_HI,
114         DSI_PKT_SEQ_3_LO,
115         DSI_PKT_SEQ_3_HI,
116         DSI_PKT_SEQ_4_LO,
117         DSI_PKT_SEQ_4_HI,
118         DSI_PKT_SEQ_5_LO,
119         DSI_PKT_SEQ_5_HI,
120 };
121
122 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
123         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
124         0,
125         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
126         0,
127         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
128         0,
129         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
130         PKT_ID2(CMD_HE) | PKT_LEN2(0),
131         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
132         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
133         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
134         0,
135         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
136         PKT_ID2(CMD_HE) | PKT_LEN2(0),
137         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
138         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
139 };
140
141 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
142         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
143         0,
144         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
145         0,
146         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
147         0,
148         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
149         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
150         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
151         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
152         0,
153         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
154         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
155         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
156 };
157
158 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
159         PKT_ID0(CMD_VS) | PKT_LEN0(0),
160         0,
161         PKT_ID0(CMD_HS) | PKT_LEN0(0),
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0),
164         0,
165         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
166         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
167         0,
168         PKT_ID0(CMD_HS) | PKT_LEN0(0),
169         0,
170         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
171         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
172         0,
173 };
174
175 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
176         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
179         0,
180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
181         0,
182         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
183         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
184         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
185         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
186         0,
187         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
188         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
189         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
190 };
191
192 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
193         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
194         0,
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
196         0,
197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
198         0,
199         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
200         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
201         0,
202         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
203         0,
204         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
205         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
206         0,
207 };
208
209 /* TODO: verify with hw about this format */
210 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
211         0,
212         0,
213         0,
214         0,
215         0,
216         0,
217         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
218         0,
219         0,
220         0,
221         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
222         0,
223 };
224
225 const u32 init_reg[] = {
226         DSI_INT_ENABLE,
227         DSI_INT_STATUS,
228         DSI_INT_MASK,
229         DSI_INIT_SEQ_DATA_0,
230         DSI_INIT_SEQ_DATA_1,
231         DSI_INIT_SEQ_DATA_2,
232         DSI_INIT_SEQ_DATA_3,
233         DSI_INIT_SEQ_DATA_4,
234         DSI_INIT_SEQ_DATA_5,
235         DSI_INIT_SEQ_DATA_6,
236         DSI_INIT_SEQ_DATA_7,
237         DSI_DCS_CMDS,
238         DSI_PKT_SEQ_0_LO,
239         DSI_PKT_SEQ_1_LO,
240         DSI_PKT_SEQ_2_LO,
241         DSI_PKT_SEQ_3_LO,
242         DSI_PKT_SEQ_4_LO,
243         DSI_PKT_SEQ_5_LO,
244         DSI_PKT_SEQ_0_HI,
245         DSI_PKT_SEQ_1_HI,
246         DSI_PKT_SEQ_2_HI,
247         DSI_PKT_SEQ_3_HI,
248         DSI_PKT_SEQ_4_HI,
249         DSI_PKT_SEQ_5_HI,
250         DSI_CONTROL,
251         DSI_HOST_DSI_CONTROL,
252         DSI_PAD_CONTROL,
253         DSI_PAD_CONTROL_CD,
254         DSI_SOL_DELAY,
255         DSI_MAX_THRESHOLD,
256         DSI_TRIGGER,
257         DSI_TX_CRC,
258         DSI_INIT_SEQ_CONTROL,
259         DSI_PKT_LEN_0_1,
260         DSI_PKT_LEN_2_3,
261         DSI_PKT_LEN_4_5,
262         DSI_PKT_LEN_6_7,
263 };
264
265 const u32 init_reg_vs1_ext[] = {
266         DSI_PAD_CONTROL_0_VS1,
267         DSI_PAD_CONTROL_CD_VS1,
268         DSI_PAD_CD_STATUS_VS1,
269         DSI_PAD_CONTROL_1_VS1,
270         DSI_PAD_CONTROL_2_VS1,
271         DSI_PAD_CONTROL_3_VS1,
272         DSI_PAD_CONTROL_4_VS1,
273         DSI_GANGED_MODE_CONTROL,
274         DSI_GANGED_MODE_START,
275         DSI_GANGED_MODE_SIZE,
276 };
277
278 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
279 static int tegra_dsi_host_resume(struct tegra_dc *dc);
280 static void tegra_dc_dsi_idle_work(struct work_struct *work);
281 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
282                                      struct tegra_dc_dsi_data *dsi,
283                                      int no_of_frames);
284
285 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
286 {
287         unsigned long ret;
288
289         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
290         ret = readl(dsi->base + reg * 4);
291         trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
292         return ret;
293 }
294 EXPORT_SYMBOL(tegra_dsi_readl);
295
296 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
297 {
298         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
299         trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
300         writel(val, dsi->base + reg * 4);
301 }
302 EXPORT_SYMBOL(tegra_dsi_writel);
303
304 #ifdef CONFIG_DEBUG_FS
305 static int dbg_dsi_show(struct seq_file *s, void *unused)
306 {
307         struct tegra_dc_dsi_data *dsi = s->private;
308
309 #define DUMP_REG(a) do {                                                \
310                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
311                        #a, a, tegra_dsi_readl(dsi, a));         \
312         } while (0)
313
314         tegra_dc_io_start(dsi->dc);
315         clk_prepare_enable(dsi->dsi_clk);
316
317         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
318         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
319         DUMP_REG(DSI_CTXSW);
320         DUMP_REG(DSI_POWER_CONTROL);
321         DUMP_REG(DSI_INT_ENABLE);
322         DUMP_REG(DSI_HOST_DSI_CONTROL);
323         DUMP_REG(DSI_CONTROL);
324         DUMP_REG(DSI_SOL_DELAY);
325         DUMP_REG(DSI_MAX_THRESHOLD);
326         DUMP_REG(DSI_TRIGGER);
327         DUMP_REG(DSI_TX_CRC);
328         DUMP_REG(DSI_STATUS);
329         DUMP_REG(DSI_INIT_SEQ_CONTROL);
330         DUMP_REG(DSI_INIT_SEQ_DATA_0);
331         DUMP_REG(DSI_INIT_SEQ_DATA_1);
332         DUMP_REG(DSI_INIT_SEQ_DATA_2);
333         DUMP_REG(DSI_INIT_SEQ_DATA_3);
334         DUMP_REG(DSI_INIT_SEQ_DATA_4);
335         DUMP_REG(DSI_INIT_SEQ_DATA_5);
336         DUMP_REG(DSI_INIT_SEQ_DATA_6);
337         DUMP_REG(DSI_INIT_SEQ_DATA_7);
338         DUMP_REG(DSI_PKT_SEQ_0_LO);
339         DUMP_REG(DSI_PKT_SEQ_0_HI);
340         DUMP_REG(DSI_PKT_SEQ_1_LO);
341         DUMP_REG(DSI_PKT_SEQ_1_HI);
342         DUMP_REG(DSI_PKT_SEQ_2_LO);
343         DUMP_REG(DSI_PKT_SEQ_2_HI);
344         DUMP_REG(DSI_PKT_SEQ_3_LO);
345         DUMP_REG(DSI_PKT_SEQ_3_HI);
346         DUMP_REG(DSI_PKT_SEQ_4_LO);
347         DUMP_REG(DSI_PKT_SEQ_4_HI);
348         DUMP_REG(DSI_PKT_SEQ_5_LO);
349         DUMP_REG(DSI_PKT_SEQ_5_HI);
350         DUMP_REG(DSI_DCS_CMDS);
351         DUMP_REG(DSI_PKT_LEN_0_1);
352         DUMP_REG(DSI_PKT_LEN_2_3);
353         DUMP_REG(DSI_PKT_LEN_4_5);
354         DUMP_REG(DSI_PKT_LEN_6_7);
355         DUMP_REG(DSI_PHY_TIMING_0);
356         DUMP_REG(DSI_PHY_TIMING_1);
357         DUMP_REG(DSI_PHY_TIMING_2);
358         DUMP_REG(DSI_BTA_TIMING);
359         DUMP_REG(DSI_TIMEOUT_0);
360         DUMP_REG(DSI_TIMEOUT_1);
361         DUMP_REG(DSI_TO_TALLY);
362         DUMP_REG(DSI_PAD_CONTROL);
363         DUMP_REG(DSI_PAD_CONTROL_CD);
364         DUMP_REG(DSI_PAD_CD_STATUS);
365         DUMP_REG(DSI_VID_MODE_CONTROL);
366 #undef DUMP_REG
367
368         clk_disable_unprepare(dsi->dsi_clk);
369         tegra_dc_io_end(dsi->dc);
370
371         return 0;
372 }
373
374 static int dbg_dsi_open(struct inode *inode, struct file *file)
375 {
376         return single_open(file, dbg_dsi_show, inode->i_private);
377 }
378
379 static const struct file_operations dbg_fops = {
380         .open           = dbg_dsi_open,
381         .read           = seq_read,
382         .llseek         = seq_lseek,
383         .release        = single_release,
384 };
385
386 static struct dentry *dsidir;
387
388 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
389 {
390         struct dentry *retval;
391
392         dsidir = debugfs_create_dir("tegra_dsi", NULL);
393         if (!dsidir)
394                 return;
395         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
396                 &dbg_fops);
397         if (!retval)
398                 goto free_out;
399         return;
400 free_out:
401         debugfs_remove_recursive(dsidir);
402         dsidir = NULL;
403         return;
404 }
405 #else
406 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
407 { }
408 #endif
409
410 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
411 {
412         if (!tegra_is_clk_enabled(dsi->dsi_clk))
413                 clk_prepare_enable(dsi->dsi_clk);
414 }
415
416 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
417 {
418         if (tegra_is_clk_enabled(dsi->dsi_clk))
419                 clk_disable_unprepare(dsi->dsi_clk);
420 }
421
422 static void __maybe_unused tegra_dsi_syncpt_reset(
423                                 struct tegra_dc_dsi_data *dsi)
424 {
425         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
426         /* stabilization delay */
427         udelay(300);
428         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
429         /* stabilization delay */
430         udelay(300);
431 }
432
433 static int __maybe_unused tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
434 {
435         u32 val;
436         int ret = 0;
437
438         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
439
440         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
441                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
442         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
443
444         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
445                 dsi->syncpt_val + 1, MAX_SCHEDULE_TIMEOUT, NULL, NULL);
446         if (ret < 0) {
447                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
448                 goto fail;
449         }
450
451         (dsi->syncpt_val)++;
452         return 0;
453 fail:
454         return ret;
455 }
456
457 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
458 {
459         u32 dsi_clock_rate_khz;
460
461         switch (dsi->info.video_burst_mode) {
462         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
463         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
464         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
465         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
466                 /* Calculate DSI HS clock rate for DSI burst mode */
467                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
468                                         dsi->shift_clk_div.mul /
469                                         dsi->shift_clk_div.div;
470                 break;
471         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
472         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
473         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
474         default:
475                 /* Clock rate is default DSI clock rate for non-burst mode */
476                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
477                 break;
478         }
479
480         return dsi_clock_rate_khz;
481 }
482
483 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
484 {
485         u32 dsi_clock_rate_khz;
486
487         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
488                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
489                         dsi_clock_rate_khz =
490                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
491                 else
492                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
493         else
494                 if (lp_op == DSI_LP_OP_READ)
495                         dsi_clock_rate_khz =
496                                 dsi->info.lp_read_cmd_mode_freq_khz;
497                 else
498                         dsi_clock_rate_khz =
499                                 dsi->info.lp_cmd_mode_freq_khz;
500
501         return dsi_clock_rate_khz;
502 }
503
504 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
505                                                 struct tegra_dc_dsi_data *dsi)
506 {
507         struct tegra_dc_shift_clk_div shift_clk_div;
508         struct tegra_dc_shift_clk_div max_shift_clk_div;
509         u32 temp_lcm;
510         u32 burst_width;
511         u32 burst_width_max;
512
513         /* Get the real value of default shift_clk_div. default_shift_clk_div
514          * holds the real value of shift_clk_div.
515          */
516         shift_clk_div = dsi->default_shift_clk_div;
517
518         /* Calculate shift_clk_div which can match the video_burst_mode. */
519         if (dsi->info.video_burst_mode >=
520                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
521                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz) {
522                         /* formula:
523                          * dsi->info.max_panel_freq_khz * shift_clk_div /
524                          * dsi->default_hs_clk_khz
525                          */
526                         max_shift_clk_div.mul = dsi->info.max_panel_freq_khz *
527                                                 shift_clk_div.mul;
528                         max_shift_clk_div.div = dsi->default_hs_clk_khz *
529                                                 dsi->default_shift_clk_div.div;
530                 } else {
531                         max_shift_clk_div = shift_clk_div;
532                 }
533
534                 burst_width = dsi->info.video_burst_mode
535                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
536                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
537                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
538
539                 /* formula:
540                  * (max_shift_clk_div - shift_clk_div) *
541                  * burst_width / burst_width_max
542                  */
543                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
544                 shift_clk_div.mul = (max_shift_clk_div.mul * temp_lcm /
545                                         max_shift_clk_div.div -
546                                         shift_clk_div.mul * temp_lcm /
547                                         shift_clk_div.div)*
548                                         burst_width;
549                 shift_clk_div.div = temp_lcm * burst_width_max;
550         }
551
552         return shift_clk_div;
553 }
554
555 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
556                                         struct tegra_dc_dsi_data *dsi)
557 {
558         u32 h_width_pixels;
559         u32 h_act_corr = 0;
560         u32 hfp_corr = 0;
561         u32 temp = 0;
562
563         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
564                         dc->mode.h_sync_width + dc->mode.h_active;
565
566         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
567                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
568                 if (temp) {
569                         h_act_corr = dsi->info.n_data_lanes - temp;
570                         h_width_pixels += h_act_corr;
571                 }
572         }
573
574         temp = h_width_pixels % dsi->info.n_data_lanes;
575         if (temp) {
576                 hfp_corr = dsi->info.n_data_lanes - temp;
577                 h_width_pixels += hfp_corr;
578         }
579
580         while (1) {
581                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
582                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
583                 if (temp) {
584                         hfp_corr += dsi->info.n_data_lanes;
585                         h_width_pixels += dsi->info.n_data_lanes;
586                 }
587                 else
588                         break;
589         }
590
591         dc->mode.h_front_porch += hfp_corr;
592         dc->mode.h_active += h_act_corr;
593 }
594
595 static void tegra_dsi_init_sw(struct tegra_dc *dc,
596                         struct tegra_dc_dsi_data *dsi)
597 {
598         u32 h_width_pixels;
599         u32 v_width_lines;
600         u32 pixel_clk_hz;
601         u32 byte_clk_hz;
602         u32 plld_clk_mhz;
603         u8 n_data_lanes;
604
605         switch (dsi->info.pixel_format) {
606         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
607                 /* 2 bytes per pixel */
608                 dsi->pixel_scaler_mul = 2;
609                 dsi->pixel_scaler_div = 1;
610                 break;
611         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
612                 /* 2.25 bytes per pixel */
613                 dsi->pixel_scaler_mul = 9;
614                 dsi->pixel_scaler_div = 4;
615                 break;
616         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
617         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
618                 /* 3 bytes per pixel */
619                 dsi->pixel_scaler_mul = 3;
620                 dsi->pixel_scaler_div = 1;
621                 break;
622         default:
623                 break;
624         }
625
626         dsi->ulpm = false;
627         dsi->enabled = false;
628         dsi->clk_ref = false;
629
630         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
631                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
632                 n_data_lanes = dsi->info.n_data_lanes / 2;
633
634         dsi->dsi_control_val =
635                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
636                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
637                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
638                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
639
640         if (dsi->info.ganged_type)
641                 tegra_dsi_pix_correction(dc, dsi);
642
643         /* Below we are going to calculate dsi and dc clock rate.
644          * Calcuate the horizontal and vertical width.
645          */
646         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
647                         dc->mode.h_sync_width + dc->mode.h_active;
648
649         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
650                         dc->mode.v_sync_width + dc->mode.v_active;
651
652         /* Calculate minimum required pixel rate. */
653         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
654         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
655                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
656                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
657                                 "should be larger than rated refresh rate.\n");
658                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
659                                                 dsi->info.rated_refresh_rate;
660         }
661
662         /* Calculate minimum byte rate on DSI interface. */
663         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
664                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
665
666         /* Round up to multiple of mega hz. */
667         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
668                                                                 1000000);
669
670         /* Calculate default real shift_clk_div. */
671         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
672                                         dsi->pixel_scaler_mul;
673         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
674                                         dsi->info.n_data_lanes;
675
676         /* Calculate default DSI hs clock. DSI interface is double data rate.
677          * Data is transferred on both rising and falling edge of clk, div by 2
678          * to get the actual clock rate.
679          */
680         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
681
682         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
683                                         dsi->default_shift_clk_div.div) /
684                                         (2 * dsi->default_shift_clk_div.mul);
685
686         /* Get the actual shift_clk_div and clock rates. */
687         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
688         dsi->target_lp_clk_khz =
689                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
690         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
691
692         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
693                                         dsi->target_hs_clk_khz);
694
695 #if DSI_USE_SYNC_POINTS
696         dsi->syncpt_id = NVSYNCPT_DSI;
697 #endif
698
699         /*
700          * Force video clock to be continuous mode if
701          * enable_hs_clock_on_lp_cmd_mode is set
702          */
703         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
704                 if (dsi->info.video_clock_mode !=
705                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
706                         dev_warn(&dc->ndev->dev,
707                                 "Force clock continuous mode\n");
708
709                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
710         }
711
712         atomic_set(&dsi->host_ref, 0);
713         dsi->host_suspended = false;
714         mutex_init(&dsi->host_lock);
715         init_completion(&dc->out->user_vblank_comp);
716         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
717         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
718 }
719
720 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
721 (platform_t_phy_ns) ? ( \
722 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
723 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
724 ((default_phy) < 0 ? 0 : (default_phy)))
725
726 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
727                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
728 {
729         phy_timing_clk->t_tlpx = SELECT_T_PHY(
730                 dsi->info.phy_timing.t_tlpx_ns,
731                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
732
733         phy_timing_clk->t_clktrail = SELECT_T_PHY(
734                 dsi->info.phy_timing.t_clktrail_ns,
735                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
736
737         phy_timing_clk->t_clkpost = SELECT_T_PHY(
738                 dsi->info.phy_timing.t_clkpost_ns,
739                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
740
741         phy_timing_clk->t_clkzero = SELECT_T_PHY(
742                 dsi->info.phy_timing.t_clkzero_ns,
743                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
744
745         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
746                 dsi->info.phy_timing.t_clkprepare_ns,
747                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
748
749         phy_timing_clk->t_clkpre = SELECT_T_PHY(
750                 dsi->info.phy_timing.t_clkpre_ns,
751                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
752 }
753
754 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
755                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
756 {
757         phy_timing_clk->t_tlpx = SELECT_T_PHY(
758                 dsi->info.phy_timing.t_tlpx_ns,
759                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
760
761         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
762                 dsi->info.phy_timing.t_hsdexit_ns,
763                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
764
765         phy_timing_clk->t_hstrail = SELECT_T_PHY(
766                 dsi->info.phy_timing.t_hstrail_ns,
767                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
768
769         phy_timing_clk->t_datzero = SELECT_T_PHY(
770                 dsi->info.phy_timing.t_datzero_ns,
771                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
772
773         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
774                 dsi->info.phy_timing.t_hsprepare_ns,
775                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
776 }
777
778 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
779                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
780 {
781         phy_timing_clk->t_tlpx = SELECT_T_PHY(
782                 dsi->info.phy_timing.t_tlpx_ns,
783                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
784 }
785
786 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
787                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
788 {
789         phy_timing_clk->t_tlpx = SELECT_T_PHY(
790                 dsi->info.phy_timing.t_tlpx_ns,
791                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
792
793         phy_timing_clk->t_taget = SELECT_T_PHY(
794                 dsi->info.phy_timing.t_taget_ns,
795                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
796
797         phy_timing_clk->t_tasure = SELECT_T_PHY(
798                 dsi->info.phy_timing.t_tasure_ns,
799                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
800
801         phy_timing_clk->t_tago = SELECT_T_PHY(
802                 dsi->info.phy_timing.t_tago_ns,
803                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
804 }
805
806 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
807                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
808 {
809         phy_timing_clk->t_tlpx = SELECT_T_PHY(
810                 dsi->info.phy_timing.t_tlpx_ns,
811                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
812
813         phy_timing_clk->t_wakeup = SELECT_T_PHY(
814                 dsi->info.phy_timing.t_wakeup_ns,
815                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
816 }
817
818 #undef SELECT_T_PHY
819
820 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
821                                 struct dsi_phy_timing_inclk *phy_timing_clk,
822                                 u32 clk_ns, u8 lphs)
823 {
824         if (tegra_platform_is_fpga() && !(dsi->info.ganged_type)) {
825                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
826                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
827         }
828
829         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
830                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
831                         (T_HSEXIT_DEFAULT(clk_ns));
832
833         if (lphs == DSI_LPHS_IN_HS_MODE) {
834                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
835                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
836         } else {
837                 /* default is LP mode */
838                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
839                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
840                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
841                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
842                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
843         }
844 }
845
846 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
847                                 struct dsi_phy_timing_inclk *phy_timing,
848                                 u32 clk_ns, u8 lphs)
849 {
850         int err = 0;
851
852 #define CHECK_RANGE(val, min, max) ( \
853                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
854                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
855
856         if (tegra_platform_is_fpga())
857                 clk_ns = dsi->info.fpga_freq_khz ?
858                         ((1000 * 1000) / dsi->info.fpga_freq_khz) :
859                         DEFAULT_FPGA_FREQ_KHZ;
860
861         err = CHECK_RANGE(
862         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
863                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
864                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
865         if (err < 0) {
866                 dev_warn(&dsi->dc->ndev->dev,
867                         "dsi: Tlpx mipi range violated\n");
868                 goto fail;
869         }
870
871         if (lphs == DSI_LPHS_IN_HS_MODE) {
872                 err = CHECK_RANGE(
873                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
874                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
875                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
876                 if (err < 0) {
877                         dev_warn(&dsi->dc->ndev->dev,
878                                 "dsi: HsExit mipi range violated\n");
879                         goto fail;
880                 }
881
882                 err = CHECK_RANGE(
883                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
884                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
885                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
886                 if (err < 0) {
887                         dev_warn(&dsi->dc->ndev->dev,
888                                 "dsi: HsTrail mipi range violated\n");
889                         goto fail;
890                 }
891
892                 err = CHECK_RANGE(
893                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
894                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
895                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
896                 if (err < 0) {
897                         dev_warn(&dsi->dc->ndev->dev,
898                                 "dsi: HsZero mipi range violated\n");
899                         goto fail;
900                 }
901
902                 err = CHECK_RANGE(
903                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
904                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
905                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
906                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
907                 if (err < 0) {
908                         dev_warn(&dsi->dc->ndev->dev,
909                                 "dsi: HsPrepare mipi range violated\n");
910                         goto fail;
911                 }
912
913                 err = CHECK_RANGE(
914                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
915                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
916                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
917                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
918                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
919                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
920                 if (err < 0) {
921                         dev_warn(&dsi->dc->ndev->dev,
922                         "dsi: HsPrepare + HsZero mipi range violated\n");
923                         goto fail;
924                 }
925         } else {
926                 /* default is LP mode */
927                 err = CHECK_RANGE(
928                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
929                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
930                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
931                 if (err < 0) {
932                         dev_warn(&dsi->dc->ndev->dev,
933                                 "dsi: WakeUp mipi range violated\n");
934                         goto fail;
935                 }
936
937                 err = CHECK_RANGE(
938                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
939                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
940                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
941                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
942                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
943                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
944                 if (err < 0) {
945                         dev_warn(&dsi->dc->ndev->dev,
946                                 "dsi: TaSure mipi range violated\n");
947                         goto fail;
948                 }
949         }
950
951         if (lphs == DSI_LPHS_IN_HS_MODE ||
952                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
953                 err = CHECK_RANGE(
954                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
955                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
956                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
957                 if (err < 0) {
958                         dev_warn(&dsi->dc->ndev->dev,
959                                 "dsi: ClkTrail mipi range violated\n");
960                         goto fail;
961                 }
962
963                 err = CHECK_RANGE(
964                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
965                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
966                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
967                 if (err < 0) {
968                         dev_warn(&dsi->dc->ndev->dev,
969                                 "dsi: ClkPost mipi range violated\n");
970                         goto fail;
971                 }
972
973                 err = CHECK_RANGE(
974                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
975                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
976                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
977                 if (err < 0) {
978                         dev_warn(&dsi->dc->ndev->dev,
979                                 "dsi: ClkZero mipi range violated\n");
980                         goto fail;
981                 }
982
983                 err = CHECK_RANGE(
984                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
985                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
986                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
987                 if (err < 0) {
988                         dev_warn(&dsi->dc->ndev->dev,
989                                 "dsi: ClkPrepare mipi range violated\n");
990                         goto fail;
991                 }
992
993                 err = CHECK_RANGE(
994                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
995                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
996                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
997                 if (err < 0) {
998                         dev_warn(&dsi->dc->ndev->dev,
999                                 "dsi: ClkPre mipi range violated\n");
1000                         goto fail;
1001                 }
1002
1003                 err = CHECK_RANGE(
1004                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1005                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1006                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1007                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
1008                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
1009                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
1010                 if (err < 0) {
1011                         dev_warn(&dsi->dc->ndev->dev,
1012                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1013                         goto fail;
1014                 }
1015         }
1016 fail:
1017 #undef CHECK_RANGE
1018         return err;
1019 }
1020
1021 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1022                                 struct dsi_phy_timing_inclk *phy_timing,
1023                                 u32 clk_ns, u8 lphs)
1024 {
1025         u32 hs_t_phy_ns = 0;
1026         u32 clk_t_phy_ns = 0;
1027         u32 t_phy_ns;
1028         u32 h_blank_ns;
1029         struct tegra_dc_mode *modes;
1030         u32 t_pix_ns;
1031         int err = 0;
1032
1033         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1034                 goto fail;
1035
1036         if (dsi->info.video_data_type ==
1037                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1038                 dsi->info.video_burst_mode <=
1039                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1040                 goto fail;
1041
1042         modes = dsi->dc->out->modes;
1043         t_pix_ns = clk_ns * BITS_PER_BYTE *
1044                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1045
1046         hs_t_phy_ns =
1047                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1048                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1049                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1050                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1051                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1052                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1053                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1054                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1055                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1056                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1057                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1058                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1059
1060         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1061                 clk_t_phy_ns =
1062                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1063                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1064                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1065                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1066                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1067                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1068                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1069                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1070                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1071                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1072                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1073                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1074                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1075                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1076
1077                 /* clk_pre overlaps LP-11 hs mode start sequence */
1078                 hs_t_phy_ns -= DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1079                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC);
1080         }
1081
1082         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1083                                                 modes->h_front_porch);
1084
1085         /* Extra tlpx and byte cycle required by dsi HW */
1086         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1087                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1088                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1089                 clk_ns * BITS_PER_BYTE);
1090
1091         if (h_blank_ns < t_phy_ns) {
1092                 err = -EINVAL;
1093                 dev_WARN(&dsi->dc->ndev->dev,
1094                         "dsi: Hblank is smaller than HS trans phy timing\n");
1095                 goto fail;
1096         }
1097
1098         return 0;
1099 fail:
1100         return err;
1101 }
1102
1103 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1104                                 struct dsi_phy_timing_inclk *phy_timing,
1105                                 u32 clk_ns, u8 lphs)
1106 {
1107         int err = 0;
1108
1109         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1110         if (err < 0) {
1111                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1112                 goto fail;
1113         }
1114
1115         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1116         if (err < 0) {
1117                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1118                 goto fail;
1119         }
1120
1121         /* TODO: add more contraints */
1122 fail:
1123         return err;
1124 }
1125
1126 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1127 {
1128         u32 val;
1129         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1130
1131         tegra_dsi_get_phy_timing
1132                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1133
1134         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1135                                         dsi->current_bit_clk_ns, lphs);
1136
1137         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1138                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1139                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1140                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1141                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1142
1143                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1144                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1145                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1146                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1147
1148                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1149                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1150                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1151
1152                 phy_timing.t_taget += T_TAGET_HW_INC;
1153                 phy_timing.t_tasure += T_TASURE_HW_INC;
1154                 phy_timing.t_tago += T_TAGO_HW_INC;
1155         }
1156         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1157                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1158                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1159                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1160         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1161
1162         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1163                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1164                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1165                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1166         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1167
1168         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1169                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1170                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1171         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1172
1173         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1174                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1175                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1176         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1177
1178         dsi->phy_timing = phy_timing;
1179 }
1180
1181 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1182                                 struct tegra_dc_dsi_data *dsi)
1183 {
1184         u32 dsi_to_pixel_clk_ratio;
1185         u32 temp;
1186         u32 temp1;
1187         u32 mipi_clk_adj_kHz = 0;
1188         u32 sol_delay;
1189         struct tegra_dc_mode *dc_modes = &dc->mode;
1190
1191         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1192         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1193                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1194
1195         /* Convert Fdsi to byte format */
1196         dsi_to_pixel_clk_ratio *= 1000/8;
1197
1198         /* Multiplying by 1000 so that we don't loose the fraction part */
1199         temp = dc_modes->h_active * 1000;
1200         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1201                         dc_modes->h_sync_width;
1202
1203         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1204                         temp * dsi->pixel_scaler_mul /
1205                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1206
1207         /* Do rounding on sol delay */
1208         sol_delay = (sol_delay + 1000 - 1)/1000;
1209
1210         /* TODO:
1211          * 1. find out the correct sol fifo depth to use
1212          * 2. verify with hw about the clamping function
1213          */
1214         if (sol_delay > (480 * 4)) {
1215                 sol_delay = (480 * 4);
1216                 mipi_clk_adj_kHz = sol_delay +
1217                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1218                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1219
1220                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1221
1222                 mipi_clk_adj_kHz *= 4;
1223         }
1224
1225         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1226
1227         return sol_delay;
1228 }
1229
1230 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1231                                 struct tegra_dc_dsi_data *dsi)
1232 {
1233         u32 sol_delay;
1234         u32 internal_delay;
1235         u32 h_width_byte_clk;
1236         u32 h_width_pixels;
1237         u32 h_width_ganged_byte_clk;
1238         u8 n_data_lanes_this_cont = 0;
1239         u8 n_data_lanes_ganged = 0;
1240
1241         if (!(dsi->info.ganged_type)) {
1242                 if (dsi->info.video_burst_mode ==
1243                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1244                         dsi->info.video_burst_mode ==
1245                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1246 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1247                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1248                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1249 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1250                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1251                 } else {
1252                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1253                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1254                 }
1255         } else {
1256 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1257 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1258 #define FIFO_WR_PIX_CLK_DELAY 2
1259 #define FIFO_RD_BYTE_CLK_DELAY 6
1260 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1261                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1262                                 FIFO_WR_PIX_CLK_DELAY)
1263
1264                 internal_delay = DIV_ROUND_UP(
1265                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1266                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1267                                 + FIFO_RD_BYTE_CLK_DELAY;
1268
1269                 h_width_pixels = dc->mode.h_sync_width +
1270                                         dc->mode.h_back_porch +
1271                                         dc->mode.h_active +
1272                                         dc->mode.h_front_porch;
1273
1274                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1275                                         dsi->pixel_scaler_mul,
1276                                         dsi->pixel_scaler_div *
1277                                         dsi->info.n_data_lanes);
1278
1279                 if (dsi->info.ganged_type ==
1280                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1281                         dsi->info.ganged_type ==
1282                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1283                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1284                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1285                 }
1286
1287                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1288                                         n_data_lanes_this_cont *
1289                                         h_width_byte_clk,
1290                                         n_data_lanes_ganged);
1291
1292                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1293                                                         internal_delay;
1294                 sol_delay = (dsi->info.video_data_type ==
1295                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1296                                 sol_delay + 20: sol_delay;
1297
1298 #undef SOL_TO_VALID_PIX_CLK_DELAY
1299 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1300 #undef FIFO_WR_PIX_CLK_DELAY
1301 #undef FIFO_RD_BYTE_CLK_DELAY
1302 #undef TOT_INTERNAL_PIX_DELAY
1303         }
1304
1305         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1306                                                 DSI_SOL_DELAY);
1307 }
1308
1309 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1310 {
1311         u32 val;
1312         u32 bytes_per_frame;
1313         u32 timeout = 0;
1314
1315         /* TODO: verify the following equation */
1316         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1317                                                 (dsi->info.refresh_rate * 8);
1318         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1319         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1320
1321         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1322                         DSI_TIMEOUT_0_HTX_TO(timeout);
1323         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1324
1325         if (dsi->info.panel_reset_timeout_msec)
1326                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1327                                         / dsi->current_bit_clk_ns;
1328         else
1329                 timeout = DSI_PR_TO_VALUE;
1330
1331         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1332                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1333         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1334
1335         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1336                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1337                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1338                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1339         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1340 }
1341
1342 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1343                                                 struct tegra_dc_dsi_data *dsi)
1344 {
1345         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1346         u32 hact_pkt_len_pix = 0;
1347         u32 hact_pkt_len_bytes = 0;
1348         u32 hfp_pkt_len_bytes = 0;
1349         u32 pix_per_line_orig = 0;
1350         u32 pix_per_line = 0;
1351         u32 val = 0;
1352
1353 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1354 #define HEADER_OVERHEAD 16
1355
1356         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1357                         dc->mode.h_active + dc->mode.h_front_porch;
1358
1359         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1360                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1361                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1362                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1363                 if (dsi->controller_index) {
1364                         hact_pkt_len_pix =
1365                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1366                         pix_per_line = pix_per_line_orig - pix_per_line;
1367                 }
1368                 hact_pkt_len_bytes = hact_pkt_len_pix *
1369                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1370                 hfp_pkt_len_bytes = pix_per_line *
1371                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1372                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1373         }
1374
1375         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1376                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1377         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1378
1379         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1380                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1381         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1382
1383         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1384                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1385         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1386
1387         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1388                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1389         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1390
1391 #undef HEADER_OVERHEAD
1392 }
1393
1394 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1395                                                 struct tegra_dc_dsi_data *dsi)
1396 {
1397         u32 val;
1398         u32 hact_pkt_len;
1399         u32 hsa_pkt_len;
1400         u32 hbp_pkt_len;
1401         u32 hfp_pkt_len;
1402
1403         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1404                                                         dsi->pixel_scaler_div;
1405         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1406                                                         dsi->pixel_scaler_div;
1407         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1408                                                         dsi->pixel_scaler_div;
1409         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1410                                                         dsi->pixel_scaler_div;
1411
1412         if (dsi->info.video_burst_mode !=
1413                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1414                 hbp_pkt_len += hsa_pkt_len;
1415
1416         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1417         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1418         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1419
1420         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1421                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1422         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1423
1424         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1425                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1426         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1427
1428         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1429                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1430         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1431
1432         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1433         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1434 }
1435
1436 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1437                                                 struct tegra_dc_dsi_data *dsi)
1438 {
1439         unsigned long   val;
1440         unsigned long   act_bytes;
1441
1442         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1443                         dsi->pixel_scaler_div + 1;
1444
1445         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1446         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1447
1448         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1449         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1450
1451         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1452         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1453
1454         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1455         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1456 }
1457
1458 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1459                                 struct tegra_dc_dsi_data *dsi)
1460 {
1461         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1462                 return;
1463
1464         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1465                 if (dsi->info.ganged_type)
1466                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1467                 else
1468                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1469         } else {
1470                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1471         }
1472 }
1473
1474 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1475                                 struct tegra_dc_dsi_data *dsi)
1476 {
1477         const u32 *pkt_seq;
1478         u32 rgb_info;
1479         u32 pkt_seq_3_5_rgb_lo;
1480         u32 pkt_seq_3_5_rgb_hi;
1481         u32     val;
1482         u32 reg;
1483         u8  i;
1484
1485         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1486                 return;
1487
1488         switch (dsi->info.pixel_format) {
1489         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1490                 rgb_info = CMD_RGB_16BPP;
1491                 break;
1492         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1493                 rgb_info = CMD_RGB_18BPP;
1494                 break;
1495         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1496                 rgb_info = CMD_RGB_18BPPNP;
1497                 break;
1498         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1499         default:
1500                 rgb_info = CMD_RGB_24BPP;
1501                 break;
1502         }
1503
1504         pkt_seq_3_5_rgb_lo = 0;
1505         pkt_seq_3_5_rgb_hi = 0;
1506         if (dsi->info.pkt_seq)
1507                 pkt_seq = dsi->info.pkt_seq;
1508         else if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1509                 pkt_seq = dsi_pkt_seq_cmd_mode;
1510         else {
1511                 switch (dsi->info.video_burst_mode) {
1512                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1513                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1514                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1515                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1516                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1517                         pkt_seq_3_5_rgb_lo =
1518                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1519                         if (!dsi->info.no_pkt_seq_eot)
1520                                 pkt_seq = dsi_pkt_seq_video_burst;
1521                         else
1522                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1523                         break;
1524                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1525                         pkt_seq_3_5_rgb_hi =
1526                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1527                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1528                         break;
1529                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1530                 default:
1531                         if (dsi->info.ganged_type) {
1532                                 pkt_seq_3_5_rgb_lo =
1533                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1534                                 pkt_seq =
1535                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1536                         } else {
1537                                 pkt_seq_3_5_rgb_lo =
1538                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1539                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1540                         }
1541                         break;
1542                 }
1543         }
1544
1545         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1546                 val = pkt_seq[i];
1547                 reg = dsi_pkt_seq_reg[i];
1548                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1549                         val |= pkt_seq_3_5_rgb_lo;
1550                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1551                         val |= pkt_seq_3_5_rgb_hi;
1552                 tegra_dsi_writel(dsi, val, reg);
1553         }
1554 }
1555
1556 static void tegra_dsi_reset_underflow_overflow
1557                                 (struct tegra_dc_dsi_data *dsi)
1558 {
1559         u32 val;
1560
1561         val = tegra_dsi_readl(dsi, DSI_STATUS);
1562         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1563         if (val) {
1564                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1565                         dev_warn(&dsi->dc->ndev->dev,
1566                                 "dsi: video fifo overflow. Resetting flag\n");
1567                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1568                         dev_warn(&dsi->dc->ndev->dev,
1569                                 "dsi: video fifo underflow. Resetting flag\n");
1570                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1571                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1572                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1573                 udelay(5);
1574         }
1575 }
1576
1577 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1578 {
1579         u32 trigger;
1580         u32 val;
1581         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1582         struct tegra_dc_mode mode = dsi->dc->mode;
1583         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1584                                 mode.v_active + mode.v_front_porch;
1585         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1586         u32 timeout_cnt = 0;
1587
1588 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1589 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1590
1591         val = tegra_dsi_readl(dsi, DSI_STATUS);
1592         while (!(val & DSI_STATUS_IDLE(0x1))) {
1593                 cpu_relax();
1594                 udelay(line_period);
1595                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1596                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1597                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1598                         break;
1599                 }
1600         }
1601
1602         tegra_dsi_writel(dsi,
1603                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1604                 DSI_POWER_CONTROL);
1605         /* stabilization delay */
1606         udelay(300);
1607
1608         tegra_dsi_writel(dsi,
1609                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1610                 DSI_POWER_CONTROL);
1611         /* stabilization delay */
1612         udelay(300);
1613
1614         /* dsi HW does not clear host trigger bit automatically
1615          * on dsi interface disable if host fifo is empty or in mid
1616          * of host transmission
1617          */
1618         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1619         if (trigger)
1620                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1621
1622 #undef DSI_IDLE_TIMEOUT
1623 }
1624
1625 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1626                                         struct tegra_dc_dsi_data *dsi)
1627 {
1628         /* extra reference to dc clk */
1629         clk_prepare_enable(dc->clk);
1630
1631         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1632         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1633         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1634         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1635
1636         /* balance extra dc clk reference */
1637         clk_disable_unprepare(dc->clk);
1638
1639         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1640 }
1641
1642 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1643  * whichever happens to occur first
1644  */
1645 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1646                                 struct tegra_dc_dsi_data *dsi,
1647                                 u32 timeout_n_frames)
1648 {
1649         int val;
1650         long timeout;
1651         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1652         struct tegra_dc_mode mode = dc->mode;
1653         u32 line_period = DIV_ROUND_UP(
1654                                 MS_TO_US(frame_period),
1655                                 mode.v_sync_width + mode.v_back_porch +
1656                                 mode.v_active + mode.v_front_porch);
1657
1658         if (timeout_n_frames < 2)
1659                 dev_WARN(&dc->ndev->dev,
1660                 "dsi: to stop at next frame give at least 2 frame delay\n");
1661
1662         INIT_COMPLETION(dc->frame_end_complete);
1663
1664         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
1665         /* unmask frame end interrupt */
1666         val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1667
1668         timeout = wait_for_completion_interruptible_timeout(
1669                         &dc->frame_end_complete,
1670                         msecs_to_jiffies(timeout_n_frames * frame_period));
1671
1672         /* reinstate interrupt mask */
1673         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1674
1675         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1676         udelay(mode.v_ref_to_sync * line_period);
1677
1678         return timeout;
1679 }
1680
1681 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1682                                                 struct tegra_dc_dsi_data *dsi,
1683                                                 u32 timeout_n_frames)
1684 {
1685         tegra_dsi_stop_dc_stream(dc, dsi);
1686
1687         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1688
1689         tegra_dsi_soft_reset(dsi);
1690
1691         tegra_dsi_reset_underflow_overflow(dsi);
1692 }
1693
1694 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1695 {
1696         int err;
1697
1698         /* convert to spio */
1699         err = gpio_request(gpio, "temp_request");
1700         if (err < 0) {
1701                 dev_err(&dsi->dc->ndev->dev,
1702                         "dsi: %s: gpio request failed %d\n", __func__, err);
1703                 return;
1704         }
1705         gpio_free(gpio);
1706 }
1707
1708 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1709                                         struct tegra_dc_dsi_data *dsi)
1710 {
1711         u32 val;
1712
1713         /* take extra reference to dc clk */
1714         clk_prepare_enable(dc->clk);
1715
1716         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1717
1718         /* TODO: clean up */
1719         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1720                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1721                         DC_CMD_DISPLAY_POWER_CONTROL);
1722
1723         /* Configure one-shot mode or continuous mode */
1724         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1725                 /* disable LSPI/LCD_DE output */
1726                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1727                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1728
1729                 /* enable MSF & set MSF polarity */
1730                 val = MSF_ENABLE | MSF_LSPI;
1731                 if (!dsi->info.te_polarity_low)
1732                         val |= MSF_POLARITY_HIGH;
1733                 else
1734                         val |= MSF_POLARITY_LOW;
1735                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1736
1737                 /* set non-continuous mode */
1738                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1739                                                 DC_CMD_DISPLAY_COMMAND);
1740                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1741                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1742                                                 DC_CMD_STATE_CONTROL);
1743
1744                 if (dsi->info.te_gpio)
1745                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1746         } else {
1747                 /* set continuous mode */
1748                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1749                                                 DC_CMD_DISPLAY_COMMAND);
1750                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1751                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1752         }
1753
1754         /* balance extra dc clk reference */
1755         clk_disable_unprepare(dc->clk);
1756
1757         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1758 }
1759
1760 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1761                                 struct tegra_dc_dsi_data *dsi)
1762 {
1763         u32 shift_clk_div_register;
1764         u32 val;
1765
1766         /* formula: (dsi->shift_clk_div - 1) * 2 */
1767         shift_clk_div_register = (dsi->shift_clk_div.mul -
1768                                 dsi->shift_clk_div.div) * 2 /
1769                                 dsi->shift_clk_div.div;
1770
1771         if (tegra_platform_is_fpga()) {
1772                 shift_clk_div_register = 1;
1773                 if (dsi->info.ganged_type)
1774                         shift_clk_div_register = 0;
1775         }
1776
1777         val = PIXEL_CLK_DIVIDER_PCD1 |
1778                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1779
1780         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1781          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1782          * After 2us delay, write the target values to it. */
1783 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1784         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1785         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1786         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1787
1788         udelay(2);
1789 #endif
1790
1791         /* TODO: find out if PCD3 option is required */
1792         val = PIXEL_CLK_DIVIDER_PCD1 |
1793                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1794
1795         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1796 }
1797
1798 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1799                         struct tegra_dc_dsi_data *dsi, u32 clk)
1800 {
1801         u32 rm;
1802         u32 pclk_khz;
1803
1804         /* Round up to MHz */
1805         rm = clk % 1000;
1806         if (rm != 0)
1807                 clk -= rm;
1808
1809         /* Set up pixel clock */
1810         pclk_khz = (clk * dsi->shift_clk_div.div) /
1811                                 dsi->shift_clk_div.mul;
1812
1813         dc->mode.pclk = pclk_khz * 1000;
1814
1815         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1816         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1817
1818         /* TODO: Define one shot work delay in board file. */
1819         /* Since for one-shot mode, refresh rate is usually set larger than
1820          * expected refresh rate, it needs at least 3 frame period. Less
1821          * delay one shot work is, more powering saving we have. */
1822         dc->one_shot_delay_ms = 4 *
1823                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1824
1825         /* Enable DSI clock */
1826         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1827         tegra_dsi_clk_enable(dsi);
1828         tegra_periph_reset_deassert(dsi->dsi_clk);
1829
1830         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1831         dsi->current_bit_clk_ns =  1000*1000 / (dsi->current_dsi_clk_khz * 2);
1832 }
1833
1834 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1835 {
1836         u32 val;
1837
1838         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1839         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1840
1841         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1842                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1843                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1844         } else {
1845                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1846                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1847         }
1848         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1849
1850         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1851         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1852         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1853         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1854
1855         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1856 }
1857
1858 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1859 {
1860         u32 val;
1861         tegra_dsi_hs_clk_out_enable(dsi);
1862
1863         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1864         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1865         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1866         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1867 }
1868
1869 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1870                                                 struct tegra_dc_dsi_data *dsi)
1871 {
1872         u32 val;
1873
1874         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1875                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1876
1877         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1878         /* stabilization delay */
1879         udelay(300);
1880
1881         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1882         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1883         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1884         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1885
1886         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1887         /* stabilization delay */
1888         udelay(300);
1889
1890         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1891         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1892 }
1893
1894 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1895 {
1896         u32 dsi_control;
1897         u32 host_dsi_control;
1898         u32 max_threshold;
1899
1900         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1901         host_dsi_control = HOST_DSI_CTRL_COMMON |
1902                         HOST_DSI_CTRL_HOST_DRIVEN |
1903                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1904         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1905
1906         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1907         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1908         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1909
1910         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1911         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1912         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1913 }
1914
1915 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1916                                                 u8 driven_mode)
1917 {
1918         u32 dsi_control;
1919         u32 host_dsi_control;
1920         u32 max_threshold;
1921         u32 dcs_cmd;
1922
1923         dsi_control = dsi->dsi_control_val;
1924         host_dsi_control = HOST_DSI_CTRL_COMMON;
1925         max_threshold = 0;
1926         dcs_cmd = 0;
1927
1928         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1929                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1930                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1931                 max_threshold =
1932                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1933                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1934         } else {
1935                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1936                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1937                 max_threshold =
1938                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1939                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1940
1941                 if (dsi->info.video_data_type ==
1942                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1943                         dsi_control |= DSI_CTRL_CMD_MODE;
1944                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1945                                 DSI_WRITE_MEMORY_START)|
1946                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1947                                 DSI_WRITE_MEMORY_CONTINUE);
1948                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1949                 } else {
1950                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1951                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1952                 }
1953         }
1954
1955         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1956         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1957         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1958         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1959 }
1960
1961 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1962 {
1963         u32 val;
1964
1965         if (dsi->info.controller_vs == DSI_VS_1) {
1966                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1967                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1968                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1969                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1970                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
1971                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1972                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
1973                                                 (TEGRA_DSI_PAD_DISABLE) |
1974                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1975                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
1976                                                 (TEGRA_DSI_PAD_DISABLE);
1977                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
1978         } else {
1979                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
1980                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1981                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
1982                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
1983                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
1984                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
1985                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
1986                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
1987         }
1988 }
1989
1990 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
1991 {
1992         u32 val;
1993
1994         if (dsi->info.controller_vs == DSI_VS_1) {
1995                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
1996                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
1997                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
1998                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
1999                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2000                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2001                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2002                                                 TEGRA_DSI_PAD_ENABLE) |
2003                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2004                                                 TEGRA_DSI_PAD_ENABLE) |
2005                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2006                                                 TEGRA_DSI_PAD_ENABLE);
2007                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2008         } else {
2009                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2010                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2011                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2012                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2013                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2014                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2015                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2016                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2017         }
2018 }
2019 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2020 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2021 {
2022         u32 val;
2023         /* Calibration settings begin */
2024         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2025                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2026                 DSI_PAD_OUTADJCLK(0x0));
2027         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2028
2029         if (!dsi->controller_index) {
2030                 val = tegra_dsi_readl(dsi,
2031                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2032                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2033                         MIPI_CAL_SELDSIA(0x1) |
2034                         MIPI_CAL_HSPDOSDSIA(0x2) |
2035                         MIPI_CAL_HSPUOSDSIA(0x0) |
2036                         MIPI_CAL_TERMOSDSIA(0x5);
2037                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2038                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2039                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2040                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2041
2042                 /* Deselect PAD C */
2043                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2044                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2045                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2046                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2047                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2048
2049                 /* Deselect PAD D */
2050                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2051                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2052                 val &= ~(MIPI_CAL_SELDSID(0x1));
2053                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2054                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2055         } else {
2056                 val = tegra_dsi_readl(dsi,
2057                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2058                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2059                         MIPI_CAL_SELDSIC(0x1) |
2060                         MIPI_CAL_HSPDOSDSIC(0x2) |
2061                         MIPI_CAL_HSPUOSDSIC(0x0) |
2062                         MIPI_CAL_TERMOSDSIC(0x5);
2063                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2064                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2065                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2066                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2067
2068                 /* Deselect PAD A */
2069                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2070                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2071                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2072                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2073                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2074
2075                 /* Deselect PAD B */
2076                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2077                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2078                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2079                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2080                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2081         }
2082
2083         val = tegra_mipi_cal_read(dsi->mipi_cal,
2084                 MIPI_CAL_MIPI_CAL_CTRL_0);
2085         val = MIPI_CAL_NOISE_FLT(0xa) |
2086                   MIPI_CAL_PRESCALE(0x2) |
2087                   MIPI_CAL_CLKEN_OVR(0x1) |
2088                   MIPI_CAL_AUTOCAL_EN(0x0);
2089         tegra_mipi_cal_write(dsi->mipi_cal, val,
2090                 MIPI_CAL_MIPI_CAL_CTRL_0);
2091
2092 }
2093 #endif
2094 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2095 {
2096         u32 val = 0;
2097         u32 timeout = 0;
2098         if (!dsi->ulpm)
2099                 tegra_dsi_pad_enable(dsi);
2100         else
2101                 tegra_dsi_pad_disable(dsi);
2102
2103         if (dsi->info.controller_vs == DSI_VS_1) {
2104
2105                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2106
2107                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2108
2109                 tegra_mipi_cal_write(dsi->mipi_cal,
2110                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2111                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2112                 tegra_mipi_cal_write(dsi->mipi_cal,
2113                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2114                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2115
2116 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2117                 tegra_dsi_mipi_calibration_11x(dsi);
2118 #endif
2119                 /* Start calibration */
2120                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2121                         MIPI_CAL_MIPI_CAL_CTRL_0);
2122                 val |= (MIPI_CAL_STARTCAL(0x1));
2123                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2124                         MIPI_CAL_MIPI_CAL_CTRL_0);
2125
2126                         for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2127                                         timeout; timeout -= 100) {
2128                                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2129                                 MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2130                                 if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2131                                         (val & MIPI_AUTO_CAL_DONE(0x1))) {
2132                                                 dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2133                                                 break;
2134                                 }
2135                                 usleep_range(10, 100);
2136                         }
2137                         if (timeout <= 0)
2138                                 dev_err(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2139
2140                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2141         } else {
2142                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2143                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2144                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2145                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2146                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2147                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2148
2149                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2150                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2151                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2152                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2153                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2154
2155                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2156
2157                 val = MIPI_CAL_TERMOSA(0x4);
2158                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2159
2160                 val = MIPI_CAL_TERMOSB(0x4);
2161                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2162
2163                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2164                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2165
2166                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2167                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2168         }
2169
2170         val = PAD_CIL_PDVREG(0x0);
2171         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2172 }
2173
2174 static void tegra_dsi_panelB_enable(void)
2175 {
2176         unsigned int val;
2177
2178         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2179         val |= DSIB_MODE_ENABLE;
2180         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2181 }
2182
2183 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2184                                 struct tegra_dc_dsi_data *dsi)
2185 {
2186         u32 i;
2187
2188         regulator_enable(dsi->avdd_dsi_csi);
2189         /* stablization delay */
2190         mdelay(50);
2191
2192         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2193
2194         /* Stop DC stream before configuring DSI registers
2195          * to avoid visible glitches on panel during transition
2196          * from bootloader to kernel driver
2197          */
2198         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2199
2200         tegra_dsi_writel(dsi,
2201                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2202                 DSI_POWER_CONTROL);
2203         /* stabilization delay */
2204         udelay(300);
2205
2206         if (dsi->info.dsi_instance)
2207                 tegra_dsi_panelB_enable();
2208
2209         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2210
2211         /* Initialize DSI registers */
2212         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2213                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2214         if (dsi->info.controller_vs == DSI_VS_1) {
2215                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2216                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2217         }
2218
2219         tegra_dsi_pad_calibration(dsi);
2220
2221         tegra_dsi_writel(dsi,
2222                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2223                 DSI_POWER_CONTROL);
2224         /* stabilization delay */
2225         udelay(300);
2226
2227         dsi->status.init = DSI_MODULE_INIT;
2228         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2229         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2230         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2231         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2232         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2233         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2234         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2235         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2236
2237         return 0;
2238 }
2239
2240 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2241                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2242 {
2243         int err;
2244
2245         if (dsi->status.init != DSI_MODULE_INIT) {
2246                 err = -EPERM;
2247                 goto fail;
2248         }
2249
2250         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2251                         dsi->status.lp_op == lp_op)
2252                 goto success;
2253
2254         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2255                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2256
2257         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2258         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2259                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2260                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2261
2262         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2263         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2264                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2265                 tegra_dsi_set_timeout(dsi);
2266         }
2267
2268         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2269
2270         tegra_dsi_set_control_reg_lp(dsi);
2271
2272         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2273                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2274                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2275
2276         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2277         dsi->status.lp_op = lp_op;
2278         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2279 success:
2280         err = 0;
2281 fail:
2282         return err;
2283 }
2284
2285 static void tegra_dsi_ganged(struct tegra_dc *dc,
2286                                 struct tegra_dc_dsi_data *dsi)
2287 {
2288         u32 start = 0;
2289         u32 low_width = 0;
2290         u32 high_width = 0;
2291         u32 h_active = dc->out->modes->h_active;
2292         u32 val = 0;
2293
2294         if (dsi->info.controller_vs < DSI_VS_1) {
2295                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2296                 "supported with current controller version\n");
2297                 return;
2298         }
2299
2300         if (dsi->info.ganged_type ==
2301                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2302                 low_width = DIV_ROUND_UP(h_active, 2);
2303                 high_width = h_active - low_width;
2304                 if (dsi->controller_index)
2305                         start = h_active / 2;
2306                 else
2307                         start = 0;
2308         } else if (dsi->info.ganged_type ==
2309                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2310                 low_width = 0x1;
2311                 high_width = 0x1;
2312                 if (dsi->controller_index)
2313                         start = 1;
2314                 else
2315                         start = 0;
2316         }
2317
2318         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2319                                                 DSI_GANGED_MODE_START);
2320
2321         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2322                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2323         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2324
2325         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2326                                                 DSI_GANGED_MODE_CONTROL);
2327 }
2328
2329 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2330                                         struct tegra_dc_dsi_data *dsi,
2331                                         u8 driven_mode)
2332 {
2333         int err;
2334
2335         if (dsi->status.init != DSI_MODULE_INIT) {
2336                 err = -EPERM;
2337                 goto fail;
2338         }
2339
2340         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2341                 dsi->driven_mode == driven_mode)
2342                 goto success;
2343
2344         dsi->driven_mode = driven_mode;
2345
2346         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2347                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2348
2349         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2350                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2351                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2352
2353         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2354                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2355                 tegra_dsi_set_timeout(dsi);
2356         }
2357
2358         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2359
2360         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2361                 tegra_dsi_set_pkt_seq(dc, dsi);
2362                 tegra_dsi_set_pkt_length(dc, dsi);
2363                 tegra_dsi_set_sol_delay(dc, dsi);
2364                 tegra_dsi_set_dc_clk(dc, dsi);
2365         }
2366
2367         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2368
2369         if (dsi->info.ganged_type)
2370                 tegra_dsi_ganged(dc, dsi);
2371
2372         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2373                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2374                 tegra_dsi_hs_clk_out_enable(dsi);
2375
2376         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2377 success:
2378         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2379         err = 0;
2380 fail:
2381         return err;
2382 }
2383
2384 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2385 {
2386         u32 timeout = 0;
2387         bool retVal = true;
2388
2389         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2390                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2391                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2392                         retVal = false;
2393                         break;
2394                 }
2395                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2396                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2397         }
2398
2399         return retVal;
2400 }
2401
2402 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2403 {
2404         u32 timeout = 0;
2405         bool retVal = true;
2406
2407         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2408                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2409                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2410                         retVal = false;
2411                         break;
2412                 }
2413                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2414                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2415         }
2416
2417         return retVal;
2418 }
2419
2420 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2421 {
2422         int err = 0;
2423
2424         if (tegra_dsi_write_busy(dsi)) {
2425                 err = -EBUSY;
2426                 dev_err(&dsi->dc->ndev->dev,
2427                         "DSI trigger bit already set\n");
2428                 goto fail;
2429         }
2430
2431         if (tegra_dsi_read_busy(dsi)) {
2432                 err = -EBUSY;
2433                 dev_err(&dsi->dc->ndev->dev,
2434                         "DSI immediate bta bit already set\n");
2435                 goto fail;
2436         }
2437 fail:
2438         return (err < 0 ? true : false);
2439 }
2440
2441 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2442 {
2443         u32 val;
2444
2445         val = tegra_dsi_readl(dsi, DSI_STATUS);
2446         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2447         if (val) {
2448                 dev_warn(&dsi->dc->ndev->dev,
2449                         "DSI read count not zero, resetting\n");
2450                 tegra_dsi_soft_reset(dsi);
2451         }
2452 }
2453
2454 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2455                                                 struct tegra_dc_dsi_data *dsi,
2456                                                 struct tegra_dc *dc,
2457                                                 u8 lp_op)
2458 {
2459         struct dsi_status *init_status = NULL;
2460         int err;
2461
2462         if (dsi->status.init != DSI_MODULE_INIT ||
2463                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2464                 err = -EPERM;
2465                 goto fail;
2466         }
2467
2468         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2469         if (!init_status)
2470                 return ERR_PTR(-ENOMEM);
2471
2472         *init_status = dsi->status;
2473
2474         if (dsi->info.hs_cmd_mode_supported) {
2475                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2476                                 TEGRA_DSI_DRIVEN_BY_HOST);
2477                 if (err < 0) {
2478                         dev_err(&dc->ndev->dev,
2479                         "Switch to HS host mode failed\n");
2480                         goto fail;
2481                 }
2482
2483                 goto success;
2484         }
2485
2486         if (dsi->status.lp_op != lp_op) {
2487                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2488                 if (err < 0) {
2489                         dev_err(&dc->ndev->dev,
2490                         "DSI failed to go to LP mode\n");
2491                         goto fail;
2492                 }
2493         }
2494 success:
2495         return init_status;
2496 fail:
2497         kfree(init_status);
2498         return ERR_PTR(err);
2499 }
2500
2501 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2502                                 struct tegra_dc *dc,
2503                                 struct tegra_dc_dsi_data *dsi,
2504                                 u8 lp_op)
2505 {
2506         int err = 0;
2507         struct dsi_status *init_status;
2508         bool restart_dc_stream = false;
2509
2510         if (dsi->status.init != DSI_MODULE_INIT ||
2511                 dsi->ulpm) {
2512                 err = -EPERM;
2513                 goto fail;
2514         }
2515
2516         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2517                 restart_dc_stream = true;
2518                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2519         }
2520
2521         if (tegra_dsi_host_busy(dsi)) {
2522                 tegra_dsi_soft_reset(dsi);
2523                 if (tegra_dsi_host_busy(dsi)) {
2524                         err = -EBUSY;
2525                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2526                         goto fail;
2527                 }
2528         }
2529
2530         if (lp_op == DSI_LP_OP_READ)
2531                 tegra_dsi_reset_read_count(dsi);
2532
2533         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2534                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2535                 if (err < 0) {
2536                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2537                         goto fail;
2538                 }
2539         }
2540
2541         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2542                                         (dsi, dc, lp_op);
2543         if (IS_ERR_OR_NULL(init_status)) {
2544                 err = PTR_ERR(init_status);
2545                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2546                 goto fail;
2547         }
2548
2549         if (restart_dc_stream)
2550                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2551
2552         if (atomic_read(&dsi_syncpt_rst))
2553                 tegra_dsi_syncpt_reset(dsi);
2554
2555         return init_status;
2556 fail:
2557         return ERR_PTR(err);
2558 }
2559
2560 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2561                                 struct tegra_dc_dsi_data *dsi,
2562                                 struct dsi_status *init_status)
2563 {
2564         int err = 0;
2565
2566         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2567                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2568                 if (err < 0) {
2569                         dev_err(&dc->ndev->dev,
2570                                 "Failed to config LP mode\n");
2571                         goto fail;
2572                 }
2573                 goto success;
2574         }
2575
2576         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2577                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2578                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2579                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2580                 if (err < 0) {
2581                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2582                         goto fail;
2583                 }
2584         }
2585
2586         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2587                 tegra_dsi_start_dc_stream(dc, dsi);
2588 success:
2589 fail:
2590         kfree(init_status);
2591         return err;
2592 }
2593
2594 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2595 {
2596         int status = 0;
2597
2598         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2599                 status = -EBUSY;
2600                 goto fail;
2601         }
2602
2603         tegra_dsi_writel(dsi,
2604                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2605
2606 #if DSI_USE_SYNC_POINTS
2607         status = tegra_dsi_syncpt(dsi);
2608         if (status < 0) {
2609                 dev_err(&dsi->dc->ndev->dev,
2610                         "DSI syncpt for host trigger failed\n");
2611                 goto fail;
2612         }
2613 #else
2614         if (tegra_dsi_write_busy(dsi)) {
2615                 status = -EBUSY;
2616                 dev_err(&dsi->dc->ndev->dev,
2617                         "Timeout waiting on write completion\n");
2618         }
2619 #endif
2620
2621 fail:
2622         return status;
2623 }
2624
2625 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2626                                         u8 *pdata, u8 data_id, u16 data_len)
2627 {
2628         u8 virtual_channel;
2629         u32 val;
2630         int err;
2631
2632         err = 0;
2633
2634         virtual_channel = dsi->info.virtual_channel <<
2635                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2636
2637         /* always use hw for ecc */
2638         val = (virtual_channel | data_id) << 0 |
2639                         data_len << 8;
2640         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2641
2642         /* if pdata != NULL, pkt type is long pkt */
2643         if (pdata != NULL) {
2644                 while (data_len) {
2645                         if (data_len >= 4) {
2646                                 val = ((u32 *) pdata)[0];
2647                                 data_len -= 4;
2648                                 pdata += 4;
2649                         } else {
2650                                 val = 0;
2651                                 memcpy(&val, pdata, data_len);
2652                                 pdata += data_len;
2653                                 data_len = 0;
2654                         }
2655                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2656                 }
2657         }
2658
2659         err = tegra_dsi_host_trigger(dsi);
2660         if (err < 0)
2661                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2662
2663         return err;
2664 }
2665
2666 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2667 {
2668         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2669
2670         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2671                 atomic_inc(&dsi->host_ref);
2672                 tegra_dsi_host_resume(dc);
2673         }
2674 }
2675
2676 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2677 {
2678         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2679
2680         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2681                 atomic_dec(&dsi->host_ref);
2682
2683                 if (!atomic_read(&dsi->host_ref) &&
2684                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2685                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2686         }
2687 }
2688
2689 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2690 {
2691         struct tegra_dc_dsi_data *dsi = container_of(
2692                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2693
2694         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2695                 tegra_dsi_host_suspend(dsi->dc);
2696 }
2697
2698 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2699                         struct tegra_dc_dsi_data *dsi,
2700                         u8 *pdata, u8 data_id, u16 data_len)
2701 {
2702         int err = 0;
2703         struct dsi_status *init_status;
2704
2705         init_status = tegra_dsi_prepare_host_transmission(
2706                                 dc, dsi, DSI_LP_OP_WRITE);
2707         if (IS_ERR_OR_NULL(init_status)) {
2708                 err = PTR_ERR(init_status);
2709                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2710                 goto fail;
2711         }
2712
2713         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2714 fail:
2715         err = tegra_dsi_restore_state(dc, dsi, init_status);
2716         if (err < 0)
2717                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2718
2719         return err;
2720 }
2721
2722 int tegra_dsi_write_data(struct tegra_dc *dc,
2723                         struct tegra_dc_dsi_data *dsi,
2724                         u8 *pdata, u8 data_id, u16 data_len)
2725 {
2726         int err;
2727
2728         tegra_dc_io_start(dc);
2729         tegra_dc_dsi_hold_host(dc);
2730
2731         err = tegra_dsi_write_data_nosync(dc, dsi, pdata, data_id, data_len);
2732
2733         tegra_dc_dsi_release_host(dc);
2734         tegra_dc_io_end(dc);
2735
2736         return err;
2737 }
2738
2739 EXPORT_SYMBOL(tegra_dsi_write_data);
2740
2741 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2742                                         struct tegra_dc_dsi_data *dsi,
2743                                         struct tegra_dsi_cmd *cmd,
2744                                         u32 n_cmd)
2745 {
2746         u32 i;
2747         int err;
2748
2749         err = 0;
2750         for (i = 0; i < n_cmd; i++) {
2751                 struct tegra_dsi_cmd *cur_cmd;
2752                 cur_cmd = &cmd[i];
2753
2754                 /*
2755                  * Some Panels need reset midway in the command sequence.
2756                  */
2757                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
2758                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
2759                                        cur_cmd->data_id);
2760                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
2761                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2762                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
2763                                 tegra_dsi_send_dc_frames(dc,
2764                                                 dsi,
2765                                                 cur_cmd->sp_len_dly.frame_cnt);
2766                 } else {
2767                         err = tegra_dsi_write_data_nosync(dc, dsi,
2768                                                 cur_cmd->pdata,
2769                                                 cur_cmd->data_id,
2770                                                 cur_cmd->sp_len_dly.data_len);
2771                         mdelay(1);
2772                         if (err < 0)
2773                                 break;
2774                 }
2775         }
2776         return err;
2777 }
2778
2779 static u8 tegra_dsi_ecc(u32 header)
2780 {
2781         char ecc_parity[24] = {
2782                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2783                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2784                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2785         };
2786         u8 ecc_byte;
2787         int i;
2788
2789         ecc_byte = 0;
2790         for (i = 0; i < 24; i++)
2791                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2792
2793         return ecc_byte;
2794 }
2795
2796 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2797 {
2798         u16 byte_cnt;
2799         u8 bit_cnt;
2800         char curr_byte;
2801         u16 crc = 0xFFFF;
2802         u16 poly = 0x8408;
2803
2804         if (data_len > 0) {
2805                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2806                         curr_byte = pdata[byte_cnt];
2807                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2808                                 if (((crc & 0x0001 ) ^
2809                                         (curr_byte & 0x0001)) > 0)
2810                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2811                                 else
2812                                         crc = (crc >> 1) & 0x7FFF;
2813
2814                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2815                         }
2816                 }
2817         }
2818         return crc;
2819 }
2820
2821 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2822                                                 struct tegra_dsi_cmd *cmd)
2823 {
2824         u8 virtual_channel;
2825         u32 val;
2826         u16 data_len = cmd->sp_len_dly.data_len;
2827         u8 seq_ctrl_reg = 0;
2828
2829         virtual_channel = dsi->info.virtual_channel <<
2830                                 DSI_VIR_CHANNEL_BIT_POSITION;
2831
2832         val = (virtual_channel | cmd->data_id) << 0 |
2833                 data_len << 8;
2834
2835         val |= tegra_dsi_ecc(val) << 24;
2836
2837         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2838
2839         /* if pdata != NULL, pkt type is long pkt */
2840         if (cmd->pdata != NULL) {
2841                 u8 *pdata;
2842                 u8 *pdata_mem;
2843                 /* allocate memory for pdata + 2 bytes checksum */
2844                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2845                 if (!pdata_mem) {
2846                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2847                         tegra_dsi_soft_reset(dsi);
2848                         return -ENOMEM;
2849                 }
2850
2851                 memcpy(pdata_mem, cmd->pdata, data_len);
2852                 pdata = pdata_mem;
2853                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2854
2855                 /* data_len = length of pdata + 2 byte checksum */
2856                 data_len += 2;
2857
2858                 while (data_len) {
2859                         if (data_len >= 4) {
2860                                 val = ((u32 *) pdata)[0];
2861                                 data_len -= 4;
2862                                 pdata += 4;
2863                         } else {
2864                                 val = 0;
2865                                 memcpy(&val, pdata, data_len);
2866                                 pdata += data_len;
2867                                 data_len = 0;
2868                         }
2869                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2870                                                         seq_ctrl_reg++);
2871                 }
2872                 kfree(pdata_mem);
2873         }
2874
2875         return 0;
2876 }
2877
2878 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2879                                                 struct tegra_dsi_cmd *cmd)
2880 {
2881 #define PKT_HEADER_LEN_BYTE     4
2882 #define CHECKSUM_LEN_BYTE       2
2883
2884         int err = 0;
2885         u32 val;
2886         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2887         struct tegra_dc *dc = dsi->dc;
2888
2889         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2890                 return -EINVAL;
2891
2892         mutex_lock(&dsi->lock);
2893         tegra_dc_io_start(dc);
2894         tegra_dc_dsi_hold_host(dc);
2895
2896 #if DSI_USE_SYNC_POINTS
2897         atomic_set(&dsi_syncpt_rst, 1);
2898 #endif
2899
2900         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2901         if (err < 0) {
2902                 dev_err(&dsi->dc->ndev->dev,
2903                         "dsi: dcs pkt seq ctrl init failed\n");
2904                 goto fail;
2905         }
2906
2907         if (cmd->pdata) {
2908                 u16 data_len = cmd->sp_len_dly.data_len;
2909                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2910         }
2911
2912         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2913                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2914                                                 TEGRA_DSI_ENABLE);
2915         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2916
2917 fail:
2918         tegra_dc_dsi_release_host(dc);
2919         tegra_dc_io_end(dc);
2920         mutex_unlock(&dsi->lock);
2921         return err;
2922
2923 #undef PKT_HEADER_LEN_BYTE
2924 #undef CHECKSUM_LEN_BYTE
2925 }
2926 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2927
2928 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2929 {
2930         struct tegra_dc *dc = dsi->dc;
2931         u32 cnt;
2932
2933         mutex_lock(&dsi->lock);
2934         tegra_dc_io_start(dc);
2935         tegra_dc_dsi_hold_host(dc);
2936
2937         if (atomic_read(&dsi_syncpt_rst)) {
2938                 tegra_dsi_wait_frame_end(dc, dsi, 2);
2939                 tegra_dsi_syncpt_reset(dsi);
2940                 atomic_set(&dsi_syncpt_rst, 0);
2941         }
2942
2943         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2944
2945         /* clear seq data registers */
2946         for (cnt = 0; cnt < 8; cnt++)
2947                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2948
2949         tegra_dc_dsi_release_host(dc);
2950         tegra_dc_io_end(dc);
2951
2952         mutex_unlock(&dsi->lock);
2953 }
2954 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2955
2956 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
2957 {
2958         u32 val;
2959         int err = 0;
2960
2961         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
2962         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
2963         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
2964
2965 #if DSI_USE_SYNC_POINTS
2966         err = tegra_dsi_syncpt(dsi);
2967         if (err < 0) {
2968                 dev_err(&dsi->dc->ndev->dev,
2969                         "DSI syncpt for bta failed\n");
2970         }
2971 #else
2972         if (tegra_dsi_read_busy(dsi)) {
2973                 err = -EBUSY;
2974                 dev_err(&dsi->dc->ndev->dev,
2975                         "Timeout wating on read completion\n");
2976         }
2977 #endif
2978
2979         return err;
2980 }
2981
2982 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
2983                                         u32 rd_fifo_cnt, u8 *read_fifo)
2984 {
2985         int err;
2986         u32 payload_size;
2987
2988         payload_size = 0;
2989         err = 0;
2990
2991         switch (read_fifo[0]) {
2992         case DSI_ESCAPE_CMD:
2993                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
2994                 break;
2995         case DSI_ACK_NO_ERR:
2996                 dev_info(&dc->ndev->dev,
2997                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
2998                 return err;
2999         default:
3000                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3001                 break;
3002         }
3003
3004         switch (read_fifo[4] & 0xff) {
3005         case GEN_LONG_RD_RES:
3006                 /* Fall through */
3007         case DCS_LONG_RD_RES:
3008                 payload_size = (read_fifo[5] |
3009                                 (read_fifo[6] << 8)) & 0xFFFF;
3010                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3011                                 "payload_size[0x%x]\n", payload_size);
3012                 break;
3013         case GEN_1_BYTE_SHORT_RD_RES:
3014                 /* Fall through */
3015         case DCS_1_BYTE_SHORT_RD_RES:
3016                 payload_size = 1;
3017                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3018                         "payload_size[0x%x]\n", payload_size);
3019                 break;
3020         case GEN_2_BYTE_SHORT_RD_RES:
3021                 /* Fall through */
3022         case DCS_2_BYTE_SHORT_RD_RES:
3023                 payload_size = 2;
3024                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3025                         "payload_size[0x%x]\n", payload_size);
3026                 break;
3027         case ACK_ERR_RES:
3028                 payload_size = 2;
3029                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3030                         "Packet payload_size[0x%x]\n", payload_size);
3031                 break;
3032         default:
3033                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3034                 err = -EINVAL;
3035                 break;
3036         }
3037         return err;
3038 }
3039
3040 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3041                         struct tegra_dc_dsi_data *dsi,
3042                         u8 *read_fifo)
3043 {
3044         u32 val;
3045         u32 i;
3046         u32 poll_time = 0;
3047         u32 rd_fifo_cnt;
3048         int err = 0;
3049         u8 *read_fifo_cp = read_fifo;
3050
3051         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3052                 mdelay(1);
3053                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3054                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3055                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3056                         dev_err(&dc->ndev->dev,
3057                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3058                         break;
3059                 }
3060                 poll_time++;
3061         }
3062
3063         if (rd_fifo_cnt == 0) {
3064                 dev_info(&dc->ndev->dev,
3065                         "DSI RD_FIFO_CNT is zero\n");
3066                 err = -EINVAL;
3067                 goto fail;
3068         }
3069
3070         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3071                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3072                 dev_warn(&dc->ndev->dev,
3073                         "DSI overflow/underflow error\n");
3074         }
3075
3076         /* Read data from FIFO */
3077         for (i = 0; i < rd_fifo_cnt; i++) {
3078                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3079                 if (enable_read_debug)
3080                         dev_info(&dc->ndev->dev,
3081                         "Read data[%d]: 0x%x\n", i, val);
3082                 memcpy(read_fifo, &val, 4);
3083                 read_fifo += 4;
3084         }
3085
3086         /* Make sure all the data is read from the FIFO */
3087         val = tegra_dsi_readl(dsi, DSI_STATUS);
3088         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3089         if (val)
3090                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3091                 " even after reading FIFO_RD_CNT words from read fifo\n");
3092
3093         if (enable_read_debug) {
3094                 err =
3095                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3096                 if (err < 0)
3097                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3098         }
3099 fail:
3100         return err;
3101 }
3102
3103 int tegra_dsi_read_data(struct tegra_dc *dc,
3104                                 struct tegra_dc_dsi_data *dsi,
3105                                 u32 max_ret_payload_size,
3106                                 u32 panel_reg_addr, u8 *read_data)
3107 {
3108         int err = 0;
3109         struct dsi_status *init_status;
3110
3111         mutex_lock(&dsi->lock);
3112         tegra_dc_io_start(dc);
3113         clk_prepare_enable(dsi->dsi_fixed_clk);
3114
3115         init_status = tegra_dsi_prepare_host_transmission(
3116                                 dc, dsi, DSI_LP_OP_WRITE);
3117         if (IS_ERR_OR_NULL(init_status)) {
3118                 err = PTR_ERR(init_status);
3119                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3120                 goto fail;
3121         }
3122
3123         /* Set max return payload size in words */
3124         err = _tegra_dsi_write_data(dsi, NULL,
3125                 dsi_command_max_return_pkt_size,
3126                 max_ret_payload_size);
3127         if (err < 0) {
3128                 dev_err(&dc->ndev->dev,
3129                                 "DSI write failed\n");
3130                 goto fail;
3131         }
3132
3133         /* DCS to read given panel register */
3134         err = _tegra_dsi_write_data(dsi, NULL,
3135                 dsi_command_dcs_read_with_no_params,
3136                 panel_reg_addr);
3137         if (err < 0) {
3138                 dev_err(&dc->ndev->dev,
3139                                 "DSI write failed\n");
3140                 goto fail;
3141         }
3142
3143         tegra_dsi_reset_read_count(dsi);
3144
3145         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3146                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3147                 if (err < 0) {
3148                         dev_err(&dc->ndev->dev,
3149                         "DSI failed to go to LP read mode\n");
3150                         goto fail;
3151                 }
3152         }
3153
3154         err = tegra_dsi_bta(dsi);
3155         if (err < 0) {
3156                 dev_err(&dc->ndev->dev,
3157                         "DSI IMM BTA timeout\n");
3158                 goto fail;
3159         }
3160
3161         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3162         if (err < 0) {
3163                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3164                 goto fail;
3165         }
3166 fail:
3167         err = tegra_dsi_restore_state(dc, dsi, init_status);
3168         if (err < 0)
3169                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3170         clk_disable_unprepare(dsi->dsi_fixed_clk);
3171         tegra_dc_io_end(dc);
3172         mutex_unlock(&dsi->lock);
3173         return err;
3174 }
3175 EXPORT_SYMBOL(tegra_dsi_read_data);
3176
3177 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3178                                 struct tegra_dc_dsi_data *dsi)
3179 {
3180         int err = 0;
3181         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3182         struct dsi_status *init_status;
3183         static struct tegra_dsi_cmd dsi_nop_cmd =
3184                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3185
3186         tegra_dc_io_start(dc);
3187         clk_prepare_enable(dsi->dsi_fixed_clk);
3188
3189         init_status = tegra_dsi_prepare_host_transmission(
3190                                         dc, dsi, DSI_LP_OP_WRITE);
3191         if (IS_ERR_OR_NULL(init_status)) {
3192                 err = PTR_ERR(init_status);
3193                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3194                 goto fail;
3195         }
3196
3197         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
3198         if (err < 0) {
3199                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3200                 goto fail;
3201         }
3202
3203         tegra_dsi_reset_read_count(dsi);
3204
3205         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3206                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3207                 if (err < 0) {
3208                         dev_err(&dc->ndev->dev,
3209                         "DSI failed to go to LP read mode\n");
3210                         goto fail;
3211                 }
3212         }
3213
3214         err = tegra_dsi_bta(dsi);
3215         if (err < 0) {
3216                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3217                 goto fail;
3218         }
3219
3220         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3221         if (err < 0) {
3222                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3223                 goto fail;
3224         }
3225
3226         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3227                 dev_warn(&dc->ndev->dev,
3228                         "Ack no error trigger message not received\n");
3229                 err = -EAGAIN;
3230         }
3231 fail:
3232         err = tegra_dsi_restore_state(dc, dsi, init_status);
3233         if (err < 0)
3234                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3235         clk_disable_unprepare(dsi->dsi_fixed_clk);
3236         tegra_dc_io_end(dc);
3237         return err;
3238 }
3239 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3240
3241 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3242 {
3243         u32 val;
3244         int ret = 0;
3245
3246         if (atomic_read(&dsi_syncpt_rst))
3247                 tegra_dsi_syncpt_reset(dsi);
3248
3249         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3250         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3251         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3252         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3253
3254 #if DSI_USE_SYNC_POINTS
3255         ret = tegra_dsi_syncpt(dsi);
3256         if (ret < 0) {
3257                 dev_err(&dsi->dc->ndev->dev,
3258                         "DSI syncpt for ulpm enter failed\n");
3259                 return ret;
3260         }
3261 #else
3262         /* TODO: Find exact delay required */
3263         mdelay(10);
3264 #endif
3265         dsi->ulpm = true;
3266
3267         return ret;
3268 }
3269
3270 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3271 {
3272         u32 val;
3273         int ret = 0;
3274
3275         if (atomic_read(&dsi_syncpt_rst))
3276                 tegra_dsi_syncpt_reset(dsi);
3277
3278         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3279         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3280         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3281         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3282
3283 #if DSI_USE_SYNC_POINTS
3284         ret = tegra_dsi_syncpt(dsi);
3285         if (ret < 0) {
3286                 dev_err(&dsi->dc->ndev->dev,
3287                         "DSI syncpt for ulpm exit failed\n");
3288                 return ret;
3289         }
3290 #else
3291         /* TODO: Find exact delay required */
3292         mdelay(10);
3293 #endif
3294         dsi->ulpm = false;
3295
3296         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3297         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3298         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3299         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3300
3301         return ret;
3302 }
3303
3304 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3305                                      struct tegra_dc_dsi_data *dsi,
3306                                      int no_of_frames)
3307 {
3308         int err;
3309         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3310         u8 lp_op = dsi->status.lp_op;
3311         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3312
3313         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3314                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3315                                 TEGRA_DSI_DRIVEN_BY_DC);
3316                 if (err < 0) {
3317                         dev_err(&dc->ndev->dev,
3318                                 "Switch to HS host mode failed\n");
3319                         return;
3320                 }
3321         }
3322
3323         /*
3324          * Some panels need DC frames be sent under certain
3325          * conditions. We are working on the right fix for this
3326          * requirement, while using this current fix.
3327          */
3328         tegra_dsi_start_dc_stream(dc, dsi);
3329
3330         /*
3331          * Send frames in Continuous or One-shot mode.
3332          */
3333         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3334                 while (no_of_frames--) {
3335                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3336                                         DC_CMD_STATE_CONTROL);
3337                         mdelay(frame_period);
3338                 }
3339         } else
3340                 mdelay(no_of_frames * frame_period);
3341
3342         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3343
3344         if (switch_to_lp) {
3345                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3346                 if (err < 0)
3347                         dev_err(&dc->ndev->dev,
3348                                 "DSI failed to go to LP mode\n");
3349         }
3350 }
3351
3352 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
3353 {
3354         regulator_enable(dsi->avdd_dsi_csi);
3355
3356         dsi->status.init = DSI_MODULE_INIT;
3357         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3358         dsi->status.driven = DSI_DRIVEN_MODE_DC;
3359         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3360         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
3361         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3362         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
3363
3364         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
3365                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
3366         else
3367                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
3368
3369         if (!(dsi->info.ganged_type)) {
3370                 if (dsi->info.video_burst_mode ==
3371                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
3372                         dsi->info.video_burst_mode ==
3373                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
3374                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
3375                 else
3376                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
3377         }
3378
3379         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
3380                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
3381         else
3382                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
3383
3384         tegra_dsi_clk_enable(dsi);
3385
3386         dsi->enabled = true;
3387 }
3388
3389 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3390 {
3391         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3392         int err = 0;
3393
3394         mutex_lock(&dsi->lock);
3395         tegra_dc_io_start(dc);
3396
3397         /*
3398          * Do not program this panel as the bootloader as has already
3399          * initialized it. This avoids periods of blanking during boot.
3400          */
3401         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
3402                 tegra_dsi_setup_initialized_panel(dsi);
3403                 goto fail;
3404         }
3405
3406         /* Stop DC stream before configuring DSI registers
3407          * to avoid visible glitches on panel during transition
3408          * from bootloader to kernel driver
3409          */
3410         tegra_dsi_stop_dc_stream(dc, dsi);
3411
3412         if (dsi->enabled) {
3413                 if (dsi->ulpm) {
3414                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3415                                 dev_err(&dc->ndev->dev,
3416                                         "DSI failed to exit ulpm\n");
3417                                 goto fail;
3418                         }
3419                 }
3420
3421                 if (dsi->info.panel_reset) {
3422                         /*
3423                          * Certain panels need dc frames be sent before
3424                          * waking panel.
3425                          */
3426                         if (dsi->info.panel_send_dc_frames)
3427                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3428
3429                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3430                                                         dsi->info.dsi_init_cmd,
3431                                                         dsi->info.n_init_cmd);
3432                         if (err < 0) {
3433                                 dev_err(&dc->ndev->dev,
3434                                 "dsi: error sending dsi init cmd\n");
3435                                 goto fail;
3436                         }
3437                 } else if (dsi->info.dsi_late_resume_cmd) {
3438                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3439                                                 dsi->info.dsi_late_resume_cmd,
3440                                                 dsi->info.n_late_resume_cmd);
3441                         if (err < 0) {
3442                                 dev_err(&dc->ndev->dev,
3443                                 "dsi: error sending late resume cmd\n");
3444                                 goto fail;
3445                         }
3446                 }
3447         } else {
3448                 err = tegra_dsi_init_hw(dc, dsi);
3449                 if (err < 0) {
3450                         dev_err(&dc->ndev->dev,
3451                                 "dsi: not able to init dsi hardware\n");
3452                         goto fail;
3453                 }
3454
3455                 if (dsi->ulpm) {
3456                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3457                                 dev_err(&dc->ndev->dev,
3458                                         "DSI failed to enter ulpm\n");
3459                                 goto fail;
3460                         }
3461
3462                         tegra_dsi_pad_enable(dsi);
3463
3464                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3465                                 dev_err(&dc->ndev->dev,
3466                                         "DSI failed to exit ulpm\n");
3467                                 goto fail;
3468                         }
3469                 }
3470
3471                 /*
3472                  * Certain panels need dc frames be sent before
3473                  * waking panel.
3474                  */
3475                 if (dsi->info.panel_send_dc_frames)
3476                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3477
3478                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3479                 if (err < 0) {
3480                         dev_err(&dc->ndev->dev,
3481                                 "dsi: not able to set to lp mode\n");
3482                         goto fail;
3483                 }
3484
3485                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3486                                                 dsi->info.n_init_cmd);
3487                 if (err < 0) {
3488                         dev_err(&dc->ndev->dev,
3489                                 "dsi: error while sending dsi init cmd\n");
3490                         goto fail;
3491                 }
3492
3493                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3494                                 TEGRA_DSI_DRIVEN_BY_DC);
3495                 if (err < 0) {
3496                         dev_err(&dc->ndev->dev,
3497                                 "dsi: not able to set to hs mode\n");
3498                         goto fail;
3499                 }
3500
3501                 dsi->enabled = true;
3502         }
3503
3504         if (dsi->out_ops && dsi->out_ops->enable)
3505                 dsi->out_ops->enable(dsi);
3506
3507         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3508                 tegra_dsi_start_dc_stream(dc, dsi);
3509
3510         dsi->host_suspended = false;
3511 fail:
3512         tegra_dc_io_end(dc);
3513         mutex_unlock(&dsi->lock);
3514 }
3515
3516 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3517 {
3518         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3519
3520         tegra_dc_dsi_debug_create(dsi);
3521
3522         if (dsi->info.dsi2lvds_bridge_enable)
3523                 dsi->out_ops = &tegra_dsi2lvds_ops;
3524         else if (dsi->info.dsi2edp_bridge_enable)
3525                 dsi->out_ops = &tegra_dsi2edp_ops;
3526         else
3527                 dsi->out_ops = NULL;
3528
3529         if (dsi->out_ops && dsi->out_ops->init)
3530                 dsi->out_ops->init(dsi);
3531
3532         tegra_dsi_init_sw(dc, dsi);
3533 }
3534
3535 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3536                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3537 {
3538         u16 i;
3539         u16 len;
3540
3541         memcpy(dst, src, sizeof(*dst) * n_cmd);
3542
3543         for (i = 0; i < n_cmd; i++)
3544                 if (src[i].pdata) {
3545                         len = sizeof(*src[i].pdata) *
3546                                         src[i].sp_len_dly.data_len;
3547                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3548                         if (!dst[i].pdata)
3549                                 goto free_cmd_pdata;
3550                         memcpy(dst[i].pdata, src[i].pdata, len);
3551                 }
3552
3553         return 0;
3554
3555 free_cmd_pdata:
3556         while (i--)
3557                 if (dst[i].pdata)
3558                         kfree(dst[i].pdata);
3559         return -ENOMEM;
3560 }
3561
3562 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi,
3563                                         struct tegra_dsi_out *p_dsi)
3564 {
3565         struct tegra_dsi_cmd *p_init_cmd;
3566         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3567         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3568         struct tegra_dsi_cmd *p_suspend_cmd;
3569         int err;
3570
3571         if (p_dsi->n_data_lanes > MAX_DSI_DATA_LANES)
3572                 return -EINVAL;
3573
3574         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3575                                 p_dsi->n_init_cmd, GFP_KERNEL);
3576         if (!p_init_cmd)
3577                 return -ENOMEM;
3578
3579         if (p_dsi->dsi_early_suspend_cmd) {
3580                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3581                                         p_dsi->n_early_suspend_cmd,
3582                                         GFP_KERNEL);
3583                 if (!p_early_suspend_cmd) {
3584                         err = -ENOMEM;
3585                         goto err_free_init_cmd;
3586                 }
3587         }
3588
3589         if (p_dsi->dsi_late_resume_cmd) {
3590                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3591                                         p_dsi->n_late_resume_cmd,
3592                                         GFP_KERNEL);
3593                 if (!p_late_resume_cmd) {
3594                         err = -ENOMEM;
3595                         goto err_free_p_early_suspend_cmd;
3596                 }
3597         }
3598
3599         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3600                                 GFP_KERNEL);
3601         if (!p_suspend_cmd) {
3602                 err = -ENOMEM;
3603                 goto err_free_p_late_resume_cmd;
3604         }
3605
3606         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3607
3608         /* Copy panel init cmd */
3609         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3610                                                 p_init_cmd, p_dsi->n_init_cmd);
3611         if (err < 0)
3612                 goto err_free;
3613         dsi->info.dsi_init_cmd = p_init_cmd;
3614
3615         /* Copy panel early suspend cmd */
3616         if (p_dsi->dsi_early_suspend_cmd) {
3617                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3618                                         p_early_suspend_cmd,
3619                                         p_dsi->n_early_suspend_cmd);
3620                 if (err < 0)
3621                         goto err_free;
3622                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3623         }
3624
3625         /* Copy panel late resume cmd */
3626         if (p_dsi->dsi_late_resume_cmd) {
3627                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3628                                                 p_late_resume_cmd,
3629                                                 p_dsi->n_late_resume_cmd);
3630                 if (err < 0)
3631                         goto err_free;
3632                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3633         }
3634
3635         /* Copy panel suspend cmd */
3636         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3637                                         p_dsi->n_suspend_cmd);
3638         if (err < 0)
3639                 goto err_free;
3640         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3641
3642         if (!dsi->info.panel_reset_timeout_msec)
3643                 dsi->info.panel_reset_timeout_msec =
3644                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3645
3646         if (!dsi->info.panel_buffer_size_byte)
3647                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3648
3649         if (!dsi->info.max_panel_freq_khz) {
3650                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3651
3652                 if (dsi->info.video_burst_mode >
3653                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3654                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3655                                         "is not set for DSI burst mode.\n");
3656                         dsi->info.video_burst_mode =
3657                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3658                 }
3659         }
3660
3661         if (!dsi->info.lp_cmd_mode_freq_khz)
3662                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3663
3664         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3665                 dev_warn(&dsi->dc->ndev->dev,
3666                         "DSI: Failed to get chip info\n");
3667
3668         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3669                 dsi->info.lp_read_cmd_mode_freq_khz =
3670                         dsi->info.lp_cmd_mode_freq_khz;
3671
3672         /* host mode is for testing only */
3673         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3674         return 0;
3675
3676 err_free:
3677         kfree(p_suspend_cmd);
3678 err_free_p_late_resume_cmd:
3679         kfree(p_late_resume_cmd);
3680 err_free_p_early_suspend_cmd:
3681         kfree(p_early_suspend_cmd);
3682 err_free_init_cmd:
3683         kfree(p_init_cmd);
3684         return err;
3685 }
3686
3687 /* returns next null enumeration from  tegra_dsi_instance */
3688 static inline int tegra_dsi_get_enumeration(void)
3689 {
3690         int i = 0;
3691         for (; i < MAX_DSI_INSTANCE; i++) {
3692                 if (!tegra_dsi_instance[i])
3693                         return i;
3694         }
3695         return -EINVAL;
3696 }
3697
3698 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3699 {
3700         struct tegra_dc_dsi_data *dsi;
3701         struct resource *res;
3702         struct resource *base_res;
3703         void __iomem *base;
3704         struct clk *dc_clk = NULL;
3705         struct clk *dsi_clk = NULL;
3706         struct clk *dsi_fixed_clk = NULL;
3707         struct tegra_dsi_out *dsi_pdata;
3708         int err = 0;
3709         int dsi_enum = -1;
3710
3711         if (dc->pdata->default_out->dsi->dsi_instance)
3712                 dsi_enum = 1;
3713         else
3714                 dsi_enum = tegra_dsi_get_enumeration();
3715         if (dsi_enum < 0) {
3716                 err = -EINVAL;
3717                 dev_err(&dc->ndev->dev, "dsi: invalid enum retured\n");
3718                 return err;
3719         }
3720
3721         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3722         if (!dsi) {
3723                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3724                 return -ENOMEM;
3725         }
3726         tegra_dsi_instance[dsi_enum] = dsi;
3727
3728         if (dc->out->dsi->ganged_type) {
3729                 if (dsi_enum)
3730                         res = platform_get_resource_byname(dc->ndev,
3731                                                 IORESOURCE_MEM,
3732                                                 "ganged_dsib_regs");
3733                 else
3734                         res = platform_get_resource_byname(dc->ndev,
3735                                                 IORESOURCE_MEM,
3736                                                 "ganged_dsia_regs");
3737         } else {
3738                 res = platform_get_resource_byname(dc->ndev,
3739                                         IORESOURCE_MEM,
3740                                         "dsi_regs");
3741         }
3742
3743         if (!res) {
3744                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3745                 err = -ENOENT;
3746                 goto err_free_dsi;
3747         }
3748
3749         base_res = request_mem_region(res->start, resource_size(res),
3750                                 dc->ndev->name);
3751         if (!base_res) {
3752                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3753                 err = -EBUSY;
3754                 goto err_free_dsi;
3755         }
3756
3757         base = ioremap(res->start, resource_size(res));
3758         if (!base) {
3759                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3760                 err = -EBUSY;
3761                 goto err_release_regs;
3762         }
3763
3764         dsi_pdata = dc->pdata->default_out->dsi;
3765         if (!dsi_pdata) {
3766                 dev_err(&dc->ndev->dev, "dsi: dsi data not available\n");
3767                 goto err_release_regs;
3768         }
3769
3770         if (dsi_enum)
3771                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3772         else
3773                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
3774
3775         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
3776
3777         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
3778                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
3779                 err = -EBUSY;
3780                 goto err_release_regs;
3781         }
3782
3783         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
3784         if (IS_ERR_OR_NULL(dc_clk)) {
3785                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
3786                         dev_name(&dc->ndev->dev));
3787                 err = -EBUSY;
3788                 goto err_dsi_clk_put;
3789         }
3790
3791         mutex_init(&dsi->lock);
3792         dsi->controller_index = dsi_enum;
3793         dsi->dc = dc;
3794         dsi->base = base;
3795         dsi->base_res = base_res;
3796         dsi->dc_clk = dc_clk;
3797         dsi->dsi_clk = dsi_clk;
3798         dsi->dsi_fixed_clk = dsi_fixed_clk;
3799
3800         err = tegra_dc_dsi_cp_info(dsi, dsi_pdata);
3801         if (err < 0)
3802                 goto err_dc_clk_put;
3803
3804         tegra_dc_set_outdata(dc, dsi);
3805         __tegra_dc_dsi_init(dc);
3806
3807         return 0;
3808
3809 err_dc_clk_put:
3810         clk_put(dc_clk);
3811 err_dsi_clk_put:
3812         clk_put(dsi_clk);
3813         clk_put(dsi_fixed_clk);
3814 err_release_regs:
3815         release_resource(base_res);
3816 err_free_dsi:
3817         kfree(dsi);
3818
3819         return err;
3820 }
3821
3822 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
3823 {
3824         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3825         u16 i;
3826         u32 val;
3827
3828         mutex_lock(&dsi->lock);
3829
3830         if (dsi->out_ops && dsi->out_ops->destroy)
3831                 dsi->out_ops->destroy(dsi);
3832
3833         /* free up the pdata */
3834         for (i = 0; i < dsi->info.n_init_cmd; i++) {
3835                 if (dsi->info.dsi_init_cmd[i].pdata)
3836                         kfree(dsi->info.dsi_init_cmd[i].pdata);
3837         }
3838         kfree(dsi->info.dsi_init_cmd);
3839
3840         /* Disable dc stream */
3841         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
3842                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3843
3844         /* Disable dsi phy clock */
3845         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
3846                 tegra_dsi_hs_clk_out_disable(dc, dsi);
3847
3848         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3849         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3850
3851         iounmap(dsi->base);
3852         release_resource(dsi->base_res);
3853
3854         clk_put(dsi->dc_clk);
3855         clk_put(dsi->dsi_clk);
3856
3857         mutex_unlock(&dsi->lock);
3858
3859         mutex_destroy(&dsi->lock);
3860         kfree(dsi);
3861 }
3862
3863 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
3864                                                         u32 settings)
3865 {
3866         struct clk *parent_clk = NULL;
3867         struct clk *base_clk = NULL;
3868
3869         parent_clk = clk_get_parent(dsi->dsi_clk);
3870         base_clk = clk_get_parent(parent_clk);
3871 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3872         if (dsi->info.dsi_instance)
3873                 tegra_clk_cfg_ex(base_clk,
3874                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
3875                                 settings);
3876         else
3877                 tegra_clk_cfg_ex(base_clk,
3878                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
3879                                 settings);
3880 #else
3881         tegra_clk_cfg_ex(base_clk,
3882                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
3883                         settings);
3884 #endif
3885 }
3886
3887 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
3888                                         struct tegra_dc_dsi_data *dsi,
3889                                         u32 suspend_aggr)
3890 {
3891         u32 val = 0;
3892         int err = 0;
3893
3894         switch (suspend_aggr) {
3895         case DSI_HOST_SUSPEND_LV2:
3896                 if (!dsi->ulpm) {
3897                         err = tegra_dsi_enter_ulpm(dsi);
3898                         if (err < 0) {
3899                                 dev_err(&dc->ndev->dev,
3900                                         "DSI failed to enter ulpm\n");
3901                                 goto fail;
3902                         }
3903                 }
3904
3905                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3906                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3907                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3908                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1);
3909                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3910
3911                 /* Suspend core-logic */
3912                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
3913                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
3914                 /* fall through */
3915         case DSI_HOST_SUSPEND_LV1:
3916                 /* Disable dsi fast and slow clock */
3917                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
3918                 /* fall through */
3919         case DSI_HOST_SUSPEND_LV0:
3920                 /* Disable dsi source clock */
3921                 tegra_dsi_clk_disable(dsi);
3922                 break;
3923         case DSI_NO_SUSPEND:
3924                 break;
3925         default:
3926                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
3927                                                 "is not supported.\n");
3928         }
3929
3930         return 0;
3931 fail:
3932         return err;
3933 }
3934
3935 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
3936                                         struct tegra_dc_dsi_data *dsi,
3937                                         u32 suspend_aggr)
3938 {
3939         u32 val;
3940         int err;
3941
3942         switch (dsi->info.suspend_aggr) {
3943         case DSI_HOST_SUSPEND_LV0:
3944                 tegra_dsi_clk_enable(dsi);
3945                 break;
3946         case DSI_HOST_SUSPEND_LV1:
3947                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3948                 tegra_dsi_clk_enable(dsi);
3949                 break;
3950         case DSI_HOST_SUSPEND_LV2:
3951                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
3952                 tegra_dsi_clk_enable(dsi);
3953
3954                 tegra_dsi_writel(dsi,
3955                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
3956                         DSI_POWER_CONTROL);
3957
3958                 if (dsi->ulpm) {
3959                         err = tegra_dsi_enter_ulpm(dsi);
3960                         if (err < 0) {
3961                                 dev_err(&dc->ndev->dev,
3962                                         "DSI failed to enter ulpm\n");
3963                                 goto fail;
3964                         }
3965
3966                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
3967                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
3968                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
3969                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
3970                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
3971
3972                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3973                                 dev_err(&dc->ndev->dev,
3974                                         "DSI failed to exit ulpm\n");
3975                                 goto fail;
3976                         }
3977                 }
3978                 break;
3979         case DSI_NO_SUSPEND:
3980                 break;
3981         default:
3982                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
3983                                                 "is not supported.\n");
3984         }
3985
3986         return 0;
3987 fail:
3988         return err;
3989 }
3990
3991 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
3992 {
3993         int err = 0;
3994         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3995
3996         if (!dsi->enabled)
3997                 return -EINVAL;
3998
3999         if (dsi->host_suspended)
4000                 return 0;
4001
4002         mutex_lock(&dsi->host_lock);
4003         tegra_dc_io_start(dc);
4004         dsi->host_suspended = true;
4005
4006         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4007
4008         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4009         if (err < 0)
4010                 dev_err(&dc->ndev->dev,
4011                         "DSI host suspend failed\n");
4012
4013         tegra_dc_io_end(dc);
4014         mutex_unlock(&dsi->host_lock);
4015         return err;
4016 }
4017
4018 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
4019                                 struct tegra_dc_dsi_data *dsi)
4020 {
4021         int val = 0;
4022         int err = 0;
4023
4024         if (!dsi->enabled)
4025                 return 0;
4026
4027         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4028         if (err < 0) {
4029                 dev_err(&dc->ndev->dev,
4030                 "DSI failed to go to LP mode\n");
4031                 goto fail;
4032         }
4033
4034         /* Suspend DSI panel */
4035         err = tegra_dsi_send_panel_cmd(dc, dsi,
4036                         dsi->info.dsi_suspend_cmd,
4037                         dsi->info.n_suspend_cmd);
4038
4039         /*
4040          * Certain panels need dc frames be sent after
4041          * putting panel to sleep.
4042          */
4043         if (dsi->info.panel_send_dc_frames)
4044                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4045
4046         if (err < 0) {
4047                 dev_err(&dc->ndev->dev,
4048                         "dsi: Error sending suspend cmd\n");
4049                 goto fail;
4050         }
4051
4052         if (!dsi->ulpm) {
4053                 err = tegra_dsi_enter_ulpm(dsi);
4054                 if (err < 0) {
4055                         dev_err(&dc->ndev->dev,
4056                                 "DSI failed to enter ulpm\n");
4057                         goto fail;
4058                 }
4059         }
4060
4061         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
4062                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
4063                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
4064         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
4065
4066         /* Suspend core-logic */
4067         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4068         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4069
4070         /* Disable dsi fast and slow clock */
4071         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4072
4073         /* Disable dsi source clock */
4074         tegra_dsi_clk_disable(dsi);
4075
4076         regulator_disable(dsi->avdd_dsi_csi);
4077
4078         dsi->enabled = false;
4079         dsi->host_suspended = true;
4080
4081         return 0;
4082 fail:
4083         return err;
4084 }
4085
4086 static int tegra_dsi_host_resume(struct tegra_dc *dc)
4087 {
4088         int err = 0;
4089         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4090
4091         if (!dsi->enabled)
4092                 return -EINVAL;
4093
4094         mutex_lock(&dsi->host_lock);
4095         cancel_delayed_work_sync(&dsi->idle_work);
4096         if (!dsi->host_suspended) {
4097                 mutex_unlock(&dsi->host_lock);
4098                 return 0;
4099         }
4100
4101         tegra_dc_io_start(dc);
4102
4103         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
4104         if (err < 0) {
4105                 dev_err(&dc->ndev->dev,
4106                         "DSI host resume failed\n");
4107                 goto fail;
4108         }
4109
4110         tegra_dsi_start_dc_stream(dc, dsi);
4111         dsi->host_suspended = false;
4112 fail:
4113         tegra_dc_io_end(dc);
4114         mutex_unlock(&dsi->host_lock);
4115         return err;
4116 }
4117
4118 static void _tegra_dc_dsi_disable(struct tegra_dc *dc)
4119 {
4120         int err;
4121         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4122
4123         if (dsi->host_suspended)
4124                 tegra_dsi_host_resume(dc);
4125
4126         mutex_lock(&dsi->lock);
4127         tegra_dc_io_start(dc);
4128
4129         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4130                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4131
4132         if (dsi->out_ops && dsi->out_ops->disable)
4133                 dsi->out_ops->disable(dsi);
4134
4135         if (dsi->info.power_saving_suspend) {
4136                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4137                         dev_err(&dc->ndev->dev,
4138                                 "DSI failed to enter deep sleep\n");
4139                         goto fail;
4140                 }
4141         } else {
4142                 if (dsi->info.dsi_early_suspend_cmd) {
4143                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4144                                 dsi->info.dsi_early_suspend_cmd,
4145                                 dsi->info.n_early_suspend_cmd);
4146                         if (err < 0) {
4147                                 dev_err(&dc->ndev->dev,
4148                                 "dsi: Error sending early suspend cmd\n");
4149                                 goto fail;
4150                         }
4151                 }
4152
4153                 if (!dsi->ulpm) {
4154                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4155                                 dev_err(&dc->ndev->dev,
4156                                         "DSI failed to enter ulpm\n");
4157                                 goto fail;
4158                         }
4159                 }
4160         }
4161 fail:
4162         mutex_unlock(&dsi->lock);
4163         tegra_dc_io_end(dc);
4164 }
4165
4166 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4167 {
4168         _tegra_dc_dsi_disable(dc);
4169
4170         if (dc->out->dsi->ganged_type) {
4171                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4172                 _tegra_dc_dsi_disable(dc);
4173                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4174         }
4175 }
4176
4177
4178 #ifdef CONFIG_PM
4179 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
4180 {
4181         struct tegra_dc_dsi_data *dsi;
4182
4183         dsi = tegra_dc_get_outdata(dc);
4184
4185         if (!dsi->enabled)
4186                 return;
4187
4188         if (dsi->host_suspended)
4189                 tegra_dsi_host_resume(dc);
4190
4191         tegra_dc_io_start(dc);
4192         mutex_lock(&dsi->lock);
4193
4194         if (dsi->out_ops && dsi->out_ops->suspend)
4195                 dsi->out_ops->suspend(dsi);
4196
4197         if (!dsi->info.power_saving_suspend) {
4198                 if (dsi->ulpm) {
4199                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4200                                 dev_err(&dc->ndev->dev,
4201                                         "DSI failed to exit ulpm");
4202                                 goto fail;
4203                         }
4204                 }
4205
4206                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4207                         dev_err(&dc->ndev->dev,
4208                                 "DSI failed to enter deep sleep\n");
4209                         goto fail;
4210                 }
4211         }
4212 fail:
4213         mutex_unlock(&dsi->lock);
4214         tegra_dc_io_end(dc);
4215 }
4216
4217 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
4218 {
4219         struct tegra_dc_dsi_data *dsi;
4220
4221         dsi = tegra_dc_get_outdata(dc);
4222
4223         /* No dsi config required since tegra_dc_dsi_enable
4224          * will reconfigure the controller from scratch
4225          */
4226
4227          if (dsi->out_ops && dsi->out_ops->resume)
4228                 dsi->out_ops->resume(dsi);
4229 }
4230
4231 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4232 {
4233         _tegra_dc_dsi_suspend(dc);
4234
4235         if (dc->out->dsi->ganged_type) {
4236                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4237                 _tegra_dc_dsi_suspend(dc);
4238                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4239         }
4240 }
4241
4242 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
4243 {
4244         _tegra_dc_dsi_resume(dc);
4245
4246         if (dc->out->dsi->ganged_type) {
4247                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4248                 _tegra_dc_dsi_resume(dc);
4249                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4250         }
4251 }
4252 #endif
4253
4254 static int tegra_dc_dsi_init(struct tegra_dc *dc)
4255 {
4256         struct tegra_dc_dsi_data *dsi;
4257         int err = 0;
4258
4259         err = _tegra_dc_dsi_init(dc);
4260         if (err < 0) {
4261                 dev_err(&dc->ndev->dev,
4262                         "dsi: Instance A init failed\n");
4263                 goto err;
4264         }
4265
4266         dsi = tegra_dc_get_outdata(dc);
4267
4268         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
4269         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
4270                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
4271                 err = PTR_ERR(dsi->avdd_dsi_csi);
4272                 goto err_reg;
4273         }
4274
4275         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
4276         if (IS_ERR(dsi->mipi_cal)) {
4277                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
4278                 err = PTR_ERR(dsi->mipi_cal);
4279                 goto err_mipi;
4280         }
4281
4282         if (dc->out->dsi->ganged_type) {
4283                 err = _tegra_dc_dsi_init(dc);
4284                 if (err < 0) {
4285                         dev_err(&dc->ndev->dev,
4286                                 "dsi: Instance B init failed\n");
4287                         goto err_ganged;
4288                 }
4289                 tegra_dsi_instance[DSI_INSTANCE_1]->avdd_dsi_csi =
4290                                                         dsi->avdd_dsi_csi;
4291                 tegra_dsi_instance[DSI_INSTANCE_1]->mipi_cal =
4292                                                         dsi->mipi_cal;
4293                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4294         }
4295         return 0;
4296 err_ganged:
4297         tegra_mipi_cal_destroy(dc);
4298 err_mipi:
4299         regulator_put(dsi->avdd_dsi_csi);
4300 err_reg:
4301         _tegra_dc_dsi_destroy(dc);
4302 err:
4303         return err;
4304 }
4305
4306 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4307 {
4308         struct regulator *avdd_dsi_csi;
4309         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4310
4311         avdd_dsi_csi = dsi->avdd_dsi_csi;
4312
4313         _tegra_dc_dsi_destroy(dc);
4314
4315         if (dc->out->dsi->ganged_type) {
4316                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4317                 _tegra_dc_dsi_destroy(dc);
4318                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4319         }
4320
4321         regulator_put(avdd_dsi_csi);
4322         tegra_mipi_cal_destroy(dc);
4323 }
4324
4325 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4326 {
4327         _tegra_dc_dsi_enable(dc);
4328
4329         if (dc->out->dsi->ganged_type) {
4330                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4331                 _tegra_dc_dsi_enable(dc);
4332                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4333         }
4334 }
4335
4336 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
4337 {
4338         unsigned long rate;
4339         struct clk *parent_clk;
4340         struct clk *base_clk;
4341         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4342
4343         /* divide by 1000 to avoid overflow */
4344         dc->mode.pclk /= 1000;
4345         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
4346                                 / dc->shift_clk_div.div;
4347         rate *= 1000;
4348         dc->mode.pclk *= 1000;
4349
4350         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
4351                 goto skip_setup;
4352
4353         if (clk == dc->clk) {
4354                 parent_clk = clk_get_sys(NULL,
4355                                 dc->out->parent_clk ? : "pll_d_out0");
4356                 base_clk = clk_get_parent(parent_clk);
4357         } else {
4358                 if (dc->pdata->default_out->dsi->dsi_instance) {
4359                         parent_clk = clk_get_sys(NULL,
4360                                 dc->out->parent_clk ? : "pll_d2_out0");
4361                         base_clk = clk_get_parent(parent_clk);
4362                 } else {
4363                         parent_clk = clk_get_sys(NULL,
4364                                 dc->out->parent_clk ? : "pll_d_out0");
4365                         base_clk = clk_get_parent(parent_clk);
4366                 }
4367         }
4368         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4369
4370         if (rate != clk_get_rate(base_clk))
4371                 clk_set_rate(base_clk, rate);
4372
4373         if (clk_get_parent(clk) != parent_clk)
4374                 clk_set_parent(clk, parent_clk);
4375
4376 skip_setup:
4377         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4378
4379         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
4380 }
4381
4382 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4383         .init = tegra_dc_dsi_init,
4384         .destroy = tegra_dc_dsi_destroy,
4385         .enable = tegra_dc_dsi_enable,
4386         .disable = tegra_dc_dsi_disable,
4387         .hold = tegra_dc_dsi_hold_host,
4388         .release = tegra_dc_dsi_release_host,
4389 #ifdef CONFIG_PM
4390         .suspend = tegra_dc_dsi_suspend,
4391         .resume = tegra_dc_dsi_resume,
4392 #endif
4393         .setup_clk = tegra_dc_dsi_setup_clk,
4394 };