video: tegra: bitness sanitary cleanup
[linux-3.10.git] / drivers / video / tegra / dc / dsi.c
1 /*
2  * drivers/video/tegra/dc/dsi.c
3  *
4  * Copyright (c) 2011-2013, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/kernel.h>
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
21 #include <linux/fb.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/slab.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27 #include <linux/moduleparam.h>
28 #include <linux/export.h>
29 #include <linux/debugfs.h>
30 #include <linux/seq_file.h>
31 #include <linux/nvhost.h>
32 #include <linux/lcm.h>
33 #include <linux/of_address.h>
34 #include <linux/of_gpio.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
37
38 #include <mach/clk.h>
39 #include <mach/dc.h>
40 #include <mach/fb.h>
41 #include <mach/csi.h>
42 #include <linux/nvhost.h>
43
44 #include "dc_reg.h"
45 #include "dc_priv.h"
46 #include "dev.h"
47 #include "dsi_regs.h"
48 #include "dsi.h"
49 #include "mipi_cal.h"
50
51 /* HACK! This needs to come from DT */
52 #include "../../../../arch/arm/mach-tegra/iomap.h"
53
54 #define APB_MISC_GP_MIPI_PAD_CTRL_0     (TEGRA_APB_MISC_BASE + 0x820)
55 #define DSIB_MODE_ENABLE                0x2
56
57 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
58 #define DSI_USE_SYNC_POINTS 0
59 #else
60 #define DSI_USE_SYNC_POINTS 1
61 #endif
62
63 #define S_TO_MS(x)                      (1000 * (x))
64 #define MS_TO_US(x)                     (1000 * (x))
65
66 #define DSI_MODULE_NOT_INIT             0x0
67 #define DSI_MODULE_INIT                 0x1
68
69 #define DSI_LPHS_NOT_INIT               0x0
70 #define DSI_LPHS_IN_LP_MODE             0x1
71 #define DSI_LPHS_IN_HS_MODE             0x2
72
73 #define DSI_VIDEO_TYPE_NOT_INIT         0x0
74 #define DSI_VIDEO_TYPE_VIDEO_MODE       0x1
75 #define DSI_VIDEO_TYPE_CMD_MODE         0x2
76
77 #define DSI_DRIVEN_MODE_NOT_INIT        0x0
78 #define DSI_DRIVEN_MODE_DC              0x1
79 #define DSI_DRIVEN_MODE_HOST            0x2
80
81 #define DSI_PHYCLK_OUT_DIS              0x0
82 #define DSI_PHYCLK_OUT_EN               0x1
83
84 #define DSI_PHYCLK_NOT_INIT             0x0
85 #define DSI_PHYCLK_CONTINUOUS           0x1
86 #define DSI_PHYCLK_TX_ONLY              0x2
87
88 #define DSI_CLK_BURST_NOT_INIT          0x0
89 #define DSI_CLK_BURST_NONE_BURST        0x1
90 #define DSI_CLK_BURST_BURST_MODE        0x2
91
92 #define DSI_DC_STREAM_DISABLE           0x0
93 #define DSI_DC_STREAM_ENABLE            0x1
94
95 #define DSI_LP_OP_NOT_INIT              0x0
96 #define DSI_LP_OP_WRITE                 0x1
97 #define DSI_LP_OP_READ                  0x2
98
99 #define DSI_HOST_IDLE_PERIOD            1000
100 #if DSI_USE_SYNC_POINTS
101 static atomic_t dsi_syncpt_rst = ATOMIC_INIT(0);
102 #endif
103
104 static bool enable_read_debug;
105 module_param(enable_read_debug, bool, 0644);
106 MODULE_PARM_DESC(enable_read_debug,
107                 "Enable to print read fifo and return packet type");
108
109 /* source of video data */
110 enum {
111         TEGRA_DSI_DRIVEN_BY_DC,
112         TEGRA_DSI_DRIVEN_BY_HOST,
113 };
114
115 static struct tegra_dc_dsi_data *tegra_dsi_instance[MAX_DSI_INSTANCE];
116
117 const u32 dsi_pkt_seq_reg[NUMOF_PKT_SEQ] = {
118         DSI_PKT_SEQ_0_LO,
119         DSI_PKT_SEQ_0_HI,
120         DSI_PKT_SEQ_1_LO,
121         DSI_PKT_SEQ_1_HI,
122         DSI_PKT_SEQ_2_LO,
123         DSI_PKT_SEQ_2_HI,
124         DSI_PKT_SEQ_3_LO,
125         DSI_PKT_SEQ_3_HI,
126         DSI_PKT_SEQ_4_LO,
127         DSI_PKT_SEQ_4_HI,
128         DSI_PKT_SEQ_5_LO,
129         DSI_PKT_SEQ_5_HI,
130 };
131
132 const u32 dsi_pkt_seq_video_non_burst_syne[NUMOF_PKT_SEQ] = {
133         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
134         0,
135         PKT_ID0(CMD_VE) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
136         0,
137         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
138         0,
139         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
140         PKT_ID2(CMD_HE) | PKT_LEN2(0),
141         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
142         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
143         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
144         0,
145         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(1) |
146         PKT_ID2(CMD_HE) | PKT_LEN2(0),
147         PKT_ID3(CMD_BLNK) | PKT_LEN3(2) | PKT_ID4(CMD_RGB) | PKT_LEN4(3) |
148         PKT_ID5(CMD_BLNK) | PKT_LEN5(4),
149 };
150
151 const u32 dsi_pkt_seq_video_non_burst[NUMOF_PKT_SEQ] = {
152         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
153         0,
154         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
155         0,
156         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
157         0,
158         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
159         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
160         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
161         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
162         0,
163         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
164         PKT_ID2(CMD_RGB) | PKT_LEN2(3),
165         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
166 };
167
168 const u32 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp[NUMOF_PKT_SEQ] = {
169         PKT_ID0(CMD_VS) | PKT_LEN0(0),
170         0,
171         PKT_ID0(CMD_HS) | PKT_LEN0(0),
172         0,
173         PKT_ID0(CMD_HS) | PKT_LEN0(0),
174         0,
175         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
176         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
177         0,
178         PKT_ID0(CMD_HS) | PKT_LEN0(0),
179         0,
180         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_RGB) | PKT_LEN1(3) |
181         PKT_ID2(CMD_BLNK) | PKT_LEN2(4),
182         0,
183 };
184
185 static const u32 dsi_pkt_seq_video_burst[NUMOF_PKT_SEQ] = {
186         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
187         0,
188         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
189         0,
190         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
191         0,
192         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
193         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
194         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
195         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_EOT) | PKT_LEN1(7) | PKT_LP,
196         0,
197         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
198         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
199         PKT_ID0(CMD_EOT) | PKT_LEN0(7),
200 };
201
202 static const u32 dsi_pkt_seq_video_burst_no_eot[NUMOF_PKT_SEQ] = {
203         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
204         0,
205         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
206         0,
207         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
208         0,
209         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
210         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
211         0,
212         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
213         0,
214         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2)|
215         PKT_ID2(CMD_RGB) | PKT_LEN2(3) | PKT_LP,
216         0,
217 };
218
219 const u32 dsi_pkt_seq_video_non_burst_no_eot[NUMOF_PKT_SEQ] = {
220         PKT_ID0(CMD_VS) | PKT_LEN0(0) | PKT_LP,
221         0,
222         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
223         0,
224         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
225         0,
226         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
227                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
228         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
229         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_LP,
230         0,
231         PKT_ID0(CMD_HS) | PKT_LEN0(0) | PKT_ID1(CMD_BLNK) | PKT_LEN1(2) |
232                 PKT_ID2(CMD_RGB) | PKT_LEN2(3),
233         PKT_ID3(CMD_BLNK) | PKT_LEN3(4),
234 };
235
236
237 /* TODO: verify with hw about this format */
238 const u32 dsi_pkt_seq_cmd_mode[NUMOF_PKT_SEQ] = {
239         0,
240         0,
241         0,
242         0,
243         0,
244         0,
245         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
246         0,
247         0,
248         0,
249         PKT_ID0(CMD_LONGW) | PKT_LEN0(3) | PKT_ID1(CMD_EOT) | PKT_LEN1(7),
250         0,
251 };
252
253 const u32 init_reg[] = {
254         DSI_INT_ENABLE,
255         DSI_INT_STATUS,
256         DSI_INT_MASK,
257         DSI_INIT_SEQ_DATA_0,
258         DSI_INIT_SEQ_DATA_1,
259         DSI_INIT_SEQ_DATA_2,
260         DSI_INIT_SEQ_DATA_3,
261         DSI_INIT_SEQ_DATA_4,
262         DSI_INIT_SEQ_DATA_5,
263         DSI_INIT_SEQ_DATA_6,
264         DSI_INIT_SEQ_DATA_7,
265         DSI_DCS_CMDS,
266         DSI_PKT_SEQ_0_LO,
267         DSI_PKT_SEQ_1_LO,
268         DSI_PKT_SEQ_2_LO,
269         DSI_PKT_SEQ_3_LO,
270         DSI_PKT_SEQ_4_LO,
271         DSI_PKT_SEQ_5_LO,
272         DSI_PKT_SEQ_0_HI,
273         DSI_PKT_SEQ_1_HI,
274         DSI_PKT_SEQ_2_HI,
275         DSI_PKT_SEQ_3_HI,
276         DSI_PKT_SEQ_4_HI,
277         DSI_PKT_SEQ_5_HI,
278         DSI_CONTROL,
279         DSI_HOST_DSI_CONTROL,
280         DSI_PAD_CONTROL,
281         DSI_PAD_CONTROL_CD,
282         DSI_SOL_DELAY,
283         DSI_MAX_THRESHOLD,
284         DSI_TRIGGER,
285         DSI_TX_CRC,
286         DSI_INIT_SEQ_CONTROL,
287         DSI_PKT_LEN_0_1,
288         DSI_PKT_LEN_2_3,
289         DSI_PKT_LEN_4_5,
290         DSI_PKT_LEN_6_7,
291 };
292
293 const u32 init_reg_vs1_ext[] = {
294         DSI_PAD_CONTROL_0_VS1,
295         DSI_PAD_CONTROL_CD_VS1,
296         DSI_PAD_CD_STATUS_VS1,
297         DSI_PAD_CONTROL_1_VS1,
298         DSI_PAD_CONTROL_2_VS1,
299         DSI_PAD_CONTROL_3_VS1,
300         DSI_PAD_CONTROL_4_VS1,
301         DSI_GANGED_MODE_CONTROL,
302         DSI_GANGED_MODE_START,
303         DSI_GANGED_MODE_SIZE,
304 };
305
306 static int tegra_dsi_host_suspend(struct tegra_dc *dc);
307 static int tegra_dsi_host_resume(struct tegra_dc *dc);
308 static void tegra_dc_dsi_idle_work(struct work_struct *work);
309 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
310                                      struct tegra_dc_dsi_data *dsi,
311                                      int no_of_frames);
312
313 inline unsigned long tegra_dsi_readl(struct tegra_dc_dsi_data *dsi, u32 reg)
314 {
315         unsigned long ret;
316
317         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
318         ret = readl(dsi->base + reg * 4);
319         trace_display_readl(dsi->dc, ret, dsi->base + reg * 4);
320         return ret;
321 }
322 EXPORT_SYMBOL(tegra_dsi_readl);
323
324 inline void tegra_dsi_writel(struct tegra_dc_dsi_data *dsi, u32 val, u32 reg)
325 {
326         BUG_ON(!nvhost_module_powered_ext(dsi->dc->ndev));
327         trace_display_writel(dsi->dc, val, dsi->base + reg * 4);
328         writel(val, dsi->base + reg * 4);
329 }
330 EXPORT_SYMBOL(tegra_dsi_writel);
331
332 #ifdef CONFIG_DEBUG_FS
333 static int dbg_dsi_show(struct seq_file *s, void *unused)
334 {
335         struct tegra_dc_dsi_data *dsi = s->private;
336
337 #define DUMP_REG(a) do {                                                \
338                 seq_printf(s, "%-32s\t%03x\t%08lx\n",                   \
339                        #a, a, tegra_dsi_readl(dsi, a));         \
340         } while (0)
341
342         tegra_dc_io_start(dsi->dc);
343         clk_prepare_enable(dsi->dsi_clk);
344
345         DUMP_REG(DSI_INCR_SYNCPT_CNTRL);
346         DUMP_REG(DSI_INCR_SYNCPT_ERROR);
347         DUMP_REG(DSI_CTXSW);
348         DUMP_REG(DSI_POWER_CONTROL);
349         DUMP_REG(DSI_INT_ENABLE);
350         DUMP_REG(DSI_HOST_DSI_CONTROL);
351         DUMP_REG(DSI_CONTROL);
352         DUMP_REG(DSI_SOL_DELAY);
353         DUMP_REG(DSI_MAX_THRESHOLD);
354         DUMP_REG(DSI_TRIGGER);
355         DUMP_REG(DSI_TX_CRC);
356         DUMP_REG(DSI_STATUS);
357         DUMP_REG(DSI_INIT_SEQ_CONTROL);
358         DUMP_REG(DSI_INIT_SEQ_DATA_0);
359         DUMP_REG(DSI_INIT_SEQ_DATA_1);
360         DUMP_REG(DSI_INIT_SEQ_DATA_2);
361         DUMP_REG(DSI_INIT_SEQ_DATA_3);
362         DUMP_REG(DSI_INIT_SEQ_DATA_4);
363         DUMP_REG(DSI_INIT_SEQ_DATA_5);
364         DUMP_REG(DSI_INIT_SEQ_DATA_6);
365         DUMP_REG(DSI_INIT_SEQ_DATA_7);
366         DUMP_REG(DSI_PKT_SEQ_0_LO);
367         DUMP_REG(DSI_PKT_SEQ_0_HI);
368         DUMP_REG(DSI_PKT_SEQ_1_LO);
369         DUMP_REG(DSI_PKT_SEQ_1_HI);
370         DUMP_REG(DSI_PKT_SEQ_2_LO);
371         DUMP_REG(DSI_PKT_SEQ_2_HI);
372         DUMP_REG(DSI_PKT_SEQ_3_LO);
373         DUMP_REG(DSI_PKT_SEQ_3_HI);
374         DUMP_REG(DSI_PKT_SEQ_4_LO);
375         DUMP_REG(DSI_PKT_SEQ_4_HI);
376         DUMP_REG(DSI_PKT_SEQ_5_LO);
377         DUMP_REG(DSI_PKT_SEQ_5_HI);
378         DUMP_REG(DSI_DCS_CMDS);
379         DUMP_REG(DSI_PKT_LEN_0_1);
380         DUMP_REG(DSI_PKT_LEN_2_3);
381         DUMP_REG(DSI_PKT_LEN_4_5);
382         DUMP_REG(DSI_PKT_LEN_6_7);
383         DUMP_REG(DSI_PHY_TIMING_0);
384         DUMP_REG(DSI_PHY_TIMING_1);
385         DUMP_REG(DSI_PHY_TIMING_2);
386         DUMP_REG(DSI_BTA_TIMING);
387         DUMP_REG(DSI_TIMEOUT_0);
388         DUMP_REG(DSI_TIMEOUT_1);
389         DUMP_REG(DSI_TO_TALLY);
390         DUMP_REG(DSI_PAD_CONTROL);
391         DUMP_REG(DSI_PAD_CONTROL_CD);
392         DUMP_REG(DSI_PAD_CD_STATUS);
393         DUMP_REG(DSI_VID_MODE_CONTROL);
394 #undef DUMP_REG
395
396         clk_disable_unprepare(dsi->dsi_clk);
397         tegra_dc_io_end(dsi->dc);
398
399         return 0;
400 }
401
402 static int dbg_dsi_open(struct inode *inode, struct file *file)
403 {
404         return single_open(file, dbg_dsi_show, inode->i_private);
405 }
406
407 static const struct file_operations dbg_fops = {
408         .open           = dbg_dsi_open,
409         .read           = seq_read,
410         .llseek         = seq_lseek,
411         .release        = single_release,
412 };
413
414 static struct dentry *dsidir;
415
416 static void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
417 {
418         struct dentry *retval;
419
420         dsidir = debugfs_create_dir("tegra_dsi", NULL);
421         if (!dsidir)
422                 return;
423         retval = debugfs_create_file("regs", S_IRUGO, dsidir, dsi,
424                 &dbg_fops);
425         if (!retval)
426                 goto free_out;
427         return;
428 free_out:
429         debugfs_remove_recursive(dsidir);
430         dsidir = NULL;
431         return;
432 }
433 #else
434 static inline void tegra_dc_dsi_debug_create(struct tegra_dc_dsi_data *dsi)
435 { }
436 #endif
437
438 static inline void tegra_dsi_clk_enable(struct tegra_dc_dsi_data *dsi)
439 {
440         if (!tegra_is_clk_enabled(dsi->dsi_clk))
441                 clk_prepare_enable(dsi->dsi_clk);
442 }
443
444 static inline void tegra_dsi_clk_disable(struct tegra_dc_dsi_data *dsi)
445 {
446         if (tegra_is_clk_enabled(dsi->dsi_clk))
447                 clk_disable_unprepare(dsi->dsi_clk);
448 }
449
450 static void __maybe_unused tegra_dsi_syncpt_reset(
451                                 struct tegra_dc_dsi_data *dsi)
452 {
453         tegra_dsi_writel(dsi, 0x1, DSI_INCR_SYNCPT_CNTRL);
454         /* stabilization delay */
455         udelay(300);
456         tegra_dsi_writel(dsi, 0x0, DSI_INCR_SYNCPT_CNTRL);
457         /* stabilization delay */
458         udelay(300);
459 }
460
461 static int __maybe_unused tegra_dsi_syncpt(struct tegra_dc_dsi_data *dsi)
462 {
463         u32 val;
464         int ret = 0;
465
466         dsi->syncpt_val = nvhost_syncpt_read_ext(dsi->dc->ndev, dsi->syncpt_id);
467
468         val = DSI_INCR_SYNCPT_COND(OP_DONE) |
469                 DSI_INCR_SYNCPT_INDX(dsi->syncpt_id);
470         tegra_dsi_writel(dsi, val, DSI_INCR_SYNCPT);
471
472         ret = nvhost_syncpt_wait_timeout_ext(dsi->dc->ndev, dsi->syncpt_id,
473                 dsi->syncpt_val + 1, (u32)MAX_SCHEDULE_TIMEOUT, NULL, NULL);
474         if (ret < 0) {
475                 dev_err(&dsi->dc->ndev->dev, "DSI sync point failure\n");
476                 goto fail;
477         }
478
479         (dsi->syncpt_val)++;
480         return 0;
481 fail:
482         return ret;
483 }
484
485 static u32 tegra_dsi_get_hs_clk_rate(struct tegra_dc_dsi_data *dsi)
486 {
487         u32 dsi_clock_rate_khz;
488
489         switch (dsi->info.video_burst_mode) {
490         case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
491         case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
492         case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
493         case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
494                 /* Calculate DSI HS clock rate for DSI burst mode */
495                 dsi_clock_rate_khz = dsi->default_pixel_clk_khz *
496                                         dsi->shift_clk_div.mul /
497                                         dsi->shift_clk_div.div;
498                 break;
499         case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
500         case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
501         case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
502         default:
503                 /* Clock rate is default DSI clock rate for non-burst mode */
504                 dsi_clock_rate_khz = dsi->default_hs_clk_khz;
505                 break;
506         }
507
508         return dsi_clock_rate_khz;
509 }
510
511 static u32 tegra_dsi_get_lp_clk_rate(struct tegra_dc_dsi_data *dsi, u8 lp_op)
512 {
513         u32 dsi_clock_rate_khz;
514
515         if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
516                 if (dsi->info.hs_clk_in_lp_cmd_mode_freq_khz)
517                         dsi_clock_rate_khz =
518                                 dsi->info.hs_clk_in_lp_cmd_mode_freq_khz;
519                 else
520                         dsi_clock_rate_khz = tegra_dsi_get_hs_clk_rate(dsi);
521         else
522                 if (lp_op == DSI_LP_OP_READ)
523                         dsi_clock_rate_khz =
524                                 dsi->info.lp_read_cmd_mode_freq_khz;
525                 else
526                         dsi_clock_rate_khz =
527                                 dsi->info.lp_cmd_mode_freq_khz;
528
529         return dsi_clock_rate_khz;
530 }
531
532 static struct tegra_dc_shift_clk_div tegra_dsi_get_shift_clk_div(
533                                                 struct tegra_dc_dsi_data *dsi)
534 {
535         struct tegra_dc_shift_clk_div shift_clk_div;
536         struct tegra_dc_shift_clk_div max_shift_clk_div;
537         u32 temp_lcm;
538         u32 burst_width;
539         u32 burst_width_max;
540
541         /* Get the real value of default shift_clk_div. default_shift_clk_div
542          * holds the real value of shift_clk_div.
543          */
544         shift_clk_div = dsi->default_shift_clk_div;
545
546         /* Calculate shift_clk_div which can match the video_burst_mode. */
547         if (dsi->info.video_burst_mode >=
548                         TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED) {
549                 if (dsi->info.max_panel_freq_khz >= dsi->default_hs_clk_khz) {
550                         /* formula:
551                          * dsi->info.max_panel_freq_khz * shift_clk_div /
552                          * dsi->default_hs_clk_khz
553                          */
554                         max_shift_clk_div.mul = dsi->info.max_panel_freq_khz *
555                                                 shift_clk_div.mul;
556                         max_shift_clk_div.div = dsi->default_hs_clk_khz *
557                                                 dsi->default_shift_clk_div.div;
558                 } else {
559                         max_shift_clk_div = shift_clk_div;
560                 }
561
562                 burst_width = dsi->info.video_burst_mode
563                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
564                 burst_width_max = TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED
565                                 - TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
566
567                 /* formula:
568                  * (max_shift_clk_div - shift_clk_div) *
569                  * burst_width / burst_width_max
570                  */
571                 temp_lcm = lcm(max_shift_clk_div.div, shift_clk_div.div);
572                 shift_clk_div.mul = (max_shift_clk_div.mul * temp_lcm /
573                                         max_shift_clk_div.div -
574                                         shift_clk_div.mul * temp_lcm /
575                                         shift_clk_div.div)*
576                                         burst_width;
577                 shift_clk_div.div = temp_lcm * burst_width_max;
578         }
579
580         return shift_clk_div;
581 }
582
583 static void tegra_dsi_pix_correction(struct tegra_dc *dc,
584                                         struct tegra_dc_dsi_data *dsi)
585 {
586         u32 h_width_pixels;
587         u32 h_act_corr = 0;
588         u32 hfp_corr = 0;
589         u32 temp = 0;
590
591         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
592                         dc->mode.h_sync_width + dc->mode.h_active;
593
594         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
595                 temp = dc->mode.h_active % dsi->info.n_data_lanes;
596                 if (temp) {
597                         h_act_corr = dsi->info.n_data_lanes - temp;
598                         h_width_pixels += h_act_corr;
599                 }
600         }
601
602         temp = h_width_pixels % dsi->info.n_data_lanes;
603         if (temp) {
604                 hfp_corr = dsi->info.n_data_lanes - temp;
605                 h_width_pixels += hfp_corr;
606         }
607
608         while (1) {
609                 temp = (h_width_pixels * dsi->pixel_scaler_mul /
610                         dsi->pixel_scaler_div) % dsi->info.n_data_lanes;
611                 if (temp) {
612                         hfp_corr += dsi->info.n_data_lanes;
613                         h_width_pixels += dsi->info.n_data_lanes;
614                 }
615                 else
616                         break;
617         }
618
619         dc->mode.h_front_porch += hfp_corr;
620         dc->mode.h_active += h_act_corr;
621 }
622
623 static void tegra_dsi_init_sw(struct tegra_dc *dc,
624                         struct tegra_dc_dsi_data *dsi)
625 {
626         u32 h_width_pixels;
627         u32 v_width_lines;
628         u32 pixel_clk_hz;
629         u32 byte_clk_hz;
630         u32 plld_clk_mhz;
631         u8 n_data_lanes;
632
633         switch (dsi->info.pixel_format) {
634         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
635                 /* 2 bytes per pixel */
636                 dsi->pixel_scaler_mul = 2;
637                 dsi->pixel_scaler_div = 1;
638                 break;
639         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
640                 /* 2.25 bytes per pixel */
641                 dsi->pixel_scaler_mul = 9;
642                 dsi->pixel_scaler_div = 4;
643                 break;
644         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
645         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
646                 /* 3 bytes per pixel */
647                 dsi->pixel_scaler_mul = 3;
648                 dsi->pixel_scaler_div = 1;
649                 break;
650         default:
651                 break;
652         }
653
654         dsi->ulpm = false;
655         dsi->enabled = false;
656         dsi->clk_ref = false;
657
658         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
659                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD)
660                 n_data_lanes = dsi->info.n_data_lanes / 2;
661
662         dsi->dsi_control_val =
663                         DSI_CONTROL_VIRTUAL_CHANNEL(dsi->info.virtual_channel) |
664                         DSI_CONTROL_NUM_DATA_LANES(dsi->info.n_data_lanes - 1) |
665                         DSI_CONTROL_VID_SOURCE(dc->ndev->id) |
666                         DSI_CONTROL_DATA_FORMAT(dsi->info.pixel_format);
667
668         if (dsi->info.ganged_type)
669                 tegra_dsi_pix_correction(dc, dsi);
670
671         /* Below we are going to calculate dsi and dc clock rate.
672          * Calcuate the horizontal and vertical width.
673          */
674         h_width_pixels = dc->mode.h_back_porch + dc->mode.h_front_porch +
675                         dc->mode.h_sync_width + dc->mode.h_active;
676
677         v_width_lines = dc->mode.v_back_porch + dc->mode.v_front_porch +
678                         dc->mode.v_sync_width + dc->mode.v_active;
679
680         /* Calculate minimum required pixel rate. */
681         pixel_clk_hz = h_width_pixels * v_width_lines * dsi->info.refresh_rate;
682         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
683                 if (dsi->info.rated_refresh_rate >= dsi->info.refresh_rate)
684                         dev_info(&dc->ndev->dev, "DSI: measured refresh rate "
685                                 "should be larger than rated refresh rate.\n");
686                 dc->mode.rated_pclk = h_width_pixels * v_width_lines *
687                                                 dsi->info.rated_refresh_rate;
688         }
689
690         /* Calculate minimum byte rate on DSI interface. */
691         byte_clk_hz = (pixel_clk_hz * dsi->pixel_scaler_mul) /
692                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
693
694         /* Round up to multiple of mega hz. */
695         plld_clk_mhz = DIV_ROUND_UP((byte_clk_hz * NUMOF_BIT_PER_BYTE),
696                                                                 1000000);
697
698         /* Calculate default real shift_clk_div. */
699         dsi->default_shift_clk_div.mul = NUMOF_BIT_PER_BYTE *
700                                         dsi->pixel_scaler_mul;
701         dsi->default_shift_clk_div.div = 2 * dsi->pixel_scaler_div *
702                                         dsi->info.n_data_lanes;
703
704         /* Calculate default DSI hs clock. DSI interface is double data rate.
705          * Data is transferred on both rising and falling edge of clk, div by 2
706          * to get the actual clock rate.
707          */
708         dsi->default_hs_clk_khz = plld_clk_mhz * 1000 / 2;
709
710         dsi->default_pixel_clk_khz = (plld_clk_mhz * 1000 *
711                                         dsi->default_shift_clk_div.div) /
712                                         (2 * dsi->default_shift_clk_div.mul);
713
714         /* Get the actual shift_clk_div and clock rates. */
715         dsi->shift_clk_div = tegra_dsi_get_shift_clk_div(dsi);
716         dsi->target_lp_clk_khz =
717                         tegra_dsi_get_lp_clk_rate(dsi, DSI_LP_OP_WRITE);
718         dsi->target_hs_clk_khz = tegra_dsi_get_hs_clk_rate(dsi);
719
720         dev_info(&dc->ndev->dev, "DSI: HS clock rate is %d\n",
721                                         dsi->target_hs_clk_khz);
722
723 #if DSI_USE_SYNC_POINTS
724         dsi->syncpt_id = NVSYNCPT_DSI;
725 #endif
726
727         /*
728          * Force video clock to be continuous mode if
729          * enable_hs_clock_on_lp_cmd_mode is set
730          */
731         if (dsi->info.enable_hs_clock_on_lp_cmd_mode) {
732                 if (dsi->info.video_clock_mode !=
733                                         TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
734                         dev_warn(&dc->ndev->dev,
735                                 "Force clock continuous mode\n");
736
737                 dsi->info.video_clock_mode = TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS;
738         }
739
740         atomic_set(&dsi->host_ref, 0);
741         dsi->host_suspended = false;
742         mutex_init(&dsi->host_lock);
743         init_completion(&dc->out->user_vblank_comp);
744         INIT_DELAYED_WORK(&dsi->idle_work, tegra_dc_dsi_idle_work);
745         dsi->idle_delay = msecs_to_jiffies(DSI_HOST_IDLE_PERIOD);
746 }
747
748 #define SELECT_T_PHY(platform_t_phy_ns, default_phy, clk_ns, hw_inc) ( \
749 (platform_t_phy_ns) ? ( \
750 ((DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)) < 0 ? 0 : \
751 (DSI_CONVERT_T_PHY_NS_TO_T_PHY(platform_t_phy_ns, clk_ns, hw_inc)))) : \
752 ((default_phy) < 0 ? 0 : (default_phy)))
753
754 static void tegra_dsi_get_clk_phy_timing(struct tegra_dc_dsi_data *dsi,
755                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
756 {
757         phy_timing_clk->t_tlpx = SELECT_T_PHY(
758                 dsi->info.phy_timing.t_tlpx_ns,
759                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
760
761         phy_timing_clk->t_clktrail = SELECT_T_PHY(
762                 dsi->info.phy_timing.t_clktrail_ns,
763                 T_CLKTRAIL_DEFAULT(clk_ns), clk_ns, T_CLKTRAIL_HW_INC);
764
765         phy_timing_clk->t_clkpost = SELECT_T_PHY(
766                 dsi->info.phy_timing.t_clkpost_ns,
767                 T_CLKPOST_DEFAULT(clk_ns), clk_ns, T_CLKPOST_HW_INC);
768
769         phy_timing_clk->t_clkzero = SELECT_T_PHY(
770                 dsi->info.phy_timing.t_clkzero_ns,
771                 T_CLKZERO_DEFAULT(clk_ns), clk_ns, T_CLKZERO_HW_INC);
772
773         phy_timing_clk->t_clkprepare = SELECT_T_PHY(
774                 dsi->info.phy_timing.t_clkprepare_ns,
775                 T_CLKPREPARE_DEFAULT(clk_ns), clk_ns, T_CLKPREPARE_HW_INC);
776
777         phy_timing_clk->t_clkpre = SELECT_T_PHY(
778                 dsi->info.phy_timing.t_clkpre_ns,
779                 T_CLKPRE_DEFAULT, clk_ns, T_CLKPRE_HW_INC);
780 }
781
782 static void tegra_dsi_get_hs_phy_timing(struct tegra_dc_dsi_data *dsi,
783                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
784 {
785         phy_timing_clk->t_tlpx = SELECT_T_PHY(
786                 dsi->info.phy_timing.t_tlpx_ns,
787                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
788
789         phy_timing_clk->t_hsdexit = SELECT_T_PHY(
790                 dsi->info.phy_timing.t_hsdexit_ns,
791                 T_HSEXIT_DEFAULT(clk_ns), clk_ns, T_HSEXIT_HW_INC);
792
793         phy_timing_clk->t_hstrail = SELECT_T_PHY(
794                 dsi->info.phy_timing.t_hstrail_ns,
795                 T_HSTRAIL_DEFAULT(clk_ns), clk_ns, T_HSTRAIL_HW_INC);
796
797         phy_timing_clk->t_datzero = SELECT_T_PHY(
798                 dsi->info.phy_timing.t_datzero_ns,
799                 T_DATZERO_DEFAULT(clk_ns), clk_ns, T_DATZERO_HW_INC);
800
801         phy_timing_clk->t_hsprepare = SELECT_T_PHY(
802                 dsi->info.phy_timing.t_hsprepare_ns,
803                 T_HSPREPARE_DEFAULT(clk_ns), clk_ns, T_HSPREPARE_HW_INC);
804 }
805
806 static void tegra_dsi_get_escape_phy_timing(struct tegra_dc_dsi_data *dsi,
807                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
808 {
809         phy_timing_clk->t_tlpx = SELECT_T_PHY(
810                 dsi->info.phy_timing.t_tlpx_ns,
811                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
812 }
813
814 static void tegra_dsi_get_bta_phy_timing(struct tegra_dc_dsi_data *dsi,
815                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
816 {
817         phy_timing_clk->t_tlpx = SELECT_T_PHY(
818                 dsi->info.phy_timing.t_tlpx_ns,
819                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
820
821         phy_timing_clk->t_taget = SELECT_T_PHY(
822                 dsi->info.phy_timing.t_taget_ns,
823                 T_TAGET_DEFAULT(clk_ns), clk_ns, T_TAGET_HW_INC);
824
825         phy_timing_clk->t_tasure = SELECT_T_PHY(
826                 dsi->info.phy_timing.t_tasure_ns,
827                 T_TASURE_DEFAULT(clk_ns), clk_ns, T_TASURE_HW_INC);
828
829         phy_timing_clk->t_tago = SELECT_T_PHY(
830                 dsi->info.phy_timing.t_tago_ns,
831                 T_TAGO_DEFAULT(clk_ns), clk_ns, T_TAGO_HW_INC);
832 }
833
834 static void tegra_dsi_get_ulps_phy_timing(struct tegra_dc_dsi_data *dsi,
835                 struct dsi_phy_timing_inclk *phy_timing_clk, u32 clk_ns)
836 {
837         phy_timing_clk->t_tlpx = SELECT_T_PHY(
838                 dsi->info.phy_timing.t_tlpx_ns,
839                 T_TLPX_DEFAULT(clk_ns), clk_ns, T_TLPX_HW_INC);
840
841         phy_timing_clk->t_wakeup = SELECT_T_PHY(
842                 dsi->info.phy_timing.t_wakeup_ns,
843                 T_WAKEUP_DEFAULT, clk_ns, T_WAKEUP_HW_INC);
844 }
845
846 #undef SELECT_T_PHY
847
848 static void tegra_dsi_get_phy_timing(struct tegra_dc_dsi_data *dsi,
849                                 struct dsi_phy_timing_inclk *phy_timing_clk,
850                                 u32 clk_ns, u8 lphs)
851 {
852         if (tegra_platform_is_fpga() && !(dsi->info.ganged_type)) {
853                 clk_ns = (1000 * 1000) / (dsi->info.fpga_freq_khz ?
854                         dsi->info.fpga_freq_khz : DEFAULT_FPGA_FREQ_KHZ);
855         }
856
857         phy_timing_clk->t_hsdexit = dsi->info.phy_timing.t_hsdexit_ns ?
858                         (dsi->info.phy_timing.t_hsdexit_ns / clk_ns) :
859                         (T_HSEXIT_DEFAULT(clk_ns));
860
861         if (lphs == DSI_LPHS_IN_HS_MODE) {
862                 tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
863                 tegra_dsi_get_hs_phy_timing(dsi, phy_timing_clk, clk_ns);
864         } else {
865                 /* default is LP mode */
866                 tegra_dsi_get_escape_phy_timing(dsi, phy_timing_clk, clk_ns);
867                 tegra_dsi_get_bta_phy_timing(dsi, phy_timing_clk, clk_ns);
868                 tegra_dsi_get_ulps_phy_timing(dsi, phy_timing_clk, clk_ns);
869                 if (dsi->info.enable_hs_clock_on_lp_cmd_mode)
870                         tegra_dsi_get_clk_phy_timing(dsi, phy_timing_clk, clk_ns);
871         }
872 }
873
874 static int tegra_dsi_mipi_phy_timing_range(struct tegra_dc_dsi_data *dsi,
875                                 struct dsi_phy_timing_inclk *phy_timing,
876                                 u32 clk_ns, u8 lphs)
877 {
878         int err = 0;
879
880 #define CHECK_RANGE(val, min, max) ( \
881                 ((min) == NOT_DEFINED ? 0 : (val) < (min)) || \
882                 ((max) == NOT_DEFINED ? 0 : (val) > (max)) ? -EINVAL : 0)
883
884         if (tegra_platform_is_fpga())
885                 clk_ns = dsi->info.fpga_freq_khz ?
886                         ((1000 * 1000) / dsi->info.fpga_freq_khz) :
887                         DEFAULT_FPGA_FREQ_KHZ;
888
889         err = CHECK_RANGE(
890         DSI_CONVERT_T_PHY_TO_T_PHY_NS(
891                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC),
892                         MIPI_T_TLPX_NS_MIN, MIPI_T_TLPX_NS_MAX);
893         if (err < 0) {
894                 dev_warn(&dsi->dc->ndev->dev,
895                         "dsi: Tlpx mipi range violated\n");
896                 goto fail;
897         }
898
899         if (lphs == DSI_LPHS_IN_HS_MODE) {
900                 err = CHECK_RANGE(
901                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
902                         phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC),
903                         MIPI_T_HSEXIT_NS_MIN, MIPI_T_HSEXIT_NS_MAX);
904                 if (err < 0) {
905                         dev_warn(&dsi->dc->ndev->dev,
906                                 "dsi: HsExit mipi range violated\n");
907                         goto fail;
908                 }
909
910                 err = CHECK_RANGE(
911                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
912                         phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC),
913                         MIPI_T_HSTRAIL_NS_MIN(clk_ns), MIPI_T_HSTRAIL_NS_MAX);
914                 if (err < 0) {
915                         dev_warn(&dsi->dc->ndev->dev,
916                                 "dsi: HsTrail mipi range violated\n");
917                         goto fail;
918                 }
919
920                 err = CHECK_RANGE(
921                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
922                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
923                         MIPI_T_HSZERO_NS_MIN, MIPI_T_HSZERO_NS_MAX);
924                 if (err < 0) {
925                         dev_warn(&dsi->dc->ndev->dev,
926                                 "dsi: HsZero mipi range violated\n");
927                         goto fail;
928                 }
929
930                 err = CHECK_RANGE(
931                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
932                         phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC),
933                         MIPI_T_HSPREPARE_NS_MIN(clk_ns),
934                         MIPI_T_HSPREPARE_NS_MAX(clk_ns));
935                 if (err < 0) {
936                         dev_warn(&dsi->dc->ndev->dev,
937                                 "dsi: HsPrepare mipi range violated\n");
938                         goto fail;
939                 }
940
941                 err = CHECK_RANGE(
942                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
943                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
944                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
945                         phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC),
946                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MIN(clk_ns),
947                         MIPI_T_HSPREPARE_ADD_HSZERO_NS_MAX);
948                 if (err < 0) {
949                         dev_warn(&dsi->dc->ndev->dev,
950                         "dsi: HsPrepare + HsZero mipi range violated\n");
951                         goto fail;
952                 }
953         } else {
954                 /* default is LP mode */
955                 err = CHECK_RANGE(
956                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
957                         phy_timing->t_wakeup, clk_ns, T_WAKEUP_HW_INC),
958                         MIPI_T_WAKEUP_NS_MIN, MIPI_T_WAKEUP_NS_MAX);
959                 if (err < 0) {
960                         dev_warn(&dsi->dc->ndev->dev,
961                                 "dsi: WakeUp mipi range violated\n");
962                         goto fail;
963                 }
964
965                 err = CHECK_RANGE(
966                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
967                         phy_timing->t_tasure, clk_ns, T_TASURE_HW_INC),
968                         MIPI_T_TASURE_NS_MIN(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
969                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)),
970                         MIPI_T_TASURE_NS_MAX(DSI_CONVERT_T_PHY_TO_T_PHY_NS(
971                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC)));
972                 if (err < 0) {
973                         dev_warn(&dsi->dc->ndev->dev,
974                                 "dsi: TaSure mipi range violated\n");
975                         goto fail;
976                 }
977         }
978
979         if (lphs == DSI_LPHS_IN_HS_MODE ||
980                 dsi->info.enable_hs_clock_on_lp_cmd_mode) {
981                 err = CHECK_RANGE(
982                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
983                         phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC),
984                         MIPI_T_CLKTRAIL_NS_MIN, MIPI_T_CLKTRAIL_NS_MAX);
985                 if (err < 0) {
986                         dev_warn(&dsi->dc->ndev->dev,
987                                 "dsi: ClkTrail mipi range violated\n");
988                         goto fail;
989                 }
990
991                 err = CHECK_RANGE(
992                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
993                         phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC),
994                         MIPI_T_CLKPOST_NS_MIN(clk_ns), MIPI_T_CLKPOST_NS_MAX);
995                 if (err < 0) {
996                         dev_warn(&dsi->dc->ndev->dev,
997                                 "dsi: ClkPost mipi range violated\n");
998                         goto fail;
999                 }
1000
1001                 err = CHECK_RANGE(
1002                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1003                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
1004                         MIPI_T_CLKZERO_NS_MIN, MIPI_T_CLKZERO_NS_MAX);
1005                 if (err < 0) {
1006                         dev_warn(&dsi->dc->ndev->dev,
1007                                 "dsi: ClkZero mipi range violated\n");
1008                         goto fail;
1009                 }
1010
1011                 err = CHECK_RANGE(
1012                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1013                         phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC),
1014                         MIPI_T_CLKPREPARE_NS_MIN, MIPI_T_CLKPREPARE_NS_MAX);
1015                 if (err < 0) {
1016                         dev_warn(&dsi->dc->ndev->dev,
1017                                 "dsi: ClkPrepare mipi range violated\n");
1018                         goto fail;
1019                 }
1020
1021                 err = CHECK_RANGE(
1022                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1023                         phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC),
1024                         MIPI_T_CLKPRE_NS_MIN, MIPI_T_CLKPRE_NS_MAX);
1025                 if (err < 0) {
1026                         dev_warn(&dsi->dc->ndev->dev,
1027                                 "dsi: ClkPre mipi range violated\n");
1028                         goto fail;
1029                 }
1030
1031                 err = CHECK_RANGE(
1032                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1033                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1034                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1035                         phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC),
1036                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MIN,
1037                         MIPI_T_CLKPREPARE_ADD_CLKZERO_NS_MAX);
1038                 if (err < 0) {
1039                         dev_warn(&dsi->dc->ndev->dev,
1040                         "dsi: ClkPrepare + ClkZero mipi range violated\n");
1041                         goto fail;
1042                 }
1043         }
1044 fail:
1045 #undef CHECK_RANGE
1046         return err;
1047 }
1048
1049 static int tegra_dsi_hs_phy_len(struct tegra_dc_dsi_data *dsi,
1050                                 struct dsi_phy_timing_inclk *phy_timing,
1051                                 u32 clk_ns, u8 lphs)
1052 {
1053         u32 hs_t_phy_ns = 0;
1054         u32 clk_t_phy_ns = 0;
1055         u32 t_phy_ns;
1056         u32 h_blank_ns;
1057         struct tegra_dc_mode *modes;
1058         u32 t_pix_ns;
1059         int err = 0;
1060
1061         if (!(lphs == DSI_LPHS_IN_HS_MODE))
1062                 goto fail;
1063
1064         if (dsi->info.video_data_type ==
1065                 TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE &&
1066                 dsi->info.video_burst_mode <=
1067                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1068                 goto fail;
1069
1070         modes = dsi->dc->out->modes;
1071         t_pix_ns = clk_ns * BITS_PER_BYTE *
1072                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1073
1074         hs_t_phy_ns =
1075                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1076                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1077                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1078                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1079                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1080                 phy_timing->t_hsprepare, clk_ns, T_HSPREPARE_HW_INC) +
1081                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1082                 phy_timing->t_datzero, clk_ns, T_DATZERO_HW_INC) +
1083                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1084                 phy_timing->t_hstrail, clk_ns, T_HSTRAIL_HW_INC) +
1085                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1086                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC);
1087
1088         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_TX_ONLY) {
1089                 clk_t_phy_ns =
1090                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1091                 phy_timing->t_clkpost, clk_ns, T_CLKPOST_HW_INC) +
1092                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1093                 phy_timing->t_clktrail, clk_ns, T_CLKTRAIL_HW_INC) +
1094                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1095                 phy_timing->t_hsdexit, clk_ns, T_HSEXIT_HW_INC) +
1096                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1097                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1098                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1099                 phy_timing->t_clkprepare, clk_ns, T_CLKPREPARE_HW_INC) +
1100                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1101                 phy_timing->t_clkzero, clk_ns, T_CLKZERO_HW_INC) +
1102                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1103                 phy_timing->t_clkpre, clk_ns, T_CLKPRE_HW_INC);
1104
1105                 /* clk_pre overlaps LP-11 hs mode start sequence */
1106                 hs_t_phy_ns -= DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1107                         phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC);
1108         }
1109
1110         h_blank_ns = t_pix_ns * (modes->h_sync_width + modes->h_back_porch +
1111                                                 modes->h_front_porch);
1112
1113         /* Extra tlpx and byte cycle required by dsi HW */
1114         t_phy_ns = dsi->info.n_data_lanes * (hs_t_phy_ns + clk_t_phy_ns +
1115                 DSI_CONVERT_T_PHY_TO_T_PHY_NS(
1116                 phy_timing->t_tlpx, clk_ns, T_TLPX_HW_INC) +
1117                 clk_ns * BITS_PER_BYTE);
1118
1119         if (h_blank_ns < t_phy_ns) {
1120                 err = -EINVAL;
1121                 dev_WARN(&dsi->dc->ndev->dev,
1122                         "dsi: Hblank is smaller than HS trans phy timing\n");
1123                 goto fail;
1124         }
1125
1126         return 0;
1127 fail:
1128         return err;
1129 }
1130
1131 static int tegra_dsi_constraint_phy_timing(struct tegra_dc_dsi_data *dsi,
1132                                 struct dsi_phy_timing_inclk *phy_timing,
1133                                 u32 clk_ns, u8 lphs)
1134 {
1135         int err = 0;
1136
1137         err = tegra_dsi_mipi_phy_timing_range(dsi, phy_timing, clk_ns, lphs);
1138         if (err < 0) {
1139                 dev_warn(&dsi->dc->ndev->dev, "dsi: mipi range violated\n");
1140                 goto fail;
1141         }
1142
1143         err = tegra_dsi_hs_phy_len(dsi, phy_timing, clk_ns, lphs);
1144         if (err < 0) {
1145                 dev_err(&dsi->dc->ndev->dev, "dsi: Hblank too short\n");
1146                 goto fail;
1147         }
1148
1149         /* TODO: add more contraints */
1150 fail:
1151         return err;
1152 }
1153
1154 static void tegra_dsi_set_phy_timing(struct tegra_dc_dsi_data *dsi, u8 lphs)
1155 {
1156         u32 val;
1157         struct dsi_phy_timing_inclk phy_timing = dsi->phy_timing;
1158
1159         tegra_dsi_get_phy_timing
1160                 (dsi, &phy_timing, dsi->current_bit_clk_ns, lphs);
1161
1162         tegra_dsi_constraint_phy_timing(dsi, &phy_timing,
1163                                         dsi->current_bit_clk_ns, lphs);
1164
1165         if (tegra_platform_is_fpga() && dsi->info.ganged_type) {
1166                 phy_timing.t_hsdexit += T_HSEXIT_HW_INC;
1167                 phy_timing.t_hstrail += T_HSTRAIL_HW_INC + 3;
1168                 phy_timing.t_datzero += T_DATZERO_HW_INC;
1169                 phy_timing.t_hsprepare += T_HSPREPARE_HW_INC;
1170
1171                 phy_timing.t_clktrail += T_CLKTRAIL_HW_INC;
1172                 phy_timing.t_clkpost += T_CLKPOST_HW_INC;
1173                 phy_timing.t_clkzero += T_CLKZERO_HW_INC;
1174                 phy_timing.t_tlpx += T_TLPX_HW_INC;
1175
1176                 phy_timing.t_clkprepare += T_CLKPREPARE_HW_INC;
1177                 phy_timing.t_clkpre += T_CLKPRE_HW_INC;
1178                 phy_timing.t_wakeup += T_WAKEUP_HW_INC;
1179
1180                 phy_timing.t_taget += T_TAGET_HW_INC;
1181                 phy_timing.t_tasure += T_TASURE_HW_INC;
1182                 phy_timing.t_tago += T_TAGO_HW_INC;
1183         }
1184         val = DSI_PHY_TIMING_0_THSDEXIT(phy_timing.t_hsdexit) |
1185                         DSI_PHY_TIMING_0_THSTRAIL(phy_timing.t_hstrail) |
1186                         DSI_PHY_TIMING_0_TDATZERO(phy_timing.t_datzero) |
1187                         DSI_PHY_TIMING_0_THSPREPR(phy_timing.t_hsprepare);
1188         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_0);
1189
1190         val = DSI_PHY_TIMING_1_TCLKTRAIL(phy_timing.t_clktrail) |
1191                         DSI_PHY_TIMING_1_TCLKPOST(phy_timing.t_clkpost) |
1192                         DSI_PHY_TIMING_1_TCLKZERO(phy_timing.t_clkzero) |
1193                         DSI_PHY_TIMING_1_TTLPX(phy_timing.t_tlpx);
1194         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_1);
1195
1196         val = DSI_PHY_TIMING_2_TCLKPREPARE(phy_timing.t_clkprepare) |
1197                 DSI_PHY_TIMING_2_TCLKPRE(phy_timing.t_clkpre) |
1198                         DSI_PHY_TIMING_2_TWAKEUP(phy_timing.t_wakeup);
1199         tegra_dsi_writel(dsi, val, DSI_PHY_TIMING_2);
1200
1201         val = DSI_BTA_TIMING_TTAGET(phy_timing.t_taget) |
1202                         DSI_BTA_TIMING_TTASURE(phy_timing.t_tasure) |
1203                         DSI_BTA_TIMING_TTAGO(phy_timing.t_tago);
1204         tegra_dsi_writel(dsi, val, DSI_BTA_TIMING);
1205
1206         dsi->phy_timing = phy_timing;
1207 }
1208
1209 static u32 tegra_dsi_sol_delay_burst(struct tegra_dc *dc,
1210                                 struct tegra_dc_dsi_data *dsi)
1211 {
1212         u32 dsi_to_pixel_clk_ratio;
1213         u32 temp;
1214         u32 temp1;
1215         u32 mipi_clk_adj_kHz = 0;
1216         u32 sol_delay;
1217         struct tegra_dc_mode *dc_modes = &dc->mode;
1218
1219         /* Get Fdsi/Fpixel ration (note: Fdsi is in bit format) */
1220         dsi_to_pixel_clk_ratio = (dsi->current_dsi_clk_khz * 2 +
1221                 dsi->default_pixel_clk_khz - 1) / dsi->default_pixel_clk_khz;
1222
1223         /* Convert Fdsi to byte format */
1224         dsi_to_pixel_clk_ratio *= 1000/8;
1225
1226         /* Multiplying by 1000 so that we don't loose the fraction part */
1227         temp = dc_modes->h_active * 1000;
1228         temp1 = dc_modes->h_active + dc_modes->h_back_porch +
1229                         dc_modes->h_sync_width;
1230
1231         sol_delay = temp1 * dsi_to_pixel_clk_ratio -
1232                         temp * dsi->pixel_scaler_mul /
1233                         (dsi->pixel_scaler_div * dsi->info.n_data_lanes);
1234
1235         /* Do rounding on sol delay */
1236         sol_delay = (sol_delay + 1000 - 1)/1000;
1237
1238         /* TODO:
1239          * 1. find out the correct sol fifo depth to use
1240          * 2. verify with hw about the clamping function
1241          */
1242         if (sol_delay > (480 * 4)) {
1243                 sol_delay = (480 * 4);
1244                 mipi_clk_adj_kHz = sol_delay +
1245                         (dc_modes->h_active * dsi->pixel_scaler_mul) /
1246                         (dsi->info.n_data_lanes * dsi->pixel_scaler_div);
1247
1248                 mipi_clk_adj_kHz *= (dsi->default_pixel_clk_khz / temp1);
1249
1250                 mipi_clk_adj_kHz *= 4;
1251         }
1252
1253         dsi->target_hs_clk_khz = mipi_clk_adj_kHz;
1254
1255         return sol_delay;
1256 }
1257
1258 static void tegra_dsi_set_sol_delay(struct tegra_dc *dc,
1259                                 struct tegra_dc_dsi_data *dsi)
1260 {
1261         u32 sol_delay;
1262         u32 internal_delay;
1263         u32 h_width_byte_clk;
1264         u32 h_width_pixels;
1265         u32 h_width_ganged_byte_clk;
1266         u8 n_data_lanes_this_cont = 0;
1267         u8 n_data_lanes_ganged = 0;
1268
1269         if (!(dsi->info.ganged_type)) {
1270                 if (dsi->info.video_burst_mode ==
1271                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
1272                         dsi->info.video_burst_mode ==
1273                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END) {
1274 #define VIDEO_FIFO_LATENCY_PIXEL_CLK 8
1275                         sol_delay = VIDEO_FIFO_LATENCY_PIXEL_CLK *
1276                                 dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1277 #undef VIDEO_FIFO_LATENCY_PIXEL_CLK
1278                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
1279                 } else {
1280                         sol_delay = tegra_dsi_sol_delay_burst(dc, dsi);
1281                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
1282                 }
1283         } else {
1284 #define SOL_TO_VALID_PIX_CLK_DELAY 4
1285 #define VALID_TO_FIFO_PIX_CLK_DELAY 4
1286 #define FIFO_WR_PIX_CLK_DELAY 2
1287 #define FIFO_RD_BYTE_CLK_DELAY 6
1288 #define TOT_INTERNAL_PIX_DELAY (SOL_TO_VALID_PIX_CLK_DELAY + \
1289                                 VALID_TO_FIFO_PIX_CLK_DELAY + \
1290                                 FIFO_WR_PIX_CLK_DELAY)
1291
1292                 internal_delay = DIV_ROUND_UP(
1293                                 TOT_INTERNAL_PIX_DELAY * dsi->pixel_scaler_mul,
1294                                 dsi->pixel_scaler_div * dsi->info.n_data_lanes)
1295                                 + FIFO_RD_BYTE_CLK_DELAY;
1296
1297                 h_width_pixels = dc->mode.h_sync_width +
1298                                         dc->mode.h_back_porch +
1299                                         dc->mode.h_active +
1300                                         dc->mode.h_front_porch;
1301
1302                 h_width_byte_clk = DIV_ROUND_UP(h_width_pixels *
1303                                         dsi->pixel_scaler_mul,
1304                                         dsi->pixel_scaler_div *
1305                                         dsi->info.n_data_lanes);
1306
1307                 if (dsi->info.ganged_type ==
1308                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1309                         dsi->info.ganged_type ==
1310                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1311                         n_data_lanes_this_cont = dsi->info.n_data_lanes / 2;
1312                         n_data_lanes_ganged = dsi->info.n_data_lanes;
1313                 }
1314
1315                 h_width_ganged_byte_clk = DIV_ROUND_UP(
1316                                         n_data_lanes_this_cont *
1317                                         h_width_byte_clk,
1318                                         n_data_lanes_ganged);
1319
1320                 sol_delay = h_width_byte_clk - h_width_ganged_byte_clk +
1321                                                         internal_delay;
1322                 sol_delay = (dsi->info.video_data_type ==
1323                                 TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) ?
1324                                 sol_delay + 20: sol_delay;
1325
1326 #undef SOL_TO_VALID_PIX_CLK_DELAY
1327 #undef VALID_TO_FIFO_PIX_CLK_DELAY
1328 #undef FIFO_WR_PIX_CLK_DELAY
1329 #undef FIFO_RD_BYTE_CLK_DELAY
1330 #undef TOT_INTERNAL_PIX_DELAY
1331         }
1332
1333         tegra_dsi_writel(dsi, DSI_SOL_DELAY_SOL_DELAY(sol_delay),
1334                                                 DSI_SOL_DELAY);
1335 }
1336
1337 static void tegra_dsi_set_timeout(struct tegra_dc_dsi_data *dsi)
1338 {
1339         u32 val;
1340         u32 bytes_per_frame;
1341         u32 timeout = 0;
1342
1343         /* TODO: verify the following equation */
1344         bytes_per_frame = dsi->current_dsi_clk_khz * 1000 * 2 /
1345                                                 (dsi->info.refresh_rate * 8);
1346         timeout = bytes_per_frame / DSI_CYCLE_COUNTER_VALUE;
1347         timeout = (timeout + DSI_HTX_TO_MARGIN) & 0xffff;
1348
1349         val = DSI_TIMEOUT_0_LRXH_TO(DSI_LRXH_TO_VALUE) |
1350                         DSI_TIMEOUT_0_HTX_TO(timeout);
1351         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_0);
1352
1353         if (dsi->info.panel_reset_timeout_msec)
1354                 timeout = (dsi->info.panel_reset_timeout_msec * 1000*1000)
1355                                         / dsi->current_bit_clk_ns;
1356         else
1357                 timeout = DSI_PR_TO_VALUE;
1358
1359         val = DSI_TIMEOUT_1_PR_TO(timeout) |
1360                 DSI_TIMEOUT_1_TA_TO(DSI_TA_TO_VALUE);
1361         tegra_dsi_writel(dsi, val, DSI_TIMEOUT_1);
1362
1363         val = DSI_TO_TALLY_P_RESET_STATUS(IN_RESET) |
1364                 DSI_TO_TALLY_TA_TALLY(DSI_TA_TALLY_VALUE)|
1365                 DSI_TO_TALLY_LRXH_TALLY(DSI_LRXH_TALLY_VALUE)|
1366                 DSI_TO_TALLY_HTX_TALLY(DSI_HTX_TALLY_VALUE);
1367         tegra_dsi_writel(dsi, val, DSI_TO_TALLY);
1368 }
1369
1370 static void tegra_dsi_setup_ganged_mode_pkt_length(struct tegra_dc *dc,
1371                                                 struct tegra_dc_dsi_data *dsi)
1372 {
1373         u32 hact_pkt_len_pix_orig = dc->mode.h_active;
1374         u32 hact_pkt_len_pix = 0;
1375         u32 hact_pkt_len_bytes = 0;
1376         u32 hfp_pkt_len_bytes = 0;
1377         u32 pix_per_line_orig = 0;
1378         u32 pix_per_line = 0;
1379         u32 val = 0;
1380
1381 /* hsync + hact + hfp = (4) + (4+2) + (4+2) */
1382 #define HEADER_OVERHEAD 16
1383
1384         pix_per_line_orig = dc->mode.h_sync_width + dc->mode.h_back_porch +
1385                         dc->mode.h_active + dc->mode.h_front_porch;
1386
1387         if (dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT ||
1388                 dsi->info.ganged_type == TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
1389                 hact_pkt_len_pix = DIV_ROUND_UP(hact_pkt_len_pix_orig, 2);
1390                 pix_per_line = DIV_ROUND_UP(pix_per_line_orig, 2);
1391                 if (dsi->controller_index) {
1392                         hact_pkt_len_pix =
1393                                 hact_pkt_len_pix_orig - hact_pkt_len_pix;
1394                         pix_per_line = pix_per_line_orig - pix_per_line;
1395                 }
1396                 hact_pkt_len_bytes = hact_pkt_len_pix *
1397                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div;
1398                 hfp_pkt_len_bytes = pix_per_line *
1399                         dsi->pixel_scaler_mul / dsi->pixel_scaler_div -
1400                         hact_pkt_len_bytes - HEADER_OVERHEAD;
1401         }
1402
1403         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1404                 DSI_PKT_LEN_0_1_LENGTH_1(0);
1405         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1406
1407         val = DSI_PKT_LEN_2_3_LENGTH_2(0x0) |
1408                 DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len_bytes);
1409         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1410
1411         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len_bytes) |
1412                 DSI_PKT_LEN_4_5_LENGTH_5(0);
1413         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1414
1415         val = DSI_PKT_LEN_6_7_LENGTH_6(0) |
1416                 DSI_PKT_LEN_6_7_LENGTH_7(0);
1417         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1418
1419 #undef HEADER_OVERHEAD
1420 }
1421
1422 static void tegra_dsi_setup_video_mode_pkt_length(struct tegra_dc *dc,
1423                                                 struct tegra_dc_dsi_data *dsi)
1424 {
1425         u32 val;
1426         u32 hact_pkt_len;
1427         u32 hsa_pkt_len;
1428         u32 hbp_pkt_len;
1429         u32 hfp_pkt_len;
1430
1431         hact_pkt_len = dc->mode.h_active * dsi->pixel_scaler_mul /
1432                                                         dsi->pixel_scaler_div;
1433         hsa_pkt_len = dc->mode.h_sync_width * dsi->pixel_scaler_mul /
1434                                                         dsi->pixel_scaler_div;
1435         hbp_pkt_len = dc->mode.h_back_porch * dsi->pixel_scaler_mul /
1436                                                         dsi->pixel_scaler_div;
1437         hfp_pkt_len = dc->mode.h_front_porch * dsi->pixel_scaler_mul /
1438                                                         dsi->pixel_scaler_div;
1439
1440         if (dsi->info.video_burst_mode !=
1441                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
1442                 hbp_pkt_len += hsa_pkt_len;
1443
1444         hsa_pkt_len -= DSI_HSYNC_BLNK_PKT_OVERHEAD;
1445         hbp_pkt_len -= DSI_HBACK_PORCH_PKT_OVERHEAD;
1446         hfp_pkt_len -= DSI_HFRONT_PORCH_PKT_OVERHEAD;
1447
1448         val = DSI_PKT_LEN_0_1_LENGTH_0(0) |
1449                         DSI_PKT_LEN_0_1_LENGTH_1(hsa_pkt_len);
1450         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1451
1452         val = DSI_PKT_LEN_2_3_LENGTH_2(hbp_pkt_len) |
1453                         DSI_PKT_LEN_2_3_LENGTH_3(hact_pkt_len);
1454         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1455
1456         val = DSI_PKT_LEN_4_5_LENGTH_4(hfp_pkt_len) |
1457                         DSI_PKT_LEN_4_5_LENGTH_5(0);
1458         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1459
1460         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1461         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1462 }
1463
1464 static void tegra_dsi_setup_cmd_mode_pkt_length(struct tegra_dc *dc,
1465                                                 struct tegra_dc_dsi_data *dsi)
1466 {
1467         unsigned long   val;
1468         unsigned long   act_bytes;
1469
1470         act_bytes = dc->mode.h_active * dsi->pixel_scaler_mul /
1471                         dsi->pixel_scaler_div + 1;
1472
1473         val = DSI_PKT_LEN_0_1_LENGTH_0(0) | DSI_PKT_LEN_0_1_LENGTH_1(0);
1474         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_0_1);
1475
1476         val = DSI_PKT_LEN_2_3_LENGTH_2(0) | DSI_PKT_LEN_2_3_LENGTH_3(act_bytes);
1477         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_2_3);
1478
1479         val = DSI_PKT_LEN_4_5_LENGTH_4(0) | DSI_PKT_LEN_4_5_LENGTH_5(act_bytes);
1480         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_4_5);
1481
1482         val = DSI_PKT_LEN_6_7_LENGTH_6(0) | DSI_PKT_LEN_6_7_LENGTH_7(0x0f0f);
1483         tegra_dsi_writel(dsi, val, DSI_PKT_LEN_6_7);
1484 }
1485
1486 static void tegra_dsi_set_pkt_length(struct tegra_dc *dc,
1487                                 struct tegra_dc_dsi_data *dsi)
1488 {
1489         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1490                 return;
1491
1492         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_VIDEO_MODE) {
1493                 if (dsi->info.ganged_type)
1494                         tegra_dsi_setup_ganged_mode_pkt_length(dc, dsi);
1495                 else
1496                         tegra_dsi_setup_video_mode_pkt_length(dc, dsi);
1497         } else {
1498                 tegra_dsi_setup_cmd_mode_pkt_length(dc, dsi);
1499         }
1500 }
1501
1502 static void tegra_dsi_set_pkt_seq(struct tegra_dc *dc,
1503                                 struct tegra_dc_dsi_data *dsi)
1504 {
1505         const u32 *pkt_seq;
1506         u32 rgb_info;
1507         u32 pkt_seq_3_5_rgb_lo;
1508         u32 pkt_seq_3_5_rgb_hi;
1509         u32     val;
1510         u32 reg;
1511         u8  i;
1512
1513         if (dsi->driven_mode == TEGRA_DSI_DRIVEN_BY_HOST)
1514                 return;
1515
1516         switch (dsi->info.pixel_format) {
1517         case TEGRA_DSI_PIXEL_FORMAT_16BIT_P:
1518                 rgb_info = CMD_RGB_16BPP;
1519                 break;
1520         case TEGRA_DSI_PIXEL_FORMAT_18BIT_P:
1521                 rgb_info = CMD_RGB_18BPP;
1522                 break;
1523         case TEGRA_DSI_PIXEL_FORMAT_18BIT_NP:
1524                 rgb_info = CMD_RGB_18BPPNP;
1525                 break;
1526         case TEGRA_DSI_PIXEL_FORMAT_24BIT_P:
1527         default:
1528                 rgb_info = CMD_RGB_24BPP;
1529                 break;
1530         }
1531
1532         pkt_seq_3_5_rgb_lo = 0;
1533         pkt_seq_3_5_rgb_hi = 0;
1534         if (dsi->info.pkt_seq)
1535                 pkt_seq = dsi->info.pkt_seq;
1536         else if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
1537                 pkt_seq = dsi_pkt_seq_cmd_mode;
1538         else {
1539                 switch (dsi->info.video_burst_mode) {
1540                 case TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED:
1541                 case TEGRA_DSI_VIDEO_BURST_MODE_LOW_SPEED:
1542                 case TEGRA_DSI_VIDEO_BURST_MODE_MEDIUM_SPEED:
1543                 case TEGRA_DSI_VIDEO_BURST_MODE_FAST_SPEED:
1544                 case TEGRA_DSI_VIDEO_BURST_MODE_FASTEST_SPEED:
1545                         pkt_seq_3_5_rgb_lo =
1546                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1547                         if (!dsi->info.no_pkt_seq_eot)
1548                                 pkt_seq = dsi_pkt_seq_video_burst;
1549                         else
1550                                 pkt_seq = dsi_pkt_seq_video_burst_no_eot;
1551                         break;
1552                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END:
1553                         pkt_seq_3_5_rgb_hi =
1554                                         DSI_PKT_SEQ_3_HI_PKT_34_ID(rgb_info);
1555                         pkt_seq = dsi_pkt_seq_video_non_burst_syne;
1556                         break;
1557                 case TEGRA_DSI_VIDEO_NONE_BURST_MODE:
1558                 default:
1559                         if (dsi->info.ganged_type) {
1560                                 pkt_seq_3_5_rgb_lo =
1561                                         DSI_PKT_SEQ_3_LO_PKT_31_ID(rgb_info);
1562                                 pkt_seq =
1563                                 dsi_pkt_seq_video_non_burst_no_eot_no_lp_no_hbp;
1564                         } else {
1565                                 pkt_seq_3_5_rgb_lo =
1566                                         DSI_PKT_SEQ_3_LO_PKT_32_ID(rgb_info);
1567                                 pkt_seq = dsi_pkt_seq_video_non_burst;
1568                         }
1569 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1570                         /* Simulator does not support EOT packet yet */
1571                         pkt_seq = dsi_pkt_seq_video_non_burst_no_eot;
1572 #else
1573                         pkt_seq = dsi_pkt_seq_video_non_burst;
1574 #endif
1575                         break;
1576                 }
1577         }
1578
1579         for (i = 0; i < NUMOF_PKT_SEQ; i++) {
1580                 val = pkt_seq[i];
1581                 reg = dsi_pkt_seq_reg[i];
1582                 if ((reg == DSI_PKT_SEQ_3_LO) || (reg == DSI_PKT_SEQ_5_LO))
1583                         val |= pkt_seq_3_5_rgb_lo;
1584                 if ((reg == DSI_PKT_SEQ_3_HI) || (reg == DSI_PKT_SEQ_5_HI))
1585                         val |= pkt_seq_3_5_rgb_hi;
1586                 tegra_dsi_writel(dsi, val, reg);
1587         }
1588 }
1589
1590 static void tegra_dsi_reset_underflow_overflow
1591                                 (struct tegra_dc_dsi_data *dsi)
1592 {
1593         u32 val;
1594
1595         val = tegra_dsi_readl(dsi, DSI_STATUS);
1596         val &= (DSI_STATUS_LB_OVERFLOW(0x1) | DSI_STATUS_LB_UNDERFLOW(0x1));
1597         if (val) {
1598                 if (val & DSI_STATUS_LB_OVERFLOW(0x1))
1599                         dev_warn(&dsi->dc->ndev->dev,
1600                                 "dsi: video fifo overflow. Resetting flag\n");
1601                 if (val & DSI_STATUS_LB_UNDERFLOW(0x1))
1602                         dev_warn(&dsi->dc->ndev->dev,
1603                                 "dsi: video fifo underflow. Resetting flag\n");
1604                 val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1605                 val |= DSI_HOST_CONTROL_FIFO_STAT_RESET(0x1);
1606                 tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1607                 udelay(5);
1608         }
1609 }
1610
1611 static void tegra_dsi_soft_reset(struct tegra_dc_dsi_data *dsi)
1612 {
1613         u32 trigger;
1614         u32 val;
1615         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1616         struct tegra_dc_mode mode = dsi->dc->mode;
1617         u32 tot_lines = mode.v_sync_width + mode.v_back_porch +
1618                                 mode.v_active + mode.v_front_porch;
1619         u32 line_period = DIV_ROUND_UP(MS_TO_US(frame_period), tot_lines);
1620         u32 timeout_cnt = 0;
1621
1622 /* wait for 1 frame duration + few extra cycles for dsi to go idle */
1623 #define DSI_IDLE_TIMEOUT        (tot_lines + 5)
1624
1625         val = tegra_dsi_readl(dsi, DSI_STATUS);
1626         while (!(val & DSI_STATUS_IDLE(0x1))) {
1627                 cpu_relax();
1628                 udelay(line_period);
1629                 val = tegra_dsi_readl(dsi, DSI_STATUS);
1630                 if (timeout_cnt++ > DSI_IDLE_TIMEOUT) {
1631                         dev_warn(&dsi->dc->ndev->dev, "dsi not idle when soft reset\n");
1632                         break;
1633                 }
1634         }
1635
1636         tegra_dsi_writel(dsi,
1637                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
1638                 DSI_POWER_CONTROL);
1639         /* stabilization delay */
1640         udelay(300);
1641
1642         tegra_dsi_writel(dsi,
1643                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
1644                 DSI_POWER_CONTROL);
1645         /* stabilization delay */
1646         udelay(300);
1647
1648         /* dsi HW does not clear host trigger bit automatically
1649          * on dsi interface disable if host fifo is empty or in mid
1650          * of host transmission
1651          */
1652         trigger = tegra_dsi_readl(dsi, DSI_TRIGGER);
1653         if (trigger)
1654                 tegra_dsi_writel(dsi, 0x0, DSI_TRIGGER);
1655
1656 #undef DSI_IDLE_TIMEOUT
1657 }
1658
1659 static void tegra_dsi_stop_dc_stream(struct tegra_dc *dc,
1660                                         struct tegra_dc_dsi_data *dsi)
1661 {
1662         tegra_dc_get(dc);
1663
1664         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1665         tegra_dc_writel(dc, 0, DC_DISP_DISP_WIN_OPTIONS);
1666         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1667         tegra_dc_writel(dc, GENERAL_ACT_REQ , DC_CMD_STATE_CONTROL);
1668
1669         tegra_dc_put(dc);
1670
1671         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
1672 }
1673
1674 /* wait for frame end interrupt or (timeout_n_frames * 1 frame duration)
1675  * whichever happens to occur first
1676  */
1677 static int tegra_dsi_wait_frame_end(struct tegra_dc *dc,
1678                                 struct tegra_dc_dsi_data *dsi,
1679                                 u32 timeout_n_frames)
1680 {
1681         int val;
1682         long timeout;
1683         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1684         struct tegra_dc_mode mode = dc->mode;
1685         u32 line_period = DIV_ROUND_UP(
1686                                 MS_TO_US(frame_period),
1687                                 mode.v_sync_width + mode.v_back_porch +
1688                                 mode.v_active + mode.v_front_porch);
1689
1690         if (timeout_n_frames < 2)
1691                 dev_WARN(&dc->ndev->dev,
1692                 "dsi: to stop at next frame give at least 2 frame delay\n");
1693
1694         INIT_COMPLETION(dc->frame_end_complete);
1695
1696         tegra_dc_get(dc);
1697
1698         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
1699         /* unmask frame end interrupt */
1700         val = tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1701
1702         timeout = wait_for_completion_interruptible_timeout(
1703                         &dc->frame_end_complete,
1704                         msecs_to_jiffies(timeout_n_frames * frame_period));
1705
1706         /* reinstate interrupt mask */
1707         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1708
1709         /* wait for v_ref_to_sync no. of lines after frame end interrupt */
1710         udelay(mode.v_ref_to_sync * line_period);
1711
1712         tegra_dc_put(dc);
1713
1714         return timeout;
1715 }
1716
1717 static void tegra_dsi_stop_dc_stream_at_frame_end(struct tegra_dc *dc,
1718                                                 struct tegra_dc_dsi_data *dsi,
1719                                                 u32 timeout_n_frames)
1720 {
1721         tegra_dsi_stop_dc_stream(dc, dsi);
1722
1723         tegra_dsi_wait_frame_end(dc, dsi, timeout_n_frames);
1724
1725         tegra_dsi_soft_reset(dsi);
1726
1727         tegra_dsi_reset_underflow_overflow(dsi);
1728 }
1729
1730 static void tegra_dc_gpio_to_spio(struct tegra_dc_dsi_data *dsi, unsigned gpio)
1731 {
1732         int err;
1733
1734         /* convert to spio */
1735         err = gpio_request(gpio, "temp_request");
1736         if (err < 0) {
1737                 dev_err(&dsi->dc->ndev->dev,
1738                         "dsi: %s: gpio request failed %d\n", __func__, err);
1739                 return;
1740         }
1741         gpio_free(gpio);
1742 }
1743
1744 static void tegra_dsi_start_dc_stream(struct tegra_dc *dc,
1745                                         struct tegra_dc_dsi_data *dsi)
1746 {
1747         u32 val;
1748
1749         tegra_dc_get(dc);
1750         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
1751
1752         tegra_dc_writel(dc, DSI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1753
1754         /* TODO: clean up */
1755         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1756                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1757                         DC_CMD_DISPLAY_POWER_CONTROL);
1758
1759         /* Configure one-shot mode or continuous mode */
1760         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1761                 /* disable LSPI/LCD_DE output */
1762                 val = PIN_OUTPUT_LSPI_OUTPUT_DIS;
1763                 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_ENABLE3);
1764
1765                 /* enable MSF & set MSF polarity */
1766                 val = MSF_ENABLE | MSF_LSPI;
1767                 if (!dsi->info.te_polarity_low)
1768                         val |= MSF_POLARITY_HIGH;
1769                 else
1770                         val |= MSF_POLARITY_LOW;
1771                 tegra_dc_writel(dc, val, DC_CMD_DISPLAY_COMMAND_OPTION0);
1772
1773                 /* set non-continuous mode */
1774                 tegra_dc_writel(dc, DISP_CTRL_MODE_NC_DISPLAY,
1775                                                 DC_CMD_DISPLAY_COMMAND);
1776                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1777                 tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
1778                                                 DC_CMD_STATE_CONTROL);
1779
1780                 if (dsi->info.te_gpio)
1781                         tegra_dc_gpio_to_spio(dsi, dsi->info.te_gpio);
1782         } else {
1783                 /* set continuous mode */
1784                 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY,
1785                                                 DC_CMD_DISPLAY_COMMAND);
1786                 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1787                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1788         }
1789
1790         tegra_dc_put(dc);
1791
1792         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
1793 }
1794
1795 static void tegra_dsi_set_dc_clk(struct tegra_dc *dc,
1796                                 struct tegra_dc_dsi_data *dsi)
1797 {
1798         u32 shift_clk_div_register;
1799         u32 val;
1800
1801         /* formula: (dsi->shift_clk_div - 1) * 2 */
1802         shift_clk_div_register = (dsi->shift_clk_div.mul -
1803                                 dsi->shift_clk_div.div) * 2 /
1804                                 dsi->shift_clk_div.div;
1805
1806         if (tegra_platform_is_fpga()) {
1807                 shift_clk_div_register = 1;
1808                 if (dsi->info.ganged_type)
1809                         shift_clk_div_register = 0;
1810         }
1811
1812         val = PIXEL_CLK_DIVIDER_PCD1 |
1813                 SHIFT_CLK_DIVIDER(shift_clk_div_register + 2);
1814
1815         /* SW WAR for bug 1045373. To make the shift clk dividor effect under
1816          * all circumstances, write N+2 to SHIFT_CLK_DIVIDER and activate it.
1817          * After 2us delay, write the target values to it. */
1818 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1819         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1820         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1821         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1822
1823         udelay(2);
1824 #endif
1825
1826         /* TODO: find out if PCD3 option is required */
1827         val = PIXEL_CLK_DIVIDER_PCD1 |
1828                 SHIFT_CLK_DIVIDER(shift_clk_div_register);
1829
1830         tegra_dc_writel(dc, val, DC_DISP_DISP_CLOCK_CONTROL);
1831 }
1832
1833 static void tegra_dsi_set_dsi_clk(struct tegra_dc *dc,
1834                         struct tegra_dc_dsi_data *dsi, u32 clk)
1835 {
1836         u32 rm;
1837         u32 pclk_khz;
1838
1839         /* Round up to MHz */
1840         rm = clk % 1000;
1841         if (rm != 0)
1842                 clk -= rm;
1843
1844         /* Set up pixel clock */
1845         pclk_khz = (clk * dsi->shift_clk_div.div) /
1846                                 dsi->shift_clk_div.mul;
1847
1848         dc->mode.pclk = pclk_khz * 1000;
1849
1850         dc->shift_clk_div.mul = dsi->shift_clk_div.mul;
1851         dc->shift_clk_div.div = dsi->shift_clk_div.div;
1852
1853         /* TODO: Define one shot work delay in board file. */
1854         /* Since for one-shot mode, refresh rate is usually set larger than
1855          * expected refresh rate, it needs at least 3 frame period. Less
1856          * delay one shot work is, more powering saving we have. */
1857         dc->one_shot_delay_ms = 4 *
1858                         DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
1859
1860         /* Enable DSI clock */
1861         tegra_dc_setup_clk(dc, dsi->dsi_clk);
1862         tegra_dsi_clk_enable(dsi);
1863         tegra_periph_reset_deassert(dsi->dsi_clk);
1864
1865         dsi->current_dsi_clk_khz = clk_get_rate(dsi->dsi_clk) / 1000;
1866         dsi->current_bit_clk_ns =  DIV_ROUND_CLOSEST((1000 * 1000),
1867                                                 (dsi->current_dsi_clk_khz * 2));
1868 }
1869
1870 static void tegra_dsi_hs_clk_out_enable(struct tegra_dc_dsi_data *dsi)
1871 {
1872         u32 val;
1873
1874         val = tegra_dsi_readl(dsi, DSI_CONTROL);
1875         val &= ~DSI_CONTROL_HS_CLK_CTRL(1);
1876
1877         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS) {
1878                 val |= DSI_CONTROL_HS_CLK_CTRL(CONTINUOUS);
1879                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
1880         } else {
1881                 val |= DSI_CONTROL_HS_CLK_CTRL(TX_ONLY);
1882                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
1883         }
1884         tegra_dsi_writel(dsi, val, DSI_CONTROL);
1885
1886         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1887         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1888         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_HIGH);
1889         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1890
1891         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
1892 }
1893
1894 static void tegra_dsi_hs_clk_out_enable_in_lp(struct tegra_dc_dsi_data *dsi)
1895 {
1896         u32 val;
1897         tegra_dsi_hs_clk_out_enable(dsi);
1898
1899         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1900         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1901         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1902         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1903 }
1904
1905 static void tegra_dsi_hs_clk_out_disable(struct tegra_dc *dc,
1906                                                 struct tegra_dc_dsi_data *dsi)
1907 {
1908         u32 val;
1909
1910         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
1911                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
1912
1913         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_POWER_CONTROL);
1914         /* stabilization delay */
1915         udelay(300);
1916
1917         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
1918         val &= ~DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(1);
1919         val |= DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1920         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
1921
1922         tegra_dsi_writel(dsi, TEGRA_DSI_ENABLE, DSI_POWER_CONTROL);
1923         /* stabilization delay */
1924         udelay(300);
1925
1926         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
1927         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
1928 }
1929
1930 static void tegra_dsi_set_control_reg_lp(struct tegra_dc_dsi_data *dsi)
1931 {
1932         u32 dsi_control;
1933         u32 host_dsi_control;
1934         u32 max_threshold;
1935
1936         dsi_control = dsi->dsi_control_val | DSI_CTRL_HOST_DRIVEN;
1937         host_dsi_control = HOST_DSI_CTRL_COMMON |
1938                         HOST_DSI_CTRL_HOST_DRIVEN |
1939                         DSI_HOST_DSI_CONTROL_HIGH_SPEED_TRANS(TEGRA_DSI_LOW);
1940         max_threshold = DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1941
1942         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1943         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1944         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1945
1946         dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1947         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
1948         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
1949 }
1950
1951 static void tegra_dsi_set_control_reg_hs(struct tegra_dc_dsi_data *dsi,
1952                                                 u8 driven_mode)
1953 {
1954         u32 dsi_control;
1955         u32 host_dsi_control;
1956         u32 max_threshold;
1957         u32 dcs_cmd;
1958
1959         dsi_control = dsi->dsi_control_val;
1960         host_dsi_control = HOST_DSI_CTRL_COMMON;
1961         max_threshold = 0;
1962         dcs_cmd = 0;
1963
1964         if (driven_mode == TEGRA_DSI_DRIVEN_BY_HOST) {
1965                 dsi_control |= DSI_CTRL_HOST_DRIVEN;
1966                 host_dsi_control |= HOST_DSI_CTRL_HOST_DRIVEN;
1967                 max_threshold =
1968                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_HOST_FIFO_DEPTH);
1969                 dsi->status.driven = DSI_DRIVEN_MODE_HOST;
1970         } else {
1971                 dsi_control |= DSI_CTRL_DC_DRIVEN;
1972                 host_dsi_control |= HOST_DSI_CTRL_DC_DRIVEN;
1973                 max_threshold =
1974                         DSI_MAX_THRESHOLD_MAX_THRESHOLD(DSI_VIDEO_FIFO_DEPTH);
1975                 dsi->status.driven = DSI_DRIVEN_MODE_DC;
1976
1977                 if (dsi->info.video_data_type ==
1978                         TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE) {
1979                         dsi_control |= DSI_CTRL_CMD_MODE;
1980                         dcs_cmd = DSI_DCS_CMDS_LT5_DCS_CMD(
1981                                 DSI_WRITE_MEMORY_START)|
1982                                 DSI_DCS_CMDS_LT3_DCS_CMD(
1983                                 DSI_WRITE_MEMORY_CONTINUE);
1984                         dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
1985                 } else {
1986                         dsi_control |= DSI_CTRL_VIDEO_MODE;
1987                         dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
1988                 }
1989         }
1990
1991         tegra_dsi_writel(dsi, max_threshold, DSI_MAX_THRESHOLD);
1992         tegra_dsi_writel(dsi, dcs_cmd, DSI_DCS_CMDS);
1993         tegra_dsi_writel(dsi, dsi_control, DSI_CONTROL);
1994         tegra_dsi_writel(dsi, host_dsi_control, DSI_HOST_DSI_CONTROL);
1995 }
1996
1997 static void tegra_dsi_pad_disable(struct tegra_dc_dsi_data *dsi)
1998 {
1999         u32 val;
2000
2001         if (dsi->info.controller_vs == DSI_VS_1) {
2002                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2003                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2004                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2005                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2006                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2007                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2008                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK
2009                                                 (TEGRA_DSI_PAD_DISABLE) |
2010                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2011                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB
2012                                                 (TEGRA_DSI_PAD_DISABLE);
2013                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2014         } else {
2015                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2016                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2017                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2018                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2019                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2020                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_DISABLE) |
2021                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_DISABLE);
2022                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2023         }
2024 }
2025
2026 static void tegra_dsi_pad_enable(struct tegra_dc_dsi_data *dsi)
2027 {
2028         u32 val;
2029
2030         if (dsi->info.controller_vs == DSI_VS_1) {
2031                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL_0_VS1);
2032                 val &= ~(DSI_PAD_CONTROL_0_VS1_PAD_PDIO(0xf) |
2033                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(0x1) |
2034                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(0xf) |
2035                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(0x1));
2036                 val |= DSI_PAD_CONTROL_0_VS1_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2037                         DSI_PAD_CONTROL_0_VS1_PAD_PDIO_CLK(
2038                                                 TEGRA_DSI_PAD_ENABLE) |
2039                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_ENAB(
2040                                                 TEGRA_DSI_PAD_ENABLE) |
2041                         DSI_PAD_CONTROL_0_VS1_PAD_PULLDN_CLK_ENAB(
2042                                                 TEGRA_DSI_PAD_ENABLE);
2043                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_0_VS1);
2044         } else {
2045                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2046                 val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
2047                         DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
2048                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
2049                 val |= DSI_PAD_CONTROL_PAD_PDIO(TEGRA_DSI_PAD_ENABLE) |
2050                         DSI_PAD_CONTROL_PAD_PDIO_CLK(TEGRA_DSI_PAD_ENABLE) |
2051                         DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_PAD_ENABLE);
2052                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2053         }
2054 }
2055 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2056 static void tegra_dsi_mipi_calibration_11x(struct tegra_dc_dsi_data *dsi)
2057 {
2058         u32 val;
2059         /* Calibration settings begin */
2060         val = (DSI_PAD_SLEWUPADJ(0x7) | DSI_PAD_SLEWDNADJ(0x7) |
2061                 DSI_PAD_LPUPADJ(0x1) | DSI_PAD_LPDNADJ(0x1) |
2062                 DSI_PAD_OUTADJCLK(0x0));
2063         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL_2_VS1);
2064
2065         if (!dsi->controller_index) {
2066                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2067                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2068                 val = MIPI_CAL_OVERIDEDSIA(0x0) |
2069                         MIPI_CAL_SELDSIA(0x1) |
2070                         MIPI_CAL_HSPDOSDSIA(0x0) |
2071                         MIPI_CAL_HSPUOSDSIA(0x4) |
2072                         MIPI_CAL_TERMOSDSIA(0x5);
2073                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2074                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2075                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2076                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2077
2078                 /* Deselect PAD C */
2079                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2080                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2081                 val &= ~(MIPI_CAL_SELDSIC(0x1));
2082                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2083                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2084
2085                 /* Deselect PAD D */
2086                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2087                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2088                 val &= ~(MIPI_CAL_SELDSID(0x1));
2089                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2090                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2091         } else {
2092                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2093                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2094                 val = MIPI_CAL_OVERIDEDSIC(0x0) |
2095                         MIPI_CAL_SELDSIC(0x1) |
2096                         MIPI_CAL_HSPDOSDSIC(0x0) |
2097                         MIPI_CAL_HSPUOSDSIC(0x4) |
2098                         MIPI_CAL_TERMOSDSIC(0x5);
2099                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2100                         MIPI_CAL_DSIC_MIPI_CAL_CONFIG_0);
2101                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2102                         MIPI_CAL_DSID_MIPI_CAL_CONFIG_0);
2103
2104                 /* Deselect PAD A */
2105                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2106                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2107                 val &= ~(MIPI_CAL_SELDSIA(0x1));
2108                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2109                         MIPI_CAL_DSIA_MIPI_CAL_CONFIG_0);
2110
2111                 /* Deselect PAD B */
2112                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2113                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2114                 val &= ~(MIPI_CAL_SELDSIB(0x1));
2115                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2116                         MIPI_CAL_DSIB_MIPI_CAL_CONFIG_0);
2117         }
2118
2119         val = tegra_mipi_cal_read(dsi->mipi_cal,
2120                 MIPI_CAL_MIPI_CAL_CTRL_0);
2121         val = MIPI_CAL_NOISE_FLT(0xa) |
2122                   MIPI_CAL_PRESCALE(0x2) |
2123                   MIPI_CAL_CLKEN_OVR(0x1) |
2124                   MIPI_CAL_AUTOCAL_EN(0x0);
2125         tegra_mipi_cal_write(dsi->mipi_cal, val,
2126                 MIPI_CAL_MIPI_CAL_CTRL_0);
2127
2128 }
2129 #endif
2130 static void tegra_dsi_pad_calibration(struct tegra_dc_dsi_data *dsi)
2131 {
2132         u32 val = 0;
2133         u32 __maybe_unused timeout = 0;
2134         if (!dsi->ulpm)
2135                 tegra_dsi_pad_enable(dsi);
2136         else
2137                 tegra_dsi_pad_disable(dsi);
2138
2139         if (dsi->info.controller_vs == DSI_VS_1) {
2140
2141                 tegra_mipi_cal_init_hw(dsi->mipi_cal);
2142
2143                 tegra_mipi_cal_clk_enable(dsi->mipi_cal);
2144
2145                 tegra_mipi_cal_write(dsi->mipi_cal,
2146                         MIPI_BIAS_PAD_E_VCLAMP_REF(0x1),
2147                         MIPI_CAL_MIPI_BIAS_PAD_CFG0_0);
2148                 tegra_mipi_cal_write(dsi->mipi_cal,
2149                         PAD_PDVREG(0x0) | PAD_VCLAMP_LEVEL(0x0),
2150                         MIPI_CAL_MIPI_BIAS_PAD_CFG2_0);
2151
2152 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2153                 tegra_dsi_mipi_calibration_11x(dsi);
2154 #endif
2155
2156 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2157                 /* Start calibration */
2158                 val = tegra_mipi_cal_read(dsi->mipi_cal,
2159                         MIPI_CAL_MIPI_CAL_CTRL_0);
2160                 val |= (MIPI_CAL_STARTCAL(0x1));
2161                 tegra_mipi_cal_write(dsi->mipi_cal, val,
2162                         MIPI_CAL_MIPI_CAL_CTRL_0);
2163
2164                 for (timeout = MIPI_DSI_AUTOCAL_TIMEOUT_USEC;
2165                                 timeout; timeout -= 100) {
2166                         val = tegra_mipi_cal_read(dsi->mipi_cal,
2167                         MIPI_CAL_CIL_MIPI_CAL_STATUS_0);
2168                         if (!(val & MIPI_CAL_ACTIVE(0x1)) &&
2169                                 (val & MIPI_AUTO_CAL_DONE(0x1))) {
2170                                         dev_info(&dsi->dc->ndev->dev, "DSI pad calibration done\n");
2171                                         break;
2172                         }
2173                         usleep_range(10, 100);
2174                 }
2175                 if (timeout <= 0)
2176                         dev_err(&dsi->dc->ndev->dev, "DSI calibration timed out\n");
2177 #endif
2178
2179                 tegra_mipi_cal_clk_disable(dsi->mipi_cal);
2180         } else {
2181                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
2182                 val &= ~(DSI_PAD_CONTROL_PAD_LPUPADJ(0x3) |
2183                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x3) |
2184                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2185                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x7) |
2186                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x7));
2187
2188                 val |= DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) |
2189                         DSI_PAD_CONTROL_PAD_LPDNADJ(0x1) |
2190                         DSI_PAD_CONTROL_PAD_PREEMP_EN(0x1) |
2191                         DSI_PAD_CONTROL_PAD_SLEWDNADJ(0x6) |
2192                         DSI_PAD_CONTROL_PAD_SLEWUPADJ(0x6);
2193
2194                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
2195
2196                 val = MIPI_CAL_TERMOSA(0x4);
2197                 tegra_vi_csi_writel(val, CSI_CILA_MIPI_CAL_CONFIG_0);
2198
2199                 val = MIPI_CAL_TERMOSB(0x4);
2200                 tegra_vi_csi_writel(val, CSI_CILB_MIPI_CAL_CONFIG_0);
2201
2202                 val = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4);
2203                 tegra_vi_csi_writel(val, CSI_DSI_MIPI_CAL_CONFIG);
2204
2205                 val = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7);
2206                 tegra_vi_csi_writel(val, CSI_MIPIBIAS_PAD_CONFIG);
2207         }
2208
2209         val = PAD_CIL_PDVREG(0x0);
2210         tegra_vi_csi_writel(val, CSI_CIL_PAD_CONFIG);
2211 }
2212
2213 static void tegra_dsi_panelB_enable(void)
2214 {
2215         unsigned int val;
2216
2217         val = readl(IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0));
2218         val |= DSIB_MODE_ENABLE;
2219         writel(val, (IO_ADDRESS(APB_MISC_GP_MIPI_PAD_CTRL_0)));
2220 }
2221
2222 static int tegra_dsi_init_hw(struct tegra_dc *dc,
2223                                 struct tegra_dc_dsi_data *dsi)
2224 {
2225         u32 i;
2226
2227         regulator_enable(dsi->avdd_dsi_csi);
2228         /* stablization delay */
2229         mdelay(50);
2230
2231         tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2232
2233         /* Stop DC stream before configuring DSI registers
2234          * to avoid visible glitches on panel during transition
2235          * from bootloader to kernel driver
2236          */
2237         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2238
2239         tegra_dsi_writel(dsi,
2240                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE),
2241                 DSI_POWER_CONTROL);
2242         /* stabilization delay */
2243         udelay(300);
2244
2245         if (dsi->info.dsi_instance)
2246                 tegra_dsi_panelB_enable();
2247
2248         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2249
2250         /* Initialize DSI registers */
2251         for (i = 0; i < ARRAY_SIZE(init_reg); i++)
2252                 tegra_dsi_writel(dsi, 0, init_reg[i]);
2253         if (dsi->info.controller_vs == DSI_VS_1) {
2254                 for (i = 0; i < ARRAY_SIZE(init_reg_vs1_ext); i++)
2255                         tegra_dsi_writel(dsi, 0, init_reg_vs1_ext[i]);
2256         }
2257
2258         tegra_dsi_pad_calibration(dsi);
2259
2260         tegra_dsi_writel(dsi,
2261                 DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
2262                 DSI_POWER_CONTROL);
2263         /* stabilization delay */
2264         udelay(300);
2265
2266         dsi->status.init = DSI_MODULE_INIT;
2267         dsi->status.lphs = DSI_LPHS_NOT_INIT;
2268         dsi->status.vtype = DSI_VIDEO_TYPE_NOT_INIT;
2269         dsi->status.driven = DSI_DRIVEN_MODE_NOT_INIT;
2270         dsi->status.clk_out = DSI_PHYCLK_OUT_DIS;
2271         dsi->status.clk_mode = DSI_PHYCLK_NOT_INIT;
2272         dsi->status.clk_burst = DSI_CLK_BURST_NOT_INIT;
2273         dsi->status.dc_stream = DSI_DC_STREAM_DISABLE;
2274         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2275
2276         return 0;
2277 }
2278
2279 static int tegra_dsi_set_to_lp_mode(struct tegra_dc *dc,
2280                         struct tegra_dc_dsi_data *dsi, u8 lp_op)
2281 {
2282         int err;
2283
2284         if (dsi->status.init != DSI_MODULE_INIT) {
2285                 err = -EPERM;
2286                 goto fail;
2287         }
2288
2289         if (dsi->status.lphs == DSI_LPHS_IN_LP_MODE &&
2290                         dsi->status.lp_op == lp_op)
2291                 goto success;
2292
2293         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2294                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2295
2296         /* disable/enable hs clk according to enable_hs_clock_on_lp_cmd_mode */
2297         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2298                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2299                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2300
2301         dsi->target_lp_clk_khz = tegra_dsi_get_lp_clk_rate(dsi, lp_op);
2302         if (dsi->current_dsi_clk_khz != dsi->target_lp_clk_khz) {
2303                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_lp_clk_khz);
2304                 tegra_dsi_set_timeout(dsi);
2305         }
2306
2307         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_LP_MODE);
2308
2309         tegra_dsi_set_control_reg_lp(dsi);
2310
2311         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_DIS) &&
2312                 (dsi->info.enable_hs_clock_on_lp_cmd_mode))
2313                 tegra_dsi_hs_clk_out_enable_in_lp(dsi);
2314
2315         dsi->status.lphs = DSI_LPHS_IN_LP_MODE;
2316         dsi->status.lp_op = lp_op;
2317         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_HOST;
2318 success:
2319         err = 0;
2320 fail:
2321         return err;
2322 }
2323
2324 static void tegra_dsi_ganged(struct tegra_dc *dc,
2325                                 struct tegra_dc_dsi_data *dsi)
2326 {
2327         u32 start = 0;
2328         u32 low_width = 0;
2329         u32 high_width = 0;
2330         u32 h_active = dc->out->modes->h_active;
2331         u32 val = 0;
2332
2333         if (dsi->info.controller_vs < DSI_VS_1) {
2334                 dev_err(&dc->ndev->dev, "dsi: ganged mode not"
2335                 "supported with current controller version\n");
2336                 return;
2337         }
2338
2339         if (dsi->info.ganged_type ==
2340                         TEGRA_DSI_GANGED_SYMMETRIC_LEFT_RIGHT) {
2341                 low_width = DIV_ROUND_UP(h_active, 2);
2342                 high_width = h_active - low_width;
2343                 if (dsi->controller_index)
2344                         start = h_active / 2;
2345                 else
2346                         start = 0;
2347         } else if (dsi->info.ganged_type ==
2348                         TEGRA_DSI_GANGED_SYMMETRIC_EVEN_ODD) {
2349                 low_width = 0x1;
2350                 high_width = 0x1;
2351                 if (dsi->controller_index)
2352                         start = 1;
2353                 else
2354                         start = 0;
2355         }
2356
2357         tegra_dsi_writel(dsi, DSI_GANGED_MODE_START_POINTER(start),
2358                                                 DSI_GANGED_MODE_START);
2359
2360         val = DSI_GANGED_MODE_SIZE_VALID_LOW_WIDTH(low_width) |
2361                 DSI_GANGED_MODE_SIZE_VALID_HIGH_WIDTH(high_width);
2362         tegra_dsi_writel(dsi, val, DSI_GANGED_MODE_SIZE);
2363
2364         tegra_dsi_writel(dsi, DSI_GANGED_MODE_CONTROL_EN(TEGRA_DSI_ENABLE),
2365                                                 DSI_GANGED_MODE_CONTROL);
2366 }
2367
2368 static int tegra_dsi_set_to_hs_mode(struct tegra_dc *dc,
2369                                         struct tegra_dc_dsi_data *dsi,
2370                                         u8 driven_mode)
2371 {
2372         int err;
2373
2374         if (dsi->status.init != DSI_MODULE_INIT) {
2375                 err = -EPERM;
2376                 goto fail;
2377         }
2378
2379         if (dsi->status.lphs == DSI_LPHS_IN_HS_MODE &&
2380                 dsi->driven_mode == driven_mode)
2381                 goto success;
2382
2383         dsi->driven_mode = driven_mode;
2384
2385         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
2386                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2387
2388         if ((dsi->status.clk_out == DSI_PHYCLK_OUT_EN) &&
2389                 (!dsi->info.enable_hs_clock_on_lp_cmd_mode))
2390                 tegra_dsi_hs_clk_out_disable(dc, dsi);
2391
2392         if (dsi->current_dsi_clk_khz != dsi->target_hs_clk_khz) {
2393                 tegra_dsi_set_dsi_clk(dc, dsi, dsi->target_hs_clk_khz);
2394                 tegra_dsi_set_timeout(dsi);
2395         }
2396
2397         tegra_dsi_set_phy_timing(dsi, DSI_LPHS_IN_HS_MODE);
2398
2399         if (driven_mode == TEGRA_DSI_DRIVEN_BY_DC) {
2400                 tegra_dsi_set_pkt_seq(dc, dsi);
2401                 tegra_dsi_set_pkt_length(dc, dsi);
2402                 tegra_dsi_set_sol_delay(dc, dsi);
2403                 tegra_dsi_set_dc_clk(dc, dsi);
2404         }
2405
2406         tegra_dsi_set_control_reg_hs(dsi, driven_mode);
2407
2408         if (dsi->info.ganged_type)
2409                 tegra_dsi_ganged(dc, dsi);
2410
2411         if (dsi->status.clk_out == DSI_PHYCLK_OUT_DIS ||
2412                 dsi->info.enable_hs_clock_on_lp_cmd_mode)
2413                 tegra_dsi_hs_clk_out_enable(dsi);
2414
2415         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
2416 success:
2417         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
2418         err = 0;
2419 fail:
2420         return err;
2421 }
2422
2423 static bool tegra_dsi_write_busy(struct tegra_dc_dsi_data *dsi)
2424 {
2425         u32 timeout = 0;
2426         bool retVal = true;
2427
2428         while (timeout <= DSI_MAX_COMMAND_DELAY_USEC) {
2429                 if (!(DSI_TRIGGER_HOST_TRIGGER(0x1) &
2430                         tegra_dsi_readl(dsi, DSI_TRIGGER))) {
2431                         retVal = false;
2432                         break;
2433                 }
2434                 udelay(DSI_COMMAND_DELAY_STEPS_USEC);
2435                 timeout += DSI_COMMAND_DELAY_STEPS_USEC;
2436         }
2437
2438         return retVal;
2439 }
2440
2441 static bool tegra_dsi_read_busy(struct tegra_dc_dsi_data *dsi)
2442 {
2443         u32 timeout = 0;
2444         bool retVal = true;
2445
2446         while (timeout <  DSI_STATUS_POLLING_DURATION_USEC) {
2447                 if (!(DSI_HOST_DSI_CONTROL_IMM_BTA(0x1) &
2448                         tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL))) {
2449                         retVal = false;
2450                         break;
2451                 }
2452                 udelay(DSI_STATUS_POLLING_DELAY_USEC);
2453                 timeout += DSI_STATUS_POLLING_DELAY_USEC;
2454         }
2455
2456         return retVal;
2457 }
2458
2459 static bool tegra_dsi_host_busy(struct tegra_dc_dsi_data *dsi)
2460 {
2461         int err = 0;
2462
2463         if (tegra_dsi_write_busy(dsi)) {
2464                 err = -EBUSY;
2465                 dev_err(&dsi->dc->ndev->dev,
2466                         "DSI trigger bit already set\n");
2467                 goto fail;
2468         }
2469
2470         if (tegra_dsi_read_busy(dsi)) {
2471                 err = -EBUSY;
2472                 dev_err(&dsi->dc->ndev->dev,
2473                         "DSI immediate bta bit already set\n");
2474                 goto fail;
2475         }
2476 fail:
2477         return (err < 0 ? true : false);
2478 }
2479
2480 static void tegra_dsi_reset_read_count(struct tegra_dc_dsi_data *dsi)
2481 {
2482         u32 val;
2483
2484         val = tegra_dsi_readl(dsi, DSI_STATUS);
2485         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
2486         if (val) {
2487                 dev_warn(&dsi->dc->ndev->dev,
2488                         "DSI read count not zero, resetting\n");
2489                 tegra_dsi_soft_reset(dsi);
2490         }
2491 }
2492
2493 static struct dsi_status *tegra_dsi_save_state_switch_to_host_cmd_mode(
2494                                                 struct tegra_dc_dsi_data *dsi,
2495                                                 struct tegra_dc *dc,
2496                                                 u8 lp_op)
2497 {
2498         struct dsi_status *init_status = NULL;
2499         int err;
2500
2501         if (dsi->status.init != DSI_MODULE_INIT ||
2502                 dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2503                 err = -EPERM;
2504                 goto fail;
2505         }
2506
2507         init_status = kzalloc(sizeof(*init_status), GFP_KERNEL);
2508         if (!init_status)
2509                 return ERR_PTR(-ENOMEM);
2510
2511         *init_status = dsi->status;
2512
2513         if (dsi->info.hs_cmd_mode_supported) {
2514                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
2515                                 TEGRA_DSI_DRIVEN_BY_HOST);
2516                 if (err < 0) {
2517                         dev_err(&dc->ndev->dev,
2518                         "Switch to HS host mode failed\n");
2519                         goto fail;
2520                 }
2521
2522                 goto success;
2523         }
2524
2525         if (dsi->status.lp_op != lp_op) {
2526                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2527                 if (err < 0) {
2528                         dev_err(&dc->ndev->dev,
2529                         "DSI failed to go to LP mode\n");
2530                         goto fail;
2531                 }
2532         }
2533 success:
2534         return init_status;
2535 fail:
2536         kfree(init_status);
2537         return ERR_PTR(err);
2538 }
2539
2540 static struct dsi_status *tegra_dsi_prepare_host_transmission(
2541                                 struct tegra_dc *dc,
2542                                 struct tegra_dc_dsi_data *dsi,
2543                                 u8 lp_op)
2544 {
2545         int err = 0;
2546         struct dsi_status *init_status;
2547         bool restart_dc_stream = false;
2548
2549         if (dsi->status.init != DSI_MODULE_INIT ||
2550                 dsi->ulpm) {
2551                 err = -EPERM;
2552                 goto fail;
2553         }
2554
2555         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE) {
2556                 restart_dc_stream = true;
2557                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
2558         }
2559
2560         if (tegra_dsi_host_busy(dsi)) {
2561                 tegra_dsi_soft_reset(dsi);
2562                 if (tegra_dsi_host_busy(dsi)) {
2563                         err = -EBUSY;
2564                         dev_err(&dc->ndev->dev, "DSI host busy\n");
2565                         goto fail;
2566                 }
2567         }
2568
2569         if (lp_op == DSI_LP_OP_READ)
2570                 tegra_dsi_reset_read_count(dsi);
2571
2572         if (dsi->status.lphs == DSI_LPHS_NOT_INIT) {
2573                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
2574                 if (err < 0) {
2575                         dev_err(&dc->ndev->dev, "Failed to config LP write\n");
2576                         goto fail;
2577                 }
2578         }
2579
2580         init_status = tegra_dsi_save_state_switch_to_host_cmd_mode
2581                                         (dsi, dc, lp_op);
2582         if (IS_ERR_OR_NULL(init_status)) {
2583                 err = PTR_ERR(init_status);
2584                 dev_err(&dc->ndev->dev, "DSI state saving failed\n");
2585                 goto fail;
2586         }
2587
2588         if (restart_dc_stream)
2589                 init_status->dc_stream = DSI_DC_STREAM_ENABLE;
2590
2591 #if DSI_USE_SYNC_POINTS
2592         if (atomic_read(&dsi_syncpt_rst))
2593                 tegra_dsi_syncpt_reset(dsi);
2594 #endif
2595
2596         return init_status;
2597 fail:
2598         return ERR_PTR(err);
2599 }
2600
2601 static int tegra_dsi_restore_state(struct tegra_dc *dc,
2602                                 struct tegra_dc_dsi_data *dsi,
2603                                 struct dsi_status *init_status)
2604 {
2605         int err = 0;
2606
2607         if (init_status->lphs == DSI_LPHS_IN_LP_MODE) {
2608                 err = tegra_dsi_set_to_lp_mode(dc, dsi, init_status->lp_op);
2609                 if (err < 0) {
2610                         dev_err(&dc->ndev->dev,
2611                                 "Failed to config LP mode\n");
2612                         goto fail;
2613                 }
2614                 goto success;
2615         }
2616
2617         if (init_status->lphs == DSI_LPHS_IN_HS_MODE) {
2618                 u8 driven = (init_status->driven == DSI_DRIVEN_MODE_DC) ?
2619                         TEGRA_DSI_DRIVEN_BY_DC : TEGRA_DSI_DRIVEN_BY_HOST;
2620                 err = tegra_dsi_set_to_hs_mode(dc, dsi, driven);
2621                 if (err < 0) {
2622                         dev_err(&dc->ndev->dev, "Failed to config HS mode\n");
2623                         goto fail;
2624                 }
2625         }
2626
2627         if (init_status->dc_stream == DSI_DC_STREAM_ENABLE)
2628                 tegra_dsi_start_dc_stream(dc, dsi);
2629 success:
2630 fail:
2631         kfree(init_status);
2632         return err;
2633 }
2634
2635 static int tegra_dsi_host_trigger(struct tegra_dc_dsi_data *dsi)
2636 {
2637         int status = 0;
2638
2639         if (tegra_dsi_readl(dsi, DSI_TRIGGER)) {
2640                 status = -EBUSY;
2641                 goto fail;
2642         }
2643
2644         tegra_dsi_writel(dsi,
2645                 DSI_TRIGGER_HOST_TRIGGER(TEGRA_DSI_ENABLE), DSI_TRIGGER);
2646
2647 #if DSI_USE_SYNC_POINTS
2648         status = tegra_dsi_syncpt(dsi);
2649         if (status < 0) {
2650                 dev_err(&dsi->dc->ndev->dev,
2651                         "DSI syncpt for host trigger failed\n");
2652                 goto fail;
2653         }
2654 #else
2655         if (tegra_dsi_write_busy(dsi)) {
2656                 status = -EBUSY;
2657                 dev_err(&dsi->dc->ndev->dev,
2658                         "Timeout waiting on write completion\n");
2659         }
2660 #endif
2661
2662 fail:
2663         return status;
2664 }
2665
2666 static int _tegra_dsi_write_data(struct tegra_dc_dsi_data *dsi,
2667                                         u8 *pdata, u8 data_id, u16 data_len)
2668 {
2669         u8 virtual_channel;
2670         u32 val;
2671         int err;
2672
2673         err = 0;
2674
2675         virtual_channel = dsi->info.virtual_channel <<
2676                                                 DSI_VIR_CHANNEL_BIT_POSITION;
2677
2678         /* always use hw for ecc */
2679         val = (virtual_channel | data_id) << 0 |
2680                         data_len << 8;
2681         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2682
2683         /* if pdata != NULL, pkt type is long pkt */
2684         if (pdata != NULL) {
2685                 while (data_len) {
2686                         if (data_len >= 4) {
2687                                 val = ((u32 *) pdata)[0];
2688                                 data_len -= 4;
2689                                 pdata += 4;
2690                         } else {
2691                                 val = 0;
2692                                 memcpy(&val, pdata, data_len);
2693                                 pdata += data_len;
2694                                 data_len = 0;
2695                         }
2696                         tegra_dsi_writel(dsi, val, DSI_WR_DATA);
2697                 }
2698         }
2699
2700         err = tegra_dsi_host_trigger(dsi);
2701         if (err < 0)
2702                 dev_err(&dsi->dc->ndev->dev, "DSI host trigger failed\n");
2703
2704         return err;
2705 }
2706
2707 static void tegra_dc_dsi_hold_host(struct tegra_dc *dc)
2708 {
2709         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2710
2711         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2712                 atomic_inc(&dsi->host_ref);
2713                 tegra_dsi_host_resume(dc);
2714         }
2715 }
2716
2717 static void tegra_dc_dsi_release_host(struct tegra_dc *dc)
2718 {
2719         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
2720
2721         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE) {
2722                 atomic_dec(&dsi->host_ref);
2723
2724                 if (!atomic_read(&dsi->host_ref) &&
2725                     (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE))
2726                         schedule_delayed_work(&dsi->idle_work, dsi->idle_delay);
2727         }
2728 }
2729
2730 static void tegra_dc_dsi_idle_work(struct work_struct *work)
2731 {
2732         struct tegra_dc_dsi_data *dsi = container_of(
2733                 to_delayed_work(work), struct tegra_dc_dsi_data, idle_work);
2734
2735         if (dsi->dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2736                 tegra_dsi_host_suspend(dsi->dc);
2737 }
2738
2739 static int tegra_dsi_write_data_nosync(struct tegra_dc *dc,
2740                         struct tegra_dc_dsi_data *dsi,
2741                         u8 *pdata, u8 data_id, u16 data_len)
2742 {
2743         int err = 0;
2744         struct dsi_status *init_status;
2745
2746         init_status = tegra_dsi_prepare_host_transmission(
2747                                 dc, dsi, DSI_LP_OP_WRITE);
2748         if (IS_ERR_OR_NULL(init_status)) {
2749                 err = PTR_ERR(init_status);
2750                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
2751                 goto fail;
2752         }
2753
2754         err = _tegra_dsi_write_data(dsi, pdata, data_id, data_len);
2755 fail:
2756         err = tegra_dsi_restore_state(dc, dsi, init_status);
2757         if (err < 0)
2758                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
2759
2760         return err;
2761 }
2762
2763 int tegra_dsi_write_data(struct tegra_dc *dc,
2764                         struct tegra_dc_dsi_data *dsi,
2765                         u8 *pdata, u8 data_id, u16 data_len)
2766 {
2767         int err;
2768
2769         tegra_dc_io_start(dc);
2770         tegra_dc_dsi_hold_host(dc);
2771
2772         err = tegra_dsi_write_data_nosync(dc, dsi, pdata, data_id, data_len);
2773
2774         tegra_dc_dsi_release_host(dc);
2775         tegra_dc_io_end(dc);
2776
2777         return err;
2778 }
2779
2780 EXPORT_SYMBOL(tegra_dsi_write_data);
2781
2782 static int tegra_dsi_send_panel_cmd(struct tegra_dc *dc,
2783                                         struct tegra_dc_dsi_data *dsi,
2784                                         struct tegra_dsi_cmd *cmd,
2785                                         u32 n_cmd)
2786 {
2787         u32 i;
2788         int err;
2789
2790         err = 0;
2791         for (i = 0; i < n_cmd; i++) {
2792                 struct tegra_dsi_cmd *cur_cmd;
2793                 cur_cmd = &cmd[i];
2794
2795                 /*
2796                  * Some Panels need reset midway in the command sequence.
2797                  */
2798                 if (cur_cmd->cmd_type == TEGRA_DSI_GPIO_SET) {
2799                         gpio_set_value(cur_cmd->sp_len_dly.gpio,
2800                                        cur_cmd->data_id);
2801                 } else if (cur_cmd->cmd_type == TEGRA_DSI_DELAY_MS) {
2802                         mdelay(cur_cmd->sp_len_dly.delay_ms);
2803                 } else if (cur_cmd->cmd_type == TEGRA_DSI_SEND_FRAME) {
2804                                 tegra_dsi_send_dc_frames(dc,
2805                                                 dsi,
2806                                                 cur_cmd->sp_len_dly.frame_cnt);
2807                 } else {
2808                         err = tegra_dsi_write_data_nosync(dc, dsi,
2809                                                 cur_cmd->pdata,
2810                                                 cur_cmd->data_id,
2811                                                 cur_cmd->sp_len_dly.data_len);
2812                         mdelay(1);
2813                         if (err < 0)
2814                                 break;
2815                 }
2816         }
2817         return err;
2818 }
2819
2820 static u8 tegra_dsi_ecc(u32 header)
2821 {
2822         char ecc_parity[24] = {
2823                 0x07, 0x0b, 0x0d, 0x0e, 0x13, 0x15, 0x16, 0x19,
2824                 0x1a, 0x1c, 0x23, 0x25, 0x26, 0x29, 0x2a, 0x2c,
2825                 0x31, 0x32, 0x34, 0x38, 0x1f, 0x2f, 0x37, 0x3b
2826         };
2827         u8 ecc_byte;
2828         int i;
2829
2830         ecc_byte = 0;
2831         for (i = 0; i < 24; i++)
2832                 ecc_byte ^= ((header >> i) & 1) ? ecc_parity[i] : 0x00;
2833
2834         return ecc_byte;
2835 }
2836
2837 static u16 tegra_dsi_cs(char *pdata, u16 data_len)
2838 {
2839         u16 byte_cnt;
2840         u8 bit_cnt;
2841         char curr_byte;
2842         u16 crc = 0xFFFF;
2843         u16 poly = 0x8408;
2844
2845         if (data_len > 0) {
2846                 for (byte_cnt = 0; byte_cnt < data_len; byte_cnt++) {
2847                         curr_byte = pdata[byte_cnt];
2848                         for (bit_cnt = 0; bit_cnt < 8; bit_cnt++) {
2849                                 if (((crc & 0x0001 ) ^
2850                                         (curr_byte & 0x0001)) > 0)
2851                                         crc = ((crc >> 1) & 0x7FFF) ^ poly;
2852                                 else
2853                                         crc = (crc >> 1) & 0x7FFF;
2854
2855                                 curr_byte = (curr_byte >> 1 ) & 0x7F;
2856                         }
2857                 }
2858         }
2859         return crc;
2860 }
2861
2862 static int tegra_dsi_dcs_pkt_seq_ctrl_init(struct tegra_dc_dsi_data *dsi,
2863                                                 struct tegra_dsi_cmd *cmd)
2864 {
2865         u8 virtual_channel;
2866         u32 val;
2867         u16 data_len = cmd->sp_len_dly.data_len;
2868         u8 seq_ctrl_reg = 0;
2869
2870         virtual_channel = dsi->info.virtual_channel <<
2871                                 DSI_VIR_CHANNEL_BIT_POSITION;
2872
2873         val = (virtual_channel | cmd->data_id) << 0 |
2874                 data_len << 8;
2875
2876         val |= tegra_dsi_ecc(val) << 24;
2877
2878         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 + seq_ctrl_reg++);
2879
2880         /* if pdata != NULL, pkt type is long pkt */
2881         if (cmd->pdata != NULL) {
2882                 u8 *pdata;
2883                 u8 *pdata_mem;
2884                 /* allocate memory for pdata + 2 bytes checksum */
2885                 pdata_mem = kzalloc(sizeof(u8) * data_len + 2, GFP_KERNEL);
2886                 if (!pdata_mem) {
2887                         dev_err(&dsi->dc->ndev->dev, "dsi: memory err\n");
2888                         tegra_dsi_soft_reset(dsi);
2889                         return -ENOMEM;
2890                 }
2891
2892                 memcpy(pdata_mem, cmd->pdata, data_len);
2893                 pdata = pdata_mem;
2894                 *((u16 *)(pdata + data_len)) = tegra_dsi_cs(pdata, data_len);
2895
2896                 /* data_len = length of pdata + 2 byte checksum */
2897                 data_len += 2;
2898
2899                 while (data_len) {
2900                         if (data_len >= 4) {
2901                                 val = ((u32 *) pdata)[0];
2902                                 data_len -= 4;
2903                                 pdata += 4;
2904                         } else {
2905                                 val = 0;
2906                                 memcpy(&val, pdata, data_len);
2907                                 pdata += data_len;
2908                                 data_len = 0;
2909                         }
2910                         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_DATA_0 +
2911                                                         seq_ctrl_reg++);
2912                 }
2913                 kfree(pdata_mem);
2914         }
2915
2916         return 0;
2917 }
2918
2919 int tegra_dsi_start_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi,
2920                                                 struct tegra_dsi_cmd *cmd)
2921 {
2922 #define PKT_HEADER_LEN_BYTE     4
2923 #define CHECKSUM_LEN_BYTE       2
2924
2925         int err = 0;
2926         u32 val;
2927         u16 tot_pkt_len = PKT_HEADER_LEN_BYTE;
2928         struct tegra_dc *dc = dsi->dc;
2929
2930         if (cmd->cmd_type != TEGRA_DSI_PACKET_CMD)
2931                 return -EINVAL;
2932
2933         mutex_lock(&dsi->lock);
2934         tegra_dc_io_start(dc);
2935         tegra_dc_dsi_hold_host(dc);
2936
2937 #if DSI_USE_SYNC_POINTS
2938         atomic_set(&dsi_syncpt_rst, 1);
2939 #endif
2940
2941         err = tegra_dsi_dcs_pkt_seq_ctrl_init(dsi, cmd);
2942         if (err < 0) {
2943                 dev_err(&dsi->dc->ndev->dev,
2944                         "dsi: dcs pkt seq ctrl init failed\n");
2945                 goto fail;
2946         }
2947
2948         if (cmd->pdata) {
2949                 u16 data_len = cmd->sp_len_dly.data_len;
2950                 tot_pkt_len += data_len + CHECKSUM_LEN_BYTE;
2951         }
2952
2953         val = DSI_INIT_SEQ_CONTROL_DSI_FRAME_INIT_BYTE_COUNT(tot_pkt_len) |
2954                 DSI_INIT_SEQ_CONTROL_DSI_SEND_INIT_SEQUENCE(
2955                                                 TEGRA_DSI_ENABLE);
2956         tegra_dsi_writel(dsi, val, DSI_INIT_SEQ_CONTROL);
2957
2958 fail:
2959         tegra_dc_dsi_release_host(dc);
2960         tegra_dc_io_end(dc);
2961         mutex_unlock(&dsi->lock);
2962         return err;
2963
2964 #undef PKT_HEADER_LEN_BYTE
2965 #undef CHECKSUM_LEN_BYTE
2966 }
2967 EXPORT_SYMBOL(tegra_dsi_start_host_cmd_v_blank_dcs);
2968
2969 void tegra_dsi_stop_host_cmd_v_blank_dcs(struct tegra_dc_dsi_data * dsi)
2970 {
2971         struct tegra_dc *dc = dsi->dc;
2972         u32 cnt;
2973
2974         mutex_lock(&dsi->lock);
2975         tegra_dc_io_start(dc);
2976         tegra_dc_dsi_hold_host(dc);
2977
2978 #if DSI_USE_SYNC_POINTS
2979         if (atomic_read(&dsi_syncpt_rst)) {
2980                 tegra_dsi_wait_frame_end(dc, dsi, 2);
2981                 tegra_dsi_syncpt_reset(dsi);
2982                 atomic_set(&dsi_syncpt_rst, 0);
2983         }
2984 #endif
2985
2986         tegra_dsi_writel(dsi, TEGRA_DSI_DISABLE, DSI_INIT_SEQ_CONTROL);
2987
2988         /* clear seq data registers */
2989         for (cnt = 0; cnt < 8; cnt++)
2990                 tegra_dsi_writel(dsi, 0, DSI_INIT_SEQ_DATA_0 + cnt);
2991
2992         tegra_dc_dsi_release_host(dc);
2993         tegra_dc_io_end(dc);
2994
2995         mutex_unlock(&dsi->lock);
2996 }
2997 EXPORT_SYMBOL(tegra_dsi_stop_host_cmd_v_blank_dcs);
2998
2999 static int tegra_dsi_bta(struct tegra_dc_dsi_data *dsi)
3000 {
3001         u32 val;
3002         int err = 0;
3003
3004         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3005         val |= DSI_HOST_DSI_CONTROL_IMM_BTA(TEGRA_DSI_ENABLE);
3006         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3007
3008 #if DSI_USE_SYNC_POINTS
3009         err = tegra_dsi_syncpt(dsi);
3010         if (err < 0) {
3011                 dev_err(&dsi->dc->ndev->dev,
3012                         "DSI syncpt for bta failed\n");
3013         }
3014 #else
3015         if (tegra_dsi_read_busy(dsi)) {
3016                 err = -EBUSY;
3017                 dev_err(&dsi->dc->ndev->dev,
3018                         "Timeout wating on read completion\n");
3019         }
3020 #endif
3021
3022         return err;
3023 }
3024
3025 static int tegra_dsi_parse_read_response(struct tegra_dc *dc,
3026                                         u32 rd_fifo_cnt, u8 *read_fifo)
3027 {
3028         int err;
3029         u32 payload_size;
3030
3031         payload_size = 0;
3032         err = 0;
3033
3034         switch (read_fifo[0]) {
3035         case DSI_ESCAPE_CMD:
3036                 dev_info(&dc->ndev->dev, "escape cmd[0x%x]\n", read_fifo[0]);
3037                 break;
3038         case DSI_ACK_NO_ERR:
3039                 dev_info(&dc->ndev->dev,
3040                         "Panel ack, no err[0x%x]\n", read_fifo[0]);
3041                 return err;
3042         default:
3043                 dev_info(&dc->ndev->dev, "Invalid read response\n");
3044                 break;
3045         }
3046
3047         switch (read_fifo[4] & 0xff) {
3048         case GEN_LONG_RD_RES:
3049                 /* Fall through */
3050         case DCS_LONG_RD_RES:
3051                 payload_size = (read_fifo[5] |
3052                                 (read_fifo[6] << 8)) & 0xFFFF;
3053                 dev_info(&dc->ndev->dev, "Long read response Packet\n"
3054                                 "payload_size[0x%x]\n", payload_size);
3055                 break;
3056         case GEN_1_BYTE_SHORT_RD_RES:
3057                 /* Fall through */
3058         case DCS_1_BYTE_SHORT_RD_RES:
3059                 payload_size = 1;
3060                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3061                         "payload_size[0x%x]\n", payload_size);
3062                 break;
3063         case GEN_2_BYTE_SHORT_RD_RES:
3064                 /* Fall through */
3065         case DCS_2_BYTE_SHORT_RD_RES:
3066                 payload_size = 2;
3067                 dev_info(&dc->ndev->dev, "Short read response Packet\n"
3068                         "payload_size[0x%x]\n", payload_size);
3069                 break;
3070         case ACK_ERR_RES:
3071                 payload_size = 2;
3072                 dev_info(&dc->ndev->dev, "Acknowledge error report response\n"
3073                         "Packet payload_size[0x%x]\n", payload_size);
3074                 break;
3075         default:
3076                 dev_info(&dc->ndev->dev, "Invalid response packet\n");
3077                 err = -EINVAL;
3078                 break;
3079         }
3080         return err;
3081 }
3082
3083 static int tegra_dsi_read_fifo(struct tegra_dc *dc,
3084                         struct tegra_dc_dsi_data *dsi,
3085                         u8 *read_fifo)
3086 {
3087         u32 val;
3088         u32 i;
3089         u32 poll_time = 0;
3090         u32 rd_fifo_cnt;
3091         int err = 0;
3092         u8 *read_fifo_cp = read_fifo;
3093
3094         while (poll_time <  DSI_DELAY_FOR_READ_FIFO) {
3095                 mdelay(1);
3096                 val = tegra_dsi_readl(dsi, DSI_STATUS);
3097                 rd_fifo_cnt = val & DSI_STATUS_RD_FIFO_COUNT(0x1f);
3098                 if (rd_fifo_cnt << 2 > DSI_READ_FIFO_DEPTH) {
3099                         dev_err(&dc->ndev->dev,
3100                         "DSI RD_FIFO_CNT is greater than RD_FIFO_DEPTH\n");
3101                         break;
3102                 }
3103                 poll_time++;
3104         }
3105
3106         if (rd_fifo_cnt == 0) {
3107                 dev_info(&dc->ndev->dev,
3108                         "DSI RD_FIFO_CNT is zero\n");
3109                 err = -EINVAL;
3110                 goto fail;
3111         }
3112
3113         if (val & (DSI_STATUS_LB_UNDERFLOW(0x1) |
3114                 DSI_STATUS_LB_OVERFLOW(0x1))) {
3115                 dev_warn(&dc->ndev->dev,
3116                         "DSI overflow/underflow error\n");
3117         }
3118
3119         /* Read data from FIFO */
3120         for (i = 0; i < rd_fifo_cnt; i++) {
3121                 val = tegra_dsi_readl(dsi, DSI_RD_DATA);
3122                 if (enable_read_debug)
3123                         dev_info(&dc->ndev->dev,
3124                         "Read data[%d]: 0x%x\n", i, val);
3125                 memcpy(read_fifo, &val, 4);
3126                 read_fifo += 4;
3127         }
3128
3129         /* Make sure all the data is read from the FIFO */
3130         val = tegra_dsi_readl(dsi, DSI_STATUS);
3131         val &= DSI_STATUS_RD_FIFO_COUNT(0x1f);
3132         if (val)
3133                 dev_err(&dc->ndev->dev, "DSI FIFO_RD_CNT not zero"
3134                 " even after reading FIFO_RD_CNT words from read fifo\n");
3135
3136         if (enable_read_debug) {
3137                 err =
3138                 tegra_dsi_parse_read_response(dc, rd_fifo_cnt, read_fifo_cp);
3139                 if (err < 0)
3140                         dev_warn(&dc->ndev->dev, "Unexpected read data\n");
3141         }
3142 fail:
3143         return err;
3144 }
3145
3146 int tegra_dsi_read_data(struct tegra_dc *dc,
3147                                 struct tegra_dc_dsi_data *dsi,
3148                                 u32 max_ret_payload_size,
3149                                 u32 panel_reg_addr, u8 *read_data)
3150 {
3151         int err = 0;
3152         struct dsi_status *init_status;
3153
3154         if (!dsi->enabled) {
3155                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3156                 return -EINVAL;
3157         }
3158         tegra_dc_dsi_hold_host(dc);
3159         mutex_lock(&dsi->lock);
3160         tegra_dc_io_start(dc);
3161         clk_prepare_enable(dsi->dsi_fixed_clk);
3162         clk_prepare_enable(dsi->dsi_lp_clk);
3163         init_status = tegra_dsi_prepare_host_transmission(
3164                                 dc, dsi, DSI_LP_OP_WRITE);
3165         if (IS_ERR_OR_NULL(init_status)) {
3166                 err = PTR_ERR(init_status);
3167                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3168                 goto fail;
3169         }
3170
3171         /* Set max return payload size in words */
3172         err = _tegra_dsi_write_data(dsi, NULL,
3173                 dsi_command_max_return_pkt_size,
3174                 max_ret_payload_size);
3175         if (err < 0) {
3176                 dev_err(&dc->ndev->dev,
3177                                 "DSI write failed\n");
3178                 goto fail;
3179         }
3180
3181         /* DCS to read given panel register */
3182         err = _tegra_dsi_write_data(dsi, NULL,
3183                 dsi_command_dcs_read_with_no_params,
3184                 panel_reg_addr);
3185         if (err < 0) {
3186                 dev_err(&dc->ndev->dev,
3187                                 "DSI write failed\n");
3188                 goto fail;
3189         }
3190
3191         tegra_dsi_reset_read_count(dsi);
3192
3193         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3194                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3195                 if (err < 0) {
3196                         dev_err(&dc->ndev->dev,
3197                         "DSI failed to go to LP read mode\n");
3198                         goto fail;
3199                 }
3200         }
3201
3202         err = tegra_dsi_bta(dsi);
3203         if (err < 0) {
3204                 dev_err(&dc->ndev->dev,
3205                         "DSI IMM BTA timeout\n");
3206                 goto fail;
3207         }
3208
3209         err = tegra_dsi_read_fifo(dc, dsi, read_data);
3210         if (err < 0) {
3211                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3212                 goto fail;
3213         }
3214 fail:
3215         err = tegra_dsi_restore_state(dc, dsi, init_status);
3216         if (err < 0)
3217                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3218         clk_disable_unprepare(dsi->dsi_lp_clk);
3219         clk_disable_unprepare(dsi->dsi_fixed_clk);
3220         tegra_dc_io_end(dc);
3221         mutex_unlock(&dsi->lock);
3222         tegra_dc_dsi_release_host(dc);
3223         return err;
3224 }
3225 EXPORT_SYMBOL(tegra_dsi_read_data);
3226
3227 int tegra_dsi_panel_sanity_check(struct tegra_dc *dc,
3228                                 struct tegra_dc_dsi_data *dsi)
3229 {
3230         int err = 0;
3231         u8 read_fifo[DSI_READ_FIFO_DEPTH];
3232         struct dsi_status *init_status;
3233         static struct tegra_dsi_cmd dsi_nop_cmd =
3234                         DSI_CMD_SHORT(0x05, 0x0, 0x0);
3235
3236         if (!dsi->enabled) {
3237                 dev_err(&dc->ndev->dev, "DSI controller suspended\n");
3238                 return -EINVAL;
3239         }
3240         tegra_dc_dsi_hold_host(dc);
3241         tegra_dc_io_start(dc);
3242         clk_prepare_enable(dsi->dsi_fixed_clk);
3243         clk_prepare_enable(dsi->dsi_lp_clk);
3244
3245         init_status = tegra_dsi_prepare_host_transmission(
3246                                         dc, dsi, DSI_LP_OP_WRITE);
3247         if (IS_ERR_OR_NULL(init_status)) {
3248                 err = PTR_ERR(init_status);
3249                 dev_err(&dc->ndev->dev, "DSI host config failed\n");
3250                 goto fail;
3251         }
3252
3253         err = _tegra_dsi_write_data(dsi, NULL, dsi_nop_cmd.data_id, 0x0);
3254         if (err < 0) {
3255                 dev_err(&dc->ndev->dev, "DSI nop write failed\n");
3256                 goto fail;
3257         }
3258
3259         tegra_dsi_reset_read_count(dsi);
3260
3261         if (dsi->status.lp_op == DSI_LP_OP_WRITE) {
3262                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_READ);
3263                 if (err < 0) {
3264                         dev_err(&dc->ndev->dev,
3265                         "DSI failed to go to LP read mode\n");
3266                         goto fail;
3267                 }
3268         }
3269
3270         err = tegra_dsi_bta(dsi);
3271         if (err < 0) {
3272                 dev_err(&dc->ndev->dev, "DSI BTA failed\n");
3273                 goto fail;
3274         }
3275
3276         err = tegra_dsi_read_fifo(dc, dsi, read_fifo);
3277         if (err < 0) {
3278                 dev_err(&dc->ndev->dev, "DSI read fifo failure\n");
3279                 goto fail;
3280         }
3281
3282         if (read_fifo[0] != DSI_ACK_NO_ERR) {
3283                 dev_warn(&dc->ndev->dev,
3284                         "Ack no error trigger message not received\n");
3285                 err = -EAGAIN;
3286         }
3287 fail:
3288         err = tegra_dsi_restore_state(dc, dsi, init_status);
3289         if (err < 0)
3290                 dev_err(&dc->ndev->dev, "Failed to restore prev state\n");
3291         clk_disable_unprepare(dsi->dsi_lp_clk);
3292         clk_disable_unprepare(dsi->dsi_fixed_clk);
3293         tegra_dc_io_end(dc);
3294         tegra_dc_dsi_release_host(dc);
3295         return err;
3296 }
3297 EXPORT_SYMBOL(tegra_dsi_panel_sanity_check);
3298
3299 static int tegra_dsi_enter_ulpm(struct tegra_dc_dsi_data *dsi)
3300 {
3301         u32 val;
3302         int ret = 0;
3303
3304 #if DSI_USE_SYNC_POINTS
3305         if (atomic_read(&dsi_syncpt_rst))
3306                 tegra_dsi_syncpt_reset(dsi);
3307 #endif
3308
3309         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3310         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3311         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(ENTER_ULPM);
3312         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3313
3314 #if DSI_USE_SYNC_POINTS
3315         ret = tegra_dsi_syncpt(dsi);
3316         if (ret < 0) {
3317                 dev_err(&dsi->dc->ndev->dev,
3318                         "DSI syncpt for ulpm enter failed\n");
3319                 return ret;
3320         }
3321 #else
3322         /* TODO: Find exact delay required */
3323         mdelay(10);
3324 #endif
3325         dsi->ulpm = true;
3326
3327         return ret;
3328 }
3329
3330 static int tegra_dsi_exit_ulpm(struct tegra_dc_dsi_data *dsi)
3331 {
3332         u32 val;
3333         int ret = 0;
3334
3335 #if DSI_USE_SYNC_POINTS
3336         if (atomic_read(&dsi_syncpt_rst))
3337                 tegra_dsi_syncpt_reset(dsi);
3338 #endif
3339
3340         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3341         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(3);
3342         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(EXIT_ULPM);
3343         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3344
3345 #if DSI_USE_SYNC_POINTS
3346         ret = tegra_dsi_syncpt(dsi);
3347         if (ret < 0) {
3348                 dev_err(&dsi->dc->ndev->dev,
3349                         "DSI syncpt for ulpm exit failed\n");
3350                 return ret;
3351         }
3352 #else
3353         /* TODO: Find exact delay required */
3354         mdelay(10);
3355 #endif
3356         dsi->ulpm = false;
3357
3358         val = tegra_dsi_readl(dsi, DSI_HOST_DSI_CONTROL);
3359         val &= ~DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(0x3);
3360         val |= DSI_HOST_DSI_CONTROL_ULTRA_LOW_POWER(NORMAL);
3361         tegra_dsi_writel(dsi, val, DSI_HOST_DSI_CONTROL);
3362
3363         return ret;
3364 }
3365
3366 static void tegra_dsi_send_dc_frames(struct tegra_dc *dc,
3367                                      struct tegra_dc_dsi_data *dsi,
3368                                      int no_of_frames)
3369 {
3370         int err;
3371         u32 frame_period = DIV_ROUND_UP(S_TO_MS(1), dsi->info.refresh_rate);
3372         u8 lp_op = dsi->status.lp_op;
3373         bool switch_to_lp = (dsi->status.lphs == DSI_LPHS_IN_LP_MODE);
3374
3375         if (dsi->status.lphs != DSI_LPHS_IN_HS_MODE) {
3376                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3377                                 TEGRA_DSI_DRIVEN_BY_DC);
3378                 if (err < 0) {
3379                         dev_err(&dc->ndev->dev,
3380                                 "Switch to HS host mode failed\n");
3381                         return;
3382                 }
3383         }
3384
3385         /*
3386          * Some panels need DC frames be sent under certain
3387          * conditions. We are working on the right fix for this
3388          * requirement, while using this current fix.
3389          */
3390         tegra_dsi_start_dc_stream(dc, dsi);
3391
3392         /*
3393          * Send frames in Continuous or One-shot mode.
3394          */
3395         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3396                 while (no_of_frames--) {
3397                         tegra_dc_writel(dc, GENERAL_ACT_REQ | NC_HOST_TRIG,
3398                                         DC_CMD_STATE_CONTROL);
3399                         mdelay(frame_period);
3400                 }
3401         } else
3402                 mdelay(no_of_frames * frame_period);
3403
3404         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
3405
3406         if (switch_to_lp) {
3407                 err = tegra_dsi_set_to_lp_mode(dc, dsi, lp_op);
3408                 if (err < 0)
3409                         dev_err(&dc->ndev->dev,
3410                                 "DSI failed to go to LP mode\n");
3411         }
3412 }
3413
3414 static void tegra_dsi_setup_initialized_panel(struct tegra_dc_dsi_data *dsi)
3415 {
3416         regulator_enable(dsi->avdd_dsi_csi);
3417
3418         dsi->status.init = DSI_MODULE_INIT;
3419         dsi->status.lphs = DSI_LPHS_IN_HS_MODE;
3420         dsi->status.driven = DSI_DRIVEN_MODE_DC;
3421         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3422         dsi->status.clk_out = DSI_PHYCLK_OUT_EN;
3423         dsi->status.lp_op = DSI_LP_OP_NOT_INIT;
3424         dsi->status.dc_stream = DSI_DC_STREAM_ENABLE;
3425
3426         if (dsi->info.video_clock_mode == TEGRA_DSI_VIDEO_CLOCK_CONTINUOUS)
3427                 dsi->status.clk_mode = DSI_PHYCLK_CONTINUOUS;
3428         else
3429                 dsi->status.clk_mode = DSI_PHYCLK_TX_ONLY;
3430
3431         if (!(dsi->info.ganged_type)) {
3432                 if (dsi->info.video_burst_mode ==
3433                         TEGRA_DSI_VIDEO_NONE_BURST_MODE ||
3434                         dsi->info.video_burst_mode ==
3435                         TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END)
3436                         dsi->status.clk_burst = DSI_CLK_BURST_NONE_BURST;
3437                 else
3438                         dsi->status.clk_burst = DSI_CLK_BURST_BURST_MODE;
3439         }
3440
3441         if (dsi->info.video_data_type == TEGRA_DSI_VIDEO_TYPE_COMMAND_MODE)
3442                 dsi->status.vtype = DSI_VIDEO_TYPE_CMD_MODE;
3443         else
3444                 dsi->status.vtype = DSI_VIDEO_TYPE_VIDEO_MODE;
3445
3446         tegra_dsi_clk_enable(dsi);
3447
3448         dsi->enabled = true;
3449 }
3450
3451 static void _tegra_dc_dsi_enable(struct tegra_dc *dc)
3452 {
3453         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3454         int err = 0;
3455
3456         mutex_lock(&dsi->lock);
3457         tegra_dc_io_start(dc);
3458
3459         /*
3460          * Do not program this panel as the bootloader as has already
3461          * initialized it. This avoids periods of blanking during boot.
3462          */
3463         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE) {
3464                 tegra_dsi_setup_initialized_panel(dsi);
3465                 goto fail;
3466         }
3467
3468         /* Stop DC stream before configuring DSI registers
3469          * to avoid visible glitches on panel during transition
3470          * from bootloader to kernel driver
3471          */
3472         tegra_dsi_stop_dc_stream(dc, dsi);
3473
3474         if (dsi->enabled) {
3475                 if (dsi->ulpm) {
3476                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3477                                 dev_err(&dc->ndev->dev,
3478                                         "DSI failed to exit ulpm\n");
3479                                 goto fail;
3480                         }
3481                 }
3482
3483                 if (dsi->info.panel_reset) {
3484                         /*
3485                          * Certain panels need dc frames be sent before
3486                          * waking panel.
3487                          */
3488                         if (dsi->info.panel_send_dc_frames)
3489                                 tegra_dsi_send_dc_frames(dc, dsi, 2);
3490
3491                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3492                                                         dsi->info.dsi_init_cmd,
3493                                                         dsi->info.n_init_cmd);
3494                         if (err < 0) {
3495                                 dev_err(&dc->ndev->dev,
3496                                 "dsi: error sending dsi init cmd\n");
3497                                 goto fail;
3498                         }
3499                 } else if (dsi->info.dsi_late_resume_cmd) {
3500                         err = tegra_dsi_send_panel_cmd(dc, dsi,
3501                                                 dsi->info.dsi_late_resume_cmd,
3502                                                 dsi->info.n_late_resume_cmd);
3503                         if (err < 0) {
3504                                 dev_err(&dc->ndev->dev,
3505                                 "dsi: error sending late resume cmd\n");
3506                                 goto fail;
3507                         }
3508                 }
3509         } else {
3510                 err = tegra_dsi_init_hw(dc, dsi);
3511                 if (err < 0) {
3512                         dev_err(&dc->ndev->dev,
3513                                 "dsi: not able to init dsi hardware\n");
3514                         goto fail;
3515                 }
3516
3517                 if (dsi->ulpm) {
3518                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
3519                                 dev_err(&dc->ndev->dev,
3520                                         "DSI failed to enter ulpm\n");
3521                                 goto fail;
3522                         }
3523
3524                         tegra_dsi_pad_enable(dsi);
3525
3526                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
3527                                 dev_err(&dc->ndev->dev,
3528                                         "DSI failed to exit ulpm\n");
3529                                 goto fail;
3530                         }
3531                 }
3532
3533                 /*
3534                  * Certain panels need dc frames be sent before
3535                  * waking panel.
3536                  */
3537                 if (dsi->info.panel_send_dc_frames)
3538                         tegra_dsi_send_dc_frames(dc, dsi, 2);
3539
3540                 err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
3541                 if (err < 0) {
3542                         dev_err(&dc->ndev->dev,
3543                                 "dsi: not able to set to lp mode\n");
3544                         goto fail;
3545                 }
3546
3547                 err = tegra_dsi_send_panel_cmd(dc, dsi, dsi->info.dsi_init_cmd,
3548                                                 dsi->info.n_init_cmd);
3549                 if (err < 0) {
3550                         dev_err(&dc->ndev->dev,
3551                                 "dsi: error while sending dsi init cmd\n");
3552                         goto fail;
3553                 }
3554
3555                 err = tegra_dsi_set_to_hs_mode(dc, dsi,
3556                                 TEGRA_DSI_DRIVEN_BY_DC);
3557                 if (err < 0) {
3558                         dev_err(&dc->ndev->dev,
3559                                 "dsi: not able to set to hs mode\n");
3560                         goto fail;
3561                 }
3562
3563                 dsi->enabled = true;
3564         }
3565
3566         if (dsi->out_ops && dsi->out_ops->enable)
3567                 dsi->out_ops->enable(dsi);
3568
3569         if (dsi->status.driven == DSI_DRIVEN_MODE_DC)
3570                 tegra_dsi_start_dc_stream(dc, dsi);
3571
3572         dsi->host_suspended = false;
3573 fail:
3574         tegra_dc_io_end(dc);
3575         mutex_unlock(&dsi->lock);
3576 }
3577
3578 static void __tegra_dc_dsi_init(struct tegra_dc *dc)
3579 {
3580         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
3581
3582         tegra_dc_dsi_debug_create(dsi);
3583
3584         if (dsi->info.dsi2lvds_bridge_enable)
3585                 dsi->out_ops = &tegra_dsi2lvds_ops;
3586         else if (dsi->info.dsi2edp_bridge_enable)
3587                 dsi->out_ops = &tegra_dsi2edp_ops;
3588         else
3589                 dsi->out_ops = NULL;
3590
3591         if (dsi->out_ops && dsi->out_ops->init)
3592                 dsi->out_ops->init(dsi);
3593
3594         tegra_dsi_init_sw(dc, dsi);
3595 }
3596
3597 struct tegra_dsi_cmd *tegra_dsi_parse_cmd_dt(struct tegra_dc_dsi_data *dsi,
3598                                                 const struct device_node *node,
3599                                                 struct property *prop,
3600                                                 u32 n_cmd)
3601 {
3602         struct tegra_dsi_cmd *dsi_cmd, *temp;
3603         u32 *prop_val_ptr;
3604         u32 cnt = 0, i = 0;
3605         u8 arg1, arg2;
3606
3607         if (!prop)
3608                 return NULL;
3609         prop_val_ptr = prop->value;
3610
3611         dsi_cmd = kzalloc(sizeof(*dsi_cmd) * n_cmd, GFP_KERNEL);
3612         if (!dsi_cmd) {
3613                 dev_err(&dsi->dc->ndev->dev,
3614                         "dsi: cmd memory allocation failed\n");
3615                 return ERR_PTR(-ENOMEM);
3616         }
3617         temp = dsi_cmd;
3618
3619         for (cnt  = 0; cnt < n_cmd; cnt++, temp++) {
3620                 temp->cmd_type = be32_to_cpu(*prop_val_ptr++);
3621                 if (temp->cmd_type == TEGRA_DSI_PACKET_CMD) {
3622                         temp->data_id = be32_to_cpu(*prop_val_ptr++);
3623                         arg1 = be32_to_cpu(*prop_val_ptr++);
3624                         arg2 = be32_to_cpu(*prop_val_ptr++);
3625                         prop_val_ptr++; /* skip ecc */
3626                         if (temp->data_id == DSI_GENERIC_LONG_WRITE ||
3627                                 temp->data_id == DSI_DCS_LONG_WRITE ||
3628                                 temp->data_id == DSI_NULL_PKT_NO_DATA ||
3629                                 temp->data_id == DSI_BLANKING_PKT_NO_DATA) {
3630                                 /* long pkt */
3631                                 temp->sp_len_dly.data_len =
3632                                         (arg2 << NUMOF_BIT_PER_BYTE) | arg1;
3633                                 temp->pdata = kzalloc(
3634                                         temp->sp_len_dly.data_len, GFP_KERNEL);
3635                                 for (i = 0; i < temp->sp_len_dly.data_len; i++)
3636                                         (temp->pdata)[i] =
3637                                         be32_to_cpu(*prop_val_ptr++);
3638                                 prop_val_ptr += 2; /* skip checksum */
3639                         } else {
3640                                 temp->sp_len_dly.sp.data0 = arg1;
3641                                 temp->sp_len_dly.sp.data1 = arg2;
3642                         }
3643                 } else if (temp->cmd_type == TEGRA_DSI_DELAY_MS) {
3644                         temp->sp_len_dly.delay_ms =
3645                                 be32_to_cpu(*prop_val_ptr++);
3646                 }
3647         }
3648
3649         return dsi_cmd;
3650 }
3651
3652 struct device_node *tegra_dsi_panel_detect(void)
3653 {
3654         /* TODO: currently only lg 720p panel has dt support */
3655         return of_find_compatible_node(NULL, NULL, "lg,720p-5");
3656 }
3657
3658 static int tegra_dc_dsi_cp_info_dt(struct tegra_dc_dsi_data *dsi)
3659 {
3660         struct device_node *panel_dt_node = tegra_dsi_panel_detect();
3661         struct device_node *dsi_dt_node =
3662                 of_find_compatible_node(NULL, NULL, "nvidia,tegra114-dsi");
3663         struct tegra_dsi_out *dsi_pdata = &dsi->info;
3664         int err = 0;
3665
3666         if (!panel_dt_node || !dsi_dt_node) {
3667                 dev_info(&dsi->dc->ndev->dev,
3668                         "dsi dt support not available\n");
3669                 err = -ENOENT;
3670                 goto fail;
3671         }
3672
3673         if (panel_dt_node && dsi_dt_node) {
3674                 const char *panel_dt_status;
3675                 const char *dsi_dt_status;
3676                 of_property_read_string(panel_dt_node,
3677                                 "status", &panel_dt_status);
3678                 of_property_read_string(dsi_dt_node,
3679                                 "status", &dsi_dt_status);
3680                 if (strcmp(panel_dt_status, "okay") ||
3681                                 strcmp(dsi_dt_status, "okay")) {
3682                         dev_info(&dsi->dc->ndev->dev,
3683                                 "dsi dt support disabled\n");
3684                         err = -ENOENT;
3685                         goto fail;
3686                 }
3687         }
3688
3689         of_property_read_u32(panel_dt_node, "nvidia,n-data-lanes",
3690                                         (u32 *)&dsi_pdata->n_data_lanes);
3691
3692         of_property_read_u32(panel_dt_node, "nvidia,pixel-format",
3693                                         (u32 *)&dsi_pdata->pixel_format);
3694
3695         of_property_read_u32(panel_dt_node, "nvidia,refresh-rate",
3696                                         (u32 *)&dsi_pdata->refresh_rate);
3697
3698         of_property_read_u32(panel_dt_node, "nvidia,video-data-type",
3699                                         (u32 *)&dsi_pdata->video_data_type);
3700
3701         of_property_read_u32(panel_dt_node, "nvidia,video-clock-mode",
3702                                         (u32 *)&dsi_pdata->video_clock_mode);
3703
3704         of_property_read_u32(panel_dt_node, "nvidia,video-burst-mode",
3705                                         (u32 *)&dsi_pdata->video_burst_mode);
3706
3707         of_property_read_u32(panel_dt_node, "nvidia,virtual-channel",
3708                                         (u32 *)&dsi_pdata->virtual_channel);
3709
3710         of_property_read_u32(panel_dt_node, "nvidia,panel-reset",
3711                                         (u32 *)&dsi_pdata->panel_reset);
3712
3713         dsi_pdata->power_saving_suspend = of_property_read_bool(panel_dt_node,
3714                                                 "nvidia,power-saving-suspend");
3715
3716         of_property_read_u32(dsi_dt_node, "nvidia,controller-vs",
3717                                         (u32 *)&dsi_pdata->controller_vs);
3718
3719         of_property_read_u32(panel_dt_node, "nvidia,n-init-cmd",
3720                                         (u32 *)&dsi_pdata->n_init_cmd);
3721
3722         dsi_pdata->dsi_init_cmd = tegra_dsi_parse_cmd_dt(dsi, panel_dt_node,
3723                                 of_find_property(
3724                                 panel_dt_node, "nvidia,dsi-init-cmd", NULL),
3725                                 dsi_pdata->n_init_cmd);
3726         if (IS_ERR_OR_NULL(dsi_pdata->dsi_init_cmd)) {
3727                 dev_err(&dsi->dc->ndev->dev,
3728                         "dsi: copy init cmd from dt failed\n");
3729                 err = PTR_ERR(dsi_pdata->dsi_init_cmd);
3730                 goto fail;
3731         }
3732
3733         dsi->dc->pdata->default_out->dsi = &dsi->info;
3734         dsi->dc->out->dsi = &dsi->info;
3735 fail:
3736         of_node_put(dsi_dt_node);
3737         of_node_put(panel_dt_node);
3738         return err;
3739 }
3740
3741 static int tegra_dc_dsi_cp_p_cmd(struct tegra_dsi_cmd *src,
3742                                         struct tegra_dsi_cmd *dst, u16 n_cmd)
3743 {
3744         u16 i;
3745         u16 len;
3746
3747         memcpy(dst, src, sizeof(*dst) * n_cmd);
3748
3749         for (i = 0; i < n_cmd; i++)
3750                 if (src[i].pdata) {
3751                         len = sizeof(*src[i].pdata) *
3752                                         src[i].sp_len_dly.data_len;
3753                         dst[i].pdata = kzalloc(len, GFP_KERNEL);
3754                         if (!dst[i].pdata)
3755                                 goto free_cmd_pdata;
3756                         memcpy(dst[i].pdata, src[i].pdata, len);
3757                 }
3758
3759         return 0;
3760
3761 free_cmd_pdata:
3762         while (i--)
3763                 if (dst[i].pdata)
3764                         kfree(dst[i].pdata);
3765         return -ENOMEM;
3766 }
3767
3768 static int tegra_dc_dsi_cp_info_board(struct tegra_dc_dsi_data *dsi,
3769                                                 struct tegra_dsi_out *p_dsi)
3770 {
3771         struct tegra_dsi_cmd *p_init_cmd;
3772         struct tegra_dsi_cmd *p_early_suspend_cmd = NULL;
3773         struct tegra_dsi_cmd *p_late_resume_cmd = NULL;
3774         struct tegra_dsi_cmd *p_suspend_cmd;
3775         int err = 0;
3776
3777         p_init_cmd = kzalloc(sizeof(*p_init_cmd) *
3778                                 p_dsi->n_init_cmd, GFP_KERNEL);
3779         if (!p_init_cmd)
3780                 return -ENOMEM;
3781
3782         if (p_dsi->dsi_early_suspend_cmd) {
3783                 p_early_suspend_cmd = kzalloc(sizeof(*p_early_suspend_cmd) *
3784                                         p_dsi->n_early_suspend_cmd,
3785                                         GFP_KERNEL);
3786                 if (!p_early_suspend_cmd) {
3787                         err = -ENOMEM;
3788                         goto err_free_init_cmd;
3789                 }
3790         }
3791
3792         if (p_dsi->dsi_late_resume_cmd) {
3793                 p_late_resume_cmd = kzalloc(sizeof(*p_late_resume_cmd) *
3794                                         p_dsi->n_late_resume_cmd,
3795                                         GFP_KERNEL);
3796                 if (!p_late_resume_cmd) {
3797                         err = -ENOMEM;
3798                         goto err_free_p_early_suspend_cmd;
3799                 }
3800         }
3801
3802         p_suspend_cmd = kzalloc(sizeof(*p_suspend_cmd) * p_dsi->n_suspend_cmd,
3803                                 GFP_KERNEL);
3804         if (!p_suspend_cmd) {
3805                 err = -ENOMEM;
3806                 goto err_free_p_late_resume_cmd;
3807         }
3808
3809         memcpy(&dsi->info, p_dsi, sizeof(dsi->info));
3810
3811         /* Copy panel init cmd */
3812         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_init_cmd,
3813                                                 p_init_cmd, p_dsi->n_init_cmd);
3814         if (err < 0)
3815                 goto err_free;
3816         dsi->info.dsi_init_cmd = p_init_cmd;
3817
3818         /* Copy panel early suspend cmd */
3819         if (p_dsi->dsi_early_suspend_cmd) {
3820                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_early_suspend_cmd,
3821                                         p_early_suspend_cmd,
3822                                         p_dsi->n_early_suspend_cmd);
3823                 if (err < 0)
3824                         goto err_free;
3825                 dsi->info.dsi_early_suspend_cmd = p_early_suspend_cmd;
3826         }
3827
3828         /* Copy panel late resume cmd */
3829         if (p_dsi->dsi_late_resume_cmd) {
3830                 err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_late_resume_cmd,
3831                                                 p_late_resume_cmd,
3832                                                 p_dsi->n_late_resume_cmd);
3833                 if (err < 0)
3834                         goto err_free;
3835                 dsi->info.dsi_late_resume_cmd = p_late_resume_cmd;
3836         }
3837
3838         /* Copy panel suspend cmd */
3839         err = tegra_dc_dsi_cp_p_cmd(p_dsi->dsi_suspend_cmd, p_suspend_cmd,
3840                                         p_dsi->n_suspend_cmd);
3841         if (err < 0)
3842                 goto err_free;
3843         dsi->info.dsi_suspend_cmd = p_suspend_cmd;
3844
3845         return 0;
3846 err_free:
3847         kfree(p_suspend_cmd);
3848 err_free_p_late_resume_cmd:
3849         kfree(p_late_resume_cmd);
3850 err_free_p_early_suspend_cmd:
3851         kfree(p_early_suspend_cmd);
3852 err_free_init_cmd:
3853         kfree(p_init_cmd);
3854         return err;
3855 }
3856
3857 static int tegra_dc_dsi_cp_info(struct tegra_dc_dsi_data *dsi)
3858 {
3859         int err;
3860
3861         err = tegra_dc_dsi_cp_info_dt(dsi);
3862         if (err < 0) {
3863                 /* resort to platform files */
3864                 struct tegra_dsi_out *p_dsi;
3865                 dev_warn(&dsi->dc->ndev->dev,
3866                         "dsi: copy from dt failed, trying platform file\n");
3867                 p_dsi = dsi->dc->pdata->default_out->dsi;
3868                 if (!p_dsi) {
3869                         dev_err(&dsi->dc->ndev->dev,
3870                                 "dsi: platform dsi data not available\n");
3871                         return -EINVAL;
3872                 }
3873                 err = tegra_dc_dsi_cp_info_board(dsi, p_dsi);
3874                 if (err < 0) {
3875                         dev_err(&dsi->dc->ndev->dev,
3876                                 "dsi: copy from platform files failed\n");
3877                         return err;
3878                 }
3879         }
3880
3881         if (dsi->info.n_data_lanes > MAX_DSI_DATA_LANES)
3882                 return -EINVAL;
3883
3884         if (!dsi->info.panel_reset_timeout_msec)
3885                 dsi->info.panel_reset_timeout_msec =
3886                                                 DEFAULT_PANEL_RESET_TIMEOUT;
3887         if (!dsi->info.panel_buffer_size_byte)
3888                 dsi->info.panel_buffer_size_byte = DEFAULT_PANEL_BUFFER_BYTE;
3889
3890         if (!dsi->info.max_panel_freq_khz) {
3891                 dsi->info.max_panel_freq_khz = DEFAULT_MAX_DSI_PHY_CLK_KHZ;
3892
3893                 if (dsi->info.video_burst_mode >
3894                                 TEGRA_DSI_VIDEO_NONE_BURST_MODE_WITH_SYNC_END){
3895                         dev_err(&dsi->dc->ndev->dev, "DSI: max_panel_freq_khz"
3896                                         "is not set for DSI burst mode.\n");
3897                         dsi->info.video_burst_mode =
3898                                 TEGRA_DSI_VIDEO_BURST_MODE_LOWEST_SPEED;
3899                 }
3900         }
3901
3902         if (!dsi->info.lp_cmd_mode_freq_khz)
3903                 dsi->info.lp_cmd_mode_freq_khz = DEFAULT_LP_CMD_MODE_CLK_KHZ;
3904
3905         if (!dsi->info.chip_id || !dsi->info.chip_rev)
3906                 dev_warn(&dsi->dc->ndev->dev,
3907                         "DSI: Failed to get chip info\n");
3908
3909         if (!dsi->info.lp_read_cmd_mode_freq_khz)
3910                 dsi->info.lp_read_cmd_mode_freq_khz =
3911                         dsi->info.lp_cmd_mode_freq_khz;
3912
3913         /* host mode is for testing only */
3914         dsi->driven_mode = TEGRA_DSI_DRIVEN_BY_DC;
3915         return 0;
3916 }
3917
3918 /* returns next null enumeration from  tegra_dsi_instance */
3919 static inline int tegra_dsi_get_enumeration(void)
3920 {
3921         int i = 0;
3922         for (; i < MAX_DSI_INSTANCE; i++) {
3923                 if (!tegra_dsi_instance[i])
3924                         return i;
3925         }
3926         return -EINVAL;
3927 }
3928
3929 static int _tegra_dc_dsi_init(struct tegra_dc *dc)
3930 {
3931         struct tegra_dc_dsi_data *dsi;
3932         struct resource *res;
3933         struct resource *base_res;
3934         void __iomem *base;
3935         struct clk *dc_clk = NULL;
3936         struct clk *dsi_clk = NULL;
3937         struct clk *dsi_fixed_clk = NULL;
3938         struct clk *dsi_lp_clk = NULL;
3939         int err = 0;
3940         int dsi_enum = -1;
3941
3942         dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
3943         if (!dsi) {
3944                 dev_err(&dc->ndev->dev, "dsi: memory allocation failed\n");
3945                 return -ENOMEM;
3946         }
3947
3948         dsi->dc = dc;
3949         err = tegra_dc_dsi_cp_info(dsi);
3950         if (err < 0)
3951                 goto err_free_dsi;
3952
3953         dsi_enum = dsi->info.dsi_instance ? : tegra_dsi_get_enumeration();
3954         if (dsi_enum < 0) {
3955                 dev_err(&dc->ndev->dev, "dsi: invalid enumeration\n");
3956                 err = -EINVAL;
3957                 goto err_free_dsi;
3958         }
3959         tegra_dsi_instance[dsi_enum] = dsi;
3960
3961         if (dc->out->dsi->ganged_type) {
3962                 if (dsi_enum)
3963                         res = platform_get_resource_byname(dc->ndev,
3964                                                 IORESOURCE_MEM,
3965                                                 "ganged_dsib_regs");
3966                 else
3967                         res = platform_get_resource_byname(dc->ndev,
3968                                                 IORESOURCE_MEM,
3969                                                 "ganged_dsia_regs");
3970         } else {
3971                 res = platform_get_resource_byname(dc->ndev,
3972                                         IORESOURCE_MEM,
3973                                         "dsi_regs");
3974         }
3975
3976         if (!res) {
3977                 dev_err(&dc->ndev->dev, "dsi: no mem resource\n");
3978                 err = -ENOENT;
3979                 goto err_free_dsi;
3980         }
3981
3982         base_res = request_mem_region(res->start, resource_size(res),
3983                                 dc->ndev->name);
3984         if (!base_res) {
3985                 dev_err(&dc->ndev->dev, "dsi: request_mem_region failed\n");
3986                 err = -EBUSY;
3987                 goto err_free_dsi;
3988         }
3989
3990         base = ioremap(res->start, resource_size(res));
3991         if (!base) {
3992                 dev_err(&dc->ndev->dev, "dsi: registers can't be mapped\n");
3993                 err = -EBUSY;
3994                 goto err_release_regs;
3995         }
3996
3997         if (dsi_enum) {
3998                 dsi_clk = clk_get(&dc->ndev->dev, "dsib");
3999                 dsi_lp_clk = clk_get(&dc->ndev->dev, "dsiblp");
4000         } else {
4001                 dsi_clk = clk_get(&dc->ndev->dev, "dsia");
4002                 dsi_lp_clk = clk_get(&dc->ndev->dev, "dsialp");
4003         }
4004
4005         dsi_fixed_clk = clk_get(&dc->ndev->dev, "dsi-fixed");
4006
4007         if (IS_ERR_OR_NULL(dsi_clk) || IS_ERR_OR_NULL(dsi_fixed_clk)) {
4008                 dev_err(&dc->ndev->dev, "dsi: can't get clock\n");
4009                 err = -EBUSY;
4010                 goto err_release_regs;
4011         }
4012
4013         dc_clk = clk_get_sys(dev_name(&dc->ndev->dev), NULL);
4014         if (IS_ERR_OR_NULL(dc_clk)) {
4015                 dev_err(&dc->ndev->dev, "dsi: dc clock %s unavailable\n",
4016                         dev_name(&dc->ndev->dev));
4017                 err = -EBUSY;
4018                 goto err_dsi_clk_put;
4019         }
4020
4021         mutex_init(&dsi->lock);
4022         dsi->controller_index = dsi_enum;
4023         dsi->base = base;
4024         dsi->base_res = base_res;
4025         dsi->dc_clk = dc_clk;
4026         dsi->dsi_clk = dsi_clk;
4027         dsi->dsi_fixed_clk = dsi_fixed_clk;
4028         dsi->dsi_lp_clk = dsi_lp_clk;
4029
4030         tegra_dc_set_outdata(dc, dsi);
4031         __tegra_dc_dsi_init(dc);
4032
4033         return 0;
4034
4035 err_dsi_clk_put:
4036         clk_put(dsi_clk);
4037         clk_put(dsi_fixed_clk);
4038 err_release_regs:
4039         release_resource(base_res);
4040 err_free_dsi:
4041         kfree(dsi);
4042
4043         return err;
4044 }
4045
4046 static void _tegra_dc_dsi_destroy(struct tegra_dc *dc)
4047 {
4048         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4049         u16 i;
4050         u32 val;
4051
4052         mutex_lock(&dsi->lock);
4053
4054         if (dsi->out_ops && dsi->out_ops->destroy)
4055                 dsi->out_ops->destroy(dsi);
4056
4057         /* free up the pdata */
4058         for (i = 0; i < dsi->info.n_init_cmd; i++) {
4059                 if (dsi->info.dsi_init_cmd[i].pdata)
4060                         kfree(dsi->info.dsi_init_cmd[i].pdata);
4061         }
4062         kfree(dsi->info.dsi_init_cmd);
4063
4064         /* Disable dc stream */
4065         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4066                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4067
4068         /* Disable dsi phy clock */
4069         if (dsi->status.clk_out == DSI_PHYCLK_OUT_EN)
4070                 tegra_dsi_hs_clk_out_disable(dc, dsi);
4071
4072         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4073         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4074
4075         iounmap(dsi->base);
4076         release_resource(dsi->base_res);
4077
4078         clk_put(dsi->dc_clk);
4079         clk_put(dsi->dsi_clk);
4080
4081         mutex_unlock(&dsi->lock);
4082
4083         mutex_destroy(&dsi->lock);
4084         kfree(dsi);
4085 }
4086
4087 static void tegra_dsi_config_phy_clk(struct tegra_dc_dsi_data *dsi,
4088                                                         u32 settings)
4089 {
4090         struct clk *parent_clk = NULL;
4091         struct clk *base_clk = NULL;
4092
4093         parent_clk = clk_get_parent(dsi->dsi_clk);
4094         base_clk = clk_get_parent(parent_clk);
4095 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
4096         if (dsi->info.dsi_instance)
4097                 tegra_clk_cfg_ex(base_clk,
4098                                 TEGRA_CLK_PLLD_CSI_OUT_ENB,
4099                                 settings);
4100         else
4101                 tegra_clk_cfg_ex(base_clk,
4102                                 TEGRA_CLK_PLLD_DSI_OUT_ENB,
4103                                 settings);
4104 #else
4105         tegra_clk_cfg_ex(base_clk,
4106                         TEGRA_CLK_PLLD_DSI_OUT_ENB,
4107                         settings);
4108 #endif
4109 }
4110
4111 static int _tegra_dsi_host_suspend(struct tegra_dc *dc,
4112                                         struct tegra_dc_dsi_data *dsi,
4113                                         u32 suspend_aggr)
4114 {
4115         u32 val = 0;
4116         int err = 0;
4117
4118         switch (suspend_aggr) {
4119         case DSI_HOST_SUSPEND_LV2:
4120                 if (!dsi->ulpm) {
4121                         err = tegra_dsi_enter_ulpm(dsi);
4122                         if (err < 0) {
4123                                 dev_err(&dc->ndev->dev,
4124                                         "DSI failed to enter ulpm\n");
4125                                 goto fail;
4126                         }
4127                 }
4128
4129                 val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
4130                 val |= DSI_PAD_CONTROL_PAD_PDIO(0x3) |
4131                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
4132                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1);
4133                 tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
4134
4135                 /* Suspend core-logic */
4136                 val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4137                 tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4138                 /* fall through */
4139         case DSI_HOST_SUSPEND_LV1:
4140                 /* Disable dsi fast and slow clock */
4141                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4142                 /* fall through */
4143         case DSI_HOST_SUSPEND_LV0:
4144                 /* Disable dsi source clock */
4145                 tegra_dsi_clk_disable(dsi);
4146                 break;
4147         case DSI_NO_SUSPEND:
4148                 break;
4149         default:
4150                 dev_err(&dc->ndev->dev, "DSI suspend aggressiveness"
4151                                                 "is not supported.\n");
4152         }
4153
4154         return 0;
4155 fail:
4156         return err;
4157 }
4158
4159 static int _tegra_dsi_host_resume(struct tegra_dc *dc,
4160                                         struct tegra_dc_dsi_data *dsi,
4161                                         u32 suspend_aggr)
4162 {
4163         u32 val;
4164         int err;
4165
4166         switch (dsi->info.suspend_aggr) {
4167         case DSI_HOST_SUSPEND_LV0:
4168                 tegra_dsi_clk_enable(dsi);
4169                 break;
4170         case DSI_HOST_SUSPEND_LV1:
4171                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4172                 tegra_dsi_clk_enable(dsi);
4173                 break;
4174         case DSI_HOST_SUSPEND_LV2:
4175                 tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4176                 tegra_dsi_clk_enable(dsi);
4177
4178                 tegra_dsi_writel(dsi,
4179                         DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_ENABLE),
4180                         DSI_POWER_CONTROL);
4181
4182                 if (dsi->ulpm) {
4183                         err = tegra_dsi_enter_ulpm(dsi);
4184                         if (err < 0) {
4185                                 dev_err(&dc->ndev->dev,
4186                                         "DSI failed to enter ulpm\n");
4187                                 goto fail;
4188                         }
4189
4190                         val = tegra_dsi_readl(dsi, DSI_PAD_CONTROL);
4191                         val &= ~(DSI_PAD_CONTROL_PAD_PDIO(0x3) |
4192                                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
4193                                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(0x1));
4194                         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
4195
4196                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4197                                 dev_err(&dc->ndev->dev,
4198                                         "DSI failed to exit ulpm\n");
4199                                 goto fail;
4200                         }
4201                 }
4202                 break;
4203         case DSI_NO_SUSPEND:
4204                 break;
4205         default:
4206                 dev_err(&dc->ndev->dev, "DSI suspend aggressivenes"
4207                                                 "is not supported.\n");
4208         }
4209
4210         return 0;
4211 fail:
4212         return err;
4213 }
4214
4215 static int tegra_dsi_host_suspend(struct tegra_dc *dc)
4216 {
4217         int err = 0;
4218         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4219
4220         if (!dsi->enabled)
4221                 return -EINVAL;
4222
4223         if (dsi->host_suspended)
4224                 return 0;
4225
4226         mutex_lock(&dsi->host_lock);
4227         mutex_lock(&dc->one_shot_lock);
4228         mutex_lock(&dc->lock);
4229         mutex_lock(&dc->one_shot_lp_lock);
4230         tegra_dc_io_start(dc);
4231         dsi->host_suspended = true;
4232
4233         tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4234
4235         err = _tegra_dsi_host_suspend(dc, dsi, dsi->info.suspend_aggr);
4236         if (err < 0)
4237                 dev_err(&dc->ndev->dev,
4238                         "DSI host suspend failed\n");
4239
4240         /* Shutting down. Drop any reference to dc clk */
4241         while (tegra_is_clk_enabled(dc->clk))
4242                 clk_disable_unprepare(dc->clk);
4243
4244         pm_runtime_put_sync(&dc->ndev->dev);
4245
4246         tegra_dc_io_end(dc);
4247         mutex_unlock(&dc->one_shot_lp_lock);
4248         mutex_unlock(&dc->lock);
4249         mutex_unlock(&dc->one_shot_lock);
4250         mutex_unlock(&dsi->host_lock);
4251         return err;
4252 }
4253
4254 static int tegra_dsi_deep_sleep(struct tegra_dc *dc,
4255                                 struct tegra_dc_dsi_data *dsi)
4256 {
4257         int val = 0;
4258         int err = 0;
4259
4260         if (!dsi->enabled)
4261                 return 0;
4262
4263         err = tegra_dsi_set_to_lp_mode(dc, dsi, DSI_LP_OP_WRITE);
4264         if (err < 0) {
4265                 dev_err(&dc->ndev->dev,
4266                 "DSI failed to go to LP mode\n");
4267                 goto fail;
4268         }
4269
4270         /* Suspend DSI panel */
4271         err = tegra_dsi_send_panel_cmd(dc, dsi,
4272                         dsi->info.dsi_suspend_cmd,
4273                         dsi->info.n_suspend_cmd);
4274
4275         /*
4276          * Certain panels need dc frames be sent after
4277          * putting panel to sleep.
4278          */
4279         if (dsi->info.panel_send_dc_frames)
4280                 tegra_dsi_send_dc_frames(dc, dsi, 2);
4281
4282         if (err < 0) {
4283                 dev_err(&dc->ndev->dev,
4284                         "dsi: Error sending suspend cmd\n");
4285                 goto fail;
4286         }
4287
4288         if (!dsi->ulpm) {
4289                 err = tegra_dsi_enter_ulpm(dsi);
4290                 if (err < 0) {
4291                         dev_err(&dc->ndev->dev,
4292                                 "DSI failed to enter ulpm\n");
4293                         goto fail;
4294                 }
4295         }
4296
4297         val = DSI_PAD_CONTROL_PAD_PDIO(0x3) |
4298                 DSI_PAD_CONTROL_PAD_PDIO_CLK(0x1) |
4299                 DSI_PAD_CONTROL_PAD_PULLDN_ENAB(TEGRA_DSI_ENABLE);
4300         tegra_dsi_writel(dsi, val, DSI_PAD_CONTROL);
4301
4302         /* Suspend core-logic */
4303         val = DSI_POWER_CONTROL_LEG_DSI_ENABLE(TEGRA_DSI_DISABLE);
4304         tegra_dsi_writel(dsi, val, DSI_POWER_CONTROL);
4305
4306         /* Disable dsi fast and slow clock */
4307         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_DISABLE);
4308
4309         /* Disable dsi source clock */
4310         tegra_dsi_clk_disable(dsi);
4311
4312         regulator_disable(dsi->avdd_dsi_csi);
4313
4314         dsi->enabled = false;
4315         dsi->host_suspended = true;
4316
4317         return 0;
4318 fail:
4319         return err;
4320 }
4321
4322 static int tegra_dsi_host_resume(struct tegra_dc *dc)
4323 {
4324         int err = 0;
4325         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4326
4327         if (!dsi->enabled)
4328                 return -EINVAL;
4329
4330         mutex_lock(&dsi->host_lock);
4331         cancel_delayed_work_sync(&dsi->idle_work);
4332         if (!dsi->host_suspended) {
4333                 mutex_unlock(&dsi->host_lock);
4334                 return 0;
4335         }
4336
4337         tegra_dc_io_start(dc);
4338         clk_prepare_enable(dc->clk);
4339
4340         pm_runtime_get_sync(&dc->ndev->dev);
4341
4342         err = _tegra_dsi_host_resume(dc, dsi, dsi->info.suspend_aggr);
4343         if (err < 0) {
4344                 dev_err(&dc->ndev->dev,
4345                         "DSI host resume failed\n");
4346                 goto fail;
4347         }
4348
4349         tegra_dsi_start_dc_stream(dc, dsi);
4350         dsi->host_suspended = false;
4351 fail:
4352         tegra_dc_io_end(dc);
4353         mutex_unlock(&dsi->host_lock);
4354         return err;
4355 }
4356
4357 static void _tegra_dc_dsi_disable(struct tegra_dc *dc)
4358 {
4359         int err;
4360         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4361
4362         if (dsi->host_suspended)
4363                 tegra_dsi_host_resume(dc);
4364
4365         mutex_lock(&dsi->lock);
4366         tegra_dc_io_start(dc);
4367
4368         if (dsi->status.dc_stream == DSI_DC_STREAM_ENABLE)
4369                 tegra_dsi_stop_dc_stream_at_frame_end(dc, dsi, 2);
4370
4371         if (dsi->out_ops && dsi->out_ops->disable)
4372                 dsi->out_ops->disable(dsi);
4373
4374         if (dsi->info.power_saving_suspend) {
4375                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4376                         dev_err(&dc->ndev->dev,
4377                                 "DSI failed to enter deep sleep\n");
4378                         goto fail;
4379                 }
4380         } else {
4381                 if (dsi->info.dsi_early_suspend_cmd) {
4382                         err = tegra_dsi_send_panel_cmd(dc, dsi,
4383                                 dsi->info.dsi_early_suspend_cmd,
4384                                 dsi->info.n_early_suspend_cmd);
4385                         if (err < 0) {
4386                                 dev_err(&dc->ndev->dev,
4387                                 "dsi: Error sending early suspend cmd\n");
4388                                 goto fail;
4389                         }
4390                 }
4391
4392                 if (!dsi->ulpm) {
4393                         if (tegra_dsi_enter_ulpm(dsi) < 0) {
4394                                 dev_err(&dc->ndev->dev,
4395                                         "DSI failed to enter ulpm\n");
4396                                 goto fail;
4397                         }
4398                 }
4399         }
4400 fail:
4401         mutex_unlock(&dsi->lock);
4402         tegra_dc_io_end(dc);
4403 }
4404
4405 static void tegra_dc_dsi_disable(struct tegra_dc *dc)
4406 {
4407         _tegra_dc_dsi_disable(dc);
4408
4409         if (dc->out->dsi->ganged_type) {
4410                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4411                 _tegra_dc_dsi_disable(dc);
4412                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4413         }
4414 }
4415
4416
4417 #ifdef CONFIG_PM
4418 static void _tegra_dc_dsi_suspend(struct tegra_dc *dc)
4419 {
4420         struct tegra_dc_dsi_data *dsi;
4421
4422         dsi = tegra_dc_get_outdata(dc);
4423
4424         if (!dsi->enabled)
4425                 return;
4426
4427         if (dsi->host_suspended)
4428                 tegra_dsi_host_resume(dc);
4429
4430         tegra_dc_io_start(dc);
4431         mutex_lock(&dsi->lock);
4432
4433         if (dsi->out_ops && dsi->out_ops->suspend)
4434                 dsi->out_ops->suspend(dsi);
4435
4436         if (!dsi->info.power_saving_suspend) {
4437                 if (dsi->ulpm) {
4438                         if (tegra_dsi_exit_ulpm(dsi) < 0) {
4439                                 dev_err(&dc->ndev->dev,
4440                                         "DSI failed to exit ulpm");
4441                                 goto fail;
4442                         }
4443                 }
4444
4445                 if (tegra_dsi_deep_sleep(dc, dsi) < 0) {
4446                         dev_err(&dc->ndev->dev,
4447                                 "DSI failed to enter deep sleep\n");
4448                         goto fail;
4449                 }
4450         }
4451 fail:
4452         mutex_unlock(&dsi->lock);
4453         tegra_dc_io_end(dc);
4454 }
4455
4456 static void _tegra_dc_dsi_resume(struct tegra_dc *dc)
4457 {
4458         struct tegra_dc_dsi_data *dsi;
4459
4460         dsi = tegra_dc_get_outdata(dc);
4461
4462         /* No dsi config required since tegra_dc_dsi_enable
4463          * will reconfigure the controller from scratch
4464          */
4465
4466          if (dsi->out_ops && dsi->out_ops->resume)
4467                 dsi->out_ops->resume(dsi);
4468 }
4469
4470 static void tegra_dc_dsi_suspend(struct tegra_dc *dc)
4471 {
4472         _tegra_dc_dsi_suspend(dc);
4473
4474         if (dc->out->dsi->ganged_type) {
4475                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4476                 _tegra_dc_dsi_suspend(dc);
4477                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4478         }
4479 }
4480
4481 static void tegra_dc_dsi_resume(struct tegra_dc *dc)
4482 {
4483         _tegra_dc_dsi_resume(dc);
4484
4485         if (dc->out->dsi->ganged_type) {
4486                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4487                 _tegra_dc_dsi_resume(dc);
4488                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4489         }
4490 }
4491 #endif
4492
4493 static int tegra_dc_dsi_init(struct tegra_dc *dc)
4494 {
4495         struct tegra_dc_dsi_data *dsi;
4496         int err = 0;
4497
4498         err = _tegra_dc_dsi_init(dc);
4499         if (err < 0) {
4500                 dev_err(&dc->ndev->dev,
4501                         "dsi: Instance A init failed\n");
4502                 goto err;
4503         }
4504
4505         dsi = tegra_dc_get_outdata(dc);
4506
4507         dsi->avdd_dsi_csi =  regulator_get(&dc->ndev->dev, "avdd_dsi_csi");
4508         if (IS_ERR_OR_NULL(dsi->avdd_dsi_csi)) {
4509                 dev_err(&dc->ndev->dev, "dsi: avdd_dsi_csi reg get failed\n");
4510                 err = PTR_ERR(dsi->avdd_dsi_csi);
4511                 goto err_reg;
4512         }
4513
4514         dsi->mipi_cal = tegra_mipi_cal_init_sw(dc);
4515         if (IS_ERR(dsi->mipi_cal)) {
4516                 dev_err(&dc->ndev->dev, "dsi: mipi_cal sw init failed\n");
4517                 err = PTR_ERR(dsi->mipi_cal);
4518                 goto err_mipi;
4519         }
4520
4521         if (dc->out->dsi->ganged_type) {
4522                 err = _tegra_dc_dsi_init(dc);
4523                 if (err < 0) {
4524                         dev_err(&dc->ndev->dev,
4525                                 "dsi: Instance B init failed\n");
4526                         goto err_ganged;
4527                 }
4528                 tegra_dsi_instance[DSI_INSTANCE_1]->avdd_dsi_csi =
4529                                                         dsi->avdd_dsi_csi;
4530                 tegra_dsi_instance[DSI_INSTANCE_1]->mipi_cal =
4531                                                         dsi->mipi_cal;
4532                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4533         }
4534         return 0;
4535 err_ganged:
4536         tegra_mipi_cal_destroy(dc);
4537 err_mipi:
4538         regulator_put(dsi->avdd_dsi_csi);
4539 err_reg:
4540         _tegra_dc_dsi_destroy(dc);
4541 err:
4542         return err;
4543 }
4544
4545 static void tegra_dc_dsi_destroy(struct tegra_dc *dc)
4546 {
4547         struct regulator *avdd_dsi_csi;
4548         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4549
4550         avdd_dsi_csi = dsi->avdd_dsi_csi;
4551
4552         _tegra_dc_dsi_destroy(dc);
4553
4554         if (dc->out->dsi->ganged_type) {
4555                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4556                 _tegra_dc_dsi_destroy(dc);
4557                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4558         }
4559
4560         regulator_put(avdd_dsi_csi);
4561         tegra_mipi_cal_destroy(dc);
4562 }
4563
4564 static void tegra_dc_dsi_enable(struct tegra_dc *dc)
4565 {
4566         _tegra_dc_dsi_enable(dc);
4567
4568         if (dc->out->dsi->ganged_type) {
4569                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_1]);
4570                 _tegra_dc_dsi_enable(dc);
4571                 tegra_dc_set_outdata(dc, tegra_dsi_instance[DSI_INSTANCE_0]);
4572         }
4573 }
4574
4575 static long tegra_dc_dsi_setup_clk(struct tegra_dc *dc, struct clk *clk)
4576 {
4577         unsigned long rate;
4578         struct clk *parent_clk;
4579         struct clk *base_clk;
4580         struct tegra_dc_dsi_data *dsi = tegra_dc_get_outdata(dc);
4581
4582         /* divide by 1000 to avoid overflow */
4583         dc->mode.pclk /= 1000;
4584         rate = (dc->mode.pclk * dc->shift_clk_div.mul * 2)
4585                                 / dc->shift_clk_div.div;
4586         rate *= 1000;
4587         dc->mode.pclk *= 1000;
4588
4589         if (dc->out->flags & TEGRA_DC_OUT_INITIALIZED_MODE)
4590                 goto skip_setup;
4591
4592         if (clk == dc->clk) {
4593                 parent_clk = clk_get_sys(NULL,
4594                                 dc->out->parent_clk ? : "pll_d_out0");
4595                 base_clk = clk_get_parent(parent_clk);
4596         } else {
4597                 if (dc->pdata->default_out->dsi->dsi_instance) {
4598                         parent_clk = clk_get_sys(NULL,
4599                                 dc->out->parent_clk ? : "pll_d2_out0");
4600                         base_clk = clk_get_parent(parent_clk);
4601                 } else {
4602                         parent_clk = clk_get_sys(NULL,
4603                                 dc->out->parent_clk ? : "pll_d_out0");
4604                         base_clk = clk_get_parent(parent_clk);
4605                 }
4606         }
4607         tegra_dsi_config_phy_clk(dsi, TEGRA_DSI_ENABLE);
4608
4609         if (rate != clk_get_rate(base_clk))
4610                 clk_set_rate(base_clk, rate);
4611
4612         if (clk_get_parent(clk) != parent_clk)
4613                 clk_set_parent(clk, parent_clk);
4614
4615 skip_setup:
4616         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4617
4618         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
4619 }
4620
4621 struct tegra_dc_out_ops tegra_dc_dsi_ops = {
4622         .init = tegra_dc_dsi_init,
4623         .destroy = tegra_dc_dsi_destroy,
4624         .enable = tegra_dc_dsi_enable,
4625         .disable = tegra_dc_dsi_disable,
4626         .hold = tegra_dc_dsi_hold_host,
4627         .release = tegra_dc_dsi_release_host,
4628 #ifdef CONFIG_PM
4629         .suspend = tegra_dc_dsi_suspend,
4630         .resume = tegra_dc_dsi_resume,
4631 #endif
4632         .setup_clk = tegra_dc_dsi_setup_clk,
4633 };