video: tegra: dc: Update t12x pll selection
[linux-3.10.git] / drivers / video / tegra / dc / dp.c
1 /*
2  * drivers/video/tegra/dc/dp.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/kernel.h>
23 #include <linux/nvhost.h>
24 #include <linux/wait.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31
32 #include "dp.h"
33 #include "sor.h"
34 #include "sor_regs.h"
35 #include "dpaux_regs.h"
36 #include "dc_priv.h"
37
38
39
40 static inline unsigned long tegra_dpaux_readl(struct tegra_dc_dp_data *dp,
41         unsigned long reg)
42 {
43         return readl(dp->aux_base + reg * 4);
44 }
45
46 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
47         unsigned long reg, unsigned long val)
48 {
49         writel(val, dp->aux_base + reg * 4);
50 }
51
52
53 static unsigned long tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
54         u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
55 {
56         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
57         u32 reg_val = 0;
58
59         do {
60                 usleep_range(poll_interval_us, poll_interval_us << 1);
61                 reg_val = tegra_dpaux_readl(dp, reg);
62         } while (((reg_val & mask) != exp_val) &&
63                 time_after(timeout_jf, jiffies));
64
65         if ((reg_val & mask) == exp_val)
66                 return 0;       /* success */
67         dev_dbg(&dp->dc->ndev->dev,
68                 "sor_poll_register 0x%x: timeout\n", reg);
69         return jiffies - timeout_jf + 1;
70 }
71
72
73 static int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
74 {
75         /* According to DP spec, each aux transaction needs to finish
76            within 40ms. */
77         if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
78                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
79                         DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
80                         100, DP_AUX_TIMEOUT_MS) != 0) {
81                 dev_err(&dp->dc->ndev->dev,
82                         "dp: DPAUX transaction timeout\n");
83                 return -EFAULT;
84         }
85         return 0;
86 }
87
88
89 static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
90 {
91         unsigned long reg_val;
92
93         /* clear interrupt */
94         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
95         /* do not enable interrupt for now. Enable them when Isr in place */
96         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
97
98         /* Power up aux/hybrid pads */
99         /* TODO: this may not needed for t124 */
100         reg_val = DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP;
101         tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, reg_val);
102
103         /* Put HYBRID PAD in AUX mode */
104         reg_val = tegra_dpaux_readl(dp, DPAUX_HYBRID_PADCTL);
105         reg_val &= ~DPAUX_HYBRID_PADCTL_MODE_I2C;
106         reg_val |= DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE;
107         reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE;
108         reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE;
109         tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, reg_val);
110
111 }
112
113 static void tegra_dc_dpaux_disable(struct tegra_dc_dp_data *dp)
114 {
115         tegra_dpaux_writel(dp, NV_DPCD_SET_POWER,
116                 NV_DPCD_SET_POWER_VAL_D3_PWRDWN);
117
118         /* TODO: power down DPAUX_HYBRID_SPARE too? */
119 }
120
121
122 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
123         u32 addr, u8 *data, u32 *size, u32 *aux_stat)
124 {
125         int             i;
126         unsigned long   reg_val;
127         u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
128         u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
129
130         if (*size >= DP_AUX_MAX_BYTES)
131                 return -EINVAL; /* only write one chunk of data */
132
133         /* Make sure the command is write command */
134         switch (cmd) {
135         case DPAUX_DP_AUXCTL_CMD_I2CWR:
136         case DPAUX_DP_AUXCTL_CMD_MOTWR:
137         case DPAUX_DP_AUXCTL_CMD_AUXWR:
138                 break;
139         default:
140                 dev_err(&dp->dc->ndev->dev, "dp: aux write cmd 0x%x is invalid\n",
141                         cmd);
142                 return -EINVAL;
143         }
144
145 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
146         *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
147         if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
148                 dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
149                 return -EFAULT;
150         }
151 #endif
152
153         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
154         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
155                 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
156                         (unsigned long)*data);
157                 data += 4;
158         }
159
160         reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
161         reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
162         reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
163         reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
164         reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
165
166         while ((timeout_retries > 0) && (defer_retries > 0)) {
167                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
168                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
169                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
170                                 DP_DPCP_RETRY_SLEEP_NS << 1);
171
172                 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
173                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
174
175                 if (tegra_dpaux_wait_transaction(dp))
176                         dev_err(&dp->dc->ndev->dev,
177                                 "dp: aux write transaction timeout\n");
178
179                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
180
181                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
182                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
183                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
184                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
185                         if (timeout_retries-- > 0) {
186                                 dev_dbg(&dp->dc->ndev->dev,
187                                         "dp: aux write retry (0x%x) -- %d\n",
188                                         *aux_stat, timeout_retries);
189                                 continue;
190                         } else {
191                                 dev_err(&dp->dc->ndev->dev, "dp: aux write got error (0x%x)\n",
192                                         *aux_stat);
193                                 return -EFAULT;
194                         }
195                 }
196
197                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
198                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
199                         if (defer_retries-- > 0) {
200                                 dev_dbg(&dp->dc->ndev->dev,
201                                         "dp: aux write defer (0x%x) -- %d\n",
202                                         *aux_stat, defer_retries);
203                                 continue;
204                         } else {
205                                 dev_err(&dp->dc->ndev->dev,
206                                         "dp: aux write defer exceeds max retries (0x%x)\n",
207                                         *aux_stat);
208                                 return -EFAULT;
209                         }
210                 }
211
212                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
213                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
214                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
215                         return 0;
216                 } else {
217                         dev_err(&dp->dc->ndev->dev,
218                                 "dp: aux write failed (0x%x)\n", *aux_stat);
219                         return -EFAULT;
220                 }
221         }
222         /* Should never come to here */
223         return -EFAULT;
224 }
225
226 static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
227         u8 *data, u32 *size, u32 *aux_stat)
228 {
229         u32     cur_size = 0;
230         u32     finished = 0;
231         int     ret      = 0;
232
233         do {
234                 cur_size = *size - finished;
235                 if (cur_size >= DP_AUX_MAX_BYTES)
236                         cur_size = DP_AUX_MAX_BYTES - 1;
237                 ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
238                         data, &cur_size, aux_stat);
239
240                 finished += cur_size;
241                 addr += cur_size;
242                 data += cur_size;
243
244                 if (ret)
245                         break;
246         } while (*size >= finished);
247
248         *size = finished;
249         return ret;
250 }
251
252 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
253         u32 addr, u8 *data, u32 *size, u32 *aux_stat)
254 {
255         unsigned long   reg_val;
256         u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
257         u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
258
259         if (*size >= DP_AUX_MAX_BYTES)
260                 return -EINVAL; /* only read one chunk */
261
262         /* Check to make sure the command is read command */
263         switch (cmd) {
264         case DPAUX_DP_AUXCTL_CMD_I2CRD:
265         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
266         case DPAUX_DP_AUXCTL_CMD_MOTRD:
267         case DPAUX_DP_AUXCTL_CMD_AUXRD:
268                 break;
269         default:
270                 dev_err(&dp->dc->ndev->dev,
271                         "dp: aux read cmd 0x%x is invalid\n", cmd);
272                 return -EINVAL;
273         }
274
275 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
276         *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
277         if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
278                 dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
279                 return -EFAULT;
280         }
281 #endif
282
283         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
284
285         reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
286         reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
287         reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
288         reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
289         reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
290
291         while ((timeout_retries > 0) && (defer_retries > 0)) {
292                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
293                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
294                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
295                                 DP_DPCP_RETRY_SLEEP_NS << 1);
296
297
298                 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
299                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
300
301                 if (tegra_dpaux_wait_transaction(dp))
302                         dev_err(&dp->dc->ndev->dev,
303                                 "dp: aux read transaction timeout\n");
304
305                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
306
307                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
308                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
309                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
310                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
311                         if (timeout_retries-- > 0) {
312                                 dev_dbg(&dp->dc->ndev->dev,
313                                         "dp: aux read retry (0x%x) -- %d\n",
314                                         *aux_stat, timeout_retries);
315                                 continue; /* retry */
316                         } else {
317                                 dev_err(&dp->dc->ndev->dev, "dp: aux read got error (0x%x)\n",
318                                         *aux_stat);
319                                 return -EFAULT;
320                         }
321                 }
322
323                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
324                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
325                         if (defer_retries-- > 0) {
326                                 dev_dbg(&dp->dc->ndev->dev,
327                                         "dp: aux read defer (0x%x) -- %d\n",
328                                         *aux_stat, defer_retries);
329                                 continue;
330                         } else {
331                                 dev_err(&dp->dc->ndev->dev,
332                                         "dp: aux read defer exceeds max retries (0x%x)\n",
333                                         *aux_stat);
334                                 return -EFAULT;
335                         }
336                 }
337
338                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
339                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
340                         int i;
341                         u32 temp_data[4];
342
343                         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
344                                 temp_data[i] = tegra_dpaux_readl(dp,
345                                         DPAUX_DP_AUXDATA_READ_W(i));
346
347                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
348                         memcpy(temp_data, data, *size);
349
350                         return 0;
351                 } else {
352                         dev_err(&dp->dc->ndev->dev,
353                                 "dp: aux read failed (0x%x\n", *aux_stat);
354                         return -EFAULT;
355                 }
356         }
357         /* Should never come to here */
358         return -EFAULT;
359 }
360
361 static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
362         u8 *data, u32 *size, u32 *aux_stat)
363 {
364         u32     finished = 0;
365         u32     cur_size;
366         int     ret      = 0;
367
368         do {
369                 cur_size = *size - finished;
370                 if (cur_size >= DP_AUX_MAX_BYTES)
371                         cur_size = DP_AUX_MAX_BYTES - 1;
372
373                 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
374                         data, &cur_size, aux_stat);
375
376                 /* cur_size should be the real size returned */
377                 addr += cur_size;
378                 data += cur_size;
379                 finished += cur_size;
380
381                 if (ret)
382                         break;
383         } while (*size >= finished);
384
385         *size = finished;
386         return ret;
387 }
388
389 static inline int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
390         u8 *data_ptr)
391 {
392         u32 size = 0;
393         u32 status = 0;
394         int ret;
395
396         ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
397                 cmd, data_ptr, &size, &status);
398         if (!ret)
399                 dev_err(&dp->dc->ndev->dev,
400                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
401                         cmd, status);
402
403         return ret;
404 }
405
406 static inline int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
407         u8 data)
408 {
409         u32 size = 0;
410         u32 status = 0;
411         int ret;
412
413         ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
414                 cmd, &data, &size, &status);
415         if (!ret)
416                 dev_err(&dp->dc->ndev->dev,
417                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
418                         cmd, status);
419         return ret;
420 }
421
422
423 static inline u64 tegra_div64(u64 dividend, u32 divisor)
424 {
425         do_div(dividend, divisor);
426         return dividend;
427 }
428
429
430 static int tegra_dc_init_max_link_cfg(struct tegra_dc_dp_data *dp,
431         struct tegra_dc_dp_link_config *cfg)
432 {
433         u8     dpcd_data;
434         int    ret;
435
436         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
437                         &dpcd_data));
438         cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
439
440         cfg->support_enhanced_framing =
441                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
442                 true : false;
443
444         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
445                         &dpcd_data));
446         cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
447                 true : false;
448
449         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
450                         &cfg->max_link_bw));
451
452         cfg->bytes_per_pixel = dp->dc->pdata->fb->bits_per_pixel / 8;
453
454         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
455                         &dpcd_data));
456         cfg->alt_scramber_reset_cap =
457                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
458                 true : false;
459         cfg->only_enhanced_framing =
460                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
461                 true : false;
462
463         return 0;
464 }
465
466 static bool tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp,
467         struct tegra_dc_dp_link_config *cfg)
468 {
469         if (cfg->link_bw == DP_LINK_SPEED_G1_62) {
470                 if (cfg->max_link_bw > DP_LINK_SPEED_G1_62)
471                         cfg->link_bw = DP_LINK_SPEED_G2_7;
472                 cfg->lane_count /= 2;
473         } else if (cfg->link_bw == DP_LINK_SPEED_G2_7)
474                 cfg->link_bw = DP_LINK_SPEED_G1_62;
475         else if (cfg->link_bw == DP_LINK_SPEED_G5_4) {
476                 if (cfg->lane_count == 1) {
477                         cfg->link_bw = DP_LINK_SPEED_G2_7;
478                         cfg->lane_count = cfg->max_lane_count;
479                 } else
480                         cfg->lane_count /= 2;
481         } else {
482                 dev_err(&dp->dc->ndev->dev,
483                         "dp: Error link rate %d\n", cfg->link_bw);
484                 return false;
485         }
486         return (cfg->lane_count > 0);
487 }
488
489
490 /* Calcuate if given cfg can meet the mode request. */
491 /* Return true if mode is possible, false otherwise. */
492 static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
493         const struct tegra_dc_mode *mode,
494         struct tegra_dc_dp_link_config *cfg)
495 {
496         const u32       link_rate = 27 * cfg->link_bw * 1000 * 1000;
497         const u64       f         = 100000;     /* precision factor */
498
499         u32     num_linkclk_line; /* Number of link clocks per line */
500         u64     ratio_f; /* Ratio of incoming to outgoing data rate */
501         u64     frac_f;
502         u64     activesym_f;    /* Activesym per TU */
503         u64     activecount_f;
504         u32     activecount;
505         u32     activepolarity;
506         u32     activefrac;
507         u64     approx_value_f;
508         u64     accumulated_error_f       = 0;
509         u32     lowest_neg_activecount    = 0;
510         u32     lowest_neg_activepolarity = 0;
511         u32     lowest_neg_tusize         = 64;
512         u32     num_symbols_per_line;
513         u64     lowest_neg_activefrac     = 0;
514         u64     lowest_neg_error_f        = 64 * f;
515         u64     watermark_f;
516
517         int     i;
518         bool    neg;
519
520
521         if (!link_rate || !cfg->lane_count || !mode->pclk ||
522                 !cfg->bytes_per_pixel)
523                 return false;
524
525         if (mode->pclk * cfg->bytes_per_pixel >=
526                 8 * link_rate * cfg->lane_count)
527                 return false;
528
529         num_linkclk_line = (u32)tegra_div64(
530                 (u64)link_rate * mode->h_active, mode->pclk);
531
532         ratio_f = (u64)mode->pclk * cfg->bytes_per_pixel * f;
533         ratio_f /= 8;
534         ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
535
536         for (i = 64; i >= 32; --i) {
537                 activesym_f     = ratio_f * i;
538                 activecount_f   = tegra_div64(activesym_f, (u32)f) * f;
539                 frac_f          = activesym_f - activecount_f;
540                 activecount     = (u32)tegra_div64(activecount_f, (u32)f);
541
542                 if (frac_f < (f / 2)) /* fraction < 0.5 */
543                         activepolarity = 0;
544                 else {
545                         activepolarity = 1;
546                         frac_f = f - frac_f;
547                 }
548
549                 if (frac_f != 0) {
550                         frac_f = tegra_div64((f * f),  frac_f); /* 1/fraction */
551                         if (frac_f > (15 * f))
552                                 activefrac = activepolarity ? 1 : 15;
553                         else
554                                 activefrac = activepolarity ?
555                                         (u32)tegra_div64(frac_f, (u32)f) + 1 :
556                                         (u32)tegra_div64(frac_f, (u32)f);
557                 }
558
559                 if (activefrac == 1)
560                         activepolarity = 0;
561
562                 if (activepolarity == 1)
563                         approx_value_f = activefrac ? tegra_div64(
564                                 activecount_f + (activefrac * f - f) * f,
565                                 (activefrac * f)) :
566                                 activecount_f + f;
567                 else
568                         approx_value_f = activefrac ?
569                                 activecount_f + tegra_div64(f, activefrac) :
570                                 activecount_f;
571
572                 if (activesym_f < approx_value_f) {
573                         accumulated_error_f = num_linkclk_line *
574                                 tegra_div64(approx_value_f - activesym_f, i);
575                         neg = true;
576                 } else {
577                         accumulated_error_f = num_linkclk_line *
578                                 tegra_div64(activesym_f - approx_value_f, i);
579                         neg = false;
580                 }
581
582                 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
583                         (accumulated_error_f == 0)) {
584                         lowest_neg_error_f = accumulated_error_f;
585                         lowest_neg_tusize = i;
586                         lowest_neg_activecount = activecount;
587                         lowest_neg_activepolarity = activepolarity;
588                         lowest_neg_activefrac = activefrac;
589
590                         if (accumulated_error_f == 0)
591                                 break;
592                 }
593         }
594
595         if (lowest_neg_activefrac == 0) {
596                 cfg->activepolarity = 0;
597                 cfg->active_count   = lowest_neg_activepolarity ?
598                         lowest_neg_activecount : lowest_neg_activecount - 1;
599                 cfg->tu_size          = lowest_neg_tusize;
600                 cfg->active_frac    = 1;
601         } else {
602                 cfg->activepolarity = lowest_neg_activepolarity;
603                 cfg->active_count   = (u32)lowest_neg_activecount;
604                 cfg->tu_size          = lowest_neg_tusize;
605                 cfg->active_frac    = (u32)lowest_neg_activefrac;
606         }
607
608         dev_dbg(&dp->dc->ndev->dev,
609                 "dp: sor configuration: polarity: %d active count: %d "
610                 "tu size: %d, active frac: %d\n",
611                 cfg->activepolarity, cfg->active_count, cfg->tu_size,
612                 cfg->active_frac);
613
614         watermark_f = ratio_f * cfg->tu_size * tegra_div64(f - ratio_f, f);
615         cfg->watermark = 2*((cfg->bytes_per_pixel) * f / 8) + watermark_f +
616                 (u32)tegra_div64(lowest_neg_error_f, (u32)f) - 1;
617         num_symbols_per_line = (mode->h_active * cfg->bytes_per_pixel) /
618                 (8 * cfg->lane_count);
619         if (cfg->watermark > 30) {
620                 dev_dbg(&dp->dc->ndev->dev,
621                         "dp: sor setting: unable to get a good tusize, "
622                         "force watermark to 30.\n");
623                 cfg->watermark = 30;
624                 return false;
625         } else if (cfg->watermark > num_symbols_per_line) {
626                 dev_dbg(&dp->dc->ndev->dev,
627                         "dp: sor setting: force watermark to the number "
628                         "of symbols in the line.\n");
629                 cfg->watermark = num_symbols_per_line;
630                 return false;
631         }
632
633         /* Refer to dev_disp.ref for more information. */
634         /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
635         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
636         /*                      - 3 * enhanced_framing - Y */
637         /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
638         cfg->hblank_sym = tegra_div64((u64)(mode->h_back_porch +
639                         mode->h_front_porch + mode->h_sync_width - 7)
640                 * link_rate, mode->pclk)
641                 - 3 * cfg->enhanced_framing - (12 / cfg->lane_count);
642
643         if (cfg->hblank_sym < 0)
644                 cfg->hblank_sym = 0;
645
646
647         /* Refer to dev_disp.ref for more information. */
648         /* # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
649         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
650         /*                      - Y - 1; */
651         /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
652         cfg->vblank_sym = tegra_div64((u64)(mode->v_back_porch +
653                         mode->v_front_porch + mode->v_sync_width - 25)
654                 * link_rate, mode->pclk) - (36 / cfg->lane_count) - 4;
655
656         if (cfg->vblank_sym < 0)
657                 cfg->vblank_sym = 0;
658         return true;
659 }
660
661 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
662 {
663         int ret;
664
665         u8 dpcd_data = ena ?
666                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
667                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
668
669         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
670                         dpcd_data));
671
672         /* Also reset the scrambler to 0xfffe */
673         tegra_dc_sor_set_internal_panel(dp->sor, ena);
674         return 0;
675 }
676
677
678 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
679 {
680         tegra_dc_sor_set_link_bandwidth(dp->sor, link_bw);
681
682         /* Sink side */
683         return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
684 }
685
686 static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
687         const struct tegra_dc_dp_link_config *cfg)
688 {
689         u8      dpcd_data;
690         int     ret;
691
692         /* check if panel support enhanched_framing */
693         dpcd_data = cfg->lane_count;
694         if (cfg->enhanced_framing)
695                 dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T;
696         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET,
697                         dpcd_data));
698
699         tegra_dc_sor_set_lane_count(dp->sor, cfg->lane_count);
700
701         /* Also power down lanes that will not be used */
702         return tegra_dc_sor_powerdown_dplanes(dp->sor, cfg->lane_count);
703 }
704
705 static int tegra_dc_dp_set_lane_config(struct tegra_dc_dp_data *dp,
706         u32 lane_count, const u8 *edc, const u8 *c2, u8 training_pattern)
707 {
708         u32 lane;
709         u8  pre_emphasis;
710         u8  drive_current;
711         u8  post_cursor2;
712         u8  temp_edc[5];
713         u8  temp_c2[2];
714         u32 size;
715         u32 status;
716         int ret;
717
718         temp_c2[0] = temp_c2[1] = 0;
719         memset(temp_edc, 0, sizeof(temp_edc));
720         for (lane = 0; lane < lane_count; ++lane) {
721                 if (lane & 1) { /* Lane 1, 3 */
722                         pre_emphasis = (edc[lane/2] &
723                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >>
724                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT;
725                         drive_current = (edc[lane/2] &
726                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >>
727                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT;
728                 } else {        /* Lane 0, 2 */
729                         pre_emphasis = (edc[lane/2] &
730                                 NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
731                                 NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT;
732                         drive_current = (edc[lane/2] &
733                                 NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>
734                                 NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT;
735                 }
736                 post_cursor2 = (*c2 >>
737                         NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(lane)) &
738                         NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK;
739
740                 temp_edc[lane+1] = drive_current <<
741                         NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT;
742                 if (drive_current == driveCurrent_Level3)
743                         temp_edc[lane+1] |=
744                                 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T;
745                 temp_edc[lane+1] |=
746                         (pre_emphasis << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT);
747                 if (pre_emphasis == preEmphasis_Level3)
748                         temp_edc[lane+1] |=
749                                 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T;
750
751                 if (lane & 1) { /* lane 1 and 3 */
752                         temp_c2[lane/2] |= post_cursor2 <<
753                                 NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT;
754                         if (post_cursor2 == postCursor2_Level3)
755                                 temp_c2[lane/2] |=
756                                      NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T;
757                 } else {        /* lane 0 and 2 */
758                         temp_c2[lane/2] |= post_cursor2 <<
759                                 NV_DPCD_LANEX_SET2_PC2_SHIFT;
760                         if (post_cursor2 == postCursor2_Level3)
761                                 temp_c2[lane/2] |=
762                                         NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T;
763                 }
764
765                 tegra_dc_sor_set_dp_lanedata(dp->sor, lane_count, post_cursor2,
766                         pre_emphasis, drive_current);
767         }
768
769         usleep_range(10, 30);
770
771         /* Now program the sink */
772         if (training_pattern != trainingPattern_None) {
773                 tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_PATTERN_SET,
774                         temp_edc);
775                 temp_edc[0] &= NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK;
776                 temp_edc[0] |= (training_pattern &
777                         NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK);
778
779                 size = 4;
780                 ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
781                         NV_DPCD_TRAINING_PATTERN_SET, temp_edc, &size, &status);
782                 if (ret) {
783                         dev_err(&dp->dc->ndev->dev,
784                                 "Failed to set NV_DPCD_TRAINING_PATTERN_SET\n");
785                         return ret;
786                 }
787         } else {                /* No training pattern, only set LANE config */
788                 size = 3;
789                 ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
790                         NV_DPCD_TRAINING_LANE0_SET, temp_edc+1, &size, &status);
791                 if (ret) {
792                         dev_err(&dp->dc->ndev->dev,
793                                 "Failed to set NV_DPCD_TRAINING_LANE0_SET\n");
794                         return ret;
795                 }
796         }
797
798         size = 1;
799         ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
800                 NV_DPCD_TRAINING_LANE0_1_SET2, temp_c2, &size, &status);
801         if (ret)
802                 dev_err(&dp->dc->ndev->dev,
803                         "Failed to set NV_DPCD_TRAINING_LANE0_1_SET2\n");
804         return ret;
805 }
806
807
808 static int tegra_dc_dpcd_read_lane_request(struct tegra_dc_dp_data *dp,
809         u32 lane_count, u8 *edc, u8* c2)
810 {
811         u32 size;
812         int ret;
813         u32 status;
814
815         /* read the new preemphasis & drive current values */
816         size = lane_count/2;
817         ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
818                 NV_DPCD_LANE0_1_ADJUST_REQ, edc, &size, &status);
819         if (ret) {
820                 dev_err(&dp->dc->ndev->dev,
821                         "Failed to read NV_DPCD_LANE0_1_ADJUST_REQ\n");
822                 return ret;
823         }
824         return tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2, c2);
825 }
826
827 static int tegra_dc_dp_lt_clock_recovery(struct tegra_dc_dp_data *dp,
828         const struct tegra_dc_dp_link_config *cfg)
829 {
830
831         int     ret;
832         u8      edc_data[2] = { 0, 0 };
833         u8      c2_data = 0;
834         u32     lane;
835         u8      temp_edc[4];
836         u8      data;
837         u32     cr_done;
838         bool    sl_changed;
839         u32     sl_max_count;
840         u32     sl_retry_count;
841         u8      mask;
842         u32     retry_count;
843
844
845         /* Set pattern on the source side */
846         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_1,
847                 cfg, false);
848
849         /* Now the sink side */
850         ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
851                 &c2_data, trainingPattern_1);
852         if (ret)
853                 dev_dbg(&dp->dc->ndev->dev,
854                         "Failed to set the sink link for clock recovery\n");
855
856         sl_retry_count = 0;
857         retry_count = 0;
858         do {
859                 usleep_range(100, 200);
860                 temp_edc[0] = edc_data[0];
861                 temp_edc[1] = edc_data[1];
862
863                 /* read lane registers for all the lanes */
864                 for (lane = 0, cr_done = 0; lane < cfg->lane_count; ++lane) {
865                         ret = tegra_dc_dp_dpcd_read(dp,
866                                 (lane/2) ? NV_DPCD_LANE2_3_STATUS :
867                                 NV_DPCD_LANE0_1_STATUS, &data);
868                         if (ret)
869                                 return ret;
870
871                         mask = (lane & 1) ?
872                                 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES :
873                                 NV_DPCD_STATUS_LANEX_CR_DONE_YES;
874
875                         if (data & mask)
876                                 cr_done++;
877                         else    /* no need to check the rest of the lanes */
878                                 break;
879                 }
880
881                 if (cr_done == cfg->lane_count)
882                         break;  /* Success -- Done with clock recovery */
883
884                 /* Check if the swing-levels changed or reached maxium */
885                 sl_max_count = 0;
886                 sl_changed = false;
887                 for (lane = 0; lane < cfg->lane_count; ++lane) {
888                         mask = (lane & 1) ?
889                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK :
890                                 NV_DPCD_ADJUST_REQ_LANEX_DC_MASK;
891                         if ((edc_data[lane/2] & mask) !=
892                                 (temp_edc[lane/2] & mask)) {
893                                 sl_changed = true;
894                                 sl_retry_count = 0;
895                                 break;
896                         }
897                         if ((edc_data[lane/2] & mask) == driveCurrent_Level3)
898                                 sl_max_count++;
899                 }
900
901                 if (sl_max_count == cfg->lane_count) {
902                         dev_err(&dp->dc->ndev->dev,
903                                 "Reached MAX_SWING_LEVEL yet CR_LOCK failed\n");
904                         return -EFAULT;
905                 }
906                 if (!sl_changed && (sl_retry_count++ >
907                                 DP_CLOCK_RECOVERY_MAX_TRIES)) {
908                         dev_err(&dp->dc->ndev->dev, "Exceeded max combination\n");
909                         return -EFAULT;
910                 }
911
912                 /* Read the config on the sink side */
913                 ret = tegra_dc_dpcd_read_lane_request(dp, cfg->lane_count,
914                         edc_data, &c2_data);
915
916                 /* Write the data */
917                 ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
918                         &c2_data, trainingPattern_None);
919                 if (ret) {
920                         dev_err(&dp->dc->ndev->dev,
921                                 "Failed to update lane configuration");
922                         return ret;
923                 }
924         } while (++retry_count < DP_CLOCK_RECOVERY_TOT_TRIES);
925
926         if (retry_count == DP_CLOCK_RECOVERY_TOT_TRIES) {
927                 dev_err(&dp->dc->ndev->dev, "Exceeded max retry times\n");
928                 return -EFAULT;
929         }
930         return ret;
931 }
932
933 static int tegra_dc_dp_lt_channel_equalization(struct tegra_dc_dp_data *dp,
934         const struct tegra_dc_dp_link_config *cfg)
935 {
936         int ret;
937         u8  data;
938         u8  edc_data[2] = { 0, 0 };
939         u8  c2_data = 0;
940         u8  updated_status;
941         u32 tries;
942         u8  lane;
943         u32 ce_done;
944         u8  mask;
945
946
947         /* Set pattern on the source side */
948         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_2,
949                 cfg, true);
950
951         /* Now the sink side */
952         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_PATTERN_SET,
953                         &data));
954
955         data &= ~NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK;
956         data |= trainingPattern_2;
957
958         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
959                         data));
960
961         usleep_range(400, 800);
962
963         for (tries = 0; tries <= DP_CLOCK_RECOVERY_MAX_TRIES; ++tries) {
964                 ret = tegra_dc_dpcd_read_lane_request(dp, cfg->lane_count,
965                         edc_data, &c2_data);
966                 if (ret)
967                         return ret;
968                 /* Write the data */
969                 ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
970                         &c2_data, trainingPattern_None);
971                 if (ret) {
972                         dev_err(&dp->dc->ndev->dev,
973                                 "Failed to update lane configuration");
974                         return ret;
975                 }
976
977                 usleep_range(400, 800);
978
979                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
980                                 NV_DPCD_LANE_ALIGN_STATUS_UPDATED,
981                                 &updated_status));
982
983                 for (lane = 0, ce_done = 0; lane < cfg->lane_count; ++lane) {
984                         CHECK_RET(tegra_dc_dp_dpcd_read(dp,
985                                         (lane/2) ? NV_DPCD_LANE2_3_STATUS :
986                                         NV_DPCD_LANE0_1_STATUS,
987                                         &data));
988
989                         mask = (lane & 1) ?
990                                 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
991                                 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
992                                 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
993                                 NV_DPCD_STATUS_LANEX_CR_DONE_YES |
994                                 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
995                                 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
996
997                         if (((data & mask) == mask)
998                                 && (updated_status &
999                                     NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES))
1000                                 ce_done++;
1001                         else
1002                                 /* no need to check the rest of the lanes */
1003                                 break;
1004                 }
1005
1006                 if ((data & NV_DPCD_STATUS_LANEX_CR_DONE_YES) == 0) {
1007                         dev_err(&dp->dc->ndev->dev,
1008                                 "Clock recovery has not been locked\n");
1009                         return -EFAULT;
1010                 }
1011
1012                 if (ce_done == cfg->lane_count) {
1013                         /* All lanes done with training */
1014                         dev_dbg(&dp->dc->ndev->dev,
1015                                 "Channel Equalization passed\n");
1016                         return 0;
1017                 }
1018         }
1019
1020         /* Reaches max tries */
1021         dev_err(&dp->dc->ndev->dev,
1022                 "Channel Equalization exceeded max combinations\n");
1023         return -EFAULT;
1024 }
1025
1026
1027 static int tegra_dc_dp_link_training(struct tegra_dc_dp_data *dp,
1028         const struct tegra_dc_dp_link_config *cfg)
1029 {
1030         int ret = tegra_dc_dp_lt_clock_recovery(dp, cfg);
1031         if (ret)
1032                 dev_dbg(&dp->dc->ndev->dev,
1033                         "DP: failed link training clock recovery with "
1034                         "lane %d bw %d\n", cfg->lane_count, cfg->link_bw);
1035         else {
1036                 ret = tegra_dc_dp_lt_channel_equalization(dp, cfg);
1037
1038                 if (ret)
1039                         dev_dbg(&dp->dc->ndev->dev,
1040                                 "DP: failed link training channel equal with "
1041                                 "lane %d bw %d\n",
1042                                 cfg->lane_count, cfg->link_bw);
1043         }
1044
1045         /* TODO: read back the link status for debugging purpose */
1046         return ret;
1047 }
1048
1049 static bool tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
1050         struct tegra_dc_dp_link_config *cfg)
1051 {
1052         u32 lane;
1053         u8  mask;
1054         u8  data;
1055         int ret;
1056
1057         for (lane = 0; lane < cfg->lane_count; ++lane) {
1058                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ?
1059                                 NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS,
1060                                 &data));
1061                 mask = (lane & 1) ?
1062                         NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
1063                         NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
1064                         NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
1065                         NV_DPCD_STATUS_LANEX_CR_DONE_YES |
1066                         NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
1067                         NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
1068                 if ((data & mask) != mask)
1069                         return false;
1070         }
1071         return true;
1072 }
1073
1074
1075 static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
1076         struct tegra_dc_dp_link_config *cfg)
1077 {
1078         struct tegra_dc_sor_data *sor = dp->sor;
1079         int ret;
1080
1081         tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
1082         tegra_dc_sor_set_lane_count(sor, cfg->lane_count);
1083
1084         /* Send TP1 */
1085         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_1, cfg,
1086                 false);
1087
1088         usleep_range(500, 1000);
1089         /* enable ASSR */
1090         tegra_dc_dp_set_assr(dp, true);
1091         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_2, cfg,
1092                 true);
1093
1094         usleep_range(500, 1000);
1095         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_Disabled,
1096                 cfg, false);
1097
1098         ret = tegra_dc_dp_link_trained(dp, cfg);
1099         if (!ret) {
1100                 tegra_dc_sor_read_link_config(dp->sor, &cfg->link_bw,
1101                         &cfg->lane_count);
1102         }
1103         return ret;
1104 }
1105
1106 static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
1107         const struct tegra_dc_dp_link_config *cfg)
1108 {
1109         u8      dpcd_data;
1110         u8      link_bw;
1111         u8      lane_count;
1112         u32     retry;
1113         int     ret;
1114
1115         if (cfg->lane_count == 0) {
1116                 /* TODO: shutdown the link */
1117                 return 0;
1118         }
1119
1120         /* Set power state if it is not in normal level */
1121         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data));
1122         if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
1123                 dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
1124                 retry = 3;      /* DP spec requires 3 retries */
1125                 do {
1126                         ret = tegra_dc_dp_dpcd_write(dp,
1127                                 NV_DPCD_SET_POWER, dpcd_data);
1128                 } while ((--retry > 0) && (ret != 0));
1129                 if (ret) {
1130                         dev_err(&dp->dc->ndev->dev,
1131                                 "dp: Failed to set DP panel power\n");
1132                         return ret;
1133                 }
1134         }
1135
1136         /* Enable ASSR if possible */
1137         if (cfg->alt_scramber_reset_cap)
1138                 CHECK_RET(tegra_dc_dp_set_assr(dp, true));
1139
1140         ret = tegra_dp_set_link_bandwidth(dp, cfg->link_bw);
1141         if (ret) {
1142                 dev_err(&dp->dc->ndev->dev, "dp: Failed to set link bandwidth\n");
1143                 return ret;
1144         }
1145         ret = tegra_dp_set_lane_count(dp, cfg);
1146         if (ret) {
1147                 dev_err(&dp->dc->ndev->dev, "dp: Failed to set lane count\n");
1148                 return ret;
1149         }
1150         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_Disabled,
1151                 cfg, true);
1152
1153         /* Now do the link training */
1154         ret = tegra_dc_dp_link_training(dp, cfg);
1155         if (ret) {
1156                 dev_dbg(&dp->dc->ndev->dev, "dp: link training failed\n");
1157                 return ret;
1158         }
1159
1160         /* Everything goes well, double check the link config */
1161         /* TODO: record edc/c2 data for debugging */
1162         tegra_dc_sor_read_link_config(dp->sor, &link_bw, &lane_count);
1163
1164         if ((cfg->link_bw == link_bw) && (cfg->lane_count == lane_count))
1165                 return 0;
1166         else
1167                 return -EFAULT;
1168 }
1169
1170 static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
1171         struct tegra_dc_dp_link_config *cfg, struct tegra_dc_mode *mode)
1172 {
1173         struct tegra_dc_dp_link_config temp_cfg;
1174
1175         if (!mode->pclk || !mode->h_active || !mode->v_active) {
1176                 dev_err(&dp->dc->ndev->dev,
1177                         "dp: error mode configuration");
1178                 return -EINVAL;
1179         }
1180         if (!cfg->max_link_bw || !cfg->max_lane_count) {
1181                 dev_err(&dp->dc->ndev->dev,
1182                         "dp: error link configuration");
1183                 return -EINVAL;
1184         }
1185
1186         cfg->is_valid = false;
1187         memcpy(cfg, &temp_cfg, sizeof(temp_cfg));
1188
1189         temp_cfg.link_bw    = temp_cfg.max_link_bw;
1190         temp_cfg.lane_count = temp_cfg.max_lane_count;
1191
1192         while (tegra_dc_dp_calc_config(dp, mode, &temp_cfg) &&
1193                 tegra_dp_link_config(dp, &temp_cfg)) {
1194                 /* current link cfg is doable */
1195                 memcpy(&temp_cfg, cfg, sizeof(temp_cfg));
1196                 cfg->is_valid = true;
1197
1198                 /* try to lower the config */
1199                 if (!tegra_dc_dp_lower_config(dp, &temp_cfg))
1200                         break;
1201         }
1202
1203         return cfg->is_valid ? 0 : -EFAULT;
1204 }
1205
1206 static void tegra_dc_dp_lt_worker(struct work_struct *work)
1207 {
1208         struct tegra_dc_dp_data *dp =
1209                 container_of(work, struct tegra_dc_dp_data, lt_work);
1210
1211         tegra_dc_disable(dp->dc);
1212
1213         if (!dp->link_cfg.is_valid ||
1214                 !tegra_dp_link_config(dp, &dp->link_cfg)) {
1215                 /* If current config is not valid or cannot be trained,
1216                    needs to re-explore the possilbe config */
1217                 if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg))
1218                         dev_err(&dp->dc->ndev->dev,
1219                                 "dp: failed to init link configuration\n");
1220                 else if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg,
1221                                 dp->mode))
1222                         dev_err(&dp->dc->ndev->dev,
1223                                 "dp irq: cannot get working config\n");
1224         }
1225
1226         tegra_dc_enable(dp->dc);
1227 }
1228
1229
1230 static irqreturn_t tegra_dc_dp_hpd_irq(int irq, void *ptr)
1231 {
1232         struct tegra_dc         *dc = ptr;
1233         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1234         u8                       data;
1235         u8                       clear_data = 0;
1236
1237         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR,
1238                         &data))
1239                 dev_err(&dc->ndev->dev, "dp: failed to read IRQ_VECTOR\n");
1240
1241         dev_dbg(&dc->ndev->dev,
1242                 "dp irq: Trying to handle HPD with DPCD_IRQ_VECTOR 0x%x\n",
1243                 data);
1244
1245         /* For eDP only answer auto_test_request */
1246         if (data & NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES &&
1247                 dp->link_cfg.is_valid) {
1248                 /* Schedule to do the link training */
1249                 schedule_work(&dp->lt_work);
1250
1251                 /* Now clear auto_test bit */
1252                 clear_data |= NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES;
1253         }
1254
1255         if (clear_data)
1256                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR,
1257                         clear_data);
1258
1259         return IRQ_HANDLED;
1260 }
1261
1262 static int tegra_dc_dp_init(struct tegra_dc *dc)
1263 {
1264         struct tegra_dc_dp_data *dp;
1265         struct resource         *res;
1266         struct resource         *base_res;
1267         void __iomem            *base;
1268         struct clk              *clk;
1269         int                      err;
1270
1271
1272         dp = kzalloc(sizeof(*dp), GFP_KERNEL);
1273         if (!dp)
1274                 return -ENOMEM;
1275
1276         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "dpaux");
1277         if (!res) {
1278                 dev_err(&dc->ndev->dev, "dp: no mem resources for dpaux\n");
1279                 err = -EFAULT;
1280                 goto err_free_dp;
1281         }
1282
1283         base_res = request_mem_region(res->start, resource_size(res),
1284                 dc->ndev->name);
1285         if (!base_res) {
1286                 dev_err(&dc->ndev->dev, "dp: request_mem_region failed\n");
1287                 err = -EFAULT;
1288                 goto err_free_dp;
1289         }
1290
1291         base = ioremap(res->start, resource_size(res));
1292         if (!base) {
1293                 dev_err(&dc->ndev->dev, "dp: registers can't be mapped\n");
1294                 err = -EFAULT;
1295                 goto err_release_resource_reg;
1296         }
1297
1298         clk = clk_get(&dc->ndev->dev, "edp");
1299         if (IS_ERR_OR_NULL(clk)) {
1300                 dev_err(&dc->ndev->dev, "dp: dc clock %s.edp unavailable\n",
1301                         dev_name(&dc->ndev->dev));
1302                 err = -EFAULT;
1303                 goto err_iounmap_reg;
1304         }
1305
1306         /* TODO: confirm interrupt num is acquired from gpio_to_irq,
1307            Also how to differentiate them from HDMI HPD.
1308          */
1309         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_dp_hpd_irq,
1310                         IRQF_DISABLED | IRQF_TRIGGER_RISING |
1311                         IRQF_TRIGGER_FALLING, dev_name(&dc->ndev->dev), dc)) {
1312                 dev_err(&dc->ndev->dev, "dp: request_irq %d failed\n",
1313                         gpio_to_irq(dc->out->hotplug_gpio));
1314                 err = -EBUSY;
1315                 goto err_get_clk;
1316         }
1317
1318
1319         dp->dc           = dc;
1320         dp->aux_base     = base;
1321         dp->aux_base_res = base_res;
1322         dp->clk          = clk;
1323         dp->mode         = &dc->mode;
1324         dp->sor          = tegra_dc_sor_init(dc, &dp->link_cfg);
1325
1326         if (IS_ERR_OR_NULL(dp->sor)) {
1327                 err = PTR_ERR(dp->sor);
1328                 dp->sor = NULL;
1329                 goto err_get_clk;
1330         }
1331
1332         INIT_WORK(&dp->lt_work, tegra_dc_dp_lt_worker);
1333
1334         tegra_dc_set_outdata(dc, dp);
1335
1336         return 0;
1337
1338 err_get_clk:
1339         clk_put(clk);
1340 err_iounmap_reg:
1341         iounmap(base);
1342 err_release_resource_reg:
1343         release_resource(base_res);
1344 err_free_dp:
1345         kfree(dp);
1346
1347         return err;
1348 }
1349
1350 static void tegra_dc_dp_enable(struct tegra_dc *dc)
1351 {
1352         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1353         u8     data;
1354         u32    retry;
1355         int    ret;
1356
1357         tegra_dc_dpaux_enable(dp);
1358         clk_enable(dp->clk);
1359
1360         /* Power on panel */
1361         tegra_dc_sor_set_panel_power(dp->sor, true);
1362
1363         /* TODO: power on lanes as well? */
1364
1365         /* Enable backlight -- TODO: need to go through I2C */
1366
1367         msleep(DP_LCDVCC_TO_HPD_DELAY_MS);
1368
1369         /* Write power on to DPCD */
1370         data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
1371         retry = 0;
1372         do {
1373                 ret = tegra_dc_dp_dpcd_write(dp,
1374                         NV_DPCD_SET_POWER, data);
1375         } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1376
1377         if (ret) {
1378                 dev_err(&dp->dc->ndev->dev,
1379                         "dp: failed to power on panel (0x%x)\n", ret);
1380                 return;
1381         }
1382
1383         /* Confirm DP is plugging status */
1384 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1385         if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
1386                         DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
1387                 dev_err(&dp->dc->ndev->dev, "dp: could not detect HPD\n");
1388                 return;
1389         }
1390 #endif
1391
1392         /* Check DP version */
1393         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
1394                 dev_err(&dp->dc->ndev->dev,
1395                         "dp: failed to read the revision number from sink\n");
1396
1397         if (!dp->link_cfg.is_valid ||
1398                 tegra_dc_dp_fast_link_training(dp, &dp->link_cfg)) {
1399                 /* if valid link config is not ready yet, or current
1400                    config cannot be link-trained, try to find the
1401                    new minimal config */
1402                 if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg)) {
1403                         dev_err(&dp->dc->ndev->dev,
1404                                 "dp: failed to init link configuration\n");
1405                         return;
1406                 }
1407                 if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, dp->mode) ||
1408                         tegra_dc_dp_link_training(dp, &dp->link_cfg)) {
1409                         dev_err(&dp->dc->ndev->dev,
1410                                 "dp: Current mode is not possible\n");
1411                         return;
1412                 }
1413         }
1414
1415         /* enable SOR by programming the watermark/v/hblank_sym etc */
1416         tegra_dc_sor_enable(dp->sor);
1417 }
1418
1419 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
1420 {
1421         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1422
1423         if (dp->sor)
1424                 tegra_dc_sor_destroy(dp->sor);
1425         clk_put(dp->clk);
1426         iounmap(dp->aux_base);
1427         release_resource(dp->aux_base_res);
1428
1429         kfree(dp);
1430 }
1431
1432 static void tegra_dc_dp_disable(struct tegra_dc *dc)
1433 {
1434         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1435
1436         /* TODO: confirm that dpaux_disable is not needed for eDP */
1437         tegra_dc_dpaux_disable(dp);
1438
1439         /* Power down SOR */
1440         tegra_dc_sor_disable(dp->sor);
1441
1442         clk_disable(dp->clk);
1443         /* TODO: Now power down the panel -- through GPIO */
1444         /* Make sure the timing meet the eDP specs */
1445 }
1446
1447
1448
1449 static void tegra_dc_dp_suspend(struct tegra_dc *dc)
1450 {
1451         /* TBD */
1452 }
1453
1454
1455 static void tegra_dc_dp_resume(struct tegra_dc *dc)
1456 {
1457         /* TBD */
1458 }
1459
1460 struct tegra_dc_out_ops tegra_dc_dp_ops = {
1461         .init    = tegra_dc_dp_init,
1462         .destroy = tegra_dc_dp_destroy,
1463         .enable  = tegra_dc_dp_enable,
1464         .disable = tegra_dc_dp_disable,
1465         .suspend = tegra_dc_dp_suspend,
1466         .resume  = tegra_dc_dp_resume,
1467 };