3546ec277516c9716fee18e307a1a614ff171d31
[linux-3.10.git] / drivers / video / tegra / dc / dp.c
1 /*
2  * drivers/video/tegra/dc/dp.c
3  *
4  * Copyright (c) 2011, NVIDIA Corporation.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17
18 #include <linux/clk.h>
19 #include <linux/err.h>
20 #include <linux/fb.h>
21 #include <linux/gpio.h>
22 #include <linux/kernel.h>
23 #include <linux/nvhost.h>
24 #include <linux/wait.h>
25 #include <linux/delay.h>
26 #include <linux/interrupt.h>
27
28 #include <mach/clk.h>
29 #include <mach/dc.h>
30 #include <mach/fb.h>
31
32 #include "dp.h"
33 #include "sor.h"
34 #include "sor_regs.h"
35 #include "dpaux_regs.h"
36 #include "dc_priv.h"
37
38
39
40 static inline unsigned long tegra_dpaux_readl(struct tegra_dc_dp_data *dp,
41         unsigned long reg)
42 {
43         return readl(dp->aux_base + reg * 4);
44 }
45
46 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
47         unsigned long reg, unsigned long val)
48 {
49         writel(val, dp->aux_base + reg * 4);
50 }
51
52
53 static unsigned long tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
54         u32 reg, u32 mask, u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
55 {
56         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
57         u32 reg_val = 0;
58
59         do {
60                 usleep(poll_interval_us);
61                 reg_val = tegra_dpaux_readl(dp, reg);
62         } while (((reg_val & mask) != exp_val) &&
63                 time_after(timeout_jf, jiffies));
64
65         if ((reg_val & mask) == exp_val)
66                 return 0;       /* success */
67         dev_dbg(&dp->dc->ndev->dev,
68                 "sor_poll_register 0x%x: timeout\n", reg);
69         return jiffies - timeout_jf + 1;
70 }
71
72
73 static int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
74 {
75         /* According to DP spec, each aux transaction needs to finish
76            within 40ms. */
77         if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
78                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
79                         DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
80                         100, DP_AUX_TIMEOUT_MS) != 0) {
81                 dev_err(&dp->dc->ndev->dev,
82                         "dp: DPAUX transaction timeout\n");
83                 return -EFAULT;
84         }
85         return 0;
86 }
87
88
89 static void tegra_dc_dpaux_enable(struct tegra_dc_dp_data *dp)
90 {
91         unsigned long reg_val;
92
93         /* clear interrupt */
94         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
95         /* do not enable interrupt for now. Enable them when Isr in place */
96         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
97
98         /* Power up aux/hybrid pads */
99         /* TODO: this may not needed for t124 */
100         reg_val = DPAUX_HYBRID_SPARE_PAD_PWR_POWERUP;
101         tegra_dpaux_writel(dp, DPAUX_HYBRID_SPARE, reg_val);
102
103         /* Put HYBRID PAD in AUX mode */
104         reg_val = tegra_dpaux_readl(dp, DPAUX_HYBRID_PADCTL);
105         reg_val &= ~DPAUX_HYBRID_PADCTL_MODE_I2C;
106         reg_val |= DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE;
107         reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE;
108         reg_val &= ~DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE;
109         tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL, reg_val);
110
111 }
112
113 static void tegra_dc_dpaux_disable(struct tegra_dc_dp_data *dp)
114 {
115         tegra_dpaux_writel(dp, NV_DPCD_SET_POWER,
116                 NV_DPCD_SET_POWER_VAL_D3_PWRDWN);
117
118         /* TODO: power down DPAUX_HYBRID_SPARE too? */
119 }
120
121
122 static int tegra_dc_dpaux_write_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
123         u32 addr, u8 *data, u32 *size, u32 *aux_stat)
124 {
125         int             i;
126         unsigned long   reg_val;
127         u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
128         u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
129
130         if (*size >= DP_AUX_MAX_BYTES)
131                 return -EINVAL; /* only write one chunk of data */
132
133         /* Make sure the command is write command */
134         switch (cmd) {
135         case DPAUX_DP_AUXCTL_CMD_I2CWR:
136         case DPAUX_DP_AUXCTL_CMD_MOTWR:
137         case DPAUX_DP_AUXCTL_CMD_AUXWR:
138                 break;
139         default:
140                 dev_err(&dp->dc->ndev->dev, "dp: aux write cmd 0x%x is invalid\n",
141                         cmd);
142                 return -EINVAL;
143         }
144
145 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
146         *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
147         if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
148                 dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
149                 return -EFAULT;
150         }
151 #endif
152
153         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
154         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i) {
155                 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i),
156                         (unsigned long)*data);
157                 data += 4;
158         }
159
160         reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
161         reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
162         reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
163         reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
164         reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
165
166         while ((timeout_retries > 0) && (defer_retries > 0)) {
167                 /* Reset AUX first*/
168                 reg_val |= DPAUX_DP_AUXCTL_RST_ASSERT;
169                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
170                 reg_val &= ~DPAUX_DP_AUXCTL_RST_ASSERT;
171                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
172
173                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
174                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
175                         usleep(DP_DPCP_RETRY_SLEEP_NS);
176
177                 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
178                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
179
180                 if (tegra_dpaux_wait_transaction(dp))
181                         dev_err(&dp->dc->ndev->dev,
182                                 "dp: aux write transaction timeout\n");
183
184                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
185
186                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
187                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
188                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
189                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
190                         if (timeout_retries-- > 0) {
191                                 dev_dbg(&dp->dc->ndev->dev,
192                                         "dp: aux write retry (0x%x) -- %d\n",
193                                         *aux_stat, timeout_retries);
194                                 continue;
195                         } else {
196                                 dev_err(&dp->dc->ndev->dev, "dp: aux write got error (0x%x)\n",
197                                         *aux_stat);
198                                 return -EFAULT;
199                         }
200                 }
201
202                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
203                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
204                         if (defer_retries-- > 0) {
205                                 dev_dbg(&dp->dc->ndev->dev,
206                                         "dp: aux write defer (0x%x) -- %d\n",
207                                         *aux_stat, defer_retries);
208                                 continue;
209                         } else {
210                                 dev_err(&dp->dc->ndev->dev,
211                                         "dp: aux write defer exceeds max retries (0x%x)\n",
212                                         *aux_stat);
213                                 return -EFAULT;
214                         }
215                 }
216
217                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
218                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
219                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
220                         return 0;
221                 } else {
222                         dev_err(&dp->dc->ndev->dev,
223                                 "dp: aux write failed (0x%x)\n", *aux_stat);
224                         return -EFAULT;
225                 }
226         }
227         /* Should never come to here */
228         return -EFAULT;
229 }
230
231 static int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
232         u8 *data, u32 *size, u32 *aux_stat)
233 {
234         u32     cur_size = 0;
235         u32     finished = 0;
236         int     ret      = 0;
237
238         do {
239                 cur_size = *size - finished;
240                 if (cur_size >= DP_AUX_MAX_BYTES)
241                         cur_size = DP_AUX_MAX_BYTES - 1;
242                 ret = tegra_dc_dpaux_write_chunk(dp, cmd, addr,
243                         data, &cur_size, aux_stat);
244
245                 finished += cur_size;
246                 addr += cur_size;
247                 data += cur_size;
248
249                 if (ret)
250                         break;
251         } while (*size >= finished);
252
253         *size = finished;
254         return ret;
255 }
256
257 static int tegra_dc_dpaux_read_chunk(struct tegra_dc_dp_data *dp, u32 cmd,
258         u32 addr, u8 *data, u32 *size, u32 *aux_stat)
259 {
260         unsigned long   reg_val;
261         u32             timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
262         u32             defer_retries   = DP_AUX_DEFER_MAX_TRIES;
263
264         if (*size >= DP_AUX_MAX_BYTES)
265                 return -EINVAL; /* only read one chunk */
266
267         /* Check to make sure the command is read command */
268         switch (cmd) {
269         case DPAUX_DP_AUXCTL_CMD_I2CRD:
270         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
271         case DPAUX_DP_AUXCTL_CMD_MOTRD:
272         case DPAUX_DP_AUXCTL_CMD_AUXRD:
273                 break;
274         default:
275                 dev_err(&dp->dc->ndev->dev,
276                         "dp: aux read cmd 0x%x is invalid\n", cmd);
277                 return -EINVAL;
278         }
279
280 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
281         *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
282         if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
283                 dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
284                 return -EFAULT;
285         }
286 #endif
287
288         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
289
290         reg_val = tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL);
291         reg_val &= ~DPAUX_DP_AUXCTL_CMD_MASK;
292         reg_val |= (cmd << DPAUX_DP_AUXCTL_CMD_SHIFT);
293         reg_val &= ~DPAUX_DP_AUXCTL_CMDLEN_FIELD;
294         reg_val |= (*size << DPAUX_DP_AUXCTL_CMDLEN_SHIFT);
295
296         while ((timeout_retries > 0) && (defer_retries > 0)) {
297                 /* Reset AUX first*/
298                 reg_val |= DPAUX_DP_AUXCTL_RST_ASSERT;
299                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
300                 reg_val &= ~DPAUX_DP_AUXCTL_RST_ASSERT;
301                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
302
303                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
304                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
305                         usleep(DP_DPCP_RETRY_SLEEP_NS);
306
307
308                 reg_val |= DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING;
309                 tegra_dpaux_writel(dp, DPAUX_DP_AUXCTL, reg_val);
310
311                 if (tegra_dpaux_wait_transaction(dp))
312                         dev_err(&dp->dc->ndev->dev,
313                                 "dp: aux read transaction timeout\n");
314
315                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
316
317                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
318                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
319                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
320                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
321                         if (timeout_retries-- > 0) {
322                                 dev_dbg(&dp->dc->ndev->dev,
323                                         "dp: aux read retry (0x%x) -- %d\n",
324                                         *aux_stat, timeout_retries);
325                                 continue; /* retry */
326                         } else {
327                                 dev_err(&dp->dc->ndev->dev, "dp: aux read got error (0x%x)\n",
328                                         *aux_stat);
329                                 return -EFAULT;
330                         }
331                 }
332
333                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
334                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
335                         if (defer_retries-- > 0) {
336                                 dev_dbg(&dp->dc->ndev->dev,
337                                         "dp: aux read defer (0x%x) -- %d\n",
338                                         *aux_stat, defer_retries);
339                                 continue;
340                         } else {
341                                 dev_err(&dp->dc->ndev->dev,
342                                         "dp: aux read defer exceeds max retries (0x%x)\n",
343                                         *aux_stat);
344                                 return -EFAULT;
345                         }
346                 }
347
348                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
349                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
350                         int i;
351                         u32 temp_data[4];
352
353                         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
354                                 temp_data[i] = tegra_dpaux_readl(dp,
355                                         DPAUX_DP_AUXDATA_READ_W(i));
356
357                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
358                         memcpy(temp_data, data, *size);
359
360                         return 0;
361                 } else {
362                         dev_err(&dp->dc->ndev->dev,
363                                 "dp: aux read failed (0x%x\n", *aux_stat);
364                         return -EFAULT;
365                 }
366         }
367         /* Should never come to here */
368         return -EFAULT;
369 }
370
371 static int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
372         u8 *data, u32 *size, u32 *aux_stat)
373 {
374         u32     finished = 0;
375         u32     cur_size;
376         int     ret      = 0;
377
378         do {
379                 cur_size = *size - finished;
380                 if (cur_size >= DP_AUX_MAX_BYTES)
381                         cur_size = DP_AUX_MAX_BYTES - 1;
382
383                 ret = tegra_dc_dpaux_read_chunk(dp, cmd, addr,
384                         data, &cur_size, aux_stat);
385
386                 /* cur_size should be the real size returned */
387                 addr += cur_size;
388                 data += cur_size;
389                 finished += cur_size;
390
391                 if (ret)
392                         break;
393         } while (*size >= finished);
394
395         *size = finished;
396         return ret;
397 }
398
399 static inline int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
400         u8 *data_ptr)
401 {
402         u32 size = 0;
403         u32 status = 0;
404         int ret;
405
406         ret = tegra_dc_dpaux_read_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
407                 cmd, data_ptr, &size, &status);
408         if (!ret)
409                 dev_err(&dp->dc->ndev->dev,
410                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
411                         cmd, status);
412
413         return ret;
414 }
415
416 static inline int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
417         u8 data)
418 {
419         u32 size = 0;
420         u32 status = 0;
421         int ret;
422
423         ret = tegra_dc_dpaux_write_chunk(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
424                 cmd, &data, &size, &status);
425         if (!ret)
426                 dev_err(&dp->dc->ndev->dev,
427                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
428                         cmd, status);
429         return ret;
430 }
431
432
433 static inline u64 tegra_div64(u64 dividend, u32 divisor)
434 {
435         do_div(dividend, divisor);
436         return dividend;
437 }
438
439
440 static int tegra_dc_init_max_link_cfg(struct tegra_dc_dp_data *dp,
441         struct tegra_dc_dp_link_config *cfg)
442 {
443         u8     dpcd_data;
444         int    ret;
445
446         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LANE_COUNT,
447                         &dpcd_data));
448         cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
449
450         cfg->support_enhanced_framing =
451                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
452                 true : false;
453
454         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_DOWNSPREAD,
455                         &dpcd_data));
456         cfg->downspread = (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
457                 true : false;
458
459         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_MAX_LINK_BANDWIDTH,
460                         &cfg->max_link_bw));
461
462         cfg->bytes_per_pixel = dp->dc->pdata->fb->bits_per_pixel / 8;
463
464         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
465                         &dpcd_data));
466         cfg->alt_scramber_reset_cap =
467                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
468                 true : false;
469         cfg->only_enhanced_framing =
470                 (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
471                 true : false;
472
473         return 0;
474 }
475
476 static bool tegra_dc_dp_lower_config(struct tegra_dc_dp_data *dp,
477         struct tegra_dc_dp_link_config *cfg)
478 {
479         if (cfg->link_bw == DP_LINK_SPEED_G1_62) {
480                 if (cfg->max_link_bw > DP_LINK_SPEED_G1_62)
481                         cfg->link_bw = DP_LINK_SPEED_G2_7;
482                 cfg->lane_count /= 2;
483         } else if (cfg->link_bw == DP_LINK_SPEED_G2_7)
484                 cfg->link_bw = DP_LINK_SPEED_G1_62;
485         else if (cfg->link_bw == DP_LINK_SPEED_G5_4) {
486                 if (cfg->lane_count == 1) {
487                         cfg->link_bw = DP_LINK_SPEED_G2_7;
488                         cfg->lane_count = cfg->max_lane_count;
489                 } else
490                         cfg->lane_count /= 2;
491         } else {
492                 dev_err(&dp->dc->ndev->dev,
493                         "dp: Error link rate %d\n", cfg->link_bw);
494                 return false;
495         }
496         return (cfg->lane_count > 0);
497 }
498
499
500 /* Calcuate if given cfg can meet the mode request. */
501 /* Return true if mode is possible, false otherwise. */
502 static bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
503         const struct tegra_dc_mode *mode,
504         struct tegra_dc_dp_link_config *cfg)
505 {
506         const u32       link_rate = 27 * cfg->link_bw * 1000 * 1000;
507         const u64       f         = 100000;     /* precision factor */
508
509         u32     num_linkclk_line; /* Number of link clocks per line */
510         u64     ratio_f; /* Ratio of incoming to outgoing data rate */
511         u64     frac_f;
512         u64     activesym_f;    /* Activesym per TU */
513         u64     activecount_f;
514         u32     activecount;
515         u32     activepolarity;
516         u32     activefrac;
517         u64     approx_value_f;
518         u64     accumulated_error_f       = 0;
519         u32     lowest_neg_activecount    = 0;
520         u32     lowest_neg_activepolarity = 0;
521         u32     lowest_neg_tusize         = 64;
522         u32     num_symbols_per_line;
523         u64     lowest_neg_activefrac     = 0;
524         u64     lowest_neg_error_f        = 64 * f;
525         u64     watermark_f;
526
527         int     i;
528         bool    neg;
529
530
531         if (!link_rate || !cfg->lane_count || !mode->pclk ||
532                 !cfg->bytes_per_pixel)
533                 return false;
534
535         if (mode->pclk * cfg->bytes_per_pixel >=
536                 8 * link_rate * cfg->lane_count)
537                 return false;
538
539         num_linkclk_line = (u32)tegra_div64(
540                 (u64)link_rate * mode->h_active, mode->pclk);
541
542         ratio_f = (u64)mode->pclk * cfg->bytes_per_pixel * f;
543         ratio_f /= 8;
544         ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
545
546         for (i = 64; i >= 32; --i) {
547                 activesym_f     = ratio_f * i;
548                 activecount_f   = tegra_div64(activesym_f, (u32)f) * f;
549                 frac_f          = activesym_f - activecount_f;
550                 activecount     = (u32)tegra_div64(activecount_f, (u32)f);
551
552                 if (frac_f < (f / 2)) /* fraction < 0.5 */
553                         activepolarity = 0;
554                 else {
555                         activepolarity = 1;
556                         frac_f = f - frac_f;
557                 }
558
559                 if (frac_f != 0) {
560                         frac_f = tegra_div64((f * f),  frac_f); /* 1/fraction */
561                         if (frac_f > (15 * f))
562                                 activefrac = activepolarity ? 1 : 15;
563                         else
564                                 activefrac = activepolarity ?
565                                         (u32)tegra_div64(frac_f, (u32)f) + 1 :
566                                         (u32)tegra_div64(frac_f, (u32)f);
567                 }
568
569                 if (activefrac == 1)
570                         activepolarity = 0;
571
572                 if (activepolarity == 1)
573                         approx_value_f = activefrac ? tegra_div64(
574                                 activecount_f + (activefrac * f - f) * f,
575                                 (activefrac * f)) :
576                                 activecount_f + f;
577                 else
578                         approx_value_f = activefrac ?
579                                 activecount_f + tegra_div64(f, activefrac) :
580                                 activecount_f;
581
582                 if (activesym_f < approx_value_f) {
583                         accumulated_error_f = num_linkclk_line *
584                                 tegra_div64(approx_value_f - activesym_f, i);
585                         neg = true;
586                 } else {
587                         accumulated_error_f = num_linkclk_line *
588                                 tegra_div64(activesym_f - approx_value_f, i);
589                         neg = false;
590                 }
591
592                 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
593                         (accumulated_error_f == 0)) {
594                         lowest_neg_error_f = accumulated_error_f;
595                         lowest_neg_tusize = i;
596                         lowest_neg_activecount = activecount;
597                         lowest_neg_activepolarity = activepolarity;
598                         lowest_neg_activefrac = activefrac;
599
600                         if (accumulated_error_f == 0)
601                                 break;
602                 }
603         }
604
605         if (lowest_neg_activefrac == 0) {
606                 cfg->activepolarity = 0;
607                 cfg->active_count   = lowest_neg_activepolarity ?
608                         lowest_neg_activecount : lowest_neg_activecount - 1;
609                 cfg->tu_size          = lowest_neg_tusize;
610                 cfg->active_frac    = 1;
611         } else {
612                 cfg->activepolarity = lowest_neg_activepolarity;
613                 cfg->active_count   = (u32)lowest_neg_activecount;
614                 cfg->tu_size          = lowest_neg_tusize;
615                 cfg->active_frac    = (u32)lowest_neg_activefrac;
616         }
617
618         dev_dbg(&dp->dc->ndev->dev,
619                 "dp: sor configuration: polarity: %d active count: %d "
620                 "tu size: %d, active frac: %d\n",
621                 cfg->activepolarity, cfg->active_count, cfg->tu_size,
622                 cfg->active_frac);
623
624         watermark_f = ratio_f * cfg->tu_size * tegra_div64(f - ratio_f, f);
625         cfg->watermark = 2*((cfg->bytes_per_pixel) * f / 8) + watermark_f +
626                 (u32)tegra_div64(lowest_neg_error_f, (u32)f) - 1;
627         num_symbols_per_line = (mode->h_active * cfg->bytes_per_pixel) /
628                 (8 * cfg->lane_count);
629         if (cfg->watermark > 30) {
630                 dev_dbg(&dp->dc->ndev->dev,
631                         "dp: sor setting: unable to get a good tusize, "
632                         "force watermark to 30.\n");
633                 cfg->watermark = 30;
634                 return false;
635         } else if (cfg->watermark > num_symbols_per_line) {
636                 dev_dbg(&dp->dc->ndev->dev,
637                         "dp: sor setting: force watermark to the number "
638                         "of symbols in the line.\n");
639                 cfg->watermark = num_symbols_per_line;
640                 return false;
641         }
642
643         /* Refer to dev_disp.ref for more information. */
644         /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
645         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
646         /*                      - 3 * enhanced_framing - Y */
647         /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
648         cfg->hblank_sym = tegra_div64((u64)(mode->h_back_porch +
649                         mode->h_front_porch + mode->h_sync_width - 7)
650                 * link_rate, mode->pclk)
651                 - 3 * cfg->enhanced_framing - (12 / cfg->lane_count);
652
653         if (cfg->hblank_sym < 0)
654                 cfg->hblank_sym = 0;
655
656
657         /* Refer to dev_disp.ref for more information. */
658         /* # symbols/vblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
659         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
660         /*                      - Y - 1; */
661         /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
662         cfg->vblank_sym = tegra_div64((u64)(mode->v_back_porch +
663                         mode->v_front_porch + mode->v_sync_width - 25)
664                 * link_rate, mode->pclk) - (36 / cfg->lane_count) - 4;
665
666         if (cfg->vblank_sym < 0)
667                 cfg->vblank_sym = 0;
668         return true;
669 }
670
671 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
672 {
673         int ret;
674
675         u8 dpcd_data = ena ?
676                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
677                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
678
679         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
680                         dpcd_data));
681
682         /* Also reset the scrambler to 0xfffe */
683         tegra_dc_sor_set_internal_panel(dp->sor, ena);
684         return 0;
685 }
686
687
688 static int tegra_dp_set_link_bandwidth(struct tegra_dc_dp_data *dp, u8 link_bw)
689 {
690         tegra_dc_sor_set_link_bandwidth(dp->sor, link_bw);
691
692         /* Sink side */
693         return tegra_dc_dp_dpcd_write(dp, NV_DPCD_LINK_BANDWIDTH_SET, link_bw);
694 }
695
696 static int tegra_dp_set_lane_count(struct tegra_dc_dp_data *dp,
697         const struct tegra_dc_dp_link_config *cfg)
698 {
699         u8      dpcd_data;
700         int     ret;
701
702         /* check if panel support enhanched_framing */
703         dpcd_data = cfg->lane_count;
704         if (cfg->enhanced_framing)
705                 dpcd_data |= NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T;
706         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_LANE_COUNT_SET,
707                         dpcd_data));
708
709         tegra_dc_sor_set_lane_count(dp->sor, cfg->lane_count);
710
711         /* Also power down lanes that will not be used */
712         return tegra_dc_sor_powerdown_dplanes(dp->sor, cfg->lane_count);
713 }
714
715 static int tegra_dc_dp_set_lane_config(struct tegra_dc_dp_data *dp,
716         u32 lane_count, const u8 *edc, const u8 *c2, u8 training_pattern)
717 {
718         u32 lane;
719         u8  pre_emphasis;
720         u8  drive_current;
721         u8  post_cursor2;
722         u8  temp_edc[5];
723         u8  temp_c2[2];
724         u32 size;
725         u32 status;
726         int ret;
727
728         temp_c2[0] = temp_c2[1] = 0;
729         memset(temp_edc, 0, sizeof(temp_edc));
730         for (lane = 0; lane < lane_count; ++lane) {
731                 if (lane & 1) { /* Lane 1, 3 */
732                         pre_emphasis = (edc[lane/2] &
733                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_MASK) >>
734                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_PE_SHIFT;
735                         drive_current = (edc[lane/2] &
736                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK) >>
737                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_SHIFT;
738                 } else {        /* Lane 0, 2 */
739                         pre_emphasis = (edc[lane/2] &
740                                 NV_DPCD_ADJUST_REQ_LANEX_PE_MASK) >>
741                                 NV_DPCD_ADJUST_REQ_LANEX_PE_SHIFT;
742                         drive_current = (edc[lane/2] &
743                                 NV_DPCD_ADJUST_REQ_LANEX_DC_MASK) >>
744                                 NV_DPCD_ADJUST_REQ_LANEX_DC_SHIFT;
745                 }
746                 post_cursor2 = (*c2 >>
747                         NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_SHIFT(lane)) &
748                         NV_DPCD_ADJUST_REQ_POST_CURSOR2_LANE_MASK;
749
750                 temp_edc[lane+1] = drive_current <<
751                         NV_DPCD_TRAINING_LANEX_SET_DC_SHIFT;
752                 if (drive_current == driveCurrent_Level3)
753                         temp_edc[lane+1] |=
754                                 NV_DPCD_TRAINING_LANEX_SET_DC_MAX_REACHED_T;
755                 temp_edc[lane+1] |=
756                         (pre_emphasis << NV_DPCD_TRAINING_LANEX_SET_PE_SHIFT);
757                 if (pre_emphasis == preEmphasis_Level3)
758                         temp_edc[lane+1] |=
759                                 NV_DPCD_TRAINING_LANEX_SET_PE_MAX_REACHED_T;
760
761                 if (lane & 1) { /* lane 1 and 3 */
762                         temp_c2[lane/2] |= post_cursor2 <<
763                                 NV_DPCD_LANEXPLUS1_SET2_PC2_SHIFT;
764                         if (post_cursor2 == postCursor2_Level3)
765                                 temp_c2[lane/2] |=
766                                      NV_DPCD_LANEXPLUS1_SET2_PC2_MAX_REACHED_T;
767                 } else {        /* lane 0 and 2 */
768                         temp_c2[lane/2] |= post_cursor2 <<
769                                 NV_DPCD_LANEX_SET2_PC2_SHIFT;
770                         if (post_cursor2 == postCursor2_Level3)
771                                 temp_c2[lane/2] |=
772                                         NV_DPCD_LANEX_SET2_PC2_MAX_REACHED_T;
773                 }
774
775                 tegra_dc_sor_set_dp_lanedata(dp->sor, lane_count, post_cursor2,
776                         pre_emphasis, drive_current);
777         }
778
779         usleep(10);
780
781         /* Now program the sink */
782         if (training_pattern != trainingPattern_None) {
783                 tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_PATTERN_SET,
784                         temp_edc);
785                 temp_edc[0] &= NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK;
786                 temp_edc[0] |= (training_pattern &
787                         NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK);
788
789                 size = 4;
790                 ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
791                         NV_DPCD_TRAINING_PATTERN_SET, temp_edc, &size, &status);
792                 if (ret) {
793                         dev_err(&dp->dc->ndev->dev,
794                                 "Failed to set NV_DPCD_TRAINING_PATTERN_SET\n");
795                         return ret;
796                 }
797         } else {                /* No training pattern, only set LANE config */
798                 size = 3;
799                 ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
800                         NV_DPCD_TRAINING_LANE0_SET, temp_edc+1, &size, &status);
801                 if (ret) {
802                         dev_err(&dp->dc->ndev->dev,
803                                 "Failed to set NV_DPCD_TRAINING_LANE0_SET\n");
804                         return ret;
805                 }
806         }
807
808         size = 1;
809         ret = tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
810                 NV_DPCD_TRAINING_LANE0_1_SET2, temp_c2, &size, &status);
811         if (ret)
812                 dev_err(&dp->dc->ndev->dev,
813                         "Failed to set NV_DPCD_TRAINING_LANE0_1_SET2\n");
814         return ret;
815 }
816
817
818 static int tegra_dc_dpcd_read_lane_request(struct tegra_dc_dp_data *dp,
819         u32 lane_count, u8 *edc, u8* c2)
820 {
821         u32 size;
822         int ret;
823         u32 status;
824
825         /* read the new preemphasis & drive current values */
826         size = lane_count/2;
827         ret = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
828                 NV_DPCD_LANE0_1_ADJUST_REQ, edc, &size, &status);
829         if (ret) {
830                 dev_err(&dp->dc->ndev->dev,
831                         "Failed to read NV_DPCD_LANE0_1_ADJUST_REQ\n");
832                 return ret;
833         }
834         return tegra_dc_dp_dpcd_read(dp, NV_DPCD_ADJUST_REQ_POST_CURSOR2, c2);
835 }
836
837 static int tegra_dc_dp_lt_clock_recovery(struct tegra_dc_dp_data *dp,
838         const struct tegra_dc_dp_link_config *cfg)
839 {
840
841         int     ret;
842         u8      edc_data[2] = { 0, 0 };
843         u8      c2_data = 0;
844         u32     lane;
845         u8      temp_edc[4];
846         u8      data;
847         u32     cr_done;
848         bool    sl_changed;
849         u32     sl_max_count;
850         u32     sl_retry_count;
851         u8      mask;
852         u32     retry_count;
853
854
855         /* Set pattern on the source side */
856         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_1,
857                 cfg, false);
858
859         /* Now the sink side */
860         ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
861                 &c2_data, trainingPattern_1);
862         if (ret)
863                 dev_dbg(&dp->dc->ndev->dev,
864                         "Failed to set the sink link for clock recovery\n");
865
866         sl_retry_count = 0;
867         retry_count = 0;
868         do {
869                 usleep(100);
870                 temp_edc[0] = edc_data[0];
871                 temp_edc[1] = edc_data[1];
872
873                 /* read lane registers for all the lanes */
874                 for (lane = 0, cr_done = 0; lane < cfg->lane_count; ++lane) {
875                         ret = tegra_dc_dp_dpcd_read(dp,
876                                 (lane/2) ? NV_DPCD_LANE2_3_STATUS :
877                                 NV_DPCD_LANE0_1_STATUS, &data);
878                         if (ret)
879                                 return ret;
880
881                         mask = (lane & 1) ?
882                                 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES :
883                                 NV_DPCD_STATUS_LANEX_CR_DONE_YES;
884
885                         if (data & mask)
886                                 cr_done++;
887                         else    /* no need to check the rest of the lanes */
888                                 break;
889                 }
890
891                 if (cr_done == cfg->lane_count)
892                         break;  /* Success -- Done with clock recovery */
893
894                 /* Check if the swing-levels changed or reached maxium */
895                 sl_max_count = 0;
896                 sl_changed = false;
897                 for (lane = 0; lane < cfg->lane_count; ++lane) {
898                         mask = (lane & 1) ?
899                                 NV_DPCD_ADJUST_REQ_LANEXPLUS1_DC_MASK :
900                                 NV_DPCD_ADJUST_REQ_LANEX_DC_MASK;
901                         if ((edc_data[lane/2] & mask) !=
902                                 (temp_edc[lane/2] & mask)) {
903                                 sl_changed = true;
904                                 sl_retry_count = 0;
905                                 break;
906                         }
907                         if ((edc_data[lane/2] & mask) == driveCurrent_Level3)
908                                 sl_max_count++;
909                 }
910
911                 if (sl_max_count == cfg->lane_count) {
912                         dev_err(&dp->dc->ndev->dev,
913                                 "Reached MAX_SWING_LEVEL yet CR_LOCK failed\n");
914                         return -EFAULT;
915                 }
916                 if (!sl_changed && (sl_retry_count++ >
917                                 DP_CLOCK_RECOVERY_MAX_TRIES)) {
918                         dev_err(&dp->dc->ndev->dev, "Exceeded max combination\n");
919                         return -EFAULT;
920                 }
921
922                 /* Read the config on the sink side */
923                 ret = tegra_dc_dpcd_read_lane_request(dp, cfg->lane_count,
924                         edc_data, &c2_data);
925
926                 /* Write the data */
927                 ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
928                         &c2_data, trainingPattern_None);
929                 if (ret) {
930                         dev_err(&dp->dc->ndev->dev,
931                                 "Failed to update lane configuration");
932                         return ret;
933                 }
934         } while (++retry_count < DP_CLOCK_RECOVERY_TOT_TRIES);
935
936         if (retry_count == DP_CLOCK_RECOVERY_TOT_TRIES) {
937                 dev_err(&dp->dc->ndev->dev, "Exceeded max retry times\n");
938                 return -EFAULT;
939         }
940         return ret;
941 }
942
943 static int tegra_dc_dp_lt_channel_equalization(struct tegra_dc_dp_data *dp,
944         const struct tegra_dc_dp_link_config *cfg)
945 {
946         int ret;
947         u8  data;
948         u8  edc_data[2] = { 0, 0 };
949         u8  c2_data = 0;
950         u8  updated_status;
951         u32 tries;
952         u8  lane;
953         u32 ce_done;
954         u8  mask;
955
956
957         /* Set pattern on the source side */
958         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_2,
959                 cfg, true);
960
961         /* Now the sink side */
962         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_TRAINING_PATTERN_SET,
963                         &data));
964
965         data &= ~NV_DPCD_TRAINING_PATTERN_SET_TPS_MASK;
966         data |= trainingPattern_2;
967
968         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
969                         data));
970
971         usleep(400);
972
973         for (tries = 0; tries <= DP_CLOCK_RECOVERY_MAX_TRIES; ++tries) {
974                 ret = tegra_dc_dpcd_read_lane_request(dp, cfg->lane_count,
975                         edc_data, &c2_data);
976                 if (ret)
977                         return ret;
978                 /* Write the data */
979                 ret = tegra_dc_dp_set_lane_config(dp, cfg->lane_count, edc_data,
980                         &c2_data, trainingPattern_None);
981                 if (ret) {
982                         dev_err(&dp->dc->ndev->dev,
983                                 "Failed to update lane configuration");
984                         return ret;
985                 }
986
987                 usleep(400);
988
989                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
990                                 NV_DPCD_LANE_ALIGN_STATUS_UPDATED,
991                                 &updated_status));
992
993                 for (lane = 0, ce_done = 0; lane < cfg->lane_count; ++lane) {
994                         CHECK_RET(tegra_dc_dp_dpcd_read(dp,
995                                         (lane/2) ? NV_DPCD_LANE2_3_STATUS :
996                                         NV_DPCD_LANE0_1_STATUS,
997                                         &data));
998
999                         mask = (lane & 1) ?
1000                                 NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
1001                                 NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
1002                                 NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
1003                                 NV_DPCD_STATUS_LANEX_CR_DONE_YES |
1004                                 NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
1005                                 NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
1006
1007                         if (((data & mask) == mask)
1008                                 && (updated_status &
1009                                     NV_DPCD_LANE_ALIGN_STATUS_UPDATED_DONE_YES))
1010                                 ce_done++;
1011                         else
1012                                 /* no need to check the rest of the lanes */
1013                                 break;
1014                 }
1015
1016                 if ((data & NV_DPCD_STATUS_LANEX_CR_DONE_YES) == 0) {
1017                         dev_err(&dp->dc->ndev->dev,
1018                                 "Clock recovery has not been locked\n");
1019                         return -EFAULT;
1020                 }
1021
1022                 if (ce_done == cfg->lane_count) {
1023                         /* All lanes done with training */
1024                         dev_dbg(&dp->dc->ndev->dev,
1025                                 "Channel Equalization passed\n");
1026                         return 0;
1027                 }
1028         }
1029
1030         /* Reaches max tries */
1031         dev_err(&dp->dc->ndev->dev,
1032                 "Channel Equalization exceeded max combinations\n");
1033         return -EFAULT;
1034 }
1035
1036
1037 static int tegra_dc_dp_link_training(struct tegra_dc_dp_data *dp,
1038         const struct tegra_dc_dp_link_config *cfg)
1039 {
1040         int ret = tegra_dc_dp_lt_clock_recovery(dp, cfg);
1041         if (ret)
1042                 dev_dbg(&dp->dc->ndev->dev,
1043                         "DP: failed link training clock recovery with "
1044                         "lane %d bw %d\n", cfg->lane_count, cfg->link_bw);
1045         else {
1046                 ret = tegra_dc_dp_lt_channel_equalization(dp, cfg);
1047
1048                 if (ret)
1049                         dev_dbg(&dp->dc->ndev->dev,
1050                                 "DP: failed link training channel equal with "
1051                                 "lane %d bw %d\n",
1052                                 cfg->lane_count, cfg->link_bw);
1053         }
1054
1055         /* TODO: read back the link status for debugging purpose */
1056         return ret;
1057 }
1058
1059 static bool tegra_dc_dp_link_trained(struct tegra_dc_dp_data *dp,
1060         struct tegra_dc_dp_link_config *cfg)
1061 {
1062         u32 lane;
1063         u8  mask;
1064         u8  data;
1065         int ret;
1066
1067         for (lane = 0; lane < cfg->lane_count; ++lane) {
1068                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, (lane/2) ?
1069                                 NV_DPCD_LANE2_3_STATUS : NV_DPCD_LANE0_1_STATUS,
1070                                 &data));
1071                 mask = (lane & 1) ?
1072                         NV_DPCD_STATUS_LANEXPLUS1_CR_DONE_YES |
1073                         NV_DPCD_STATUS_LANEXPLUS1_CHN_EQ_DONE_YES |
1074                         NV_DPCD_STATUS_LANEXPLUS1_SYMBOL_LOCKED_YES :
1075                         NV_DPCD_STATUS_LANEX_CR_DONE_YES |
1076                         NV_DPCD_STATUS_LANEX_CHN_EQ_DONE_YES |
1077                         NV_DPCD_STATUS_LANEX_SYMBOL_LOCKED_YES;
1078                 if ((data & mask) != mask)
1079                         return false;
1080         }
1081         return true;
1082 }
1083
1084
1085 static int tegra_dc_dp_fast_link_training(struct tegra_dc_dp_data *dp,
1086         struct tegra_dc_dp_link_config *cfg)
1087 {
1088         struct tegra_dc_sor_data *sor = dp->sor;
1089         int ret;
1090
1091         tegra_dc_sor_set_link_bandwidth(sor, cfg->link_bw);
1092         tegra_dc_sor_set_lane_count(sor, cfg->lane_count);
1093
1094         /* Send TP1 */
1095         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_1, cfg,
1096                 false);
1097
1098         usleep(500);
1099         /* enable ASSR */
1100         tegra_dc_dp_set_assr(dp, true);
1101         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_2, cfg,
1102                 true);
1103
1104         usleep(500);
1105         tegra_dc_sor_set_dp_linkctl(sor, true, trainingPattern_Disabled,
1106                 cfg, false);
1107
1108         ret = tegra_dc_dp_link_trained(dp, cfg);
1109         if (!ret) {
1110                 tegra_dc_sor_read_link_config(dp->sor, &cfg->link_bw,
1111                         &cfg->lane_count);
1112         }
1113         return ret;
1114 }
1115
1116 static int tegra_dp_link_config(struct tegra_dc_dp_data *dp,
1117         const struct tegra_dc_dp_link_config *cfg)
1118 {
1119         u8      dpcd_data;
1120         u8      link_bw;
1121         u8      lane_count;
1122         u32     retry;
1123         int     ret;
1124
1125         if (cfg->lane_count == 0) {
1126                 /* TODO: shutdown the link */
1127                 return 0;
1128         }
1129
1130         /* Set power state if it is not in normal level */
1131         CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_SET_POWER, &dpcd_data));
1132         if (dpcd_data == NV_DPCD_SET_POWER_VAL_D3_PWRDWN) {
1133                 dpcd_data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
1134                 retry = 3;      /* DP spec requires 3 retries */
1135                 do {
1136                         ret = tegra_dc_dp_dpcd_write(dp,
1137                                 NV_DPCD_SET_POWER, dpcd_data);
1138                 } while ((--retry > 0) && (ret != 0));
1139                 if (ret) {
1140                         dev_err(&dp->dc->ndev->dev,
1141                                 "dp: Failed to set DP panel power\n");
1142                         return ret;
1143                 }
1144         }
1145
1146         /* Enable ASSR if possible */
1147         if (cfg->alt_scramber_reset_cap)
1148                 CHECK_RET(tegra_dc_dp_set_assr(dp, true));
1149
1150         ret = tegra_dp_set_link_bandwidth(dp, cfg->link_bw);
1151         if (ret) {
1152                 dev_err(&dp->dc->ndev->dev, "dp: Failed to set link bandwidth\n");
1153                 return ret;
1154         }
1155         ret = tegra_dp_set_lane_count(dp, cfg);
1156         if (ret) {
1157                 dev_err(&dp->dc->ndev->dev, "dp: Failed to set lane count\n");
1158                 return ret;
1159         }
1160         tegra_dc_sor_set_dp_linkctl(dp->sor, true, trainingPattern_Disabled,
1161                 cfg, true);
1162
1163         /* Now do the link training */
1164         ret = tegra_dc_dp_link_training(dp, cfg);
1165         if (ret) {
1166                 dev_dbg(&dp->dc->ndev->dev, "dp: link training failed\n");
1167                 return ret;
1168         }
1169
1170         /* Everything goes well, double check the link config */
1171         /* TODO: record edc/c2 data for debugging */
1172         tegra_dc_sor_read_link_config(dp->sor, &link_bw, &lane_count);
1173
1174         if ((cfg->link_bw == link_bw) && (cfg->lane_count == lane_count))
1175                 return 0;
1176         else
1177                 return -EFAULT;
1178 }
1179
1180 static int tegra_dc_dp_explore_link_cfg(struct tegra_dc_dp_data *dp,
1181         struct tegra_dc_dp_link_config *cfg, struct tegra_dc_mode *mode)
1182 {
1183         struct tegra_dc_dp_link_config temp_cfg;
1184
1185         if (!mode->pclk || !mode->h_active || !mode->v_active) {
1186                 dev_err(&dp->dc->ndev->dev,
1187                         "dp: error mode configuration");
1188                 return -EINVAL;
1189         }
1190         if (!cfg->max_link_bw || !cfg->max_lane_count) {
1191                 dev_err(&dp->dc->ndev->dev,
1192                         "dp: error link configuration");
1193                 return -EINVAL;
1194         }
1195
1196         cfg->is_valid = false;
1197         memcpy(cfg, &temp_cfg, sizeof(temp_cfg));
1198
1199         temp_cfg.link_bw    = temp_cfg.max_link_bw;
1200         temp_cfg.lane_count = temp_cfg.max_lane_count;
1201
1202         while (tegra_dc_dp_calc_config(dp, mode, &temp_cfg) &&
1203                 tegra_dp_link_config(dp, &temp_cfg)) {
1204                 /* current link cfg is doable */
1205                 memcpy(&temp_cfg, cfg, sizeof(temp_cfg));
1206                 cfg->is_valid = true;
1207
1208                 /* try to lower the config */
1209                 if (!tegra_dc_dp_lower_config(dp, &temp_cfg))
1210                         break;
1211         }
1212
1213         return cfg->is_valid ? 0 : -EFAULT;
1214 }
1215
1216 static void tegra_dc_dp_lt_worker(struct work_struct *work)
1217 {
1218         struct tegra_dc_dp_data *dp =
1219                 container_of(work, struct tegra_dc_dp_data, lt_work);
1220
1221         tegra_dc_disable(dp->dc);
1222
1223         if (!dp->link_cfg.is_valid ||
1224                 !tegra_dp_link_config(dp, &dp->link_cfg)) {
1225                 /* If current config is not valid or cannot be trained,
1226                    needs to re-explore the possilbe config */
1227                 if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg))
1228                         dev_err(&dp->dc->ndev->dev,
1229                                 "dp: failed to init link configuration\n");
1230                 else if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg,
1231                                 dp->mode))
1232                         dev_err(&dp->dc->ndev->dev,
1233                                 "dp irq: cannot get working config\n");
1234         }
1235
1236         tegra_dc_enable(dp->dc);
1237 }
1238
1239
1240 static irqreturn_t tegra_dc_dp_hpd_irq(int irq, void *ptr)
1241 {
1242         struct tegra_dc         *dc = ptr;
1243         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1244         u8                       data;
1245         u8                       clear_data = 0;
1246
1247         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR,
1248                         &data))
1249                 dev_err(&dc->ndev->dev, "dp: failed to read IRQ_VECTOR\n");
1250
1251         dev_dbg(&dc->ndev->dev,
1252                 "dp irq: Trying to handle HPD with DPCD_IRQ_VECTOR 0x%x\n",
1253                 data);
1254
1255         /* For eDP only answer auto_test_request */
1256         if (data & NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES &&
1257                 dp->link_cfg.is_valid) {
1258                 /* Schedule to do the link training */
1259                 schedule_work(&dp->lt_work);
1260
1261                 /* Now clear auto_test bit */
1262                 clear_data |= NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTO_TEST_YES;
1263         }
1264
1265         if (clear_data)
1266                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_DEVICE_SERVICE_IRQ_VECTOR,
1267                         clear_data);
1268
1269         return IRQ_HANDLED;
1270 }
1271
1272 static int tegra_dc_dp_init(struct tegra_dc *dc)
1273 {
1274         struct tegra_dc_dp_data *dp;
1275         struct resource         *res;
1276         struct resource         *base_res;
1277         void __iomem            *base;
1278         struct clk              *clk;
1279         int                      err;
1280
1281
1282         dp = kzalloc(sizeof(*dp), GFP_KERNEL);
1283         if (!dp)
1284                 return -ENOMEM;
1285
1286         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "dpaux");
1287         if (!res) {
1288                 dev_err(&dc->ndev->dev, "dp: no mem resources for dpaux\n");
1289                 err = -EFAULT;
1290                 goto err_free_dp;
1291         }
1292
1293         base_res = request_mem_region(res->start, resource_size(res),
1294                 dc->ndev->name);
1295         if (!base_res) {
1296                 dev_err(&dc->ndev->dev, "dp: request_mem_region failed\n");
1297                 err = -EFAULT;
1298                 goto err_free_dp;
1299         }
1300
1301         base = ioremap(res->start, resource_size(res));
1302         if (!base) {
1303                 dev_err(&dc->ndev->dev, "dp: registers can't be mapped\n");
1304                 err = -EFAULT;
1305                 goto err_release_resource_reg;
1306         }
1307
1308         clk = clk_get(&dc->ndev->dev, NULL);
1309         if (IS_ERR_OR_NULL(clk)) {
1310                 dev_err(&dc->ndev->dev, "dp: dc clock %s unavailable\n",
1311                         dev_name(&dc->ndev->dev));
1312                 err = -EFAULT;
1313                 goto err_iounmap_reg;
1314         }
1315
1316         /* TODO: confirm interrupt num is acquired from gpio_to_irq,
1317            Also how to differentiate them from HDMI HPD.
1318          */
1319         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_dp_hpd_irq,
1320                         IRQF_DISABLED | IRQF_TRIGGER_RISING |
1321                         IRQF_TRIGGER_FALLING, dev_name(&dc->ndev->dev), dc)) {
1322                 dev_err(&dc->ndev->dev, "dp: request_irq %d failed\n",
1323                         gpio_to_irq(dc->out->hotplug_gpio));
1324                 err = -EBUSY;
1325                 goto err_get_clk;
1326         }
1327
1328
1329         dp->dc           = dc;
1330         dp->aux_base     = base;
1331         dp->aux_base_res = base_res;
1332         dp->clk          = clk;
1333         dp->mode         = &dc->mode;
1334         dp->sor          = tegra_dc_sor_init(dc, &dp->link_cfg);
1335
1336         if (IS_ERR_OR_NULL(dp->sor)) {
1337                 err = PTR_ERR(dp->sor);
1338                 dp->sor = NULL;
1339                 goto err_get_clk;
1340         }
1341
1342         INIT_WORK(&dp->lt_work, tegra_dc_dp_lt_worker);
1343
1344         tegra_dc_set_outdata(dc, dp);
1345
1346         return 0;
1347
1348 err_get_clk:
1349         clk_put(clk);
1350 err_iounmap_reg:
1351         iounmap(base);
1352 err_release_resource_reg:
1353         release_resource(base_res);
1354 err_free_dp:
1355         kfree(dp);
1356
1357         return err;
1358 }
1359
1360 static void tegra_dc_dp_enable(struct tegra_dc *dc)
1361 {
1362         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1363         u8     data;
1364         u32    retry;
1365         int    ret;
1366
1367         tegra_dc_dpaux_enable(dp);
1368
1369         /* Power on panel */
1370         tegra_dc_sor_set_panel_power(dp->sor, true);
1371
1372         /* TODO: power on lanes as well? */
1373
1374         /* Enable backlight -- TODO: need to go through I2C */
1375
1376         msleep(DP_LCDVCC_TO_HPD_DELAY_MS);
1377
1378         /* Write power on to DPCD */
1379         data = NV_DPCD_SET_POWER_VAL_D0_NORMAL;
1380         retry = 0;
1381         do {
1382                 ret = tegra_dc_dp_dpcd_write(dp,
1383                         NV_DPCD_SET_POWER, data);
1384         } while ((retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1385
1386         if (ret) {
1387                 dev_err(&dp->dc->ndev->dev,
1388                         "dp: failed to power on panel (0x%x)\n", ret);
1389                 return;
1390         }
1391
1392         /* Confirm DP is plugging status */
1393 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1394         if (!(tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT) &
1395                         DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
1396                 dev_err(&dp->dc->ndev->dev, "dp: could not detect HPD\n");
1397                 return;
1398         }
1399 #endif
1400
1401         /* Check DP version */
1402         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
1403                 dev_err(&dp->dc->ndev->dev,
1404                         "dp: failed to read the revision number from sink\n");
1405
1406         if (!dp->link_cfg.is_valid ||
1407                 tegra_dc_dp_fast_link_training(dp, &dp->link_cfg)) {
1408                 /* if valid link config is not ready yet, or current
1409                    config cannot be link-trained, try to find the
1410                    new minimal config */
1411                 if (tegra_dc_init_max_link_cfg(dp, &dp->link_cfg)) {
1412                         dev_err(&dp->dc->ndev->dev,
1413                                 "dp: failed to init link configuration\n");
1414                         return;
1415                 }
1416                 if (tegra_dc_dp_explore_link_cfg(dp, &dp->link_cfg, dp->mode) ||
1417                         tegra_dc_dp_link_training(dp, &dp->link_cfg)) {
1418                         dev_err(&dp->dc->ndev->dev,
1419                                 "dp: Current mode is not possible\n");
1420                         return;
1421                 }
1422         }
1423
1424         /* enable SOR by programming the watermark/v/hblank_sym etc */
1425         tegra_dc_sor_enable(dp->sor);
1426 }
1427
1428 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
1429 {
1430         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1431
1432         if (dp->sor)
1433                 tegra_dc_sor_destroy(dp->sor);
1434         clk_put(dp->clk);
1435         iounmap(dp->aux_base);
1436         release_resource(dp->aux_base_res);
1437
1438         kfree(dp);
1439 }
1440
1441 static void tegra_dc_dp_disable(struct tegra_dc *dc)
1442 {
1443         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1444
1445         /* TODO: confirm that dpaux_disable is not needed for eDP */
1446         tegra_dc_dpaux_disable(dp);
1447
1448         /* Power down SOR */
1449         tegra_dc_sor_disable(dp->sor);
1450
1451         /* TODO: Now power down the panel -- through GPIO */
1452         /* Make sure the timing meet the eDP specs */
1453 }
1454
1455
1456
1457 static void tegra_dc_dp_suspend(struct tegra_dc *dc)
1458 {
1459         /* TBD */
1460 }
1461
1462
1463 static void tegra_dc_dp_resume(struct tegra_dc *dc)
1464 {
1465         /* TBD */
1466 }
1467
1468 struct tegra_dc_out_ops tegra_dc_dp_ops = {
1469         .init    = tegra_dc_dp_init,
1470         .destroy = tegra_dc_dp_destroy,
1471         .enable  = tegra_dc_dp_enable,
1472         .disable = tegra_dc_dp_disable,
1473         .suspend = tegra_dc_dp_suspend,
1474         .resume  = tegra_dc_dp_resume,
1475 };