2e986a6a726a787a87fe2d4f949a3399a180d52d
[linux-3.10.git] / drivers / video / tegra / dc / dp.c
1 /*
2  * drivers/video/tegra/dc/dp.c
3  *
4  * Copyright (c) 2011-2016, NVIDIA CORPORATION, All rights reserved.
5  *
6  * This software is licensed under the terms of the GNU General Public
7  * License version 2, as published by the Free Software Foundation, and
8  * may be copied, distributed, and modified under those terms.
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  *
15  */
16
17 #include <linux/err.h>
18 #include <linux/gpio.h>
19 #include <linux/wait.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/seq_file.h>
23 #include <linux/debugfs.h>
24 #include <linux/tegra-soc.h>
25 #include <linux/clk/tegra.h>
26 #include <linux/moduleparam.h>
27 #include <linux/of.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #ifdef CONFIG_SWITCH
31 #include <linux/switch.h>
32 #endif
33
34 #include <mach/dc.h>
35 #include <mach/fb.h>
36
37 #include "dp.h"
38 #include "sor.h"
39 #include "sor_regs.h"
40 #include "dpaux_regs.h"
41 #include "dpaux.h"
42 #include "dc_priv.h"
43 #include "edid.h"
44 #include "dphdcp.h"
45 #include "dp_lt.h"
46
47 #if defined(CONFIG_MODS) && (defined(CONFIG_ARCH_TEGRA_21x_SOC) || \
48         defined(CONFIG_ARCH_TEGRA_18x_SOC))
49 #include <linux/ctype.h>
50 #include <asm/uaccess.h>
51 #endif
52
53 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_ARCH_TEGRA_18x_SOC)
54 #include "hda_dc.h"
55 #endif
56
57 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
58 #include "fake_panel.h"
59 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
60
61 #include <linux/tegra_prod.h>
62
63 #define PROD_NODE       "/host1x/sor1"
64
65 static bool tegra_dp_debug = true;
66 module_param(tegra_dp_debug, bool, 0644);
67 MODULE_PARM_DESC(tegra_dp_debug, "Enable to print all link configs");
68
69 /*
70  * WAR for DPR-120 firmware v1.9[r6] limitation for CTS 400.3.2.*
71  * The analyzer issues IRQ_EVENT while we are still link training.
72  * Not expected but analyzer limitation.
73  * Ongoing link training confuses the analyzer leading to false failure.
74  * The WAR eludes link training during unblank. This keeps the purpose
75  * of CTS intact within analyzer limitation.
76  */
77 static bool no_lt_at_unblank = false;
78 module_param(no_lt_at_unblank, bool, 0644);
79 MODULE_PARM_DESC(no_lt_at_unblank, "DP enabled but link not trained");
80
81 static struct tegra_hpd_ops hpd_ops;
82
83 static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp);
84 static inline void tegra_dp_default_int(struct tegra_dc_dp_data *dp,
85                                         bool enable);
86 static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp);
87
88 static inline u32 tegra_dpaux_readl(struct tegra_dc_dp_data *dp, u32 reg)
89 {
90         return readl(dp->aux_base + reg * 4);
91 }
92
93 static inline void tegra_dpaux_writel(struct tegra_dc_dp_data *dp,
94         u32 reg, u32 val)
95 {
96         writel(val, dp->aux_base + reg * 4);
97 }
98
99 static inline void tegra_dpaux_clk_enable(struct tegra_dc_dp_data *dp)
100 {
101         tegra_disp_clk_prepare_enable(dp->dpaux_clk);
102 }
103
104 static inline void tegra_dpaux_clk_disable(struct tegra_dc_dp_data *dp)
105 {
106         tegra_disp_clk_disable_unprepare(dp->dpaux_clk);
107 }
108
109 static inline void tegra_dp_clk_enable(struct tegra_dc_dp_data *dp)
110 {
111         if (!tegra_is_clk_enabled(dp->parent_clk))
112                 tegra_disp_clk_prepare_enable(dp->parent_clk);
113 }
114
115 static inline void tegra_dp_clk_disable(struct tegra_dc_dp_data *dp)
116 {
117         if (tegra_is_clk_enabled(dp->parent_clk))
118                 tegra_disp_clk_disable_unprepare(dp->parent_clk);
119 }
120
121 static inline void tegra_dpaux_write_field(struct tegra_dc_dp_data *dp,
122                                         u32 reg, u32 mask, u32 val)
123 {
124         u32 reg_val = tegra_dpaux_readl(dp, reg);
125         reg_val = (reg_val & ~mask) | (val & mask);
126         tegra_dpaux_writel(dp, reg, reg_val);
127 }
128
129 static inline void tegra_dp_int_en(struct tegra_dc_dp_data *dp, u32 intr)
130 {
131         u32 val;
132
133         /* clear pending interrupt */
134         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, intr);
135
136         val = tegra_dpaux_readl(dp, DPAUX_INTR_EN_AUX);
137         val |= intr;
138
139         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, val);
140 }
141
142 static inline void tegra_dp_int_dis(struct tegra_dc_dp_data *dp, u32 intr)
143 {
144         u32 val;
145
146         val = tegra_dpaux_readl(dp, DPAUX_INTR_EN_AUX);
147         val &= ~intr;
148
149         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, val);
150 }
151
152 static inline void tegra_dp_enable_irq(u32 irq)
153 {
154         if (tegra_platform_is_fpga())
155                 return;
156
157         enable_irq(irq);
158 }
159
160 static inline void tegra_dp_disable_irq(u32 irq)
161 {
162         if (tegra_platform_is_fpga())
163                 return;
164
165         disable_irq(irq);
166 }
167
168 #define is_hotplug_supported(dp) \
169 ({ \
170         !tegra_platform_is_fpga() && \
171         !tegra_platform_is_linsim() && \
172         tegra_dc_is_ext_dp_panel(dp->dc) && \
173         dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP; \
174 })
175
176 static inline void tegra_dp_pending_hpd(struct tegra_dc_dp_data *dp)
177 {
178         if (!is_hotplug_supported(dp))
179                 return;
180
181         tegra_hpd_set_pending_evt(&dp->hpd_data);
182 }
183
184 static inline unsigned long
185 tegra_dc_dpaux_poll_register(struct tegra_dc_dp_data *dp,
186                                 u32 reg, u32 mask, u32 exp_val,
187                                 u32 poll_interval_us, u32 timeout_ms)
188 {
189         unsigned long   timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
190         u32             reg_val    = 0;
191
192         if (tegra_platform_is_linsim())
193                 return 0;
194
195         do {
196                 usleep_range(poll_interval_us, poll_interval_us << 1);
197                 reg_val = tegra_dpaux_readl(dp, reg);
198         } while (((reg_val & mask) != exp_val) &&
199                 time_after(timeout_jf, jiffies));
200
201         if ((reg_val & mask) == exp_val)
202                 return 0;       /* success */
203         dev_dbg(&dp->dc->ndev->dev,
204                 "dpaux_poll_register 0x%x: timeout\n", reg);
205         return jiffies - timeout_jf + 1;
206 }
207
208 static inline int tegra_dpaux_wait_transaction(struct tegra_dc_dp_data *dp)
209 {
210         int err = 0;
211
212         if (unlikely(tegra_platform_is_fpga())) {
213                 if (tegra_dc_dpaux_poll_register(dp, DPAUX_DP_AUXCTL,
214                                 DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
215                                 DPAUX_DP_AUXCTL_TRANSACTREQ_DONE,
216                                 100, DP_AUX_TIMEOUT_MS) != 0)
217                         err = -EFAULT;
218         }
219
220         if (likely(tegra_platform_is_silicon())) {
221                 INIT_COMPLETION(dp->aux_tx);
222                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_TX_DONE);
223                 if (tegra_dpaux_readl(dp, DPAUX_DP_AUXCTL) &
224                                 DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING) {
225                         if (!wait_for_completion_timeout(&dp->aux_tx,
226                                 msecs_to_jiffies(DP_AUX_TIMEOUT_MS)))
227                                 err = -EBUSY;
228                 }
229                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_TX_DONE);
230         }
231
232         if (err)
233                 dev_err(&dp->dc->ndev->dev, "dp: aux tx timeout\n");
234         return err;
235 }
236
237
238 /*
239  * To config DPAUX Transaction Control
240  * o Inputs
241  *  - dp    : pointer to DP information
242  *  - cmd   : transaction command DPAUX_DP_AUXCTL_CMD_xxx
243  *  - addr  : transaction address (20 bit sink device AUX reg addr space)
244  *  - p_wrdt: pointer to the write data buffer / NULL:no write data
245  *  - size  : 1-16: number of byte to read/write
246  *            0   : address only transaction
247  * o Outputs
248  *  - return: error status; 0:no error / !0:error
249  */
250 static int tegra_dp_aux_tx_config(struct tegra_dc_dp_data *dp,
251                                 u32 cmd, u32 addr, u8 *p_wrdt, u32 size)
252 {
253         int i;
254         u32  *data = (u32 *)p_wrdt;
255
256         if (DP_AUX_MAX_BYTES < size)
257                 goto fail;
258
259         switch (cmd) {
260         case DPAUX_DP_AUXCTL_CMD_I2CWR:
261         case DPAUX_DP_AUXCTL_CMD_I2CRD:
262         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
263         case DPAUX_DP_AUXCTL_CMD_MOTWR:
264         case DPAUX_DP_AUXCTL_CMD_MOTRD:
265         case DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT:
266         case DPAUX_DP_AUXCTL_CMD_AUXWR:
267         case DPAUX_DP_AUXCTL_CMD_AUXRD:
268                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
269                                         DPAUX_DP_AUXCTL_CMD_MASK, cmd);
270                 break;
271         default:
272                 goto fail;
273         };
274         tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
275                                 DPAUX_DP_AUXCTL_CMDLEN_MASK,
276                                 size ? size - 1 : 0);
277         tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
278                         DPAUX_DP_AUXCTL_ADDRESS_ONLY_MASK,
279                         (0 == size) ? DPAUX_DP_AUXCTL_ADDRESS_ONLY_TRUE :
280                                 DPAUX_DP_AUXCTL_ADDRESS_ONLY_FALSE);
281
282         tegra_dpaux_writel(dp, DPAUX_DP_AUXADDR, addr);
283         for (i = 0; size && data && i < (DP_AUX_MAX_BYTES / 4); ++i)
284                 tegra_dpaux_writel(dp, DPAUX_DP_AUXDATA_WRITE_W(i), data[i]);
285
286         return 0;
287 fail:
288         return -EINVAL;
289 }
290
291 int tegra_dc_dpaux_write_chunk_locked(struct tegra_dc_dp_data *dp,
292         u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat)
293 {
294         int err = 0;
295         u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
296         u32 defer_retries       = DP_AUX_DEFER_MAX_TRIES;
297
298         WARN_ON(!mutex_is_locked(&dp->dpaux_lock));
299
300         switch (cmd) {
301         case DPAUX_DP_AUXCTL_CMD_I2CWR:
302         case DPAUX_DP_AUXCTL_CMD_MOTWR:
303         case DPAUX_DP_AUXCTL_CMD_AUXWR:
304                 break;
305         default:
306                 dev_err(&dp->dc->ndev->dev,
307                         "dp: invalid aux write cmd: 0x%x\n", cmd);
308                 return -EINVAL;
309         };
310
311         err = tegra_dp_aux_tx_config(dp, cmd, addr, data, *size);
312         if (err < 0) {
313                 dev_err(&dp->dc->ndev->dev, "dp: incorrect aux tx params\n");
314                 return err;
315         }
316
317         if (tegra_platform_is_silicon()) {
318                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
319                 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
320                         dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
321                         return -EFAULT;
322                 }
323         }
324
325         while (1) {
326                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
327                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
328                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
329                                 DP_DPCP_RETRY_SLEEP_NS << 1);
330
331                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
332                                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
333                                         DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING);
334
335                 if (tegra_dpaux_wait_transaction(dp))
336                         dev_err(&dp->dc->ndev->dev,
337                                 "dp: aux write transaction timeout\n");
338
339                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
340
341                 /* Ignore I2C errors on fpga */
342                 if (tegra_platform_is_fpga())
343                         *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
344
345                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
346                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
347                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
348                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING) ||
349                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_NACK) ||
350                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK)) {
351                         if (timeout_retries-- > 0) {
352                                 dev_info(&dp->dc->ndev->dev,
353                                         "dp: aux write retry (0x%x) -- %d\n",
354                                         *aux_stat, timeout_retries);
355                                 /* clear the error bits */
356                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
357                                         *aux_stat);
358                                 continue;
359                         } else {
360                                 dev_err(&dp->dc->ndev->dev,
361                                         "dp: aux write got error (0x%x)\n",
362                                         *aux_stat);
363                                 return -EFAULT;
364                         }
365                 }
366
367                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
368                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
369                         if (defer_retries-- > 0) {
370                                 dev_info(&dp->dc->ndev->dev,
371                                         "dp: aux write defer (0x%x) -- %d\n",
372                                         *aux_stat, defer_retries);
373                                 /* clear the error bits */
374                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
375                                         *aux_stat);
376                                 continue;
377                         } else {
378                                 dev_err(&dp->dc->ndev->dev,
379                                         "dp: aux write defer exceeds max retries "
380                                         "(0x%x)\n",
381                                         *aux_stat);
382                                 return -EFAULT;
383                         }
384                 }
385
386                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
387                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
388                         (*size)++;
389                         return 0;
390                 } else {
391                         dev_err(&dp->dc->ndev->dev,
392                                 "dp: aux write failed (0x%x)\n", *aux_stat);
393                         return -EFAULT;
394                 }
395         }
396         /* Should never come to here */
397         return -EFAULT;
398 }
399
400 int tegra_dc_dpaux_write(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
401         u8 *data, u32 *size, u32 *aux_stat)
402 {
403         u32     cur_size = 0;
404         u32     finished = 0;
405         int     ret      = 0;
406
407         if (*size == 0) {
408                 dev_err(&dp->dc->ndev->dev,
409                         "dp: aux write size can't be 0\n");
410                 return -EINVAL;
411         }
412
413         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
414                 return ret;
415
416         mutex_lock(&dp->dpaux_lock);
417         do {
418                 cur_size = *size - finished;
419                 if (cur_size > DP_AUX_MAX_BYTES)
420                         cur_size = DP_AUX_MAX_BYTES;
421
422                 ret = tegra_dc_dpaux_write_chunk_locked(dp, cmd, addr,
423                         data, &cur_size, aux_stat);
424
425                 finished += cur_size;
426                 addr += cur_size;
427                 data += cur_size;
428
429                 if (ret)
430                         break;
431         } while (*size > finished);
432         mutex_unlock(&dp->dpaux_lock);
433
434         *size = finished;
435         return ret;
436 }
437
438 int tegra_dc_dpaux_read_chunk_locked(struct tegra_dc_dp_data *dp,
439         u32 cmd, u32 addr, u8 *data, u32 *size, u32 *aux_stat)
440 {
441         int err = 0;
442         u32 timeout_retries = DP_AUX_TIMEOUT_MAX_TRIES;
443         u32 defer_retries       = DP_AUX_DEFER_MAX_TRIES;
444
445         WARN_ON(!mutex_is_locked(&dp->dpaux_lock));
446
447         switch (cmd) {
448         case DPAUX_DP_AUXCTL_CMD_I2CRD:
449         case DPAUX_DP_AUXCTL_CMD_I2CREQWSTAT:
450         case DPAUX_DP_AUXCTL_CMD_MOTREQWSTAT:
451         case DPAUX_DP_AUXCTL_CMD_MOTRD:
452         case DPAUX_DP_AUXCTL_CMD_AUXRD:
453                 break;
454         default:
455                 dev_err(&dp->dc->ndev->dev,
456                         "dp: invalid aux read cmd: 0x%x\n", cmd);
457                 return -EINVAL;
458         };
459
460         err = tegra_dp_aux_tx_config(dp, cmd, addr, NULL, *size);
461         if (err < 0) {
462                 dev_err(&dp->dc->ndev->dev, "dp: incorrect aux tx params\n");
463                 return err;
464         }
465
466         if (tegra_platform_is_silicon()) {
467                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
468                 if (!(*aux_stat & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED)) {
469                         dev_err(&dp->dc->ndev->dev, "dp: HPD is not detected\n");
470                         return -EFAULT;
471                 }
472         }
473
474         while (1) {
475                 if ((timeout_retries != DP_AUX_TIMEOUT_MAX_TRIES) ||
476                     (defer_retries != DP_AUX_DEFER_MAX_TRIES))
477                         usleep_range(DP_DPCP_RETRY_SLEEP_NS,
478                                 DP_DPCP_RETRY_SLEEP_NS << 1);
479
480                 tegra_dpaux_write_field(dp, DPAUX_DP_AUXCTL,
481                                         DPAUX_DP_AUXCTL_TRANSACTREQ_MASK,
482                                         DPAUX_DP_AUXCTL_TRANSACTREQ_PENDING);
483
484                 if (tegra_dpaux_wait_transaction(dp))
485                         dev_err(&dp->dc->ndev->dev,
486                                 "dp: aux read transaction timeout\n");
487
488                 *aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
489
490                 /* Ignore I2C errors on fpga */
491                 if (!tegra_platform_is_silicon())
492                         *aux_stat &= ~DPAUX_DP_AUXSTAT_REPLYTYPE_I2CNACK;
493
494                 if ((*aux_stat & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR_PENDING) ||
495                         (*aux_stat & DPAUX_DP_AUXSTAT_RX_ERROR_PENDING) ||
496                         (*aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) ||
497                         (*aux_stat & DPAUX_DP_AUXSTAT_NO_STOP_ERROR_PENDING)) {
498                         if (timeout_retries-- > 0) {
499                                 dev_info(&dp->dc->ndev->dev,
500                                         "dp: aux read retry (0x%x) -- %d\n",
501                                         *aux_stat, timeout_retries);
502                                 /* clear the error bits */
503                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
504                                         *aux_stat);
505                                 continue; /* retry */
506                         } else {
507                                 dev_err(&dp->dc->ndev->dev,
508                                         "dp: aux read got error (0x%x)\n",
509                                         *aux_stat);
510                                 return -EFAULT;
511                         }
512                 }
513
514                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_I2CDEFER) ||
515                         (*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_DEFER)) {
516                         if (defer_retries-- > 0) {
517                                 dev_info(&dp->dc->ndev->dev,
518                                         "dp: aux read defer (0x%x) -- %d\n",
519                                         *aux_stat, defer_retries);
520                                 /* clear the error bits */
521                                 tegra_dpaux_writel(dp, DPAUX_DP_AUXSTAT,
522                                         *aux_stat);
523                                 continue;
524                         } else {
525                                 dev_err(&dp->dc->ndev->dev,
526                                         "dp: aux read defer exceeds max retries "
527                                         "(0x%x)\n", *aux_stat);
528                                 return -EFAULT;
529                         }
530                 }
531
532                 if ((*aux_stat & DPAUX_DP_AUXSTAT_REPLYTYPE_MASK) ==
533                         DPAUX_DP_AUXSTAT_REPLYTYPE_ACK) {
534                         int i;
535                         u32 temp_data[4];
536
537                         for (i = 0; i < DP_AUX_MAX_BYTES/4; ++i)
538                                 temp_data[i] = tegra_dpaux_readl(dp,
539                                         DPAUX_DP_AUXDATA_READ_W(i));
540
541                         *size = ((*aux_stat) & DPAUX_DP_AUXSTAT_REPLY_M_MASK);
542                         memcpy(data, temp_data, *size);
543
544                         return 0;
545                 } else {
546                         dev_err(&dp->dc->ndev->dev,
547                                 "dp: aux read failed (0x%x\n", *aux_stat);
548                         return -EFAULT;
549                 }
550         }
551         /* Should never come to here */
552         return -EFAULT;
553 }
554
555 int tegra_dc_dpaux_read(struct tegra_dc_dp_data *dp, u32 cmd, u32 addr,
556         u8 *data, u32 *size, u32 *aux_stat)
557 {
558         u32     finished = 0;
559         u32     cur_size;
560         int     ret      = 0;
561
562         if (*size == 0) {
563                 dev_err(&dp->dc->ndev->dev,
564                         "dp: aux read size can't be 0\n");
565                 return -EINVAL;
566         }
567
568         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
569                 return  ret;
570
571         mutex_lock(&dp->dpaux_lock);
572         do {
573                 cur_size = *size - finished;
574                 if (cur_size > DP_AUX_MAX_BYTES)
575                         cur_size = DP_AUX_MAX_BYTES;
576
577                 ret = tegra_dc_dpaux_read_chunk_locked(dp, cmd, addr,
578                         data, &cur_size, aux_stat);
579
580                 if (ret)
581                         break;
582
583                 /* cur_size should be the real size returned */
584                 addr += cur_size;
585                 data += cur_size;
586                 finished += cur_size;
587
588         } while (*size > finished);
589         mutex_unlock(&dp->dpaux_lock);
590
591         *size = finished;
592         return ret;
593 }
594
595 /* TODO: Handle update status scenario and size > 16 bytes*/
596 static int tegra_dc_dp_i2c_write(struct tegra_dc_dp_data *dp, u32 i2c_addr,
597                                 u8 *data, u32 *size, u32 *aux_stat)
598 {
599         int ret = 0;
600
601         if (*size == 0) {
602                 dev_err(&dp->dc->ndev->dev,
603                         "dp: i2c write size can't be 0\n");
604                 return -EINVAL;
605         }
606
607         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
608                 return ret;
609
610         mutex_lock(&dp->dpaux_lock);
611
612         ret = tegra_dc_dpaux_write_chunk_locked(dp,
613                         DPAUX_DP_AUXCTL_CMD_MOTWR,
614                         i2c_addr, data, size, aux_stat);
615
616         mutex_unlock(&dp->dpaux_lock);
617
618         return ret;
619 }
620
621 static int tegra_dc_dp_i2c_read(struct tegra_dc_dp_data *dp, u32 i2c_addr,
622                                 u8 *data, u32 *size, u32 *aux_stat)
623 {
624         u32 finished = 0;
625         u32 cur_size;
626         int ret = 0;
627
628         if (*size == 0) {
629                 dev_err(&dp->dc->ndev->dev,
630                         "dp: i2c read size can't be 0\n");
631                 return -EINVAL;
632         }
633
634         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
635                 return ret;
636
637         mutex_lock(&dp->dpaux_lock);
638
639         do {
640                 cur_size = *size - finished;
641
642                 if (cur_size > DP_AUX_MAX_BYTES)
643                         cur_size = DP_AUX_MAX_BYTES;
644
645                 ret = tegra_dc_dpaux_read_chunk_locked(dp,
646                         DPAUX_DP_AUXCTL_CMD_MOTRD,
647                         i2c_addr, data, &cur_size, aux_stat);
648                 if (ret)
649                         break;
650
651                 data += cur_size;
652                 finished += cur_size;
653         } while (*size > finished);
654
655         cur_size = 0;
656         tegra_dc_dpaux_read_chunk_locked(dp,
657                         DPAUX_DP_AUXCTL_CMD_I2CRD,
658                         i2c_addr, data, &cur_size, aux_stat);
659
660         mutex_unlock(&dp->dpaux_lock);
661
662         *size = finished;
663
664         return ret;
665 }
666
667 int tegra_dc_dp_dpcd_read(struct tegra_dc_dp_data *dp, u32 cmd,
668         u8 *data_ptr)
669 {
670         u32 size = 1;
671         u32 status = 0;
672         int ret = 0;
673
674         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
675                 return ret;
676
677         mutex_lock(&dp->dpaux_lock);
678         ret = tegra_dc_dpaux_read_chunk_locked(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
679                 cmd, data_ptr, &size, &status);
680         mutex_unlock(&dp->dpaux_lock);
681         if (ret)
682                 dev_err(&dp->dc->ndev->dev,
683                         "dp: Failed to read DPCD data. CMD 0x%x, Status 0x%x\n",
684                         cmd, status);
685
686         return ret;
687 }
688
689 static int tegra_dc_dp_i2c_xfer(struct tegra_dc *dc, struct i2c_msg *msgs,
690         int num)
691 {
692         struct i2c_msg *pmsg;
693         int i;
694         u32 aux_stat;
695         int status = 0;
696         u32 len = 0;
697         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
698
699         for (i = 0; i < num; ++i) {
700                 pmsg = &msgs[i];
701
702                 if (!pmsg->flags) {
703                         len = pmsg->len;
704
705                         status = tegra_dc_dp_i2c_write(dp, pmsg->addr,
706                                                 pmsg->buf, &len, &aux_stat);
707                         if (status) {
708                                 dev_err(&dp->dc->ndev->dev,
709                                         "dp: Failed for I2C write"
710                                         " addr:%d, size:%d, stat:0x%x\n",
711                                         pmsg->addr, len, aux_stat);
712                                 return status;
713                         }
714                 } else if (pmsg->flags & I2C_M_RD) {
715                         len = pmsg->len;
716
717                         status = tegra_dc_dp_i2c_read(dp, pmsg->addr,
718                                                 pmsg->buf, &len, &aux_stat);
719                         if (status) {
720                                 dev_err(&dp->dc->ndev->dev,
721                                         "dp: Failed for I2C read"
722                                         " addr:%d, size:%d, stat:0x%x\n",
723                                         pmsg->addr, len, aux_stat);
724                                 return status;
725                         }
726                 } else {
727                         dev_err(&dp->dc->ndev->dev,
728                                 "dp: i2x_xfer: Invalid i2c flag 0x%x\n",
729                                 pmsg->flags);
730                         return -EINVAL;
731                 }
732         }
733
734         return i;
735 }
736
737 static i2c_transfer_func_t tegra_dp_hpd_op_edid_read(void *drv_data)
738 {
739         struct tegra_dc_dp_data *dp = drv_data;
740
741         return (dp->edid_src == EDID_SRC_DT) ?
742                 tegra_dc_edid_blob : tegra_dc_dp_i2c_xfer;
743 }
744
745 int tegra_dc_dp_dpcd_write(struct tegra_dc_dp_data *dp, u32 cmd,
746         u8 data)
747 {
748         u32 size = 1;
749         u32 status = 0;
750         int ret;
751
752         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
753                 return 0;
754
755         mutex_lock(&dp->dpaux_lock);
756         ret = tegra_dc_dpaux_write_chunk_locked(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
757                 cmd, &data, &size, &status);
758         mutex_unlock(&dp->dpaux_lock);
759         if (ret)
760                 dev_err(&dp->dc->ndev->dev,
761                         "dp: Failed to write DPCD data. CMD 0x%x, Status 0x%x\n",
762                         cmd, status);
763         return ret;
764 }
765
766 int tegra_dp_dpcd_write_field(struct tegra_dc_dp_data *dp,
767                                         u32 cmd, u8 mask, u8 data)
768 {
769         u8 dpcd_data;
770         int ret;
771
772         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
773                 return 0;
774
775         might_sleep();
776
777         CHECK_RET(tegra_dc_dp_dpcd_read(dp, cmd, &dpcd_data));
778         dpcd_data &= ~mask;
779         dpcd_data |= data;
780         CHECK_RET(tegra_dc_dp_dpcd_write(dp, cmd, dpcd_data));
781
782         return 0;
783 }
784
785 static inline u64 tegra_div64(u64 dividend, u32 divisor)
786 {
787         do_div(dividend, divisor);
788         return dividend;
789 }
790
791 #ifdef CONFIG_DEBUG_FS
792 static int dbg_dp_show(struct seq_file *s, void *unused)
793 {
794 #define DUMP_REG(a) seq_printf(s, "%-32s  %03x  %08x\n",        \
795                 #a, a, tegra_dpaux_readl(dp, a))
796
797         struct tegra_dc_dp_data *dp = s->private;
798
799         tegra_dc_io_start(dp->dc);
800         tegra_dpaux_clk_enable(dp);
801
802         DUMP_REG(DPAUX_INTR_EN_AUX);
803         DUMP_REG(DPAUX_INTR_AUX);
804         DUMP_REG(DPAUX_DP_AUXADDR);
805         DUMP_REG(DPAUX_DP_AUXCTL);
806         DUMP_REG(DPAUX_DP_AUXSTAT);
807         DUMP_REG(DPAUX_HPD_CONFIG);
808         DUMP_REG(DPAUX_HPD_IRQ_CONFIG);
809         DUMP_REG(DPAUX_DP_AUX_CONFIG);
810         DUMP_REG(DPAUX_HYBRID_PADCTL);
811         DUMP_REG(DPAUX_HYBRID_SPARE);
812
813         tegra_dpaux_clk_disable(dp);
814         tegra_dc_io_end(dp->dc);
815
816         return 0;
817 }
818
819 static int dbg_dp_open(struct inode *inode, struct file *file)
820 {
821         return single_open(file, dbg_dp_show, inode->i_private);
822 }
823
824 static const struct file_operations dbg_fops = {
825         .open           = dbg_dp_open,
826         .read           = seq_read,
827         .llseek         = seq_lseek,
828         .release        = single_release,
829 };
830
831 static int lane_count_show(struct seq_file *s, void *unused)
832 {
833         struct tegra_dc_dp_data *dp = s->private;
834         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
835
836         seq_puts(s, "\n");
837         seq_printf(s,
838                 "\tDP Lane_Count: \t%d\n",
839                 cfg->lane_count);
840         return 0;
841 }
842
843 static ssize_t lane_count_set(struct file *file, const char __user *buf,
844                                                 size_t count, loff_t *off)
845 {
846         struct seq_file *s = file->private_data;
847         struct tegra_dc_dp_data *dp = s->private;
848         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
849         long lane_count = 0;
850         int ret = 0;
851
852         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
853                 return -EINVAL;
854
855         ret = kstrtol_from_user(buf, count, 10, &lane_count);
856         if (ret < 0)
857                 return ret;
858
859         if (cfg->lane_count == lane_count)
860                 return -EINVAL;
861
862         /* disable the dc and output controllers */
863         if (dp->dc->enabled)
864                 tegra_dc_disable(dp->dc);
865
866         dev_info(&dp->dc->ndev->dev, "Setting the lanecount from %d to %ld\n",
867                         cfg->lane_count, lane_count);
868
869         cfg->lane_count = lane_count;
870
871         /* check if needed or not for validity purpose */
872         ret = tegra_dc_dp_calc_config(dp, dp->mode, cfg);
873         if (!ret)
874                 dev_info(&dp->dc->ndev->dev,
875                         "Unable to set lane_count properly\n");
876
877         /* disable the dc and output controllers */
878         if (!dp->dc->enabled)
879                 tegra_dc_enable(dp->dc);
880
881         return count;
882 }
883
884 static int lane_count_open(struct inode *inode, struct file *file)
885 {
886         return single_open(file, lane_count_show, inode->i_private);
887 }
888
889 static const struct file_operations lane_count_fops = {
890         .open           = lane_count_open,
891         .read           = seq_read,
892         .write          = lane_count_set,
893         .llseek         = seq_lseek,
894         .release        = single_release,
895 };
896
897 static int link_speed_show(struct seq_file *s, void *unused)
898 {
899         struct tegra_dc_dp_data *dp = s->private;
900         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
901
902         seq_puts(s, "\n");
903         seq_printf(s,
904                 "\tDP Link Speed: \t%d\n",
905                 cfg->link_bw);
906         return 0;
907 }
908
909 static ssize_t link_speed_set(struct file *file, const char __user *buf,
910                                                 size_t count, loff_t *off)
911 {
912         struct seq_file *s = file->private_data;
913         struct tegra_dc_dp_data *dp = s->private;
914         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
915         long link_speed = 0;
916         int ret = 0;
917
918         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
919                 return -EINVAL;
920
921         ret = kstrtol_from_user(buf, count, 10, &link_speed);
922         if (ret < 0)
923                 return ret;
924
925         if (cfg->link_bw == link_speed)
926                 return -EINVAL;
927
928         /* disable the dc and output controllers */
929         if (dp->dc->enabled)
930                 tegra_dc_disable(dp->dc);
931
932         dev_info(&dp->dc->ndev->dev, "Setting the linkspeed from %d to %ld\n",
933                         cfg->link_bw, link_speed);
934
935         cfg->link_bw = link_speed;
936
937         /* check if needed or not for validity purpose */
938         ret = tegra_dc_dp_calc_config(dp, dp->mode, cfg);
939         if (!ret)
940                 dev_info(&dp->dc->ndev->dev,
941                         "Unable to set linkspeed properly\n");
942
943         /* disable the dc and output controllers */
944         if (!dp->dc->enabled)
945                 tegra_dc_enable(dp->dc);
946
947         return count;
948 }
949
950 static int link_speed_open(struct inode *inode, struct file *file)
951 {
952         return single_open(file, link_speed_show, inode->i_private);
953 }
954
955 static const struct file_operations link_speed_fops = {
956         .open           = link_speed_open,
957         .read           = seq_read,
958         .write          = link_speed_set,
959         .llseek         = seq_lseek,
960         .release        = single_release,
961 };
962
963 static int dbg_hotplug_show(struct seq_file *m, void *unused)
964 {
965         struct tegra_dc_dp_data *dp = m->private;
966         struct tegra_dc *dc = dp->dc;
967
968         if (WARN_ON(!dp || !dc || !dc->out))
969                 return -EINVAL;
970
971         seq_printf(m, "dp hpd state: %d\n", dc->out->hotplug_state);
972         return 0;
973 }
974
975 static int dbg_hotplug_open(struct inode *inode, struct file *file)
976 {
977         return single_open(file, dbg_hotplug_show, inode->i_private);
978 }
979
980 /*
981  * sw control for hpd.
982  * 0 is normal state, hw drives hpd.
983  * -1 is force deassert, sw drives hpd.
984  * 1 is force assert, sw drives hpd.
985  * before releasing to hw, sw must ensure hpd state is normal i.e. 0
986  */
987 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
988         size_t len, loff_t *pos)
989 {
990         struct seq_file *m = file->private_data; /* single_open() initialized */
991         struct tegra_dc_dp_data *dp = m->private;
992         struct tegra_dc *dc = dp->dc;
993         int ret;
994         long new_state;
995
996         if (WARN_ON(!dp || !dc || !dc->out))
997                 return -EINVAL;
998
999         ret = kstrtol_from_user(addr, len, 10, &new_state);
1000         if (ret < 0)
1001                 return ret;
1002
1003         if (dc->out->hotplug_state == TEGRA_HPD_STATE_NORMAL
1004                 && new_state != TEGRA_HPD_STATE_NORMAL
1005                 && tegra_dc_hotplug_supported(dc)) {
1006                 /* SW controlled hotplug. Ignore hpd HW interrupts. */
1007                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_PLUG_EVENT |
1008                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT |
1009                                 DPAUX_INTR_EN_AUX_PLUG_EVENT);
1010         } else if (dc->out->hotplug_state != TEGRA_HPD_STATE_NORMAL
1011                 && new_state == TEGRA_HPD_STATE_NORMAL
1012                 && tegra_dc_hotplug_supported(dc)) {
1013                 /* Enable hpd HW interrupts */
1014                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_PLUG_EVENT |
1015                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT |
1016                                 DPAUX_INTR_EN_AUX_PLUG_EVENT);
1017         }
1018
1019         dc->out->hotplug_state = new_state;
1020
1021         tegra_dp_pending_hpd(dp);
1022
1023         return len;
1024 }
1025
1026 static const struct file_operations dbg_hotplug_fops = {
1027         .open = dbg_hotplug_open,
1028         .read = seq_read,
1029         .write = dbg_hotplug_write,
1030         .llseek = seq_lseek,
1031         .release = single_release,
1032 };
1033
1034 static int bits_per_pixel_show(struct seq_file *s, void *unused)
1035 {
1036         struct tegra_dc_dp_data *dp = s->private;
1037         struct tegra_dc_dp_link_config *cfg = NULL;
1038
1039         if (WARN_ON(!dp || !dp->dc || !dp->dc->out))
1040                 return -EINVAL;
1041         cfg = &dp->link_cfg;
1042
1043         if (WARN_ON(!cfg))
1044                 return -EINVAL;
1045
1046         seq_puts(s, "\n");
1047         seq_printf(s, "DP Bits Per Pixel: %u\n", cfg->bits_per_pixel);
1048         return 0;
1049 }
1050
1051 static ssize_t bits_per_pixel_set(struct file *file, const char __user *buf,
1052                                                 size_t count, loff_t *off)
1053 {
1054         struct seq_file *s = file->private_data;
1055         struct tegra_dc_dp_data *dp = s->private;
1056         struct tegra_dc_dp_link_config *cfg = NULL;
1057         u32 bits_per_pixel = 0, previous_bpp = 0;
1058         int ret = 0;
1059 #ifdef CONFIG_SWITCH
1060         bool audio_support;
1061 #endif
1062
1063         if (WARN_ON(!dp || !dp->dc || !dp->dc->out))
1064                 return -EINVAL;
1065
1066         ret = kstrtouint_from_user(buf, count, 10, &bits_per_pixel);
1067         if (ret < 0)
1068                 return ret;
1069
1070         cfg = &dp->link_cfg;
1071
1072         if (WARN_ON(!cfg))
1073                 return -EINVAL;
1074
1075         if (cfg->bits_per_pixel == bits_per_pixel)
1076                 return count;
1077         previous_bpp = cfg->bits_per_pixel;
1078
1079         /* disable the dc and output controllers */
1080         if (dp->dc->enabled)
1081                 tegra_dc_disable(dp->dc);
1082
1083         if ((bits_per_pixel == 18) || (bits_per_pixel == 24))
1084                 dev_info(&dp->dc->ndev->dev, "Setting the bits per pixel from %u to %u\n",
1085                         cfg->bits_per_pixel, bits_per_pixel);
1086         else {
1087                 dev_info(&dp->dc->ndev->dev, "%ubpp is not supported. Restoring to %ubpp\n",
1088                 bits_per_pixel, cfg->bits_per_pixel);
1089                 bits_per_pixel = previous_bpp;
1090         }
1091
1092         dp->dc->out->depth = bits_per_pixel;
1093         cfg->bits_per_pixel = bits_per_pixel;
1094
1095         ret = tegra_dc_dp_calc_config(dp, dp->mode, cfg);
1096         if (!ret) {
1097                 dev_info(&dp->dc->ndev->dev, "Unable to set %ubpp properly. Restoring to %ubpp\n",
1098                         cfg->bits_per_pixel, previous_bpp);
1099                 dp->dc->out->depth = previous_bpp;
1100                 cfg->bits_per_pixel = previous_bpp;
1101         }
1102
1103         /* enable the dc and output controllers */
1104         if (!dp->dc->enabled)
1105                 tegra_dc_enable(dp->dc);
1106
1107 #ifdef CONFIG_SWITCH
1108         audio_support = tegra_edid_audio_supported(dp->hpd_data.edid);
1109         if (audio_support) {
1110                 switch_set_state(&dp->audio_switch, 0);
1111                 msleep(1);
1112                 pr_info("dp_audio switch 0\n");
1113                 switch_set_state(&dp->audio_switch, 1);
1114                 pr_info("dp_audio switch 1\n");
1115         }
1116 #endif
1117
1118         return count;
1119 }
1120
1121 static int bits_per_pixel_open(struct inode *inode, struct file *file)
1122 {
1123         return single_open(file, bits_per_pixel_show, inode->i_private);
1124 }
1125
1126 static const struct file_operations bits_per_pixel_fops = {
1127         .open           = bits_per_pixel_open,
1128         .read           = seq_read,
1129         .write          = bits_per_pixel_set,
1130         .llseek         = seq_lseek,
1131         .release        = single_release,
1132 };
1133
1134 #if defined(CONFIG_MODS) && (defined(CONFIG_ARCH_TEGRA_21x_SOC) || \
1135         defined(CONFIG_ARCH_TEGRA_18x_SOC))
1136 static u16 dp_i2c_addr;
1137 static u32 dp_i2c_num_bytes;
1138
1139 static int dpaux_i2c_data_show(struct seq_file *s, void *unused)
1140 {
1141         struct tegra_dc_dp_data *dp = s->private;
1142         u32 size = dp_i2c_num_bytes;
1143         u32 i, j, aux_stat;
1144         u8 row_size = 16;
1145         u8 *data;
1146
1147         data = kzalloc(size, GFP_KERNEL);
1148         if (!data)
1149                 return -ENOMEM;
1150
1151         tegra_dc_dp_i2c_read(dp, dp_i2c_addr, data, &size, &aux_stat);
1152         for (i = 0; i < size; i += row_size) {
1153                 for (j = i; j < i + row_size && j < size; j++)
1154                         seq_printf(s, "%02x ", data[j]);
1155                 seq_puts(s, "\n");
1156         }
1157
1158         kfree(data);
1159         return 0;
1160 }
1161
1162 static ssize_t dpaux_i2c_data_set(struct file *file,
1163         const char __user *user_buf, size_t count, loff_t *off)
1164 {
1165         struct seq_file *s = file->private_data;
1166         struct tegra_dc_dp_data *dp = s->private;
1167         u32 i = 0, size = 0;
1168         u32 aux_stat;
1169         u8 *data;
1170         char tmp[3];
1171         char *buf;
1172         int ret = count;
1173
1174         buf = kzalloc(count, GFP_KERNEL);
1175         if (!buf)
1176                 return -ENOMEM;
1177
1178         data = kzalloc(count, GFP_KERNEL);
1179         if (!data) {
1180                 ret = -ENOMEM;
1181                 goto free_mem;
1182         }
1183
1184         if (copy_from_user(buf, user_buf, count)) {
1185                 ret = -EINVAL;
1186                 goto free_mem;
1187         }
1188
1189         /*
1190          * Assumes each line of input is of the form: XX XX XX XX ...,
1191          * where X represents one hex digit. You can have an arbitrary
1192          * amount of whitespace between each XX.
1193          */
1194         while (i + 1 < count) {
1195                 if (isspace(buf[i])) {
1196                         i += 1;
1197                         continue;
1198                 }
1199
1200                 tmp[0] = buf[i]; tmp[1] = buf[i + 1]; tmp[2] = '\0';
1201                 if (kstrtou8(tmp, 16, data + size)) {
1202                         ret = -EINVAL;
1203                         goto free_mem;
1204                 }
1205
1206                 size += 1;
1207                 i += 2;
1208         }
1209
1210         tegra_dc_dp_i2c_write(dp, dp_i2c_addr, data, &size, &aux_stat);
1211
1212 free_mem:
1213         kfree(buf);
1214         kfree(data);
1215
1216         return ret;
1217 }
1218
1219 static int dpaux_i2c_data_open(struct inode *inode, struct file *file)
1220 {
1221         return single_open(file, dpaux_i2c_data_show, inode->i_private);
1222 }
1223
1224 static const struct file_operations dpaux_i2c_data_fops = {
1225         .open           = dpaux_i2c_data_open,
1226         .read           = seq_read,
1227         .write          = dpaux_i2c_data_set,
1228         .llseek         = seq_lseek,
1229         .release        = single_release,
1230 };
1231
1232 static struct dentry *tegra_dpaux_i2c_dir_create(struct tegra_dc_dp_data *dp,
1233         struct dentry *parent)
1234 {
1235         struct dentry *dpaux_i2c_dir;
1236         struct dentry *retval = NULL;
1237
1238         dpaux_i2c_dir = debugfs_create_dir("dpaux_i2c", parent);
1239         if (!dpaux_i2c_dir)
1240                 return retval;
1241         retval = debugfs_create_u16("addr", S_IRUGO | S_IWUGO, dpaux_i2c_dir,
1242                         &dp_i2c_addr);
1243         if (!retval)
1244                 goto free_out;
1245         retval = debugfs_create_u32("num_bytes", S_IRUGO | S_IWUGO,
1246                         dpaux_i2c_dir, &dp_i2c_num_bytes);
1247         if (!retval)
1248                 goto free_out;
1249         retval = debugfs_create_file("data", S_IRUGO, dpaux_i2c_dir, dp,
1250                         &dpaux_i2c_data_fops);
1251         if (!retval)
1252                 goto free_out;
1253
1254         return retval;
1255 free_out:
1256         debugfs_remove_recursive(dpaux_i2c_dir);
1257         return retval;
1258 }
1259 #endif
1260
1261 static struct dentry *dpdir;
1262
1263 static void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
1264 {
1265         struct dentry *retval;
1266
1267         dpdir = debugfs_create_dir("tegra_dp", NULL);
1268         if (!dpdir)
1269                 return;
1270         retval = debugfs_create_file("regs", S_IRUGO, dpdir, dp, &dbg_fops);
1271         if (!retval)
1272                 goto free_out;
1273         retval = debugfs_create_file("lanes", S_IRUGO, dpdir, dp,
1274                 &lane_count_fops);
1275         if (!retval)
1276                 goto free_out;
1277         retval = debugfs_create_file("linkspeed", S_IRUGO, dpdir, dp,
1278                 &link_speed_fops);
1279         if (!retval)
1280                 goto free_out;
1281         retval = debugfs_create_file("bitsperpixel", S_IRUGO, dpdir, dp,
1282                 &bits_per_pixel_fops);
1283         if (!retval)
1284                 goto free_out;
1285         retval = debugfs_create_file("test_settings", S_IRUGO, dpdir, dp,
1286                 &test_settings_fops);
1287         if (!retval)
1288                 goto free_out;
1289
1290         /* hotplug not allowed for eDP */
1291         if (is_hotplug_supported(dp)) {
1292                 retval = debugfs_create_file("hotplug", S_IRUGO, dpdir, dp,
1293                         &dbg_hotplug_fops);
1294                 if (!retval)
1295                         goto free_out;
1296         }
1297
1298 #if defined(CONFIG_MODS) && (defined(CONFIG_ARCH_TEGRA_21x_SOC) || \
1299         defined(CONFIG_ARCH_TEGRA_18x_SOC))
1300         retval = tegra_dpaux_i2c_dir_create(dp, dpdir);
1301         if (!retval)
1302                 goto free_out;
1303 #endif
1304
1305         return;
1306 free_out:
1307         debugfs_remove_recursive(dpdir);
1308         dpdir = NULL;
1309         return;
1310 }
1311 #else
1312 static inline void tegra_dc_dp_debug_create(struct tegra_dc_dp_data *dp)
1313 { }
1314 #endif
1315
1316 static void tegra_dpaux_enable(struct tegra_dc_dp_data *dp)
1317 {
1318         /* do not enable interrupt for now. */
1319         tegra_dpaux_writel(dp, DPAUX_INTR_EN_AUX, 0x0);
1320
1321         /* clear interrupt */
1322         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, 0xffffffff);
1323
1324         tegra_dpaux_writel(dp, DPAUX_HYBRID_PADCTL,
1325                 DPAUX_HYBRID_PADCTL_AUX_DRVZ_OHM_50 |
1326                 DPAUX_HYBRID_PADCTL_AUX_CMH_V0_70 |
1327                 0x18 << DPAUX_HYBRID_PADCTL_AUX_DRVI_SHIFT |
1328                 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE);
1329
1330         tegra_dpaux_pad_power(dp->dc,
1331                 tegra_dc_which_sor(dp->dc) ? TEGRA_DPAUX_INSTANCE_1 :
1332                 TEGRA_DPAUX_INSTANCE_0, true);
1333 }
1334
1335 static int tegra_dp_panel_power_state(struct tegra_dc_dp_data *dp, u8 state)
1336 {
1337         u32 retry = 0;
1338         int ret;
1339
1340         do {
1341                 ret = tegra_dc_dp_dpcd_write(dp, NV_DPCD_SET_POWER, state);
1342         } while ((state != NV_DPCD_SET_POWER_VAL_D3_PWRDWN) &&
1343                 (retry++ < DP_POWER_ON_MAX_TRIES) && ret);
1344
1345         return ret;
1346 }
1347
1348 __maybe_unused
1349 static void tegra_dc_dp_dump_link_cfg(struct tegra_dc_dp_data *dp,
1350         const struct tegra_dc_dp_link_config *cfg)
1351 {
1352         if (!tegra_dp_debug)
1353                 return;
1354
1355         BUG_ON(!cfg);
1356
1357         dev_info(&dp->dc->ndev->dev, "DP config: cfg_name               "
1358                 "cfg_value\n");
1359         dev_info(&dp->dc->ndev->dev, "           Lane Count             %d\n",
1360                 cfg->max_lane_count);
1361         dev_info(&dp->dc->ndev->dev, "           SupportEnhancedFraming %s\n",
1362                 cfg->support_enhanced_framing ? "Y" : "N");
1363         dev_info(&dp->dc->ndev->dev, "           SupportAltScrmbRstFffe %s\n",
1364                 cfg->alt_scramber_reset_cap ? "Y" : "N");
1365         dev_info(&dp->dc->ndev->dev, "           Bandwidth              %d\n",
1366                 cfg->max_link_bw);
1367         dev_info(&dp->dc->ndev->dev, "           bpp                    %d\n",
1368                 cfg->bits_per_pixel);
1369         dev_info(&dp->dc->ndev->dev, "           EnhancedFraming        %s\n",
1370                 cfg->enhanced_framing ? "Y" : "N");
1371         dev_info(&dp->dc->ndev->dev, "           Scramble_enabled       %s\n",
1372                 cfg->scramble_ena ? "Y" : "N");
1373         dev_info(&dp->dc->ndev->dev, "           LinkBW                 %d\n",
1374                 cfg->link_bw);
1375         dev_info(&dp->dc->ndev->dev, "           lane_count             %d\n",
1376                 cfg->lane_count);
1377         dev_info(&dp->dc->ndev->dev, "           activespolarity        %d\n",
1378                 cfg->activepolarity);
1379         dev_info(&dp->dc->ndev->dev, "           active_count           %d\n",
1380                 cfg->active_count);
1381         dev_info(&dp->dc->ndev->dev, "           tu_size                %d\n",
1382                 cfg->tu_size);
1383         dev_info(&dp->dc->ndev->dev, "           active_frac            %d\n",
1384                 cfg->active_frac);
1385         dev_info(&dp->dc->ndev->dev, "           watermark              %d\n",
1386                 cfg->watermark);
1387         dev_info(&dp->dc->ndev->dev, "           hblank_sym             %d\n",
1388                 cfg->hblank_sym);
1389         dev_info(&dp->dc->ndev->dev, "           vblank_sym             %d\n",
1390                 cfg->vblank_sym);
1391 };
1392
1393 /* Calcuate if given cfg can meet the mode request. */
1394 /* Return true if mode is possible, false otherwise. */
1395 bool tegra_dc_dp_calc_config(struct tegra_dc_dp_data *dp,
1396         const struct tegra_dc_mode *mode,
1397         struct tegra_dc_dp_link_config *cfg)
1398 {
1399         const u32       link_rate = 27 * cfg->link_bw * 1000 * 1000;
1400         const u64       f         = 100000;     /* precision factor */
1401
1402         u32     num_linkclk_line; /* Number of link clocks per line */
1403         u64     ratio_f; /* Ratio of incoming to outgoing data rate */
1404         u64     frac_f;
1405         u64     activesym_f;    /* Activesym per TU */
1406         u64     activecount_f;
1407         u32     activecount;
1408         u32     activepolarity;
1409         u64     approx_value_f;
1410         u32     activefrac                = 0;
1411         u64     accumulated_error_f       = 0;
1412         u32     lowest_neg_activecount    = 0;
1413         u32     lowest_neg_activepolarity = 0;
1414         u32     lowest_neg_tusize         = 64;
1415         u32     num_symbols_per_line;
1416         u64     lowest_neg_activefrac     = 0;
1417         u64     lowest_neg_error_f        = 64 * f;
1418         u64     watermark_f;
1419
1420         int     i;
1421         bool    neg;
1422         unsigned long rate;
1423
1424         cfg->is_valid = false;
1425         rate = tegra_dc_pclk_round_rate(dp->sor->dc, dp->sor->dc->mode.pclk);
1426
1427         if (!link_rate || !cfg->lane_count || !rate ||
1428                 !cfg->bits_per_pixel)
1429                 return false;
1430
1431         if ((u64)rate * cfg->bits_per_pixel >=
1432                 (u64)link_rate * 8 * cfg->lane_count) {
1433                 dev_dbg(&dp->dc->ndev->dev,
1434                         "Requested rate calc > link_rate calc\n");
1435                 return false;
1436         }
1437
1438         num_linkclk_line = (u32)tegra_div64(
1439                 (u64)link_rate * mode->h_active, rate);
1440
1441         ratio_f = (u64)rate * cfg->bits_per_pixel * f;
1442         ratio_f /= 8;
1443         ratio_f = tegra_div64(ratio_f, link_rate * cfg->lane_count);
1444
1445         for (i = 64; i >= 32; --i) {
1446                 activesym_f     = ratio_f * i;
1447                 activecount_f   = tegra_div64(activesym_f, (u32)f) * f;
1448                 frac_f          = activesym_f - activecount_f;
1449                 activecount     = (u32)tegra_div64(activecount_f, (u32)f);
1450
1451                 if (frac_f < (f / 2)) /* fraction < 0.5 */
1452                         activepolarity = 0;
1453                 else {
1454                         activepolarity = 1;
1455                         frac_f = f - frac_f;
1456                 }
1457
1458                 if (frac_f != 0) {
1459                         frac_f = tegra_div64((f * f),  frac_f); /* 1/fraction */
1460                         if (frac_f > (15 * f))
1461                                 activefrac = activepolarity ? 1 : 15;
1462                         else
1463                                 activefrac = activepolarity ?
1464                                         (u32)tegra_div64(frac_f, (u32)f) + 1 :
1465                                         (u32)tegra_div64(frac_f, (u32)f);
1466                 }
1467
1468                 if (activefrac == 1)
1469                         activepolarity = 0;
1470
1471                 if (activepolarity == 1)
1472                         approx_value_f = activefrac ? tegra_div64(
1473                                 activecount_f + (activefrac * f - f) * f,
1474                                 (activefrac * f)) :
1475                                 activecount_f + f;
1476                 else
1477                         approx_value_f = activefrac ?
1478                                 activecount_f + tegra_div64(f, activefrac) :
1479                                 activecount_f;
1480
1481                 if (activesym_f < approx_value_f) {
1482                         accumulated_error_f = num_linkclk_line *
1483                                 tegra_div64(approx_value_f - activesym_f, i);
1484                         neg = true;
1485                 } else {
1486                         accumulated_error_f = num_linkclk_line *
1487                                 tegra_div64(activesym_f - approx_value_f, i);
1488                         neg = false;
1489                 }
1490
1491                 if ((neg && (lowest_neg_error_f > accumulated_error_f)) ||
1492                         (accumulated_error_f == 0)) {
1493                         lowest_neg_error_f = accumulated_error_f;
1494                         lowest_neg_tusize = i;
1495                         lowest_neg_activecount = activecount;
1496                         lowest_neg_activepolarity = activepolarity;
1497                         lowest_neg_activefrac = activefrac;
1498
1499                         if (accumulated_error_f == 0)
1500                                 break;
1501                 }
1502         }
1503
1504         if (lowest_neg_activefrac == 0) {
1505                 cfg->activepolarity = 0;
1506                 cfg->active_count   = lowest_neg_activepolarity ?
1507                         lowest_neg_activecount : lowest_neg_activecount - 1;
1508                 cfg->tu_size          = lowest_neg_tusize;
1509                 cfg->active_frac    = 1;
1510         } else {
1511                 cfg->activepolarity = lowest_neg_activepolarity;
1512                 cfg->active_count   = (u32)lowest_neg_activecount;
1513                 cfg->tu_size          = lowest_neg_tusize;
1514                 cfg->active_frac    = (u32)lowest_neg_activefrac;
1515         }
1516
1517         dev_dbg(&dp->dc->ndev->dev,
1518                 "dp: sor configuration: polarity: %d active count: %d "
1519                 "tu size: %d, active frac: %d\n",
1520                 cfg->activepolarity, cfg->active_count, cfg->tu_size,
1521                 cfg->active_frac);
1522
1523         watermark_f = tegra_div64(ratio_f * cfg->tu_size * (f - ratio_f), f);
1524         cfg->watermark = (u32)tegra_div64(watermark_f + lowest_neg_error_f,
1525                 f) + cfg->bits_per_pixel / 4 - 1;
1526         num_symbols_per_line = (mode->h_active * cfg->bits_per_pixel) /
1527                 (8 * cfg->lane_count);
1528         if (cfg->watermark > 30) {
1529                 dev_dbg(&dp->dc->ndev->dev,
1530                         "dp: sor setting: unable to get a good tusize, "
1531                         "force watermark to 30.\n");
1532                 cfg->watermark = 30;
1533                 return false;
1534         } else if (cfg->watermark > num_symbols_per_line) {
1535                 dev_dbg(&dp->dc->ndev->dev,
1536                         "dp: sor setting: force watermark to the number "
1537                         "of symbols in the line.\n");
1538                 cfg->watermark = num_symbols_per_line;
1539                 return false;
1540         }
1541
1542         /* Refer to dev_disp.ref for more information. */
1543         /* # symbols/hblank = ((SetRasterBlankEnd.X + SetRasterSize.Width - */
1544         /*                      SetRasterBlankStart.X - 7) * link_clk / pclk) */
1545         /*                      - 3 * enhanced_framing - Y */
1546         /* where Y = (# lanes == 4) 3 : (# lanes == 2) ? 6 : 12 */
1547         cfg->hblank_sym = (int)tegra_div64((u64)(mode->h_back_porch +
1548                         mode->h_front_porch + mode->h_sync_width - 7)
1549                 * link_rate, rate)
1550                 - 3 * cfg->enhanced_framing - (12 / cfg->lane_count);
1551
1552         if (cfg->hblank_sym < 0)
1553                 cfg->hblank_sym = 0;
1554
1555
1556         /* Refer to dev_disp.ref for more information. */
1557         /* # symbols/vblank = ((SetRasterBlankStart.X - */
1558         /*                      SetRasterBlankEen.X - 25) * link_clk / pclk) */
1559         /*                      - Y - 1; */
1560         /* where Y = (# lanes == 4) 12 : (# lanes == 2) ? 21 : 39 */
1561         cfg->vblank_sym = (int)tegra_div64((u64)(mode->h_active - 25)
1562                 * link_rate, rate) - (36 / cfg->lane_count) - 4;
1563
1564         if (cfg->vblank_sym < 0)
1565                 cfg->vblank_sym = 0;
1566
1567         cfg->is_valid = true;
1568
1569         return true;
1570 }
1571
1572 static int tegra_dp_init_max_link_cfg(struct tegra_dc_dp_data *dp,
1573                                         struct tegra_dc_dp_link_config *cfg)
1574 {
1575         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
1576                 tegra_dc_init_fake_panel_link_cfg(cfg);
1577         else {
1578                 u8 dpcd_data;
1579                 int ret;
1580
1581                 if (dp->sink_cap_valid)
1582                         dpcd_data = dp->sink_cap[NV_DPCD_MAX_LANE_COUNT];
1583                 else
1584                         CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1585                                 NV_DPCD_MAX_LANE_COUNT, &dpcd_data));
1586
1587                 cfg->max_lane_count = dpcd_data & NV_DPCD_MAX_LANE_COUNT_MASK;
1588
1589                 if (cfg->max_lane_count >= 4)
1590                         cfg->max_lane_count = 4;
1591                 else if (cfg->max_lane_count >= 2)
1592                         cfg->max_lane_count = 2;
1593                 else
1594                         cfg->max_lane_count = 1;
1595
1596                 if (dp->pdata && dp->pdata->max_n_lanes &&
1597                         dp->pdata->max_n_lanes < cfg->max_lane_count)
1598                         cfg->max_lane_count = dp->pdata->max_n_lanes;
1599
1600                 cfg->tps3_supported =
1601                         (dpcd_data &
1602                         NV_DPCD_MAX_LANE_COUNT_TPS3_SUPPORTED_YES) ?
1603                         true : false;
1604                 cfg->support_enhanced_framing =
1605                 (dpcd_data & NV_DPCD_MAX_LANE_COUNT_ENHANCED_FRAMING_YES) ?
1606                 true : false;
1607
1608                 if (dp->sink_cap_valid)
1609                         dpcd_data = dp->sink_cap[NV_DPCD_MAX_DOWNSPREAD];
1610                 else
1611                         CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1612                                         NV_DPCD_MAX_DOWNSPREAD, &dpcd_data));
1613                 cfg->downspread =
1614                         (dpcd_data & NV_DPCD_MAX_DOWNSPREAD_VAL_0_5_PCT) ?
1615                         true : false;
1616                 cfg->support_fast_lt = (dpcd_data &
1617                         NV_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LT_T) ?
1618                         true : false;
1619
1620                 CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1621                         NV_DPCD_TRAINING_AUX_RD_INTERVAL, &dpcd_data));
1622                 cfg->aux_rd_interval = dpcd_data;
1623
1624                 if (dp->sink_cap_valid)
1625                         cfg->max_link_bw =
1626                                 dp->sink_cap[NV_DPCD_MAX_LINK_BANDWIDTH];
1627                 else
1628                         CHECK_RET(tegra_dc_dp_dpcd_read(dp,
1629                                 NV_DPCD_MAX_LINK_BANDWIDTH,
1630                                 &cfg->max_link_bw));
1631
1632                 if (cfg->max_link_bw >= SOR_LINK_SPEED_G5_4)
1633                         cfg->max_link_bw = SOR_LINK_SPEED_G5_4;
1634                 else if (cfg->max_link_bw >= SOR_LINK_SPEED_G2_7)
1635                         cfg->max_link_bw = SOR_LINK_SPEED_G2_7;
1636                 else
1637                         cfg->max_link_bw = SOR_LINK_SPEED_G1_62;
1638
1639                 if (dp->pdata && dp->pdata->max_link_bw &&
1640                         dp->pdata->max_link_bw < cfg->max_link_bw)
1641                         cfg->max_link_bw = dp->pdata->max_link_bw;
1642
1643                 CHECK_RET(tegra_dc_dp_dpcd_read(dp, NV_DPCD_EDP_CONFIG_CAP,
1644                         &dpcd_data));
1645                 cfg->alt_scramber_reset_cap =
1646                         (dpcd_data & NV_DPCD_EDP_CONFIG_CAP_ASC_RESET_YES) ?
1647                         true : false;
1648                 cfg->only_enhanced_framing = (dpcd_data &
1649                         NV_DPCD_EDP_CONFIG_CAP_FRAMING_CHANGE_YES) ?
1650                         true : false;
1651                 cfg->edp_cap = (dpcd_data &
1652                         NV_DPCD_EDP_CONFIG_CAP_DISPLAY_CONTROL_CAP_YES) ?
1653                         true : false;
1654         }
1655
1656         cfg->bits_per_pixel = dp->dc->out->depth ? : 24;
1657
1658         cfg->lane_count = cfg->max_lane_count;
1659
1660         cfg->link_bw = cfg->max_link_bw;
1661
1662         cfg->enhanced_framing = cfg->support_enhanced_framing;
1663
1664         tegra_dc_dp_calc_config(dp, dp->mode, cfg);
1665
1666         dp->max_link_cfg = *cfg;
1667         return 0;
1668 }
1669
1670 static int tegra_dc_dp_set_assr(struct tegra_dc_dp_data *dp, bool ena)
1671 {
1672         int ret;
1673
1674         u8 dpcd_data = ena ?
1675                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_ENABLE :
1676                 NV_DPCD_EDP_CONFIG_SET_ASC_RESET_DISABLE;
1677
1678         CHECK_RET(tegra_dc_dp_dpcd_write(dp, NV_DPCD_EDP_CONFIG_SET,
1679                         dpcd_data));
1680
1681         /* Also reset the scrambler to 0xfffe */
1682         tegra_dc_sor_set_internal_panel(dp->sor, ena);
1683         return 0;
1684 }
1685
1686 static int tegra_dp_set_enhanced_framing(struct tegra_dc_dp_data *dp,
1687                                                 bool enable)
1688 {
1689         int ret;
1690
1691         if (enable) {
1692                 tegra_sor_write_field(dp->sor,
1693                         NV_SOR_DP_LINKCTL(dp->sor->portnum),
1694                         NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE,
1695                         NV_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE);
1696
1697                 CHECK_RET(tegra_dp_dpcd_write_field(dp, NV_DPCD_LANE_COUNT_SET,
1698                                 NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T,
1699                                 NV_DPCD_LANE_COUNT_SET_ENHANCEDFRAMING_T));
1700         }
1701
1702         return 0;
1703 }
1704
1705 static void tegra_dp_irq_evt_worker(struct work_struct *work)
1706 {
1707 #define LANE0_1_CR_CE_SL_MASK (0x7 | (0x7 << 4))
1708 #define LANE0_CR_CE_SL_MASK (0x7)
1709 #define INTERLANE_ALIGN_MASK (0x1)
1710 #define DPCD_LINK_SINK_STATUS_REGS 6
1711
1712         struct tegra_dc_dp_data *dp = container_of(to_delayed_work(work),
1713                                         struct tegra_dc_dp_data,
1714                                         irq_evt_dwork);
1715         u32 aux_stat = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
1716         bool link_stable = !!true;
1717         u8 dpcd_200h_205h[DPCD_LINK_SINK_STATUS_REGS] = {0, 0, 0, 0, 0, 0};
1718         u32 n_lanes = dp->lt_data.n_lanes;
1719
1720         tegra_dc_io_start(dp->dc);
1721
1722         if (aux_stat & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR_PENDING) {
1723                 int cnt;
1724
1725                 /*
1726                  * HW failed to automatically read DPCD
1727                  * offsets 0x200-0x205. Initiate SW transaction.
1728                  */
1729                 for (cnt = 0; cnt < DPCD_LINK_SINK_STATUS_REGS; cnt++) {
1730                         tegra_dc_dp_dpcd_read(dp, NV_DPCD_SINK_COUNT + cnt,
1731                                                 &dpcd_200h_205h[cnt]);
1732                 }
1733         } else  {
1734                 u32 aux_sinkstat_lo = tegra_dpaux_readl(dp,
1735                                         DPAUX_DP_AUX_SINKSTATLO);
1736                 u32 aux_sinkstat_hi = tegra_dpaux_readl(dp,
1737                                         DPAUX_DP_AUX_SINKSTATHI);
1738
1739                 dpcd_200h_205h[0] = aux_sinkstat_lo & 0xff;
1740                 dpcd_200h_205h[1] = (aux_sinkstat_lo >> 8) & 0xff;
1741                 dpcd_200h_205h[2] = (aux_sinkstat_lo >> 16) & 0xff;
1742                 dpcd_200h_205h[3] = (aux_sinkstat_lo >> 24) & 0xff;
1743                 dpcd_200h_205h[4] = aux_sinkstat_hi & 0xff;
1744                 dpcd_200h_205h[5] = (aux_sinkstat_hi >> 8) & 0xff;
1745         }
1746
1747         switch (n_lanes) {
1748         case 4:
1749                 link_stable &= !!((dpcd_200h_205h[3] &
1750                                 LANE0_1_CR_CE_SL_MASK) ==
1751                                 LANE0_1_CR_CE_SL_MASK);
1752                 /* fall through */
1753         case 2:
1754                 link_stable &= !!((dpcd_200h_205h[2] &
1755                                 LANE0_1_CR_CE_SL_MASK) ==
1756                                 LANE0_1_CR_CE_SL_MASK);
1757                 /* fall through */
1758         case 1:
1759                 link_stable &= !!((dpcd_200h_205h[2] &
1760                                 LANE0_CR_CE_SL_MASK) ==
1761                                 LANE0_CR_CE_SL_MASK);
1762                 /* fall through */
1763         default:
1764                 link_stable &= !!(dpcd_200h_205h[4] &
1765                                 INTERLANE_ALIGN_MASK);
1766         }
1767
1768         if (!link_stable)
1769                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
1770         else
1771                 dev_info(&dp->dc->ndev->dev,
1772                         "dp: link stable, ignore irq event\n");
1773
1774         tegra_dc_io_end(dp->dc);
1775
1776 #undef LANE0_1_CR_CE_SL_MASK
1777 #undef LANE0_CR_CE_SL_MASK
1778 #undef INTERLANE_ALIGN_MASK
1779 #undef DPCD_LINK_SINK_STATUS_REGS
1780
1781 }
1782
1783 static irqreturn_t tegra_dp_irq(int irq, void *ptr)
1784 {
1785         struct tegra_dc_dp_data *dp = ptr;
1786         struct tegra_dc *dc = dp->dc;
1787         u32 status;
1788
1789         if (tegra_platform_is_fpga())
1790                 return IRQ_NONE;
1791
1792         if (dp->suspended) {
1793                 dev_info(&dc->ndev->dev,
1794                         "dp: irq received while suspended, ignoring\n");
1795                 return IRQ_HANDLED;
1796         }
1797
1798         tegra_dc_io_start(dc);
1799
1800         /* clear pending bits */
1801         status = tegra_dpaux_readl(dp, DPAUX_INTR_AUX);
1802         tegra_dpaux_writel(dp, DPAUX_INTR_AUX, status);
1803
1804         tegra_dc_io_end(dc);
1805
1806         if (status & (DPAUX_INTR_AUX_PLUG_EVENT_PENDING |
1807                 DPAUX_INTR_AUX_UNPLUG_EVENT_PENDING)) {
1808                 if (status & DPAUX_INTR_AUX_PLUG_EVENT_PENDING) {
1809                         dev_info(&dp->dc->ndev->dev,
1810                                 "dp: plug event received\n");
1811                         complete_all(&dp->hpd_plug);
1812                 } else {
1813                         dev_info(&dp->dc->ndev->dev,
1814                                 "dp: unplug event received\n");
1815                         INIT_COMPLETION(dp->hpd_plug);
1816                 }
1817                 tegra_dp_pending_hpd(dp);
1818         } else if (status & DPAUX_INTR_AUX_IRQ_EVENT_PENDING) {
1819                 dev_info(&dp->dc->ndev->dev, "dp: irq event received%s\n",
1820                         dp->enabled ? "" : ", ignoring");
1821                 if (dp->enabled) {
1822                         cancel_delayed_work(&dp->irq_evt_dwork);
1823                         schedule_delayed_work(&dp->irq_evt_dwork,
1824                                                 msecs_to_jiffies(
1825                                                 HPD_IRQ_EVENT_TIMEOUT_MS));
1826                 }
1827         }
1828
1829         if (status & DPAUX_INTR_AUX_TX_DONE_PENDING)
1830                 complete_all(&dp->aux_tx);
1831
1832         return IRQ_HANDLED;
1833 }
1834
1835 static void _tegra_dpaux_init(struct tegra_dc_dp_data *dp)
1836 {
1837         if (dp->sor->safe_clk)
1838                 tegra_sor_safe_clk_enable(dp->sor);
1839         tegra_dpaux_clk_enable(dp);
1840
1841         tegra_dc_io_start(dp->dc);
1842
1843         tegra_dp_reset(dp);
1844
1845         tegra_dpaux_enable(dp);
1846
1847         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
1848                 tegra_dp_hpd_config(dp);
1849                 tegra_dp_default_int(dp, true);
1850         }
1851
1852         tegra_dc_io_end(dp->dc);
1853 }
1854
1855 static void tegra_dpaux_init(struct tegra_dc_dp_data *dp)
1856 {
1857         BUG_ON(!dp->dc || !dp);
1858
1859         tegra_set_dpaux_addr(dp->aux_base, tegra_dc_which_sor(dp->dc));
1860
1861         _tegra_dpaux_init(dp);
1862
1863         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
1864                 tegra_dp_enable_irq(dp->irq);
1865 }
1866
1867 static int tegra_dc_dp_hotplug_init(struct tegra_dc *dc)
1868 {
1869         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
1870
1871         /* SOR partition must be awake for dpaux */
1872         tegra_dc_unpowergate_locked(dc);
1873
1874         /*
1875          * dp interrupts are received by dpaux.
1876          * Initialize dpaux to receive hotplug events.
1877          */
1878         tegra_dpaux_init(dp);
1879
1880         return 0;
1881 }
1882
1883 static int tegra_dp_prods_init(struct tegra_dc_dp_data *dp)
1884 {
1885         struct device_node *np_prod = of_find_node_by_path(PROD_NODE);
1886
1887         if (!np_prod) {
1888                 dev_warn(&dp->dc->ndev->dev,
1889                         "dp: find prod node failed\n");
1890                 return -EINVAL;
1891         }
1892
1893         dp->prod_list =
1894                 tegra_prod_init((const struct device_node *)np_prod);
1895         if (IS_ERR(dp->prod_list)) {
1896                 dev_warn(&dp->dc->ndev->dev,
1897                         "dp: prod list init failed with error %ld\n",
1898                         PTR_ERR(dp->prod_list));
1899                 of_node_put(np_prod);
1900                 return -EINVAL;
1901         }
1902
1903         of_node_put(np_prod);
1904         return 0;
1905 }
1906
1907 static int tegra_dc_dp_init(struct tegra_dc *dc)
1908 {
1909         struct tegra_dc_dp_data *dp;
1910         struct resource *res;
1911         struct resource *base_res;
1912         struct resource of_dp_res;
1913         void __iomem *base;
1914         struct clk *clk;
1915         struct clk *parent_clk;
1916         int err;
1917         u32 irq;
1918         struct device_node *np = dc->ndev->dev.of_node;
1919         int dp_num = tegra_dc_which_sor(dc);
1920         struct device_node *np_dp =
1921                 dp_num ? of_find_node_by_path(DPAUX1_NODE)
1922                 : of_find_node_by_path(DPAUX_NODE);
1923         struct device_node *np_panel = NULL;
1924
1925         dp = devm_kzalloc(&dc->ndev->dev, sizeof(*dp), GFP_KERNEL);
1926         if (!dp) {
1927                 of_node_put(np_dp);
1928                 return -ENOMEM;
1929         }
1930
1931         dp->edid_src = EDID_SRC_PANEL;
1932         if (np) {
1933                 if (np_dp && (of_device_is_available(np_dp) ||
1934                         (dc->out->type == TEGRA_DC_OUT_FAKE_DP))) {
1935                         irq = of_irq_to_resource(np_dp, 0, NULL);
1936                         if (!irq) {
1937                                 err = -ENOENT;
1938                                 goto err_free_dp;
1939                         }
1940                         of_address_to_resource(np_dp, 0, &of_dp_res);
1941                         res = &of_dp_res;
1942                         np_panel = tegra_get_panel_node_out_type_check(dc,
1943                                 TEGRA_DC_OUT_DP);
1944                         if (np_panel && of_device_is_available(np_panel)) {
1945                                 if (of_property_read_bool(np_panel,
1946                                         "nvidia,edid"))
1947                                         dp->edid_src = EDID_SRC_DT;
1948                         }
1949                 } else {
1950                         err = -EINVAL;
1951                         goto err_free_dp;
1952                 }
1953         } else {
1954                 irq = platform_get_irq_byname(dc->ndev, "irq_dp");
1955                 if (irq <= 0) {
1956                         dev_err(&dc->ndev->dev, "dp: no irq\n");
1957                         err = -ENOENT;
1958                         goto err_free_dp;
1959                 }
1960                 res = platform_get_resource_byname(dc->ndev,
1961                         IORESOURCE_MEM, "dpaux");
1962         }
1963         if (!res) {
1964                 dev_err(&dc->ndev->dev, "dp: no mem resources for dpaux\n");
1965                 err = -EFAULT;
1966                 goto err_free_dp;
1967         }
1968
1969         base_res = devm_request_mem_region(&dc->ndev->dev,
1970                 res->start, resource_size(res),
1971                 dc->ndev->name);
1972         if (!base_res) {
1973                 dev_err(&dc->ndev->dev, "dp: request_mem_region failed\n");
1974                 err = -EFAULT;
1975                 goto err_free_dp;
1976         }
1977
1978         base = devm_ioremap(&dc->ndev->dev, res->start, resource_size(res));
1979         if (!base) {
1980                 dev_err(&dc->ndev->dev, "dp: registers can't be mapped\n");
1981                 err = -EFAULT;
1982                 goto err_release_resource_reg;
1983         }
1984
1985
1986 #ifdef CONFIG_TEGRA_NVDISPLAY
1987         clk = tegra_disp_of_clk_get_by_name(np_dp,
1988                         dc->ndev->id ? "dpaux1" : "dpaux");
1989 #else
1990         clk = clk_get_sys(dp_num ? "dpaux1" : "dpaux", NULL);
1991 #endif
1992         if (IS_ERR_OR_NULL(clk)) {
1993                 dev_err(&dc->ndev->dev, "dp: dc clock %s.edp unavailable\n",
1994                         dev_name(&dc->ndev->dev));
1995                 err = -EFAULT;
1996                 goto err_iounmap_reg;
1997         }
1998
1999 #ifdef CONFIG_TEGRA_NVDISPLAY
2000         parent_clk = tegra_disp_of_clk_get_by_name(np_dp, "plldp");
2001 #else
2002         parent_clk = tegra_get_clock_by_name("pll_dp");
2003 #endif
2004         if (IS_ERR_OR_NULL(parent_clk)) {
2005                 dev_err(&dc->ndev->dev, "dp: clock pll_dp unavailable\n");
2006                 err = -EFAULT;
2007                 goto err_iounmap_reg;
2008         }
2009
2010         if (!tegra_platform_is_fpga()) {
2011                 if (request_threaded_irq(irq, NULL, tegra_dp_irq,
2012                                         IRQF_ONESHOT, "tegra_dp", dp)) {
2013                         dev_err(&dc->ndev->dev,
2014                                 "dp: request_irq %u failed\n", irq);
2015                         err = -EBUSY;
2016                         goto err_get_clk;
2017                 }
2018         }
2019
2020         if (dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2021                 tegra_dp_disable_irq(irq);
2022
2023         dp->dc = dc;
2024         dp->aux_base = base;
2025         dp->res = res;
2026         dp->aux_base_res = base_res;
2027         dp->dpaux_clk = clk;
2028         dp->parent_clk = parent_clk;
2029         dp->mode = &dc->mode;
2030         dp->sor = tegra_dc_sor_init(dc, &dp->link_cfg);
2031         dp->irq = irq;
2032         dp->pdata = dc->pdata->default_out->dp_out;
2033         dp->suspended = false;
2034
2035         if (IS_ERR_OR_NULL(dp->sor)) {
2036                 err = PTR_ERR(dp->sor);
2037                 dp->sor = NULL;
2038                 goto err_get_clk;
2039         }
2040
2041 #ifdef CONFIG_TEGRA_DPHDCP
2042         dp->dphdcp = tegra_dphdcp_create(dp, dc->ndev->id,
2043                         dc->out->ddc_bus);
2044         if (IS_ERR_OR_NULL(dp->dphdcp)) {
2045                 err = PTR_ERR(dp->dphdcp);
2046                 goto err_free_dp;
2047         }
2048         /* create a /d entry to change the max retries */
2049         tegra_dphdcp_debugfs_init(dp->dphdcp);
2050 #endif
2051
2052         tegra_dp_prods_init(dp);
2053
2054         init_completion(&dp->aux_tx);
2055         init_completion(&dp->hpd_plug);
2056
2057         mutex_init(&dp->dpaux_lock);
2058
2059         tegra_dc_set_outdata(dc, dp);
2060
2061         /*
2062          * We don't really need hpd driver for eDP.
2063          * Nevertheless, go ahead and init hpd driver.
2064          * eDP uses some of its fields to interact with panel.
2065          */
2066         tegra_hpd_init(&dp->hpd_data, dc, dp, &hpd_ops);
2067
2068         tegra_dp_lt_init(&dp->lt_data, dp);
2069
2070         INIT_DELAYED_WORK(&dp->irq_evt_dwork, tegra_dp_irq_evt_worker);
2071
2072 #ifdef CONFIG_DEBUG_FS
2073         dp->test_settings = default_dp_test_settings;
2074 #endif
2075
2076 #ifdef CONFIG_SWITCH
2077         dp->audio_switch.name = "dp_audio";
2078         err = switch_dev_register(&dp->audio_switch);
2079         BUG_ON(err);
2080 #endif
2081
2082         tegra_dc_dp_debug_create(dp);
2083         of_node_put(np_dp);
2084
2085         return 0;
2086
2087 err_get_clk:
2088 #ifndef CONFIG_TEGRA_NVDISPLAY
2089         clk_put(clk);
2090 #endif
2091 err_iounmap_reg:
2092         devm_iounmap(&dc->ndev->dev, base);
2093 err_release_resource_reg:
2094         devm_release_mem_region(&dc->ndev->dev,
2095                 res->start,
2096                 resource_size(res));
2097
2098         if (!np_dp || !of_device_is_available(np_dp))
2099                 release_resource(res);
2100 err_free_dp:
2101         devm_kfree(&dc->ndev->dev, dp);
2102         of_node_put(np_dp);
2103
2104         return err;
2105 }
2106
2107 static void tegra_dp_hpd_config(struct tegra_dc_dp_data *dp)
2108 {
2109 #define TEGRA_DP_HPD_UNPLUG_MIN_US      2000
2110 #define TEGRA_DP_HPD_PLUG_MIN_US        250
2111 #define TEGRA_DP_HPD_IRQ_MIN_US         250
2112
2113         u32 val;
2114
2115         val = TEGRA_DP_HPD_PLUG_MIN_US |
2116                 (TEGRA_DP_HPD_UNPLUG_MIN_US <<
2117                 DPAUX_HPD_CONFIG_UNPLUG_MIN_TIME_SHIFT);
2118         tegra_dpaux_writel(dp, DPAUX_HPD_CONFIG, val);
2119
2120         tegra_dpaux_writel(dp, DPAUX_HPD_IRQ_CONFIG, TEGRA_DP_HPD_IRQ_MIN_US);
2121
2122 #undef TEGRA_DP_HPD_IRQ_MIN_US
2123 #undef TEGRA_DP_HPD_PLUG_MIN_US
2124 #undef TEGRA_DP_HPD_UNPLUG_MIN_US
2125 }
2126
2127 static void tegra_dp_dpcd_init(struct tegra_dc_dp_data *dp)
2128 {
2129         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
2130         u32 size_ieee_oui = 3, auxstat;
2131         u8 data_ieee_oui_be[3] = {(NV_IEEE_OUI >> 16) & 0xff,
2132                 (NV_IEEE_OUI >> 8) & 0xff,
2133                 NV_IEEE_OUI & 0xff};
2134
2135         /* Check DP version */
2136         if (tegra_dc_dp_dpcd_read(dp, NV_DPCD_REV, &dp->revision))
2137                 dev_err(&dp->dc->ndev->dev,
2138                         "dp: failed to read the revision number from sink\n");
2139
2140         if (tegra_dp_init_max_link_cfg(dp, cfg))
2141                 dev_err(&dp->dc->ndev->dev,
2142                         "dp: failed to init link configuration\n");
2143
2144         tegra_dc_dpaux_write(dp, DPAUX_DP_AUXCTL_CMD_AUXWR,
2145                 NV_DPCD_SOURCE_IEEE_OUI, data_ieee_oui_be, &size_ieee_oui,
2146                 &auxstat);
2147 }
2148
2149 void tegra_dp_tpg(struct tegra_dc_dp_data *dp, u32 tp, u32 n_lanes)
2150 {
2151         if (tp == TRAINING_PATTERN_DISABLE)
2152                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
2153                         (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_F));
2154         else
2155                 tegra_dc_dp_dpcd_write(dp, NV_DPCD_TRAINING_PATTERN_SET,
2156                         (tp | NV_DPCD_TRAINING_PATTERN_SET_SC_DISABLED_T));
2157
2158         tegra_sor_tpg(dp->sor, tp, n_lanes);
2159 }
2160
2161 static void tegra_dp_read_sink_cap(struct tegra_dc_dp_data *dp)
2162 {
2163         struct tegra_dc *dc = dp->dc;
2164         u32 sink_cap_rd_size = DP_DPCD_SINK_CAP_SIZE;
2165         u32 aux_stat = 0;
2166         u8 start_offset = 0;
2167         int err;
2168
2169         tegra_dc_io_start(dc);
2170
2171         dp->sink_cap_valid = false;
2172
2173         err = tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD,
2174                                 start_offset, dp->sink_cap, &sink_cap_rd_size,
2175                                 &aux_stat);
2176         if (!err)
2177                 dp->sink_cap_valid = true;
2178
2179         tegra_dc_io_end(dc);
2180 }
2181
2182 static void tegra_dp_hpd_op_edid_ready(void *drv_data)
2183 {
2184         struct tegra_dc_dp_data *dp = drv_data;
2185         struct tegra_dc *dc = dp->dc;
2186
2187         /* in mm */
2188         dc->out->h_size = dc->out->h_size ? : dp->hpd_data.mon_spec.max_x * 10;
2189         dc->out->v_size = dc->out->v_size ? : dp->hpd_data.mon_spec.max_y * 10;
2190
2191         /*
2192          * EDID specifies either the acutal screen sizes or
2193          * the aspect ratios. The panel file can choose to
2194          * trust the value as the actual sizes by leaving
2195          * width/height to 0s
2196          */
2197         dc->out->width = dc->out->width ? : dc->out->h_size;
2198         dc->out->height = dc->out->height ? : dc->out->v_size;
2199
2200         tegra_dp_read_sink_cap(dp);
2201
2202         tegra_dc_io_start(dc);
2203         tegra_dc_dp_dpcd_read(dp, NV_DPCD_SINK_COUNT,
2204                                 &dp->sink_cnt_cp_ready);
2205         tegra_dc_io_end(dc);
2206 }
2207
2208 static void tegra_dp_hpd_op_edid_recheck(void *drv_data)
2209 {
2210         struct tegra_dc_dp_data *dp = drv_data;
2211
2212         /*
2213          * Hpd dropped but soon came back.
2214          * Panel might have gone out of sync.
2215          * Initiate LT if hpd driver found no
2216          * change in edid and DP controller is enabled.
2217          * Otherwise, next unblank would anyways
2218          * initiate LT.
2219          */
2220         if (tegra_hpd_get_state(&dp->hpd_data) ==
2221                 STATE_DONE_ENABLED && dp->enabled)
2222                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
2223 }
2224
2225 static inline void tegra_dp_reset(struct tegra_dc_dp_data *dp)
2226 {
2227         if (tegra_platform_is_linsim())
2228                 return;
2229         tegra_periph_reset_assert(dp->dpaux_clk);
2230         mdelay(2);
2231         tegra_periph_reset_deassert(dp->dpaux_clk);
2232         mdelay(1);
2233 }
2234
2235 static inline void tegra_dp_default_int(struct tegra_dc_dp_data *dp,
2236                                         bool enable)
2237 {
2238         if (dp->dc->out->type == TEGRA_DC_OUT_FAKE_DP)
2239                 return;
2240
2241         if (enable)
2242                 tegra_dp_int_en(dp, DPAUX_INTR_EN_AUX_IRQ_EVENT |
2243                                 DPAUX_INTR_EN_AUX_PLUG_EVENT |
2244                                 DPAUX_INTR_EN_AUX_UNPLUG_EVENT);
2245         else
2246                 tegra_dp_int_dis(dp, DPAUX_INTR_EN_AUX_IRQ_EVENT);
2247 }
2248
2249 static int tegra_edp_edid_read(struct tegra_dc_dp_data *dp)
2250 {
2251         struct tegra_hpd_data *data = &dp->hpd_data;
2252
2253         BUG_ON(!data);
2254
2255         memset(&data->mon_spec, 0, sizeof(data->mon_spec));
2256
2257         return tegra_edid_get_monspecs(data->edid, &data->mon_spec);
2258 }
2259
2260 static void tegra_edp_mode_set(struct tegra_dc_dp_data *dp)
2261 {
2262         struct fb_videomode *best_edp_fbmode = dp->hpd_data.mon_spec.modedb;
2263
2264         if (best_edp_fbmode)
2265                 tegra_dc_set_fb_mode(dp->dc, best_edp_fbmode, false);
2266         else
2267                 tegra_dc_set_default_videomode(dp->dc);
2268 }
2269
2270 static int tegra_edp_wait_plug_hpd(struct tegra_dc_dp_data *dp)
2271 {
2272 #define TEGRA_DP_HPD_PLUG_TIMEOUT_MS    1000
2273
2274         u32 val;
2275         int err = 0;
2276
2277         might_sleep();
2278
2279         if (!tegra_platform_is_silicon()) {
2280                 msleep(TEGRA_DP_HPD_PLUG_TIMEOUT_MS);
2281                 return 0;
2282         }
2283
2284         val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
2285         if (likely(val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED))
2286                 err = 0;
2287         else if (!wait_for_completion_timeout(&dp->hpd_plug,
2288                 msecs_to_jiffies(TEGRA_DP_HPD_PLUG_TIMEOUT_MS)))
2289                 err = -ENODEV;
2290
2291         return err;
2292
2293 #undef TEGRA_DP_HPD_PLUG_TIMEOUT_MS
2294 }
2295
2296 static void tegra_dc_dp_enable(struct tegra_dc *dc)
2297 {
2298         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2299         struct tegra_dc_dp_link_config *cfg = &dp->link_cfg;
2300         struct tegra_dc_sor_data *sor = dp->sor;
2301         int ret;
2302
2303         if (dp->enabled)
2304                 return;
2305
2306         tegra_dc_io_start(dc);
2307
2308         ret = tegra_dp_panel_power_state(dp, NV_DPCD_SET_POWER_VAL_D0_NORMAL);
2309         if (ret < 0) {
2310                 dev_err(&dp->dc->ndev->dev,
2311                 "dp: failed to exit panel power save mode (0x%x)\n", ret);
2312                 tegra_dc_io_end(dp->dc);
2313                 return;
2314         }
2315
2316         /* For eDP, driver gets to decide the best mode. */
2317         if (!tegra_dc_is_ext_dp_panel(dc) &&
2318                 dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
2319                 int err;
2320
2321                 /*
2322                  * Hotplug for internal panels is not supported.
2323                  * Wait till the panel asserts hpd
2324                  */
2325                 err = tegra_edp_wait_plug_hpd(dp);
2326                 if (err < 0) {
2327                         tegra_dc_io_end(dc);
2328                         dc->connected = false;
2329                         dev_err(&dc->ndev->dev,
2330                                 "edp: plug hpd wait timeout\n");
2331                         return;
2332                 }
2333
2334                 err = tegra_edp_edid_read(dp);
2335                 if (err < 0)
2336                         dev_warn(&dc->ndev->dev, "edp: edid read failed\n");
2337                 else
2338                         tegra_dp_hpd_op_edid_ready(dp);
2339                 tegra_edp_mode_set(dp);
2340                 tegra_dc_setup_clk(dc, dc->clk);
2341         }
2342
2343         tegra_dp_dpcd_init(dp);
2344
2345         tegra_dc_sor_enable_dp(dp->sor);
2346
2347         if (cfg->alt_scramber_reset_cap)
2348                 tegra_dc_dp_set_assr(dp, true);
2349         else
2350                 tegra_dc_sor_set_internal_panel(dp->sor, false);
2351
2352         tegra_dc_dp_dpcd_write(dp, NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET,
2353                         NV_DPCD_MAIN_LINK_CHANNEL_CODING_SET_ANSI_8B10B);
2354
2355         tegra_sor_write_field(sor, NV_SOR_DP_CONFIG(sor->portnum),
2356                                 NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE,
2357                                 NV_SOR_DP_CONFIG_IDLE_BEFORE_ATTACH_ENABLE);
2358
2359         /*
2360          * enhanced framing enable field shares DPCD offset
2361          * with lane count set field. Make sure lane count is set
2362          * before enhanced framing enable. CTS waits on first
2363          * write to this offset to check for lane count set.
2364          */
2365         tegra_dp_update_link_config(dp);
2366         tegra_dp_set_enhanced_framing(dp, cfg->enhanced_framing);
2367
2368         tegra_dp_tpg(dp, TRAINING_PATTERN_DISABLE, cfg->lane_count);
2369
2370         tegra_sor_port_enable(sor, true);
2371         tegra_sor_config_xbar(dp->sor);
2372
2373         tegra_dp_clk_enable(dp);
2374         tegra_sor_config_dp_clk(dp->sor);
2375         tegra_dc_setup_clk(dc, dc->clk);
2376
2377         /* Host is ready. Start link training. */
2378         dp->enabled = true;
2379
2380 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_ARCH_TEGRA_18x_SOC)
2381         if (tegra_dc_is_ext_dp_panel(dc))
2382                 tegra_hda_set_data(dp, SINK_DP);
2383 #endif
2384
2385         if (likely(dc->out->type != TEGRA_DC_OUT_FAKE_DP) &&
2386                 !no_lt_at_unblank) {
2387                 tegra_dp_lt_set_pending_evt(&dp->lt_data);
2388                 ret = tegra_dp_lt_wait_for_completion(&dp->lt_data,
2389                                                         LT_TIMEOUT_MS);
2390                 if (!ret)
2391                         dev_err(&dp->dc->ndev->dev,
2392                                 "dp: link training failed\n");
2393         } else {
2394                 /*
2395                  * Fake panel. Just enable host.
2396                  * No not engage with panel.
2397                  */
2398                 tegra_sor_tpg(dp->sor, TRAINING_PATTERN_DISABLE,
2399                                 dp->link_cfg.lane_count);
2400                 tegra_dc_sor_attach(dp->sor);
2401         }
2402
2403         if (tegra_dc_is_ext_dp_panel(dc) &&
2404                 dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2405                 tegra_dphdcp_set_plug(dp->dphdcp, true);
2406
2407         dc->connected = true;
2408         tegra_dc_io_end(dc);
2409
2410 #ifdef CONFIG_SWITCH
2411         if (tegra_edid_audio_supported(dp->hpd_data.edid)) {
2412                 pr_info("dp_audio switch 1\n");
2413                 switch_set_state(&dp->audio_switch, 1);
2414         }
2415 #endif
2416
2417         return;
2418 }
2419
2420 void tegra_dc_dp_enable_link(struct tegra_dc_dp_data *dp)
2421 {
2422         if (!dp->enabled)
2423                 tegra_dc_dp_enable(dp->dc);
2424         else
2425                 tegra_dc_sor_attach(dp->sor);
2426 }
2427
2428 static void tegra_dc_dp_destroy(struct tegra_dc *dc)
2429 {
2430         struct device_node *np_dp =
2431                 tegra_dc_which_sor(dc) ? of_find_node_by_path(DPAUX1_NODE) :
2432                 of_find_node_by_path(DPAUX_NODE);
2433         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2434
2435         if (dp->sor)
2436                 tegra_dc_sor_destroy(dp->sor);
2437
2438         tegra_hpd_shutdown(&dp->hpd_data);
2439
2440 #ifndef CONFIG_TEGRA_NVDISPLAY
2441         clk_put(dp->dpaux_clk);
2442         clk_put(dp->parent_clk);
2443 #endif
2444
2445         devm_iounmap(&dc->ndev->dev, dp->aux_base);
2446         devm_release_mem_region(&dc->ndev->dev,
2447                 dp->res->start,
2448                 resource_size(dp->res));
2449         if (!np_dp || !of_device_is_available(np_dp))
2450                 release_resource(dp->res);
2451         devm_kfree(&dc->ndev->dev, dp);
2452         if (!IS_ERR(dp->prod_list))
2453                 tegra_prod_release(&dp->prod_list);
2454
2455 #ifdef CONFIG_SWITCH
2456         switch_dev_unregister(&dp->audio_switch);
2457 #endif
2458         of_node_put(np_dp);
2459 }
2460
2461 static void tegra_dc_dp_disable(struct tegra_dc *dc)
2462 {
2463         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2464         int ret;
2465
2466         if (!dp->enabled)
2467                 return;
2468
2469         dp->enabled = false;
2470
2471         tegra_dc_io_start(dc);
2472
2473         if (tegra_dc_is_ext_dp_panel(dc) &&
2474                 dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2475                 tegra_dphdcp_set_plug(dp->dphdcp, false);
2476
2477         cancel_delayed_work_sync(&dp->irq_evt_dwork);
2478
2479         if (dc->out->type != TEGRA_DC_OUT_FAKE_DP) {
2480                 tegra_dp_lt_force_disable(&dp->lt_data);
2481                 ret = tegra_dp_lt_wait_for_completion(&dp->lt_data,
2482                                                         LT_TIMEOUT_MS);
2483                 WARN_ON(!ret);
2484         }
2485
2486         if (tegra_dc_hpd(dc)) {
2487                 ret = tegra_dp_panel_power_state(dp,
2488                         NV_DPCD_SET_POWER_VAL_D3_PWRDWN);
2489                 if (ret < 0)
2490                         dev_info(&dp->dc->ndev->dev,
2491                                 "dp: failed to enter panel power save mode\n");
2492         }
2493
2494         tegra_dc_sor_detach(dp->sor);
2495         tegra_dc_sor_disable(dp->sor, false);
2496
2497         tegra_dp_clk_disable(dp);
2498
2499         tegra_dc_io_end(dc);
2500
2501 #if defined(CONFIG_ARCH_TEGRA_21x_SOC) || defined(CONFIG_ARCH_TEGRA_18x_SOC)
2502         if (tegra_dc_is_ext_dp_panel(dc))
2503                 tegra_hda_reset_data();
2504 #endif
2505
2506 #ifdef CONFIG_SWITCH
2507         if (tegra_edid_audio_supported(dp->hpd_data.edid)) {
2508                 pr_info("dp_audio switch 0\n");
2509                 switch_set_state(&dp->audio_switch, 0);
2510         }
2511 #endif
2512 }
2513
2514 void tegra_dc_dp_pre_disable_link(struct tegra_dc_dp_data *dp)
2515 {
2516         tegra_dc_sor_pre_detach(dp->sor);
2517 }
2518
2519 void tegra_dc_dp_disable_link(struct tegra_dc_dp_data *dp, bool powerdown)
2520 {
2521         tegra_dc_sor_detach(dp->sor);
2522
2523         if (powerdown)
2524                 tegra_dc_dp_disable(dp->dc);
2525 }
2526
2527 static long tegra_dc_dp_setup_clk(struct tegra_dc *dc, struct clk *clk)
2528 {
2529         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2530         struct clk *dc_parent_clk;
2531
2532         if (!tegra_platform_is_silicon())
2533                 return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2534
2535         if (clk == dc->clk) {
2536                 dc_parent_clk = clk_get_sys(NULL,
2537                                 dc->out->parent_clk ? : "pll_d_out0");
2538                 clk_set_parent(dc->clk, dc_parent_clk);
2539         }
2540
2541         tegra_sor_setup_clk(dp->sor, clk, false);
2542
2543         /* fixed pll_dp@270MHz */
2544         clk_set_rate(dp->parent_clk, 270000000);
2545
2546         return tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
2547 }
2548
2549 static bool tegra_dc_dp_hpd_state(struct tegra_dc *dc)
2550 {
2551         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2552         u32 val;
2553
2554         if (WARN_ON(!dc || !dc->out))
2555                 return false;
2556
2557         if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
2558                 tegra_platform_is_linsim())
2559                 return true;
2560
2561         tegra_dpaux_clk_enable(dp);
2562         tegra_dc_io_start(dc);
2563         val = tegra_dpaux_readl(dp, DPAUX_DP_AUXSTAT);
2564         tegra_dc_io_end(dc);
2565
2566         return !!(val & DPAUX_DP_AUXSTAT_HPD_STATUS_PLUGGED);
2567 }
2568
2569 /* used by tegra_dc_probe() to detect connection(HPD) status at boot */
2570 static bool tegra_dc_dp_detect(struct tegra_dc *dc)
2571 {
2572         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2573
2574         if (tegra_platform_is_linsim())
2575                 return true;
2576
2577         tegra_dp_pending_hpd(dp);
2578
2579         return tegra_dc_hpd(dc);
2580 }
2581
2582 static void tegra_dc_dp_suspend(struct tegra_dc *dc)
2583 {
2584         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2585
2586         if (dp->suspended)
2587                 return;
2588
2589         dp->suspended = true;
2590
2591         /* do not process hpd in suspend. Disable dpaux clocks. */
2592         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2593                 tegra_dp_disable_irq(dp->irq);
2594         if (dp->sor->safe_clk)
2595                 tegra_sor_safe_clk_disable(dp->sor);
2596         tegra_dpaux_clk_disable(dp);
2597
2598         tegra_dc_powergate_locked(dc);
2599 }
2600
2601 static void tegra_dc_dp_resume(struct tegra_dc *dc)
2602 {
2603         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2604
2605         if (!dp->suspended)
2606                 return;
2607
2608         tegra_dc_unpowergate_locked(dc);
2609
2610         /* Get ready to receive any hpd event */
2611         _tegra_dpaux_init(dp);
2612         if (dp->dc->out->type != TEGRA_DC_OUT_FAKE_DP)
2613                 tegra_dp_enable_irq(dp->irq);
2614
2615         tegra_dp_pending_hpd(dp);
2616
2617         dp->suspended = false;
2618 }
2619
2620 static void tegra_dc_dp_modeset_notifier(struct tegra_dc *dc)
2621 {
2622         struct tegra_dc_dp_data *dp = tegra_dc_get_outdata(dc);
2623
2624         tegra_dc_io_start(dc);
2625         tegra_dpaux_clk_enable(dp);
2626
2627         tegra_dc_sor_modeset_notifier(dp->sor, false);
2628         /* Pixel clock may be changed in new mode,
2629          * recalculate link config */
2630         if (!tegra_platform_is_linsim())
2631                 tegra_dc_dp_calc_config(dp, dp->mode, &dp->link_cfg);
2632
2633
2634         tegra_dpaux_clk_disable(dp);
2635         tegra_dc_io_end(dc);
2636 }
2637
2638 static bool tegra_dp_check_dc_constraint(const struct fb_videomode *mode)
2639 {
2640         return (mode->hsync_len >= 1) && (mode->vsync_len >= 1) &&
2641                 (mode->lower_margin + mode->vsync_len +
2642                 mode->upper_margin > 1) &&
2643                 (mode->xres >= 16) && (mode->yres >= 16);
2644 }
2645
2646 static bool tegra_dp_mode_filter(const struct tegra_dc *dc,
2647                                 struct fb_videomode *mode)
2648 {
2649         if (!mode->pixclock)
2650                 return false;
2651
2652         if (mode->xres > 4096)
2653                 return false;
2654
2655         if (mode->pixclock && tegra_dc_get_out_max_pixclock(dc) &&
2656                 mode->pixclock < tegra_dc_get_out_max_pixclock(dc))
2657                 return false;
2658
2659         /*
2660          * Work around for modes that fail the constraint:
2661          * V_FRONT_PORCH >= V_REF_TO_SYNC + 1
2662          */
2663         if (mode->lower_margin == 1) {
2664                 mode->lower_margin++;
2665                 mode->upper_margin--;
2666                 mode->vmode |= FB_VMODE_ADJUSTED;
2667         }
2668
2669         if (!tegra_dp_check_dc_constraint(mode))
2670                 return false;
2671
2672         /*
2673          * CTS mandates that if edid is corrupted
2674          * use fail-safe mode i.e. VGA 640x480@60
2675          */
2676         if (dc->edid->errors)
2677                 return (mode->xres == 640 && mode->yres == 480
2678                         && mode->refresh == 60) ? true : false;
2679
2680         return true;
2681 }
2682
2683 static bool (*tegra_dp_op_get_mode_filter(void *drv_data))
2684         (const struct tegra_dc *dc, struct fb_videomode *mode) {
2685         return tegra_dp_mode_filter;
2686 }
2687
2688 static bool tegra_dp_hpd_op_get_hpd_state(void *drv_data)
2689 {
2690         struct tegra_dc_dp_data *dp = drv_data;
2691
2692         return tegra_dc_hpd(dp->dc);
2693 }
2694
2695 static void tegra_dp_hpd_op_init(void *drv_data)
2696 {
2697         struct tegra_dc_dp_data *dp = drv_data;
2698
2699 #ifdef CONFIG_SWITCH
2700         if (tegra_dc_is_ext_dp_panel(dp->dc)) {
2701                 dp->hpd_data.hpd_switch_name = "dp";
2702         }
2703 #endif
2704 }
2705
2706 static bool tegra_dp_hpd_op_edid_read_prepare(void *drv_data)
2707 {
2708         struct tegra_dc_dp_data *dp = drv_data;
2709         int ret;
2710
2711         tegra_dc_io_start(dp->dc);
2712
2713         ret = tegra_dp_panel_power_state(dp, NV_DPCD_SET_POWER_VAL_D0_NORMAL);
2714         if (ret < 0) {
2715                 dev_err(&dp->dc->ndev->dev,
2716                 "dp: failed to exit panel power save mode (0x%x)\n", ret);
2717                 tegra_dc_io_end(dp->dc);
2718                 return false;
2719         }
2720
2721         tegra_dc_io_end(dp->dc);
2722
2723         return true;
2724 }
2725
2726 static struct tegra_hpd_ops hpd_ops = {
2727         .edid_read = tegra_dp_hpd_op_edid_read,
2728         .edid_ready = tegra_dp_hpd_op_edid_ready,
2729         .edid_recheck = tegra_dp_hpd_op_edid_recheck,
2730         .get_mode_filter = tegra_dp_op_get_mode_filter,
2731         .get_hpd_state = tegra_dp_hpd_op_get_hpd_state,
2732         .init = tegra_dp_hpd_op_init,
2733         .edid_read_prepare = tegra_dp_hpd_op_edid_read_prepare,
2734 };
2735
2736 struct tegra_dc_out_ops tegra_dc_dp_ops = {
2737         .init      = tegra_dc_dp_init,
2738         .destroy   = tegra_dc_dp_destroy,
2739         .enable    = tegra_dc_dp_enable,
2740         .disable   = tegra_dc_dp_disable,
2741         .detect    = tegra_dc_dp_detect,
2742         .setup_clk = tegra_dc_dp_setup_clk,
2743         .modeset_notifier = tegra_dc_dp_modeset_notifier,
2744         .hpd_state = tegra_dc_dp_hpd_state,
2745         .suspend = tegra_dc_dp_suspend,
2746         .resume = tegra_dc_dp_resume,
2747         .hotplug_init = tegra_dc_dp_hotplug_init,
2748 };