tegra: dc: Workaround a simulator bug.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
63 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
64 #else
65 /* ignore underflows when on simulation and fpga platform */
66 #define ALL_UF_INT (0)
67 #endif
68
69 static int no_vsync;
70 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
71         .refresh = 60,
72         .xres = 640,
73         .yres = 480,
74         .pixclock = KHZ2PICOS(25200),
75         .hsync_len = 96,        /* h_sync_width */
76         .vsync_len = 2,         /* v_sync_width */
77         .left_margin = 48,      /* h_back_porch */
78         .upper_margin = 33,     /* v_back_porch */
79         .right_margin = 16,     /* h_front_porch */
80         .lower_margin = 10,     /* v_front_porch */
81         .vmode = 0,
82         .sync = 0,
83 };
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
88
89 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
90
91 DEFINE_MUTEX(tegra_dc_lock);
92 DEFINE_MUTEX(shared_lock);
93
94 static const struct {
95         bool h;
96         bool v;
97 } can_filter[] = {
98         /* Window A has no filtering */
99         { false, false },
100         /* Window B has both H and V filtering */
101         { true,  true  },
102         /* Window C has only H filtering */
103         { false, true  },
104 };
105
106 #ifdef CONFIG_TEGRA_DC_CMU
107 static struct tegra_dc_cmu default_cmu = {
108         /* lut1 maps sRGB to linear space. */
109         {
110                 0,    1,    2,    4,    5,    6,    7,    9,
111                 10,   11,   12,   14,   15,   16,   18,   20,
112                 21,   23,   25,   27,   29,   31,   33,   35,
113                 37,   40,   42,   45,   48,   50,   53,   56,
114                 59,   62,   66,   69,   72,   76,   79,   83,
115                 87,   91,   95,   99,   103,  107,  112,  116,
116                 121,  126,  131,  136,  141,  146,  151,  156,
117                 162,  168,  173,  179,  185,  191,  197,  204,
118                 210,  216,  223,  230,  237,  244,  251,  258,
119                 265,  273,  280,  288,  296,  304,  312,  320,
120                 329,  337,  346,  354,  363,  372,  381,  390,
121                 400,  409,  419,  428,  438,  448,  458,  469,
122                 479,  490,  500,  511,  522,  533,  544,  555,
123                 567,  578,  590,  602,  614,  626,  639,  651,
124                 664,  676,  689,  702,  715,  728,  742,  755,
125                 769,  783,  797,  811,  825,  840,  854,  869,
126                 884,  899,  914,  929,  945,  960,  976,  992,
127                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
128                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
129                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
130                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
131                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
132                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
133                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
134                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
135                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
136                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
137                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
138                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
139                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
140                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
141                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
142         },
143         /* csc */
144         {
145                 0x100, 0x0,   0x0,
146                 0x0,   0x100, 0x0,
147                 0x0,   0x0,   0x100,
148         },
149         /* lut2 maps linear space to sRGB*/
150         {
151                 0,    1,    2,    2,    3,    4,    5,    6,
152                 6,    7,    8,    9,    10,   10,   11,   12,
153                 13,   13,   14,   15,   15,   16,   16,   17,
154                 18,   18,   19,   19,   20,   20,   21,   21,
155                 22,   22,   23,   23,   23,   24,   24,   25,
156                 25,   25,   26,   26,   27,   27,   27,   28,
157                 28,   29,   29,   29,   30,   30,   30,   31,
158                 31,   31,   32,   32,   32,   33,   33,   33,
159                 34,   34,   34,   34,   35,   35,   35,   36,
160                 36,   36,   37,   37,   37,   37,   38,   38,
161                 38,   38,   39,   39,   39,   40,   40,   40,
162                 40,   41,   41,   41,   41,   42,   42,   42,
163                 42,   43,   43,   43,   43,   43,   44,   44,
164                 44,   44,   45,   45,   45,   45,   46,   46,
165                 46,   46,   46,   47,   47,   47,   47,   48,
166                 48,   48,   48,   48,   49,   49,   49,   49,
167                 49,   50,   50,   50,   50,   50,   51,   51,
168                 51,   51,   51,   52,   52,   52,   52,   52,
169                 53,   53,   53,   53,   53,   54,   54,   54,
170                 54,   54,   55,   55,   55,   55,   55,   55,
171                 56,   56,   56,   56,   56,   57,   57,   57,
172                 57,   57,   57,   58,   58,   58,   58,   58,
173                 58,   59,   59,   59,   59,   59,   59,   60,
174                 60,   60,   60,   60,   60,   61,   61,   61,
175                 61,   61,   61,   62,   62,   62,   62,   62,
176                 62,   63,   63,   63,   63,   63,   63,   64,
177                 64,   64,   64,   64,   64,   64,   65,   65,
178                 65,   65,   65,   65,   66,   66,   66,   66,
179                 66,   66,   66,   67,   67,   67,   67,   67,
180                 67,   67,   68,   68,   68,   68,   68,   68,
181                 68,   69,   69,   69,   69,   69,   69,   69,
182                 70,   70,   70,   70,   70,   70,   70,   71,
183                 71,   71,   71,   71,   71,   71,   72,   72,
184                 72,   72,   72,   72,   72,   72,   73,   73,
185                 73,   73,   73,   73,   73,   74,   74,   74,
186                 74,   74,   74,   74,   74,   75,   75,   75,
187                 75,   75,   75,   75,   75,   76,   76,   76,
188                 76,   76,   76,   76,   77,   77,   77,   77,
189                 77,   77,   77,   77,   78,   78,   78,   78,
190                 78,   78,   78,   78,   78,   79,   79,   79,
191                 79,   79,   79,   79,   79,   80,   80,   80,
192                 80,   80,   80,   80,   80,   81,   81,   81,
193                 81,   81,   81,   81,   81,   81,   82,   82,
194                 82,   82,   82,   82,   82,   82,   83,   83,
195                 83,   83,   83,   83,   83,   83,   83,   84,
196                 84,   84,   84,   84,   84,   84,   84,   84,
197                 85,   85,   85,   85,   85,   85,   85,   85,
198                 85,   86,   86,   86,   86,   86,   86,   86,
199                 86,   86,   87,   87,   87,   87,   87,   87,
200                 87,   87,   87,   88,   88,   88,   88,   88,
201                 88,   88,   88,   88,   88,   89,   89,   89,
202                 89,   89,   89,   89,   89,   89,   90,   90,
203                 90,   90,   90,   90,   90,   90,   90,   90,
204                 91,   91,   91,   91,   91,   91,   91,   91,
205                 91,   91,   92,   92,   92,   92,   92,   92,
206                 92,   92,   92,   92,   93,   93,   93,   93,
207                 93,   93,   93,   93,   93,   93,   94,   94,
208                 94,   94,   94,   94,   94,   94,   94,   94,
209                 95,   95,   95,   95,   95,   95,   95,   95,
210                 95,   95,   96,   96,   96,   96,   96,   96,
211                 96,   96,   96,   96,   96,   97,   97,   97,
212                 97,   97,   97,   97,   97,   97,   97,   98,
213                 98,   98,   98,   98,   98,   98,   98,   98,
214                 98,   98,   99,   99,   99,   99,   99,   99,
215                 99,   100,  101,  101,  102,  103,  103,  104,
216                 105,  105,  106,  107,  107,  108,  109,  109,
217                 110,  111,  111,  112,  113,  113,  114,  115,
218                 115,  116,  116,  117,  118,  118,  119,  119,
219                 120,  120,  121,  122,  122,  123,  123,  124,
220                 124,  125,  126,  126,  127,  127,  128,  128,
221                 129,  129,  130,  130,  131,  131,  132,  132,
222                 133,  133,  134,  134,  135,  135,  136,  136,
223                 137,  137,  138,  138,  139,  139,  140,  140,
224                 141,  141,  142,  142,  143,  143,  144,  144,
225                 145,  145,  145,  146,  146,  147,  147,  148,
226                 148,  149,  149,  150,  150,  150,  151,  151,
227                 152,  152,  153,  153,  153,  154,  154,  155,
228                 155,  156,  156,  156,  157,  157,  158,  158,
229                 158,  159,  159,  160,  160,  160,  161,  161,
230                 162,  162,  162,  163,  163,  164,  164,  164,
231                 165,  165,  166,  166,  166,  167,  167,  167,
232                 168,  168,  169,  169,  169,  170,  170,  170,
233                 171,  171,  172,  172,  172,  173,  173,  173,
234                 174,  174,  174,  175,  175,  176,  176,  176,
235                 177,  177,  177,  178,  178,  178,  179,  179,
236                 179,  180,  180,  180,  181,  181,  182,  182,
237                 182,  183,  183,  183,  184,  184,  184,  185,
238                 185,  185,  186,  186,  186,  187,  187,  187,
239                 188,  188,  188,  189,  189,  189,  189,  190,
240                 190,  190,  191,  191,  191,  192,  192,  192,
241                 193,  193,  193,  194,  194,  194,  195,  195,
242                 195,  196,  196,  196,  196,  197,  197,  197,
243                 198,  198,  198,  199,  199,  199,  200,  200,
244                 200,  200,  201,  201,  201,  202,  202,  202,
245                 202,  203,  203,  203,  204,  204,  204,  205,
246                 205,  205,  205,  206,  206,  206,  207,  207,
247                 207,  207,  208,  208,  208,  209,  209,  209,
248                 209,  210,  210,  210,  211,  211,  211,  211,
249                 212,  212,  212,  213,  213,  213,  213,  214,
250                 214,  214,  214,  215,  215,  215,  216,  216,
251                 216,  216,  217,  217,  217,  217,  218,  218,
252                 218,  219,  219,  219,  219,  220,  220,  220,
253                 220,  221,  221,  221,  221,  222,  222,  222,
254                 223,  223,  223,  223,  224,  224,  224,  224,
255                 225,  225,  225,  225,  226,  226,  226,  226,
256                 227,  227,  227,  227,  228,  228,  228,  228,
257                 229,  229,  229,  229,  230,  230,  230,  230,
258                 231,  231,  231,  231,  232,  232,  232,  232,
259                 233,  233,  233,  233,  234,  234,  234,  234,
260                 235,  235,  235,  235,  236,  236,  236,  236,
261                 237,  237,  237,  237,  238,  238,  238,  238,
262                 239,  239,  239,  239,  240,  240,  240,  240,
263                 240,  241,  241,  241,  241,  242,  242,  242,
264                 242,  243,  243,  243,  243,  244,  244,  244,
265                 244,  244,  245,  245,  245,  245,  246,  246,
266                 246,  246,  247,  247,  247,  247,  247,  248,
267                 248,  248,  248,  249,  249,  249,  249,  249,
268                 250,  250,  250,  250,  251,  251,  251,  251,
269                 251,  252,  252,  252,  252,  253,  253,  253,
270                 253,  253,  254,  254,  254,  254,  255,  255,
271         },
272 };
273 #endif
274
275 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
276 {
277         if (!tegra_is_clk_enabled(dc->clk)) {
278                 clk_enable(dc->clk);
279                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
280         }
281 }
282
283 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
284 {
285         if (tegra_is_clk_enabled(dc->clk)) {
286                 clk_disable(dc->clk);
287                 tegra_dvfs_set_rate(dc->clk, 0);
288         }
289 }
290
291 #define DUMP_REG(a) do {                        \
292         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
293                  #a, a, tegra_dc_readl(dc, a));               \
294         print(data, buff);                                    \
295         } while (0)
296
297 #define print_mode_info(dc, mode) do {                        \
298         trace_printk("%s:Mode settings: "                              \
299                         "ref_to_sync: H = %d V = %d, "                  \
300                         "sync_width: H = %d V = %d, "                   \
301                         "back_porch: H = %d V = %d, "                   \
302                         "active: H = %d V = %d, "                       \
303                         "front_porch: H = %d V = %d, "                  \
304                         "pclk = %d, stereo mode = %d\n",                \
305                         dc->ndev->name,                                 \
306                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
307                         mode.h_sync_width, mode.v_sync_width,           \
308                         mode.h_back_porch, mode.v_back_porch,           \
309                         mode.h_active, mode.v_active,                   \
310                         mode.h_front_porch, mode.v_front_porch,         \
311                         mode.pclk, mode.stereo_mode);                   \
312         } while (0)
313
314 #define print_underflow_info(dc) do {                 \
315         trace_printk("%s:Underflow stats: underflows : %llu, "      \
316                         "undeflows_a : %llu, "                          \
317                         "underflows_b : %llu, "                         \
318                         "underflows_c : %llu\n",                        \
319                         dc->ndev->name,                                 \
320                         dc->stats.underflows,                           \
321                         dc->stats.underflows_a, dc->stats.underflows_b, \
322                         dc->stats.underflows_c);                        \
323         } while (0)
324
325 static void _dump_regs(struct tegra_dc *dc, void *data,
326                        void (* print)(void *data, const char *str))
327 {
328         int i;
329         char buff[256];
330
331         tegra_dc_io_start(dc);
332         tegra_dc_clk_enable(dc);
333
334         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
335         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
336         DUMP_REG(DC_CMD_SIGNAL_RAISE);
337         DUMP_REG(DC_CMD_INT_STATUS);
338         DUMP_REG(DC_CMD_INT_MASK);
339         DUMP_REG(DC_CMD_INT_ENABLE);
340         DUMP_REG(DC_CMD_INT_TYPE);
341         DUMP_REG(DC_CMD_INT_POLARITY);
342         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
343         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
344         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
345         DUMP_REG(DC_CMD_STATE_ACCESS);
346         DUMP_REG(DC_CMD_STATE_CONTROL);
347         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
348         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
349
350         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
351         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
352         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
353         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
354         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
355         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
356         DUMP_REG(DC_DISP_REF_TO_SYNC);
357         DUMP_REG(DC_DISP_SYNC_WIDTH);
358         DUMP_REG(DC_DISP_BACK_PORCH);
359         DUMP_REG(DC_DISP_DISP_ACTIVE);
360         DUMP_REG(DC_DISP_FRONT_PORCH);
361         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
362         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
363         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
364         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
365         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
366         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
367         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
368         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
369         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
370         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
371         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
372         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
373         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
374         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
375         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
376         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
377         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
378         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
379         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
380         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
381         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
382         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
383         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
384         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
385         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
386         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
387         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
388         DUMP_REG(DC_DISP_M0_CONTROL);
389         DUMP_REG(DC_DISP_M1_CONTROL);
390         DUMP_REG(DC_DISP_DI_CONTROL);
391         DUMP_REG(DC_DISP_PP_CONTROL);
392         DUMP_REG(DC_DISP_PP_SELECT_A);
393         DUMP_REG(DC_DISP_PP_SELECT_B);
394         DUMP_REG(DC_DISP_PP_SELECT_C);
395         DUMP_REG(DC_DISP_PP_SELECT_D);
396         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
397         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
398         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
399         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
400         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
401         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
402         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
403         DUMP_REG(DC_DISP_BORDER_COLOR);
404         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
405         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
406         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
407         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
408         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
409         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
410         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
411         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
412         DUMP_REG(DC_DISP_CURSOR_POSITION);
413         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
414         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
415         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
416         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
417         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
418         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
419         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
420         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
421         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
422         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
423         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
424         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
425         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
426
427
428         for (i = 0; i < 3; i++) {
429                 print(data, "\n");
430                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
431                 print(data, buff);
432
433                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
434                                 DC_CMD_DISPLAY_WINDOW_HEADER);
435                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
436                 DUMP_REG(DC_WIN_WIN_OPTIONS);
437                 DUMP_REG(DC_WIN_BYTE_SWAP);
438                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
439                 DUMP_REG(DC_WIN_COLOR_DEPTH);
440                 DUMP_REG(DC_WIN_POSITION);
441                 DUMP_REG(DC_WIN_SIZE);
442                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
443                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
444                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
445                 DUMP_REG(DC_WIN_DDA_INCREMENT);
446                 DUMP_REG(DC_WIN_LINE_STRIDE);
447 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
448                 DUMP_REG(DC_WIN_BUF_STRIDE);
449                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
450 #endif
451                 DUMP_REG(DC_WIN_BLEND_NOKEY);
452                 DUMP_REG(DC_WIN_BLEND_1WIN);
453                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
454                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
455                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
456                 DUMP_REG(DC_WINBUF_START_ADDR);
457                 DUMP_REG(DC_WINBUF_START_ADDR_U);
458                 DUMP_REG(DC_WINBUF_START_ADDR_V);
459                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
460                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
461                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
462                 DUMP_REG(DC_WIN_CSC_YOF);
463                 DUMP_REG(DC_WIN_CSC_KYRGB);
464                 DUMP_REG(DC_WIN_CSC_KUR);
465                 DUMP_REG(DC_WIN_CSC_KVR);
466                 DUMP_REG(DC_WIN_CSC_KUG);
467                 DUMP_REG(DC_WIN_CSC_KVG);
468                 DUMP_REG(DC_WIN_CSC_KUB);
469                 DUMP_REG(DC_WIN_CSC_KVB);
470         }
471
472         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
473         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
474         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
475         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
476         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
477         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
478         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
479         DUMP_REG(DC_DISP_M1_CONTROL);
480         DUMP_REG(DC_COM_PM1_CONTROL);
481         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
482         DUMP_REG(DC_DISP_SD_CONTROL);
483
484         tegra_dc_clk_disable(dc->clk);
485         tegra_dc_io_end(dc);
486 }
487
488 #undef DUMP_REG
489
490 #ifdef DEBUG
491 static void dump_regs_print(void *data, const char *str)
492 {
493         struct tegra_dc *dc = data;
494         dev_dbg(&dc->ndev->dev, "%s", str);
495 }
496
497 static void dump_regs(struct tegra_dc *dc)
498 {
499         _dump_regs(dc, dc, dump_regs_print);
500 }
501 #else /* !DEBUG */
502
503 static void dump_regs(struct tegra_dc *dc) {}
504
505 #endif /* DEBUG */
506
507 #ifdef CONFIG_DEBUG_FS
508
509 static void dbg_regs_print(void *data, const char *str)
510 {
511         struct seq_file *s = data;
512
513         seq_printf(s, "%s", str);
514 }
515
516 #undef DUMP_REG
517
518 static int dbg_dc_show(struct seq_file *s, void *unused)
519 {
520         struct tegra_dc *dc = s->private;
521
522         _dump_regs(dc, s, dbg_regs_print);
523
524         return 0;
525 }
526
527
528 static int dbg_dc_open(struct inode *inode, struct file *file)
529 {
530         return single_open(file, dbg_dc_show, inode->i_private);
531 }
532
533 static const struct file_operations regs_fops = {
534         .open           = dbg_dc_open,
535         .read           = seq_read,
536         .llseek         = seq_lseek,
537         .release        = single_release,
538 };
539
540 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
541 {
542         struct tegra_dc *dc = s->private;
543         struct tegra_dc_mode *m;
544
545         mutex_lock(&dc->lock);
546         m = &dc->mode;
547         seq_printf(s,
548                 "pclk: %d\n"
549                 "h_ref_to_sync: %d\n"
550                 "v_ref_to_sync: %d\n"
551                 "h_sync_width: %d\n"
552                 "v_sync_width: %d\n"
553                 "h_back_porch: %d\n"
554                 "v_back_porch: %d\n"
555                 "h_active: %d\n"
556                 "v_active: %d\n"
557                 "h_front_porch: %d\n"
558                 "v_front_porch: %d\n"
559                 "stereo_mode: %d\n",
560                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
561                 m->h_sync_width, m->v_sync_width,
562                 m->h_back_porch, m->v_back_porch,
563                 m->h_active, m->v_active,
564                 m->h_front_porch, m->v_front_porch,
565                 m->stereo_mode);
566         mutex_unlock(&dc->lock);
567         return 0;
568 }
569
570 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
571 {
572         return single_open(file, dbg_dc_mode_show, inode->i_private);
573 }
574
575 static const struct file_operations mode_fops = {
576         .open           = dbg_dc_mode_open,
577         .read           = seq_read,
578         .llseek         = seq_lseek,
579         .release        = single_release,
580 };
581
582 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
583 {
584         struct tegra_dc *dc = s->private;
585
586         mutex_lock(&dc->lock);
587         seq_printf(s,
588                 "underflows: %llu\n"
589                 "underflows_a: %llu\n"
590                 "underflows_b: %llu\n"
591                 "underflows_c: %llu\n",
592                 dc->stats.underflows,
593                 dc->stats.underflows_a,
594                 dc->stats.underflows_b,
595                 dc->stats.underflows_c);
596         mutex_unlock(&dc->lock);
597
598         return 0;
599 }
600
601 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
602 {
603         return single_open(file, dbg_dc_stats_show, inode->i_private);
604 }
605
606 static const struct file_operations stats_fops = {
607         .open           = dbg_dc_stats_open,
608         .read           = seq_read,
609         .llseek         = seq_lseek,
610         .release        = single_release,
611 };
612
613 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
614 {
615         if (dc->debugdir)
616                 debugfs_remove_recursive(dc->debugdir);
617         dc->debugdir = NULL;
618 }
619
620 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
621 {
622         struct dentry *retval;
623
624         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
625         if (!dc->debugdir)
626                 goto remove_out;
627
628         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
629                 &regs_fops);
630         if (!retval)
631                 goto remove_out;
632
633         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
634                 &mode_fops);
635         if (!retval)
636                 goto remove_out;
637
638         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
639                 &stats_fops);
640         if (!retval)
641                 goto remove_out;
642
643         return;
644 remove_out:
645         dev_err(&dc->ndev->dev, "could not create debugfs\n");
646         tegra_dc_remove_debugfs(dc);
647 }
648
649 #else /* !CONFIG_DEBUGFS */
650 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
651 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
652 #endif /* CONFIG_DEBUGFS */
653
654 static int tegra_dc_set(struct tegra_dc *dc, int index)
655 {
656         int ret = 0;
657
658         mutex_lock(&tegra_dc_lock);
659         if (index >= TEGRA_MAX_DC) {
660                 ret = -EINVAL;
661                 goto out;
662         }
663
664         if (dc != NULL && tegra_dcs[index] != NULL) {
665                 ret = -EBUSY;
666                 goto out;
667         }
668
669         tegra_dcs[index] = dc;
670
671 out:
672         mutex_unlock(&tegra_dc_lock);
673
674         return ret;
675 }
676
677 unsigned int tegra_dc_has_multiple_dc(void)
678 {
679         unsigned int idx;
680         unsigned int cnt = 0;
681         struct tegra_dc *dc;
682
683         mutex_lock(&tegra_dc_lock);
684         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
685                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
686         mutex_unlock(&tegra_dc_lock);
687
688         return (cnt > 1);
689 }
690
691 /* get the stride size of a window.
692  * return: stride size in bytes for window win. or 0 if unavailble. */
693 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
694 {
695         u32 stride;
696
697         if (!dc->enabled)
698                 return 0;
699         BUG_ON(win > DC_N_WINDOWS);
700         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
701                 DC_CMD_DISPLAY_WINDOW_HEADER);
702         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
703         return GET_LINE_STRIDE(stride);
704 }
705 EXPORT_SYMBOL(tegra_dc_get_stride);
706
707 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
708 {
709         if (idx < TEGRA_MAX_DC)
710                 return tegra_dcs[idx];
711         else
712                 return NULL;
713 }
714 EXPORT_SYMBOL(tegra_dc_get_dc);
715
716 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
717 {
718         if (win >= dc->n_windows)
719                 return NULL;
720
721         return &dc->windows[win];
722 }
723 EXPORT_SYMBOL(tegra_dc_get_window);
724
725 static int get_topmost_window(u32 *depths, unsigned long *wins, int win_num)
726 {
727         int idx, best = -1;
728
729         for_each_set_bit(idx, wins, win_num) {
730                 if (best == -1 || depths[idx] < depths[best])
731                         best = idx;
732         }
733         clear_bit(best, wins);
734         return best;
735 }
736
737 bool tegra_dc_get_connected(struct tegra_dc *dc)
738 {
739         return dc->connected;
740 }
741 EXPORT_SYMBOL(tegra_dc_get_connected);
742
743 bool tegra_dc_hpd(struct tegra_dc *dc)
744 {
745         int sense;
746         int level;
747
748         level = gpio_get_value(dc->out->hotplug_gpio);
749
750         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
751
752         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
753                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
754 }
755 EXPORT_SYMBOL(tegra_dc_hpd);
756
757 static u32 blend_topwin(u32 flags)
758 {
759         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
760                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
761         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
762                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
763         else
764                 return BLEND(NOKEY, FIX, 0xff, 0xff);
765 }
766
767 static u32 blend_2win(int idx, unsigned long behind_mask,
768                                                 u32* flags, int xy, int win_num)
769 {
770         int other;
771
772         for (other = 0; other < win_num; other++) {
773                 if (other != idx && (xy-- == 0))
774                         break;
775         }
776         if (BIT(other) & behind_mask)
777                 return blend_topwin(flags[idx]);
778         else if (flags[other])
779                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
780         else
781                 return BLEND(NOKEY, FIX, 0x00, 0x00);
782 }
783
784 static u32 blend_3win(int idx, unsigned long behind_mask,
785                                                 u32* flags, int win_num)
786 {
787         unsigned long infront_mask;
788         int first;
789
790         infront_mask = ~(behind_mask | BIT(idx));
791         infront_mask &= (BIT(win_num) - 1);
792         first = ffs(infront_mask) - 1;
793
794         if (!infront_mask)
795                 return blend_topwin(flags[idx]);
796         else if (behind_mask && first != -1 && flags[first])
797                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
798         else
799                 return BLEND(NOKEY, FIX, 0x0, 0x0);
800 }
801
802 static void tegra_dc_set_gen1_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
803 {
804         int win_num = dc->gen1_blend_num;
805         unsigned long mask = BIT(win_num) - 1;
806
807         while (mask) {
808                 int idx = get_topmost_window(blend->z, &mask, win_num);
809
810                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
811                                 DC_CMD_DISPLAY_WINDOW_HEADER);
812                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
813                                 DC_WIN_BLEND_NOKEY);
814                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
815                                 DC_WIN_BLEND_1WIN);
816                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0,
817                                 win_num), DC_WIN_BLEND_2WIN_X);
818                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1,
819                                 win_num), DC_WIN_BLEND_2WIN_Y);
820                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags,
821                                 win_num), DC_WIN_BLEND_3WIN_XY);
822         }
823 }
824
825 static void tegra_dc_set_gen2_blending(struct tegra_dc *dc,
826                                                 struct tegra_dc_blend *blend)
827 {
828         long val;
829         int i = 0;
830
831         for (i = 0; i < DC_N_WINDOWS; i++) {
832                 if (!tegra_dc_feature_is_gen2_blender(dc, i))
833                         continue;
834
835                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
836                                 DC_CMD_DISPLAY_WINDOW_HEADER);
837
838                 if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_COVERAGE) {
839                         tegra_dc_writel(dc,
840                                         WIN_K1(0xff) |
841                                         WIN_K2(0xff) |
842                                         WIN_BLEND_ENABLE,
843                                         DC_WINBUF_BLEND_LAYER_CONTROL);
844
845                         tegra_dc_writel(dc,
846                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC |
847                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC |
848                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
849                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
850                         DC_WINBUF_BLEND_MATCH_SELECT);
851
852                         tegra_dc_writel(dc,
853                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
854                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
855                                         DC_WINBUF_BLEND_ALPHA_1BIT);
856                 } else if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_PREMULT) {
857                         tegra_dc_writel(dc,
858                                         WIN_K1(0xff) |
859                                         WIN_K2(0xff) |
860                                         WIN_BLEND_ENABLE,
861                                         DC_WINBUF_BLEND_LAYER_CONTROL);
862
863                         tegra_dc_writel(dc,
864                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 |
865                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 |
866                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
867                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
868                         DC_WINBUF_BLEND_MATCH_SELECT);
869
870                         tegra_dc_writel(dc,
871                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
872                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
873                                         DC_WINBUF_BLEND_ALPHA_1BIT);
874                 } else {
875                         tegra_dc_writel(dc,
876                                         WIN_BLEND_BYPASS,
877                                         DC_WINBUF_BLEND_LAYER_CONTROL);
878                 }
879         }
880 }
881
882 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
883 {
884         csc->yof   = 0x00f0;
885         csc->kyrgb = 0x012a;
886         csc->kur   = 0x0000;
887         csc->kvr   = 0x0198;
888         csc->kug   = 0x039b;
889         csc->kvg   = 0x032f;
890         csc->kub   = 0x0204;
891         csc->kvb   = 0x0000;
892 }
893
894 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
895 {
896         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
897         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
898         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
899         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
900         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
901         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
902         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
903         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
904 }
905
906 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
907 {
908         mutex_lock(&dc->lock);
909
910         if (!dc->enabled) {
911                 mutex_unlock(&dc->lock);
912                 return -EFAULT;
913         }
914
915         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
916                         DC_CMD_DISPLAY_WINDOW_HEADER);
917
918         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
919
920         mutex_unlock(&dc->lock);
921
922         return 0;
923 }
924 EXPORT_SYMBOL(tegra_dc_update_csc);
925
926 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
927 {
928         int i;
929         for (i = 0; i < 256; i++)
930                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
931 }
932
933 static int tegra_dc_loop_lut(struct tegra_dc *dc,
934                              struct tegra_dc_win *win,
935                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
936 {
937         struct tegra_dc_lut *lut = &win->lut;
938         struct tegra_dc_lut *global_lut = &dc->fb_lut;
939         int i;
940         for (i = 0; i < 256; i++) {
941
942                 u32 r = (u32)lut->r[i];
943                 u32 g = (u32)lut->g[i];
944                 u32 b = (u32)lut->b[i];
945
946                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
947                         r = (u32)global_lut->r[r];
948                         g = (u32)global_lut->g[g];
949                         b = (u32)global_lut->b[b];
950                 }
951
952                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
953                         return 0;
954         }
955         return 1;
956 }
957
958 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
959 {
960         if (rgb != (i | (i<<8) | (i<<16)))
961                 return 0;
962         return 1;
963 }
964
965 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
966 {
967         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
968         return 1;
969 }
970
971 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
972 {
973         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
974
975         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
976
977         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
978                 val |= CP_ENABLE;
979         else
980                 val &= ~CP_ENABLE;
981
982         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
983 }
984
985 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
986 {
987         struct tegra_dc_win *win = &dc->windows[win_idx];
988
989         mutex_lock(&dc->lock);
990
991         if (!dc->enabled) {
992                 mutex_unlock(&dc->lock);
993                 return -EFAULT;
994         }
995
996         if (fbovr > 0)
997                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
998         else if (fbovr == 0)
999                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
1000
1001         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
1002                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
1003         else
1004                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
1005
1006         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
1007                         DC_CMD_DISPLAY_WINDOW_HEADER);
1008
1009         tegra_dc_set_lut(dc, win);
1010
1011         mutex_unlock(&dc->lock);
1012
1013         tegra_dc_update_windows(&win, 1);
1014
1015         return 0;
1016 }
1017
1018 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
1019 {
1020         if (win_idx > -1)
1021                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
1022
1023         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
1024                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
1025                 if (err)
1026                         return err;
1027         }
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL(tegra_dc_update_lut);
1032
1033 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1034 {
1035         unsigned i;
1036         unsigned v0 = 128;
1037         unsigned v1 = 0;
1038         /* linear horizontal and vertical filters */
1039         for (i = 0; i < 16; i++) {
1040                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1041                                 DC_WIN_H_FILTER_P(i));
1042
1043                 tegra_dc_writel(dc, v0,
1044                                 DC_WIN_V_FILTER_P(i));
1045                 v0 -= 8;
1046                 v1 += 8;
1047         }
1048 }
1049
1050 #ifdef CONFIG_TEGRA_DC_CMU
1051 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
1052                                                 struct tegra_dc_cmu *src_cmu)
1053 {
1054         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
1055 }
1056
1057 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1058 {
1059         u32 val;
1060         u32 i;
1061
1062         for (i = 0; i < 256; i++) {
1063                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1064                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1065         }
1066
1067         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1068         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1069         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1070         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1071         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1072         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1073         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1074         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1075         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1076
1077         for (i = 0; i < 960; i++) {
1078                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1079                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1080         }
1081 }
1082
1083 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1084 {
1085         u32 val;
1086         u32 i;
1087         bool flags;
1088
1089         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1090         if (val & CMU_ENABLE)
1091                 flags = true;
1092
1093         val &= ~CMU_ENABLE;
1094         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1095         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1096         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1097
1098         /*TODO: Sync up with frame end */
1099         mdelay(20);
1100
1101         for (i = 0; i < 256; i++) {
1102                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
1103                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
1104                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
1105                 cmu->lut1[i] = LUT1_READ_DATA(val);
1106         }
1107
1108         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
1109         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
1110         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
1111         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
1112         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
1113         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
1114         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
1115         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
1116         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
1117
1118         for (i = 0; i < 960; i++) {
1119                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
1120                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
1121                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
1122                 cmu->lut2[i] = LUT2_READ_DATA(val);
1123         }
1124 }
1125
1126 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
1127 {
1128         mutex_lock(&dc->lock);
1129
1130         if (!dc->enabled) {
1131                 mutex_unlock(&dc->lock);
1132                 return -EFAULT;
1133         }
1134
1135         if (cmu_enable) {
1136                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
1137         } else {
1138                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
1139                 return 0;
1140         }
1141
1142         tegra_dc_set_cmu(dc, &dc->cmu);
1143
1144         mutex_unlock(&dc->lock);
1145
1146         return 0;
1147 }
1148 EXPORT_SYMBOL(tegra_dc_update_cmu);
1149 #else
1150 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
1151 #define tegra_dc_set_cmu(dc, cmu)
1152 #endif
1153
1154 void tegra_dc_host_suspend(struct tegra_dc *dc)
1155 {
1156         tegra_dsi_host_suspend(dc);
1157         tegra_dc_clk_disable(dc);
1158 }
1159
1160 void tegra_dc_host_resume(struct tegra_dc *dc) {
1161         tegra_dc_clk_enable(dc);
1162         tegra_dsi_host_resume(dc);
1163 }
1164
1165 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1166                                   bool v, unsigned Bpp)
1167 {
1168         /*
1169          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1170          *           (post_scaled_size_in_pixels - 1)), MAX)
1171          * Where the value of MAX is as follows:
1172          * For V_DDA_INCREMENT: 15.0 (0xF000)
1173          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1174          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1175          */
1176
1177         fixed20_12 out = dfixed_init(out_int);
1178         u32 dda_inc;
1179         int max;
1180
1181         if (v) {
1182                 max = 15;
1183         } else {
1184                 switch (Bpp) {
1185                 default:
1186                         WARN_ON_ONCE(1);
1187                         /* fallthrough */
1188                 case 4:
1189                         max = 4;
1190                         break;
1191                 case 2:
1192                         max = 8;
1193                         break;
1194                 }
1195         }
1196
1197         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1198         in.full -= dfixed_const(1);
1199
1200         dda_inc = dfixed_div(in, out);
1201
1202         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1203
1204         return dda_inc;
1205 }
1206
1207 static inline u32 compute_initial_dda(fixed20_12 in)
1208 {
1209         return dfixed_frac(in);
1210 }
1211
1212 /* does not support updating windows on multiple dcs in one call */
1213 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1214 {
1215         struct tegra_dc *dc;
1216         unsigned long update_mask = GENERAL_ACT_REQ;
1217         unsigned long val;
1218         bool update_gen1_blend = false;
1219         bool update_gen2_blend = false;
1220         int i;
1221
1222         dc = windows[0]->dc;
1223
1224         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1225                 /* Acquire one_shot_lock to avoid race condition between
1226                  * cancellation of old delayed work and schedule of new
1227                  * delayed work. */
1228                 mutex_lock(&dc->one_shot_lock);
1229                 cancel_delayed_work_sync(&dc->one_shot_work);
1230         }
1231         mutex_lock(&dc->lock);
1232
1233         if (!dc->enabled) {
1234                 mutex_unlock(&dc->lock);
1235                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1236                         mutex_unlock(&dc->one_shot_lock);
1237                 return -EFAULT;
1238         }
1239
1240         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1241                 tegra_dc_host_resume(dc);
1242
1243         if (no_vsync)
1244                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1245         else
1246                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1247
1248         for (i = 0; i < n; i++) {
1249                 struct tegra_dc_win *win = windows[i];
1250                 unsigned h_dda;
1251                 unsigned v_dda;
1252                 fixed20_12 h_offset, v_offset;
1253                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1254                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1255                 bool yuv = tegra_dc_is_yuv(win->fmt);
1256                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1257                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1258                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1259                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1260                 const bool filter_h = win_use_h_filter(dc, win);
1261                 const bool filter_v = win_use_v_filter(dc, win);
1262
1263                 if (win->z != dc->blend.z[win->idx]) {
1264                         dc->blend.z[win->idx] = win->z;
1265                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1266                                 update_gen2_blend = true;
1267                         else
1268                                 update_gen1_blend = true;
1269                 }
1270                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1271                         dc->blend.flags[win->idx]) {
1272                         dc->blend.flags[win->idx] =
1273                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1274                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1275                                 update_gen2_blend = true;
1276                         else
1277                                 update_gen1_blend = true;
1278                 }
1279
1280                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1281                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1282
1283                 if (!no_vsync)
1284                         update_mask |= WIN_A_ACT_REQ << win->idx;
1285
1286                 if (!WIN_IS_ENABLED(win)) {
1287                         dc->windows[i].dirty = 1;
1288                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1289                         continue;
1290                 }
1291
1292                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1293                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1294
1295                 tegra_dc_writel(dc,
1296                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1297                                 DC_WIN_POSITION);
1298                 tegra_dc_writel(dc,
1299                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1300                                 DC_WIN_SIZE);
1301
1302                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
1303                         tegra_dc_writel(dc,
1304                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1305                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1306                                         DC_WIN_PRESCALED_SIZE);
1307
1308                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1309                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1310                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1311                                         DC_WIN_DDA_INCREMENT);
1312                         h_dda = compute_initial_dda(win->x);
1313                         v_dda = compute_initial_dda(win->y);
1314                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1315                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1316                 }
1317
1318 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1319                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1320                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1321 #endif
1322                 tegra_dc_writel(dc,
1323                                 (unsigned long)win->phys_addr,
1324                                 DC_WINBUF_START_ADDR);
1325
1326                 if (!yuvp) {
1327                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1328                 } else {
1329                         tegra_dc_writel(dc,
1330                                         (unsigned long)win->phys_addr_u,
1331                                         DC_WINBUF_START_ADDR_U);
1332                         tegra_dc_writel(dc,
1333                                         (unsigned long)win->phys_addr_v,
1334                                         DC_WINBUF_START_ADDR_V);
1335                         tegra_dc_writel(dc,
1336                                         LINE_STRIDE(win->stride) |
1337                                         UV_LINE_STRIDE(win->stride_uv),
1338                                         DC_WIN_LINE_STRIDE);
1339                 }
1340
1341                 h_offset = win->x;
1342                 if (invert_h) {
1343                         h_offset.full += win->w.full - dfixed_const(1);
1344                 }
1345
1346                 v_offset = win->y;
1347                 if (invert_v) {
1348                         v_offset.full += win->h.full - dfixed_const(1);
1349                 }
1350
1351                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1352                                 DC_WINBUF_ADDR_H_OFFSET);
1353                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1354                                 DC_WINBUF_ADDR_V_OFFSET);
1355
1356                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1357                         if (WIN_IS_TILED(win))
1358                                 tegra_dc_writel(dc,
1359                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1360                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1361                                                 DC_WIN_BUFFER_ADDR_MODE);
1362                         else
1363                                 tegra_dc_writel(dc,
1364                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1365                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1366                                                 DC_WIN_BUFFER_ADDR_MODE);
1367                 }
1368
1369                 val = WIN_ENABLE;
1370                 if (yuv)
1371                         val |= CSC_ENABLE;
1372                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1373                         val |= COLOR_EXPAND;
1374
1375                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1376                         val |= CP_ENABLE;
1377
1378                 if (filter_h)
1379                         val |= H_FILTER_ENABLE;
1380                 if (filter_v)
1381                         val |= V_FILTER_ENABLE;
1382
1383                 if (invert_h)
1384                         val |= H_DIRECTION_DECREMENT;
1385                 if (invert_v)
1386                         val |= V_DIRECTION_DECREMENT;
1387
1388                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1389
1390 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1391                 if (win->global_alpha == 255)
1392                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1393                 else
1394                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1395                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1396 #endif
1397
1398                 win->dirty = no_vsync ? 0 : 1;
1399
1400                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1401                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1402                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1403                         __func__, win->idx, win->z,
1404                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1405                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1406                         win->out_x, win->out_y, win->out_w, win->out_h,
1407                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1408                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1409                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1410                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1411         }
1412
1413         if (update_gen1_blend || update_gen2_blend) {
1414                 if (update_gen1_blend)
1415                         tegra_dc_set_gen1_blending(dc, &dc->blend);
1416                 if (update_gen2_blend)
1417                         tegra_dc_set_gen2_blending(dc, &dc->blend);
1418                 for (i = 0; i < DC_N_WINDOWS; i++) {
1419                         if (!no_vsync)
1420                                 dc->windows[i].dirty = 1;
1421                         update_mask |= WIN_A_ACT_REQ << i;
1422                 }
1423         }
1424
1425         tegra_dc_set_dynamic_emc(windows, n);
1426
1427         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1428
1429         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1430         if (!no_vsync) {
1431                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1432                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1433         } else {
1434                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1435                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1436         }
1437
1438         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1439                 schedule_delayed_work(&dc->one_shot_work,
1440                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1441
1442         /* update EMC clock if calculated bandwidth has changed */
1443         tegra_dc_program_bandwidth(dc, false);
1444
1445         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1446                 update_mask |= NC_HOST_TRIG;
1447
1448         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1449         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1450
1451         mutex_unlock(&dc->lock);
1452         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1453                 mutex_unlock(&dc->one_shot_lock);
1454
1455         return 0;
1456 }
1457 EXPORT_SYMBOL(tegra_dc_update_windows);
1458
1459 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1460 {
1461         return dc->syncpt[i].id;
1462 }
1463 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1464
1465 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1466 {
1467         u32 max;
1468
1469         mutex_lock(&dc->lock);
1470         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1471                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1472         dc->syncpt[i].max = max;
1473         mutex_unlock(&dc->lock);
1474
1475         return max;
1476 }
1477
1478 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1479 {
1480         mutex_lock(&dc->lock);
1481         if ( dc->enabled )
1482                 while (dc->syncpt[i].min < val) {
1483                         dc->syncpt[i].min++;
1484                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1485                 }
1486         mutex_unlock(&dc->lock);
1487 }
1488
1489 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1490                                              int n)
1491 {
1492         int i;
1493
1494         for (i = 0; i < n; i++) {
1495                 if (windows[i]->dirty)
1496                         return false;
1497         }
1498
1499         return true;
1500 }
1501
1502 /* does not support syncing windows on multiple dcs in one call */
1503 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1504 {
1505         int ret;
1506         if (n < 1 || n > DC_N_WINDOWS)
1507                 return -EINVAL;
1508
1509         if (!windows[0]->dc->enabled)
1510                 return -EFAULT;
1511
1512 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
1513         /* Don't want to timeout on simulator */
1514         ret = wait_event_interruptible(windows[0]->dc->wq,
1515                 tegra_dc_windows_are_clean(windows, n));
1516 #else
1517         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1518                         windows[0]->dc->ndev->name);
1519         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1520                                          tegra_dc_windows_are_clean(windows, n),
1521                                          HZ);
1522         trace_printk("%s:After wait_event_interruptible_timeout\n",
1523                         windows[0]->dc->ndev->name);
1524 #endif
1525         return ret;
1526 }
1527 EXPORT_SYMBOL(tegra_dc_sync_windows);
1528
1529 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1530 {
1531 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1532         return clk_get_rate(dc->clk);
1533 #else
1534         return 27000000;
1535 #endif
1536 }
1537
1538 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1539 {
1540         unsigned long rate;
1541         unsigned long div;
1542
1543         rate = tegra_dc_clk_get_rate(dc);
1544
1545         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1546
1547         if (div < 2)
1548                 return 0;
1549
1550         return rate * 2 / div;
1551 }
1552
1553 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1554 {
1555         unsigned long rate;
1556         unsigned long div;
1557
1558         rate = clk_get_rate(parent);
1559
1560         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1561
1562         if (div < 2)
1563                 return 0;
1564
1565         return rate * 2 / div;
1566 }
1567
1568 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1569 {
1570         int pclk;
1571
1572         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1573                 unsigned long rate;
1574                 struct clk *parent_clk =
1575                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1576
1577                 if (dc->out->parent_clk_backup &&
1578                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1579                         rate = tegra_dc_pclk_predict_rate(
1580                                 parent_clk, dc->mode.pclk);
1581                         /* use pll_d as last resort */
1582                         if (rate < (dc->mode.pclk / 100 * 99) ||
1583                             rate > (dc->mode.pclk / 100 * 109))
1584                                 parent_clk = clk_get_sys(
1585                                         NULL, dc->out->parent_clk_backup);
1586                 }
1587
1588                 if (clk_get_parent(clk) != parent_clk)
1589                         clk_set_parent(clk, parent_clk);
1590
1591                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1592                         struct clk *base_clk = clk_get_parent(parent_clk);
1593
1594                         /* Assuming either pll_d or pll_d2 is used */
1595                         rate = dc->mode.pclk * 2;
1596
1597                         if (rate != clk_get_rate(base_clk))
1598                                 clk_set_rate(base_clk, rate);
1599                 }
1600         }
1601
1602         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1603                 unsigned long rate;
1604                 struct clk *parent_clk =
1605                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1606                 struct clk *base_clk = clk_get_parent(parent_clk);
1607
1608                 /*
1609                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1610                  * The required rate needs to be setup at 4x multiplier,
1611                  * as out0 is 1/2 of the actual PLL output.
1612                  */
1613
1614                 rate = dc->mode.pclk * 4;
1615                 if (rate != clk_get_rate(base_clk))
1616                         clk_set_rate(base_clk, rate);
1617
1618                 if (clk_get_parent(clk) != parent_clk)
1619                         clk_set_parent(clk, parent_clk);
1620         }
1621
1622         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1623                 unsigned long rate;
1624                 struct clk *parent_clk;
1625                 struct clk *base_clk;
1626
1627                 if (clk == dc->clk) {
1628                         parent_clk = clk_get_sys(NULL,
1629                                         dc->out->parent_clk ? : "pll_d_out0");
1630                         base_clk = clk_get_parent(parent_clk);
1631                         tegra_clk_cfg_ex(base_clk,
1632                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1633                 } else {
1634                         if (dc->pdata->default_out->dsi->dsi_instance) {
1635                                 parent_clk = clk_get_sys(NULL,
1636                                         dc->out->parent_clk ? : "pll_d2_out0");
1637                                 base_clk = clk_get_parent(parent_clk);
1638                                 tegra_clk_cfg_ex(base_clk,
1639                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1640                         } else {
1641                                 parent_clk = clk_get_sys(NULL,
1642                                         dc->out->parent_clk ? : "pll_d_out0");
1643                                 base_clk = clk_get_parent(parent_clk);
1644                                 tegra_clk_cfg_ex(base_clk,
1645                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1646                         }
1647                 }
1648
1649                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1650                 if (rate != clk_get_rate(base_clk))
1651                         clk_set_rate(base_clk, rate);
1652
1653                 if (clk_get_parent(clk) != parent_clk)
1654                         clk_set_parent(clk, parent_clk);
1655         }
1656
1657         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1658         tegra_dvfs_set_rate(clk, pclk);
1659 }
1660
1661 /* return non-zero if constraint is violated */
1662 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1663 {
1664         long a, b;
1665
1666         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1667         a = 0;
1668
1669         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1670         b = mode->h_front_porch - 1;
1671
1672         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1673         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1674                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1675         /* check Constraint 1 and 6 */
1676         if (a > b)
1677                 return 1;
1678
1679         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1680         if (mode->h_sync_width < 1)
1681                 return 4;
1682
1683         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1684         if (mode->h_active < 16)
1685                 return 7;
1686
1687         if (href) {
1688                 if (b > a && a % 2)
1689                         *href = a + 1; /* use smallest even value */
1690                 else
1691                         *href = a; /* even or only possible value */
1692         }
1693
1694         return 0;
1695 }
1696
1697 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1698 {
1699         long a;
1700         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1701
1702         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1703         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1704                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1705
1706         /* Constraint 6 */
1707         if (mode->v_front_porch < a + 1)
1708                 a = mode->v_front_porch - 1;
1709
1710         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1711         if (mode->v_sync_width < 1)
1712                 return 4;
1713
1714         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1715         if (mode->v_active < 16)
1716                 return 7;
1717
1718         if (vref)
1719                 *vref = a;
1720         return 0;
1721 }
1722
1723 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1724 {
1725         int ret;
1726         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1727         if (ret)
1728                 return ret;
1729         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1730         if (ret)
1731                 return ret;
1732
1733         return 0;
1734 }
1735
1736 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1737 {
1738         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1739         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1740                 return false;
1741
1742         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1743         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1744                 return false;
1745
1746         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1747          * (vertical blank). */
1748         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1749                 return false;
1750
1751         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1752         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1753                 return false;
1754
1755         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1756         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1757                 return false;
1758
1759         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1760          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1761         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1762                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1763                 return false;
1764
1765         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1766         if (mode->h_active < 16 || mode->v_active < 16)
1767                 return false;
1768
1769         return true;
1770 }
1771
1772 #ifdef DEBUG
1773 /* return in 1000ths of a Hertz */
1774 static int calc_refresh(const struct tegra_dc_mode *m)
1775 {
1776         long h_total, v_total, refresh;
1777         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1778                 m->h_sync_width;
1779         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1780                 m->v_sync_width;
1781         refresh = m->pclk / h_total;
1782         refresh *= 1000;
1783         refresh /= v_total;
1784         return refresh;
1785 }
1786
1787 static void print_mode(struct tegra_dc *dc,
1788                         const struct tegra_dc_mode *mode, const char *note)
1789 {
1790         if (mode) {
1791                 int refresh = calc_refresh(dc, mode);
1792                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1793                         note ? note : "",
1794                         mode->h_active, mode->v_active,
1795                         refresh / 1000, refresh % 1000,
1796                         mode->pclk);
1797         }
1798 }
1799 #else /* !DEBUG */
1800 static inline void print_mode(struct tegra_dc *dc,
1801                         const struct tegra_dc_mode *mode, const char *note) { }
1802 #endif /* DEBUG */
1803
1804 static inline void enable_dc_irq(unsigned int irq)
1805 {
1806 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1807         enable_irq(irq);
1808 #else
1809         /* Always disable DC interrupts on FPGA. */
1810         disable_irq(irq);
1811 #endif
1812 }
1813
1814 static inline void disable_dc_irq(unsigned int irq)
1815 {
1816         disable_irq(irq);
1817 }
1818
1819 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1820 {
1821         u32 val;
1822
1823         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1824         val |= int_val;
1825         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1826 }
1827
1828 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1829 {
1830         u32 val;
1831
1832         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1833         val &= ~int_val;
1834         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1835 }
1836
1837 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1838 {
1839         unsigned long val;
1840         unsigned long rate;
1841         unsigned long div;
1842         unsigned long pclk;
1843
1844         print_mode(dc, mode, __func__);
1845
1846         /* use default EMC rate when switching modes */
1847         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1848         tegra_dc_program_bandwidth(dc, true);
1849
1850         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1851         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1852                         DC_DISP_REF_TO_SYNC);
1853         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1854                         DC_DISP_SYNC_WIDTH);
1855         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1856                         DC_DISP_BACK_PORCH);
1857         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1858                         DC_DISP_DISP_ACTIVE);
1859         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1860                         DC_DISP_FRONT_PORCH);
1861
1862         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1863                         DC_DISP_DATA_ENABLE_OPTIONS);
1864
1865         /* TODO: MIPI/CRT/HDMI clock cals */
1866
1867         val = DISP_DATA_FORMAT_DF1P1C;
1868
1869         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1870                 val |= DISP_DATA_ALIGNMENT_MSB;
1871         else
1872                 val |= DISP_DATA_ALIGNMENT_LSB;
1873
1874         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1875                 val |= DISP_DATA_ORDER_RED_BLUE;
1876         else
1877                 val |= DISP_DATA_ORDER_BLUE_RED;
1878
1879         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1880
1881         rate = tegra_dc_clk_get_rate(dc);
1882
1883         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1884         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1885         if (pclk < (mode->pclk / 100 * 99) ||
1886             pclk > (mode->pclk / 100 * 109)) {
1887                 dev_err(&dc->ndev->dev,
1888                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1889                         rate, mode->pclk,
1890                         pclk, (mode->pclk / 100 * 99),
1891                         (mode->pclk / 100 * 109));
1892                 return -EINVAL;
1893         }
1894
1895         div = (rate * 2 / pclk) - 2;
1896         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1897
1898         tegra_dc_writel(dc, 0x00010001,
1899                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1900         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1901                         DC_DISP_DISP_CLOCK_CONTROL);
1902
1903 #ifdef CONFIG_SWITCH
1904         switch_set_state(&dc->modeset_switch,
1905                          (mode->h_active << 16) | mode->v_active);
1906 #endif
1907
1908         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1909         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1910
1911         print_mode_info(dc, dc->mode);
1912         return 0;
1913 }
1914
1915
1916 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1917 {
1918         memcpy(&dc->mode, mode, sizeof(dc->mode));
1919
1920         print_mode(dc, mode, __func__);
1921
1922         return 0;
1923 }
1924 EXPORT_SYMBOL(tegra_dc_set_mode);
1925
1926 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1927                 const struct fb_videomode *fbmode, bool stereo_mode)
1928 {
1929         struct tegra_dc_mode mode;
1930
1931         if (!fbmode->pixclock)
1932                 return -EINVAL;
1933
1934         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1935         mode.h_sync_width = fbmode->hsync_len;
1936         mode.v_sync_width = fbmode->vsync_len;
1937         mode.h_back_porch = fbmode->left_margin;
1938         mode.v_back_porch = fbmode->upper_margin;
1939         mode.h_active = fbmode->xres;
1940         mode.v_active = fbmode->yres;
1941         mode.h_front_porch = fbmode->right_margin;
1942         mode.v_front_porch = fbmode->lower_margin;
1943         mode.stereo_mode = stereo_mode;
1944         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1945                 /* HDMI controller requires h_ref=1, v_ref=1 */
1946                 mode.h_ref_to_sync = 1;
1947                 mode.v_ref_to_sync = 1;
1948         } else {
1949                 calc_ref_to_sync(&mode);
1950         }
1951         if (!check_ref_to_sync(&mode)) {
1952                 dev_err(&dc->ndev->dev,
1953                                 "Display timing doesn't meet restrictions.\n");
1954                 return -EINVAL;
1955         }
1956         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1957                 mode.h_active, mode.v_active, mode.pclk,
1958                 mode.h_ref_to_sync, mode.v_ref_to_sync
1959         );
1960
1961 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1962         /* Double the pixel clock and update v_active only for frame packed mode */
1963         if (mode.stereo_mode) {
1964                 mode.pclk *= 2;
1965                 /* total v_active = yres*2 + activespace */
1966                 mode.v_active = fbmode->yres*2 +
1967                                 fbmode->vsync_len +
1968                                 fbmode->upper_margin +
1969                                 fbmode->lower_margin;
1970         }
1971 #endif
1972
1973         mode.flags = 0;
1974
1975         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1976                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1977
1978         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1979                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1980
1981         return tegra_dc_set_mode(dc, &mode);
1982 }
1983 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1984
1985 void
1986 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1987 {
1988         unsigned int ctrl;
1989         unsigned long out_sel;
1990         unsigned long cmd_state;
1991
1992         mutex_lock(&dc->lock);
1993         if (!dc->enabled) {
1994                 mutex_unlock(&dc->lock);
1995                 return;
1996         }
1997
1998         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1999                 tegra_dc_host_resume(dc);
2000
2001         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
2002                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
2003                 cfg->clk_select);
2004
2005         /* The new value should be effected immediately */
2006         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
2007         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
2008
2009         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
2010                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
2011         else
2012                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
2013
2014         switch (cfg->which_pwm) {
2015         case TEGRA_PWM_PM0:
2016                 /* Select the LM0 on PM0 */
2017                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2018                 out_sel &= ~(7 << 0);
2019                 out_sel |= (3 << 0);
2020                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2021                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2022                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2023                 break;
2024         case TEGRA_PWM_PM1:
2025                 /* Select the LM1 on PM1 */
2026                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2027                 out_sel &= ~(7 << 4);
2028                 out_sel |= (3 << 4);
2029                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2030                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2031                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2032                 break;
2033         default:
2034                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2035                 break;
2036         }
2037         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2038         mutex_unlock(&dc->lock);
2039 }
2040 EXPORT_SYMBOL(tegra_dc_config_pwm);
2041
2042 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2043                                 const struct tegra_dc_out_pin *pins,
2044                                 const unsigned int n_pins)
2045 {
2046         unsigned int i;
2047
2048         int name;
2049         int pol;
2050
2051         u32 pol1, pol3;
2052
2053         u32 set1, unset1;
2054         u32 set3, unset3;
2055
2056         set1 = set3 = unset1 = unset3 = 0;
2057
2058         for (i = 0; i < n_pins; i++) {
2059                 name = (pins + i)->name;
2060                 pol  = (pins + i)->pol;
2061
2062                 /* set polarity by name */
2063                 switch (name) {
2064                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2065                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2066                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2067                         else
2068                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2069                         break;
2070                 case TEGRA_DC_OUT_PIN_H_SYNC:
2071                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2072                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2073                         else
2074                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2075                         break;
2076                 case TEGRA_DC_OUT_PIN_V_SYNC:
2077                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2078                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2079                         else
2080                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2081                         break;
2082                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2083                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2084                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2085                         else
2086                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2087                         break;
2088                 default:
2089                         printk("Invalid argument in function %s\n",
2090                                __FUNCTION__);
2091                         break;
2092                 }
2093         }
2094
2095         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2096         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2097
2098         pol1 |= set1;
2099         pol1 &= ~unset1;
2100
2101         pol3 |= set3;
2102         pol3 &= ~unset3;
2103
2104         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2105         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2106 }
2107
2108 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2109 {
2110         dc->out = out;
2111
2112         if (out->n_modes > 0)
2113                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2114
2115         switch (out->type) {
2116         case TEGRA_DC_OUT_RGB:
2117                 dc->out_ops = &tegra_dc_rgb_ops;
2118                 break;
2119
2120         case TEGRA_DC_OUT_HDMI:
2121                 dc->out_ops = &tegra_dc_hdmi_ops;
2122                 break;
2123
2124         case TEGRA_DC_OUT_DSI:
2125                 dc->out_ops = &tegra_dc_dsi_ops;
2126                 break;
2127
2128         default:
2129                 dc->out_ops = NULL;
2130                 break;
2131         }
2132
2133         if (dc->out_ops && dc->out_ops->init)
2134                 dc->out_ops->init(dc);
2135
2136 }
2137
2138 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2139 {
2140         if (dc->out)
2141                 return dc->out->height;
2142         else
2143                 return 0;
2144 }
2145 EXPORT_SYMBOL(tegra_dc_get_out_height);
2146
2147 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2148 {
2149         if (dc->out)
2150                 return dc->out->width;
2151         else
2152                 return 0;
2153 }
2154 EXPORT_SYMBOL(tegra_dc_get_out_width);
2155
2156 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2157 {
2158         if (dc->out && dc->out->max_pixclock)
2159                 return dc->out->max_pixclock;
2160         else
2161                 return 0;
2162 }
2163 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2164
2165 void tegra_dc_enable_crc(struct tegra_dc *dc)
2166 {
2167         u32 val;
2168         tegra_dc_io_start(dc);
2169
2170         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2171                 CRC_ENABLE_ENABLE;
2172         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2173         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2174         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2175 }
2176
2177 void tegra_dc_disable_crc(struct tegra_dc *dc)
2178 {
2179         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2180         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2181         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2182
2183         tegra_dc_io_end(dc);
2184 }
2185
2186 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2187 {
2188         int crc = 0;
2189
2190         if (!dc) {
2191                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2192                 goto crc_error;
2193         }
2194
2195 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2196         /* TODO: Replace mdelay with code to sync VBlANK, since
2197          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2198         mdelay(TEGRA_CRC_LATCHED_DELAY);
2199 #endif
2200
2201         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2202 crc_error:
2203         return crc;
2204 }
2205
2206 static void tegra_dc_vblank(struct work_struct *work)
2207 {
2208         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2209         bool nvsd_updated = false;
2210
2211         mutex_lock(&dc->lock);
2212
2213         if (!dc->enabled) {
2214                 mutex_unlock(&dc->lock);
2215                 return;
2216         }
2217
2218         /* use the new frame's bandwidth setting instead of max(current, new),
2219          * skip this if we're using tegra_dc_one_shot_worker() */
2220         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2221                 tegra_dc_program_bandwidth(dc, true);
2222
2223         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2224         if (!tegra_dc_windows_are_dirty(dc))
2225                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2226
2227         /* Update the SD brightness */
2228         if (dc->enabled && dc->out->sd_settings) {
2229                 nvsd_updated = nvsd_update_brightness(dc);
2230                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2231                  * V_BLANK_NVSD bit of vblank ref-count. */
2232                 if (nvsd_updated) {
2233                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2234                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2235                 } else {
2236                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2237                 }
2238         }
2239
2240         /* Mask vblank interrupt if ref-count is zero. */
2241         if (!dc->vblank_ref_count)
2242                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2243
2244         mutex_unlock(&dc->lock);
2245
2246         /* Do the actual brightness update outside of the mutex */
2247         if (nvsd_updated && dc->out->sd_settings &&
2248             dc->out->sd_settings->bl_device) {
2249
2250                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2251                 struct backlight_device *bl = platform_get_drvdata(pdev);
2252                 if (bl)
2253                         backlight_update_status(bl);
2254         }
2255 }
2256
2257 static void tegra_dc_one_shot_worker(struct work_struct *work)
2258 {
2259         struct tegra_dc *dc = container_of(
2260                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2261         mutex_lock(&dc->lock);
2262
2263         /* memory client has gone idle */
2264         tegra_dc_clear_bandwidth(dc);
2265
2266         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2267                 tegra_dc_host_suspend(dc);
2268
2269         mutex_unlock(&dc->lock);
2270 }
2271
2272 /* return an arbitrarily large number if count overflow occurs.
2273  * make it a nice base-10 number to show up in stats output */
2274 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2275 {
2276         unsigned count = tegra_dc_readl(dc, reg);
2277         tegra_dc_writel(dc, 0, reg);
2278         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2279 }
2280
2281 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2282 {
2283         u32 val;
2284         int i;
2285
2286         dc->stats.underflows++;
2287         if (dc->underflow_mask & WIN_A_UF_INT) {
2288                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2289                         DC_WINBUF_AD_UFLOW_STATUS);
2290                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2291         }
2292         if (dc->underflow_mask & WIN_B_UF_INT) {
2293                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2294                         DC_WINBUF_BD_UFLOW_STATUS);
2295                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2296         }
2297         if (dc->underflow_mask & WIN_C_UF_INT) {
2298                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2299                         DC_WINBUF_CD_UFLOW_STATUS);
2300                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2301         }
2302
2303         /* Check for any underflow reset conditions */
2304         for (i = 0; i < DC_N_WINDOWS; i++) {
2305                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2306                         dc->windows[i].underflows++;
2307
2308 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2309                         if (dc->windows[i].underflows > 4) {
2310                                 schedule_work(&dc->reset_work);
2311                                 /* reset counter */
2312                                 dc->windows[i].underflows = 0;
2313                                 trace_printk("%s:Reset work scheduled for "
2314                                                 "window %c\n",
2315                                                 dc->ndev->name, (65 + i));
2316                         }
2317 #endif
2318 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2319                         if (dc->windows[i].underflows > 4) {
2320                                 printk("%s:dc in underflow state."
2321                                         " enable UF_LINE_FLUSH to clear up\n",
2322                                         __func__);
2323                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2324                                                 DC_DISP_DISP_MISC_CONTROL);
2325                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2326                                                 DC_CMD_STATE_CONTROL);
2327                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2328                                                 DC_CMD_STATE_CONTROL);
2329
2330                                 tegra_dc_writel(dc, 0,
2331                                                 DC_DISP_DISP_MISC_CONTROL);
2332                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2333                                                 DC_CMD_STATE_CONTROL);
2334                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2335                                                 DC_CMD_STATE_CONTROL);
2336                         }
2337 #endif
2338                 } else {
2339                         dc->windows[i].underflows = 0;
2340                 }
2341         }
2342
2343         /* Clear the underflow mask now that we've checked it. */
2344         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2345         dc->underflow_mask = 0;
2346         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2347         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2348         print_underflow_info(dc);
2349 }
2350
2351 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2352 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2353 {
2354 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2355         u32 val;
2356
2357         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2358         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
2359             return true;
2360 #endif
2361         return false;
2362 }
2363
2364 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2365 {
2366         u32 val, i;
2367         u32 completed = 0;
2368         u32 dirty = 0;
2369
2370         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2371         for (i = 0; i < DC_N_WINDOWS; i++) {
2372 #ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
2373                 /* FIXME: this is not needed when the simulator
2374                    clears WIN_x_UPDATE bits as in HW */
2375                 dc->windows[i].dirty = 0;
2376                 completed = 1;
2377 #else
2378                 if (!(val & (WIN_A_ACT_REQ << i))) {
2379                         dc->windows[i].dirty = 0;
2380                         completed = 1;
2381                 } else {
2382                         dirty = 1;
2383                 }
2384 #endif
2385         }
2386
2387         if (!dirty) {
2388                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2389                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2390         }
2391
2392         if (completed)
2393                 wake_up(&dc->wq);
2394 }
2395
2396 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2397 {
2398         if (status & V_BLANK_INT) {
2399                 /* Sync up windows. */
2400                 tegra_dc_trigger_windows(dc);
2401
2402                 /* Schedule any additional bottom-half vblank actvities. */
2403                 schedule_work(&dc->vblank_work);
2404         }
2405
2406         if (status & FRAME_END_INT) {
2407                 /* Mark the frame_end as complete. */
2408                 if (!completion_done(&dc->frame_end_complete))
2409                         complete(&dc->frame_end_complete);
2410         }
2411 }
2412
2413 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2414 {
2415         /* Schedule any additional bottom-half vblank actvities. */
2416         if (status & V_BLANK_INT)
2417                 schedule_work(&dc->vblank_work);
2418
2419         if (status & FRAME_END_INT) {
2420                 /* Mark the frame_end as complete. */
2421                 if (!completion_done(&dc->frame_end_complete))
2422                         complete(&dc->frame_end_complete);
2423
2424                 tegra_dc_trigger_windows(dc);
2425         }
2426 }
2427 #endif
2428
2429 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2430 {
2431 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2432         struct tegra_dc *dc = ptr;
2433         unsigned long status;
2434         unsigned long underflow_mask;
2435         u32 val;
2436
2437         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
2438                 WARN(1, "IRQ when DC not powered!\n");
2439                 tegra_dc_io_start(dc);
2440                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2441                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2442                 tegra_dc_io_end(dc);
2443                 return IRQ_HANDLED;
2444         }
2445
2446         /* clear all status flags except underflow, save those for the worker */
2447         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2448         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2449         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2450         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2451
2452         /*
2453          * Overlays can get thier internal state corrupted during and underflow
2454          * condition.  The only way to fix this state is to reset the DC.
2455          * if we get 4 consecutive frames with underflows, assume we're
2456          * hosed and reset.
2457          */
2458         underflow_mask = status & ALL_UF_INT;
2459
2460         /* Check underflow */
2461         if (underflow_mask) {
2462                 dc->underflow_mask |= underflow_mask;
2463                 schedule_delayed_work(&dc->underflow_work,
2464                         msecs_to_jiffies(1));
2465         }
2466
2467         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2468                 tegra_dc_one_shot_irq(dc, status);
2469         else
2470                 tegra_dc_continuous_irq(dc, status);
2471
2472         return IRQ_HANDLED;
2473 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2474         return IRQ_NONE;
2475 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2476 }
2477
2478 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2479 {
2480         u32 color_control;
2481
2482         switch (dc->out->depth) {
2483         case 3:
2484                 color_control = BASE_COLOR_SIZE111;
2485                 break;
2486
2487         case 6:
2488                 color_control = BASE_COLOR_SIZE222;
2489                 break;
2490
2491         case 8:
2492                 color_control = BASE_COLOR_SIZE332;
2493                 break;
2494
2495         case 9:
2496                 color_control = BASE_COLOR_SIZE333;
2497                 break;
2498
2499         case 12:
2500                 color_control = BASE_COLOR_SIZE444;
2501                 break;
2502
2503         case 15:
2504                 color_control = BASE_COLOR_SIZE555;
2505                 break;
2506
2507         case 16:
2508                 color_control = BASE_COLOR_SIZE565;
2509                 break;
2510
2511         case 18:
2512                 color_control = BASE_COLOR_SIZE666;
2513                 break;
2514
2515         default:
2516                 color_control = BASE_COLOR_SIZE888;
2517                 break;
2518         }
2519
2520         switch (dc->out->dither) {
2521         case TEGRA_DC_DISABLE_DITHER:
2522                 color_control |= DITHER_CONTROL_DISABLE;
2523                 break;
2524         case TEGRA_DC_ORDERED_DITHER:
2525                 color_control |= DITHER_CONTROL_ORDERED;
2526                 break;
2527         case TEGRA_DC_ERRDIFF_DITHER:
2528                 /* The line buffer for error-diffusion dither is limited
2529                  * to 1280 pixels per line. This limits the maximum
2530                  * horizontal active area size to 1280 pixels when error
2531                  * diffusion is enabled.
2532                  */
2533                 BUG_ON(dc->mode.h_active > 1280);
2534                 color_control |= DITHER_CONTROL_ERRDIFF;
2535                 break;
2536         }
2537
2538 #ifdef CONFIG_TEGRA_DC_CMU
2539         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
2540                 color_control |= CMU_ENABLE;
2541 #endif
2542
2543         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2544 }
2545
2546 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2547 {
2548         u32 syncpt_id;
2549
2550         switch (dc->ndev->id) {
2551         case 0:
2552                 switch (idx) {
2553                 case 0:
2554                         syncpt_id = NVSYNCPT_DISP0_A;
2555                         break;
2556                 case 1:
2557                         syncpt_id = NVSYNCPT_DISP0_B;
2558                         break;
2559                 case 2:
2560                         syncpt_id = NVSYNCPT_DISP0_C;
2561                         break;
2562                 default:
2563                         BUG();
2564                         break;
2565                 }
2566                 break;
2567         case 1:
2568                 switch (idx) {
2569                 case 0:
2570                         syncpt_id = NVSYNCPT_DISP1_A;
2571                         break;
2572                 case 1:
2573                         syncpt_id = NVSYNCPT_DISP1_B;
2574                         break;
2575                 case 2:
2576                         syncpt_id = NVSYNCPT_DISP1_C;
2577                         break;
2578                 default:
2579                         BUG();
2580                         break;
2581                 }
2582                 break;
2583         default:
2584                 BUG();
2585                 break;
2586         }
2587
2588         return syncpt_id;
2589 }
2590
2591 static int tegra_dc_init(struct tegra_dc *dc)
2592 {
2593         int i;
2594
2595         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2596         if (dc->ndev->id == 0) {
2597                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2598                                       TEGRA_MC_PRIO_MED);
2599                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2600                                       TEGRA_MC_PRIO_MED);
2601                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2602                                       TEGRA_MC_PRIO_MED);
2603                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2604                                       TEGRA_MC_PRIO_MED);
2605                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2606                                       TEGRA_MC_PRIO_HIGH);
2607         } else if (dc->ndev->id == 1) {
2608                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2609                                       TEGRA_MC_PRIO_MED);
2610                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2611                                       TEGRA_MC_PRIO_MED);
2612                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2613                                       TEGRA_MC_PRIO_MED);
2614                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2615                                       TEGRA_MC_PRIO_MED);
2616                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2617                                       TEGRA_MC_PRIO_HIGH);
2618         }
2619         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2620                         DC_CMD_CONT_SYNCPT_VSYNC);
2621         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2622         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2623         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2624         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2625 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2626         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2627 #endif
2628         /* enable interrupts for vblank, frame_end and underflows */
2629         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2630                 DC_CMD_INT_ENABLE);
2631         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2632
2633         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2634
2635         tegra_dc_set_color_control(dc);
2636         for (i = 0; i < DC_N_WINDOWS; i++) {
2637                 struct tegra_dc_win *win = &dc->windows[i];
2638                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2639                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2640                 tegra_dc_set_csc(dc, &win->csc);
2641                 tegra_dc_set_lut(dc, win);
2642                 tegra_dc_set_scaling_filter(dc);
2643         }
2644
2645         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
2646         tegra_dc_set_cmu(dc, &dc->cmu);
2647
2648         for (i = 0; i < dc->n_windows; i++) {
2649                 u32 syncpt = get_syncpt(dc, i);
2650
2651                 dc->syncpt[i].id = syncpt;
2652
2653                 dc->syncpt[i].min = dc->syncpt[i].max =
2654                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
2655         }
2656
2657         print_mode(dc, &dc->mode, __func__);
2658
2659         if (dc->mode.pclk)
2660                 if (tegra_dc_program_mode(dc, &dc->mode))
2661                         return -EINVAL;
2662
2663         /* Initialize SD AFTER the modeset.
2664            nvsd_init handles the sd_settings = NULL case. */
2665         nvsd_init(dc, dc->out->sd_settings);
2666
2667         return 0;
2668 }
2669
2670 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2671 {
2672         int failed_init = 0;
2673
2674         if (dc->out->enable)
2675                 dc->out->enable();
2676
2677         tegra_dc_setup_clk(dc, dc->clk);
2678         tegra_dc_clk_enable(dc);
2679
2680         /* do not accept interrupts during initialization */
2681         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2682         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2683
2684         enable_dc_irq(dc->irq);
2685
2686         failed_init = tegra_dc_init(dc);
2687         if (failed_init) {
2688                 _tegra_dc_controller_disable(dc);
2689                 return false;
2690         }
2691
2692         if (dc->out_ops && dc->out_ops->enable)
2693                 dc->out_ops->enable(dc);
2694
2695         if (dc->out->postpoweron)
2696                 dc->out->postpoweron();
2697
2698         /* force a full blending update */
2699         dc->blend.z[0] = -1;
2700
2701         tegra_dc_ext_enable(dc->ext);
2702
2703         trace_printk("%s:enable\n", dc->ndev->name);
2704         return true;
2705 }
2706
2707 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2708 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2709 {
2710         bool ret = true;
2711
2712         if (dc->out->enable)
2713                 dc->out->enable();
2714
2715         tegra_dc_setup_clk(dc, dc->clk);
2716         tegra_dc_clk_enable(dc);
2717
2718         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2719                 mutex_lock(&tegra_dcs[1]->lock);
2720                 disable_irq(tegra_dcs[1]->irq);
2721         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2722                 mutex_lock(&tegra_dcs[0]->lock);
2723                 disable_irq(tegra_dcs[0]->irq);
2724         }
2725
2726         msleep(5);
2727         tegra_periph_reset_assert(dc->clk);
2728         msleep(2);
2729 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2730         tegra_periph_reset_deassert(dc->clk);
2731         msleep(1);
2732 #endif
2733
2734         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2735                 enable_dc_irq(tegra_dcs[1]->irq);
2736                 mutex_unlock(&tegra_dcs[1]->lock);
2737         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2738                 enable_dc_irq(tegra_dcs[0]->irq);
2739                 mutex_unlock(&tegra_dcs[0]->lock);
2740         }
2741
2742         enable_dc_irq(dc->irq);
2743
2744         if (tegra_dc_init(dc)) {
2745                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2746                 ret = false;
2747         }
2748
2749         if (dc->out_ops && dc->out_ops->enable)
2750                 dc->out_ops->enable(dc);
2751
2752         if (dc->out->postpoweron)
2753                 dc->out->postpoweron();
2754
2755         /* force a full blending update */
2756         dc->blend.z[0] = -1;
2757
2758         tegra_dc_ext_enable(dc->ext);
2759
2760         if (!ret) {
2761                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2762                 _tegra_dc_controller_disable(dc);
2763         }
2764
2765         trace_printk("%s:reset enable\n", dc->ndev->name);
2766         return ret;
2767 }
2768 #endif
2769
2770 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2771 {
2772         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2773 }
2774
2775 static bool _tegra_dc_enable(struct tegra_dc *dc)
2776 {
2777         if (dc->mode.pclk == 0) {
2778                 switch (dc->out->type) {
2779                 case TEGRA_DC_OUT_HDMI:
2780                 /* DC enable called but no videomode is loaded.
2781                      Check if HDMI is connected, then set fallback mdoe */
2782                 if (tegra_dc_hpd(dc)) {
2783                         if (_tegra_dc_set_default_videomode(dc))
2784                                 return false;
2785                 } else
2786                         return false;
2787
2788                 break;
2789
2790                 /* Do nothing for other outputs for now */
2791                 case TEGRA_DC_OUT_RGB:
2792
2793                 case TEGRA_DC_OUT_DSI:
2794
2795                 default:
2796                         return false;
2797                 }
2798         }
2799
2800         if (!dc->out)
2801                 return false;
2802
2803         tegra_dc_io_start(dc);
2804
2805         return _tegra_dc_controller_enable(dc);
2806 }
2807
2808 void tegra_dc_enable(struct tegra_dc *dc)
2809 {
2810         mutex_lock(&dc->lock);
2811
2812         if (!dc->enabled)
2813                 dc->enabled = _tegra_dc_enable(dc);
2814
2815         mutex_unlock(&dc->lock);
2816         print_mode_info(dc, dc->mode);
2817 }
2818
2819 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2820 {
2821         unsigned i;
2822
2823         if (dc->out && dc->out->prepoweroff)
2824                 dc->out->prepoweroff();
2825
2826         if (dc->out_ops && dc->out_ops->disable)
2827                 dc->out_ops->disable(dc);
2828
2829         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2830         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2831         disable_irq(dc->irq);
2832
2833         tegra_dc_clear_bandwidth(dc);
2834         tegra_dc_clk_disable(dc);
2835
2836         if (dc->out && dc->out->disable)
2837                 dc->out->disable();
2838
2839         for (i = 0; i < dc->n_windows; i++) {
2840                 struct tegra_dc_win *w = &dc->windows[i];
2841
2842                 /* reset window bandwidth */
2843                 w->bandwidth = 0;
2844                 w->new_bandwidth = 0;
2845
2846                 /* disable windows */
2847                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2848
2849                 /* flush any pending syncpt waits */
2850                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2851                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2852                                 dc->syncpt[i].id);
2853                         dc->syncpt[i].min++;
2854                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2855                 }
2856         }
2857         trace_printk("%s:disabled\n", dc->ndev->name);
2858 }
2859
2860 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2861 {
2862 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2863         u32 val;
2864         if (dc->enabled)  {
2865                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2866                 if (enable)
2867                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2868                 else
2869                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2870                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2871         }
2872 #endif
2873 }
2874
2875 bool tegra_dc_stats_get(struct tegra_dc *dc)
2876 {
2877 #if 0 /* right now it is always enabled */
2878         u32 val;
2879         bool res;
2880
2881         if (dc->enabled)  {
2882                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2883                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2884         } else {
2885                 res = false;
2886         }
2887
2888         return res;
2889 #endif
2890         return true;
2891 }
2892
2893 /* make the screen blank by disabling all windows */
2894 void tegra_dc_blank(struct tegra_dc *dc)
2895 {
2896         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2897         unsigned i;
2898
2899         for (i = 0; i < DC_N_WINDOWS; i++) {
2900                 dcwins[i] = tegra_dc_get_window(dc, i);
2901                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2902         }
2903
2904         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2905         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2906 }
2907
2908 static void _tegra_dc_disable(struct tegra_dc *dc)
2909 {
2910         _tegra_dc_controller_disable(dc);
2911         tegra_dc_io_end(dc);
2912 }
2913
2914 void tegra_dc_disable(struct tegra_dc *dc)
2915 {
2916         tegra_dc_ext_disable(dc->ext);
2917
2918         /* it's important that new underflow work isn't scheduled before the
2919          * lock is acquired. */
2920         cancel_delayed_work_sync(&dc->underflow_work);
2921         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2922                 mutex_lock(&dc->one_shot_lock);
2923                 cancel_delayed_work_sync(&dc->one_shot_work);
2924         }
2925
2926         mutex_lock(&dc->lock);
2927
2928         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2929                 tegra_dc_host_resume(dc);
2930
2931         if (dc->enabled) {
2932                 dc->enabled = false;
2933
2934                 if (!dc->suspended)
2935                         _tegra_dc_disable(dc);
2936         }
2937
2938 #ifdef CONFIG_SWITCH
2939         switch_set_state(&dc->modeset_switch, 0);
2940 #endif
2941
2942         mutex_unlock(&dc->lock);
2943         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2944                 mutex_unlock(&dc->one_shot_lock);
2945         print_mode_info(dc, dc->mode);
2946 }
2947
2948 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2949 static void tegra_dc_reset_worker(struct work_struct *work)
2950 {
2951         struct tegra_dc *dc =
2952                 container_of(work, struct tegra_dc, reset_work);
2953
2954         unsigned long val = 0;
2955
2956         mutex_lock(&shared_lock);
2957
2958         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2959
2960         tegra_dc_ext_disable(dc->ext);
2961
2962         mutex_lock(&dc->lock);
2963
2964         if (dc->enabled == false)
2965                 goto unlock;
2966
2967         dc->enabled = false;
2968
2969         /*
2970          * off host read bus
2971          */
2972         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2973         val &= ~(0x00000100);
2974         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2975
2976         /*
2977          * set DC to STOP mode
2978          */
2979         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2980
2981         msleep(10);
2982
2983         _tegra_dc_controller_disable(dc);
2984
2985         /* _tegra_dc_controller_reset_enable deasserts reset */
2986         _tegra_dc_controller_reset_enable(dc);
2987
2988         dc->enabled = true;
2989
2990         /* reopen host read bus */
2991         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2992         val &= ~(0x00000100);
2993         val |= 0x100;
2994         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2995
2996 unlock:
2997         mutex_unlock(&dc->lock);
2998         mutex_unlock(&shared_lock);
2999         trace_printk("%s:reset complete\n", dc->ndev->name);
3000 }
3001 #endif
3002
3003 static void tegra_dc_underflow_worker(struct work_struct *work)
3004 {
3005         struct tegra_dc *dc = container_of(
3006                 to_delayed_work(work), struct tegra_dc, underflow_work);
3007
3008         mutex_lock(&dc->lock);
3009         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
3010                 tegra_dc_host_resume(dc);
3011
3012         if (dc->enabled) {
3013                 tegra_dc_underflow_handler(dc);
3014         }
3015         mutex_unlock(&dc->lock);
3016 }
3017
3018 #ifdef CONFIG_SWITCH
3019 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
3020 {
3021         struct tegra_dc *dc =
3022                 container_of(sdev, struct tegra_dc, modeset_switch);
3023
3024         if (!sdev->state)
3025                 return sprintf(buf, "offline\n");
3026
3027         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
3028 }
3029 #endif
3030
3031 static int tegra_dc_probe(struct nvhost_device *ndev,
3032         struct nvhost_device_id *id_table)
3033 {
3034         struct tegra_dc *dc;
3035         struct clk *clk;
3036         struct clk *emc_clk;
3037         struct resource *res;
3038         struct resource *base_res;
3039         struct resource *fb_mem = NULL;
3040         int ret = 0;
3041         void __iomem *base;
3042         int irq;
3043         int i;
3044
3045         if (!ndev->dev.platform_data) {
3046                 dev_err(&ndev->dev, "no platform data\n");
3047                 return -ENOENT;
3048         }
3049
3050         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3051         if (!dc) {
3052                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3053                 return -ENOMEM;
3054         }
3055
3056         irq = nvhost_get_irq_byname(ndev, "irq");
3057         if (irq <= 0) {
3058                 dev_err(&ndev->dev, "no irq\n");
3059                 ret = -ENOENT;
3060                 goto err_free;
3061         }
3062
3063         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
3064         if (!res) {
3065                 dev_err(&ndev->dev, "no mem resource\n");
3066                 ret = -ENOENT;
3067                 goto err_free;
3068         }
3069
3070         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
3071         if (!base_res) {
3072                 dev_err(&ndev->dev, "request_mem_region failed\n");
3073                 ret = -EBUSY;
3074                 goto err_free;
3075         }
3076
3077         base = ioremap(res->start, resource_size(res));
3078         if (!base) {
3079                 dev_err(&ndev->dev, "registers can't be mapped\n");
3080                 ret = -EBUSY;
3081                 goto err_release_resource_reg;
3082         }
3083
3084         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
3085
3086         clk = clk_get(&ndev->dev, NULL);
3087         if (IS_ERR_OR_NULL(clk)) {
3088                 dev_err(&ndev->dev, "can't get clock\n");
3089                 ret = -ENOENT;
3090                 goto err_iounmap_reg;
3091         }
3092
3093         emc_clk = clk_get(&ndev->dev, "emc");
3094         if (IS_ERR_OR_NULL(emc_clk)) {
3095                 dev_err(&ndev->dev, "can't get emc clock\n");
3096                 ret = -ENOENT;
3097                 goto err_put_clk;
3098         }
3099
3100         dc->clk = clk;
3101         dc->emc_clk = emc_clk;
3102         dc->shift_clk_div = 1;
3103         /* Initialize one shot work delay, it will be assigned by dsi
3104          * according to refresh rate later. */
3105         dc->one_shot_delay_ms = 40;
3106
3107         dc->base_res = base_res;
3108         dc->base = base;
3109         dc->irq = irq;
3110         dc->ndev = ndev;
3111         dc->pdata = ndev->dev.platform_data;
3112
3113         /*
3114          * The emc is a shared clock, it will be set based on
3115          * the requirements for each user on the bus.
3116          */
3117         dc->emc_clk_rate = 0;
3118
3119         mutex_init(&dc->lock);
3120         mutex_init(&dc->one_shot_lock);
3121         init_completion(&dc->frame_end_complete);
3122         init_waitqueue_head(&dc->wq);
3123 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3124         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3125 #endif
3126         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3127         dc->vblank_ref_count = 0;
3128         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3129         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3130
3131         tegra_dc_init_lut_defaults(&dc->fb_lut);
3132
3133         dc->n_windows = DC_N_WINDOWS;
3134         for (i = 0; i < dc->n_windows; i++) {
3135                 struct tegra_dc_win *win = &dc->windows[i];
3136                 win->idx = i;
3137                 win->dc = dc;
3138                 tegra_dc_init_csc_defaults(&win->csc);
3139                 tegra_dc_init_lut_defaults(&win->lut);
3140         }
3141
3142         ret = tegra_dc_set(dc, ndev->id);
3143         if (ret < 0) {
3144                 dev_err(&ndev->dev, "can't add dc\n");
3145                 goto err_free_irq;
3146         }
3147
3148         nvhost_set_drvdata(ndev, dc);
3149
3150 #ifdef CONFIG_SWITCH
3151         dc->modeset_switch.name = dev_name(&ndev->dev);
3152         dc->modeset_switch.state = 0;
3153         dc->modeset_switch.print_state = switch_modeset_print_mode;
3154         switch_dev_register(&dc->modeset_switch);
3155 #endif
3156
3157         tegra_dc_feature_register(dc);
3158
3159         if (dc->pdata->default_out)
3160                 tegra_dc_set_out(dc, dc->pdata->default_out);
3161         else
3162                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3163
3164         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3165                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3166
3167         dc->ext = tegra_dc_ext_register(ndev, dc);
3168         if (IS_ERR_OR_NULL(dc->ext)) {
3169                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3170                 dc->ext = NULL;
3171         }
3172
3173         mutex_lock(&dc->lock);
3174         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
3175                 dc->enabled = _tegra_dc_enable(dc);
3176         mutex_unlock(&dc->lock);
3177
3178         /* interrupt handler must be registered before tegra_fb_register() */
3179         if (request_irq(irq, tegra_dc_irq, 0,
3180                         dev_name(&ndev->dev), dc)) {
3181                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3182                 ret = -EBUSY;
3183                 goto err_put_emc_clk;
3184         }
3185
3186         tegra_dc_create_debugfs(dc);
3187
3188         dev_info(&ndev->dev, "probed\n");
3189
3190         if (dc->pdata->fb) {
3191                 if (dc->pdata->fb->bits_per_pixel == -1) {
3192                         unsigned long fmt;
3193                         tegra_dc_writel(dc,
3194                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3195                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3196
3197                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3198                         dc->pdata->fb->bits_per_pixel =
3199                                 tegra_dc_fmt_bpp(fmt);
3200                 }
3201
3202                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3203                 if (IS_ERR_OR_NULL(dc->fb))
3204                         dc->fb = NULL;
3205         }
3206
3207         if (dc->out && dc->out->hotplug_init)
3208                 dc->out->hotplug_init();
3209
3210         if (dc->out_ops && dc->out_ops->detect)
3211                 dc->out_ops->detect(dc);
3212         else
3213                 dc->connected = true;
3214
3215         tegra_dc_create_sysfs(&dc->ndev->dev);
3216
3217         return 0;
3218
3219 err_free_irq:
3220         free_irq(irq, dc);
3221 err_put_emc_clk:
3222         clk_put(emc_clk);
3223 err_put_clk:
3224         clk_put(clk);
3225 err_iounmap_reg:
3226         iounmap(base);
3227         if (fb_mem)
3228                 release_resource(fb_mem);
3229 err_release_resource_reg:
3230         release_resource(base_res);
3231 err_free:
3232         kfree(dc);
3233
3234         return ret;
3235 }
3236
3237 static int tegra_dc_remove(struct nvhost_device *ndev)
3238 {
3239         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3240
3241         tegra_dc_remove_sysfs(&dc->ndev->dev);
3242         tegra_dc_remove_debugfs(dc);
3243
3244         if (dc->fb) {
3245                 tegra_fb_unregister(dc->fb);
3246                 if (dc->fb_mem)
3247                         release_resource(dc->fb_mem);
3248         }
3249
3250         tegra_dc_ext_disable(dc->ext);
3251
3252         if (dc->ext)
3253                 tegra_dc_ext_unregister(dc->ext);
3254
3255         if (dc->enabled)
3256                 _tegra_dc_disable(dc);
3257
3258 #ifdef CONFIG_SWITCH
3259         switch_dev_unregister(&dc->modeset_switch);
3260 #endif
3261         free_irq(dc->irq, dc);
3262         clk_put(dc->emc_clk);
3263         clk_put(dc->clk);
3264         iounmap(dc->base);
3265         if (dc->fb_mem)
3266                 release_resource(dc->base_res);
3267         kfree(dc);
3268         tegra_dc_set(NULL, ndev->id);
3269         return 0;
3270 }
3271
3272 #ifdef CONFIG_PM
3273 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3274 {
3275         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3276
3277         trace_printk("%s:suspend\n", dc->ndev->name);
3278         dev_info(&ndev->dev, "suspend\n");
3279
3280         tegra_dc_ext_disable(dc->ext);
3281
3282         mutex_lock(&dc->lock);
3283
3284         if (dc->out_ops && dc->out_ops->suspend)
3285                 dc->out_ops->suspend(dc);
3286
3287         if (dc->enabled) {
3288                 _tegra_dc_disable(dc);
3289
3290                 dc->suspended = true;
3291         }
3292
3293         if (dc->out && dc->out->postsuspend) {
3294                 dc->out->postsuspend();
3295                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3296                         /*
3297                          * avoid resume event due to voltage falling
3298                          */
3299                         msleep(100);
3300         }
3301
3302         mutex_unlock(&dc->lock);
3303
3304         return 0;
3305 }
3306
3307 static int tegra_dc_resume(struct nvhost_device *ndev)
3308 {
3309         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3310
3311         trace_printk("%s:resume\n", dc->ndev->name);
3312         dev_info(&ndev->dev, "resume\n");
3313
3314         mutex_lock(&dc->lock);
3315         dc->suspended = false;
3316
3317         if (dc->enabled)
3318                 _tegra_dc_enable(dc);
3319
3320         if (dc->out && dc->out->hotplug_init)
3321                 dc->out->hotplug_init();
3322
3323         if (dc->out_ops && dc->out_ops->resume)
3324                 dc->out_ops->resume(dc);
3325         mutex_unlock(&dc->lock);
3326
3327         return 0;
3328 }
3329
3330 #endif /* CONFIG_PM */
3331
3332 static void tegra_dc_shutdown(struct nvhost_device *ndev)
3333 {
3334         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3335
3336         if (!dc || !dc->enabled)
3337                 return;
3338
3339         tegra_dc_blank(dc);
3340         tegra_dc_disable(dc);
3341 }
3342
3343 extern int suspend_set(const char *val, struct kernel_param *kp)
3344 {
3345         if (!strcmp(val, "dump"))
3346                 dump_regs(tegra_dcs[0]);
3347 #ifdef CONFIG_PM
3348         else if (!strcmp(val, "suspend"))
3349                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3350         else if (!strcmp(val, "resume"))
3351                 tegra_dc_resume(tegra_dcs[0]->ndev);
3352 #endif
3353
3354         return 0;
3355 }
3356
3357 extern int suspend_get(char *buffer, struct kernel_param *kp)
3358 {
3359         return 0;
3360 }
3361
3362 int suspend;
3363
3364 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3365
3366 struct nvhost_driver tegra_dc_driver = {
3367         .driver = {
3368                 .name = "tegradc",
3369                 .owner = THIS_MODULE,
3370         },
3371         .probe = tegra_dc_probe,
3372         .remove = tegra_dc_remove,
3373 #ifdef CONFIG_PM
3374         .suspend = tegra_dc_suspend,
3375         .resume = tegra_dc_resume,
3376 #endif
3377         .shutdown = tegra_dc_shutdown,
3378 };
3379
3380 static int __init tegra_dc_module_init(void)
3381 {
3382         int ret = tegra_dc_ext_module_init();
3383         if (ret)
3384                 return ret;
3385         return nvhost_driver_register(&tegra_dc_driver);
3386 }
3387
3388 static void __exit tegra_dc_module_exit(void)
3389 {
3390         nvhost_driver_unregister(&tegra_dc_driver);
3391         tegra_dc_ext_module_exit();
3392 }
3393
3394 module_exit(tegra_dc_module_exit);
3395 module_init(tegra_dc_module_init);