video: tegra: dc: fix the clock-gate for suspend.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 /* A mutex used to protect the critical section used by both DC heads. */
67 static struct mutex status_lock;
68
69 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static struct tegra_dc_mode override_disp_mode[3];
85
86 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
87
88 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
89
90 DEFINE_MUTEX(tegra_dc_lock);
91 DEFINE_MUTEX(shared_lock);
92
93 static const struct {
94         bool h;
95         bool v;
96 } can_filter[] = {
97         /* Window A has no filtering */
98         { false, false },
99         /* Window B has both H and V filtering */
100         { true,  true  },
101         /* Window C has only H filtering */
102         { false, true  },
103 };
104
105 #ifdef CONFIG_TEGRA_DC_CMU
106 static struct tegra_dc_cmu default_cmu = {
107         /* lut1 maps sRGB to linear space. */
108         {
109                 0,    1,    2,    4,    5,    6,    7,    9,
110                 10,   11,   12,   14,   15,   16,   18,   20,
111                 21,   23,   25,   27,   29,   31,   33,   35,
112                 37,   40,   42,   45,   48,   50,   53,   56,
113                 59,   62,   66,   69,   72,   76,   79,   83,
114                 87,   91,   95,   99,   103,  107,  112,  116,
115                 121,  126,  131,  136,  141,  146,  151,  156,
116                 162,  168,  173,  179,  185,  191,  197,  204,
117                 210,  216,  223,  230,  237,  244,  251,  258,
118                 265,  273,  280,  288,  296,  304,  312,  320,
119                 329,  337,  346,  354,  363,  372,  381,  390,
120                 400,  409,  419,  428,  438,  448,  458,  469,
121                 479,  490,  500,  511,  522,  533,  544,  555,
122                 567,  578,  590,  602,  614,  626,  639,  651,
123                 664,  676,  689,  702,  715,  728,  742,  755,
124                 769,  783,  797,  811,  825,  840,  854,  869,
125                 884,  899,  914,  929,  945,  960,  976,  992,
126                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
127                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
128                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
129                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
130                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
131                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
132                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
133                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
134                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
135                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
136                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
137                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
138                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
139                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
140                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
141         },
142         /* csc */
143         {
144                 0x100, 0x0,   0x0,
145                 0x0,   0x100, 0x0,
146                 0x0,   0x0,   0x100,
147         },
148         /* lut2 maps linear space to sRGB*/
149         {
150                 0,    1,    2,    2,    3,    4,    5,    6,
151                 6,    7,    8,    9,    10,   10,   11,   12,
152                 13,   13,   14,   15,   15,   16,   16,   17,
153                 18,   18,   19,   19,   20,   20,   21,   21,
154                 22,   22,   23,   23,   23,   24,   24,   25,
155                 25,   25,   26,   26,   27,   27,   27,   28,
156                 28,   29,   29,   29,   30,   30,   30,   31,
157                 31,   31,   32,   32,   32,   33,   33,   33,
158                 34,   34,   34,   34,   35,   35,   35,   36,
159                 36,   36,   37,   37,   37,   37,   38,   38,
160                 38,   38,   39,   39,   39,   40,   40,   40,
161                 40,   41,   41,   41,   41,   42,   42,   42,
162                 42,   43,   43,   43,   43,   43,   44,   44,
163                 44,   44,   45,   45,   45,   45,   46,   46,
164                 46,   46,   46,   47,   47,   47,   47,   48,
165                 48,   48,   48,   48,   49,   49,   49,   49,
166                 49,   50,   50,   50,   50,   50,   51,   51,
167                 51,   51,   51,   52,   52,   52,   52,   52,
168                 53,   53,   53,   53,   53,   54,   54,   54,
169                 54,   54,   55,   55,   55,   55,   55,   55,
170                 56,   56,   56,   56,   56,   57,   57,   57,
171                 57,   57,   57,   58,   58,   58,   58,   58,
172                 58,   59,   59,   59,   59,   59,   59,   60,
173                 60,   60,   60,   60,   60,   61,   61,   61,
174                 61,   61,   61,   62,   62,   62,   62,   62,
175                 62,   63,   63,   63,   63,   63,   63,   64,
176                 64,   64,   64,   64,   64,   64,   65,   65,
177                 65,   65,   65,   65,   66,   66,   66,   66,
178                 66,   66,   66,   67,   67,   67,   67,   67,
179                 67,   67,   68,   68,   68,   68,   68,   68,
180                 68,   69,   69,   69,   69,   69,   69,   69,
181                 70,   70,   70,   70,   70,   70,   70,   71,
182                 71,   71,   71,   71,   71,   71,   72,   72,
183                 72,   72,   72,   72,   72,   72,   73,   73,
184                 73,   73,   73,   73,   73,   74,   74,   74,
185                 74,   74,   74,   74,   74,   75,   75,   75,
186                 75,   75,   75,   75,   75,   76,   76,   76,
187                 76,   76,   76,   76,   77,   77,   77,   77,
188                 77,   77,   77,   77,   78,   78,   78,   78,
189                 78,   78,   78,   78,   78,   79,   79,   79,
190                 79,   79,   79,   79,   79,   80,   80,   80,
191                 80,   80,   80,   80,   80,   81,   81,   81,
192                 81,   81,   81,   81,   81,   81,   82,   82,
193                 82,   82,   82,   82,   82,   82,   83,   83,
194                 83,   83,   83,   83,   83,   83,   83,   84,
195                 84,   84,   84,   84,   84,   84,   84,   84,
196                 85,   85,   85,   85,   85,   85,   85,   85,
197                 85,   86,   86,   86,   86,   86,   86,   86,
198                 86,   86,   87,   87,   87,   87,   87,   87,
199                 87,   87,   87,   88,   88,   88,   88,   88,
200                 88,   88,   88,   88,   88,   89,   89,   89,
201                 89,   89,   89,   89,   89,   89,   90,   90,
202                 90,   90,   90,   90,   90,   90,   90,   90,
203                 91,   91,   91,   91,   91,   91,   91,   91,
204                 91,   91,   92,   92,   92,   92,   92,   92,
205                 92,   92,   92,   92,   93,   93,   93,   93,
206                 93,   93,   93,   93,   93,   93,   94,   94,
207                 94,   94,   94,   94,   94,   94,   94,   94,
208                 95,   95,   95,   95,   95,   95,   95,   95,
209                 95,   95,   96,   96,   96,   96,   96,   96,
210                 96,   96,   96,   96,   96,   97,   97,   97,
211                 97,   97,   97,   97,   97,   97,   97,   98,
212                 98,   98,   98,   98,   98,   98,   98,   98,
213                 98,   98,   99,   99,   99,   99,   99,   99,
214                 99,   100,  101,  101,  102,  103,  103,  104,
215                 105,  105,  106,  107,  107,  108,  109,  109,
216                 110,  111,  111,  112,  113,  113,  114,  115,
217                 115,  116,  116,  117,  118,  118,  119,  119,
218                 120,  120,  121,  122,  122,  123,  123,  124,
219                 124,  125,  126,  126,  127,  127,  128,  128,
220                 129,  129,  130,  130,  131,  131,  132,  132,
221                 133,  133,  134,  134,  135,  135,  136,  136,
222                 137,  137,  138,  138,  139,  139,  140,  140,
223                 141,  141,  142,  142,  143,  143,  144,  144,
224                 145,  145,  145,  146,  146,  147,  147,  148,
225                 148,  149,  149,  150,  150,  150,  151,  151,
226                 152,  152,  153,  153,  153,  154,  154,  155,
227                 155,  156,  156,  156,  157,  157,  158,  158,
228                 158,  159,  159,  160,  160,  160,  161,  161,
229                 162,  162,  162,  163,  163,  164,  164,  164,
230                 165,  165,  166,  166,  166,  167,  167,  167,
231                 168,  168,  169,  169,  169,  170,  170,  170,
232                 171,  171,  172,  172,  172,  173,  173,  173,
233                 174,  174,  174,  175,  175,  176,  176,  176,
234                 177,  177,  177,  178,  178,  178,  179,  179,
235                 179,  180,  180,  180,  181,  181,  182,  182,
236                 182,  183,  183,  183,  184,  184,  184,  185,
237                 185,  185,  186,  186,  186,  187,  187,  187,
238                 188,  188,  188,  189,  189,  189,  189,  190,
239                 190,  190,  191,  191,  191,  192,  192,  192,
240                 193,  193,  193,  194,  194,  194,  195,  195,
241                 195,  196,  196,  196,  196,  197,  197,  197,
242                 198,  198,  198,  199,  199,  199,  200,  200,
243                 200,  200,  201,  201,  201,  202,  202,  202,
244                 202,  203,  203,  203,  204,  204,  204,  205,
245                 205,  205,  205,  206,  206,  206,  207,  207,
246                 207,  207,  208,  208,  208,  209,  209,  209,
247                 209,  210,  210,  210,  211,  211,  211,  211,
248                 212,  212,  212,  213,  213,  213,  213,  214,
249                 214,  214,  214,  215,  215,  215,  216,  216,
250                 216,  216,  217,  217,  217,  217,  218,  218,
251                 218,  219,  219,  219,  219,  220,  220,  220,
252                 220,  221,  221,  221,  221,  222,  222,  222,
253                 223,  223,  223,  223,  224,  224,  224,  224,
254                 225,  225,  225,  225,  226,  226,  226,  226,
255                 227,  227,  227,  227,  228,  228,  228,  228,
256                 229,  229,  229,  229,  230,  230,  230,  230,
257                 231,  231,  231,  231,  232,  232,  232,  232,
258                 233,  233,  233,  233,  234,  234,  234,  234,
259                 235,  235,  235,  235,  236,  236,  236,  236,
260                 237,  237,  237,  237,  238,  238,  238,  238,
261                 239,  239,  239,  239,  240,  240,  240,  240,
262                 240,  241,  241,  241,  241,  242,  242,  242,
263                 242,  243,  243,  243,  243,  244,  244,  244,
264                 244,  244,  245,  245,  245,  245,  246,  246,
265                 246,  246,  247,  247,  247,  247,  247,  248,
266                 248,  248,  248,  249,  249,  249,  249,  249,
267                 250,  250,  250,  250,  251,  251,  251,  251,
268                 251,  252,  252,  252,  252,  253,  253,  253,
269                 253,  253,  254,  254,  254,  254,  255,  255,
270         },
271 };
272 #endif
273
274 void tegra_dc_clk_enable(struct tegra_dc *dc)
275 {
276         if (!tegra_is_clk_enabled(dc->clk)) {
277                 clk_prepare_enable(dc->clk);
278                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
279         }
280 }
281
282 void tegra_dc_clk_disable(struct tegra_dc *dc)
283 {
284         if (tegra_is_clk_enabled(dc->clk)) {
285                 clk_disable_unprepare(dc->clk);
286                 tegra_dvfs_set_rate(dc->clk, 0);
287         }
288 }
289
290 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
291 {
292         if (dc->out_ops->hold)
293                 dc->out_ops->hold(dc);
294 }
295
296 void tegra_dc_release_dc_out(struct tegra_dc *dc)
297 {
298         if (dc->out_ops->release)
299                 dc->out_ops->release(dc);
300 }
301
302 #define DUMP_REG(a) do {                        \
303         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
304                  #a, a, tegra_dc_readl(dc, a));               \
305         print(data, buff);                                    \
306         } while (0)
307
308 static void _dump_regs(struct tegra_dc *dc, void *data,
309                        void (* print)(void *data, const char *str))
310 {
311         int i;
312         char buff[256];
313
314         mutex_lock(&dc->lock);
315         tegra_dc_io_start(dc);
316         tegra_dc_hold_dc_out(dc);
317
318         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
319         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
320         DUMP_REG(DC_CMD_SIGNAL_RAISE);
321         DUMP_REG(DC_CMD_INT_STATUS);
322         DUMP_REG(DC_CMD_INT_MASK);
323         DUMP_REG(DC_CMD_INT_ENABLE);
324         DUMP_REG(DC_CMD_INT_TYPE);
325         DUMP_REG(DC_CMD_INT_POLARITY);
326         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
327         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
328         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
329         DUMP_REG(DC_CMD_STATE_ACCESS);
330         DUMP_REG(DC_CMD_STATE_CONTROL);
331         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
332         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
333
334         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
335         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
336         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
337         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
338         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
339         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
340         DUMP_REG(DC_DISP_REF_TO_SYNC);
341         DUMP_REG(DC_DISP_SYNC_WIDTH);
342         DUMP_REG(DC_DISP_BACK_PORCH);
343         DUMP_REG(DC_DISP_DISP_ACTIVE);
344         DUMP_REG(DC_DISP_FRONT_PORCH);
345         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
347         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
348         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
349         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
350         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
352         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
353         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
354         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
355         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
357         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
358         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
359         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
360         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
367         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
368         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
369         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
370         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
371         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
372         DUMP_REG(DC_DISP_M0_CONTROL);
373         DUMP_REG(DC_DISP_M1_CONTROL);
374         DUMP_REG(DC_DISP_DI_CONTROL);
375         DUMP_REG(DC_DISP_PP_CONTROL);
376         DUMP_REG(DC_DISP_PP_SELECT_A);
377         DUMP_REG(DC_DISP_PP_SELECT_B);
378         DUMP_REG(DC_DISP_PP_SELECT_C);
379         DUMP_REG(DC_DISP_PP_SELECT_D);
380         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
381         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
382         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
383         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
384         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
385         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
386         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
387         DUMP_REG(DC_DISP_BORDER_COLOR);
388         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
389         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
390         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
391         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
392         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
393         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
394         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
395         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
396         DUMP_REG(DC_DISP_CURSOR_POSITION);
397         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
398         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
400         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
401         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
402         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
403         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
406         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
407 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
408         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
409 #endif
410         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
411         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
412
413
414         for (i = 0; i < 3; i++) {
415                 print(data, "\n");
416                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
417                 print(data, buff);
418
419                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
420                                 DC_CMD_DISPLAY_WINDOW_HEADER);
421                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
422                 DUMP_REG(DC_WIN_WIN_OPTIONS);
423                 DUMP_REG(DC_WIN_BYTE_SWAP);
424                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
425                 DUMP_REG(DC_WIN_COLOR_DEPTH);
426                 DUMP_REG(DC_WIN_POSITION);
427                 DUMP_REG(DC_WIN_SIZE);
428                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
429                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
430                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
431                 DUMP_REG(DC_WIN_DDA_INCREMENT);
432                 DUMP_REG(DC_WIN_LINE_STRIDE);
433 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
434                 DUMP_REG(DC_WIN_BUF_STRIDE);
435                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
436 #endif
437                 DUMP_REG(DC_WIN_BLEND_NOKEY);
438                 DUMP_REG(DC_WIN_BLEND_1WIN);
439                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
440                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
441                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
442                 DUMP_REG(DC_WINBUF_START_ADDR);
443                 DUMP_REG(DC_WINBUF_START_ADDR_U);
444                 DUMP_REG(DC_WINBUF_START_ADDR_V);
445                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
446                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
447                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
448                 DUMP_REG(DC_WIN_CSC_YOF);
449                 DUMP_REG(DC_WIN_CSC_KYRGB);
450                 DUMP_REG(DC_WIN_CSC_KUR);
451                 DUMP_REG(DC_WIN_CSC_KVR);
452                 DUMP_REG(DC_WIN_CSC_KUG);
453                 DUMP_REG(DC_WIN_CSC_KVG);
454                 DUMP_REG(DC_WIN_CSC_KUB);
455                 DUMP_REG(DC_WIN_CSC_KVB);
456         }
457
458         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
459         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
461         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
462         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
463         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
464         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
465         DUMP_REG(DC_DISP_M1_CONTROL);
466         DUMP_REG(DC_COM_PM1_CONTROL);
467         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
468         DUMP_REG(DC_DISP_SD_CONTROL);
469 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
470         DUMP_REG(DC_COM_CMU_CSC_KRR);
471         DUMP_REG(DC_COM_CMU_CSC_KGR);
472         DUMP_REG(DC_COM_CMU_CSC_KBR);
473         DUMP_REG(DC_COM_CMU_CSC_KRG);
474         DUMP_REG(DC_COM_CMU_CSC_KGG);
475         DUMP_REG(DC_COM_CMU_CSC_KBR);
476         DUMP_REG(DC_COM_CMU_CSC_KRB);
477         DUMP_REG(DC_COM_CMU_CSC_KGB);
478         DUMP_REG(DC_COM_CMU_CSC_KBB);
479 #endif
480
481         tegra_dc_release_dc_out(dc);
482         tegra_dc_io_end(dc);
483         mutex_unlock(&dc->lock);
484 }
485
486 #undef DUMP_REG
487
488 #ifdef DEBUG
489 static void dump_regs_print(void *data, const char *str)
490 {
491         struct tegra_dc *dc = data;
492         dev_dbg(&dc->ndev->dev, "%s", str);
493 }
494
495 static void dump_regs(struct tegra_dc *dc)
496 {
497         _dump_regs(dc, dc, dump_regs_print);
498 }
499 #else /* !DEBUG */
500
501 static void dump_regs(struct tegra_dc *dc) {}
502
503 #endif /* DEBUG */
504
505 #ifdef CONFIG_DEBUG_FS
506
507 static void dbg_regs_print(void *data, const char *str)
508 {
509         struct seq_file *s = data;
510
511         seq_printf(s, "%s", str);
512 }
513
514 #undef DUMP_REG
515
516 static int dbg_dc_show(struct seq_file *s, void *unused)
517 {
518         struct tegra_dc *dc = s->private;
519
520         _dump_regs(dc, s, dbg_regs_print);
521
522         return 0;
523 }
524
525
526 static int dbg_dc_open(struct inode *inode, struct file *file)
527 {
528         return single_open(file, dbg_dc_show, inode->i_private);
529 }
530
531 static const struct file_operations regs_fops = {
532         .open           = dbg_dc_open,
533         .read           = seq_read,
534         .llseek         = seq_lseek,
535         .release        = single_release,
536 };
537
538 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
539 {
540         struct tegra_dc *dc = s->private;
541         struct tegra_dc_mode *m;
542
543         mutex_lock(&dc->lock);
544         m = &dc->mode;
545         seq_printf(s,
546                 "pclk: %d\n"
547                 "h_ref_to_sync: %d\n"
548                 "v_ref_to_sync: %d\n"
549                 "h_sync_width: %d\n"
550                 "v_sync_width: %d\n"
551                 "h_back_porch: %d\n"
552                 "v_back_porch: %d\n"
553                 "h_active: %d\n"
554                 "v_active: %d\n"
555                 "h_front_porch: %d\n"
556                 "v_front_porch: %d\n"
557                 "stereo_mode: %d\n",
558                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
559                 m->h_sync_width, m->v_sync_width,
560                 m->h_back_porch, m->v_back_porch,
561                 m->h_active, m->v_active,
562                 m->h_front_porch, m->v_front_porch,
563                 m->stereo_mode);
564         mutex_unlock(&dc->lock);
565         return 0;
566 }
567
568 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
569 {
570         return single_open(file, dbg_dc_mode_show, inode->i_private);
571 }
572
573 static const struct file_operations mode_fops = {
574         .open           = dbg_dc_mode_open,
575         .read           = seq_read,
576         .llseek         = seq_lseek,
577         .release        = single_release,
578 };
579
580 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
581 {
582         struct tegra_dc *dc = s->private;
583
584         mutex_lock(&dc->lock);
585         seq_printf(s,
586                 "underflows: %llu\n"
587                 "underflows_a: %llu\n"
588                 "underflows_b: %llu\n"
589                 "underflows_c: %llu\n",
590                 dc->stats.underflows,
591                 dc->stats.underflows_a,
592                 dc->stats.underflows_b,
593                 dc->stats.underflows_c);
594         mutex_unlock(&dc->lock);
595
596         return 0;
597 }
598
599 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
600 {
601         return single_open(file, dbg_dc_stats_show, inode->i_private);
602 }
603
604 static const struct file_operations stats_fops = {
605         .open           = dbg_dc_stats_open,
606         .read           = seq_read,
607         .llseek         = seq_lseek,
608         .release        = single_release,
609 };
610
611 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
612 {
613         if (dc->debugdir)
614                 debugfs_remove_recursive(dc->debugdir);
615         dc->debugdir = NULL;
616 }
617
618 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
619 {
620         struct dentry *retval;
621
622         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
623         if (!dc->debugdir)
624                 goto remove_out;
625
626         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
627                 &regs_fops);
628         if (!retval)
629                 goto remove_out;
630
631         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
632                 &mode_fops);
633         if (!retval)
634                 goto remove_out;
635
636         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
637                 &stats_fops);
638         if (!retval)
639                 goto remove_out;
640
641         return;
642 remove_out:
643         dev_err(&dc->ndev->dev, "could not create debugfs\n");
644         tegra_dc_remove_debugfs(dc);
645 }
646
647 #else /* !CONFIG_DEBUGFS */
648 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
649 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
650 #endif /* CONFIG_DEBUGFS */
651
652 static int tegra_dc_set(struct tegra_dc *dc, int index)
653 {
654         int ret = 0;
655
656         mutex_lock(&tegra_dc_lock);
657         if (index >= TEGRA_MAX_DC) {
658                 ret = -EINVAL;
659                 goto out;
660         }
661
662         if (dc != NULL && tegra_dcs[index] != NULL) {
663                 ret = -EBUSY;
664                 goto out;
665         }
666
667         tegra_dcs[index] = dc;
668
669 out:
670         mutex_unlock(&tegra_dc_lock);
671
672         return ret;
673 }
674
675 unsigned int tegra_dc_has_multiple_dc(void)
676 {
677         unsigned int idx;
678         unsigned int cnt = 0;
679         struct tegra_dc *dc;
680
681         mutex_lock(&tegra_dc_lock);
682         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
683                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
684         mutex_unlock(&tegra_dc_lock);
685
686         return (cnt > 1);
687 }
688
689 /* get the stride size of a window.
690  * return: stride size in bytes for window win. or 0 if unavailble. */
691 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
692 {
693         u32 stride;
694
695         if (!dc->enabled)
696                 return 0;
697         BUG_ON(win > DC_N_WINDOWS);
698         mutex_lock(&dc->lock);
699         tegra_dc_io_start(dc);
700         tegra_dc_hold_dc_out(dc);
701         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
702                 DC_CMD_DISPLAY_WINDOW_HEADER);
703         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
704         tegra_dc_release_dc_out(dc);
705         tegra_dc_io_end(dc);
706         mutex_unlock(&dc->lock);
707         return GET_LINE_STRIDE(stride);
708 }
709 EXPORT_SYMBOL(tegra_dc_get_stride);
710
711 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
712 {
713         if (idx < TEGRA_MAX_DC)
714                 return tegra_dcs[idx];
715         else
716                 return NULL;
717 }
718 EXPORT_SYMBOL(tegra_dc_get_dc);
719
720 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
721 {
722         if (win >= dc->n_windows)
723                 return NULL;
724
725         return &dc->windows[win];
726 }
727 EXPORT_SYMBOL(tegra_dc_get_window);
728
729 bool tegra_dc_get_connected(struct tegra_dc *dc)
730 {
731         return dc->connected;
732 }
733 EXPORT_SYMBOL(tegra_dc_get_connected);
734
735 bool tegra_dc_hpd(struct tegra_dc *dc)
736 {
737         int sense;
738         int level;
739
740         level = gpio_get_value(dc->out->hotplug_gpio);
741
742         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
743
744         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
745                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
746 }
747 EXPORT_SYMBOL(tegra_dc_hpd);
748
749 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
750 {
751         unsigned i;
752         unsigned v0 = 128;
753         unsigned v1 = 0;
754
755         /* linear horizontal and vertical filters */
756         for (i = 0; i < 16; i++) {
757                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
758                                 DC_WIN_H_FILTER_P(i));
759
760                 tegra_dc_writel(dc, v0,
761                                 DC_WIN_V_FILTER_P(i));
762                 v0 -= 8;
763                 v1 += 8;
764         }
765 }
766
767 #ifdef CONFIG_TEGRA_DC_CMU
768 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
769                                         struct tegra_dc_cmu *src_cmu)
770 {
771         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
772 }
773
774 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
775 {
776         u32 val;
777         u32 i;
778
779         for (i = 0; i < 256; i++) {
780                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
781                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
782         }
783
784         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
785         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
786         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
787         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
788         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
789         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
790         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
791         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
792         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
793
794         for (i = 0; i < 960; i++) {
795                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
796                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
797         }
798 }
799
800 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
801 {
802         u32 val;
803         u32 i;
804         bool flags;
805
806         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
807         if (val & CMU_ENABLE)
808                 flags = true;
809
810         val &= ~CMU_ENABLE;
811         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
812         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
813         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
814
815         /*TODO: Sync up with frame end */
816         mdelay(20);
817
818         for (i = 0; i < 256; i++) {
819                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
820                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
821                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
822                 cmu->lut1[i] = LUT1_READ_DATA(val);
823         }
824
825         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
826         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
827         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
828         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
829         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
830         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
831         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
832         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
833         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
834
835         for (i = 0; i < 960; i++) {
836                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
837                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
838                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
839                 cmu->lut2[i] = LUT2_READ_DATA(val);
840         }
841 }
842 EXPORT_SYMBOL(tegra_dc_get_cmu);
843
844 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
845 {
846         u32 val;
847
848         if (dc->pdata->cmu_enable) {
849                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
850         } else {
851                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
852                 return 0;
853         }
854
855         if (cmu != &dc->cmu) {
856                 tegra_dc_cache_cmu(&dc->cmu, cmu);
857
858                 /* Disable CMU */
859                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
860                 if (val & CMU_ENABLE) {
861                         val &= ~CMU_ENABLE;
862                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
863                         val = GENERAL_UPDATE;
864                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
865                         val = GENERAL_ACT_REQ;
866                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
867                         /*TODO: Sync up with vsync */
868                         mdelay(20);
869                 }
870
871                 tegra_dc_set_cmu(dc, &dc->cmu);
872         }
873
874         return 0;
875 }
876
877 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
878 {
879         int ret;
880
881         mutex_lock(&dc->lock);
882         tegra_dc_io_start(dc);
883         tegra_dc_hold_dc_out(dc);
884
885         ret = _tegra_dc_update_cmu(dc, cmu);
886         tegra_dc_set_color_control(dc);
887
888         tegra_dc_release_dc_out(dc);
889         tegra_dc_io_end(dc);
890         mutex_unlock(&dc->lock);
891
892         return ret;
893 }
894 EXPORT_SYMBOL(tegra_dc_update_cmu);
895
896 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
897 {
898         dc->pdata->cmu_enable = cmu_enable;
899         tegra_dc_update_cmu(dc, &dc->cmu);
900 }
901 #else
902 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
903 #define tegra_dc_set_cmu(dc, cmu)
904 #define tegra_dc_update_cmu(dc, cmu)
905 #endif
906
907 /* disable_irq() blocks until handler completes, calling this function while
908  * holding dc->lock can deadlock. */
909 static inline void disable_dc_irq(const struct tegra_dc *dc)
910 {
911         disable_irq(dc->irq);
912 }
913
914 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
915 {
916         return dc->syncpt[i].id;
917 }
918 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
919
920 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
921 {
922         u32 max;
923
924         mutex_lock(&dc->lock);
925         tegra_dc_io_start(dc);
926         tegra_dc_hold_dc_out(dc);
927         max = nvhost_syncpt_incr_max_ext(dc->ndev,
928                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
929         dc->syncpt[i].max = max;
930         tegra_dc_release_dc_out(dc);
931         tegra_dc_io_end(dc);
932         mutex_unlock(&dc->lock);
933
934         return max;
935 }
936
937 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
938 {
939         mutex_lock(&dc->lock);
940         if (dc->enabled) {
941                 tegra_dc_io_start(dc);
942                 tegra_dc_hold_dc_out(dc);
943                 while (dc->syncpt[i].min < val) {
944                         dc->syncpt[i].min++;
945                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
946                 }
947                 tegra_dc_release_dc_out(dc);
948                 tegra_dc_io_end(dc);
949         }
950         mutex_unlock(&dc->lock);
951 }
952
953 void
954 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
955 {
956         unsigned int ctrl;
957         unsigned long out_sel;
958         unsigned long cmd_state;
959
960         mutex_lock(&dc->lock);
961         if (!dc->enabled) {
962                 mutex_unlock(&dc->lock);
963                 return;
964         }
965
966         tegra_dc_io_start(dc);
967         tegra_dc_hold_dc_out(dc);
968
969         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
970                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
971                 cfg->clk_select);
972
973         /* The new value should be effected immediately */
974         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
975         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
976
977         switch (cfg->which_pwm) {
978         case TEGRA_PWM_PM0:
979                 /* Select the LM0 on PM0 */
980                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
981                 out_sel &= ~(7 << 0);
982                 out_sel |= (3 << 0);
983                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
984                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
985                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
986                 break;
987         case TEGRA_PWM_PM1:
988                 /* Select the LM1 on PM1 */
989                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
990                 out_sel &= ~(7 << 4);
991                 out_sel |= (3 << 4);
992                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
993                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
994                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
995                 break;
996         default:
997                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
998                 break;
999         }
1000         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1001         tegra_dc_release_dc_out(dc);
1002         tegra_dc_io_end(dc);
1003         mutex_unlock(&dc->lock);
1004 }
1005 EXPORT_SYMBOL(tegra_dc_config_pwm);
1006
1007 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1008                                 const struct tegra_dc_out_pin *pins,
1009                                 const unsigned int n_pins)
1010 {
1011         unsigned int i;
1012
1013         int name;
1014         int pol;
1015
1016         u32 pol1, pol3;
1017
1018         u32 set1, unset1;
1019         u32 set3, unset3;
1020
1021         set1 = set3 = unset1 = unset3 = 0;
1022
1023         for (i = 0; i < n_pins; i++) {
1024                 name = (pins + i)->name;
1025                 pol  = (pins + i)->pol;
1026
1027                 /* set polarity by name */
1028                 switch (name) {
1029                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1030                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1031                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1032                         else
1033                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1034                         break;
1035                 case TEGRA_DC_OUT_PIN_H_SYNC:
1036                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1037                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1038                         else
1039                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1040                         break;
1041                 case TEGRA_DC_OUT_PIN_V_SYNC:
1042                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1043                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1044                         else
1045                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1046                         break;
1047                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1048                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1049                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1050                         else
1051                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1052                         break;
1053                 default:
1054                         printk("Invalid argument in function %s\n",
1055                                __FUNCTION__);
1056                         break;
1057                 }
1058         }
1059
1060         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1061         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1062
1063         pol1 |= set1;
1064         pol1 &= ~unset1;
1065
1066         pol3 |= set3;
1067         pol3 &= ~unset3;
1068
1069         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1070         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1071 }
1072
1073 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1074 {
1075         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1076                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1077                 dc->out->type == TEGRA_DC_OUT_DSI)
1078                 return override_disp_mode[dc->out->type].pclk ?
1079                         &override_disp_mode[dc->out->type] : NULL;
1080         else
1081                 return NULL;
1082 }
1083
1084 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1085 {
1086         struct tegra_dc_mode *mode;
1087
1088         dc->out = out;
1089         mode = tegra_dc_get_override_mode(dc);
1090
1091         if (mode)
1092                 tegra_dc_set_mode(dc, mode);
1093         else if (out->n_modes > 0)
1094                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1095
1096         switch (out->type) {
1097         case TEGRA_DC_OUT_RGB:
1098                 dc->out_ops = &tegra_dc_rgb_ops;
1099                 break;
1100
1101         case TEGRA_DC_OUT_HDMI:
1102                 dc->out_ops = &tegra_dc_hdmi_ops;
1103                 break;
1104
1105         case TEGRA_DC_OUT_DSI:
1106                 dc->out_ops = &tegra_dc_dsi_ops;
1107                 break;
1108
1109         default:
1110                 dc->out_ops = NULL;
1111                 break;
1112         }
1113
1114         if (dc->out_ops && dc->out_ops->init)
1115                 dc->out_ops->init(dc);
1116 }
1117
1118 /* returns on error: -EINVAL
1119  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1120 int tegra_dc_get_out(const struct tegra_dc *dc)
1121 {
1122         if (dc && dc->out)
1123                 return dc->out->type;
1124         return -EINVAL;
1125 }
1126
1127 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1128 {
1129         if (dc->out)
1130                 return dc->out->height;
1131         else
1132                 return 0;
1133 }
1134 EXPORT_SYMBOL(tegra_dc_get_out_height);
1135
1136 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1137 {
1138         if (dc->out)
1139                 return dc->out->width;
1140         else
1141                 return 0;
1142 }
1143 EXPORT_SYMBOL(tegra_dc_get_out_width);
1144
1145 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1146 {
1147         if (dc->out && dc->out->max_pixclock)
1148                 return dc->out->max_pixclock;
1149         else
1150                 return 0;
1151 }
1152 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1153
1154 void tegra_dc_enable_crc(struct tegra_dc *dc)
1155 {
1156         u32 val;
1157
1158         mutex_lock(&dc->lock);
1159         tegra_dc_io_start(dc);
1160         tegra_dc_hold_dc_out(dc);
1161
1162         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1163                 CRC_ENABLE_ENABLE;
1164         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1165         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1166         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1167         tegra_dc_release_dc_out(dc);
1168         tegra_dc_io_end(dc);
1169         mutex_unlock(&dc->lock);
1170 }
1171
1172 void tegra_dc_disable_crc(struct tegra_dc *dc)
1173 {
1174         mutex_lock(&dc->lock);
1175         tegra_dc_io_start(dc);
1176         tegra_dc_hold_dc_out(dc);
1177         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1178         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1179         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1180
1181         tegra_dc_release_dc_out(dc);
1182         tegra_dc_io_end(dc);
1183         mutex_unlock(&dc->lock);
1184 }
1185
1186 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1187 {
1188         int crc = 0;
1189
1190         if (!dc) {
1191                 pr_err("Failed to get dc: NULL parameter.\n");
1192                 goto crc_error;
1193         }
1194
1195 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1196         /* TODO: Replace mdelay with code to sync VBlANK, since
1197          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1198         mdelay(TEGRA_CRC_LATCHED_DELAY);
1199 #endif
1200
1201         mutex_lock(&dc->lock);
1202         tegra_dc_io_start(dc);
1203         tegra_dc_hold_dc_out(dc);
1204         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1205         tegra_dc_release_dc_out(dc);
1206         tegra_dc_io_end(dc);
1207         mutex_unlock(&dc->lock);
1208 crc_error:
1209         return crc;
1210 }
1211
1212 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1213 {
1214 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1215         u32 val;
1216
1217         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1218         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1219             return true;
1220 #endif
1221         return false;
1222 }
1223
1224 static inline void enable_dc_irq(const struct tegra_dc *dc)
1225 {
1226 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1227         enable_irq(dc->irq);
1228 #else
1229         /* Always disable DC interrupts on FPGA. */
1230         disable_irq(dc->irq);
1231 #endif
1232 }
1233
1234 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1235 {
1236         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1237                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1238 }
1239
1240 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1241 {
1242         int ret = -ENOTTY;
1243
1244         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1245                 return ret;
1246
1247         /*
1248          * Logic is as follows
1249          * a) Indicate we need a vblank.
1250          * b) Wait for completion to be signalled from isr.
1251          * c) Initialize completion for next iteration.
1252          */
1253
1254         tegra_dc_hold_dc_out(dc);
1255         dc->out->user_needs_vblank = true;
1256
1257         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1258         init_completion(&dc->out->user_vblank_comp);
1259         tegra_dc_release_dc_out(dc);
1260
1261         return ret;
1262 }
1263
1264 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1265 {
1266         /* Do the actual brightness update outside of the mutex dc->lock */
1267         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1268                 dc->out->sd_settings->bl_device_name) {
1269                 char *bl_device_name =
1270                         dc->out->sd_settings->bl_device_name;
1271                 dc->out->sd_settings->bl_device =
1272                         get_backlight_device_by_name(bl_device_name);
1273         }
1274
1275         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1276                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1277                 backlight_update_status(bl);
1278         }
1279 }
1280
1281 static void tegra_dc_vblank(struct work_struct *work)
1282 {
1283         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1284         bool nvsd_updated = false;
1285
1286         mutex_lock(&dc->lock);
1287
1288         if (!dc->enabled) {
1289                 mutex_unlock(&dc->lock);
1290                 return;
1291         }
1292
1293         tegra_dc_io_start(dc);
1294         tegra_dc_hold_dc_out(dc);
1295         /* use the new frame's bandwidth setting instead of max(current, new),
1296          * skip this if we're using tegra_dc_one_shot_worker() */
1297         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1298                 tegra_dc_program_bandwidth(dc, true);
1299
1300         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1301         if (!tegra_dc_windows_are_dirty(dc))
1302                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1303
1304         /* Update the SD brightness */
1305         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1306                 nvsd_updated = nvsd_update_brightness(dc);
1307                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1308                  * V_BLANK_NVSD bit of vblank ref-count. */
1309                 if (nvsd_updated) {
1310                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1311                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1312                 } else {
1313                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1314                 }
1315         }
1316
1317         /* Mask vblank interrupt if ref-count is zero. */
1318         if (!dc->vblank_ref_count)
1319                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1320
1321         tegra_dc_release_dc_out(dc);
1322         tegra_dc_io_end(dc);
1323         mutex_unlock(&dc->lock);
1324
1325         /* Do the actual brightness update outside of the mutex dc->lock */
1326         if (nvsd_updated)
1327                 tegra_dc_prism_update_backlight(dc);
1328 }
1329
1330 static void tegra_dc_one_shot_worker(struct work_struct *work)
1331 {
1332         struct tegra_dc *dc = container_of(
1333                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1334         mutex_lock(&dc->lock);
1335
1336         /* memory client has gone idle */
1337         tegra_dc_clear_bandwidth(dc);
1338
1339         if (dc->out_ops->idle) {
1340                 tegra_dc_io_start(dc);
1341                 dc->out_ops->idle(dc);
1342                 tegra_dc_io_end(dc);
1343         }
1344
1345         mutex_unlock(&dc->lock);
1346 }
1347
1348 /* return an arbitrarily large number if count overflow occurs.
1349  * make it a nice base-10 number to show up in stats output */
1350 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1351 {
1352         unsigned count = tegra_dc_readl(dc, reg);
1353
1354         tegra_dc_writel(dc, 0, reg);
1355         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1356 }
1357
1358 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1359 {
1360         int i;
1361
1362         dc->stats.underflows++;
1363         if (dc->underflow_mask & WIN_A_UF_INT)
1364                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1365                         DC_WINBUF_AD_UFLOW_STATUS);
1366         if (dc->underflow_mask & WIN_B_UF_INT)
1367                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1368                         DC_WINBUF_BD_UFLOW_STATUS);
1369         if (dc->underflow_mask & WIN_C_UF_INT)
1370                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1371                         DC_WINBUF_CD_UFLOW_STATUS);
1372
1373         /* Check for any underflow reset conditions */
1374         for (i = 0; i < DC_N_WINDOWS; i++) {
1375                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1376                         dc->windows[i].underflows++;
1377
1378 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1379                         if (dc->windows[i].underflows > 4) {
1380                                 schedule_work(&dc->reset_work);
1381                                 /* reset counter */
1382                                 dc->windows[i].underflows = 0;
1383                                 trace_display_reset(dc);
1384                         }
1385 #endif
1386 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1387                         if (dc->windows[i].underflows > 4) {
1388                                 trace_display_reset(dc);
1389                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1390                                                 DC_DISP_DISP_MISC_CONTROL);
1391                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1392                                                 DC_CMD_STATE_CONTROL);
1393                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1394                                                 DC_CMD_STATE_CONTROL);
1395
1396                                 tegra_dc_writel(dc, 0,
1397                                                 DC_DISP_DISP_MISC_CONTROL);
1398                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1399                                                 DC_CMD_STATE_CONTROL);
1400                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1401                                                 DC_CMD_STATE_CONTROL);
1402                         }
1403 #endif
1404                 } else {
1405                         dc->windows[i].underflows = 0;
1406                 }
1407         }
1408
1409         /* Clear the underflow mask now that we've checked it. */
1410         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1411         dc->underflow_mask = 0;
1412         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1413         trace_underflow(dc);
1414 }
1415
1416 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1417 static void tegra_dc_vpulse2(struct work_struct *work)
1418 {
1419         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1420         bool nvsd_updated = false;
1421
1422         mutex_lock(&dc->lock);
1423
1424         if (!dc->enabled) {
1425                 mutex_unlock(&dc->lock);
1426                 return;
1427         }
1428
1429         tegra_dc_io_start(dc);
1430         tegra_dc_hold_dc_out(dc);
1431
1432         /* Clear the V_PULSE2_FLIP if no update */
1433         if (!tegra_dc_windows_are_dirty(dc))
1434                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1435
1436         /* Update the SD brightness */
1437         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1438                 nvsd_updated = nvsd_update_brightness(dc);
1439                 if (nvsd_updated) {
1440                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1441                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1442                 } else {
1443                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1444                 }
1445         }
1446
1447         /* Mask vpulse2 interrupt if ref-count is zero. */
1448         if (!dc->vpulse2_ref_count)
1449                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1450
1451         tegra_dc_release_dc_out(dc);
1452         tegra_dc_io_end(dc);
1453         mutex_unlock(&dc->lock);
1454
1455         /* Do the actual brightness update outside of the mutex dc->lock */
1456         if (nvsd_updated)
1457                 tegra_dc_prism_update_backlight(dc);
1458 }
1459 #endif
1460
1461 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1462 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1463 {
1464         /* pending user vblank, so wakeup */
1465         if ((status & (V_BLANK_INT | MSF_INT)) &&
1466             (dc->out->user_needs_vblank)) {
1467                 dc->out->user_needs_vblank = false;
1468                 complete(&dc->out->user_vblank_comp);
1469         }
1470
1471         if (status & V_BLANK_INT) {
1472                 /* Sync up windows. */
1473                 tegra_dc_trigger_windows(dc);
1474
1475                 /* Schedule any additional bottom-half vblank actvities. */
1476                 queue_work(system_freezable_wq, &dc->vblank_work);
1477         }
1478
1479         if (status & FRAME_END_INT) {
1480                 /* Mark the frame_end as complete. */
1481                 if (!completion_done(&dc->frame_end_complete))
1482                         complete(&dc->frame_end_complete);
1483         }
1484
1485 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1486         if (status & V_PULSE2_INT)
1487                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1488 #endif
1489 }
1490
1491 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1492 {
1493         /* Schedule any additional bottom-half vblank actvities. */
1494         if (status & V_BLANK_INT)
1495                 queue_work(system_freezable_wq, &dc->vblank_work);
1496
1497         if (status & FRAME_END_INT) {
1498                 struct timespec tm = CURRENT_TIME;
1499                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1500                 wake_up(&dc->timestamp_wq);
1501
1502                 /* Mark the frame_end as complete. */
1503                 if (!completion_done(&dc->frame_end_complete))
1504                         complete(&dc->frame_end_complete);
1505
1506                 tegra_dc_trigger_windows(dc);
1507         }
1508
1509 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1510         if (status & V_PULSE2_INT)
1511                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1512 #endif
1513 }
1514
1515 /* XXX: Not sure if we limit look ahead to 1 frame */
1516 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1517 {
1518         BUG_ON(!dc->frametime_ns);
1519         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1520 }
1521
1522 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1523 {
1524         BUG_ON(!dc->frametime_ns);
1525         return (((new_ts - old_ts) > dc->frametime_ns)
1526                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1527                         != div_s64((old_ts - dc->frame_end_timestamp),
1528                                 dc->frametime_ns)));
1529 }
1530 #endif
1531
1532 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1533 {
1534 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1535         struct tegra_dc *dc = ptr;
1536         unsigned long status;
1537         unsigned long underflow_mask;
1538         u32 val;
1539
1540         mutex_lock(&dc->lock);
1541         if (!dc->enabled) {
1542                 mutex_unlock(&dc->lock);
1543                 return IRQ_HANDLED;
1544         }
1545
1546         clk_enable(dc->clk);
1547         tegra_dc_io_start(dc);
1548         tegra_dc_hold_dc_out(dc);
1549
1550         if (!nvhost_module_powered_ext(dc->ndev)) {
1551                 WARN(1, "IRQ when DC not powered!\n");
1552                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1553                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1554                 tegra_dc_release_dc_out(dc);
1555                 tegra_dc_io_end(dc);
1556                 clk_disable(dc->clk);
1557                 mutex_unlock(&dc->lock);
1558                 return IRQ_HANDLED;
1559         }
1560
1561         /* clear all status flags except underflow, save those for the worker */
1562         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1563         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1564         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1565         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1566
1567         /*
1568          * Overlays can get thier internal state corrupted during and underflow
1569          * condition.  The only way to fix this state is to reset the DC.
1570          * if we get 4 consecutive frames with underflows, assume we're
1571          * hosed and reset.
1572          */
1573         underflow_mask = status & ALL_UF_INT;
1574
1575         /* Check underflow */
1576         if (underflow_mask) {
1577                 dc->underflow_mask |= underflow_mask;
1578                 schedule_delayed_work(&dc->underflow_work,
1579                         msecs_to_jiffies(1));
1580         }
1581
1582         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1583                 tegra_dc_one_shot_irq(dc, status);
1584         else
1585                 tegra_dc_continuous_irq(dc, status);
1586
1587         /* update video mode if it has changed since the last frame */
1588         if (status & (FRAME_END_INT | V_BLANK_INT))
1589                 tegra_dc_update_mode(dc);
1590
1591         tegra_dc_release_dc_out(dc);
1592         tegra_dc_io_end(dc);
1593         clk_disable(dc->clk);
1594         mutex_unlock(&dc->lock);
1595
1596         return IRQ_HANDLED;
1597 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1598         return IRQ_NONE;
1599 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1600 }
1601
1602 void tegra_dc_set_color_control(struct tegra_dc *dc)
1603 {
1604         u32 color_control;
1605
1606         switch (dc->out->depth) {
1607         case 3:
1608                 color_control = BASE_COLOR_SIZE111;
1609                 break;
1610
1611         case 6:
1612                 color_control = BASE_COLOR_SIZE222;
1613                 break;
1614
1615         case 8:
1616                 color_control = BASE_COLOR_SIZE332;
1617                 break;
1618
1619         case 9:
1620                 color_control = BASE_COLOR_SIZE333;
1621                 break;
1622
1623         case 12:
1624                 color_control = BASE_COLOR_SIZE444;
1625                 break;
1626
1627         case 15:
1628                 color_control = BASE_COLOR_SIZE555;
1629                 break;
1630
1631         case 16:
1632                 color_control = BASE_COLOR_SIZE565;
1633                 break;
1634
1635         case 18:
1636                 color_control = BASE_COLOR_SIZE666;
1637                 break;
1638
1639         default:
1640                 color_control = BASE_COLOR_SIZE888;
1641                 break;
1642         }
1643
1644         switch (dc->out->dither) {
1645         case TEGRA_DC_DISABLE_DITHER:
1646                 color_control |= DITHER_CONTROL_DISABLE;
1647                 break;
1648         case TEGRA_DC_ORDERED_DITHER:
1649                 color_control |= DITHER_CONTROL_ORDERED;
1650                 break;
1651         case TEGRA_DC_ERRDIFF_DITHER:
1652                 /* The line buffer for error-diffusion dither is limited
1653                  * to 1280 pixels per line. This limits the maximum
1654                  * horizontal active area size to 1280 pixels when error
1655                  * diffusion is enabled.
1656                  */
1657                 BUG_ON(dc->mode.h_active > 1280);
1658                 color_control |= DITHER_CONTROL_ERRDIFF;
1659                 break;
1660         }
1661
1662 #ifdef CONFIG_TEGRA_DC_CMU
1663         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1664                 color_control |= CMU_ENABLE;
1665 #endif
1666
1667         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1668 }
1669
1670 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1671 {
1672         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1673                 return dc->win_syncpt[idx];
1674         BUG();
1675 }
1676
1677 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1678 {
1679 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1680         u32 start, end;
1681         unsigned long val;
1682
1683         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1684         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1685
1686         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1687                 dc->mode.v_back_porch + dc->mode.v_active;
1688         end = start + 1;
1689         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1690         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1691
1692         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1693         val |= V_PULSE2_INT;
1694         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1695
1696         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1697         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1698 #endif
1699 }
1700
1701 static int tegra_dc_init(struct tegra_dc *dc)
1702 {
1703         int i;
1704         int int_enable;
1705
1706         tegra_dc_io_start(dc);
1707         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1708         if (dc->ndev->id == 0) {
1709                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1710                                       TEGRA_MC_PRIO_MED);
1711                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1712                                       TEGRA_MC_PRIO_MED);
1713                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1714                                       TEGRA_MC_PRIO_MED);
1715 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1716                 /* only present on Tegra2 and 3 */
1717                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1718                                       TEGRA_MC_PRIO_MED);
1719 #endif
1720                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1721                                       TEGRA_MC_PRIO_HIGH);
1722         } else if (dc->ndev->id == 1) {
1723                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1724                                       TEGRA_MC_PRIO_MED);
1725                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1726                                       TEGRA_MC_PRIO_MED);
1727                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1728                                       TEGRA_MC_PRIO_MED);
1729 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1730                 /* only present on Tegra2 and 3 */
1731                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1732                                       TEGRA_MC_PRIO_MED);
1733 #endif
1734                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1735                                       TEGRA_MC_PRIO_HIGH);
1736         }
1737         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1738                         DC_CMD_CONT_SYNCPT_VSYNC);
1739
1740         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1741         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1742         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1743         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1744 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1745         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1746 #endif
1747         /* enable interrupts for vblank, frame_end and underflows */
1748         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1749         /* for panels with one-shot mode enable tearing effect interrupt */
1750         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1751                 int_enable |= MSF_INT;
1752
1753         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1754         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1755         tegra_dc_init_vpulse2_int(dc);
1756
1757         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1758
1759 #ifdef CONFIG_TEGRA_DC_CMU
1760         if (dc->pdata->cmu)
1761                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1762         else
1763                 _tegra_dc_update_cmu(dc, &default_cmu);
1764 #endif
1765         tegra_dc_set_color_control(dc);
1766         for (i = 0; i < DC_N_WINDOWS; i++) {
1767                 struct tegra_dc_win *win = &dc->windows[i];
1768                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1769                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1770                 tegra_dc_set_csc(dc, &win->csc);
1771                 tegra_dc_set_lut(dc, win);
1772                 tegra_dc_set_scaling_filter(dc);
1773         }
1774
1775         for (i = 0; i < dc->n_windows; i++) {
1776                 u32 syncpt = get_syncpt(dc, i);
1777
1778                 dc->syncpt[i].id = syncpt;
1779
1780                 dc->syncpt[i].min = dc->syncpt[i].max =
1781                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1782         }
1783
1784         trace_display_mode(dc, &dc->mode);
1785
1786         if (dc->mode.pclk) {
1787                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1788                         tegra_dc_io_end(dc);
1789                         return -EINVAL;
1790                 }
1791         }
1792
1793         /* Initialize SD AFTER the modeset.
1794            nvsd_init handles the sd_settings = NULL case. */
1795         nvsd_init(dc, dc->out->sd_settings);
1796
1797         tegra_dc_io_end(dc);
1798
1799         return 0;
1800 }
1801
1802 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1803 {
1804         int failed_init = 0;
1805
1806         mutex_lock(&status_lock);
1807         tegra_dc_unpowergate_locked(dc);
1808         mutex_unlock(&status_lock);
1809
1810         if (dc->out->enable)
1811                 dc->out->enable(&dc->ndev->dev);
1812
1813         tegra_dc_setup_clk(dc, dc->clk);
1814         tegra_dc_clk_enable(dc);
1815         tegra_dc_io_start(dc);
1816
1817         tegra_dc_power_on(dc);
1818
1819         /* do not accept interrupts during initialization */
1820         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1821
1822         enable_dc_irq(dc);
1823
1824         failed_init = tegra_dc_init(dc);
1825         if (failed_init) {
1826                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1827                 disable_irq_nosync(dc->irq);
1828                 tegra_dc_clear_bandwidth(dc);
1829                 tegra_dc_clk_disable(dc);
1830                 if (dc->out && dc->out->disable)
1831                         dc->out->disable();
1832                 tegra_dc_io_end(dc);
1833                 return false;
1834         }
1835
1836         if (dc->out_ops && dc->out_ops->enable)
1837                 dc->out_ops->enable(dc);
1838
1839         /* force a full blending update */
1840         dc->blend.z[0] = -1;
1841
1842         tegra_dc_ext_enable(dc->ext);
1843
1844         trace_display_enable(dc);
1845
1846         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1847         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1848
1849         if (dc->out->postpoweron)
1850                 dc->out->postpoweron();
1851
1852         tegra_dc_io_end(dc);
1853         return true;
1854 }
1855
1856 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1857 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1858 {
1859         bool ret = true;
1860
1861         if (dc->out->enable)
1862                 dc->out->enable(&dc->ndev->dev);
1863
1864         tegra_dc_setup_clk(dc, dc->clk);
1865         tegra_dc_clk_enable(dc);
1866
1867         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1868                 mutex_lock(&tegra_dcs[1]->lock);
1869                 disable_irq_nosync(tegra_dcs[1]->irq);
1870         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1871                 mutex_lock(&tegra_dcs[0]->lock);
1872                 disable_irq_nosync(tegra_dcs[0]->irq);
1873         }
1874
1875         msleep(5);
1876         tegra_periph_reset_assert(dc->clk);
1877         msleep(2);
1878 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1879         tegra_periph_reset_deassert(dc->clk);
1880         msleep(1);
1881 #endif
1882
1883         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1884                 enable_dc_irq(tegra_dcs[1]);
1885                 mutex_unlock(&tegra_dcs[1]->lock);
1886         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1887                 enable_dc_irq(tegra_dcs[0]);
1888                 mutex_unlock(&tegra_dcs[0]->lock);
1889         }
1890
1891         enable_dc_irq(dc);
1892
1893         if (tegra_dc_init(dc)) {
1894                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1895                 ret = false;
1896         }
1897
1898         if (dc->out_ops && dc->out_ops->enable)
1899                 dc->out_ops->enable(dc);
1900
1901         if (dc->out->postpoweron)
1902                 dc->out->postpoweron();
1903
1904         /* force a full blending update */
1905         dc->blend.z[0] = -1;
1906
1907         tegra_dc_ext_enable(dc->ext);
1908
1909         if (!ret) {
1910                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1911                 _tegra_dc_controller_disable(dc);
1912         }
1913
1914         trace_display_reset(dc);
1915         return ret;
1916 }
1917 #endif
1918
1919 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1920 {
1921         if (dc->mode.pclk == 0) {
1922                 switch (dc->out->type) {
1923                 case TEGRA_DC_OUT_HDMI:
1924                 /* DC enable called but no videomode is loaded.
1925                      Check if HDMI is connected, then set fallback mdoe */
1926                 if (tegra_dc_hpd(dc)) {
1927                         return tegra_dc_set_fb_mode(dc,
1928                                         &tegra_dc_hdmi_fallback_mode, 0);
1929                 } else
1930                         return false;
1931
1932                 break;
1933
1934                 /* Do nothing for other outputs for now */
1935                 case TEGRA_DC_OUT_RGB:
1936
1937                 case TEGRA_DC_OUT_DSI:
1938
1939                 default:
1940                         return false;
1941                 }
1942         }
1943
1944         return false;
1945 }
1946
1947 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1948 {
1949         return _tegra_dc_set_default_videomode(dc);
1950 }
1951
1952 static bool _tegra_dc_enable(struct tegra_dc *dc)
1953 {
1954         if (dc->mode.pclk == 0)
1955                 return false;
1956
1957         if (!dc->out)
1958                 return false;
1959
1960         if (dc->enabled)
1961                 return true;
1962
1963         if (!_tegra_dc_controller_enable(dc))
1964                 return false;
1965
1966         return true;
1967 }
1968
1969 void tegra_dc_enable(struct tegra_dc *dc)
1970 {
1971         mutex_lock(&dc->lock);
1972
1973         if (!dc->enabled)
1974                 dc->enabled = _tegra_dc_enable(dc);
1975
1976         mutex_unlock(&dc->lock);
1977         trace_display_mode(dc, &dc->mode);
1978 }
1979
1980 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1981 {
1982         unsigned i;
1983
1984         tegra_dc_hold_dc_out(dc);
1985
1986         if (dc->out && dc->out->prepoweroff)
1987                 dc->out->prepoweroff();
1988
1989         if (dc->out_ops && dc->out_ops->disable)
1990                 dc->out_ops->disable(dc);
1991
1992         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1993
1994         disable_irq_nosync(dc->irq);
1995
1996         tegra_dc_clear_bandwidth(dc);
1997
1998         /* ugly hack */
1999         if (dc->out_ops->release &&
2000                 (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE))
2001                 tegra_dc_release_dc_out(dc);
2002         else
2003                 tegra_dc_clk_disable(dc);
2004
2005         if (dc->out && dc->out->disable)
2006                 dc->out->disable();
2007
2008         for (i = 0; i < dc->n_windows; i++) {
2009                 struct tegra_dc_win *w = &dc->windows[i];
2010
2011                 /* reset window bandwidth */
2012                 w->bandwidth = 0;
2013                 w->new_bandwidth = 0;
2014
2015                 /* disable windows */
2016                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2017
2018                 /* flush any pending syncpt waits */
2019                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2020                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2021                                 dc->syncpt[i].min, dc->syncpt[i].max);
2022                         dc->syncpt[i].min++;
2023                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2024                 }
2025         }
2026         trace_display_disable(dc);
2027 }
2028
2029 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2030 {
2031 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2032         u32 val;
2033         if (dc->enabled)  {
2034                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2035                 if (enable)
2036                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2037                 else
2038                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2039                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2040         }
2041 #endif
2042 }
2043
2044 bool tegra_dc_stats_get(struct tegra_dc *dc)
2045 {
2046 #if 0 /* right now it is always enabled */
2047         u32 val;
2048         bool res;
2049
2050         if (dc->enabled)  {
2051                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2052                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2053         } else {
2054                 res = false;
2055         }
2056
2057         return res;
2058 #endif
2059         return true;
2060 }
2061
2062 /* make the screen blank by disabling all windows */
2063 void tegra_dc_blank(struct tegra_dc *dc)
2064 {
2065         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2066         unsigned i;
2067
2068         for (i = 0; i < DC_N_WINDOWS; i++) {
2069                 dcwins[i] = tegra_dc_get_window(dc, i);
2070                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2071         }
2072
2073         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2074         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2075 }
2076
2077 static void _tegra_dc_disable(struct tegra_dc *dc)
2078 {
2079         struct tegra_dc *dc_partner;
2080         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2081                 mutex_lock(&dc->one_shot_lock);
2082                 cancel_delayed_work_sync(&dc->one_shot_work);
2083         }
2084
2085         mutex_lock(&status_lock);
2086
2087         tegra_dc_io_start(dc);
2088         _tegra_dc_controller_disable(dc);
2089         tegra_dc_io_end(dc);
2090
2091         /* Get the handler of the other display controller. */
2092         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2093         if (!dc_partner)
2094                 tegra_dc_powergate_locked(dc);
2095         else if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2096                 /* If DISB is powergated, then powergate DISA. */
2097                 if (!dc_partner->powered)
2098                         tegra_dc_powergate_locked(dc);
2099         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2100                 /* If DISA is enabled, only powergate DISB;
2101                  * otherwise, powergate DISA and DISB.
2102                  * */
2103                 if (dc_partner->enabled) {
2104                         tegra_dc_powergate_locked(dc);
2105                 } else {
2106                         tegra_dc_powergate_locked(dc);
2107                         tegra_dc_powergate_locked(dc_partner);
2108                 }
2109         }
2110         mutex_unlock(&status_lock);
2111
2112         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2113                 mutex_unlock(&dc->one_shot_lock);
2114 }
2115
2116 void tegra_dc_disable(struct tegra_dc *dc)
2117 {
2118         tegra_dc_ext_disable(dc->ext);
2119
2120         /* it's important that new underflow work isn't scheduled before the
2121          * lock is acquired. */
2122         cancel_delayed_work_sync(&dc->underflow_work);
2123
2124         mutex_lock(&dc->lock);
2125
2126         if (dc->enabled) {
2127                 dc->enabled = false;
2128
2129                 if (!dc->suspended)
2130                         _tegra_dc_disable(dc);
2131         }
2132
2133 #ifdef CONFIG_SWITCH
2134         switch_set_state(&dc->modeset_switch, 0);
2135 #endif
2136
2137         mutex_unlock(&dc->lock);
2138         synchronize_irq(dc->irq);
2139         trace_display_mode(dc, &dc->mode);
2140 }
2141
2142 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2143 static void tegra_dc_reset_worker(struct work_struct *work)
2144 {
2145         struct tegra_dc *dc =
2146                 container_of(work, struct tegra_dc, reset_work);
2147
2148         unsigned long val = 0;
2149
2150         mutex_lock(&shared_lock);
2151
2152         dev_warn(&dc->ndev->dev,
2153                 "overlay stuck in underflow state.  resetting.\n");
2154
2155         tegra_dc_ext_disable(dc->ext);
2156
2157         mutex_lock(&dc->lock);
2158
2159         if (dc->enabled == false)
2160                 goto unlock;
2161
2162         dc->enabled = false;
2163
2164         /*
2165          * off host read bus
2166          */
2167         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2168         val &= ~(0x00000100);
2169         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2170
2171         /*
2172          * set DC to STOP mode
2173          */
2174         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2175
2176         msleep(10);
2177
2178         _tegra_dc_controller_disable(dc);
2179
2180         /* _tegra_dc_controller_reset_enable deasserts reset */
2181         _tegra_dc_controller_reset_enable(dc);
2182
2183         dc->enabled = true;
2184
2185         /* reopen host read bus */
2186         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2187         val &= ~(0x00000100);
2188         val |= 0x100;
2189         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2190
2191 unlock:
2192         mutex_unlock(&dc->lock);
2193         mutex_unlock(&shared_lock);
2194         trace_display_reset(dc);
2195 }
2196 #endif
2197
2198 static void tegra_dc_underflow_worker(struct work_struct *work)
2199 {
2200         struct tegra_dc *dc = container_of(
2201                 to_delayed_work(work), struct tegra_dc, underflow_work);
2202
2203         mutex_lock(&dc->lock);
2204         tegra_dc_io_start(dc);
2205         tegra_dc_hold_dc_out(dc);
2206
2207         if (dc->enabled) {
2208                 tegra_dc_underflow_handler(dc);
2209         }
2210         tegra_dc_release_dc_out(dc);
2211         tegra_dc_io_end(dc);
2212         mutex_unlock(&dc->lock);
2213 }
2214
2215 #ifdef CONFIG_SWITCH
2216 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2217 {
2218         struct tegra_dc *dc =
2219                 container_of(sdev, struct tegra_dc, modeset_switch);
2220
2221         if (!sdev->state)
2222                 return sprintf(buf, "offline\n");
2223
2224         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2225 }
2226 #endif
2227
2228 static void tegra_dc_add_modes(struct tegra_dc *dc)
2229 {
2230         struct fb_monspecs specs;
2231         int i;
2232
2233         memset(&specs, 0, sizeof(specs));
2234         specs.max_x = dc->mode.h_active * 1000;
2235         specs.max_y = dc->mode.v_active * 1000;
2236         specs.modedb_len = dc->out->n_modes;
2237         specs.modedb = kzalloc(specs.modedb_len *
2238                 sizeof(struct fb_videomode), GFP_KERNEL);
2239         for (i = 0; i < dc->out->n_modes; i++)
2240                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2241                         &dc->out->modes[i]);
2242         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2243         kfree(specs.modedb);
2244 }
2245
2246 static int tegra_dc_probe(struct platform_device *ndev)
2247 {
2248         struct tegra_dc *dc;
2249         struct tegra_dc_mode *mode;
2250         struct clk *clk;
2251         struct clk *emc_clk;
2252         struct resource *res;
2253         struct resource *base_res;
2254         struct resource *fb_mem = NULL;
2255         int ret = 0;
2256         void __iomem *base;
2257         int irq;
2258         int i;
2259
2260         if (!ndev->dev.platform_data) {
2261                 dev_err(&ndev->dev, "no platform data\n");
2262                 return -ENOENT;
2263         }
2264
2265         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2266         if (!dc) {
2267                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2268                 return -ENOMEM;
2269         }
2270
2271         irq = platform_get_irq_byname(ndev, "irq");
2272         if (irq <= 0) {
2273                 dev_err(&ndev->dev, "no irq\n");
2274                 ret = -ENOENT;
2275                 goto err_free;
2276         }
2277
2278         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2279         if (!res) {
2280                 dev_err(&ndev->dev, "no mem resource\n");
2281                 ret = -ENOENT;
2282                 goto err_free;
2283         }
2284
2285         base_res = request_mem_region(res->start, resource_size(res),
2286                 ndev->name);
2287         if (!base_res) {
2288                 dev_err(&ndev->dev, "request_mem_region failed\n");
2289                 ret = -EBUSY;
2290                 goto err_free;
2291         }
2292
2293         base = ioremap(res->start, resource_size(res));
2294         if (!base) {
2295                 dev_err(&ndev->dev, "registers can't be mapped\n");
2296                 ret = -EBUSY;
2297                 goto err_release_resource_reg;
2298         }
2299         if (TEGRA_DISPLAY_BASE == res->start) {
2300                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2301                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2302                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2303                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2304                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2305         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2306                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2307                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2308                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2309                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2310                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2311         } else {
2312                 dev_err(&ndev->dev,
2313                         "Unknown base address %#08x: unable to assign syncpt\n",
2314                         res->start);
2315         }
2316
2317
2318         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2319
2320         clk = clk_get(&ndev->dev, NULL);
2321         if (IS_ERR_OR_NULL(clk)) {
2322                 dev_err(&ndev->dev, "can't get clock\n");
2323                 ret = -ENOENT;
2324                 goto err_iounmap_reg;
2325         }
2326
2327         emc_clk = clk_get(&ndev->dev, "emc");
2328         if (IS_ERR_OR_NULL(emc_clk)) {
2329                 dev_err(&ndev->dev, "can't get emc clock\n");
2330                 ret = -ENOENT;
2331                 goto err_put_clk;
2332         }
2333
2334         dc->clk = clk;
2335         dc->emc_clk = emc_clk;
2336         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2337         /* Initialize one shot work delay, it will be assigned by dsi
2338          * according to refresh rate later. */
2339         dc->one_shot_delay_ms = 40;
2340
2341         dc->base_res = base_res;
2342         dc->base = base;
2343         dc->irq = irq;
2344         dc->ndev = ndev;
2345         dc->pdata = ndev->dev.platform_data;
2346
2347         /*
2348          * The emc is a shared clock, it will be set based on
2349          * the requirements for each user on the bus.
2350          */
2351         dc->emc_clk_rate = 0;
2352
2353         mutex_init(&dc->lock);
2354         mutex_init(&dc->one_shot_lock);
2355         mutex_init(&status_lock);
2356         init_completion(&dc->frame_end_complete);
2357         init_waitqueue_head(&dc->wq);
2358         init_waitqueue_head(&dc->timestamp_wq);
2359 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2360         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2361 #endif
2362         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2363         dc->vblank_ref_count = 0;
2364 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2365         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2366 #endif
2367         dc->vpulse2_ref_count = 0;
2368         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2369         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2370
2371         tegra_dc_init_lut_defaults(&dc->fb_lut);
2372
2373         dc->n_windows = DC_N_WINDOWS;
2374         for (i = 0; i < dc->n_windows; i++) {
2375                 struct tegra_dc_win *win = &dc->windows[i];
2376                 win->idx = i;
2377                 win->dc = dc;
2378                 tegra_dc_init_csc_defaults(&win->csc);
2379                 tegra_dc_init_lut_defaults(&win->lut);
2380         }
2381
2382         ret = tegra_dc_set(dc, ndev->id);
2383         if (ret < 0) {
2384                 dev_err(&ndev->dev, "can't add dc\n");
2385                 goto err_free_irq;
2386         }
2387
2388         platform_set_drvdata(ndev, dc);
2389
2390 #ifdef CONFIG_SWITCH
2391         dc->modeset_switch.name = dev_name(&ndev->dev);
2392         dc->modeset_switch.state = 0;
2393         dc->modeset_switch.print_state = switch_modeset_print_mode;
2394         ret = switch_dev_register(&dc->modeset_switch);
2395         if (ret < 0)
2396                 dev_err(&ndev->dev, "failed to register switch driver\n");
2397 #endif
2398
2399         tegra_dc_feature_register(dc);
2400
2401         if (dc->pdata->default_out)
2402                 tegra_dc_set_out(dc, dc->pdata->default_out);
2403         else
2404                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2405         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2406
2407         dc->ext = tegra_dc_ext_register(ndev, dc);
2408         if (IS_ERR_OR_NULL(dc->ext)) {
2409                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2410                 dc->ext = NULL;
2411         }
2412
2413         /* interrupt handler must be registered before tegra_fb_register() */
2414         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2415                         dev_name(&ndev->dev), dc)) {
2416                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2417                 ret = -EBUSY;
2418                 goto err_put_emc_clk;
2419         }
2420         disable_dc_irq(dc);
2421
2422         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2423                 _tegra_dc_set_default_videomode(dc);
2424                 dc->enabled = _tegra_dc_enable(dc);
2425         }
2426
2427         tegra_dc_create_debugfs(dc);
2428
2429         dev_info(&ndev->dev, "probed\n");
2430
2431         if (dc->pdata->fb) {
2432                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2433                         unsigned long fmt;
2434                         tegra_dc_writel(dc,
2435                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2436                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2437
2438                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2439                         dc->pdata->fb->bits_per_pixel =
2440                                 tegra_dc_fmt_bpp(fmt);
2441                 }
2442
2443                 mode = tegra_dc_get_override_mode(dc);
2444                 if (mode) {
2445                         dc->pdata->fb->xres = mode->h_active;
2446                         dc->pdata->fb->yres = mode->v_active;
2447                 }
2448
2449                 tegra_dc_io_start(dc);
2450                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2451                 if (IS_ERR_OR_NULL(dc->fb))
2452                         dc->fb = NULL;
2453                 tegra_dc_io_end(dc);
2454         }
2455
2456         if (dc->out && dc->out->n_modes)
2457                 tegra_dc_add_modes(dc);
2458
2459         if (dc->out && dc->out->hotplug_init)
2460                 dc->out->hotplug_init(&ndev->dev);
2461
2462         if (dc->out_ops && dc->out_ops->detect)
2463                 dc->out_ops->detect(dc);
2464         else
2465                 dc->connected = true;
2466
2467 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2468         mutex_lock(&status_lock);
2469         /* Powergate display module when it's unconnected. */
2470         if (!tegra_dc_get_connected(dc))
2471                 tegra_dc_powergate_locked(dc);
2472         mutex_unlock(&status_lock);
2473 #endif
2474
2475         tegra_dc_create_sysfs(&dc->ndev->dev);
2476
2477         return 0;
2478
2479 err_free_irq:
2480         free_irq(irq, dc);
2481 err_put_emc_clk:
2482         clk_put(emc_clk);
2483 err_put_clk:
2484         clk_put(clk);
2485 err_iounmap_reg:
2486         iounmap(base);
2487         if (fb_mem)
2488                 release_resource(fb_mem);
2489 err_release_resource_reg:
2490         release_resource(base_res);
2491 err_free:
2492         kfree(dc);
2493
2494         return ret;
2495 }
2496
2497 static int tegra_dc_remove(struct platform_device *ndev)
2498 {
2499         struct tegra_dc *dc = platform_get_drvdata(ndev);
2500
2501         tegra_dc_remove_sysfs(&dc->ndev->dev);
2502         tegra_dc_remove_debugfs(dc);
2503
2504         if (dc->fb) {
2505                 tegra_fb_unregister(dc->fb);
2506                 if (dc->fb_mem)
2507                         release_resource(dc->fb_mem);
2508         }
2509
2510         tegra_dc_ext_disable(dc->ext);
2511
2512         if (dc->ext)
2513                 tegra_dc_ext_unregister(dc->ext);
2514
2515         mutex_lock(&dc->lock);
2516         if (dc->enabled)
2517                 _tegra_dc_disable(dc);
2518         dc->enabled = false;
2519         mutex_unlock(&dc->lock);
2520         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2521
2522 #ifdef CONFIG_SWITCH
2523         switch_dev_unregister(&dc->modeset_switch);
2524 #endif
2525         free_irq(dc->irq, dc);
2526         clk_put(dc->emc_clk);
2527         clk_put(dc->clk);
2528         iounmap(dc->base);
2529         if (dc->fb_mem)
2530                 release_resource(dc->base_res);
2531         kfree(dc);
2532         tegra_dc_set(NULL, ndev->id);
2533
2534         return 0;
2535 }
2536
2537 #ifdef CONFIG_PM
2538 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2539 {
2540         struct tegra_dc *dc = platform_get_drvdata(ndev);
2541
2542         trace_display_suspend(dc);
2543         dev_info(&ndev->dev, "suspend\n");
2544
2545         tegra_dc_ext_disable(dc->ext);
2546
2547         mutex_lock(&dc->lock);
2548         tegra_dc_io_start(dc);
2549
2550         if (dc->out_ops && dc->out_ops->suspend)
2551                 dc->out_ops->suspend(dc);
2552
2553         if (dc->enabled) {
2554                 _tegra_dc_disable(dc);
2555
2556                 dc->suspended = true;
2557         }
2558
2559         if (dc->out && dc->out->postsuspend) {
2560                 dc->out->postsuspend();
2561                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2562                         /*
2563                          * avoid resume event due to voltage falling
2564                          */
2565                         msleep(100);
2566         }
2567
2568         tegra_dc_io_end(dc);
2569         mutex_unlock(&dc->lock);
2570         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2571
2572         return 0;
2573 }
2574
2575 static int tegra_dc_resume(struct platform_device *ndev)
2576 {
2577         struct tegra_dc *dc = platform_get_drvdata(ndev);
2578
2579         trace_display_resume(dc);
2580         dev_info(&ndev->dev, "resume\n");
2581
2582         mutex_lock(&dc->lock);
2583         dc->suspended = false;
2584
2585         if (dc->enabled) {
2586                 dc->enabled = false;
2587                 _tegra_dc_set_default_videomode(dc);
2588                 dc->enabled = _tegra_dc_enable(dc);
2589         }
2590
2591         if (dc->out && dc->out->hotplug_init)
2592                 dc->out->hotplug_init(&ndev->dev);
2593
2594         if (dc->out_ops && dc->out_ops->resume)
2595                 dc->out_ops->resume(dc);
2596         mutex_unlock(&dc->lock);
2597
2598         return 0;
2599 }
2600
2601 #endif /* CONFIG_PM */
2602
2603 static void tegra_dc_shutdown(struct platform_device *ndev)
2604 {
2605         struct tegra_dc *dc = platform_get_drvdata(ndev);
2606
2607         if (!dc || !dc->enabled)
2608                 return;
2609
2610         tegra_dc_blank(dc);
2611         tegra_dc_disable(dc);
2612 }
2613
2614 extern int suspend_set(const char *val, struct kernel_param *kp)
2615 {
2616         if (!strcmp(val, "dump"))
2617                 dump_regs(tegra_dcs[0]);
2618 #ifdef CONFIG_PM
2619         else if (!strcmp(val, "suspend"))
2620                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2621         else if (!strcmp(val, "resume"))
2622                 tegra_dc_resume(tegra_dcs[0]->ndev);
2623 #endif
2624
2625         return 0;
2626 }
2627
2628 extern int suspend_get(char *buffer, struct kernel_param *kp)
2629 {
2630         return 0;
2631 }
2632
2633 int suspend;
2634
2635 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2636
2637 struct platform_driver tegra_dc_driver = {
2638         .driver = {
2639                 .name = "tegradc",
2640                 .owner = THIS_MODULE,
2641         },
2642         .probe = tegra_dc_probe,
2643         .remove = tegra_dc_remove,
2644 #ifdef CONFIG_PM
2645         .suspend = tegra_dc_suspend,
2646         .resume = tegra_dc_resume,
2647 #endif
2648         .shutdown = tegra_dc_shutdown,
2649 };
2650
2651 #ifndef MODULE
2652 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2653 {
2654         int i, params[11];
2655         char *p;
2656
2657         for (i = 0; i < ARRAY_SIZE(params); i++) {
2658                 if ((p = strsep(&options, ",")) != NULL) {
2659                         if (*p)
2660                                 params[i] = simple_strtoul(p, &p, 10);
2661                 } else
2662                         return -EINVAL;
2663         }
2664
2665         if ((mode->pclk = params[0]) == 0)
2666                 return -EINVAL;
2667
2668         mode->h_active      = params[1];
2669         mode->v_active      = params[2];
2670         mode->h_ref_to_sync = params[3];
2671         mode->v_ref_to_sync = params[4];
2672         mode->h_sync_width  = params[5];
2673         mode->v_sync_width  = params[6];
2674         mode->h_back_porch  = params[7];
2675         mode->v_back_porch  = params[8];
2676         mode->h_front_porch = params[9];
2677         mode->v_front_porch = params[10];
2678
2679         return 0;
2680 }
2681
2682 static int __init tegra_dc_mode_override(char *str)
2683 {
2684         char *p = str, *options;
2685
2686         if (!p || !*p)
2687                 return -EINVAL;
2688
2689         p = strstr(str, "hdmi:");
2690         if (p) {
2691                 p += 5;
2692                 options = strsep(&p, ";");
2693                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2694                         return -EINVAL;
2695         }
2696
2697         p = strstr(str, "rgb:");
2698         if (p) {
2699                 p += 4;
2700                 options = strsep(&p, ";");
2701                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2702                         return -EINVAL;
2703         }
2704
2705         p = strstr(str, "dsi:");
2706         if (p) {
2707                 p += 4;
2708                 options = strsep(&p, ";");
2709                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2710                         return -EINVAL;
2711         }
2712
2713         return 0;
2714 }
2715
2716 __setup("disp_params=", tegra_dc_mode_override);
2717 #endif
2718
2719 static int __init tegra_dc_module_init(void)
2720 {
2721         int ret = tegra_dc_ext_module_init();
2722         if (ret)
2723                 return ret;
2724         return platform_driver_register(&tegra_dc_driver);
2725 }
2726
2727 static void __exit tegra_dc_module_exit(void)
2728 {
2729         platform_driver_unregister(&tegra_dc_driver);
2730         tegra_dc_ext_module_exit();
2731 }
2732
2733 module_exit(tegra_dc_module_exit);
2734 module_init(tegra_dc_module_init);