video: backlight: use gpio request and free apis for backlight pin
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
63         .refresh = 60,
64         .xres = 640,
65         .yres = 480,
66         .pixclock = KHZ2PICOS(25200),
67         .hsync_len = 96,        /* h_sync_width */
68         .vsync_len = 2,         /* v_sync_width */
69         .left_margin = 48,      /* h_back_porch */
70         .upper_margin = 33,     /* v_back_porch */
71         .right_margin = 16,     /* h_front_porch */
72         .lower_margin = 10,     /* v_front_porch */
73         .vmode = 0,
74         .sync = 0,
75 };
76
77 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
78
79 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
80
81 DEFINE_MUTEX(tegra_dc_lock);
82 DEFINE_MUTEX(shared_lock);
83
84 static const struct {
85         bool h;
86         bool v;
87 } can_filter[] = {
88         /* Window A has no filtering */
89         { false, false },
90         /* Window B has both H and V filtering */
91         { true,  true  },
92         /* Window C has only H filtering */
93         { false, true  },
94 };
95
96 #ifdef CONFIG_TEGRA_DC_CMU
97 static struct tegra_dc_cmu default_cmu = {
98         /* lut1 maps sRGB to linear space. */
99         {
100                 0,    1,    2,    4,    5,    6,    7,    9,
101                 10,   11,   12,   14,   15,   16,   18,   20,
102                 21,   23,   25,   27,   29,   31,   33,   35,
103                 37,   40,   42,   45,   48,   50,   53,   56,
104                 59,   62,   66,   69,   72,   76,   79,   83,
105                 87,   91,   95,   99,   103,  107,  112,  116,
106                 121,  126,  131,  136,  141,  146,  151,  156,
107                 162,  168,  173,  179,  185,  191,  197,  204,
108                 210,  216,  223,  230,  237,  244,  251,  258,
109                 265,  273,  280,  288,  296,  304,  312,  320,
110                 329,  337,  346,  354,  363,  372,  381,  390,
111                 400,  409,  419,  428,  438,  448,  458,  469,
112                 479,  490,  500,  511,  522,  533,  544,  555,
113                 567,  578,  590,  602,  614,  626,  639,  651,
114                 664,  676,  689,  702,  715,  728,  742,  755,
115                 769,  783,  797,  811,  825,  840,  854,  869,
116                 884,  899,  914,  929,  945,  960,  976,  992,
117                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
118                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
119                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
120                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
121                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
122                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
123                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
124                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
125                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
126                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
127                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
128                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
129                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
130                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
131                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
132         },
133         /* csc */
134         {
135                 0x100, 0x0,   0x0,
136                 0x0,   0x100, 0x0,
137                 0x0,   0x0,   0x100,
138         },
139         /* lut2 maps linear space to sRGB*/
140         {
141                 0,    1,    2,    2,    3,    4,    5,    6,
142                 6,    7,    8,    9,    10,   10,   11,   12,
143                 13,   13,   14,   15,   15,   16,   16,   17,
144                 18,   18,   19,   19,   20,   20,   21,   21,
145                 22,   22,   23,   23,   23,   24,   24,   25,
146                 25,   25,   26,   26,   27,   27,   27,   28,
147                 28,   29,   29,   29,   30,   30,   30,   31,
148                 31,   31,   32,   32,   32,   33,   33,   33,
149                 34,   34,   34,   34,   35,   35,   35,   36,
150                 36,   36,   37,   37,   37,   37,   38,   38,
151                 38,   38,   39,   39,   39,   40,   40,   40,
152                 40,   41,   41,   41,   41,   42,   42,   42,
153                 42,   43,   43,   43,   43,   43,   44,   44,
154                 44,   44,   45,   45,   45,   45,   46,   46,
155                 46,   46,   46,   47,   47,   47,   47,   48,
156                 48,   48,   48,   48,   49,   49,   49,   49,
157                 49,   50,   50,   50,   50,   50,   51,   51,
158                 51,   51,   51,   52,   52,   52,   52,   52,
159                 53,   53,   53,   53,   53,   54,   54,   54,
160                 54,   54,   55,   55,   55,   55,   55,   55,
161                 56,   56,   56,   56,   56,   57,   57,   57,
162                 57,   57,   57,   58,   58,   58,   58,   58,
163                 58,   59,   59,   59,   59,   59,   59,   60,
164                 60,   60,   60,   60,   60,   61,   61,   61,
165                 61,   61,   61,   62,   62,   62,   62,   62,
166                 62,   63,   63,   63,   63,   63,   63,   64,
167                 64,   64,   64,   64,   64,   64,   65,   65,
168                 65,   65,   65,   65,   66,   66,   66,   66,
169                 66,   66,   66,   67,   67,   67,   67,   67,
170                 67,   67,   68,   68,   68,   68,   68,   68,
171                 68,   69,   69,   69,   69,   69,   69,   69,
172                 70,   70,   70,   70,   70,   70,   70,   71,
173                 71,   71,   71,   71,   71,   71,   72,   72,
174                 72,   72,   72,   72,   72,   72,   73,   73,
175                 73,   73,   73,   73,   73,   74,   74,   74,
176                 74,   74,   74,   74,   74,   75,   75,   75,
177                 75,   75,   75,   75,   75,   76,   76,   76,
178                 76,   76,   76,   76,   77,   77,   77,   77,
179                 77,   77,   77,   77,   78,   78,   78,   78,
180                 78,   78,   78,   78,   78,   79,   79,   79,
181                 79,   79,   79,   79,   79,   80,   80,   80,
182                 80,   80,   80,   80,   80,   81,   81,   81,
183                 81,   81,   81,   81,   81,   81,   82,   82,
184                 82,   82,   82,   82,   82,   82,   83,   83,
185                 83,   83,   83,   83,   83,   83,   83,   84,
186                 84,   84,   84,   84,   84,   84,   84,   84,
187                 85,   85,   85,   85,   85,   85,   85,   85,
188                 85,   86,   86,   86,   86,   86,   86,   86,
189                 86,   86,   87,   87,   87,   87,   87,   87,
190                 87,   87,   87,   88,   88,   88,   88,   88,
191                 88,   88,   88,   88,   88,   89,   89,   89,
192                 89,   89,   89,   89,   89,   89,   90,   90,
193                 90,   90,   90,   90,   90,   90,   90,   90,
194                 91,   91,   91,   91,   91,   91,   91,   91,
195                 91,   91,   92,   92,   92,   92,   92,   92,
196                 92,   92,   92,   92,   93,   93,   93,   93,
197                 93,   93,   93,   93,   93,   93,   94,   94,
198                 94,   94,   94,   94,   94,   94,   94,   94,
199                 95,   95,   95,   95,   95,   95,   95,   95,
200                 95,   95,   96,   96,   96,   96,   96,   96,
201                 96,   96,   96,   96,   96,   97,   97,   97,
202                 97,   97,   97,   97,   97,   97,   97,   98,
203                 98,   98,   98,   98,   98,   98,   98,   98,
204                 98,   98,   99,   99,   99,   99,   99,   99,
205                 99,   100,  101,  101,  102,  103,  103,  104,
206                 105,  105,  106,  107,  107,  108,  109,  109,
207                 110,  111,  111,  112,  113,  113,  114,  115,
208                 115,  116,  116,  117,  118,  118,  119,  119,
209                 120,  120,  121,  122,  122,  123,  123,  124,
210                 124,  125,  126,  126,  127,  127,  128,  128,
211                 129,  129,  130,  130,  131,  131,  132,  132,
212                 133,  133,  134,  134,  135,  135,  136,  136,
213                 137,  137,  138,  138,  139,  139,  140,  140,
214                 141,  141,  142,  142,  143,  143,  144,  144,
215                 145,  145,  145,  146,  146,  147,  147,  148,
216                 148,  149,  149,  150,  150,  150,  151,  151,
217                 152,  152,  153,  153,  153,  154,  154,  155,
218                 155,  156,  156,  156,  157,  157,  158,  158,
219                 158,  159,  159,  160,  160,  160,  161,  161,
220                 162,  162,  162,  163,  163,  164,  164,  164,
221                 165,  165,  166,  166,  166,  167,  167,  167,
222                 168,  168,  169,  169,  169,  170,  170,  170,
223                 171,  171,  172,  172,  172,  173,  173,  173,
224                 174,  174,  174,  175,  175,  176,  176,  176,
225                 177,  177,  177,  178,  178,  178,  179,  179,
226                 179,  180,  180,  180,  181,  181,  182,  182,
227                 182,  183,  183,  183,  184,  184,  184,  185,
228                 185,  185,  186,  186,  186,  187,  187,  187,
229                 188,  188,  188,  189,  189,  189,  189,  190,
230                 190,  190,  191,  191,  191,  192,  192,  192,
231                 193,  193,  193,  194,  194,  194,  195,  195,
232                 195,  196,  196,  196,  196,  197,  197,  197,
233                 198,  198,  198,  199,  199,  199,  200,  200,
234                 200,  200,  201,  201,  201,  202,  202,  202,
235                 202,  203,  203,  203,  204,  204,  204,  205,
236                 205,  205,  205,  206,  206,  206,  207,  207,
237                 207,  207,  208,  208,  208,  209,  209,  209,
238                 209,  210,  210,  210,  211,  211,  211,  211,
239                 212,  212,  212,  213,  213,  213,  213,  214,
240                 214,  214,  214,  215,  215,  215,  216,  216,
241                 216,  216,  217,  217,  217,  217,  218,  218,
242                 218,  219,  219,  219,  219,  220,  220,  220,
243                 220,  221,  221,  221,  221,  222,  222,  222,
244                 223,  223,  223,  223,  224,  224,  224,  224,
245                 225,  225,  225,  225,  226,  226,  226,  226,
246                 227,  227,  227,  227,  228,  228,  228,  228,
247                 229,  229,  229,  229,  230,  230,  230,  230,
248                 231,  231,  231,  231,  232,  232,  232,  232,
249                 233,  233,  233,  233,  234,  234,  234,  234,
250                 235,  235,  235,  235,  236,  236,  236,  236,
251                 237,  237,  237,  237,  238,  238,  238,  238,
252                 239,  239,  239,  239,  240,  240,  240,  240,
253                 240,  241,  241,  241,  241,  242,  242,  242,
254                 242,  243,  243,  243,  243,  244,  244,  244,
255                 244,  244,  245,  245,  245,  245,  246,  246,
256                 246,  246,  247,  247,  247,  247,  247,  248,
257                 248,  248,  248,  249,  249,  249,  249,  249,
258                 250,  250,  250,  250,  251,  251,  251,  251,
259                 251,  252,  252,  252,  252,  253,  253,  253,
260                 253,  253,  254,  254,  254,  254,  255,  255,
261         },
262 };
263 #endif
264
265 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
266 {
267         if (!tegra_is_clk_enabled(dc->clk)) {
268                 clk_enable(dc->clk);
269                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
270         }
271 }
272
273 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
274 {
275         if (tegra_is_clk_enabled(dc->clk)) {
276                 clk_disable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, 0);
278         }
279 }
280
281 #define DUMP_REG(a) do {                        \
282         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
283                  #a, a, tegra_dc_readl(dc, a));               \
284         print(data, buff);                                    \
285         } while (0)
286
287 #define print_underflow_info(dc) do {                 \
288         trace_printk("%s:Underflow stats: underflows : %llu, "      \
289                         "undeflows_a : %llu, "                          \
290                         "underflows_b : %llu, "                         \
291                         "underflows_c : %llu\n",                        \
292                         dc->ndev->name,                                 \
293                         dc->stats.underflows,                           \
294                         dc->stats.underflows_a, dc->stats.underflows_b, \
295                         dc->stats.underflows_c);                        \
296         } while (0)
297
298 static void _dump_regs(struct tegra_dc *dc, void *data,
299                        void (* print)(void *data, const char *str))
300 {
301         int i;
302         char buff[256];
303
304         tegra_dc_io_start(dc);
305         tegra_dc_clk_enable(dc);
306
307         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
308         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
309         DUMP_REG(DC_CMD_SIGNAL_RAISE);
310         DUMP_REG(DC_CMD_INT_STATUS);
311         DUMP_REG(DC_CMD_INT_MASK);
312         DUMP_REG(DC_CMD_INT_ENABLE);
313         DUMP_REG(DC_CMD_INT_TYPE);
314         DUMP_REG(DC_CMD_INT_POLARITY);
315         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
318         DUMP_REG(DC_CMD_STATE_ACCESS);
319         DUMP_REG(DC_CMD_STATE_CONTROL);
320         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
321         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
322
323         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
324         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
325         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
326         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
327         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
328         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
329         DUMP_REG(DC_DISP_REF_TO_SYNC);
330         DUMP_REG(DC_DISP_SYNC_WIDTH);
331         DUMP_REG(DC_DISP_BACK_PORCH);
332         DUMP_REG(DC_DISP_DISP_ACTIVE);
333         DUMP_REG(DC_DISP_FRONT_PORCH);
334         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
335         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
336         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
337         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
338         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
339         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
340         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
341         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
342         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
343         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
344         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
345         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
346         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
347         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
348         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
349         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
350         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
351         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
352         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
353         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
354         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
355         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
356         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
357         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
360         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
361         DUMP_REG(DC_DISP_M0_CONTROL);
362         DUMP_REG(DC_DISP_M1_CONTROL);
363         DUMP_REG(DC_DISP_DI_CONTROL);
364         DUMP_REG(DC_DISP_PP_CONTROL);
365         DUMP_REG(DC_DISP_PP_SELECT_A);
366         DUMP_REG(DC_DISP_PP_SELECT_B);
367         DUMP_REG(DC_DISP_PP_SELECT_C);
368         DUMP_REG(DC_DISP_PP_SELECT_D);
369         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
370         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
371         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
372         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
373         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
374         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
375         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
376         DUMP_REG(DC_DISP_BORDER_COLOR);
377         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
378         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
379         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
380         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
381         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
382         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
383         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
384         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
385         DUMP_REG(DC_DISP_CURSOR_POSITION);
386         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
387         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
388         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
389         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
390         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
391         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
392         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
393         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
394         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
395         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
396         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
397         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
398         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
399
400
401         for (i = 0; i < 3; i++) {
402                 print(data, "\n");
403                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
404                 print(data, buff);
405
406                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
407                                 DC_CMD_DISPLAY_WINDOW_HEADER);
408                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
409                 DUMP_REG(DC_WIN_WIN_OPTIONS);
410                 DUMP_REG(DC_WIN_BYTE_SWAP);
411                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
412                 DUMP_REG(DC_WIN_COLOR_DEPTH);
413                 DUMP_REG(DC_WIN_POSITION);
414                 DUMP_REG(DC_WIN_SIZE);
415                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
416                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
417                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
418                 DUMP_REG(DC_WIN_DDA_INCREMENT);
419                 DUMP_REG(DC_WIN_LINE_STRIDE);
420 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
421                 DUMP_REG(DC_WIN_BUF_STRIDE);
422                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
423 #endif
424                 DUMP_REG(DC_WIN_BLEND_NOKEY);
425                 DUMP_REG(DC_WIN_BLEND_1WIN);
426                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
427                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
428                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
429                 DUMP_REG(DC_WINBUF_START_ADDR);
430                 DUMP_REG(DC_WINBUF_START_ADDR_U);
431                 DUMP_REG(DC_WINBUF_START_ADDR_V);
432                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
433                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
434                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
435                 DUMP_REG(DC_WIN_CSC_YOF);
436                 DUMP_REG(DC_WIN_CSC_KYRGB);
437                 DUMP_REG(DC_WIN_CSC_KUR);
438                 DUMP_REG(DC_WIN_CSC_KVR);
439                 DUMP_REG(DC_WIN_CSC_KUG);
440                 DUMP_REG(DC_WIN_CSC_KVG);
441                 DUMP_REG(DC_WIN_CSC_KUB);
442                 DUMP_REG(DC_WIN_CSC_KVB);
443         }
444
445         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
446         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
447         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
448         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
449         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
450         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
451         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
452         DUMP_REG(DC_DISP_M1_CONTROL);
453         DUMP_REG(DC_COM_PM1_CONTROL);
454         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
455         DUMP_REG(DC_DISP_SD_CONTROL);
456
457         tegra_dc_clk_disable(dc);
458         tegra_dc_io_end(dc);
459 }
460
461 #undef DUMP_REG
462
463 #ifdef DEBUG
464 static void dump_regs_print(void *data, const char *str)
465 {
466         struct tegra_dc *dc = data;
467         dev_dbg(&dc->ndev->dev, "%s", str);
468 }
469
470 static void dump_regs(struct tegra_dc *dc)
471 {
472         _dump_regs(dc, dc, dump_regs_print);
473 }
474 #else /* !DEBUG */
475
476 static void dump_regs(struct tegra_dc *dc) {}
477
478 #endif /* DEBUG */
479
480 #ifdef CONFIG_DEBUG_FS
481
482 static void dbg_regs_print(void *data, const char *str)
483 {
484         struct seq_file *s = data;
485
486         seq_printf(s, "%s", str);
487 }
488
489 #undef DUMP_REG
490
491 static int dbg_dc_show(struct seq_file *s, void *unused)
492 {
493         struct tegra_dc *dc = s->private;
494
495         _dump_regs(dc, s, dbg_regs_print);
496
497         return 0;
498 }
499
500
501 static int dbg_dc_open(struct inode *inode, struct file *file)
502 {
503         return single_open(file, dbg_dc_show, inode->i_private);
504 }
505
506 static const struct file_operations regs_fops = {
507         .open           = dbg_dc_open,
508         .read           = seq_read,
509         .llseek         = seq_lseek,
510         .release        = single_release,
511 };
512
513 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
514 {
515         struct tegra_dc *dc = s->private;
516         struct tegra_dc_mode *m;
517
518         mutex_lock(&dc->lock);
519         m = &dc->mode;
520         seq_printf(s,
521                 "pclk: %d\n"
522                 "h_ref_to_sync: %d\n"
523                 "v_ref_to_sync: %d\n"
524                 "h_sync_width: %d\n"
525                 "v_sync_width: %d\n"
526                 "h_back_porch: %d\n"
527                 "v_back_porch: %d\n"
528                 "h_active: %d\n"
529                 "v_active: %d\n"
530                 "h_front_porch: %d\n"
531                 "v_front_porch: %d\n"
532                 "stereo_mode: %d\n",
533                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
534                 m->h_sync_width, m->v_sync_width,
535                 m->h_back_porch, m->v_back_porch,
536                 m->h_active, m->v_active,
537                 m->h_front_porch, m->v_front_porch,
538                 m->stereo_mode);
539         mutex_unlock(&dc->lock);
540         return 0;
541 }
542
543 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
544 {
545         return single_open(file, dbg_dc_mode_show, inode->i_private);
546 }
547
548 static const struct file_operations mode_fops = {
549         .open           = dbg_dc_mode_open,
550         .read           = seq_read,
551         .llseek         = seq_lseek,
552         .release        = single_release,
553 };
554
555 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
556 {
557         struct tegra_dc *dc = s->private;
558
559         mutex_lock(&dc->lock);
560         seq_printf(s,
561                 "underflows: %llu\n"
562                 "underflows_a: %llu\n"
563                 "underflows_b: %llu\n"
564                 "underflows_c: %llu\n",
565                 dc->stats.underflows,
566                 dc->stats.underflows_a,
567                 dc->stats.underflows_b,
568                 dc->stats.underflows_c);
569         mutex_unlock(&dc->lock);
570
571         return 0;
572 }
573
574 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
575 {
576         return single_open(file, dbg_dc_stats_show, inode->i_private);
577 }
578
579 static const struct file_operations stats_fops = {
580         .open           = dbg_dc_stats_open,
581         .read           = seq_read,
582         .llseek         = seq_lseek,
583         .release        = single_release,
584 };
585
586 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
587 {
588         if (dc->debugdir)
589                 debugfs_remove_recursive(dc->debugdir);
590         dc->debugdir = NULL;
591 }
592
593 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
594 {
595         struct dentry *retval;
596
597         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
598         if (!dc->debugdir)
599                 goto remove_out;
600
601         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
602                 &regs_fops);
603         if (!retval)
604                 goto remove_out;
605
606         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
607                 &mode_fops);
608         if (!retval)
609                 goto remove_out;
610
611         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
612                 &stats_fops);
613         if (!retval)
614                 goto remove_out;
615
616         return;
617 remove_out:
618         dev_err(&dc->ndev->dev, "could not create debugfs\n");
619         tegra_dc_remove_debugfs(dc);
620 }
621
622 #else /* !CONFIG_DEBUGFS */
623 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
624 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
625 #endif /* CONFIG_DEBUGFS */
626
627 static int tegra_dc_set(struct tegra_dc *dc, int index)
628 {
629         int ret = 0;
630
631         mutex_lock(&tegra_dc_lock);
632         if (index >= TEGRA_MAX_DC) {
633                 ret = -EINVAL;
634                 goto out;
635         }
636
637         if (dc != NULL && tegra_dcs[index] != NULL) {
638                 ret = -EBUSY;
639                 goto out;
640         }
641
642         tegra_dcs[index] = dc;
643
644 out:
645         mutex_unlock(&tegra_dc_lock);
646
647         return ret;
648 }
649
650 unsigned int tegra_dc_has_multiple_dc(void)
651 {
652         unsigned int idx;
653         unsigned int cnt = 0;
654         struct tegra_dc *dc;
655
656         mutex_lock(&tegra_dc_lock);
657         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
658                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
659         mutex_unlock(&tegra_dc_lock);
660
661         return (cnt > 1);
662 }
663
664 /* get the stride size of a window.
665  * return: stride size in bytes for window win. or 0 if unavailble. */
666 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
667 {
668         u32 stride;
669
670         if (!dc->enabled)
671                 return 0;
672         BUG_ON(win > DC_N_WINDOWS);
673         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
674                 DC_CMD_DISPLAY_WINDOW_HEADER);
675         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
676         return GET_LINE_STRIDE(stride);
677 }
678 EXPORT_SYMBOL(tegra_dc_get_stride);
679
680 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
681 {
682         if (idx < TEGRA_MAX_DC)
683                 return tegra_dcs[idx];
684         else
685                 return NULL;
686 }
687 EXPORT_SYMBOL(tegra_dc_get_dc);
688
689 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
690 {
691         if (win >= dc->n_windows)
692                 return NULL;
693
694         return &dc->windows[win];
695 }
696 EXPORT_SYMBOL(tegra_dc_get_window);
697
698 bool tegra_dc_get_connected(struct tegra_dc *dc)
699 {
700         return dc->connected;
701 }
702 EXPORT_SYMBOL(tegra_dc_get_connected);
703
704 bool tegra_dc_hpd(struct tegra_dc *dc)
705 {
706         int sense;
707         int level;
708
709         level = gpio_get_value(dc->out->hotplug_gpio);
710
711         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
712
713         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
714                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
715 }
716 EXPORT_SYMBOL(tegra_dc_hpd);
717
718 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
719 {
720         unsigned i;
721         unsigned v0 = 128;
722         unsigned v1 = 0;
723         /* linear horizontal and vertical filters */
724         for (i = 0; i < 16; i++) {
725                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
726                                 DC_WIN_H_FILTER_P(i));
727
728                 tegra_dc_writel(dc, v0,
729                                 DC_WIN_V_FILTER_P(i));
730                 v0 -= 8;
731                 v1 += 8;
732         }
733 }
734
735 #ifdef CONFIG_TEGRA_DC_CMU
736 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
737                                                 struct tegra_dc_cmu *src_cmu)
738 {
739         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
740 }
741
742 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
743 {
744         u32 val;
745         u32 i;
746
747         for (i = 0; i < 256; i++) {
748                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
749                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
750         }
751
752         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
753         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
754         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
755         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
756         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
757         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
758         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
759         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
760         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
761
762         for (i = 0; i < 960; i++) {
763                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
764                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
765         }
766 }
767
768 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
769 {
770         u32 val;
771         u32 i;
772         bool flags;
773
774         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
775         if (val & CMU_ENABLE)
776                 flags = true;
777
778         val &= ~CMU_ENABLE;
779         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
780         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
781         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
782
783         /*TODO: Sync up with frame end */
784         mdelay(20);
785
786         for (i = 0; i < 256; i++) {
787                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
788                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
789                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
790                 cmu->lut1[i] = LUT1_READ_DATA(val);
791         }
792
793         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
794         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
795         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
796         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
797         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
798         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
799         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
800         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
801         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
802
803         for (i = 0; i < 960; i++) {
804                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
805                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
806                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
807                 cmu->lut2[i] = LUT2_READ_DATA(val);
808         }
809 }
810
811 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
812 {
813         mutex_lock(&dc->lock);
814
815         if (!dc->enabled) {
816                 mutex_unlock(&dc->lock);
817                 return -EFAULT;
818         }
819
820         if (cmu_enable) {
821                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
822         } else {
823                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
824                 return 0;
825         }
826
827         tegra_dc_set_cmu(dc, &dc->cmu);
828
829         mutex_unlock(&dc->lock);
830
831         return 0;
832 }
833 EXPORT_SYMBOL(tegra_dc_update_cmu);
834 #else
835 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
836 #define tegra_dc_set_cmu(dc, cmu)
837 #endif
838
839 void tegra_dc_host_suspend(struct tegra_dc *dc)
840 {
841         tegra_dsi_host_suspend(dc);
842         tegra_dc_clk_disable(dc);
843 }
844
845 void tegra_dc_host_resume(struct tegra_dc *dc) {
846         tegra_dc_clk_enable(dc);
847         tegra_dsi_host_resume(dc);
848 }
849
850 static inline void disable_dc_irq(unsigned int irq)
851 {
852         disable_irq(irq);
853 }
854
855 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
856 {
857         return dc->syncpt[i].id;
858 }
859 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
860
861 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
862 {
863         u32 max;
864
865         mutex_lock(&dc->lock);
866         max = nvhost_syncpt_incr_max_ext(dc->ndev,
867                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
868         dc->syncpt[i].max = max;
869         mutex_unlock(&dc->lock);
870
871         return max;
872 }
873
874 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
875 {
876         mutex_lock(&dc->lock);
877         if ( dc->enabled )
878                 while (dc->syncpt[i].min < val) {
879                         dc->syncpt[i].min++;
880                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
881                 }
882         mutex_unlock(&dc->lock);
883 }
884
885 void
886 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
887 {
888         unsigned int ctrl;
889         unsigned long out_sel;
890         unsigned long cmd_state;
891
892         mutex_lock(&dc->lock);
893         if (!dc->enabled) {
894                 mutex_unlock(&dc->lock);
895                 return;
896         }
897
898         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
899                 tegra_dc_host_resume(dc);
900
901         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
902                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
903                 cfg->clk_select);
904
905         /* The new value should be effected immediately */
906         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
907         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
908
909         switch (cfg->which_pwm) {
910         case TEGRA_PWM_PM0:
911                 /* Select the LM0 on PM0 */
912                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
913                 out_sel &= ~(7 << 0);
914                 out_sel |= (3 << 0);
915                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
916                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
917                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
918                 break;
919         case TEGRA_PWM_PM1:
920                 /* Select the LM1 on PM1 */
921                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
922                 out_sel &= ~(7 << 4);
923                 out_sel |= (3 << 4);
924                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
925                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
926                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
927                 break;
928         default:
929                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
930                 break;
931         }
932         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
933         mutex_unlock(&dc->lock);
934 }
935 EXPORT_SYMBOL(tegra_dc_config_pwm);
936
937 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
938                                 const struct tegra_dc_out_pin *pins,
939                                 const unsigned int n_pins)
940 {
941         unsigned int i;
942
943         int name;
944         int pol;
945
946         u32 pol1, pol3;
947
948         u32 set1, unset1;
949         u32 set3, unset3;
950
951         set1 = set3 = unset1 = unset3 = 0;
952
953         for (i = 0; i < n_pins; i++) {
954                 name = (pins + i)->name;
955                 pol  = (pins + i)->pol;
956
957                 /* set polarity by name */
958                 switch (name) {
959                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
960                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
961                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
962                         else
963                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
964                         break;
965                 case TEGRA_DC_OUT_PIN_H_SYNC:
966                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
967                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
968                         else
969                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
970                         break;
971                 case TEGRA_DC_OUT_PIN_V_SYNC:
972                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
973                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
974                         else
975                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
976                         break;
977                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
978                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
979                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
980                         else
981                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
982                         break;
983                 default:
984                         printk("Invalid argument in function %s\n",
985                                __FUNCTION__);
986                         break;
987                 }
988         }
989
990         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
991         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
992
993         pol1 |= set1;
994         pol1 &= ~unset1;
995
996         pol3 |= set3;
997         pol3 &= ~unset3;
998
999         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1000         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1001 }
1002
1003 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1004 {
1005         dc->out = out;
1006
1007         if (out->n_modes > 0)
1008                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1009
1010         switch (out->type) {
1011         case TEGRA_DC_OUT_RGB:
1012                 dc->out_ops = &tegra_dc_rgb_ops;
1013                 break;
1014
1015         case TEGRA_DC_OUT_HDMI:
1016                 dc->out_ops = &tegra_dc_hdmi_ops;
1017                 break;
1018
1019         case TEGRA_DC_OUT_DSI:
1020                 dc->out_ops = &tegra_dc_dsi_ops;
1021                 break;
1022
1023         default:
1024                 dc->out_ops = NULL;
1025                 break;
1026         }
1027
1028         if (dc->out_ops && dc->out_ops->init)
1029                 dc->out_ops->init(dc);
1030
1031 }
1032
1033 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1034 {
1035         if (dc->out)
1036                 return dc->out->height;
1037         else
1038                 return 0;
1039 }
1040 EXPORT_SYMBOL(tegra_dc_get_out_height);
1041
1042 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1043 {
1044         if (dc->out)
1045                 return dc->out->width;
1046         else
1047                 return 0;
1048 }
1049 EXPORT_SYMBOL(tegra_dc_get_out_width);
1050
1051 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1052 {
1053         if (dc->out && dc->out->max_pixclock)
1054                 return dc->out->max_pixclock;
1055         else
1056                 return 0;
1057 }
1058 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1059
1060 void tegra_dc_enable_crc(struct tegra_dc *dc)
1061 {
1062         u32 val;
1063         tegra_dc_io_start(dc);
1064
1065         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1066                 CRC_ENABLE_ENABLE;
1067         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1068         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1069         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1070 }
1071
1072 void tegra_dc_disable_crc(struct tegra_dc *dc)
1073 {
1074         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1075         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1076         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1077
1078         tegra_dc_io_end(dc);
1079 }
1080
1081 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1082 {
1083         int crc = 0;
1084
1085         if (!dc) {
1086                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1087                 goto crc_error;
1088         }
1089
1090 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1091         /* TODO: Replace mdelay with code to sync VBlANK, since
1092          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1093         mdelay(TEGRA_CRC_LATCHED_DELAY);
1094 #endif
1095
1096         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1097 crc_error:
1098         return crc;
1099 }
1100
1101 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1102 {
1103 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1104         u32 val;
1105
1106         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1107         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1108             return true;
1109 #endif
1110         return false;
1111 }
1112
1113 static inline void enable_dc_irq(unsigned int irq)
1114 {
1115 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1116         enable_irq(irq);
1117 #else
1118         /* Always disable DC interrupts on FPGA. */
1119         disable_irq(irq);
1120 #endif
1121 }
1122
1123 static void tegra_dc_vblank(struct work_struct *work)
1124 {
1125         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1126         bool nvsd_updated = false;
1127
1128         mutex_lock(&dc->lock);
1129
1130         if (!dc->enabled) {
1131                 mutex_unlock(&dc->lock);
1132                 return;
1133         }
1134
1135         /* use the new frame's bandwidth setting instead of max(current, new),
1136          * skip this if we're using tegra_dc_one_shot_worker() */
1137         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1138                 tegra_dc_program_bandwidth(dc, true);
1139
1140         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1141         if (!tegra_dc_windows_are_dirty(dc))
1142                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1143
1144         /* Update the SD brightness */
1145         if (dc->enabled && dc->out->sd_settings) {
1146                 nvsd_updated = nvsd_update_brightness(dc);
1147                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1148                  * V_BLANK_NVSD bit of vblank ref-count. */
1149                 if (nvsd_updated) {
1150                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1151                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1152                 } else {
1153                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1154                 }
1155         }
1156
1157         /* Mask vblank interrupt if ref-count is zero. */
1158         if (!dc->vblank_ref_count)
1159                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1160
1161         mutex_unlock(&dc->lock);
1162
1163         /* Do the actual brightness update outside of the mutex */
1164         if (nvsd_updated && dc->out->sd_settings &&
1165             dc->out->sd_settings->bl_device) {
1166
1167                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1168                 struct backlight_device *bl = platform_get_drvdata(pdev);
1169                 if (bl)
1170                         backlight_update_status(bl);
1171         }
1172 }
1173
1174 static void tegra_dc_one_shot_worker(struct work_struct *work)
1175 {
1176         struct tegra_dc *dc = container_of(
1177                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1178         mutex_lock(&dc->lock);
1179
1180         /* memory client has gone idle */
1181         tegra_dc_clear_bandwidth(dc);
1182
1183         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1184                 tegra_dc_host_suspend(dc);
1185
1186         mutex_unlock(&dc->lock);
1187 }
1188
1189 /* return an arbitrarily large number if count overflow occurs.
1190  * make it a nice base-10 number to show up in stats output */
1191 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1192 {
1193         unsigned count = tegra_dc_readl(dc, reg);
1194         tegra_dc_writel(dc, 0, reg);
1195         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1196 }
1197
1198 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1199 {
1200         u32 val;
1201         int i;
1202
1203         dc->stats.underflows++;
1204         if (dc->underflow_mask & WIN_A_UF_INT) {
1205                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1206                         DC_WINBUF_AD_UFLOW_STATUS);
1207                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1208         }
1209         if (dc->underflow_mask & WIN_B_UF_INT) {
1210                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1211                         DC_WINBUF_BD_UFLOW_STATUS);
1212                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1213         }
1214         if (dc->underflow_mask & WIN_C_UF_INT) {
1215                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1216                         DC_WINBUF_CD_UFLOW_STATUS);
1217                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1218         }
1219
1220         /* Check for any underflow reset conditions */
1221         for (i = 0; i < DC_N_WINDOWS; i++) {
1222                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1223                         dc->windows[i].underflows++;
1224
1225 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1226                         if (dc->windows[i].underflows > 4) {
1227                                 schedule_work(&dc->reset_work);
1228                                 /* reset counter */
1229                                 dc->windows[i].underflows = 0;
1230                                 trace_printk("%s:Reset work scheduled for "
1231                                                 "window %c\n",
1232                                                 dc->ndev->name, (65 + i));
1233                         }
1234 #endif
1235 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1236                         if (dc->windows[i].underflows > 4) {
1237                                 printk("%s:dc in underflow state."
1238                                         " enable UF_LINE_FLUSH to clear up\n",
1239                                         __func__);
1240                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1241                                                 DC_DISP_DISP_MISC_CONTROL);
1242                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1243                                                 DC_CMD_STATE_CONTROL);
1244                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1245                                                 DC_CMD_STATE_CONTROL);
1246
1247                                 tegra_dc_writel(dc, 0,
1248                                                 DC_DISP_DISP_MISC_CONTROL);
1249                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1250                                                 DC_CMD_STATE_CONTROL);
1251                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1252                                                 DC_CMD_STATE_CONTROL);
1253                         }
1254 #endif
1255                 } else {
1256                         dc->windows[i].underflows = 0;
1257                 }
1258         }
1259
1260         /* Clear the underflow mask now that we've checked it. */
1261         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1262         dc->underflow_mask = 0;
1263         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1264         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1265         print_underflow_info(dc);
1266 }
1267
1268 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1269 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1270 {
1271         if (status & V_BLANK_INT) {
1272                 /* Sync up windows. */
1273                 tegra_dc_trigger_windows(dc);
1274
1275                 /* Schedule any additional bottom-half vblank actvities. */
1276                 schedule_work(&dc->vblank_work);
1277         }
1278
1279         if (status & FRAME_END_INT) {
1280                 /* Mark the frame_end as complete. */
1281                 if (!completion_done(&dc->frame_end_complete))
1282                         complete(&dc->frame_end_complete);
1283         }
1284 }
1285
1286 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1287 {
1288         /* Schedule any additional bottom-half vblank actvities. */
1289         if (status & V_BLANK_INT)
1290                 schedule_work(&dc->vblank_work);
1291
1292         if (status & FRAME_END_INT) {
1293                 /* Mark the frame_end as complete. */
1294                 if (!completion_done(&dc->frame_end_complete))
1295                         complete(&dc->frame_end_complete);
1296
1297                 tegra_dc_trigger_windows(dc);
1298         }
1299 }
1300 #endif
1301
1302 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1303 {
1304 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1305         struct tegra_dc *dc = ptr;
1306         unsigned long status;
1307         unsigned long underflow_mask;
1308         u32 val;
1309
1310         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1311                 WARN(1, "IRQ when DC not powered!\n");
1312                 tegra_dc_io_start(dc);
1313                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1314                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1315                 tegra_dc_io_end(dc);
1316                 return IRQ_HANDLED;
1317         }
1318
1319         /* clear all status flags except underflow, save those for the worker */
1320         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1321         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1322         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1323         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1324
1325         /*
1326          * Overlays can get thier internal state corrupted during and underflow
1327          * condition.  The only way to fix this state is to reset the DC.
1328          * if we get 4 consecutive frames with underflows, assume we're
1329          * hosed and reset.
1330          */
1331         underflow_mask = status & ALL_UF_INT;
1332
1333         /* Check underflow */
1334         if (underflow_mask) {
1335                 dc->underflow_mask |= underflow_mask;
1336                 schedule_delayed_work(&dc->underflow_work,
1337                         msecs_to_jiffies(1));
1338         }
1339
1340         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1341                 tegra_dc_one_shot_irq(dc, status);
1342         else
1343                 tegra_dc_continuous_irq(dc, status);
1344
1345         return IRQ_HANDLED;
1346 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1347         return IRQ_NONE;
1348 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1349 }
1350
1351 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1352 {
1353         u32 color_control;
1354
1355         switch (dc->out->depth) {
1356         case 3:
1357                 color_control = BASE_COLOR_SIZE111;
1358                 break;
1359
1360         case 6:
1361                 color_control = BASE_COLOR_SIZE222;
1362                 break;
1363
1364         case 8:
1365                 color_control = BASE_COLOR_SIZE332;
1366                 break;
1367
1368         case 9:
1369                 color_control = BASE_COLOR_SIZE333;
1370                 break;
1371
1372         case 12:
1373                 color_control = BASE_COLOR_SIZE444;
1374                 break;
1375
1376         case 15:
1377                 color_control = BASE_COLOR_SIZE555;
1378                 break;
1379
1380         case 16:
1381                 color_control = BASE_COLOR_SIZE565;
1382                 break;
1383
1384         case 18:
1385                 color_control = BASE_COLOR_SIZE666;
1386                 break;
1387
1388         default:
1389                 color_control = BASE_COLOR_SIZE888;
1390                 break;
1391         }
1392
1393         switch (dc->out->dither) {
1394         case TEGRA_DC_DISABLE_DITHER:
1395                 color_control |= DITHER_CONTROL_DISABLE;
1396                 break;
1397         case TEGRA_DC_ORDERED_DITHER:
1398                 color_control |= DITHER_CONTROL_ORDERED;
1399                 break;
1400         case TEGRA_DC_ERRDIFF_DITHER:
1401                 /* The line buffer for error-diffusion dither is limited
1402                  * to 1280 pixels per line. This limits the maximum
1403                  * horizontal active area size to 1280 pixels when error
1404                  * diffusion is enabled.
1405                  */
1406                 BUG_ON(dc->mode.h_active > 1280);
1407                 color_control |= DITHER_CONTROL_ERRDIFF;
1408                 break;
1409         }
1410
1411 #ifdef CONFIG_TEGRA_DC_CMU
1412         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
1413                 color_control |= CMU_ENABLE;
1414 #endif
1415
1416         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1417 }
1418
1419 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1420 {
1421         u32 syncpt_id;
1422
1423         switch (dc->ndev->id) {
1424         case 0:
1425                 switch (idx) {
1426                 case 0:
1427                         syncpt_id = NVSYNCPT_DISP0_A;
1428                         break;
1429                 case 1:
1430                         syncpt_id = NVSYNCPT_DISP0_B;
1431                         break;
1432                 case 2:
1433                         syncpt_id = NVSYNCPT_DISP0_C;
1434                         break;
1435                 default:
1436                         BUG();
1437                         break;
1438                 }
1439                 break;
1440         case 1:
1441                 switch (idx) {
1442                 case 0:
1443                         syncpt_id = NVSYNCPT_DISP1_A;
1444                         break;
1445                 case 1:
1446                         syncpt_id = NVSYNCPT_DISP1_B;
1447                         break;
1448                 case 2:
1449                         syncpt_id = NVSYNCPT_DISP1_C;
1450                         break;
1451                 default:
1452                         BUG();
1453                         break;
1454                 }
1455                 break;
1456         default:
1457                 BUG();
1458                 break;
1459         }
1460
1461         return syncpt_id;
1462 }
1463
1464 static int tegra_dc_init(struct tegra_dc *dc)
1465 {
1466         int i;
1467
1468         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1469         if (dc->ndev->id == 0) {
1470                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1471                                       TEGRA_MC_PRIO_MED);
1472                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1473                                       TEGRA_MC_PRIO_MED);
1474                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1475                                       TEGRA_MC_PRIO_MED);
1476                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1477                                       TEGRA_MC_PRIO_MED);
1478                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1479                                       TEGRA_MC_PRIO_HIGH);
1480         } else if (dc->ndev->id == 1) {
1481                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1482                                       TEGRA_MC_PRIO_MED);
1483                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1484                                       TEGRA_MC_PRIO_MED);
1485                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1486                                       TEGRA_MC_PRIO_MED);
1487                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1488                                       TEGRA_MC_PRIO_MED);
1489                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1490                                       TEGRA_MC_PRIO_HIGH);
1491         }
1492         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1493                         DC_CMD_CONT_SYNCPT_VSYNC);
1494         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1495         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1496         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1497         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1498 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1499         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1500 #endif
1501         /* enable interrupts for vblank, frame_end and underflows */
1502         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1503                 DC_CMD_INT_ENABLE);
1504         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1505
1506         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1507
1508         tegra_dc_set_color_control(dc);
1509         for (i = 0; i < DC_N_WINDOWS; i++) {
1510                 struct tegra_dc_win *win = &dc->windows[i];
1511                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1512                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1513                 tegra_dc_set_csc(dc, &win->csc);
1514                 tegra_dc_set_lut(dc, win);
1515                 tegra_dc_set_scaling_filter(dc);
1516         }
1517
1518         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
1519         tegra_dc_set_cmu(dc, &dc->cmu);
1520
1521         for (i = 0; i < dc->n_windows; i++) {
1522                 u32 syncpt = get_syncpt(dc, i);
1523
1524                 dc->syncpt[i].id = syncpt;
1525
1526                 dc->syncpt[i].min = dc->syncpt[i].max =
1527                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1528         }
1529
1530         print_mode_info(dc, dc->mode);
1531
1532         if (dc->mode.pclk)
1533                 if (tegra_dc_program_mode(dc, &dc->mode))
1534                         return -EINVAL;
1535
1536         /* Initialize SD AFTER the modeset.
1537            nvsd_init handles the sd_settings = NULL case. */
1538         nvsd_init(dc, dc->out->sd_settings);
1539
1540         return 0;
1541 }
1542
1543 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1544 {
1545         int failed_init = 0;
1546
1547         if (dc->out->enable)
1548                 dc->out->enable();
1549
1550         tegra_dc_setup_clk(dc, dc->clk);
1551         tegra_dc_clk_enable(dc);
1552
1553         /* do not accept interrupts during initialization */
1554         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1555         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1556
1557         enable_dc_irq(dc->irq);
1558
1559         failed_init = tegra_dc_init(dc);
1560         if (failed_init) {
1561                 _tegra_dc_controller_disable(dc);
1562                 return false;
1563         }
1564
1565         if (dc->out_ops && dc->out_ops->enable)
1566                 dc->out_ops->enable(dc);
1567
1568         if (dc->out->postpoweron)
1569                 dc->out->postpoweron();
1570
1571         /* force a full blending update */
1572         dc->blend.z[0] = -1;
1573
1574         tegra_dc_ext_enable(dc->ext);
1575
1576         trace_printk("%s:enable\n", dc->ndev->name);
1577         return true;
1578 }
1579
1580 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1581 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1582 {
1583         bool ret = true;
1584
1585         if (dc->out->enable)
1586                 dc->out->enable();
1587
1588         tegra_dc_setup_clk(dc, dc->clk);
1589         tegra_dc_clk_enable(dc);
1590
1591         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1592                 mutex_lock(&tegra_dcs[1]->lock);
1593                 disable_irq(tegra_dcs[1]->irq);
1594         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1595                 mutex_lock(&tegra_dcs[0]->lock);
1596                 disable_irq(tegra_dcs[0]->irq);
1597         }
1598
1599         msleep(5);
1600         tegra_periph_reset_assert(dc->clk);
1601         msleep(2);
1602 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1603         tegra_periph_reset_deassert(dc->clk);
1604         msleep(1);
1605 #endif
1606
1607         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1608                 enable_dc_irq(tegra_dcs[1]->irq);
1609                 mutex_unlock(&tegra_dcs[1]->lock);
1610         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1611                 enable_dc_irq(tegra_dcs[0]->irq);
1612                 mutex_unlock(&tegra_dcs[0]->lock);
1613         }
1614
1615         enable_dc_irq(dc->irq);
1616
1617         if (tegra_dc_init(dc)) {
1618                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1619                 ret = false;
1620         }
1621
1622         if (dc->out_ops && dc->out_ops->enable)
1623                 dc->out_ops->enable(dc);
1624
1625         if (dc->out->postpoweron)
1626                 dc->out->postpoweron();
1627
1628         /* force a full blending update */
1629         dc->blend.z[0] = -1;
1630
1631         tegra_dc_ext_enable(dc->ext);
1632
1633         if (!ret) {
1634                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1635                 _tegra_dc_controller_disable(dc);
1636         }
1637
1638         trace_printk("%s:reset enable\n", dc->ndev->name);
1639         return ret;
1640 }
1641 #endif
1642
1643 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1644 {
1645         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1646 }
1647
1648 static bool _tegra_dc_enable(struct tegra_dc *dc)
1649 {
1650         if (dc->mode.pclk == 0) {
1651                 switch (dc->out->type) {
1652                 case TEGRA_DC_OUT_HDMI:
1653                 /* DC enable called but no videomode is loaded.
1654                      Check if HDMI is connected, then set fallback mdoe */
1655                 if (tegra_dc_hpd(dc)) {
1656                         if (_tegra_dc_set_default_videomode(dc))
1657                                 return false;
1658                 } else
1659                         return false;
1660
1661                 break;
1662
1663                 /* Do nothing for other outputs for now */
1664                 case TEGRA_DC_OUT_RGB:
1665
1666                 case TEGRA_DC_OUT_DSI:
1667
1668                 default:
1669                         return false;
1670                 }
1671         }
1672
1673         if (!dc->out)
1674                 return false;
1675
1676         tegra_dc_io_start(dc);
1677
1678         return _tegra_dc_controller_enable(dc);
1679 }
1680
1681 void tegra_dc_enable(struct tegra_dc *dc)
1682 {
1683         mutex_lock(&dc->lock);
1684
1685         if (!dc->enabled)
1686                 dc->enabled = _tegra_dc_enable(dc);
1687
1688         mutex_unlock(&dc->lock);
1689         print_mode_info(dc, dc->mode);
1690 }
1691
1692 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1693 {
1694         unsigned i;
1695
1696         if (dc->out && dc->out->prepoweroff)
1697                 dc->out->prepoweroff();
1698
1699         if (dc->out_ops && dc->out_ops->disable)
1700                 dc->out_ops->disable(dc);
1701
1702         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1703         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1704         disable_irq(dc->irq);
1705
1706         tegra_dc_clear_bandwidth(dc);
1707         tegra_dc_clk_disable(dc);
1708
1709         if (dc->out && dc->out->disable)
1710                 dc->out->disable();
1711
1712         for (i = 0; i < dc->n_windows; i++) {
1713                 struct tegra_dc_win *w = &dc->windows[i];
1714
1715                 /* reset window bandwidth */
1716                 w->bandwidth = 0;
1717                 w->new_bandwidth = 0;
1718
1719                 /* disable windows */
1720                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1721
1722                 /* flush any pending syncpt waits */
1723                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1724                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1725                                 dc->syncpt[i].id);
1726                         dc->syncpt[i].min++;
1727                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1728                 }
1729         }
1730         trace_printk("%s:disabled\n", dc->ndev->name);
1731 }
1732
1733 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1734 {
1735 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1736         u32 val;
1737         if (dc->enabled)  {
1738                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1739                 if (enable)
1740                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1741                 else
1742                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1743                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1744         }
1745 #endif
1746 }
1747
1748 bool tegra_dc_stats_get(struct tegra_dc *dc)
1749 {
1750 #if 0 /* right now it is always enabled */
1751         u32 val;
1752         bool res;
1753
1754         if (dc->enabled)  {
1755                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1756                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1757         } else {
1758                 res = false;
1759         }
1760
1761         return res;
1762 #endif
1763         return true;
1764 }
1765
1766 /* make the screen blank by disabling all windows */
1767 void tegra_dc_blank(struct tegra_dc *dc)
1768 {
1769         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1770         unsigned i;
1771
1772         for (i = 0; i < DC_N_WINDOWS; i++) {
1773                 dcwins[i] = tegra_dc_get_window(dc, i);
1774                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1775         }
1776
1777         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1778         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1779 }
1780
1781 static void _tegra_dc_disable(struct tegra_dc *dc)
1782 {
1783         _tegra_dc_controller_disable(dc);
1784         tegra_dc_io_end(dc);
1785 }
1786
1787 void tegra_dc_disable(struct tegra_dc *dc)
1788 {
1789         tegra_dc_ext_disable(dc->ext);
1790
1791         /* it's important that new underflow work isn't scheduled before the
1792          * lock is acquired. */
1793         cancel_delayed_work_sync(&dc->underflow_work);
1794         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1795                 mutex_lock(&dc->one_shot_lock);
1796                 cancel_delayed_work_sync(&dc->one_shot_work);
1797         }
1798
1799         mutex_lock(&dc->lock);
1800
1801         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1802                 tegra_dc_host_resume(dc);
1803
1804         if (dc->enabled) {
1805                 dc->enabled = false;
1806
1807                 if (!dc->suspended)
1808                         _tegra_dc_disable(dc);
1809         }
1810
1811 #ifdef CONFIG_SWITCH
1812         switch_set_state(&dc->modeset_switch, 0);
1813 #endif
1814
1815         mutex_unlock(&dc->lock);
1816         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1817                 mutex_unlock(&dc->one_shot_lock);
1818         print_mode_info(dc, dc->mode);
1819 }
1820
1821 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1822 static void tegra_dc_reset_worker(struct work_struct *work)
1823 {
1824         struct tegra_dc *dc =
1825                 container_of(work, struct tegra_dc, reset_work);
1826
1827         unsigned long val = 0;
1828
1829         mutex_lock(&shared_lock);
1830
1831         dev_warn(&dc->ndev->dev,
1832                 "overlay stuck in underflow state.  resetting.\n");
1833
1834         tegra_dc_ext_disable(dc->ext);
1835
1836         mutex_lock(&dc->lock);
1837
1838         if (dc->enabled == false)
1839                 goto unlock;
1840
1841         dc->enabled = false;
1842
1843         /*
1844          * off host read bus
1845          */
1846         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1847         val &= ~(0x00000100);
1848         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1849
1850         /*
1851          * set DC to STOP mode
1852          */
1853         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1854
1855         msleep(10);
1856
1857         _tegra_dc_controller_disable(dc);
1858
1859         /* _tegra_dc_controller_reset_enable deasserts reset */
1860         _tegra_dc_controller_reset_enable(dc);
1861
1862         dc->enabled = true;
1863
1864         /* reopen host read bus */
1865         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1866         val &= ~(0x00000100);
1867         val |= 0x100;
1868         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1869
1870 unlock:
1871         mutex_unlock(&dc->lock);
1872         mutex_unlock(&shared_lock);
1873         trace_printk("%s:reset complete\n", dc->ndev->name);
1874 }
1875 #endif
1876
1877 static void tegra_dc_underflow_worker(struct work_struct *work)
1878 {
1879         struct tegra_dc *dc = container_of(
1880                 to_delayed_work(work), struct tegra_dc, underflow_work);
1881
1882         mutex_lock(&dc->lock);
1883         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1884                 tegra_dc_host_resume(dc);
1885
1886         if (dc->enabled) {
1887                 tegra_dc_underflow_handler(dc);
1888         }
1889         mutex_unlock(&dc->lock);
1890 }
1891
1892 #ifdef CONFIG_SWITCH
1893 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1894 {
1895         struct tegra_dc *dc =
1896                 container_of(sdev, struct tegra_dc, modeset_switch);
1897
1898         if (!sdev->state)
1899                 return sprintf(buf, "offline\n");
1900
1901         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1902 }
1903 #endif
1904
1905 static int tegra_dc_probe(struct nvhost_device *ndev,
1906         struct nvhost_device_id *id_table)
1907 {
1908         struct tegra_dc *dc;
1909         struct clk *clk;
1910         struct clk *emc_clk;
1911         struct resource *res;
1912         struct resource *base_res;
1913         struct resource *fb_mem = NULL;
1914         int ret = 0;
1915         void __iomem *base;
1916         int irq;
1917         int i;
1918
1919         if (!ndev->dev.platform_data) {
1920                 dev_err(&ndev->dev, "no platform data\n");
1921                 return -ENOENT;
1922         }
1923
1924         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1925         if (!dc) {
1926                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1927                 return -ENOMEM;
1928         }
1929
1930         irq = nvhost_get_irq_byname(ndev, "irq");
1931         if (irq <= 0) {
1932                 dev_err(&ndev->dev, "no irq\n");
1933                 ret = -ENOENT;
1934                 goto err_free;
1935         }
1936
1937         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1938         if (!res) {
1939                 dev_err(&ndev->dev, "no mem resource\n");
1940                 ret = -ENOENT;
1941                 goto err_free;
1942         }
1943
1944         base_res = request_mem_region(res->start, resource_size(res),
1945                 ndev->name);
1946         if (!base_res) {
1947                 dev_err(&ndev->dev, "request_mem_region failed\n");
1948                 ret = -EBUSY;
1949                 goto err_free;
1950         }
1951
1952         base = ioremap(res->start, resource_size(res));
1953         if (!base) {
1954                 dev_err(&ndev->dev, "registers can't be mapped\n");
1955                 ret = -EBUSY;
1956                 goto err_release_resource_reg;
1957         }
1958
1959         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1960
1961         clk = clk_get(&ndev->dev, NULL);
1962         if (IS_ERR_OR_NULL(clk)) {
1963                 dev_err(&ndev->dev, "can't get clock\n");
1964                 ret = -ENOENT;
1965                 goto err_iounmap_reg;
1966         }
1967
1968         emc_clk = clk_get(&ndev->dev, "emc");
1969         if (IS_ERR_OR_NULL(emc_clk)) {
1970                 dev_err(&ndev->dev, "can't get emc clock\n");
1971                 ret = -ENOENT;
1972                 goto err_put_clk;
1973         }
1974
1975         dc->clk = clk;
1976         dc->emc_clk = emc_clk;
1977         dc->shift_clk_div = 1;
1978         /* Initialize one shot work delay, it will be assigned by dsi
1979          * according to refresh rate later. */
1980         dc->one_shot_delay_ms = 40;
1981
1982         dc->base_res = base_res;
1983         dc->base = base;
1984         dc->irq = irq;
1985         dc->ndev = ndev;
1986         dc->pdata = ndev->dev.platform_data;
1987
1988         /*
1989          * The emc is a shared clock, it will be set based on
1990          * the requirements for each user on the bus.
1991          */
1992         dc->emc_clk_rate = 0;
1993
1994         mutex_init(&dc->lock);
1995         mutex_init(&dc->one_shot_lock);
1996         init_completion(&dc->frame_end_complete);
1997         init_waitqueue_head(&dc->wq);
1998 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1999         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2000 #endif
2001         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2002         dc->vblank_ref_count = 0;
2003         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2004         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2005
2006         tegra_dc_init_lut_defaults(&dc->fb_lut);
2007
2008         dc->n_windows = DC_N_WINDOWS;
2009         for (i = 0; i < dc->n_windows; i++) {
2010                 struct tegra_dc_win *win = &dc->windows[i];
2011                 win->idx = i;
2012                 win->dc = dc;
2013                 tegra_dc_init_csc_defaults(&win->csc);
2014                 tegra_dc_init_lut_defaults(&win->lut);
2015         }
2016
2017         ret = tegra_dc_set(dc, ndev->id);
2018         if (ret < 0) {
2019                 dev_err(&ndev->dev, "can't add dc\n");
2020                 goto err_free_irq;
2021         }
2022
2023         nvhost_set_drvdata(ndev, dc);
2024
2025 #ifdef CONFIG_SWITCH
2026         dc->modeset_switch.name = dev_name(&ndev->dev);
2027         dc->modeset_switch.state = 0;
2028         dc->modeset_switch.print_state = switch_modeset_print_mode;
2029         switch_dev_register(&dc->modeset_switch);
2030 #endif
2031
2032         tegra_dc_feature_register(dc);
2033
2034         if (dc->pdata->default_out)
2035                 tegra_dc_set_out(dc, dc->pdata->default_out);
2036         else
2037                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2038
2039         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2040                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2041
2042         dc->ext = tegra_dc_ext_register(ndev, dc);
2043         if (IS_ERR_OR_NULL(dc->ext)) {
2044                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2045                 dc->ext = NULL;
2046         }
2047
2048         mutex_lock(&dc->lock);
2049         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2050                 dc->enabled = _tegra_dc_enable(dc);
2051         mutex_unlock(&dc->lock);
2052
2053         /* interrupt handler must be registered before tegra_fb_register() */
2054         if (request_irq(irq, tegra_dc_irq, 0,
2055                         dev_name(&ndev->dev), dc)) {
2056                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2057                 ret = -EBUSY;
2058                 goto err_put_emc_clk;
2059         }
2060
2061         tegra_dc_create_debugfs(dc);
2062
2063         dev_info(&ndev->dev, "probed\n");
2064
2065         if (dc->pdata->fb) {
2066                 if (dc->pdata->fb->bits_per_pixel == -1) {
2067                         unsigned long fmt;
2068                         tegra_dc_writel(dc,
2069                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2070                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2071
2072                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2073                         dc->pdata->fb->bits_per_pixel =
2074                                 tegra_dc_fmt_bpp(fmt);
2075                 }
2076
2077                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2078                 if (IS_ERR_OR_NULL(dc->fb))
2079                         dc->fb = NULL;
2080         }
2081
2082         if (dc->out && dc->out->hotplug_init)
2083                 dc->out->hotplug_init();
2084
2085         if (dc->out_ops && dc->out_ops->detect)
2086                 dc->out_ops->detect(dc);
2087         else
2088                 dc->connected = true;
2089
2090         tegra_dc_create_sysfs(&dc->ndev->dev);
2091
2092         return 0;
2093
2094 err_free_irq:
2095         free_irq(irq, dc);
2096 err_put_emc_clk:
2097         clk_put(emc_clk);
2098 err_put_clk:
2099         clk_put(clk);
2100 err_iounmap_reg:
2101         iounmap(base);
2102         if (fb_mem)
2103                 release_resource(fb_mem);
2104 err_release_resource_reg:
2105         release_resource(base_res);
2106 err_free:
2107         kfree(dc);
2108
2109         return ret;
2110 }
2111
2112 static int tegra_dc_remove(struct nvhost_device *ndev)
2113 {
2114         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2115
2116         tegra_dc_remove_sysfs(&dc->ndev->dev);
2117         tegra_dc_remove_debugfs(dc);
2118
2119         if (dc->fb) {
2120                 tegra_fb_unregister(dc->fb);
2121                 if (dc->fb_mem)
2122                         release_resource(dc->fb_mem);
2123         }
2124
2125         tegra_dc_ext_disable(dc->ext);
2126
2127         if (dc->ext)
2128                 tegra_dc_ext_unregister(dc->ext);
2129
2130         if (dc->enabled)
2131                 _tegra_dc_disable(dc);
2132
2133 #ifdef CONFIG_SWITCH
2134         switch_dev_unregister(&dc->modeset_switch);
2135 #endif
2136         free_irq(dc->irq, dc);
2137         clk_put(dc->emc_clk);
2138         clk_put(dc->clk);
2139         iounmap(dc->base);
2140         if (dc->fb_mem)
2141                 release_resource(dc->base_res);
2142         kfree(dc);
2143         tegra_dc_set(NULL, ndev->id);
2144         return 0;
2145 }
2146
2147 #ifdef CONFIG_PM
2148 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2149 {
2150         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2151
2152         trace_printk("%s:suspend\n", dc->ndev->name);
2153         dev_info(&ndev->dev, "suspend\n");
2154
2155         tegra_dc_ext_disable(dc->ext);
2156
2157         mutex_lock(&dc->lock);
2158
2159         if (dc->out_ops && dc->out_ops->suspend)
2160                 dc->out_ops->suspend(dc);
2161
2162         if (dc->enabled) {
2163                 _tegra_dc_disable(dc);
2164
2165                 dc->suspended = true;
2166         }
2167
2168         if (dc->out && dc->out->postsuspend) {
2169                 dc->out->postsuspend();
2170                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2171                         /*
2172                          * avoid resume event due to voltage falling
2173                          */
2174                         msleep(100);
2175         }
2176
2177         mutex_unlock(&dc->lock);
2178
2179         return 0;
2180 }
2181
2182 static int tegra_dc_resume(struct nvhost_device *ndev)
2183 {
2184         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2185
2186         trace_printk("%s:resume\n", dc->ndev->name);
2187         dev_info(&ndev->dev, "resume\n");
2188
2189         mutex_lock(&dc->lock);
2190         dc->suspended = false;
2191
2192         if (dc->enabled)
2193                 _tegra_dc_enable(dc);
2194
2195         if (dc->out && dc->out->hotplug_init)
2196                 dc->out->hotplug_init();
2197
2198         if (dc->out_ops && dc->out_ops->resume)
2199                 dc->out_ops->resume(dc);
2200         mutex_unlock(&dc->lock);
2201
2202         return 0;
2203 }
2204
2205 #endif /* CONFIG_PM */
2206
2207 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2208 {
2209         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2210
2211         if (!dc || !dc->enabled)
2212                 return;
2213
2214         tegra_dc_blank(dc);
2215         tegra_dc_disable(dc);
2216 }
2217
2218 extern int suspend_set(const char *val, struct kernel_param *kp)
2219 {
2220         if (!strcmp(val, "dump"))
2221                 dump_regs(tegra_dcs[0]);
2222 #ifdef CONFIG_PM
2223         else if (!strcmp(val, "suspend"))
2224                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2225         else if (!strcmp(val, "resume"))
2226                 tegra_dc_resume(tegra_dcs[0]->ndev);
2227 #endif
2228
2229         return 0;
2230 }
2231
2232 extern int suspend_get(char *buffer, struct kernel_param *kp)
2233 {
2234         return 0;
2235 }
2236
2237 int suspend;
2238
2239 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2240
2241 struct nvhost_driver tegra_dc_driver = {
2242         .driver = {
2243                 .name = "tegradc",
2244                 .owner = THIS_MODULE,
2245         },
2246         .probe = tegra_dc_probe,
2247         .remove = tegra_dc_remove,
2248 #ifdef CONFIG_PM
2249         .suspend = tegra_dc_suspend,
2250         .resume = tegra_dc_resume,
2251 #endif
2252         .shutdown = tegra_dc_shutdown,
2253 };
2254
2255 static int __init tegra_dc_module_init(void)
2256 {
2257         int ret = tegra_dc_ext_module_init();
2258         if (ret)
2259                 return ret;
2260         return nvhost_driver_register(&tegra_dc_driver);
2261 }
2262
2263 static void __exit tegra_dc_module_exit(void)
2264 {
2265         nvhost_driver_unregister(&tegra_dc_driver);
2266         tegra_dc_ext_module_exit();
2267 }
2268
2269 module_exit(tegra_dc_module_exit);
2270 module_init(tegra_dc_module_init);