video: tegra: dc: support for vblank sync
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53
54 #include "dc_reg.h"
55 #include "dc_config.h"
56 #include "dc_priv.h"
57 #include "dev.h"
58 #include "nvsd.h"
59
60 #define TEGRA_CRC_LATCHED_DELAY         34
61
62 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
63 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
64
65 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
66         .refresh = 60,
67         .xres = 640,
68         .yres = 480,
69         .pixclock = KHZ2PICOS(25200),
70         .hsync_len = 96,        /* h_sync_width */
71         .vsync_len = 2,         /* v_sync_width */
72         .left_margin = 48,      /* h_back_porch */
73         .upper_margin = 33,     /* v_back_porch */
74         .right_margin = 16,     /* h_front_porch */
75         .lower_margin = 10,     /* v_front_porch */
76         .vmode = 0,
77         .sync = 0,
78 };
79
80 static struct tegra_dc_mode override_disp_mode[3];
81
82 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
83
84 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
85
86 DEFINE_MUTEX(tegra_dc_lock);
87 DEFINE_MUTEX(shared_lock);
88
89 static const struct {
90         bool h;
91         bool v;
92 } can_filter[] = {
93         /* Window A has no filtering */
94         { false, false },
95         /* Window B has both H and V filtering */
96         { true,  true  },
97         /* Window C has only H filtering */
98         { false, true  },
99 };
100
101 #ifdef CONFIG_TEGRA_DC_CMU
102 static struct tegra_dc_cmu default_cmu = {
103         /* lut1 maps sRGB to linear space. */
104         {
105                 0,    1,    2,    4,    5,    6,    7,    9,
106                 10,   11,   12,   14,   15,   16,   18,   20,
107                 21,   23,   25,   27,   29,   31,   33,   35,
108                 37,   40,   42,   45,   48,   50,   53,   56,
109                 59,   62,   66,   69,   72,   76,   79,   83,
110                 87,   91,   95,   99,   103,  107,  112,  116,
111                 121,  126,  131,  136,  141,  146,  151,  156,
112                 162,  168,  173,  179,  185,  191,  197,  204,
113                 210,  216,  223,  230,  237,  244,  251,  258,
114                 265,  273,  280,  288,  296,  304,  312,  320,
115                 329,  337,  346,  354,  363,  372,  381,  390,
116                 400,  409,  419,  428,  438,  448,  458,  469,
117                 479,  490,  500,  511,  522,  533,  544,  555,
118                 567,  578,  590,  602,  614,  626,  639,  651,
119                 664,  676,  689,  702,  715,  728,  742,  755,
120                 769,  783,  797,  811,  825,  840,  854,  869,
121                 884,  899,  914,  929,  945,  960,  976,  992,
122                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
123                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
124                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
125                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
126                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
127                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
128                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
129                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
130                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
131                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
132                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
133                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
134                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
135                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
136                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
137         },
138         /* csc */
139         {
140                 0x100, 0x0,   0x0,
141                 0x0,   0x100, 0x0,
142                 0x0,   0x0,   0x100,
143         },
144         /* lut2 maps linear space to sRGB*/
145         {
146                 0,    1,    2,    2,    3,    4,    5,    6,
147                 6,    7,    8,    9,    10,   10,   11,   12,
148                 13,   13,   14,   15,   15,   16,   16,   17,
149                 18,   18,   19,   19,   20,   20,   21,   21,
150                 22,   22,   23,   23,   23,   24,   24,   25,
151                 25,   25,   26,   26,   27,   27,   27,   28,
152                 28,   29,   29,   29,   30,   30,   30,   31,
153                 31,   31,   32,   32,   32,   33,   33,   33,
154                 34,   34,   34,   34,   35,   35,   35,   36,
155                 36,   36,   37,   37,   37,   37,   38,   38,
156                 38,   38,   39,   39,   39,   40,   40,   40,
157                 40,   41,   41,   41,   41,   42,   42,   42,
158                 42,   43,   43,   43,   43,   43,   44,   44,
159                 44,   44,   45,   45,   45,   45,   46,   46,
160                 46,   46,   46,   47,   47,   47,   47,   48,
161                 48,   48,   48,   48,   49,   49,   49,   49,
162                 49,   50,   50,   50,   50,   50,   51,   51,
163                 51,   51,   51,   52,   52,   52,   52,   52,
164                 53,   53,   53,   53,   53,   54,   54,   54,
165                 54,   54,   55,   55,   55,   55,   55,   55,
166                 56,   56,   56,   56,   56,   57,   57,   57,
167                 57,   57,   57,   58,   58,   58,   58,   58,
168                 58,   59,   59,   59,   59,   59,   59,   60,
169                 60,   60,   60,   60,   60,   61,   61,   61,
170                 61,   61,   61,   62,   62,   62,   62,   62,
171                 62,   63,   63,   63,   63,   63,   63,   64,
172                 64,   64,   64,   64,   64,   64,   65,   65,
173                 65,   65,   65,   65,   66,   66,   66,   66,
174                 66,   66,   66,   67,   67,   67,   67,   67,
175                 67,   67,   68,   68,   68,   68,   68,   68,
176                 68,   69,   69,   69,   69,   69,   69,   69,
177                 70,   70,   70,   70,   70,   70,   70,   71,
178                 71,   71,   71,   71,   71,   71,   72,   72,
179                 72,   72,   72,   72,   72,   72,   73,   73,
180                 73,   73,   73,   73,   73,   74,   74,   74,
181                 74,   74,   74,   74,   74,   75,   75,   75,
182                 75,   75,   75,   75,   75,   76,   76,   76,
183                 76,   76,   76,   76,   77,   77,   77,   77,
184                 77,   77,   77,   77,   78,   78,   78,   78,
185                 78,   78,   78,   78,   78,   79,   79,   79,
186                 79,   79,   79,   79,   79,   80,   80,   80,
187                 80,   80,   80,   80,   80,   81,   81,   81,
188                 81,   81,   81,   81,   81,   81,   82,   82,
189                 82,   82,   82,   82,   82,   82,   83,   83,
190                 83,   83,   83,   83,   83,   83,   83,   84,
191                 84,   84,   84,   84,   84,   84,   84,   84,
192                 85,   85,   85,   85,   85,   85,   85,   85,
193                 85,   86,   86,   86,   86,   86,   86,   86,
194                 86,   86,   87,   87,   87,   87,   87,   87,
195                 87,   87,   87,   88,   88,   88,   88,   88,
196                 88,   88,   88,   88,   88,   89,   89,   89,
197                 89,   89,   89,   89,   89,   89,   90,   90,
198                 90,   90,   90,   90,   90,   90,   90,   90,
199                 91,   91,   91,   91,   91,   91,   91,   91,
200                 91,   91,   92,   92,   92,   92,   92,   92,
201                 92,   92,   92,   92,   93,   93,   93,   93,
202                 93,   93,   93,   93,   93,   93,   94,   94,
203                 94,   94,   94,   94,   94,   94,   94,   94,
204                 95,   95,   95,   95,   95,   95,   95,   95,
205                 95,   95,   96,   96,   96,   96,   96,   96,
206                 96,   96,   96,   96,   96,   97,   97,   97,
207                 97,   97,   97,   97,   97,   97,   97,   98,
208                 98,   98,   98,   98,   98,   98,   98,   98,
209                 98,   98,   99,   99,   99,   99,   99,   99,
210                 99,   100,  101,  101,  102,  103,  103,  104,
211                 105,  105,  106,  107,  107,  108,  109,  109,
212                 110,  111,  111,  112,  113,  113,  114,  115,
213                 115,  116,  116,  117,  118,  118,  119,  119,
214                 120,  120,  121,  122,  122,  123,  123,  124,
215                 124,  125,  126,  126,  127,  127,  128,  128,
216                 129,  129,  130,  130,  131,  131,  132,  132,
217                 133,  133,  134,  134,  135,  135,  136,  136,
218                 137,  137,  138,  138,  139,  139,  140,  140,
219                 141,  141,  142,  142,  143,  143,  144,  144,
220                 145,  145,  145,  146,  146,  147,  147,  148,
221                 148,  149,  149,  150,  150,  150,  151,  151,
222                 152,  152,  153,  153,  153,  154,  154,  155,
223                 155,  156,  156,  156,  157,  157,  158,  158,
224                 158,  159,  159,  160,  160,  160,  161,  161,
225                 162,  162,  162,  163,  163,  164,  164,  164,
226                 165,  165,  166,  166,  166,  167,  167,  167,
227                 168,  168,  169,  169,  169,  170,  170,  170,
228                 171,  171,  172,  172,  172,  173,  173,  173,
229                 174,  174,  174,  175,  175,  176,  176,  176,
230                 177,  177,  177,  178,  178,  178,  179,  179,
231                 179,  180,  180,  180,  181,  181,  182,  182,
232                 182,  183,  183,  183,  184,  184,  184,  185,
233                 185,  185,  186,  186,  186,  187,  187,  187,
234                 188,  188,  188,  189,  189,  189,  189,  190,
235                 190,  190,  191,  191,  191,  192,  192,  192,
236                 193,  193,  193,  194,  194,  194,  195,  195,
237                 195,  196,  196,  196,  196,  197,  197,  197,
238                 198,  198,  198,  199,  199,  199,  200,  200,
239                 200,  200,  201,  201,  201,  202,  202,  202,
240                 202,  203,  203,  203,  204,  204,  204,  205,
241                 205,  205,  205,  206,  206,  206,  207,  207,
242                 207,  207,  208,  208,  208,  209,  209,  209,
243                 209,  210,  210,  210,  211,  211,  211,  211,
244                 212,  212,  212,  213,  213,  213,  213,  214,
245                 214,  214,  214,  215,  215,  215,  216,  216,
246                 216,  216,  217,  217,  217,  217,  218,  218,
247                 218,  219,  219,  219,  219,  220,  220,  220,
248                 220,  221,  221,  221,  221,  222,  222,  222,
249                 223,  223,  223,  223,  224,  224,  224,  224,
250                 225,  225,  225,  225,  226,  226,  226,  226,
251                 227,  227,  227,  227,  228,  228,  228,  228,
252                 229,  229,  229,  229,  230,  230,  230,  230,
253                 231,  231,  231,  231,  232,  232,  232,  232,
254                 233,  233,  233,  233,  234,  234,  234,  234,
255                 235,  235,  235,  235,  236,  236,  236,  236,
256                 237,  237,  237,  237,  238,  238,  238,  238,
257                 239,  239,  239,  239,  240,  240,  240,  240,
258                 240,  241,  241,  241,  241,  242,  242,  242,
259                 242,  243,  243,  243,  243,  244,  244,  244,
260                 244,  244,  245,  245,  245,  245,  246,  246,
261                 246,  246,  247,  247,  247,  247,  247,  248,
262                 248,  248,  248,  249,  249,  249,  249,  249,
263                 250,  250,  250,  250,  251,  251,  251,  251,
264                 251,  252,  252,  252,  252,  253,  253,  253,
265                 253,  253,  254,  254,  254,  254,  255,  255,
266         },
267 };
268 #endif
269
270 void tegra_dc_clk_enable(struct tegra_dc *dc)
271 {
272         if (!tegra_is_clk_enabled(dc->clk)) {
273                 clk_prepare_enable(dc->clk);
274                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
275         }
276 }
277
278 void tegra_dc_clk_disable(struct tegra_dc *dc)
279 {
280         if (tegra_is_clk_enabled(dc->clk)) {
281                 clk_disable_unprepare(dc->clk);
282                 tegra_dvfs_set_rate(dc->clk, 0);
283         }
284 }
285
286 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
287 {
288         if (dc->out_ops->hold)
289                 dc->out_ops->hold(dc);
290 }
291
292 void tegra_dc_release_dc_out(struct tegra_dc *dc)
293 {
294         if (dc->out_ops->release)
295                 dc->out_ops->release(dc);
296 }
297
298 #define DUMP_REG(a) do {                        \
299         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
300                  #a, a, tegra_dc_readl(dc, a));               \
301         print(data, buff);                                    \
302         } while (0)
303
304 static void _dump_regs(struct tegra_dc *dc, void *data,
305                        void (* print)(void *data, const char *str))
306 {
307         int i;
308         char buff[256];
309
310         mutex_lock(&dc->lock);
311         tegra_dc_hold_dc_out(dc);
312         tegra_dc_io_start(dc);
313
314         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE);
317         DUMP_REG(DC_CMD_INT_STATUS);
318         DUMP_REG(DC_CMD_INT_MASK);
319         DUMP_REG(DC_CMD_INT_ENABLE);
320         DUMP_REG(DC_CMD_INT_TYPE);
321         DUMP_REG(DC_CMD_INT_POLARITY);
322         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
325         DUMP_REG(DC_CMD_STATE_ACCESS);
326         DUMP_REG(DC_CMD_STATE_CONTROL);
327         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
328         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
329
330         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
332         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
333         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
335         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
336         DUMP_REG(DC_DISP_REF_TO_SYNC);
337         DUMP_REG(DC_DISP_SYNC_WIDTH);
338         DUMP_REG(DC_DISP_BACK_PORCH);
339         DUMP_REG(DC_DISP_DISP_ACTIVE);
340         DUMP_REG(DC_DISP_FRONT_PORCH);
341         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
342         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
346         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
347         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
351         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
352         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
356         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
357         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
360         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
367         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
368         DUMP_REG(DC_DISP_M0_CONTROL);
369         DUMP_REG(DC_DISP_M1_CONTROL);
370         DUMP_REG(DC_DISP_DI_CONTROL);
371         DUMP_REG(DC_DISP_PP_CONTROL);
372         DUMP_REG(DC_DISP_PP_SELECT_A);
373         DUMP_REG(DC_DISP_PP_SELECT_B);
374         DUMP_REG(DC_DISP_PP_SELECT_C);
375         DUMP_REG(DC_DISP_PP_SELECT_D);
376         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
377         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
378         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
379         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
380         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
381         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
382         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
383         DUMP_REG(DC_DISP_BORDER_COLOR);
384         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
385         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
386         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
388         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
389         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
390         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
392         DUMP_REG(DC_DISP_CURSOR_POSITION);
393         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
394         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
395         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
399         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
400         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
403 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
405 #endif
406         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
407         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
408
409
410         for (i = 0; i < 3; i++) {
411                 print(data, "\n");
412                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
413                 print(data, buff);
414
415                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
416                                 DC_CMD_DISPLAY_WINDOW_HEADER);
417                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_WIN_WIN_OPTIONS);
419                 DUMP_REG(DC_WIN_BYTE_SWAP);
420                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
421                 DUMP_REG(DC_WIN_COLOR_DEPTH);
422                 DUMP_REG(DC_WIN_POSITION);
423                 DUMP_REG(DC_WIN_SIZE);
424                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
425                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
426                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_DDA_INCREMENT);
428                 DUMP_REG(DC_WIN_LINE_STRIDE);
429 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
430                 DUMP_REG(DC_WIN_BUF_STRIDE);
431                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
432 #endif
433                 DUMP_REG(DC_WIN_BLEND_NOKEY);
434                 DUMP_REG(DC_WIN_BLEND_1WIN);
435                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
437                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
438                 DUMP_REG(DC_WINBUF_START_ADDR);
439                 DUMP_REG(DC_WINBUF_START_ADDR_U);
440                 DUMP_REG(DC_WINBUF_START_ADDR_V);
441                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
442                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
443                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
444                 DUMP_REG(DC_WIN_CSC_YOF);
445                 DUMP_REG(DC_WIN_CSC_KYRGB);
446                 DUMP_REG(DC_WIN_CSC_KUR);
447                 DUMP_REG(DC_WIN_CSC_KVR);
448                 DUMP_REG(DC_WIN_CSC_KUG);
449                 DUMP_REG(DC_WIN_CSC_KVG);
450                 DUMP_REG(DC_WIN_CSC_KUB);
451                 DUMP_REG(DC_WIN_CSC_KVB);
452         }
453
454         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
455         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
456         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
458         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
459         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
460         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
461         DUMP_REG(DC_DISP_M1_CONTROL);
462         DUMP_REG(DC_COM_PM1_CONTROL);
463         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
464         DUMP_REG(DC_DISP_SD_CONTROL);
465
466         tegra_dc_io_end(dc);
467         tegra_dc_release_dc_out(dc);
468         mutex_unlock(&dc->lock);
469 }
470
471 #undef DUMP_REG
472
473 #ifdef DEBUG
474 static void dump_regs_print(void *data, const char *str)
475 {
476         struct tegra_dc *dc = data;
477         dev_dbg(&dc->ndev->dev, "%s", str);
478 }
479
480 static void dump_regs(struct tegra_dc *dc)
481 {
482         _dump_regs(dc, dc, dump_regs_print);
483 }
484 #else /* !DEBUG */
485
486 static void dump_regs(struct tegra_dc *dc) {}
487
488 #endif /* DEBUG */
489
490 #ifdef CONFIG_DEBUG_FS
491
492 static void dbg_regs_print(void *data, const char *str)
493 {
494         struct seq_file *s = data;
495
496         seq_printf(s, "%s", str);
497 }
498
499 #undef DUMP_REG
500
501 static int dbg_dc_show(struct seq_file *s, void *unused)
502 {
503         struct tegra_dc *dc = s->private;
504
505         _dump_regs(dc, s, dbg_regs_print);
506
507         return 0;
508 }
509
510
511 static int dbg_dc_open(struct inode *inode, struct file *file)
512 {
513         return single_open(file, dbg_dc_show, inode->i_private);
514 }
515
516 static const struct file_operations regs_fops = {
517         .open           = dbg_dc_open,
518         .read           = seq_read,
519         .llseek         = seq_lseek,
520         .release        = single_release,
521 };
522
523 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
524 {
525         struct tegra_dc *dc = s->private;
526         struct tegra_dc_mode *m;
527
528         mutex_lock(&dc->lock);
529         m = &dc->mode;
530         seq_printf(s,
531                 "pclk: %d\n"
532                 "h_ref_to_sync: %d\n"
533                 "v_ref_to_sync: %d\n"
534                 "h_sync_width: %d\n"
535                 "v_sync_width: %d\n"
536                 "h_back_porch: %d\n"
537                 "v_back_porch: %d\n"
538                 "h_active: %d\n"
539                 "v_active: %d\n"
540                 "h_front_porch: %d\n"
541                 "v_front_porch: %d\n"
542                 "stereo_mode: %d\n",
543                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
544                 m->h_sync_width, m->v_sync_width,
545                 m->h_back_porch, m->v_back_porch,
546                 m->h_active, m->v_active,
547                 m->h_front_porch, m->v_front_porch,
548                 m->stereo_mode);
549         mutex_unlock(&dc->lock);
550         return 0;
551 }
552
553 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
554 {
555         return single_open(file, dbg_dc_mode_show, inode->i_private);
556 }
557
558 static const struct file_operations mode_fops = {
559         .open           = dbg_dc_mode_open,
560         .read           = seq_read,
561         .llseek         = seq_lseek,
562         .release        = single_release,
563 };
564
565 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
566 {
567         struct tegra_dc *dc = s->private;
568
569         mutex_lock(&dc->lock);
570         seq_printf(s,
571                 "underflows: %llu\n"
572                 "underflows_a: %llu\n"
573                 "underflows_b: %llu\n"
574                 "underflows_c: %llu\n",
575                 dc->stats.underflows,
576                 dc->stats.underflows_a,
577                 dc->stats.underflows_b,
578                 dc->stats.underflows_c);
579         mutex_unlock(&dc->lock);
580
581         return 0;
582 }
583
584 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
585 {
586         return single_open(file, dbg_dc_stats_show, inode->i_private);
587 }
588
589 static const struct file_operations stats_fops = {
590         .open           = dbg_dc_stats_open,
591         .read           = seq_read,
592         .llseek         = seq_lseek,
593         .release        = single_release,
594 };
595
596 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
597 {
598         if (dc->debugdir)
599                 debugfs_remove_recursive(dc->debugdir);
600         dc->debugdir = NULL;
601 }
602
603 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
604 {
605         struct dentry *retval;
606
607         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
608         if (!dc->debugdir)
609                 goto remove_out;
610
611         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
612                 &regs_fops);
613         if (!retval)
614                 goto remove_out;
615
616         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
617                 &mode_fops);
618         if (!retval)
619                 goto remove_out;
620
621         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
622                 &stats_fops);
623         if (!retval)
624                 goto remove_out;
625
626         return;
627 remove_out:
628         dev_err(&dc->ndev->dev, "could not create debugfs\n");
629         tegra_dc_remove_debugfs(dc);
630 }
631
632 #else /* !CONFIG_DEBUGFS */
633 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
634 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
635 #endif /* CONFIG_DEBUGFS */
636
637 static int tegra_dc_set(struct tegra_dc *dc, int index)
638 {
639         int ret = 0;
640
641         mutex_lock(&tegra_dc_lock);
642         if (index >= TEGRA_MAX_DC) {
643                 ret = -EINVAL;
644                 goto out;
645         }
646
647         if (dc != NULL && tegra_dcs[index] != NULL) {
648                 ret = -EBUSY;
649                 goto out;
650         }
651
652         tegra_dcs[index] = dc;
653
654 out:
655         mutex_unlock(&tegra_dc_lock);
656
657         return ret;
658 }
659
660 unsigned int tegra_dc_has_multiple_dc(void)
661 {
662         unsigned int idx;
663         unsigned int cnt = 0;
664         struct tegra_dc *dc;
665
666         mutex_lock(&tegra_dc_lock);
667         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
668                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
669         mutex_unlock(&tegra_dc_lock);
670
671         return (cnt > 1);
672 }
673
674 /* get the stride size of a window.
675  * return: stride size in bytes for window win. or 0 if unavailble. */
676 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
677 {
678         u32 stride;
679
680         if (!dc->enabled)
681                 return 0;
682         BUG_ON(win > DC_N_WINDOWS);
683         mutex_lock(&dc->lock);
684         tegra_dc_hold_dc_out(dc);
685         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
686                 DC_CMD_DISPLAY_WINDOW_HEADER);
687         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
688         tegra_dc_release_dc_out(dc);
689         mutex_unlock(&dc->lock);
690         return GET_LINE_STRIDE(stride);
691 }
692 EXPORT_SYMBOL(tegra_dc_get_stride);
693
694 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
695 {
696         if (idx < TEGRA_MAX_DC)
697                 return tegra_dcs[idx];
698         else
699                 return NULL;
700 }
701 EXPORT_SYMBOL(tegra_dc_get_dc);
702
703 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
704 {
705         if (win >= dc->n_windows)
706                 return NULL;
707
708         return &dc->windows[win];
709 }
710 EXPORT_SYMBOL(tegra_dc_get_window);
711
712 bool tegra_dc_get_connected(struct tegra_dc *dc)
713 {
714         return dc->connected;
715 }
716 EXPORT_SYMBOL(tegra_dc_get_connected);
717
718 bool tegra_dc_hpd(struct tegra_dc *dc)
719 {
720         int sense;
721         int level;
722
723         level = gpio_get_value(dc->out->hotplug_gpio);
724
725         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
726
727         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
728                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
729 }
730 EXPORT_SYMBOL(tegra_dc_hpd);
731
732 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
733 {
734         unsigned i;
735         unsigned v0 = 128;
736         unsigned v1 = 0;
737         /* linear horizontal and vertical filters */
738         for (i = 0; i < 16; i++) {
739                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
740                                 DC_WIN_H_FILTER_P(i));
741
742                 tegra_dc_writel(dc, v0,
743                                 DC_WIN_V_FILTER_P(i));
744                 v0 -= 8;
745                 v1 += 8;
746         }
747 }
748
749 #ifdef CONFIG_TEGRA_DC_CMU
750 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
751                                         struct tegra_dc_cmu *src_cmu)
752 {
753         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
754 }
755
756 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
757 {
758         u32 val;
759         u32 i;
760
761         for (i = 0; i < 256; i++) {
762                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
763                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
764         }
765
766         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
767         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
768         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
769         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
770         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
771         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
772         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
773         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
774         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
775
776         for (i = 0; i < 960; i++) {
777                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
778                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
779         }
780 }
781
782 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
783 {
784         u32 val;
785         u32 i;
786         bool flags;
787
788         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
789         if (val & CMU_ENABLE)
790                 flags = true;
791
792         val &= ~CMU_ENABLE;
793         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
794         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
795         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
796
797         /*TODO: Sync up with frame end */
798         mdelay(20);
799
800         for (i = 0; i < 256; i++) {
801                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
802                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
803                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
804                 cmu->lut1[i] = LUT1_READ_DATA(val);
805         }
806
807         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
808         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
809         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
810         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
811         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
812         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
813         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
814         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
815         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
816
817         for (i = 0; i < 960; i++) {
818                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
819                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
820                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
821                 cmu->lut2[i] = LUT2_READ_DATA(val);
822         }
823 }
824 EXPORT_SYMBOL(tegra_dc_get_cmu);
825
826 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
827 {
828         u32 val;
829
830         if (dc->pdata->cmu_enable) {
831                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
832         } else {
833                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
834                 return 0;
835         }
836
837         if (cmu != &dc->cmu) {
838                 tegra_dc_cache_cmu(&dc->cmu, cmu);
839
840                 /* Disable CMU */
841                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
842                 if (val & CMU_ENABLE) {
843                         val &= ~CMU_ENABLE;
844                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
845                         val = GENERAL_UPDATE;
846                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
847                         val = GENERAL_ACT_REQ;
848                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
849                         /*TODO: Sync up with vsync */
850                         mdelay(20);
851                 }
852
853                 tegra_dc_set_cmu(dc, &dc->cmu);
854         }
855
856         return 0;
857 }
858 EXPORT_SYMBOL(tegra_dc_update_cmu);
859
860 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
861 {
862         dc->pdata->cmu_enable = cmu_enable;
863         tegra_dc_update_cmu(dc, &dc->cmu);
864         tegra_dc_set_color_control(dc);
865 }
866 #else
867 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
868 #define tegra_dc_set_cmu(dc, cmu)
869 #define tegra_dc_update_cmu(dc, cmu)
870 #endif
871
872 static inline void disable_dc_irq(unsigned int irq)
873 {
874         disable_irq(irq);
875 }
876
877 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
878 {
879         return dc->syncpt[i].id;
880 }
881 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
882
883 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
884 {
885         u32 max;
886
887         mutex_lock(&dc->lock);
888         tegra_dc_hold_dc_out(dc);
889         max = nvhost_syncpt_incr_max_ext(dc->ndev,
890                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
891         dc->syncpt[i].max = max;
892         tegra_dc_release_dc_out(dc);
893         mutex_unlock(&dc->lock);
894
895         return max;
896 }
897
898 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
899 {
900         mutex_lock(&dc->lock);
901         if (dc->enabled) {
902                 tegra_dc_hold_dc_out(dc);
903                 while (dc->syncpt[i].min < val) {
904                         dc->syncpt[i].min++;
905                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
906                 }
907                 tegra_dc_release_dc_out(dc);
908         }
909         mutex_unlock(&dc->lock);
910 }
911
912 void
913 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
914 {
915         unsigned int ctrl;
916         unsigned long out_sel;
917         unsigned long cmd_state;
918
919         mutex_lock(&dc->lock);
920         if (!dc->enabled) {
921                 mutex_unlock(&dc->lock);
922                 return;
923         }
924
925         tegra_dc_hold_dc_out(dc);
926
927         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
928                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
929                 cfg->clk_select);
930
931         /* The new value should be effected immediately */
932         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
933         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
934
935         switch (cfg->which_pwm) {
936         case TEGRA_PWM_PM0:
937                 /* Select the LM0 on PM0 */
938                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
939                 out_sel &= ~(7 << 0);
940                 out_sel |= (3 << 0);
941                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
942                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
943                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
944                 break;
945         case TEGRA_PWM_PM1:
946                 /* Select the LM1 on PM1 */
947                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
948                 out_sel &= ~(7 << 4);
949                 out_sel |= (3 << 4);
950                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
951                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
952                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
953                 break;
954         default:
955                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
956                 break;
957         }
958         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
959         tegra_dc_release_dc_out(dc);
960         mutex_unlock(&dc->lock);
961 }
962 EXPORT_SYMBOL(tegra_dc_config_pwm);
963
964 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
965                                 const struct tegra_dc_out_pin *pins,
966                                 const unsigned int n_pins)
967 {
968         unsigned int i;
969
970         int name;
971         int pol;
972
973         u32 pol1, pol3;
974
975         u32 set1, unset1;
976         u32 set3, unset3;
977
978         set1 = set3 = unset1 = unset3 = 0;
979
980         for (i = 0; i < n_pins; i++) {
981                 name = (pins + i)->name;
982                 pol  = (pins + i)->pol;
983
984                 /* set polarity by name */
985                 switch (name) {
986                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
987                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
988                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
989                         else
990                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
991                         break;
992                 case TEGRA_DC_OUT_PIN_H_SYNC:
993                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
994                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
995                         else
996                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
997                         break;
998                 case TEGRA_DC_OUT_PIN_V_SYNC:
999                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1000                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1001                         else
1002                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1003                         break;
1004                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1005                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1006                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1007                         else
1008                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1009                         break;
1010                 default:
1011                         printk("Invalid argument in function %s\n",
1012                                __FUNCTION__);
1013                         break;
1014                 }
1015         }
1016
1017         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1018         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1019
1020         pol1 |= set1;
1021         pol1 &= ~unset1;
1022
1023         pol3 |= set3;
1024         pol3 &= ~unset3;
1025
1026         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1027         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1028 }
1029
1030 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1031 {
1032         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1033                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1034                 dc->out->type == TEGRA_DC_OUT_DSI)
1035                 return override_disp_mode[dc->out->type].pclk ?
1036                         &override_disp_mode[dc->out->type] : NULL;
1037         else
1038                 return NULL;
1039 }
1040
1041 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1042 {
1043         struct tegra_dc_mode *mode;
1044
1045         dc->out = out;
1046         mode = tegra_dc_get_override_mode(dc);
1047
1048         if (mode)
1049                 tegra_dc_set_mode(dc, mode);
1050         else if (out->n_modes > 0)
1051                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1052
1053         switch (out->type) {
1054         case TEGRA_DC_OUT_RGB:
1055                 dc->out_ops = &tegra_dc_rgb_ops;
1056                 break;
1057
1058         case TEGRA_DC_OUT_HDMI:
1059                 dc->out_ops = &tegra_dc_hdmi_ops;
1060                 break;
1061
1062         case TEGRA_DC_OUT_DSI:
1063                 dc->out_ops = &tegra_dc_dsi_ops;
1064                 break;
1065
1066         default:
1067                 dc->out_ops = NULL;
1068                 break;
1069         }
1070
1071         if (dc->out_ops && dc->out_ops->init)
1072                 dc->out_ops->init(dc);
1073
1074 }
1075
1076 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1077 {
1078         if (dc->out)
1079                 return dc->out->height;
1080         else
1081                 return 0;
1082 }
1083 EXPORT_SYMBOL(tegra_dc_get_out_height);
1084
1085 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1086 {
1087         if (dc->out)
1088                 return dc->out->width;
1089         else
1090                 return 0;
1091 }
1092 EXPORT_SYMBOL(tegra_dc_get_out_width);
1093
1094 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1095 {
1096         if (dc->out && dc->out->max_pixclock)
1097                 return dc->out->max_pixclock;
1098         else
1099                 return 0;
1100 }
1101 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1102
1103 void tegra_dc_enable_crc(struct tegra_dc *dc)
1104 {
1105         u32 val;
1106
1107         mutex_lock(&dc->lock);
1108         tegra_dc_hold_dc_out(dc);
1109         tegra_dc_io_start(dc);
1110
1111         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1112                 CRC_ENABLE_ENABLE;
1113         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1114         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1115         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1116         tegra_dc_release_dc_out(dc);
1117         mutex_unlock(&dc->lock);
1118 }
1119
1120 void tegra_dc_disable_crc(struct tegra_dc *dc)
1121 {
1122         mutex_lock(&dc->lock);
1123         tegra_dc_hold_dc_out(dc);
1124         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1125         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1126         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1127
1128         tegra_dc_io_end(dc);
1129         tegra_dc_release_dc_out(dc);
1130         mutex_unlock(&dc->lock);
1131 }
1132
1133 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1134 {
1135         int crc = 0;
1136
1137         if (!dc) {
1138                 pr_err("Failed to get dc: NULL parameter.\n");
1139                 goto crc_error;
1140         }
1141
1142 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1143         /* TODO: Replace mdelay with code to sync VBlANK, since
1144          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1145         mdelay(TEGRA_CRC_LATCHED_DELAY);
1146 #endif
1147
1148         mutex_lock(&dc->lock);
1149         tegra_dc_hold_dc_out(dc);
1150         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1151         tegra_dc_release_dc_out(dc);
1152         mutex_unlock(&dc->lock);
1153 crc_error:
1154         return crc;
1155 }
1156
1157 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1158 {
1159 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1160         u32 val;
1161
1162         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1163         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1164             return true;
1165 #endif
1166         return false;
1167 }
1168
1169 static inline void enable_dc_irq(unsigned int irq)
1170 {
1171 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1172         enable_irq(irq);
1173 #else
1174         /* Always disable DC interrupts on FPGA. */
1175         disable_irq(irq);
1176 #endif
1177 }
1178
1179 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1180 {
1181         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1182                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1183 }
1184
1185 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1186 {
1187         int ret = -ENOTTY;
1188
1189         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1190                 return ret;
1191
1192         /*
1193          * Logic is as follows
1194          * a) Indicate we need a vblank.
1195          * b) Wait for completion to be signalled from isr.
1196          * c) Initialize completion for next iteration.
1197          */
1198
1199         tegra_dc_hold_dc_out(dc);
1200         dc->out->user_needs_vblank = true;
1201
1202         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1203         init_completion(&dc->out->user_vblank_comp);
1204         tegra_dc_release_dc_out(dc);
1205
1206         return ret;
1207 }
1208
1209 static void tegra_dc_vblank(struct work_struct *work)
1210 {
1211         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1212         bool nvsd_updated = false;
1213
1214         mutex_lock(&dc->lock);
1215
1216         if (!dc->enabled) {
1217                 mutex_unlock(&dc->lock);
1218                 return;
1219         }
1220
1221         tegra_dc_hold_dc_out(dc);
1222         /* use the new frame's bandwidth setting instead of max(current, new),
1223          * skip this if we're using tegra_dc_one_shot_worker() */
1224         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1225                 tegra_dc_program_bandwidth(dc, true);
1226
1227         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1228         if (!tegra_dc_windows_are_dirty(dc))
1229                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1230
1231         /* Update the SD brightness */
1232         if (dc->enabled && dc->out->sd_settings) {
1233                 nvsd_updated = nvsd_update_brightness(dc);
1234                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1235                  * V_BLANK_NVSD bit of vblank ref-count. */
1236                 if (nvsd_updated) {
1237                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1238                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1239                 } else {
1240                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1241                 }
1242         }
1243
1244         /* Mask vblank interrupt if ref-count is zero. */
1245         if (!dc->vblank_ref_count)
1246                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1247
1248         tegra_dc_release_dc_out(dc);
1249         mutex_unlock(&dc->lock);
1250
1251         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1252                 dc->out->sd_settings->bl_device_name) {
1253                 char *bl_device_name =
1254                         dc->out->sd_settings->bl_device_name;
1255                 dc->out->sd_settings->bl_device =
1256                         get_backlight_device_by_name(bl_device_name);
1257         }
1258
1259         /* Do the actual brightness update outside of the mutex */
1260         if (nvsd_updated && dc->out->sd_settings &&
1261             dc->out->sd_settings->bl_device) {
1262
1263                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1264                 backlight_update_status(bl);
1265         }
1266 }
1267
1268 static void tegra_dc_one_shot_worker(struct work_struct *work)
1269 {
1270         struct tegra_dc *dc = container_of(
1271                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1272         mutex_lock(&dc->lock);
1273
1274         /* memory client has gone idle */
1275         tegra_dc_clear_bandwidth(dc);
1276
1277         if (dc->out_ops->idle)
1278                 dc->out_ops->idle(dc);
1279
1280         mutex_unlock(&dc->lock);
1281 }
1282
1283 /* return an arbitrarily large number if count overflow occurs.
1284  * make it a nice base-10 number to show up in stats output */
1285 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1286 {
1287         unsigned count = tegra_dc_readl(dc, reg);
1288         tegra_dc_writel(dc, 0, reg);
1289         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1290 }
1291
1292 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1293 {
1294         u32 val;
1295         int i;
1296
1297         dc->stats.underflows++;
1298         if (dc->underflow_mask & WIN_A_UF_INT)
1299                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1300                         DC_WINBUF_AD_UFLOW_STATUS);
1301         if (dc->underflow_mask & WIN_B_UF_INT)
1302                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1303                         DC_WINBUF_BD_UFLOW_STATUS);
1304         if (dc->underflow_mask & WIN_C_UF_INT)
1305                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1306                         DC_WINBUF_CD_UFLOW_STATUS);
1307
1308         /* Check for any underflow reset conditions */
1309         for (i = 0; i < DC_N_WINDOWS; i++) {
1310                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1311                         dc->windows[i].underflows++;
1312
1313 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1314                         if (dc->windows[i].underflows > 4) {
1315                                 schedule_work(&dc->reset_work);
1316                                 /* reset counter */
1317                                 dc->windows[i].underflows = 0;
1318                                 trace_display_reset(dc);
1319                         }
1320 #endif
1321 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1322                         if (dc->windows[i].underflows > 4) {
1323                                 trace_display_reset(dc);
1324                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1325                                                 DC_DISP_DISP_MISC_CONTROL);
1326                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1327                                                 DC_CMD_STATE_CONTROL);
1328                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1329                                                 DC_CMD_STATE_CONTROL);
1330
1331                                 tegra_dc_writel(dc, 0,
1332                                                 DC_DISP_DISP_MISC_CONTROL);
1333                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1334                                                 DC_CMD_STATE_CONTROL);
1335                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1336                                                 DC_CMD_STATE_CONTROL);
1337                         }
1338 #endif
1339                 } else {
1340                         dc->windows[i].underflows = 0;
1341                 }
1342         }
1343
1344         /* Clear the underflow mask now that we've checked it. */
1345         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1346         dc->underflow_mask = 0;
1347         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1348         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1349         trace_underflow(dc);
1350 }
1351
1352 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1353 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1354 {
1355         /* pending user vblank, so wakeup */
1356         if ((status & (V_BLANK_INT | MSF_INT)) &&
1357             (dc->out->user_needs_vblank)) {
1358                 dc->out->user_needs_vblank = false;
1359                 complete(&dc->out->user_vblank_comp);
1360         }
1361
1362         if (status & V_BLANK_INT) {
1363                 /* Sync up windows. */
1364                 tegra_dc_trigger_windows(dc);
1365
1366                 /* Schedule any additional bottom-half vblank actvities. */
1367                 queue_work(system_freezable_wq, &dc->vblank_work);
1368         }
1369
1370         if (status & FRAME_END_INT) {
1371                 /* Mark the frame_end as complete. */
1372                 if (!completion_done(&dc->frame_end_complete))
1373                         complete(&dc->frame_end_complete);
1374         }
1375 }
1376
1377 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1378 {
1379         /* Schedule any additional bottom-half vblank actvities. */
1380         if (status & V_BLANK_INT)
1381                 queue_work(system_freezable_wq, &dc->vblank_work);
1382
1383         if (status & FRAME_END_INT) {
1384                 struct timespec tm = CURRENT_TIME;
1385                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1386                 wake_up(&dc->timestamp_wq);
1387
1388                 /* Mark the frame_end as complete. */
1389                 if (!completion_done(&dc->frame_end_complete))
1390                         complete(&dc->frame_end_complete);
1391
1392                 tegra_dc_trigger_windows(dc);
1393         }
1394 }
1395
1396 /* XXX: Not sure if we limit look ahead to 1 frame */
1397 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1398 {
1399         BUG_ON(!dc->frametime_ns);
1400         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1401 }
1402
1403 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1404 {
1405         BUG_ON(!dc->frametime_ns);
1406         return (((new_ts - old_ts) > dc->frametime_ns)
1407                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1408                         != div_s64((old_ts - dc->frame_end_timestamp),
1409                                 dc->frametime_ns)));
1410 }
1411 #endif
1412
1413 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1414 {
1415 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1416         struct tegra_dc *dc = ptr;
1417         unsigned long status;
1418         unsigned long underflow_mask;
1419         u32 val;
1420
1421         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1422                 WARN(1, "IRQ when DC not powered!\n");
1423                 tegra_dc_io_start(dc);
1424                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1425                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1426                 tegra_dc_io_end(dc);
1427                 return IRQ_HANDLED;
1428         }
1429
1430         /* clear all status flags except underflow, save those for the worker */
1431         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1432         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1433         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1434         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1435
1436         /*
1437          * Overlays can get thier internal state corrupted during and underflow
1438          * condition.  The only way to fix this state is to reset the DC.
1439          * if we get 4 consecutive frames with underflows, assume we're
1440          * hosed and reset.
1441          */
1442         underflow_mask = status & ALL_UF_INT;
1443
1444         /* Check underflow */
1445         if (underflow_mask) {
1446                 dc->underflow_mask |= underflow_mask;
1447                 schedule_delayed_work(&dc->underflow_work,
1448                         msecs_to_jiffies(1));
1449         }
1450
1451         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1452                 tegra_dc_one_shot_irq(dc, status);
1453         else
1454                 tegra_dc_continuous_irq(dc, status);
1455
1456         return IRQ_HANDLED;
1457 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1458         return IRQ_NONE;
1459 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1460 }
1461
1462 void tegra_dc_set_color_control(struct tegra_dc *dc)
1463 {
1464         u32 color_control;
1465
1466         switch (dc->out->depth) {
1467         case 3:
1468                 color_control = BASE_COLOR_SIZE111;
1469                 break;
1470
1471         case 6:
1472                 color_control = BASE_COLOR_SIZE222;
1473                 break;
1474
1475         case 8:
1476                 color_control = BASE_COLOR_SIZE332;
1477                 break;
1478
1479         case 9:
1480                 color_control = BASE_COLOR_SIZE333;
1481                 break;
1482
1483         case 12:
1484                 color_control = BASE_COLOR_SIZE444;
1485                 break;
1486
1487         case 15:
1488                 color_control = BASE_COLOR_SIZE555;
1489                 break;
1490
1491         case 16:
1492                 color_control = BASE_COLOR_SIZE565;
1493                 break;
1494
1495         case 18:
1496                 color_control = BASE_COLOR_SIZE666;
1497                 break;
1498
1499         default:
1500                 color_control = BASE_COLOR_SIZE888;
1501                 break;
1502         }
1503
1504         switch (dc->out->dither) {
1505         case TEGRA_DC_DISABLE_DITHER:
1506                 color_control |= DITHER_CONTROL_DISABLE;
1507                 break;
1508         case TEGRA_DC_ORDERED_DITHER:
1509                 color_control |= DITHER_CONTROL_ORDERED;
1510                 break;
1511         case TEGRA_DC_ERRDIFF_DITHER:
1512                 /* The line buffer for error-diffusion dither is limited
1513                  * to 1280 pixels per line. This limits the maximum
1514                  * horizontal active area size to 1280 pixels when error
1515                  * diffusion is enabled.
1516                  */
1517                 BUG_ON(dc->mode.h_active > 1280);
1518                 color_control |= DITHER_CONTROL_ERRDIFF;
1519                 break;
1520         }
1521
1522 #ifdef CONFIG_TEGRA_DC_CMU
1523         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1524                 color_control |= CMU_ENABLE;
1525 #endif
1526
1527         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1528 }
1529
1530 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1531 {
1532         u32 syncpt_id;
1533
1534         switch (dc->ndev->id) {
1535         case 0:
1536                 switch (idx) {
1537                 case 0:
1538                         syncpt_id = NVSYNCPT_DISP0_A;
1539                         break;
1540                 case 1:
1541                         syncpt_id = NVSYNCPT_DISP0_B;
1542                         break;
1543                 case 2:
1544                         syncpt_id = NVSYNCPT_DISP0_C;
1545                         break;
1546                 default:
1547                         BUG();
1548                         break;
1549                 }
1550                 break;
1551         case 1:
1552                 switch (idx) {
1553                 case 0:
1554                         syncpt_id = NVSYNCPT_DISP1_A;
1555                         break;
1556                 case 1:
1557                         syncpt_id = NVSYNCPT_DISP1_B;
1558                         break;
1559                 case 2:
1560                         syncpt_id = NVSYNCPT_DISP1_C;
1561                         break;
1562                 default:
1563                         BUG();
1564                         break;
1565                 }
1566                 break;
1567         default:
1568                 BUG();
1569                 break;
1570         }
1571
1572         return syncpt_id;
1573 }
1574
1575 static int tegra_dc_init(struct tegra_dc *dc)
1576 {
1577         int i;
1578         int int_enable;
1579
1580         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1581         if (dc->ndev->id == 0) {
1582                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1583                                       TEGRA_MC_PRIO_MED);
1584                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1585                                       TEGRA_MC_PRIO_MED);
1586                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1587                                       TEGRA_MC_PRIO_MED);
1588 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1589                 /* only present on Tegra2 and 3 */
1590                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1591                                       TEGRA_MC_PRIO_MED);
1592 #endif
1593                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1594                                       TEGRA_MC_PRIO_HIGH);
1595         } else if (dc->ndev->id == 1) {
1596                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1597                                       TEGRA_MC_PRIO_MED);
1598                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1599                                       TEGRA_MC_PRIO_MED);
1600                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1601                                       TEGRA_MC_PRIO_MED);
1602 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1603                 /* only present on Tegra2 and 3 */
1604                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1605                                       TEGRA_MC_PRIO_MED);
1606 #endif
1607                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1608                                       TEGRA_MC_PRIO_HIGH);
1609         }
1610         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1611                         DC_CMD_CONT_SYNCPT_VSYNC);
1612         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1613         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1614         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1615         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1616 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1617         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1618 #endif
1619         /* enable interrupts for vblank, frame_end and underflows */
1620         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1621         /* for panels with one-shot mode enable tearing effect interrupt */
1622         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1623                 int_enable |= MSF_INT;
1624
1625         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1626         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1627
1628         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1629
1630 #ifdef CONFIG_TEGRA_DC_CMU
1631         if (dc->pdata->cmu)
1632                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
1633         else
1634                 tegra_dc_update_cmu(dc, &default_cmu);
1635 #endif
1636
1637         tegra_dc_set_color_control(dc);
1638         for (i = 0; i < DC_N_WINDOWS; i++) {
1639                 struct tegra_dc_win *win = &dc->windows[i];
1640                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1641                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1642                 tegra_dc_set_csc(dc, &win->csc);
1643                 tegra_dc_set_lut(dc, win);
1644                 tegra_dc_set_scaling_filter(dc);
1645         }
1646
1647         for (i = 0; i < dc->n_windows; i++) {
1648                 u32 syncpt = get_syncpt(dc, i);
1649
1650                 dc->syncpt[i].id = syncpt;
1651
1652                 dc->syncpt[i].min = dc->syncpt[i].max =
1653                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1654         }
1655
1656         trace_display_mode(dc, &dc->mode);
1657
1658         if (dc->mode.pclk)
1659                 if (tegra_dc_program_mode(dc, &dc->mode))
1660                         return -EINVAL;
1661
1662         /* Initialize SD AFTER the modeset.
1663            nvsd_init handles the sd_settings = NULL case. */
1664         nvsd_init(dc, dc->out->sd_settings);
1665
1666         return 0;
1667 }
1668
1669 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1670 {
1671         int failed_init = 0;
1672
1673         if (dc->out->enable)
1674                 dc->out->enable(&dc->ndev->dev);
1675
1676         tegra_dc_setup_clk(dc, dc->clk);
1677         tegra_dc_clk_enable(dc);
1678
1679         tegra_dc_power_on(dc);
1680
1681         /* do not accept interrupts during initialization */
1682         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1683
1684         enable_dc_irq(dc->irq);
1685
1686         failed_init = tegra_dc_init(dc);
1687         if (failed_init) {
1688                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1689                 disable_irq(dc->irq);
1690                 tegra_dc_clear_bandwidth(dc);
1691                 tegra_dc_clk_disable(dc);
1692                 if (dc->out && dc->out->disable)
1693                         dc->out->disable();
1694                 return false;
1695         }
1696
1697         if (dc->out_ops && dc->out_ops->enable)
1698                 dc->out_ops->enable(dc);
1699
1700         /* force a full blending update */
1701         dc->blend.z[0] = -1;
1702
1703         tegra_dc_ext_enable(dc->ext);
1704
1705         trace_display_enable(dc);
1706
1707         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1708         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1709
1710         if (dc->out->postpoweron)
1711                 dc->out->postpoweron();
1712
1713         return true;
1714 }
1715
1716 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1717 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1718 {
1719         bool ret = true;
1720
1721         if (dc->out->enable)
1722                 dc->out->enable(&dc->ndev->dev);
1723
1724         tegra_dc_setup_clk(dc, dc->clk);
1725         tegra_dc_clk_enable(dc);
1726
1727         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1728                 mutex_lock(&tegra_dcs[1]->lock);
1729                 disable_irq(tegra_dcs[1]->irq);
1730         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1731                 mutex_lock(&tegra_dcs[0]->lock);
1732                 disable_irq(tegra_dcs[0]->irq);
1733         }
1734
1735         msleep(5);
1736         tegra_periph_reset_assert(dc->clk);
1737         msleep(2);
1738 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1739         tegra_periph_reset_deassert(dc->clk);
1740         msleep(1);
1741 #endif
1742
1743         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1744                 enable_dc_irq(tegra_dcs[1]->irq);
1745                 mutex_unlock(&tegra_dcs[1]->lock);
1746         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1747                 enable_dc_irq(tegra_dcs[0]->irq);
1748                 mutex_unlock(&tegra_dcs[0]->lock);
1749         }
1750
1751         enable_dc_irq(dc->irq);
1752
1753         if (tegra_dc_init(dc)) {
1754                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1755                 ret = false;
1756         }
1757
1758         if (dc->out_ops && dc->out_ops->enable)
1759                 dc->out_ops->enable(dc);
1760
1761         if (dc->out->postpoweron)
1762                 dc->out->postpoweron();
1763
1764         /* force a full blending update */
1765         dc->blend.z[0] = -1;
1766
1767         tegra_dc_ext_enable(dc->ext);
1768
1769         if (!ret) {
1770                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1771                 _tegra_dc_controller_disable(dc);
1772         }
1773
1774         trace_display_reset(dc);
1775         return ret;
1776 }
1777 #endif
1778
1779 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1780 {
1781         if (dc->mode.pclk == 0) {
1782                 switch (dc->out->type) {
1783                 case TEGRA_DC_OUT_HDMI:
1784                 /* DC enable called but no videomode is loaded.
1785                      Check if HDMI is connected, then set fallback mdoe */
1786                 if (tegra_dc_hpd(dc)) {
1787                         return tegra_dc_set_fb_mode(dc,
1788                                         &tegra_dc_hdmi_fallback_mode, 0);
1789                 } else
1790                         return false;
1791
1792                 break;
1793
1794                 /* Do nothing for other outputs for now */
1795                 case TEGRA_DC_OUT_RGB:
1796
1797                 case TEGRA_DC_OUT_DSI:
1798
1799                 default:
1800                         return false;
1801                 }
1802         }
1803
1804         return false;
1805 }
1806
1807 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1808 {
1809         return _tegra_dc_set_default_videomode(dc);
1810 }
1811
1812 static bool _tegra_dc_enable(struct tegra_dc *dc)
1813 {
1814         if (dc->mode.pclk == 0)
1815                 return false;
1816
1817         if (!dc->out)
1818                 return false;
1819
1820         tegra_dc_io_start(dc);
1821
1822         if (!_tegra_dc_controller_enable(dc)) {
1823                 tegra_dc_io_end(dc);
1824                 return false;
1825         }
1826         return true;
1827 }
1828
1829 void tegra_dc_enable(struct tegra_dc *dc)
1830 {
1831         mutex_lock(&dc->lock);
1832
1833         if (!dc->enabled)
1834                 dc->enabled = _tegra_dc_enable(dc);
1835
1836         mutex_unlock(&dc->lock);
1837         trace_display_mode(dc, &dc->mode);
1838 }
1839
1840 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1841 {
1842         unsigned i;
1843
1844         if (dc->out && dc->out->prepoweroff)
1845                 dc->out->prepoweroff();
1846
1847         if (dc->out_ops && dc->out_ops->disable)
1848                 dc->out_ops->disable(dc);
1849
1850         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1851         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1852         disable_irq(dc->irq);
1853
1854         tegra_dc_clear_bandwidth(dc);
1855         tegra_dc_clk_disable(dc);
1856
1857         if (dc->out && dc->out->disable)
1858                 dc->out->disable();
1859
1860         for (i = 0; i < dc->n_windows; i++) {
1861                 struct tegra_dc_win *w = &dc->windows[i];
1862
1863                 /* reset window bandwidth */
1864                 w->bandwidth = 0;
1865                 w->new_bandwidth = 0;
1866
1867                 /* disable windows */
1868                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1869
1870                 /* flush any pending syncpt waits */
1871                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1872                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1873                                 dc->syncpt[i].min, dc->syncpt[i].max);
1874                         dc->syncpt[i].min++;
1875                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1876                 }
1877         }
1878         trace_display_disable(dc);
1879 }
1880
1881 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1882 {
1883 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1884         u32 val;
1885         if (dc->enabled)  {
1886                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1887                 if (enable)
1888                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1889                 else
1890                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1891                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1892         }
1893 #endif
1894 }
1895
1896 bool tegra_dc_stats_get(struct tegra_dc *dc)
1897 {
1898 #if 0 /* right now it is always enabled */
1899         u32 val;
1900         bool res;
1901
1902         if (dc->enabled)  {
1903                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1904                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1905         } else {
1906                 res = false;
1907         }
1908
1909         return res;
1910 #endif
1911         return true;
1912 }
1913
1914 /* make the screen blank by disabling all windows */
1915 void tegra_dc_blank(struct tegra_dc *dc)
1916 {
1917         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1918         unsigned i;
1919
1920         for (i = 0; i < DC_N_WINDOWS; i++) {
1921                 dcwins[i] = tegra_dc_get_window(dc, i);
1922                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1923         }
1924
1925         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1926         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1927 }
1928
1929 static void _tegra_dc_disable(struct tegra_dc *dc)
1930 {
1931         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1932                 mutex_lock(&dc->one_shot_lock);
1933                 cancel_delayed_work_sync(&dc->one_shot_work);
1934         }
1935
1936         tegra_dc_hold_dc_out(dc);
1937
1938         _tegra_dc_controller_disable(dc);
1939         tegra_dc_io_end(dc);
1940
1941         tegra_dc_release_dc_out(dc);
1942
1943         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1944                 mutex_unlock(&dc->one_shot_lock);
1945 }
1946
1947 void tegra_dc_disable(struct tegra_dc *dc)
1948 {
1949         tegra_dc_ext_disable(dc->ext);
1950
1951         /* it's important that new underflow work isn't scheduled before the
1952          * lock is acquired. */
1953         cancel_delayed_work_sync(&dc->underflow_work);
1954
1955         mutex_lock(&dc->lock);
1956
1957         if (dc->enabled) {
1958                 dc->enabled = false;
1959
1960                 if (!dc->suspended)
1961                         _tegra_dc_disable(dc);
1962         }
1963
1964 #ifdef CONFIG_SWITCH
1965         switch_set_state(&dc->modeset_switch, 0);
1966 #endif
1967
1968         mutex_unlock(&dc->lock);
1969         trace_display_mode(dc, &dc->mode);
1970 }
1971
1972 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1973 static void tegra_dc_reset_worker(struct work_struct *work)
1974 {
1975         struct tegra_dc *dc =
1976                 container_of(work, struct tegra_dc, reset_work);
1977
1978         unsigned long val = 0;
1979
1980         mutex_lock(&shared_lock);
1981
1982         dev_warn(&dc->ndev->dev,
1983                 "overlay stuck in underflow state.  resetting.\n");
1984
1985         tegra_dc_ext_disable(dc->ext);
1986
1987         mutex_lock(&dc->lock);
1988
1989         if (dc->enabled == false)
1990                 goto unlock;
1991
1992         dc->enabled = false;
1993
1994         /*
1995          * off host read bus
1996          */
1997         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1998         val &= ~(0x00000100);
1999         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2000
2001         /*
2002          * set DC to STOP mode
2003          */
2004         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2005
2006         msleep(10);
2007
2008         _tegra_dc_controller_disable(dc);
2009
2010         /* _tegra_dc_controller_reset_enable deasserts reset */
2011         _tegra_dc_controller_reset_enable(dc);
2012
2013         dc->enabled = true;
2014
2015         /* reopen host read bus */
2016         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2017         val &= ~(0x00000100);
2018         val |= 0x100;
2019         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2020
2021 unlock:
2022         mutex_unlock(&dc->lock);
2023         mutex_unlock(&shared_lock);
2024         trace_display_reset(dc);
2025 }
2026 #endif
2027
2028 static void tegra_dc_underflow_worker(struct work_struct *work)
2029 {
2030         struct tegra_dc *dc = container_of(
2031                 to_delayed_work(work), struct tegra_dc, underflow_work);
2032
2033         mutex_lock(&dc->lock);
2034         tegra_dc_hold_dc_out(dc);
2035
2036         if (dc->enabled) {
2037                 tegra_dc_underflow_handler(dc);
2038         }
2039         tegra_dc_release_dc_out(dc);
2040         mutex_unlock(&dc->lock);
2041 }
2042
2043 #ifdef CONFIG_SWITCH
2044 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2045 {
2046         struct tegra_dc *dc =
2047                 container_of(sdev, struct tegra_dc, modeset_switch);
2048
2049         if (!sdev->state)
2050                 return sprintf(buf, "offline\n");
2051
2052         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2053 }
2054 #endif
2055
2056 static int tegra_dc_probe(struct nvhost_device *ndev,
2057         struct nvhost_device_id *id_table)
2058 {
2059         struct tegra_dc *dc;
2060         struct tegra_dc_mode *mode;
2061         struct clk *clk;
2062         struct clk *emc_clk;
2063         struct resource *res;
2064         struct resource *base_res;
2065         struct resource *fb_mem = NULL;
2066         int ret = 0;
2067         void __iomem *base;
2068         int irq;
2069         int i;
2070
2071         if (!ndev->dev.platform_data) {
2072                 dev_err(&ndev->dev, "no platform data\n");
2073                 return -ENOENT;
2074         }
2075
2076         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2077         if (!dc) {
2078                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2079                 return -ENOMEM;
2080         }
2081
2082         irq = nvhost_get_irq_byname(ndev, "irq");
2083         if (irq <= 0) {
2084                 dev_err(&ndev->dev, "no irq\n");
2085                 ret = -ENOENT;
2086                 goto err_free;
2087         }
2088
2089         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2090         if (!res) {
2091                 dev_err(&ndev->dev, "no mem resource\n");
2092                 ret = -ENOENT;
2093                 goto err_free;
2094         }
2095
2096         base_res = request_mem_region(res->start, resource_size(res),
2097                 ndev->name);
2098         if (!base_res) {
2099                 dev_err(&ndev->dev, "request_mem_region failed\n");
2100                 ret = -EBUSY;
2101                 goto err_free;
2102         }
2103
2104         base = ioremap(res->start, resource_size(res));
2105         if (!base) {
2106                 dev_err(&ndev->dev, "registers can't be mapped\n");
2107                 ret = -EBUSY;
2108                 goto err_release_resource_reg;
2109         }
2110
2111         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2112
2113         clk = clk_get(&ndev->dev, NULL);
2114         if (IS_ERR_OR_NULL(clk)) {
2115                 dev_err(&ndev->dev, "can't get clock\n");
2116                 ret = -ENOENT;
2117                 goto err_iounmap_reg;
2118         }
2119
2120         emc_clk = clk_get(&ndev->dev, "emc");
2121         if (IS_ERR_OR_NULL(emc_clk)) {
2122                 dev_err(&ndev->dev, "can't get emc clock\n");
2123                 ret = -ENOENT;
2124                 goto err_put_clk;
2125         }
2126
2127         dc->clk = clk;
2128         dc->emc_clk = emc_clk;
2129         dc->shift_clk_div = 1;
2130         /* Initialize one shot work delay, it will be assigned by dsi
2131          * according to refresh rate later. */
2132         dc->one_shot_delay_ms = 40;
2133
2134         dc->base_res = base_res;
2135         dc->base = base;
2136         dc->irq = irq;
2137         dc->ndev = ndev;
2138         dc->pdata = ndev->dev.platform_data;
2139
2140         /*
2141          * The emc is a shared clock, it will be set based on
2142          * the requirements for each user on the bus.
2143          */
2144         dc->emc_clk_rate = 0;
2145
2146         mutex_init(&dc->lock);
2147         mutex_init(&dc->one_shot_lock);
2148         init_completion(&dc->frame_end_complete);
2149         init_waitqueue_head(&dc->wq);
2150         init_waitqueue_head(&dc->timestamp_wq);
2151 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2152         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2153 #endif
2154         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2155         dc->vblank_ref_count = 0;
2156         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2157         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2158
2159         tegra_dc_init_lut_defaults(&dc->fb_lut);
2160
2161         dc->n_windows = DC_N_WINDOWS;
2162         for (i = 0; i < dc->n_windows; i++) {
2163                 struct tegra_dc_win *win = &dc->windows[i];
2164                 win->idx = i;
2165                 win->dc = dc;
2166                 tegra_dc_init_csc_defaults(&win->csc);
2167                 tegra_dc_init_lut_defaults(&win->lut);
2168         }
2169
2170         ret = tegra_dc_set(dc, ndev->id);
2171         if (ret < 0) {
2172                 dev_err(&ndev->dev, "can't add dc\n");
2173                 goto err_free_irq;
2174         }
2175
2176         nvhost_set_drvdata(ndev, dc);
2177
2178 #ifdef CONFIG_SWITCH
2179         dc->modeset_switch.name = dev_name(&ndev->dev);
2180         dc->modeset_switch.state = 0;
2181         dc->modeset_switch.print_state = switch_modeset_print_mode;
2182         ret = switch_dev_register(&dc->modeset_switch);
2183         if (ret < 0)
2184                 dev_err(&ndev->dev, "failed to register switch driver\n");
2185 #endif
2186
2187         tegra_dc_feature_register(dc);
2188
2189         if (dc->pdata->default_out)
2190                 tegra_dc_set_out(dc, dc->pdata->default_out);
2191         else
2192                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2193
2194         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2195                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2196
2197         dc->ext = tegra_dc_ext_register(ndev, dc);
2198         if (IS_ERR_OR_NULL(dc->ext)) {
2199                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2200                 dc->ext = NULL;
2201         }
2202
2203         /* interrupt handler must be registered before tegra_fb_register() */
2204         if (request_irq(irq, tegra_dc_irq, 0,
2205                         dev_name(&ndev->dev), dc)) {
2206                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2207                 ret = -EBUSY;
2208                 goto err_put_emc_clk;
2209         }
2210
2211         mutex_lock(&dc->lock);
2212         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2213                 _tegra_dc_set_default_videomode(dc);
2214                 dc->enabled = _tegra_dc_enable(dc);
2215         }
2216         mutex_unlock(&dc->lock);
2217
2218         tegra_dc_create_debugfs(dc);
2219
2220         dev_info(&ndev->dev, "probed\n");
2221
2222         if (dc->pdata->fb) {
2223                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2224                         unsigned long fmt;
2225                         tegra_dc_writel(dc,
2226                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2227                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2228
2229                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2230                         dc->pdata->fb->bits_per_pixel =
2231                                 tegra_dc_fmt_bpp(fmt);
2232                 }
2233
2234                 mode = tegra_dc_get_override_mode(dc);
2235                 if (mode) {
2236                         dc->pdata->fb->xres = mode->h_active;
2237                         dc->pdata->fb->yres = mode->v_active;
2238                 }
2239
2240                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2241                 if (IS_ERR_OR_NULL(dc->fb))
2242                         dc->fb = NULL;
2243         }
2244
2245         if (dc->out && dc->out->hotplug_init)
2246                 dc->out->hotplug_init(&ndev->dev);
2247
2248         if (dc->out_ops && dc->out_ops->detect)
2249                 dc->out_ops->detect(dc);
2250         else
2251                 dc->connected = true;
2252
2253         tegra_dc_create_sysfs(&dc->ndev->dev);
2254
2255         return 0;
2256
2257 err_free_irq:
2258         free_irq(irq, dc);
2259 err_put_emc_clk:
2260         clk_put(emc_clk);
2261 err_put_clk:
2262         clk_put(clk);
2263 err_iounmap_reg:
2264         iounmap(base);
2265         if (fb_mem)
2266                 release_resource(fb_mem);
2267 err_release_resource_reg:
2268         release_resource(base_res);
2269 err_free:
2270         kfree(dc);
2271
2272         return ret;
2273 }
2274
2275 static int tegra_dc_remove(struct nvhost_device *ndev)
2276 {
2277         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2278
2279         tegra_dc_remove_sysfs(&dc->ndev->dev);
2280         tegra_dc_remove_debugfs(dc);
2281
2282         if (dc->fb) {
2283                 tegra_fb_unregister(dc->fb);
2284                 if (dc->fb_mem)
2285                         release_resource(dc->fb_mem);
2286         }
2287
2288         tegra_dc_ext_disable(dc->ext);
2289
2290         if (dc->ext)
2291                 tegra_dc_ext_unregister(dc->ext);
2292
2293         if (dc->enabled)
2294                 _tegra_dc_disable(dc);
2295
2296 #ifdef CONFIG_SWITCH
2297         switch_dev_unregister(&dc->modeset_switch);
2298 #endif
2299         free_irq(dc->irq, dc);
2300         clk_put(dc->emc_clk);
2301         clk_put(dc->clk);
2302         iounmap(dc->base);
2303         if (dc->fb_mem)
2304                 release_resource(dc->base_res);
2305         kfree(dc);
2306         tegra_dc_set(NULL, ndev->id);
2307         return 0;
2308 }
2309
2310 #ifdef CONFIG_PM
2311 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2312 {
2313         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2314
2315         trace_display_suspend(dc);
2316         dev_info(&ndev->dev, "suspend\n");
2317
2318         tegra_dc_ext_disable(dc->ext);
2319
2320         mutex_lock(&dc->lock);
2321
2322         if (dc->out_ops && dc->out_ops->suspend)
2323                 dc->out_ops->suspend(dc);
2324
2325         if (dc->enabled) {
2326                 _tegra_dc_disable(dc);
2327
2328                 dc->suspended = true;
2329         }
2330
2331         if (dc->out && dc->out->postsuspend) {
2332                 dc->out->postsuspend();
2333                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2334                         /*
2335                          * avoid resume event due to voltage falling
2336                          */
2337                         msleep(100);
2338         }
2339
2340         mutex_unlock(&dc->lock);
2341
2342         return 0;
2343 }
2344
2345 static int tegra_dc_resume(struct nvhost_device *ndev)
2346 {
2347         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2348
2349         trace_display_resume(dc);
2350         dev_info(&ndev->dev, "resume\n");
2351
2352         mutex_lock(&dc->lock);
2353         dc->suspended = false;
2354
2355         if (dc->enabled) {
2356                 _tegra_dc_set_default_videomode(dc);
2357                 _tegra_dc_enable(dc);
2358         }
2359
2360         if (dc->out && dc->out->hotplug_init)
2361                 dc->out->hotplug_init(&ndev->dev);
2362
2363         if (dc->out_ops && dc->out_ops->resume)
2364                 dc->out_ops->resume(dc);
2365         mutex_unlock(&dc->lock);
2366
2367         return 0;
2368 }
2369
2370 #endif /* CONFIG_PM */
2371
2372 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2373 {
2374         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2375
2376         if (!dc || !dc->enabled)
2377                 return;
2378
2379         tegra_dc_blank(dc);
2380         tegra_dc_disable(dc);
2381 }
2382
2383 extern int suspend_set(const char *val, struct kernel_param *kp)
2384 {
2385         if (!strcmp(val, "dump"))
2386                 dump_regs(tegra_dcs[0]);
2387 #ifdef CONFIG_PM
2388         else if (!strcmp(val, "suspend"))
2389                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2390         else if (!strcmp(val, "resume"))
2391                 tegra_dc_resume(tegra_dcs[0]->ndev);
2392 #endif
2393
2394         return 0;
2395 }
2396
2397 extern int suspend_get(char *buffer, struct kernel_param *kp)
2398 {
2399         return 0;
2400 }
2401
2402 int suspend;
2403
2404 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2405
2406 struct nvhost_driver tegra_dc_driver = {
2407         .driver = {
2408                 .name = "tegradc",
2409                 .owner = THIS_MODULE,
2410         },
2411         .probe = tegra_dc_probe,
2412         .remove = tegra_dc_remove,
2413 #ifdef CONFIG_PM
2414         .suspend = tegra_dc_suspend,
2415         .resume = tegra_dc_resume,
2416 #endif
2417         .shutdown = tegra_dc_shutdown,
2418 };
2419
2420 #ifndef MODULE
2421 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2422 {
2423         int i, params[11];
2424         char *p;
2425
2426         for (i = 0; i < ARRAY_SIZE(params); i++) {
2427                 if ((p = strsep(&options, ",")) != NULL) {
2428                         if (*p)
2429                                 params[i] = simple_strtoul(p, &p, 10);
2430                 } else
2431                         return -EINVAL;
2432         }
2433
2434         if ((mode->pclk = params[0]) == 0)
2435                 return -EINVAL;
2436
2437         mode->h_active      = params[1];
2438         mode->v_active      = params[2];
2439         mode->h_ref_to_sync = params[3];
2440         mode->v_ref_to_sync = params[4];
2441         mode->h_sync_width  = params[5];
2442         mode->v_sync_width  = params[6];
2443         mode->h_back_porch  = params[7];
2444         mode->v_back_porch  = params[8];
2445         mode->h_front_porch = params[9];
2446         mode->v_front_porch = params[10];
2447
2448         return 0;
2449 }
2450
2451 static int __init tegra_dc_mode_override(char *str)
2452 {
2453         char *p = str, *options;
2454
2455         if (!p || !*p)
2456                 return -EINVAL;
2457
2458         p = strstr(str, "hdmi:");
2459         if (p) {
2460                 p += 5;
2461                 options = strsep(&p, ";");
2462                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2463                         return -EINVAL;
2464         }
2465
2466         p = strstr(str, "rgb:");
2467         if (p) {
2468                 p += 4;
2469                 options = strsep(&p, ";");
2470                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2471                         return -EINVAL;
2472         }
2473
2474         p = strstr(str, "dsi:");
2475         if (p) {
2476                 p += 4;
2477                 options = strsep(&p, ";");
2478                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2479                         return -EINVAL;
2480         }
2481
2482         return 0;
2483 }
2484
2485 __setup("disp_params=", tegra_dc_mode_override);
2486 #endif
2487
2488 static int __init tegra_dc_module_init(void)
2489 {
2490         int ret = tegra_dc_ext_module_init();
2491         if (ret)
2492                 return ret;
2493         return nvhost_driver_register(&tegra_dc_driver);
2494 }
2495
2496 static void __exit tegra_dc_module_exit(void)
2497 {
2498         nvhost_driver_unregister(&tegra_dc_driver);
2499         tegra_dc_ext_module_exit();
2500 }
2501
2502 module_exit(tegra_dc_module_exit);
2503 module_init(tegra_dc_module_init);