video: tegra: dc: fix MC_DECERR display0_win errors on shutdown
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "host1x/host1x_syncpt.h"
56 #include "nvsd.h"
57
58 #define TEGRA_CRC_LATCHED_DELAY         34
59
60 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
61 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
62
63 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
64 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
65 #else
66 /* ignore underflows when on simulation and fpga platform */
67 #define ALL_UF_INT (0)
68 #endif
69
70 static int no_vsync;
71 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
72         .refresh = 60,
73         .xres = 640,
74         .yres = 480,
75         .pixclock = KHZ2PICOS(25200),
76         .hsync_len = 96,        /* h_sync_width */
77         .vsync_len = 2,         /* v_sync_width */
78         .left_margin = 48,      /* h_back_porch */
79         .upper_margin = 33,     /* v_back_porch */
80         .right_margin = 16,     /* h_front_porch */
81         .lower_margin = 10,     /* v_front_porch */
82         .vmode = 0,
83         .sync = 0,
84 };
85
86 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
87
88 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
89
90 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
91
92 DEFINE_MUTEX(tegra_dc_lock);
93 DEFINE_MUTEX(shared_lock);
94
95 static const struct {
96         bool h;
97         bool v;
98 } can_filter[] = {
99         /* Window A has no filtering */
100         { false, false },
101         /* Window B has both H and V filtering */
102         { true,  true  },
103         /* Window C has only H filtering */
104         { false, true  },
105 };
106
107 #ifdef CONFIG_TEGRA_DC_CMU
108 static struct tegra_dc_cmu default_cmu = {
109         /* lut1 maps sRGB to linear space. */
110         {
111                 0,    1,    2,    4,    5,    6,    7,    9,
112                 10,   11,   12,   14,   15,   16,   18,   20,
113                 21,   23,   25,   27,   29,   31,   33,   35,
114                 37,   40,   42,   45,   48,   50,   53,   56,
115                 59,   62,   66,   69,   72,   76,   79,   83,
116                 87,   91,   95,   99,   103,  107,  112,  116,
117                 121,  126,  131,  136,  141,  146,  151,  156,
118                 162,  168,  173,  179,  185,  191,  197,  204,
119                 210,  216,  223,  230,  237,  244,  251,  258,
120                 265,  273,  280,  288,  296,  304,  312,  320,
121                 329,  337,  346,  354,  363,  372,  381,  390,
122                 400,  409,  419,  428,  438,  448,  458,  469,
123                 479,  490,  500,  511,  522,  533,  544,  555,
124                 567,  578,  590,  602,  614,  626,  639,  651,
125                 664,  676,  689,  702,  715,  728,  742,  755,
126                 769,  783,  797,  811,  825,  840,  854,  869,
127                 884,  899,  914,  929,  945,  960,  976,  992,
128                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
129                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
130                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
131                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
132                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
133                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
134                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
135                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
136                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
137                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
138                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
139                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
140                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
141                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
142                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
143         },
144         /* csc */
145         {
146                 0x100, 0x0,   0x0,
147                 0x0,   0x100, 0x0,
148                 0x0,   0x0,   0x100,
149         },
150         /* lut2 maps linear space to sRGB*/
151         {
152                 0,    1,    2,    2,    3,    4,    5,    6,
153                 6,    7,    8,    9,    10,   10,   11,   12,
154                 13,   13,   14,   15,   15,   16,   16,   17,
155                 18,   18,   19,   19,   20,   20,   21,   21,
156                 22,   22,   23,   23,   23,   24,   24,   25,
157                 25,   25,   26,   26,   27,   27,   27,   28,
158                 28,   29,   29,   29,   30,   30,   30,   31,
159                 31,   31,   32,   32,   32,   33,   33,   33,
160                 34,   34,   34,   34,   35,   35,   35,   36,
161                 36,   36,   37,   37,   37,   37,   38,   38,
162                 38,   38,   39,   39,   39,   40,   40,   40,
163                 40,   41,   41,   41,   41,   42,   42,   42,
164                 42,   43,   43,   43,   43,   43,   44,   44,
165                 44,   44,   45,   45,   45,   45,   46,   46,
166                 46,   46,   46,   47,   47,   47,   47,   48,
167                 48,   48,   48,   48,   49,   49,   49,   49,
168                 49,   50,   50,   50,   50,   50,   51,   51,
169                 51,   51,   51,   52,   52,   52,   52,   52,
170                 53,   53,   53,   53,   53,   54,   54,   54,
171                 54,   54,   55,   55,   55,   55,   55,   55,
172                 56,   56,   56,   56,   56,   57,   57,   57,
173                 57,   57,   57,   58,   58,   58,   58,   58,
174                 58,   59,   59,   59,   59,   59,   59,   60,
175                 60,   60,   60,   60,   60,   61,   61,   61,
176                 61,   61,   61,   62,   62,   62,   62,   62,
177                 62,   63,   63,   63,   63,   63,   63,   64,
178                 64,   64,   64,   64,   64,   64,   65,   65,
179                 65,   65,   65,   65,   66,   66,   66,   66,
180                 66,   66,   66,   67,   67,   67,   67,   67,
181                 67,   67,   68,   68,   68,   68,   68,   68,
182                 68,   69,   69,   69,   69,   69,   69,   69,
183                 70,   70,   70,   70,   70,   70,   70,   71,
184                 71,   71,   71,   71,   71,   71,   72,   72,
185                 72,   72,   72,   72,   72,   72,   73,   73,
186                 73,   73,   73,   73,   73,   74,   74,   74,
187                 74,   74,   74,   74,   74,   75,   75,   75,
188                 75,   75,   75,   75,   75,   76,   76,   76,
189                 76,   76,   76,   76,   77,   77,   77,   77,
190                 77,   77,   77,   77,   78,   78,   78,   78,
191                 78,   78,   78,   78,   78,   79,   79,   79,
192                 79,   79,   79,   79,   79,   80,   80,   80,
193                 80,   80,   80,   80,   80,   81,   81,   81,
194                 81,   81,   81,   81,   81,   81,   82,   82,
195                 82,   82,   82,   82,   82,   82,   83,   83,
196                 83,   83,   83,   83,   83,   83,   83,   84,
197                 84,   84,   84,   84,   84,   84,   84,   84,
198                 85,   85,   85,   85,   85,   85,   85,   85,
199                 85,   86,   86,   86,   86,   86,   86,   86,
200                 86,   86,   87,   87,   87,   87,   87,   87,
201                 87,   87,   87,   88,   88,   88,   88,   88,
202                 88,   88,   88,   88,   88,   89,   89,   89,
203                 89,   89,   89,   89,   89,   89,   90,   90,
204                 90,   90,   90,   90,   90,   90,   90,   90,
205                 91,   91,   91,   91,   91,   91,   91,   91,
206                 91,   91,   92,   92,   92,   92,   92,   92,
207                 92,   92,   92,   92,   93,   93,   93,   93,
208                 93,   93,   93,   93,   93,   93,   94,   94,
209                 94,   94,   94,   94,   94,   94,   94,   94,
210                 95,   95,   95,   95,   95,   95,   95,   95,
211                 95,   95,   96,   96,   96,   96,   96,   96,
212                 96,   96,   96,   96,   96,   97,   97,   97,
213                 97,   97,   97,   97,   97,   97,   97,   98,
214                 98,   98,   98,   98,   98,   98,   98,   98,
215                 98,   98,   99,   99,   99,   99,   99,   99,
216                 99,   100,  101,  101,  102,  103,  103,  104,
217                 105,  105,  106,  107,  107,  108,  109,  109,
218                 110,  111,  111,  112,  113,  113,  114,  115,
219                 115,  116,  116,  117,  118,  118,  119,  119,
220                 120,  120,  121,  122,  122,  123,  123,  124,
221                 124,  125,  126,  126,  127,  127,  128,  128,
222                 129,  129,  130,  130,  131,  131,  132,  132,
223                 133,  133,  134,  134,  135,  135,  136,  136,
224                 137,  137,  138,  138,  139,  139,  140,  140,
225                 141,  141,  142,  142,  143,  143,  144,  144,
226                 145,  145,  145,  146,  146,  147,  147,  148,
227                 148,  149,  149,  150,  150,  150,  151,  151,
228                 152,  152,  153,  153,  153,  154,  154,  155,
229                 155,  156,  156,  156,  157,  157,  158,  158,
230                 158,  159,  159,  160,  160,  160,  161,  161,
231                 162,  162,  162,  163,  163,  164,  164,  164,
232                 165,  165,  166,  166,  166,  167,  167,  167,
233                 168,  168,  169,  169,  169,  170,  170,  170,
234                 171,  171,  172,  172,  172,  173,  173,  173,
235                 174,  174,  174,  175,  175,  176,  176,  176,
236                 177,  177,  177,  178,  178,  178,  179,  179,
237                 179,  180,  180,  180,  181,  181,  182,  182,
238                 182,  183,  183,  183,  184,  184,  184,  185,
239                 185,  185,  186,  186,  186,  187,  187,  187,
240                 188,  188,  188,  189,  189,  189,  189,  190,
241                 190,  190,  191,  191,  191,  192,  192,  192,
242                 193,  193,  193,  194,  194,  194,  195,  195,
243                 195,  196,  196,  196,  196,  197,  197,  197,
244                 198,  198,  198,  199,  199,  199,  200,  200,
245                 200,  200,  201,  201,  201,  202,  202,  202,
246                 202,  203,  203,  203,  204,  204,  204,  205,
247                 205,  205,  205,  206,  206,  206,  207,  207,
248                 207,  207,  208,  208,  208,  209,  209,  209,
249                 209,  210,  210,  210,  211,  211,  211,  211,
250                 212,  212,  212,  213,  213,  213,  213,  214,
251                 214,  214,  214,  215,  215,  215,  216,  216,
252                 216,  216,  217,  217,  217,  217,  218,  218,
253                 218,  219,  219,  219,  219,  220,  220,  220,
254                 220,  221,  221,  221,  221,  222,  222,  222,
255                 223,  223,  223,  223,  224,  224,  224,  224,
256                 225,  225,  225,  225,  226,  226,  226,  226,
257                 227,  227,  227,  227,  228,  228,  228,  228,
258                 229,  229,  229,  229,  230,  230,  230,  230,
259                 231,  231,  231,  231,  232,  232,  232,  232,
260                 233,  233,  233,  233,  234,  234,  234,  234,
261                 235,  235,  235,  235,  236,  236,  236,  236,
262                 237,  237,  237,  237,  238,  238,  238,  238,
263                 239,  239,  239,  239,  240,  240,  240,  240,
264                 240,  241,  241,  241,  241,  242,  242,  242,
265                 242,  243,  243,  243,  243,  244,  244,  244,
266                 244,  244,  245,  245,  245,  245,  246,  246,
267                 246,  246,  247,  247,  247,  247,  247,  248,
268                 248,  248,  248,  249,  249,  249,  249,  249,
269                 250,  250,  250,  250,  251,  251,  251,  251,
270                 251,  252,  252,  252,  252,  253,  253,  253,
271                 253,  253,  254,  254,  254,  254,  255,  255,
272         },
273 };
274 #endif
275
276 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
277 {
278         if (!tegra_is_clk_enabled(dc->clk)) {
279                 clk_enable(dc->clk);
280                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
281         }
282 }
283
284 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
285 {
286         if (tegra_is_clk_enabled(dc->clk)) {
287                 clk_disable(dc->clk);
288                 tegra_dvfs_set_rate(dc->clk, 0);
289         }
290 }
291
292 #define DUMP_REG(a) do {                        \
293         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
294                  #a, a, tegra_dc_readl(dc, a));               \
295         print(data, buff);                                    \
296         } while (0)
297
298 #define print_mode_info(dc, mode) do {                        \
299         trace_printk("%s:Mode settings: "                              \
300                         "ref_to_sync: H = %d V = %d, "                  \
301                         "sync_width: H = %d V = %d, "                   \
302                         "back_porch: H = %d V = %d, "                   \
303                         "active: H = %d V = %d, "                       \
304                         "front_porch: H = %d V = %d, "                  \
305                         "pclk = %d, stereo mode = %d\n",                \
306                         dc->ndev->name,                                 \
307                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
308                         mode.h_sync_width, mode.v_sync_width,           \
309                         mode.h_back_porch, mode.v_back_porch,           \
310                         mode.h_active, mode.v_active,                   \
311                         mode.h_front_porch, mode.v_front_porch,         \
312                         mode.pclk, mode.stereo_mode);                   \
313         } while (0)
314
315 #define print_underflow_info(dc) do {                 \
316         trace_printk("%s:Underflow stats: underflows : %llu, "      \
317                         "undeflows_a : %llu, "                          \
318                         "underflows_b : %llu, "                         \
319                         "underflows_c : %llu\n",                        \
320                         dc->ndev->name,                                 \
321                         dc->stats.underflows,                           \
322                         dc->stats.underflows_a, dc->stats.underflows_b, \
323                         dc->stats.underflows_c);                        \
324         } while (0)
325
326 static void _dump_regs(struct tegra_dc *dc, void *data,
327                        void (* print)(void *data, const char *str))
328 {
329         int i;
330         char buff[256];
331
332         tegra_dc_io_start(dc);
333         tegra_dc_clk_enable(dc);
334
335         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
336         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
337         DUMP_REG(DC_CMD_SIGNAL_RAISE);
338         DUMP_REG(DC_CMD_INT_STATUS);
339         DUMP_REG(DC_CMD_INT_MASK);
340         DUMP_REG(DC_CMD_INT_ENABLE);
341         DUMP_REG(DC_CMD_INT_TYPE);
342         DUMP_REG(DC_CMD_INT_POLARITY);
343         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
344         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
345         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
346         DUMP_REG(DC_CMD_STATE_ACCESS);
347         DUMP_REG(DC_CMD_STATE_CONTROL);
348         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
349         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
350
351         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
352         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
353         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
354         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
355         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
356         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
357         DUMP_REG(DC_DISP_REF_TO_SYNC);
358         DUMP_REG(DC_DISP_SYNC_WIDTH);
359         DUMP_REG(DC_DISP_BACK_PORCH);
360         DUMP_REG(DC_DISP_DISP_ACTIVE);
361         DUMP_REG(DC_DISP_FRONT_PORCH);
362         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
363         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
364         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
365         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
366         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
367         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
368         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
369         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
370         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
371         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
372         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
373         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
374         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
375         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
376         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
377         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
378         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
379         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
380         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
381         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
382         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
383         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
384         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
385         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
386         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
387         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
388         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
389         DUMP_REG(DC_DISP_M0_CONTROL);
390         DUMP_REG(DC_DISP_M1_CONTROL);
391         DUMP_REG(DC_DISP_DI_CONTROL);
392         DUMP_REG(DC_DISP_PP_CONTROL);
393         DUMP_REG(DC_DISP_PP_SELECT_A);
394         DUMP_REG(DC_DISP_PP_SELECT_B);
395         DUMP_REG(DC_DISP_PP_SELECT_C);
396         DUMP_REG(DC_DISP_PP_SELECT_D);
397         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
398         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
399         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
400         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
401         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
402         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
403         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
404         DUMP_REG(DC_DISP_BORDER_COLOR);
405         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
406         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
407         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
408         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
409         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
410         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
411         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
412         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
413         DUMP_REG(DC_DISP_CURSOR_POSITION);
414         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
415         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
416         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
417         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
418         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
419         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
420         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
421         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
422         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
423         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
424         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
425         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
426         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
427
428
429         for (i = 0; i < 3; i++) {
430                 print(data, "\n");
431                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
432                 print(data, buff);
433
434                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
435                                 DC_CMD_DISPLAY_WINDOW_HEADER);
436                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
437                 DUMP_REG(DC_WIN_WIN_OPTIONS);
438                 DUMP_REG(DC_WIN_BYTE_SWAP);
439                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
440                 DUMP_REG(DC_WIN_COLOR_DEPTH);
441                 DUMP_REG(DC_WIN_POSITION);
442                 DUMP_REG(DC_WIN_SIZE);
443                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
444                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
445                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
446                 DUMP_REG(DC_WIN_DDA_INCREMENT);
447                 DUMP_REG(DC_WIN_LINE_STRIDE);
448 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
449                 DUMP_REG(DC_WIN_BUF_STRIDE);
450                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
451 #endif
452                 DUMP_REG(DC_WIN_BLEND_NOKEY);
453                 DUMP_REG(DC_WIN_BLEND_1WIN);
454                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
455                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
456                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
457                 DUMP_REG(DC_WINBUF_START_ADDR);
458                 DUMP_REG(DC_WINBUF_START_ADDR_U);
459                 DUMP_REG(DC_WINBUF_START_ADDR_V);
460                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
461                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
462                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
463                 DUMP_REG(DC_WIN_CSC_YOF);
464                 DUMP_REG(DC_WIN_CSC_KYRGB);
465                 DUMP_REG(DC_WIN_CSC_KUR);
466                 DUMP_REG(DC_WIN_CSC_KVR);
467                 DUMP_REG(DC_WIN_CSC_KUG);
468                 DUMP_REG(DC_WIN_CSC_KVG);
469                 DUMP_REG(DC_WIN_CSC_KUB);
470                 DUMP_REG(DC_WIN_CSC_KVB);
471         }
472
473         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
474         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
475         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
476         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
477         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
478         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
479         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
480         DUMP_REG(DC_DISP_M1_CONTROL);
481         DUMP_REG(DC_COM_PM1_CONTROL);
482         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
483         DUMP_REG(DC_DISP_SD_CONTROL);
484
485         tegra_dc_clk_disable(dc->clk);
486         tegra_dc_io_end(dc);
487 }
488
489 #undef DUMP_REG
490
491 #ifdef DEBUG
492 static void dump_regs_print(void *data, const char *str)
493 {
494         struct tegra_dc *dc = data;
495         dev_dbg(&dc->ndev->dev, "%s", str);
496 }
497
498 static void dump_regs(struct tegra_dc *dc)
499 {
500         _dump_regs(dc, dc, dump_regs_print);
501 }
502 #else /* !DEBUG */
503
504 static void dump_regs(struct tegra_dc *dc) {}
505
506 #endif /* DEBUG */
507
508 #ifdef CONFIG_DEBUG_FS
509
510 static void dbg_regs_print(void *data, const char *str)
511 {
512         struct seq_file *s = data;
513
514         seq_printf(s, "%s", str);
515 }
516
517 #undef DUMP_REG
518
519 static int dbg_dc_show(struct seq_file *s, void *unused)
520 {
521         struct tegra_dc *dc = s->private;
522
523         _dump_regs(dc, s, dbg_regs_print);
524
525         return 0;
526 }
527
528
529 static int dbg_dc_open(struct inode *inode, struct file *file)
530 {
531         return single_open(file, dbg_dc_show, inode->i_private);
532 }
533
534 static const struct file_operations regs_fops = {
535         .open           = dbg_dc_open,
536         .read           = seq_read,
537         .llseek         = seq_lseek,
538         .release        = single_release,
539 };
540
541 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
542 {
543         struct tegra_dc *dc = s->private;
544         struct tegra_dc_mode *m;
545
546         mutex_lock(&dc->lock);
547         m = &dc->mode;
548         seq_printf(s,
549                 "pclk: %d\n"
550                 "h_ref_to_sync: %d\n"
551                 "v_ref_to_sync: %d\n"
552                 "h_sync_width: %d\n"
553                 "v_sync_width: %d\n"
554                 "h_back_porch: %d\n"
555                 "v_back_porch: %d\n"
556                 "h_active: %d\n"
557                 "v_active: %d\n"
558                 "h_front_porch: %d\n"
559                 "v_front_porch: %d\n"
560                 "stereo_mode: %d\n",
561                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
562                 m->h_sync_width, m->v_sync_width,
563                 m->h_back_porch, m->v_back_porch,
564                 m->h_active, m->v_active,
565                 m->h_front_porch, m->v_front_porch,
566                 m->stereo_mode);
567         mutex_unlock(&dc->lock);
568         return 0;
569 }
570
571 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
572 {
573         return single_open(file, dbg_dc_mode_show, inode->i_private);
574 }
575
576 static const struct file_operations mode_fops = {
577         .open           = dbg_dc_mode_open,
578         .read           = seq_read,
579         .llseek         = seq_lseek,
580         .release        = single_release,
581 };
582
583 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
584 {
585         struct tegra_dc *dc = s->private;
586
587         mutex_lock(&dc->lock);
588         seq_printf(s,
589                 "underflows: %llu\n"
590                 "underflows_a: %llu\n"
591                 "underflows_b: %llu\n"
592                 "underflows_c: %llu\n",
593                 dc->stats.underflows,
594                 dc->stats.underflows_a,
595                 dc->stats.underflows_b,
596                 dc->stats.underflows_c);
597         mutex_unlock(&dc->lock);
598
599         return 0;
600 }
601
602 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
603 {
604         return single_open(file, dbg_dc_stats_show, inode->i_private);
605 }
606
607 static const struct file_operations stats_fops = {
608         .open           = dbg_dc_stats_open,
609         .read           = seq_read,
610         .llseek         = seq_lseek,
611         .release        = single_release,
612 };
613
614 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
615 {
616         if (dc->debugdir)
617                 debugfs_remove_recursive(dc->debugdir);
618         dc->debugdir = NULL;
619 }
620
621 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
622 {
623         struct dentry *retval;
624
625         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
626         if (!dc->debugdir)
627                 goto remove_out;
628
629         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
630                 &regs_fops);
631         if (!retval)
632                 goto remove_out;
633
634         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
635                 &mode_fops);
636         if (!retval)
637                 goto remove_out;
638
639         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
640                 &stats_fops);
641         if (!retval)
642                 goto remove_out;
643
644         return;
645 remove_out:
646         dev_err(&dc->ndev->dev, "could not create debugfs\n");
647         tegra_dc_remove_debugfs(dc);
648 }
649
650 #else /* !CONFIG_DEBUGFS */
651 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
652 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
653 #endif /* CONFIG_DEBUGFS */
654
655 static int tegra_dc_set(struct tegra_dc *dc, int index)
656 {
657         int ret = 0;
658
659         mutex_lock(&tegra_dc_lock);
660         if (index >= TEGRA_MAX_DC) {
661                 ret = -EINVAL;
662                 goto out;
663         }
664
665         if (dc != NULL && tegra_dcs[index] != NULL) {
666                 ret = -EBUSY;
667                 goto out;
668         }
669
670         tegra_dcs[index] = dc;
671
672 out:
673         mutex_unlock(&tegra_dc_lock);
674
675         return ret;
676 }
677
678 unsigned int tegra_dc_has_multiple_dc(void)
679 {
680         unsigned int idx;
681         unsigned int cnt = 0;
682         struct tegra_dc *dc;
683
684         mutex_lock(&tegra_dc_lock);
685         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
686                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
687         mutex_unlock(&tegra_dc_lock);
688
689         return (cnt > 1);
690 }
691
692 /* get the stride size of a window.
693  * return: stride size in bytes for window win. or 0 if unavailble. */
694 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
695 {
696         u32 stride;
697
698         if (!dc->enabled)
699                 return 0;
700         BUG_ON(win > DC_N_WINDOWS);
701         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
702                 DC_CMD_DISPLAY_WINDOW_HEADER);
703         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
704         return GET_LINE_STRIDE(stride);
705 }
706 EXPORT_SYMBOL(tegra_dc_get_stride);
707
708 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
709 {
710         if (idx < TEGRA_MAX_DC)
711                 return tegra_dcs[idx];
712         else
713                 return NULL;
714 }
715 EXPORT_SYMBOL(tegra_dc_get_dc);
716
717 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
718 {
719         if (win >= dc->n_windows)
720                 return NULL;
721
722         return &dc->windows[win];
723 }
724 EXPORT_SYMBOL(tegra_dc_get_window);
725
726 static int get_topmost_window(u32 *depths, unsigned long *wins, int win_num)
727 {
728         int idx, best = -1;
729
730         for_each_set_bit(idx, wins, win_num) {
731                 if (best == -1 || depths[idx] < depths[best])
732                         best = idx;
733         }
734         clear_bit(best, wins);
735         return best;
736 }
737
738 bool tegra_dc_get_connected(struct tegra_dc *dc)
739 {
740         return dc->connected;
741 }
742 EXPORT_SYMBOL(tegra_dc_get_connected);
743
744 bool tegra_dc_hpd(struct tegra_dc *dc)
745 {
746         int sense;
747         int level;
748
749         level = gpio_get_value(dc->out->hotplug_gpio);
750
751         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
752
753         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
754                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
755 }
756 EXPORT_SYMBOL(tegra_dc_hpd);
757
758 static u32 blend_topwin(u32 flags)
759 {
760         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
761                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
762         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
763                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
764         else
765                 return BLEND(NOKEY, FIX, 0xff, 0xff);
766 }
767
768 static u32 blend_2win(int idx, unsigned long behind_mask,
769                                                 u32* flags, int xy, int win_num)
770 {
771         int other;
772
773         for (other = 0; other < win_num; other++) {
774                 if (other != idx && (xy-- == 0))
775                         break;
776         }
777         if (BIT(other) & behind_mask)
778                 return blend_topwin(flags[idx]);
779         else if (flags[other])
780                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
781         else
782                 return BLEND(NOKEY, FIX, 0x00, 0x00);
783 }
784
785 static u32 blend_3win(int idx, unsigned long behind_mask,
786                                                 u32* flags, int win_num)
787 {
788         unsigned long infront_mask;
789         int first;
790
791         infront_mask = ~(behind_mask | BIT(idx));
792         infront_mask &= (BIT(win_num) - 1);
793         first = ffs(infront_mask) - 1;
794
795         if (!infront_mask)
796                 return blend_topwin(flags[idx]);
797         else if (behind_mask && first != -1 && flags[first])
798                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
799         else
800                 return BLEND(NOKEY, FIX, 0x0, 0x0);
801 }
802
803 static void tegra_dc_set_gen1_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
804 {
805         int win_num = dc->gen1_blend_num;
806         unsigned long mask = BIT(win_num) - 1;
807
808         while (mask) {
809                 int idx = get_topmost_window(blend->z, &mask, win_num);
810
811                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
812                                 DC_CMD_DISPLAY_WINDOW_HEADER);
813                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
814                                 DC_WIN_BLEND_NOKEY);
815                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
816                                 DC_WIN_BLEND_1WIN);
817                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0,
818                                 win_num), DC_WIN_BLEND_2WIN_X);
819                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1,
820                                 win_num), DC_WIN_BLEND_2WIN_Y);
821                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags,
822                                 win_num), DC_WIN_BLEND_3WIN_XY);
823         }
824 }
825
826 static void tegra_dc_set_gen2_blending(struct tegra_dc *dc,
827                                                 struct tegra_dc_blend *blend)
828 {
829         long val;
830         int i = 0;
831
832         for (i = 0; i < DC_N_WINDOWS; i++) {
833                 if (!tegra_dc_feature_is_gen2_blender(dc, i))
834                         continue;
835
836                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
837                                 DC_CMD_DISPLAY_WINDOW_HEADER);
838
839                 if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_COVERAGE) {
840                         tegra_dc_writel(dc,
841                                         WIN_K1(0xff) |
842                                         WIN_K2(0xff) |
843                                         WIN_BLEND_ENABLE,
844                                         DC_WINBUF_BLEND_LAYER_CONTROL);
845
846                         tegra_dc_writel(dc,
847                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC |
848                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC |
849                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
850                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
851                         DC_WINBUF_BLEND_MATCH_SELECT);
852
853                         tegra_dc_writel(dc,
854                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
855                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
856                                         DC_WINBUF_BLEND_ALPHA_1BIT);
857                 } else if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_PREMULT) {
858                         tegra_dc_writel(dc,
859                                         WIN_K1(0xff) |
860                                         WIN_K2(0xff) |
861                                         WIN_BLEND_ENABLE,
862                                         DC_WINBUF_BLEND_LAYER_CONTROL);
863
864                         tegra_dc_writel(dc,
865                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 |
866                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 |
867                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
868                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
869                         DC_WINBUF_BLEND_MATCH_SELECT);
870
871                         tegra_dc_writel(dc,
872                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
873                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
874                                         DC_WINBUF_BLEND_ALPHA_1BIT);
875                 } else {
876                         tegra_dc_writel(dc,
877                                         WIN_BLEND_BYPASS,
878                                         DC_WINBUF_BLEND_LAYER_CONTROL);
879                 }
880         }
881 }
882
883 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
884 {
885         csc->yof   = 0x00f0;
886         csc->kyrgb = 0x012a;
887         csc->kur   = 0x0000;
888         csc->kvr   = 0x0198;
889         csc->kug   = 0x039b;
890         csc->kvg   = 0x032f;
891         csc->kub   = 0x0204;
892         csc->kvb   = 0x0000;
893 }
894
895 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
896 {
897         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
898         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
899         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
900         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
901         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
902         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
903         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
904         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
905 }
906
907 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
908 {
909         mutex_lock(&dc->lock);
910
911         if (!dc->enabled) {
912                 mutex_unlock(&dc->lock);
913                 return -EFAULT;
914         }
915
916         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
917                         DC_CMD_DISPLAY_WINDOW_HEADER);
918
919         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
920
921         mutex_unlock(&dc->lock);
922
923         return 0;
924 }
925 EXPORT_SYMBOL(tegra_dc_update_csc);
926
927 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
928 {
929         int i;
930         for (i = 0; i < 256; i++)
931                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
932 }
933
934 static int tegra_dc_loop_lut(struct tegra_dc *dc,
935                              struct tegra_dc_win *win,
936                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
937 {
938         struct tegra_dc_lut *lut = &win->lut;
939         struct tegra_dc_lut *global_lut = &dc->fb_lut;
940         int i;
941         for (i = 0; i < 256; i++) {
942
943                 u32 r = (u32)lut->r[i];
944                 u32 g = (u32)lut->g[i];
945                 u32 b = (u32)lut->b[i];
946
947                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
948                         r = (u32)global_lut->r[r];
949                         g = (u32)global_lut->g[g];
950                         b = (u32)global_lut->b[b];
951                 }
952
953                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
954                         return 0;
955         }
956         return 1;
957 }
958
959 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
960 {
961         if (rgb != (i | (i<<8) | (i<<16)))
962                 return 0;
963         return 1;
964 }
965
966 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
967 {
968         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
969         return 1;
970 }
971
972 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
973 {
974         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
975
976         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
977
978         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
979                 val |= CP_ENABLE;
980         else
981                 val &= ~CP_ENABLE;
982
983         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
984 }
985
986 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
987 {
988         struct tegra_dc_win *win = &dc->windows[win_idx];
989
990         mutex_lock(&dc->lock);
991
992         if (!dc->enabled) {
993                 mutex_unlock(&dc->lock);
994                 return -EFAULT;
995         }
996
997         if (fbovr > 0)
998                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
999         else if (fbovr == 0)
1000                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
1001
1002         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
1003                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
1004         else
1005                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
1006
1007         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
1008                         DC_CMD_DISPLAY_WINDOW_HEADER);
1009
1010         tegra_dc_set_lut(dc, win);
1011
1012         mutex_unlock(&dc->lock);
1013
1014         tegra_dc_update_windows(&win, 1);
1015
1016         return 0;
1017 }
1018
1019 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
1020 {
1021         if (win_idx > -1)
1022                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
1023
1024         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
1025                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
1026                 if (err)
1027                         return err;
1028         }
1029
1030         return 0;
1031 }
1032 EXPORT_SYMBOL(tegra_dc_update_lut);
1033
1034 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1035 {
1036         unsigned i;
1037         unsigned v0 = 128;
1038         unsigned v1 = 0;
1039         /* linear horizontal and vertical filters */
1040         for (i = 0; i < 16; i++) {
1041                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1042                                 DC_WIN_H_FILTER_P(i));
1043
1044                 tegra_dc_writel(dc, v0,
1045                                 DC_WIN_V_FILTER_P(i));
1046                 v0 -= 8;
1047                 v1 += 8;
1048         }
1049 }
1050
1051 #ifdef CONFIG_TEGRA_DC_CMU
1052 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
1053                                                 struct tegra_dc_cmu *src_cmu)
1054 {
1055         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
1056 }
1057
1058 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1059 {
1060         u32 val;
1061         u32 i;
1062
1063         for (i = 0; i < 256; i++) {
1064                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1065                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1066         }
1067
1068         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1069         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1070         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1071         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1072         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1073         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1074         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1075         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1076         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1077
1078         for (i = 0; i < 960; i++) {
1079                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1080                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1081         }
1082 }
1083
1084 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1085 {
1086         u32 val;
1087         u32 i;
1088         bool flags;
1089
1090         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1091         if (val & CMU_ENABLE)
1092                 flags = true;
1093
1094         val &= ~CMU_ENABLE;
1095         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1096         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1097         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1098
1099         /*TODO: Sync up with frame end */
1100         mdelay(20);
1101
1102         for (i = 0; i < 256; i++) {
1103                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
1104                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
1105                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
1106                 cmu->lut1[i] = LUT1_READ_DATA(val);
1107         }
1108
1109         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
1110         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
1111         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
1112         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
1113         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
1114         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
1115         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
1116         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
1117         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
1118
1119         for (i = 0; i < 960; i++) {
1120                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
1121                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
1122                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
1123                 cmu->lut2[i] = LUT2_READ_DATA(val);
1124         }
1125 }
1126
1127 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
1128 {
1129         mutex_lock(&dc->lock);
1130
1131         if (!dc->enabled) {
1132                 mutex_unlock(&dc->lock);
1133                 return -EFAULT;
1134         }
1135
1136         if (cmu_enable) {
1137                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
1138         } else {
1139                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
1140                 return 0;
1141         }
1142
1143         tegra_dc_set_cmu(dc, &dc->cmu);
1144
1145         mutex_unlock(&dc->lock);
1146
1147         return 0;
1148 }
1149 EXPORT_SYMBOL(tegra_dc_update_cmu);
1150 #else
1151 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
1152 #define tegra_dc_set_cmu(dc, cmu)
1153 #endif
1154
1155 void tegra_dc_host_suspend(struct tegra_dc *dc)
1156 {
1157         tegra_dsi_host_suspend(dc);
1158         tegra_dc_clk_disable(dc);
1159 }
1160
1161 void tegra_dc_host_resume(struct tegra_dc *dc) {
1162         tegra_dc_clk_enable(dc);
1163         tegra_dsi_host_resume(dc);
1164 }
1165
1166 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1167                                   bool v, unsigned Bpp)
1168 {
1169         /*
1170          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1171          *           (post_scaled_size_in_pixels - 1)), MAX)
1172          * Where the value of MAX is as follows:
1173          * For V_DDA_INCREMENT: 15.0 (0xF000)
1174          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1175          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1176          */
1177
1178         fixed20_12 out = dfixed_init(out_int);
1179         u32 dda_inc;
1180         int max;
1181
1182         if (v) {
1183                 max = 15;
1184         } else {
1185                 switch (Bpp) {
1186                 default:
1187                         WARN_ON_ONCE(1);
1188                         /* fallthrough */
1189                 case 4:
1190                         max = 4;
1191                         break;
1192                 case 2:
1193                         max = 8;
1194                         break;
1195                 }
1196         }
1197
1198         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1199         in.full -= dfixed_const(1);
1200
1201         dda_inc = dfixed_div(in, out);
1202
1203         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1204
1205         return dda_inc;
1206 }
1207
1208 static inline u32 compute_initial_dda(fixed20_12 in)
1209 {
1210         return dfixed_frac(in);
1211 }
1212
1213 /* does not support updating windows on multiple dcs in one call */
1214 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1215 {
1216         struct tegra_dc *dc;
1217         unsigned long update_mask = GENERAL_ACT_REQ;
1218         unsigned long val;
1219         bool update_gen1_blend = false;
1220         bool update_gen2_blend = false;
1221         int i;
1222
1223         dc = windows[0]->dc;
1224
1225         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1226                 /* Acquire one_shot_lock to avoid race condition between
1227                  * cancellation of old delayed work and schedule of new
1228                  * delayed work. */
1229                 mutex_lock(&dc->one_shot_lock);
1230                 cancel_delayed_work_sync(&dc->one_shot_work);
1231         }
1232         mutex_lock(&dc->lock);
1233
1234         if (!dc->enabled) {
1235                 mutex_unlock(&dc->lock);
1236                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1237                         mutex_unlock(&dc->one_shot_lock);
1238                 return -EFAULT;
1239         }
1240
1241         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1242                 tegra_dc_host_resume(dc);
1243
1244         if (no_vsync)
1245                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1246         else
1247                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1248
1249         for (i = 0; i < n; i++) {
1250                 struct tegra_dc_win *win = windows[i];
1251                 unsigned h_dda;
1252                 unsigned v_dda;
1253                 fixed20_12 h_offset, v_offset;
1254                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1255                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1256                 bool yuv = tegra_dc_is_yuv(win->fmt);
1257                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1258                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1259                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1260                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1261                 const bool filter_h = win_use_h_filter(dc, win);
1262                 const bool filter_v = win_use_v_filter(dc, win);
1263
1264                 if (win->z != dc->blend.z[win->idx]) {
1265                         dc->blend.z[win->idx] = win->z;
1266                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1267                                 update_gen2_blend = true;
1268                         else
1269                                 update_gen1_blend = true;
1270                 }
1271                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1272                         dc->blend.flags[win->idx]) {
1273                         dc->blend.flags[win->idx] =
1274                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1275                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1276                                 update_gen2_blend = true;
1277                         else
1278                                 update_gen1_blend = true;
1279                 }
1280
1281                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1282                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1283
1284                 if (!no_vsync)
1285                         update_mask |= WIN_A_ACT_REQ << win->idx;
1286
1287                 if (!WIN_IS_ENABLED(win)) {
1288                         dc->windows[i].dirty = 1;
1289                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1290                         continue;
1291                 }
1292
1293                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1294                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1295
1296                 tegra_dc_writel(dc,
1297                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1298                                 DC_WIN_POSITION);
1299                 tegra_dc_writel(dc,
1300                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1301                                 DC_WIN_SIZE);
1302
1303                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
1304                         tegra_dc_writel(dc,
1305                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1306                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1307                                         DC_WIN_PRESCALED_SIZE);
1308
1309                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1310                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1311                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1312                                         DC_WIN_DDA_INCREMENT);
1313                         h_dda = compute_initial_dda(win->x);
1314                         v_dda = compute_initial_dda(win->y);
1315                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1316                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1317                 }
1318
1319 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1320                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1321                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1322 #endif
1323                 tegra_dc_writel(dc,
1324                                 (unsigned long)win->phys_addr,
1325                                 DC_WINBUF_START_ADDR);
1326
1327                 if (!yuvp) {
1328                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1329                 } else {
1330                         tegra_dc_writel(dc,
1331                                         (unsigned long)win->phys_addr_u,
1332                                         DC_WINBUF_START_ADDR_U);
1333                         tegra_dc_writel(dc,
1334                                         (unsigned long)win->phys_addr_v,
1335                                         DC_WINBUF_START_ADDR_V);
1336                         tegra_dc_writel(dc,
1337                                         LINE_STRIDE(win->stride) |
1338                                         UV_LINE_STRIDE(win->stride_uv),
1339                                         DC_WIN_LINE_STRIDE);
1340                 }
1341
1342                 h_offset = win->x;
1343                 if (invert_h) {
1344                         h_offset.full += win->w.full - dfixed_const(1);
1345                 }
1346
1347                 v_offset = win->y;
1348                 if (invert_v) {
1349                         v_offset.full += win->h.full - dfixed_const(1);
1350                 }
1351
1352                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1353                                 DC_WINBUF_ADDR_H_OFFSET);
1354                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1355                                 DC_WINBUF_ADDR_V_OFFSET);
1356
1357                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1358                         if (WIN_IS_TILED(win))
1359                                 tegra_dc_writel(dc,
1360                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1361                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1362                                                 DC_WIN_BUFFER_ADDR_MODE);
1363                         else
1364                                 tegra_dc_writel(dc,
1365                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1366                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1367                                                 DC_WIN_BUFFER_ADDR_MODE);
1368                 }
1369
1370                 val = WIN_ENABLE;
1371                 if (yuv)
1372                         val |= CSC_ENABLE;
1373                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1374                         val |= COLOR_EXPAND;
1375
1376                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1377                         val |= CP_ENABLE;
1378
1379                 if (filter_h)
1380                         val |= H_FILTER_ENABLE;
1381                 if (filter_v)
1382                         val |= V_FILTER_ENABLE;
1383
1384                 if (invert_h)
1385                         val |= H_DIRECTION_DECREMENT;
1386                 if (invert_v)
1387                         val |= V_DIRECTION_DECREMENT;
1388
1389                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1390
1391 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1392                 if (win->global_alpha == 255)
1393                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1394                 else
1395                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1396                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1397 #endif
1398
1399                 win->dirty = no_vsync ? 0 : 1;
1400
1401                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1402                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1403                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1404                         __func__, win->idx, win->z,
1405                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1406                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1407                         win->out_x, win->out_y, win->out_w, win->out_h,
1408                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1409                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1410                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1411                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1412         }
1413
1414         if (update_gen1_blend || update_gen2_blend) {
1415                 if (update_gen1_blend)
1416                         tegra_dc_set_gen1_blending(dc, &dc->blend);
1417                 if (update_gen2_blend)
1418                         tegra_dc_set_gen2_blending(dc, &dc->blend);
1419                 for (i = 0; i < DC_N_WINDOWS; i++) {
1420                         if (!no_vsync)
1421                                 dc->windows[i].dirty = 1;
1422                         update_mask |= WIN_A_ACT_REQ << i;
1423                 }
1424         }
1425
1426         tegra_dc_set_dynamic_emc(windows, n);
1427
1428         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1429
1430         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1431         if (!no_vsync) {
1432                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1433                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1434         } else {
1435                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1436                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1437         }
1438
1439         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1440                 schedule_delayed_work(&dc->one_shot_work,
1441                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1442
1443         /* update EMC clock if calculated bandwidth has changed */
1444         tegra_dc_program_bandwidth(dc);
1445
1446         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1447                 update_mask |= NC_HOST_TRIG;
1448
1449         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1450         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1451
1452         mutex_unlock(&dc->lock);
1453         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1454                 mutex_unlock(&dc->one_shot_lock);
1455
1456         return 0;
1457 }
1458 EXPORT_SYMBOL(tegra_dc_update_windows);
1459
1460 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1461 {
1462         return dc->syncpt[i].id;
1463 }
1464 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1465
1466 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1467 {
1468         u32 max;
1469
1470         mutex_lock(&dc->lock);
1471         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1472                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1473         dc->syncpt[i].max = max;
1474         mutex_unlock(&dc->lock);
1475
1476         return max;
1477 }
1478
1479 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1480 {
1481         mutex_lock(&dc->lock);
1482         if ( dc->enabled )
1483                 while (dc->syncpt[i].min < val) {
1484                         dc->syncpt[i].min++;
1485                         nvhost_syncpt_cpu_incr(
1486                                         &nvhost_get_host(dc->ndev)->syncpt,
1487                                         dc->syncpt[i].id);
1488                 }
1489         mutex_unlock(&dc->lock);
1490 }
1491
1492 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1493                                              int n)
1494 {
1495         int i;
1496
1497         for (i = 0; i < n; i++) {
1498                 if (windows[i]->dirty)
1499                         return false;
1500         }
1501
1502         return true;
1503 }
1504
1505 /* does not support syncing windows on multiple dcs in one call */
1506 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1507 {
1508         int ret;
1509         if (n < 1 || n > DC_N_WINDOWS)
1510                 return -EINVAL;
1511
1512         if (!windows[0]->dc->enabled)
1513                 return -EFAULT;
1514
1515         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1516                         windows[0]->dc->ndev->name);
1517         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1518                                          tegra_dc_windows_are_clean(windows, n),
1519                                          HZ);
1520         trace_printk("%s:After wait_event_interruptible_timeout\n",
1521                         windows[0]->dc->ndev->name);
1522         return ret;
1523 }
1524 EXPORT_SYMBOL(tegra_dc_sync_windows);
1525
1526 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1527 {
1528 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1529         return 27000000;
1530 #else
1531         return clk_get_rate(dc->clk);
1532 #endif
1533 }
1534
1535 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1536 {
1537         unsigned long rate;
1538         unsigned long div;
1539
1540         rate = tegra_dc_clk_get_rate(dc);
1541
1542         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1543
1544         if (div < 2)
1545                 return 0;
1546
1547         return rate * 2 / div;
1548 }
1549
1550 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1551 {
1552         unsigned long rate;
1553         unsigned long div;
1554
1555         rate = clk_get_rate(parent);
1556
1557         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1558
1559         if (div < 2)
1560                 return 0;
1561
1562         return rate * 2 / div;
1563 }
1564
1565 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1566 {
1567         int pclk;
1568
1569         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1570                 unsigned long rate;
1571                 struct clk *parent_clk =
1572                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1573
1574                 if (dc->out->parent_clk_backup &&
1575                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1576                         rate = tegra_dc_pclk_predict_rate(
1577                                 parent_clk, dc->mode.pclk);
1578                         /* use pll_d as last resort */
1579                         if (rate < (dc->mode.pclk / 100 * 99) ||
1580                             rate > (dc->mode.pclk / 100 * 109))
1581                                 parent_clk = clk_get_sys(
1582                                         NULL, dc->out->parent_clk_backup);
1583                 }
1584
1585                 if (clk_get_parent(clk) != parent_clk)
1586                         clk_set_parent(clk, parent_clk);
1587
1588                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1589                         struct clk *base_clk = clk_get_parent(parent_clk);
1590
1591                         /* Assuming either pll_d or pll_d2 is used */
1592                         rate = dc->mode.pclk * 2;
1593
1594                         if (rate != clk_get_rate(base_clk))
1595                                 clk_set_rate(base_clk, rate);
1596                 }
1597         }
1598
1599         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1600                 unsigned long rate;
1601                 struct clk *parent_clk =
1602                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1603                 struct clk *base_clk = clk_get_parent(parent_clk);
1604
1605                 /*
1606                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1607                  * The required rate needs to be setup at 4x multiplier,
1608                  * as out0 is 1/2 of the actual PLL output.
1609                  */
1610
1611                 rate = dc->mode.pclk * 4;
1612                 if (rate != clk_get_rate(base_clk))
1613                         clk_set_rate(base_clk, rate);
1614
1615                 if (clk_get_parent(clk) != parent_clk)
1616                         clk_set_parent(clk, parent_clk);
1617         }
1618
1619         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1620                 unsigned long rate;
1621                 struct clk *parent_clk;
1622                 struct clk *base_clk;
1623
1624                 if (clk == dc->clk) {
1625                         parent_clk = clk_get_sys(NULL,
1626                                         dc->out->parent_clk ? : "pll_d_out0");
1627                         base_clk = clk_get_parent(parent_clk);
1628                         tegra_clk_cfg_ex(base_clk,
1629                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1630                 } else {
1631                         if (dc->pdata->default_out->dsi->dsi_instance) {
1632                                 parent_clk = clk_get_sys(NULL,
1633                                         dc->out->parent_clk ? : "pll_d2_out0");
1634                                 base_clk = clk_get_parent(parent_clk);
1635                                 tegra_clk_cfg_ex(base_clk,
1636                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1637                         } else {
1638                                 parent_clk = clk_get_sys(NULL,
1639                                         dc->out->parent_clk ? : "pll_d_out0");
1640                                 base_clk = clk_get_parent(parent_clk);
1641                                 tegra_clk_cfg_ex(base_clk,
1642                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1643                         }
1644                 }
1645
1646                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1647                 if (rate != clk_get_rate(base_clk))
1648                         clk_set_rate(base_clk, rate);
1649
1650                 if (clk_get_parent(clk) != parent_clk)
1651                         clk_set_parent(clk, parent_clk);
1652         }
1653
1654         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1655         tegra_dvfs_set_rate(clk, pclk);
1656 }
1657
1658 /* return non-zero if constraint is violated */
1659 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1660 {
1661         long a, b;
1662
1663         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1664         a = 0;
1665
1666         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1667         b = mode->h_front_porch - 1;
1668
1669         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1670         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1671                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1672         /* check Constraint 1 and 6 */
1673         if (a > b)
1674                 return 1;
1675
1676         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1677         if (mode->h_sync_width < 1)
1678                 return 4;
1679
1680         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1681         if (mode->h_active < 16)
1682                 return 7;
1683
1684         if (href) {
1685                 if (b > a && a % 2)
1686                         *href = a + 1; /* use smallest even value */
1687                 else
1688                         *href = a; /* even or only possible value */
1689         }
1690
1691         return 0;
1692 }
1693
1694 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1695 {
1696         long a;
1697         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1698
1699         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1700         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1701                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1702
1703         /* Constraint 6 */
1704         if (mode->v_front_porch < a + 1)
1705                 a = mode->v_front_porch - 1;
1706
1707         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1708         if (mode->v_sync_width < 1)
1709                 return 4;
1710
1711         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1712         if (mode->v_active < 16)
1713                 return 7;
1714
1715         if (vref)
1716                 *vref = a;
1717         return 0;
1718 }
1719
1720 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1721 {
1722         int ret;
1723         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1724         if (ret)
1725                 return ret;
1726         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1727         if (ret)
1728                 return ret;
1729
1730         return 0;
1731 }
1732
1733 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1734 {
1735         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1736         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1737                 return false;
1738
1739         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1740         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1741                 return false;
1742
1743         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1744          * (vertical blank). */
1745         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1746                 return false;
1747
1748         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1749         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1750                 return false;
1751
1752         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1753         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1754                 return false;
1755
1756         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1757          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1758         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1759                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1760                 return false;
1761
1762         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1763         if (mode->h_active < 16 || mode->v_active < 16)
1764                 return false;
1765
1766         return true;
1767 }
1768
1769 #ifdef DEBUG
1770 /* return in 1000ths of a Hertz */
1771 static int calc_refresh(const struct tegra_dc_mode *m)
1772 {
1773         long h_total, v_total, refresh;
1774         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1775                 m->h_sync_width;
1776         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1777                 m->v_sync_width;
1778         refresh = m->pclk / h_total;
1779         refresh *= 1000;
1780         refresh /= v_total;
1781         return refresh;
1782 }
1783
1784 static void print_mode(struct tegra_dc *dc,
1785                         const struct tegra_dc_mode *mode, const char *note)
1786 {
1787         if (mode) {
1788                 int refresh = calc_refresh(dc, mode);
1789                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1790                         note ? note : "",
1791                         mode->h_active, mode->v_active,
1792                         refresh / 1000, refresh % 1000,
1793                         mode->pclk);
1794         }
1795 }
1796 #else /* !DEBUG */
1797 static inline void print_mode(struct tegra_dc *dc,
1798                         const struct tegra_dc_mode *mode, const char *note) { }
1799 #endif /* DEBUG */
1800
1801 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1802 {
1803         u32 val;
1804
1805         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1806         val |= int_val;
1807         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1808 }
1809
1810 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1811 {
1812         u32 val;
1813
1814         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1815         val &= ~int_val;
1816         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1817 }
1818
1819 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1820 {
1821         unsigned long val;
1822         unsigned long rate;
1823         unsigned long div;
1824         unsigned long pclk;
1825
1826         print_mode(dc, mode, __func__);
1827
1828         /* use default EMC rate when switching modes */
1829         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1830         tegra_dc_program_bandwidth(dc);
1831
1832         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1833         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1834                         DC_DISP_REF_TO_SYNC);
1835         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1836                         DC_DISP_SYNC_WIDTH);
1837         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1838                         DC_DISP_BACK_PORCH);
1839         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1840                         DC_DISP_DISP_ACTIVE);
1841         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1842                         DC_DISP_FRONT_PORCH);
1843
1844         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1845                         DC_DISP_DATA_ENABLE_OPTIONS);
1846
1847         /* TODO: MIPI/CRT/HDMI clock cals */
1848
1849         val = DISP_DATA_FORMAT_DF1P1C;
1850
1851         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1852                 val |= DISP_DATA_ALIGNMENT_MSB;
1853         else
1854                 val |= DISP_DATA_ALIGNMENT_LSB;
1855
1856         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1857                 val |= DISP_DATA_ORDER_RED_BLUE;
1858         else
1859                 val |= DISP_DATA_ORDER_BLUE_RED;
1860
1861         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1862
1863         rate = tegra_dc_clk_get_rate(dc);
1864
1865         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1866         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1867         if (pclk < (mode->pclk / 100 * 99) ||
1868             pclk > (mode->pclk / 100 * 109)) {
1869                 dev_err(&dc->ndev->dev,
1870                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1871                         rate, mode->pclk,
1872                         pclk, (mode->pclk / 100 * 99),
1873                         (mode->pclk / 100 * 109));
1874                 return -EINVAL;
1875         }
1876
1877         div = (rate * 2 / pclk) - 2;
1878         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1879
1880         tegra_dc_writel(dc, 0x00010001,
1881                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1882         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1883                         DC_DISP_DISP_CLOCK_CONTROL);
1884
1885 #ifdef CONFIG_SWITCH
1886         switch_set_state(&dc->modeset_switch,
1887                          (mode->h_active << 16) | mode->v_active);
1888 #endif
1889
1890         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1891         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1892
1893         print_mode_info(dc, dc->mode);
1894         return 0;
1895 }
1896
1897
1898 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1899 {
1900         memcpy(&dc->mode, mode, sizeof(dc->mode));
1901
1902         print_mode(dc, mode, __func__);
1903
1904         return 0;
1905 }
1906 EXPORT_SYMBOL(tegra_dc_set_mode);
1907
1908 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1909                 const struct fb_videomode *fbmode, bool stereo_mode)
1910 {
1911         struct tegra_dc_mode mode;
1912
1913         if (!fbmode->pixclock)
1914                 return -EINVAL;
1915
1916         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1917         mode.h_sync_width = fbmode->hsync_len;
1918         mode.v_sync_width = fbmode->vsync_len;
1919         mode.h_back_porch = fbmode->left_margin;
1920         mode.v_back_porch = fbmode->upper_margin;
1921         mode.h_active = fbmode->xres;
1922         mode.v_active = fbmode->yres;
1923         mode.h_front_porch = fbmode->right_margin;
1924         mode.v_front_porch = fbmode->lower_margin;
1925         mode.stereo_mode = stereo_mode;
1926         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1927                 /* HDMI controller requires h_ref=1, v_ref=1 */
1928                 mode.h_ref_to_sync = 1;
1929                 mode.v_ref_to_sync = 1;
1930         } else {
1931                 calc_ref_to_sync(&mode);
1932         }
1933         if (!check_ref_to_sync(&mode)) {
1934                 dev_err(&dc->ndev->dev,
1935                                 "Display timing doesn't meet restrictions.\n");
1936                 return -EINVAL;
1937         }
1938         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1939                 mode.h_active, mode.v_active, mode.pclk,
1940                 mode.h_ref_to_sync, mode.v_ref_to_sync
1941         );
1942
1943 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1944         /* Double the pixel clock and update v_active only for frame packed mode */
1945         if (mode.stereo_mode) {
1946                 mode.pclk *= 2;
1947                 /* total v_active = yres*2 + activespace */
1948                 mode.v_active = fbmode->yres*2 +
1949                                 fbmode->vsync_len +
1950                                 fbmode->upper_margin +
1951                                 fbmode->lower_margin;
1952         }
1953 #endif
1954
1955         mode.flags = 0;
1956
1957         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1958                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1959
1960         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1961                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1962
1963         return tegra_dc_set_mode(dc, &mode);
1964 }
1965 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1966
1967 void
1968 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1969 {
1970         unsigned int ctrl;
1971         unsigned long out_sel;
1972         unsigned long cmd_state;
1973
1974         mutex_lock(&dc->lock);
1975         if (!dc->enabled) {
1976                 mutex_unlock(&dc->lock);
1977                 return;
1978         }
1979
1980         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1981                 tegra_dc_host_resume(dc);
1982
1983         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1984                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1985                 cfg->clk_select);
1986
1987         /* The new value should be effected immediately */
1988         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1989         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1990
1991         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1992                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1993         else
1994                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1995
1996         switch (cfg->which_pwm) {
1997         case TEGRA_PWM_PM0:
1998                 /* Select the LM0 on PM0 */
1999                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2000                 out_sel &= ~(7 << 0);
2001                 out_sel |= (3 << 0);
2002                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2003                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2004                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2005                 break;
2006         case TEGRA_PWM_PM1:
2007                 /* Select the LM1 on PM1 */
2008                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2009                 out_sel &= ~(7 << 4);
2010                 out_sel |= (3 << 4);
2011                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2012                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2013                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2014                 break;
2015         default:
2016                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2017                 break;
2018         }
2019         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2020         mutex_unlock(&dc->lock);
2021 }
2022 EXPORT_SYMBOL(tegra_dc_config_pwm);
2023
2024 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2025                                 const struct tegra_dc_out_pin *pins,
2026                                 const unsigned int n_pins)
2027 {
2028         unsigned int i;
2029
2030         int name;
2031         int pol;
2032
2033         u32 pol1, pol3;
2034
2035         u32 set1, unset1;
2036         u32 set3, unset3;
2037
2038         set1 = set3 = unset1 = unset3 = 0;
2039
2040         for (i = 0; i < n_pins; i++) {
2041                 name = (pins + i)->name;
2042                 pol  = (pins + i)->pol;
2043
2044                 /* set polarity by name */
2045                 switch (name) {
2046                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2047                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2048                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2049                         else
2050                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2051                         break;
2052                 case TEGRA_DC_OUT_PIN_H_SYNC:
2053                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2054                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2055                         else
2056                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2057                         break;
2058                 case TEGRA_DC_OUT_PIN_V_SYNC:
2059                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2060                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2061                         else
2062                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2063                         break;
2064                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2065                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2066                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2067                         else
2068                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2069                         break;
2070                 default:
2071                         printk("Invalid argument in function %s\n",
2072                                __FUNCTION__);
2073                         break;
2074                 }
2075         }
2076
2077         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2078         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2079
2080         pol1 |= set1;
2081         pol1 &= ~unset1;
2082
2083         pol3 |= set3;
2084         pol3 &= ~unset3;
2085
2086         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2087         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2088 }
2089
2090 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2091 {
2092         dc->out = out;
2093
2094         if (out->n_modes > 0)
2095                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2096
2097         switch (out->type) {
2098         case TEGRA_DC_OUT_RGB:
2099                 dc->out_ops = &tegra_dc_rgb_ops;
2100                 break;
2101
2102         case TEGRA_DC_OUT_HDMI:
2103                 dc->out_ops = &tegra_dc_hdmi_ops;
2104                 break;
2105
2106         case TEGRA_DC_OUT_DSI:
2107                 dc->out_ops = &tegra_dc_dsi_ops;
2108                 break;
2109
2110         default:
2111                 dc->out_ops = NULL;
2112                 break;
2113         }
2114
2115         if (dc->out_ops && dc->out_ops->init)
2116                 dc->out_ops->init(dc);
2117
2118 }
2119
2120 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2121 {
2122         if (dc->out)
2123                 return dc->out->height;
2124         else
2125                 return 0;
2126 }
2127 EXPORT_SYMBOL(tegra_dc_get_out_height);
2128
2129 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2130 {
2131         if (dc->out)
2132                 return dc->out->width;
2133         else
2134                 return 0;
2135 }
2136 EXPORT_SYMBOL(tegra_dc_get_out_width);
2137
2138 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2139 {
2140         if (dc->out && dc->out->max_pixclock)
2141                 return dc->out->max_pixclock;
2142         else
2143                 return 0;
2144 }
2145 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2146
2147 void tegra_dc_enable_crc(struct tegra_dc *dc)
2148 {
2149         u32 val;
2150         tegra_dc_io_start(dc);
2151
2152         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2153                 CRC_ENABLE_ENABLE;
2154         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2155         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2156         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2157 }
2158
2159 void tegra_dc_disable_crc(struct tegra_dc *dc)
2160 {
2161         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2162         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2163         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2164
2165         tegra_dc_io_end(dc);
2166 }
2167
2168 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2169 {
2170         int crc = 0;
2171
2172         if (!dc) {
2173                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2174                 goto crc_error;
2175         }
2176
2177 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2178         /* TODO: Replace mdelay with code to sync VBlANK, since
2179          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2180         mdelay(TEGRA_CRC_LATCHED_DELAY);
2181 #endif
2182
2183         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2184 crc_error:
2185         return crc;
2186 }
2187
2188 static void tegra_dc_vblank(struct work_struct *work)
2189 {
2190         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2191         bool nvsd_updated = false;
2192
2193         mutex_lock(&dc->lock);
2194
2195         /* use the new frame's bandwidth setting instead of max(current, new),
2196          * skip this if we're using tegra_dc_one_shot_worker() */
2197         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2198                 tegra_dc_program_bandwidth(dc);
2199
2200         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2201         if (!tegra_dc_windows_are_dirty(dc))
2202                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2203
2204         /* Update the SD brightness */
2205         if (dc->enabled && dc->out->sd_settings) {
2206                 nvsd_updated = nvsd_update_brightness(dc);
2207                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2208                  * V_BLANK_NVSD bit of vblank ref-count. */
2209                 if (nvsd_updated) {
2210                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2211                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2212                 } else {
2213                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2214                 }
2215         }
2216
2217         /* Mask vblank interrupt if ref-count is zero. */
2218         if (!dc->vblank_ref_count)
2219                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2220
2221         mutex_unlock(&dc->lock);
2222
2223         /* Do the actual brightness update outside of the mutex */
2224         if (nvsd_updated && dc->out->sd_settings &&
2225             dc->out->sd_settings->bl_device) {
2226
2227                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2228                 struct backlight_device *bl = platform_get_drvdata(pdev);
2229                 if (bl)
2230                         backlight_update_status(bl);
2231         }
2232 }
2233
2234 static void tegra_dc_one_shot_worker(struct work_struct *work)
2235 {
2236         struct tegra_dc *dc = container_of(
2237                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2238         mutex_lock(&dc->lock);
2239
2240         /* memory client has gone idle */
2241         tegra_dc_clear_bandwidth(dc);
2242
2243         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2244                 tegra_dc_host_suspend(dc);
2245
2246         mutex_unlock(&dc->lock);
2247 }
2248
2249 /* return an arbitrarily large number if count overflow occurs.
2250  * make it a nice base-10 number to show up in stats output */
2251 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2252 {
2253         unsigned count = tegra_dc_readl(dc, reg);
2254         tegra_dc_writel(dc, 0, reg);
2255         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2256 }
2257
2258 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2259 {
2260         u32 val;
2261         int i;
2262
2263         dc->stats.underflows++;
2264         if (dc->underflow_mask & WIN_A_UF_INT) {
2265                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2266                         DC_WINBUF_AD_UFLOW_STATUS);
2267                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2268         }
2269         if (dc->underflow_mask & WIN_B_UF_INT) {
2270                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2271                         DC_WINBUF_BD_UFLOW_STATUS);
2272                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2273         }
2274         if (dc->underflow_mask & WIN_C_UF_INT) {
2275                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2276                         DC_WINBUF_CD_UFLOW_STATUS);
2277                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2278         }
2279
2280         /* Check for any underflow reset conditions */
2281         for (i = 0; i < DC_N_WINDOWS; i++) {
2282                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2283                         dc->windows[i].underflows++;
2284
2285 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2286                         if (dc->windows[i].underflows > 4) {
2287                                 schedule_work(&dc->reset_work);
2288                                 /* reset counter */
2289                                 dc->windows[i].underflows = 0;
2290                                 trace_printk("%s:Reset work scheduled for "
2291                                                 "window %c\n",
2292                                                 dc->ndev->name, (65 + i));
2293                         }
2294 #endif
2295 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2296                         if (dc->windows[i].underflows > 4) {
2297                                 printk("%s:dc in underflow state."
2298                                         " enable UF_LINE_FLUSH to clear up\n",
2299                                         __func__);
2300                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2301                                                 DC_DISP_DISP_MISC_CONTROL);
2302                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2303                                                 DC_CMD_STATE_CONTROL);
2304                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2305                                                 DC_CMD_STATE_CONTROL);
2306
2307                                 tegra_dc_writel(dc, 0,
2308                                                 DC_DISP_DISP_MISC_CONTROL);
2309                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2310                                                 DC_CMD_STATE_CONTROL);
2311                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2312                                                 DC_CMD_STATE_CONTROL);
2313                         }
2314 #endif
2315                 } else {
2316                         dc->windows[i].underflows = 0;
2317                 }
2318         }
2319
2320         /* Clear the underflow mask now that we've checked it. */
2321         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2322         dc->underflow_mask = 0;
2323         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2324         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2325         print_underflow_info(dc);
2326 }
2327
2328 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2329 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2330 {
2331 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2332         u32 val;
2333
2334         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2335         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2336             return true;
2337 #endif
2338         return false;
2339 }
2340
2341 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2342 {
2343         u32 val, i;
2344         u32 completed = 0;
2345         u32 dirty = 0;
2346
2347         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2348         for (i = 0; i < DC_N_WINDOWS; i++) {
2349                 if (!(val & (WIN_A_ACT_REQ << i))) {
2350                         dc->windows[i].dirty = 0;
2351                         completed = 1;
2352                 } else {
2353                         dirty = 1;
2354                 }
2355         }
2356
2357         if (!dirty) {
2358                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2359                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2360         }
2361
2362         if (completed)
2363                 wake_up(&dc->wq);
2364 }
2365
2366 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2367 {
2368         if (status & V_BLANK_INT) {
2369                 /* Sync up windows. */
2370                 tegra_dc_trigger_windows(dc);
2371
2372                 /* Schedule any additional bottom-half vblank actvities. */
2373                 schedule_work(&dc->vblank_work);
2374         }
2375
2376         if (status & FRAME_END_INT) {
2377                 /* Mark the frame_end as complete. */
2378                 if (!completion_done(&dc->frame_end_complete))
2379                         complete(&dc->frame_end_complete);
2380         }
2381 }
2382
2383 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2384 {
2385         /* Schedule any additional bottom-half vblank actvities. */
2386         if (status & V_BLANK_INT)
2387                 schedule_work(&dc->vblank_work);
2388
2389         if (status & FRAME_END_INT) {
2390                 /* Mark the frame_end as complete. */
2391                 if (!completion_done(&dc->frame_end_complete))
2392                         complete(&dc->frame_end_complete);
2393
2394                 tegra_dc_trigger_windows(dc);
2395         }
2396 }
2397 #endif
2398
2399 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2400 {
2401 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2402         struct tegra_dc *dc = ptr;
2403         unsigned long status;
2404         unsigned long underflow_mask;
2405         u32 val;
2406
2407         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2408                 WARN(1, "IRQ when DC not powered!\n");
2409                 tegra_dc_io_start(dc);
2410                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2411                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2412                 tegra_dc_io_end(dc);
2413                 return IRQ_HANDLED;
2414         }
2415
2416         /* clear all status flags except underflow, save those for the worker */
2417         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2418         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2419         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2420         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2421
2422         /*
2423          * Overlays can get thier internal state corrupted during and underflow
2424          * condition.  The only way to fix this state is to reset the DC.
2425          * if we get 4 consecutive frames with underflows, assume we're
2426          * hosed and reset.
2427          */
2428         underflow_mask = status & ALL_UF_INT;
2429
2430         /* Check underflow */
2431         if (underflow_mask) {
2432                 dc->underflow_mask |= underflow_mask;
2433                 schedule_delayed_work(&dc->underflow_work,
2434                         msecs_to_jiffies(1));
2435         }
2436
2437         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2438                 tegra_dc_one_shot_irq(dc, status);
2439         else
2440                 tegra_dc_continuous_irq(dc, status);
2441
2442         return IRQ_HANDLED;
2443 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2444         return IRQ_NONE;
2445 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2446 }
2447
2448 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2449 {
2450         u32 color_control;
2451
2452         switch (dc->out->depth) {
2453         case 3:
2454                 color_control = BASE_COLOR_SIZE111;
2455                 break;
2456
2457         case 6:
2458                 color_control = BASE_COLOR_SIZE222;
2459                 break;
2460
2461         case 8:
2462                 color_control = BASE_COLOR_SIZE332;
2463                 break;
2464
2465         case 9:
2466                 color_control = BASE_COLOR_SIZE333;
2467                 break;
2468
2469         case 12:
2470                 color_control = BASE_COLOR_SIZE444;
2471                 break;
2472
2473         case 15:
2474                 color_control = BASE_COLOR_SIZE555;
2475                 break;
2476
2477         case 16:
2478                 color_control = BASE_COLOR_SIZE565;
2479                 break;
2480
2481         case 18:
2482                 color_control = BASE_COLOR_SIZE666;
2483                 break;
2484
2485         default:
2486                 color_control = BASE_COLOR_SIZE888;
2487                 break;
2488         }
2489
2490         switch (dc->out->dither) {
2491         case TEGRA_DC_DISABLE_DITHER:
2492                 color_control |= DITHER_CONTROL_DISABLE;
2493                 break;
2494         case TEGRA_DC_ORDERED_DITHER:
2495                 color_control |= DITHER_CONTROL_ORDERED;
2496                 break;
2497         case TEGRA_DC_ERRDIFF_DITHER:
2498                 /* The line buffer for error-diffusion dither is limited
2499                  * to 1280 pixels per line. This limits the maximum
2500                  * horizontal active area size to 1280 pixels when error
2501                  * diffusion is enabled.
2502                  */
2503                 BUG_ON(dc->mode.h_active > 1280);
2504                 color_control |= DITHER_CONTROL_ERRDIFF;
2505                 break;
2506         }
2507
2508 #ifdef CONFIG_TEGRA_DC_CMU
2509         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
2510                 color_control |= CMU_ENABLE;
2511 #endif
2512
2513         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2514 }
2515
2516 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2517 {
2518         u32 syncpt_id;
2519
2520         switch (dc->ndev->id) {
2521         case 0:
2522                 switch (idx) {
2523                 case 0:
2524                         syncpt_id = NVSYNCPT_DISP0_A;
2525                         break;
2526                 case 1:
2527                         syncpt_id = NVSYNCPT_DISP0_B;
2528                         break;
2529                 case 2:
2530                         syncpt_id = NVSYNCPT_DISP0_C;
2531                         break;
2532                 default:
2533                         BUG();
2534                         break;
2535                 }
2536                 break;
2537         case 1:
2538                 switch (idx) {
2539                 case 0:
2540                         syncpt_id = NVSYNCPT_DISP1_A;
2541                         break;
2542                 case 1:
2543                         syncpt_id = NVSYNCPT_DISP1_B;
2544                         break;
2545                 case 2:
2546                         syncpt_id = NVSYNCPT_DISP1_C;
2547                         break;
2548                 default:
2549                         BUG();
2550                         break;
2551                 }
2552                 break;
2553         default:
2554                 BUG();
2555                 break;
2556         }
2557
2558         return syncpt_id;
2559 }
2560
2561 static int tegra_dc_init(struct tegra_dc *dc)
2562 {
2563         int i;
2564
2565         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2566         if (dc->ndev->id == 0) {
2567                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2568                                       TEGRA_MC_PRIO_MED);
2569                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2570                                       TEGRA_MC_PRIO_MED);
2571                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2572                                       TEGRA_MC_PRIO_MED);
2573                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2574                                       TEGRA_MC_PRIO_MED);
2575                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2576                                       TEGRA_MC_PRIO_HIGH);
2577         } else if (dc->ndev->id == 1) {
2578                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2579                                       TEGRA_MC_PRIO_MED);
2580                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2581                                       TEGRA_MC_PRIO_MED);
2582                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2583                                       TEGRA_MC_PRIO_MED);
2584                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2585                                       TEGRA_MC_PRIO_MED);
2586                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2587                                       TEGRA_MC_PRIO_HIGH);
2588         }
2589         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2590                         DC_CMD_CONT_SYNCPT_VSYNC);
2591         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2592         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2593         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2594         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2595 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2596         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2597 #endif
2598         /* enable interrupts for vblank, frame_end and underflows */
2599         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2600                 DC_CMD_INT_ENABLE);
2601         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2602
2603         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2604
2605         tegra_dc_set_color_control(dc);
2606         for (i = 0; i < DC_N_WINDOWS; i++) {
2607                 struct tegra_dc_win *win = &dc->windows[i];
2608                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2609                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2610                 tegra_dc_set_csc(dc, &win->csc);
2611                 tegra_dc_set_lut(dc, win);
2612                 tegra_dc_set_scaling_filter(dc);
2613         }
2614
2615         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
2616         tegra_dc_set_cmu(dc, &dc->cmu);
2617
2618         for (i = 0; i < dc->n_windows; i++) {
2619                 u32 syncpt = get_syncpt(dc, i);
2620
2621                 dc->syncpt[i].id = syncpt;
2622
2623                 dc->syncpt[i].min = dc->syncpt[i].max =
2624                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2625                                         syncpt);
2626         }
2627
2628         print_mode(dc, &dc->mode, __func__);
2629
2630         if (dc->mode.pclk)
2631                 if (tegra_dc_program_mode(dc, &dc->mode))
2632                         return -EINVAL;
2633
2634         /* Initialize SD AFTER the modeset.
2635            nvsd_init handles the sd_settings = NULL case. */
2636         nvsd_init(dc, dc->out->sd_settings);
2637
2638         return 0;
2639 }
2640
2641 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2642 {
2643         int failed_init = 0;
2644
2645         if (dc->out->enable)
2646                 dc->out->enable();
2647
2648         tegra_dc_setup_clk(dc, dc->clk);
2649         tegra_dc_clk_enable(dc);
2650
2651         /* do not accept interrupts during initialization */
2652         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2653         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2654
2655         enable_irq(dc->irq);
2656
2657         failed_init = tegra_dc_init(dc);
2658         if (failed_init) {
2659                 _tegra_dc_controller_disable(dc);
2660                 return false;
2661         }
2662
2663         if (dc->out_ops && dc->out_ops->enable)
2664                 dc->out_ops->enable(dc);
2665
2666         if (dc->out->postpoweron)
2667                 dc->out->postpoweron();
2668
2669         /* force a full blending update */
2670         dc->blend.z[0] = -1;
2671
2672         tegra_dc_ext_enable(dc->ext);
2673
2674         trace_printk("%s:enable\n", dc->ndev->name);
2675         return true;
2676 }
2677
2678 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2679 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2680 {
2681         bool ret = true;
2682
2683         if (dc->out->enable)
2684                 dc->out->enable();
2685
2686         tegra_dc_setup_clk(dc, dc->clk);
2687         tegra_dc_clk_enable(dc);
2688
2689         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2690                 mutex_lock(&tegra_dcs[1]->lock);
2691                 disable_irq(tegra_dcs[1]->irq);
2692         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2693                 mutex_lock(&tegra_dcs[0]->lock);
2694                 disable_irq(tegra_dcs[0]->irq);
2695         }
2696
2697         msleep(5);
2698         tegra_periph_reset_assert(dc->clk);
2699         msleep(2);
2700 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2701         tegra_periph_reset_deassert(dc->clk);
2702         msleep(1);
2703 #endif
2704
2705         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2706                 enable_irq(tegra_dcs[1]->irq);
2707                 mutex_unlock(&tegra_dcs[1]->lock);
2708         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2709                 enable_irq(tegra_dcs[0]->irq);
2710                 mutex_unlock(&tegra_dcs[0]->lock);
2711         }
2712
2713         enable_irq(dc->irq);
2714
2715         if (tegra_dc_init(dc)) {
2716                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2717                 ret = false;
2718         }
2719
2720         if (dc->out_ops && dc->out_ops->enable)
2721                 dc->out_ops->enable(dc);
2722
2723         if (dc->out->postpoweron)
2724                 dc->out->postpoweron();
2725
2726         /* force a full blending update */
2727         dc->blend.z[0] = -1;
2728
2729         tegra_dc_ext_enable(dc->ext);
2730
2731         if (!ret) {
2732                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2733                 _tegra_dc_controller_disable(dc);
2734         }
2735
2736         trace_printk("%s:reset enable\n", dc->ndev->name);
2737         return ret;
2738 }
2739 #endif
2740
2741 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2742 {
2743         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2744 }
2745
2746 static bool _tegra_dc_enable(struct tegra_dc *dc)
2747 {
2748         if (dc->mode.pclk == 0) {
2749                 switch (dc->out->type) {
2750                 case TEGRA_DC_OUT_HDMI:
2751                 /* DC enable called but no videomode is loaded.
2752                      Check if HDMI is connected, then set fallback mdoe */
2753                 if (tegra_dc_hpd(dc)) {
2754                         if (_tegra_dc_set_default_videomode(dc))
2755                                 return false;
2756                 } else
2757                         return false;
2758
2759                 break;
2760
2761                 /* Do nothing for other outputs for now */
2762                 case TEGRA_DC_OUT_RGB:
2763
2764                 case TEGRA_DC_OUT_DSI:
2765
2766                 default:
2767                         return false;
2768                 }
2769         }
2770
2771         if (!dc->out)
2772                 return false;
2773
2774         tegra_dc_io_start(dc);
2775
2776         return _tegra_dc_controller_enable(dc);
2777 }
2778
2779 void tegra_dc_enable(struct tegra_dc *dc)
2780 {
2781         mutex_lock(&dc->lock);
2782
2783         if (!dc->enabled)
2784                 dc->enabled = _tegra_dc_enable(dc);
2785
2786         mutex_unlock(&dc->lock);
2787         print_mode_info(dc, dc->mode);
2788 }
2789
2790 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2791 {
2792         unsigned i;
2793
2794         if (dc->out_ops && dc->out_ops->disable)
2795                 dc->out_ops->disable(dc);
2796
2797         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2798         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2799         disable_irq(dc->irq);
2800
2801         tegra_dc_clear_bandwidth(dc);
2802         tegra_dc_clk_disable(dc);
2803
2804         if (dc->out && dc->out->disable)
2805                 dc->out->disable();
2806
2807         for (i = 0; i < dc->n_windows; i++) {
2808                 struct tegra_dc_win *w = &dc->windows[i];
2809
2810                 /* reset window bandwidth */
2811                 w->bandwidth = 0;
2812                 w->new_bandwidth = 0;
2813
2814                 /* disable windows */
2815                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2816
2817                 /* flush any pending syncpt waits */
2818                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2819                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2820                                 dc->syncpt[i].id);
2821                         dc->syncpt[i].min++;
2822                         nvhost_syncpt_cpu_incr(
2823                                 &nvhost_get_host(dc->ndev)->syncpt,
2824                                 dc->syncpt[i].id);
2825                 }
2826         }
2827         trace_printk("%s:disabled\n", dc->ndev->name);
2828 }
2829
2830 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2831 {
2832 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2833         u32 val;
2834         if (dc->enabled)  {
2835                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2836                 if (enable)
2837                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2838                 else
2839                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2840                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2841         }
2842 #endif
2843 }
2844
2845 bool tegra_dc_stats_get(struct tegra_dc *dc)
2846 {
2847 #if 0 /* right now it is always enabled */
2848         u32 val;
2849         bool res;
2850
2851         if (dc->enabled)  {
2852                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2853                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2854         } else {
2855                 res = false;
2856         }
2857
2858         return res;
2859 #endif
2860         return true;
2861 }
2862
2863 /* make the screen blank by disabling all windows */
2864 void tegra_dc_blank(struct tegra_dc *dc)
2865 {
2866         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2867         unsigned i;
2868
2869         for (i = 0; i < DC_N_WINDOWS; i++) {
2870                 dcwins[i] = tegra_dc_get_window(dc, i);
2871                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2872         }
2873
2874         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2875         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2876 }
2877
2878 static void _tegra_dc_disable(struct tegra_dc *dc)
2879 {
2880         _tegra_dc_controller_disable(dc);
2881         tegra_dc_io_end(dc);
2882 }
2883
2884 void tegra_dc_disable(struct tegra_dc *dc)
2885 {
2886         tegra_dc_ext_disable(dc->ext);
2887
2888         /* it's important that new underflow work isn't scheduled before the
2889          * lock is acquired. */
2890         cancel_delayed_work_sync(&dc->underflow_work);
2891         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2892                 mutex_lock(&dc->one_shot_lock);
2893                 cancel_delayed_work_sync(&dc->one_shot_work);
2894         }
2895
2896         mutex_lock(&dc->lock);
2897
2898         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2899                 tegra_dc_host_resume(dc);
2900
2901         if (dc->enabled) {
2902                 dc->enabled = false;
2903
2904                 if (!dc->suspended)
2905                         _tegra_dc_disable(dc);
2906         }
2907
2908 #ifdef CONFIG_SWITCH
2909         switch_set_state(&dc->modeset_switch, 0);
2910 #endif
2911
2912         mutex_unlock(&dc->lock);
2913         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2914                 mutex_unlock(&dc->one_shot_lock);
2915         print_mode_info(dc, dc->mode);
2916 }
2917
2918 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2919 static void tegra_dc_reset_worker(struct work_struct *work)
2920 {
2921         struct tegra_dc *dc =
2922                 container_of(work, struct tegra_dc, reset_work);
2923
2924         unsigned long val = 0;
2925
2926         mutex_lock(&shared_lock);
2927
2928         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2929
2930         tegra_dc_ext_disable(dc->ext);
2931
2932         mutex_lock(&dc->lock);
2933
2934         if (dc->enabled == false)
2935                 goto unlock;
2936
2937         dc->enabled = false;
2938
2939         /*
2940          * off host read bus
2941          */
2942         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2943         val &= ~(0x00000100);
2944         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2945
2946         /*
2947          * set DC to STOP mode
2948          */
2949         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2950
2951         msleep(10);
2952
2953         _tegra_dc_controller_disable(dc);
2954
2955         /* _tegra_dc_controller_reset_enable deasserts reset */
2956         _tegra_dc_controller_reset_enable(dc);
2957
2958         dc->enabled = true;
2959
2960         /* reopen host read bus */
2961         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2962         val &= ~(0x00000100);
2963         val |= 0x100;
2964         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2965
2966 unlock:
2967         mutex_unlock(&dc->lock);
2968         mutex_unlock(&shared_lock);
2969         trace_printk("%s:reset complete\n", dc->ndev->name);
2970 }
2971 #endif
2972
2973 static void tegra_dc_underflow_worker(struct work_struct *work)
2974 {
2975         struct tegra_dc *dc = container_of(
2976                 to_delayed_work(work), struct tegra_dc, underflow_work);
2977
2978         mutex_lock(&dc->lock);
2979         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2980                 tegra_dc_host_resume(dc);
2981
2982         if (dc->enabled) {
2983                 tegra_dc_underflow_handler(dc);
2984         }
2985         mutex_unlock(&dc->lock);
2986 }
2987
2988 #ifdef CONFIG_SWITCH
2989 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2990 {
2991         struct tegra_dc *dc =
2992                 container_of(sdev, struct tegra_dc, modeset_switch);
2993
2994         if (!sdev->state)
2995                 return sprintf(buf, "offline\n");
2996
2997         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2998 }
2999 #endif
3000
3001 static int tegra_dc_probe(struct nvhost_device *ndev,
3002         struct nvhost_device_id *id_table)
3003 {
3004         struct tegra_dc *dc;
3005         struct clk *clk;
3006         struct clk *emc_clk;
3007         struct resource *res;
3008         struct resource *base_res;
3009         struct resource *fb_mem = NULL;
3010         int ret = 0;
3011         void __iomem *base;
3012         int irq;
3013         int i;
3014
3015         if (!ndev->dev.platform_data) {
3016                 dev_err(&ndev->dev, "no platform data\n");
3017                 return -ENOENT;
3018         }
3019
3020         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3021         if (!dc) {
3022                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3023                 return -ENOMEM;
3024         }
3025
3026         irq = nvhost_get_irq_byname(ndev, "irq");
3027         if (irq <= 0) {
3028                 dev_err(&ndev->dev, "no irq\n");
3029                 ret = -ENOENT;
3030                 goto err_free;
3031         }
3032
3033         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
3034         if (!res) {
3035                 dev_err(&ndev->dev, "no mem resource\n");
3036                 ret = -ENOENT;
3037                 goto err_free;
3038         }
3039
3040         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
3041         if (!base_res) {
3042                 dev_err(&ndev->dev, "request_mem_region failed\n");
3043                 ret = -EBUSY;
3044                 goto err_free;
3045         }
3046
3047         base = ioremap(res->start, resource_size(res));
3048         if (!base) {
3049                 dev_err(&ndev->dev, "registers can't be mapped\n");
3050                 ret = -EBUSY;
3051                 goto err_release_resource_reg;
3052         }
3053
3054         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
3055
3056         clk = clk_get(&ndev->dev, NULL);
3057         if (IS_ERR_OR_NULL(clk)) {
3058                 dev_err(&ndev->dev, "can't get clock\n");
3059                 ret = -ENOENT;
3060                 goto err_iounmap_reg;
3061         }
3062
3063         emc_clk = clk_get(&ndev->dev, "emc");
3064         if (IS_ERR_OR_NULL(emc_clk)) {
3065                 dev_err(&ndev->dev, "can't get emc clock\n");
3066                 ret = -ENOENT;
3067                 goto err_put_clk;
3068         }
3069
3070         dc->clk = clk;
3071         dc->emc_clk = emc_clk;
3072         dc->shift_clk_div = 1;
3073         /* Initialize one shot work delay, it will be assigned by dsi
3074          * according to refresh rate later. */
3075         dc->one_shot_delay_ms = 40;
3076
3077         dc->base_res = base_res;
3078         dc->base = base;
3079         dc->irq = irq;
3080         dc->ndev = ndev;
3081         dc->pdata = ndev->dev.platform_data;
3082
3083         /*
3084          * The emc is a shared clock, it will be set based on
3085          * the requirements for each user on the bus.
3086          */
3087         dc->emc_clk_rate = 0;
3088
3089         mutex_init(&dc->lock);
3090         mutex_init(&dc->one_shot_lock);
3091         init_completion(&dc->frame_end_complete);
3092         init_waitqueue_head(&dc->wq);
3093 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3094         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3095 #endif
3096         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3097         dc->vblank_ref_count = 0;
3098         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3099         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3100
3101         tegra_dc_init_lut_defaults(&dc->fb_lut);
3102
3103         dc->n_windows = DC_N_WINDOWS;
3104         for (i = 0; i < dc->n_windows; i++) {
3105                 struct tegra_dc_win *win = &dc->windows[i];
3106                 win->idx = i;
3107                 win->dc = dc;
3108                 tegra_dc_init_csc_defaults(&win->csc);
3109                 tegra_dc_init_lut_defaults(&win->lut);
3110         }
3111
3112         ret = tegra_dc_set(dc, ndev->id);
3113         if (ret < 0) {
3114                 dev_err(&ndev->dev, "can't add dc\n");
3115                 goto err_free_irq;
3116         }
3117
3118         nvhost_set_drvdata(ndev, dc);
3119
3120 #ifdef CONFIG_SWITCH
3121         dc->modeset_switch.name = dev_name(&ndev->dev);
3122         dc->modeset_switch.state = 0;
3123         dc->modeset_switch.print_state = switch_modeset_print_mode;
3124         switch_dev_register(&dc->modeset_switch);
3125 #endif
3126
3127         tegra_dc_feature_register(dc);
3128
3129         if (dc->pdata->default_out)
3130                 tegra_dc_set_out(dc, dc->pdata->default_out);
3131         else
3132                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3133
3134         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3135                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3136
3137         dc->ext = tegra_dc_ext_register(ndev, dc);
3138         if (IS_ERR_OR_NULL(dc->ext)) {
3139                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3140                 dc->ext = NULL;
3141         }
3142
3143         mutex_lock(&dc->lock);
3144         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
3145                 dc->enabled = _tegra_dc_enable(dc);
3146         mutex_unlock(&dc->lock);
3147
3148         /* interrupt handler must be registered before tegra_fb_register() */
3149         if (request_irq(irq, tegra_dc_irq, 0,
3150                         dev_name(&ndev->dev), dc)) {
3151                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3152                 ret = -EBUSY;
3153                 goto err_put_emc_clk;
3154         }
3155
3156         tegra_dc_create_debugfs(dc);
3157
3158         dev_info(&ndev->dev, "probed\n");
3159
3160         if (dc->pdata->fb) {
3161                 if (dc->pdata->fb->bits_per_pixel == -1) {
3162                         unsigned long fmt;
3163                         tegra_dc_writel(dc,
3164                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3165                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3166
3167                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3168                         dc->pdata->fb->bits_per_pixel =
3169                                 tegra_dc_fmt_bpp(fmt);
3170                 }
3171
3172                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3173                 if (IS_ERR_OR_NULL(dc->fb))
3174                         dc->fb = NULL;
3175         }
3176
3177         if (dc->out && dc->out->hotplug_init)
3178                 dc->out->hotplug_init();
3179
3180         if (dc->out_ops && dc->out_ops->detect)
3181                 dc->out_ops->detect(dc);
3182         else
3183                 dc->connected = true;
3184
3185         tegra_dc_create_sysfs(&dc->ndev->dev);
3186
3187         return 0;
3188
3189 err_free_irq:
3190         free_irq(irq, dc);
3191 err_put_emc_clk:
3192         clk_put(emc_clk);
3193 err_put_clk:
3194         clk_put(clk);
3195 err_iounmap_reg:
3196         iounmap(base);
3197         if (fb_mem)
3198                 release_resource(fb_mem);
3199 err_release_resource_reg:
3200         release_resource(base_res);
3201 err_free:
3202         kfree(dc);
3203
3204         return ret;
3205 }
3206
3207 static int tegra_dc_remove(struct nvhost_device *ndev)
3208 {
3209         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3210
3211         tegra_dc_remove_sysfs(&dc->ndev->dev);
3212         tegra_dc_remove_debugfs(dc);
3213
3214         if (dc->fb) {
3215                 tegra_fb_unregister(dc->fb);
3216                 if (dc->fb_mem)
3217                         release_resource(dc->fb_mem);
3218         }
3219
3220         tegra_dc_ext_disable(dc->ext);
3221
3222         if (dc->ext)
3223                 tegra_dc_ext_unregister(dc->ext);
3224
3225         if (dc->enabled)
3226                 _tegra_dc_disable(dc);
3227
3228 #ifdef CONFIG_SWITCH
3229         switch_dev_unregister(&dc->modeset_switch);
3230 #endif
3231         free_irq(dc->irq, dc);
3232         clk_put(dc->emc_clk);
3233         clk_put(dc->clk);
3234         iounmap(dc->base);
3235         if (dc->fb_mem)
3236                 release_resource(dc->base_res);
3237         kfree(dc);
3238         tegra_dc_set(NULL, ndev->id);
3239         return 0;
3240 }
3241
3242 #ifdef CONFIG_PM
3243 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3244 {
3245         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3246
3247         trace_printk("%s:suspend\n", dc->ndev->name);
3248         dev_info(&ndev->dev, "suspend\n");
3249
3250         tegra_dc_ext_disable(dc->ext);
3251
3252         mutex_lock(&dc->lock);
3253
3254         if (dc->out_ops && dc->out_ops->suspend)
3255                 dc->out_ops->suspend(dc);
3256
3257         if (dc->enabled) {
3258                 _tegra_dc_disable(dc);
3259
3260                 dc->suspended = true;
3261         }
3262
3263         if (dc->out && dc->out->postsuspend) {
3264                 dc->out->postsuspend();
3265                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3266                         /*
3267                          * avoid resume event due to voltage falling
3268                          */
3269                         msleep(100);
3270         }
3271
3272         mutex_unlock(&dc->lock);
3273
3274         return 0;
3275 }
3276
3277 static int tegra_dc_resume(struct nvhost_device *ndev)
3278 {
3279         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3280
3281         trace_printk("%s:resume\n", dc->ndev->name);
3282         dev_info(&ndev->dev, "resume\n");
3283
3284         mutex_lock(&dc->lock);
3285         dc->suspended = false;
3286
3287         if (dc->enabled)
3288                 _tegra_dc_enable(dc);
3289
3290         if (dc->out && dc->out->hotplug_init)
3291                 dc->out->hotplug_init();
3292
3293         if (dc->out_ops && dc->out_ops->resume)
3294                 dc->out_ops->resume(dc);
3295         mutex_unlock(&dc->lock);
3296
3297         return 0;
3298 }
3299
3300 #endif /* CONFIG_PM */
3301
3302 static void tegra_dc_shutdown(struct nvhost_device *ndev)
3303 {
3304         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3305
3306         if (!dc || !dc->enabled)
3307                 return;
3308
3309         tegra_dc_blank(dc);
3310         tegra_dc_disable(dc);
3311 }
3312
3313 extern int suspend_set(const char *val, struct kernel_param *kp)
3314 {
3315         if (!strcmp(val, "dump"))
3316                 dump_regs(tegra_dcs[0]);
3317 #ifdef CONFIG_PM
3318         else if (!strcmp(val, "suspend"))
3319                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3320         else if (!strcmp(val, "resume"))
3321                 tegra_dc_resume(tegra_dcs[0]->ndev);
3322 #endif
3323
3324         return 0;
3325 }
3326
3327 extern int suspend_get(char *buffer, struct kernel_param *kp)
3328 {
3329         return 0;
3330 }
3331
3332 int suspend;
3333
3334 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3335
3336 struct nvhost_driver tegra_dc_driver = {
3337         .driver = {
3338                 .name = "tegradc",
3339                 .owner = THIS_MODULE,
3340         },
3341         .probe = tegra_dc_probe,
3342         .remove = tegra_dc_remove,
3343 #ifdef CONFIG_PM
3344         .suspend = tegra_dc_suspend,
3345         .resume = tegra_dc_resume,
3346 #endif
3347         .shutdown = tegra_dc_shutdown,
3348 };
3349
3350 static int __init tegra_dc_module_init(void)
3351 {
3352         int ret = tegra_dc_ext_module_init();
3353         if (ret)
3354                 return ret;
3355         return nvhost_driver_register(&tegra_dc_driver);
3356 }
3357
3358 static void __exit tegra_dc_module_exit(void)
3359 {
3360         nvhost_driver_unregister(&tegra_dc_driver);
3361         tegra_dc_ext_module_exit();
3362 }
3363
3364 module_exit(tegra_dc_module_exit);
3365 module_init(tegra_dc_module_init);