tegra: dc: Fix div by zero in frame time computation.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
63         .refresh = 60,
64         .xres = 640,
65         .yres = 480,
66         .pixclock = KHZ2PICOS(25200),
67         .hsync_len = 96,        /* h_sync_width */
68         .vsync_len = 2,         /* v_sync_width */
69         .left_margin = 48,      /* h_back_porch */
70         .upper_margin = 33,     /* v_back_porch */
71         .right_margin = 16,     /* h_front_porch */
72         .lower_margin = 10,     /* v_front_porch */
73         .vmode = 0,
74         .sync = 0,
75 };
76
77 static struct tegra_dc_mode override_disp_mode[3];
78
79 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
80
81 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
82
83 DEFINE_MUTEX(tegra_dc_lock);
84 DEFINE_MUTEX(shared_lock);
85
86 static const struct {
87         bool h;
88         bool v;
89 } can_filter[] = {
90         /* Window A has no filtering */
91         { false, false },
92         /* Window B has both H and V filtering */
93         { true,  true  },
94         /* Window C has only H filtering */
95         { false, true  },
96 };
97
98 #ifdef CONFIG_TEGRA_DC_CMU
99 static struct tegra_dc_cmu default_cmu = {
100         /* lut1 maps sRGB to linear space. */
101         {
102                 0,    1,    2,    4,    5,    6,    7,    9,
103                 10,   11,   12,   14,   15,   16,   18,   20,
104                 21,   23,   25,   27,   29,   31,   33,   35,
105                 37,   40,   42,   45,   48,   50,   53,   56,
106                 59,   62,   66,   69,   72,   76,   79,   83,
107                 87,   91,   95,   99,   103,  107,  112,  116,
108                 121,  126,  131,  136,  141,  146,  151,  156,
109                 162,  168,  173,  179,  185,  191,  197,  204,
110                 210,  216,  223,  230,  237,  244,  251,  258,
111                 265,  273,  280,  288,  296,  304,  312,  320,
112                 329,  337,  346,  354,  363,  372,  381,  390,
113                 400,  409,  419,  428,  438,  448,  458,  469,
114                 479,  490,  500,  511,  522,  533,  544,  555,
115                 567,  578,  590,  602,  614,  626,  639,  651,
116                 664,  676,  689,  702,  715,  728,  742,  755,
117                 769,  783,  797,  811,  825,  840,  854,  869,
118                 884,  899,  914,  929,  945,  960,  976,  992,
119                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
120                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
121                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
122                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
123                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
124                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
125                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
126                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
127                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
128                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
129                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
130                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
131                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
132                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
133                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
134         },
135         /* csc */
136         {
137                 0x100, 0x0,   0x0,
138                 0x0,   0x100, 0x0,
139                 0x0,   0x0,   0x100,
140         },
141         /* lut2 maps linear space to sRGB*/
142         {
143                 0,    1,    2,    2,    3,    4,    5,    6,
144                 6,    7,    8,    9,    10,   10,   11,   12,
145                 13,   13,   14,   15,   15,   16,   16,   17,
146                 18,   18,   19,   19,   20,   20,   21,   21,
147                 22,   22,   23,   23,   23,   24,   24,   25,
148                 25,   25,   26,   26,   27,   27,   27,   28,
149                 28,   29,   29,   29,   30,   30,   30,   31,
150                 31,   31,   32,   32,   32,   33,   33,   33,
151                 34,   34,   34,   34,   35,   35,   35,   36,
152                 36,   36,   37,   37,   37,   37,   38,   38,
153                 38,   38,   39,   39,   39,   40,   40,   40,
154                 40,   41,   41,   41,   41,   42,   42,   42,
155                 42,   43,   43,   43,   43,   43,   44,   44,
156                 44,   44,   45,   45,   45,   45,   46,   46,
157                 46,   46,   46,   47,   47,   47,   47,   48,
158                 48,   48,   48,   48,   49,   49,   49,   49,
159                 49,   50,   50,   50,   50,   50,   51,   51,
160                 51,   51,   51,   52,   52,   52,   52,   52,
161                 53,   53,   53,   53,   53,   54,   54,   54,
162                 54,   54,   55,   55,   55,   55,   55,   55,
163                 56,   56,   56,   56,   56,   57,   57,   57,
164                 57,   57,   57,   58,   58,   58,   58,   58,
165                 58,   59,   59,   59,   59,   59,   59,   60,
166                 60,   60,   60,   60,   60,   61,   61,   61,
167                 61,   61,   61,   62,   62,   62,   62,   62,
168                 62,   63,   63,   63,   63,   63,   63,   64,
169                 64,   64,   64,   64,   64,   64,   65,   65,
170                 65,   65,   65,   65,   66,   66,   66,   66,
171                 66,   66,   66,   67,   67,   67,   67,   67,
172                 67,   67,   68,   68,   68,   68,   68,   68,
173                 68,   69,   69,   69,   69,   69,   69,   69,
174                 70,   70,   70,   70,   70,   70,   70,   71,
175                 71,   71,   71,   71,   71,   71,   72,   72,
176                 72,   72,   72,   72,   72,   72,   73,   73,
177                 73,   73,   73,   73,   73,   74,   74,   74,
178                 74,   74,   74,   74,   74,   75,   75,   75,
179                 75,   75,   75,   75,   75,   76,   76,   76,
180                 76,   76,   76,   76,   77,   77,   77,   77,
181                 77,   77,   77,   77,   78,   78,   78,   78,
182                 78,   78,   78,   78,   78,   79,   79,   79,
183                 79,   79,   79,   79,   79,   80,   80,   80,
184                 80,   80,   80,   80,   80,   81,   81,   81,
185                 81,   81,   81,   81,   81,   81,   82,   82,
186                 82,   82,   82,   82,   82,   82,   83,   83,
187                 83,   83,   83,   83,   83,   83,   83,   84,
188                 84,   84,   84,   84,   84,   84,   84,   84,
189                 85,   85,   85,   85,   85,   85,   85,   85,
190                 85,   86,   86,   86,   86,   86,   86,   86,
191                 86,   86,   87,   87,   87,   87,   87,   87,
192                 87,   87,   87,   88,   88,   88,   88,   88,
193                 88,   88,   88,   88,   88,   89,   89,   89,
194                 89,   89,   89,   89,   89,   89,   90,   90,
195                 90,   90,   90,   90,   90,   90,   90,   90,
196                 91,   91,   91,   91,   91,   91,   91,   91,
197                 91,   91,   92,   92,   92,   92,   92,   92,
198                 92,   92,   92,   92,   93,   93,   93,   93,
199                 93,   93,   93,   93,   93,   93,   94,   94,
200                 94,   94,   94,   94,   94,   94,   94,   94,
201                 95,   95,   95,   95,   95,   95,   95,   95,
202                 95,   95,   96,   96,   96,   96,   96,   96,
203                 96,   96,   96,   96,   96,   97,   97,   97,
204                 97,   97,   97,   97,   97,   97,   97,   98,
205                 98,   98,   98,   98,   98,   98,   98,   98,
206                 98,   98,   99,   99,   99,   99,   99,   99,
207                 99,   100,  101,  101,  102,  103,  103,  104,
208                 105,  105,  106,  107,  107,  108,  109,  109,
209                 110,  111,  111,  112,  113,  113,  114,  115,
210                 115,  116,  116,  117,  118,  118,  119,  119,
211                 120,  120,  121,  122,  122,  123,  123,  124,
212                 124,  125,  126,  126,  127,  127,  128,  128,
213                 129,  129,  130,  130,  131,  131,  132,  132,
214                 133,  133,  134,  134,  135,  135,  136,  136,
215                 137,  137,  138,  138,  139,  139,  140,  140,
216                 141,  141,  142,  142,  143,  143,  144,  144,
217                 145,  145,  145,  146,  146,  147,  147,  148,
218                 148,  149,  149,  150,  150,  150,  151,  151,
219                 152,  152,  153,  153,  153,  154,  154,  155,
220                 155,  156,  156,  156,  157,  157,  158,  158,
221                 158,  159,  159,  160,  160,  160,  161,  161,
222                 162,  162,  162,  163,  163,  164,  164,  164,
223                 165,  165,  166,  166,  166,  167,  167,  167,
224                 168,  168,  169,  169,  169,  170,  170,  170,
225                 171,  171,  172,  172,  172,  173,  173,  173,
226                 174,  174,  174,  175,  175,  176,  176,  176,
227                 177,  177,  177,  178,  178,  178,  179,  179,
228                 179,  180,  180,  180,  181,  181,  182,  182,
229                 182,  183,  183,  183,  184,  184,  184,  185,
230                 185,  185,  186,  186,  186,  187,  187,  187,
231                 188,  188,  188,  189,  189,  189,  189,  190,
232                 190,  190,  191,  191,  191,  192,  192,  192,
233                 193,  193,  193,  194,  194,  194,  195,  195,
234                 195,  196,  196,  196,  196,  197,  197,  197,
235                 198,  198,  198,  199,  199,  199,  200,  200,
236                 200,  200,  201,  201,  201,  202,  202,  202,
237                 202,  203,  203,  203,  204,  204,  204,  205,
238                 205,  205,  205,  206,  206,  206,  207,  207,
239                 207,  207,  208,  208,  208,  209,  209,  209,
240                 209,  210,  210,  210,  211,  211,  211,  211,
241                 212,  212,  212,  213,  213,  213,  213,  214,
242                 214,  214,  214,  215,  215,  215,  216,  216,
243                 216,  216,  217,  217,  217,  217,  218,  218,
244                 218,  219,  219,  219,  219,  220,  220,  220,
245                 220,  221,  221,  221,  221,  222,  222,  222,
246                 223,  223,  223,  223,  224,  224,  224,  224,
247                 225,  225,  225,  225,  226,  226,  226,  226,
248                 227,  227,  227,  227,  228,  228,  228,  228,
249                 229,  229,  229,  229,  230,  230,  230,  230,
250                 231,  231,  231,  231,  232,  232,  232,  232,
251                 233,  233,  233,  233,  234,  234,  234,  234,
252                 235,  235,  235,  235,  236,  236,  236,  236,
253                 237,  237,  237,  237,  238,  238,  238,  238,
254                 239,  239,  239,  239,  240,  240,  240,  240,
255                 240,  241,  241,  241,  241,  242,  242,  242,
256                 242,  243,  243,  243,  243,  244,  244,  244,
257                 244,  244,  245,  245,  245,  245,  246,  246,
258                 246,  246,  247,  247,  247,  247,  247,  248,
259                 248,  248,  248,  249,  249,  249,  249,  249,
260                 250,  250,  250,  250,  251,  251,  251,  251,
261                 251,  252,  252,  252,  252,  253,  253,  253,
262                 253,  253,  254,  254,  254,  254,  255,  255,
263         },
264 };
265 #endif
266
267 void tegra_dc_clk_enable(struct tegra_dc *dc)
268 {
269         if (!tegra_is_clk_enabled(dc->clk)) {
270                 clk_enable(dc->clk);
271                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
272         }
273 }
274
275 void tegra_dc_clk_disable(struct tegra_dc *dc)
276 {
277         if (tegra_is_clk_enabled(dc->clk)) {
278                 clk_disable(dc->clk);
279                 tegra_dvfs_set_rate(dc->clk, 0);
280         }
281 }
282
283 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
284 {
285         if (dc->out_ops->hold)
286                 dc->out_ops->hold(dc);
287 }
288
289 void tegra_dc_release_dc_out(struct tegra_dc *dc)
290 {
291         if (dc->out_ops->release)
292                 dc->out_ops->release(dc);
293 }
294
295 #define DUMP_REG(a) do {                        \
296         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
297                  #a, a, tegra_dc_readl(dc, a));               \
298         print(data, buff);                                    \
299         } while (0)
300
301 #define print_underflow_info(dc) do {                 \
302         trace_printk("%s:Underflow stats: underflows : %llu, "      \
303                         "undeflows_a : %llu, "                          \
304                         "underflows_b : %llu, "                         \
305                         "underflows_c : %llu\n",                        \
306                         dc->ndev->name,                                 \
307                         dc->stats.underflows,                           \
308                         dc->stats.underflows_a, dc->stats.underflows_b, \
309                         dc->stats.underflows_c);                        \
310         } while (0)
311
312 static void _dump_regs(struct tegra_dc *dc, void *data,
313                        void (* print)(void *data, const char *str))
314 {
315         int i;
316         char buff[256];
317
318         mutex_lock(&dc->lock);
319         tegra_dc_hold_dc_out(dc);
320         tegra_dc_io_start(dc);
321
322         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
323         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE);
325         DUMP_REG(DC_CMD_INT_STATUS);
326         DUMP_REG(DC_CMD_INT_MASK);
327         DUMP_REG(DC_CMD_INT_ENABLE);
328         DUMP_REG(DC_CMD_INT_TYPE);
329         DUMP_REG(DC_CMD_INT_POLARITY);
330         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
331         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
332         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
333         DUMP_REG(DC_CMD_STATE_ACCESS);
334         DUMP_REG(DC_CMD_STATE_CONTROL);
335         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
336         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
337
338         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
339         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
340         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
341         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
342         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
343         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
344         DUMP_REG(DC_DISP_REF_TO_SYNC);
345         DUMP_REG(DC_DISP_SYNC_WIDTH);
346         DUMP_REG(DC_DISP_BACK_PORCH);
347         DUMP_REG(DC_DISP_DISP_ACTIVE);
348         DUMP_REG(DC_DISP_FRONT_PORCH);
349         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
350         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
351         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
352         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
353         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
354         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
355         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
356         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
357         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
358         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
359         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
360         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
361         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
362         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
363         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
364         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
367         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
368         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
369         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
370         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
371         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
372         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
373         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
374         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
375         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
376         DUMP_REG(DC_DISP_M0_CONTROL);
377         DUMP_REG(DC_DISP_M1_CONTROL);
378         DUMP_REG(DC_DISP_DI_CONTROL);
379         DUMP_REG(DC_DISP_PP_CONTROL);
380         DUMP_REG(DC_DISP_PP_SELECT_A);
381         DUMP_REG(DC_DISP_PP_SELECT_B);
382         DUMP_REG(DC_DISP_PP_SELECT_C);
383         DUMP_REG(DC_DISP_PP_SELECT_D);
384         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
385         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
386         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
387         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
388         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
389         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
390         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
391         DUMP_REG(DC_DISP_BORDER_COLOR);
392         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
393         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
394         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
395         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
396         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
397         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
398         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
399         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
400         DUMP_REG(DC_DISP_CURSOR_POSITION);
401         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
402         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
403         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
404         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
405         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
406         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
407         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
408         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
409         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
410         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
412         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
413         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
414
415
416         for (i = 0; i < 3; i++) {
417                 print(data, "\n");
418                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
419                 print(data, buff);
420
421                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
422                                 DC_CMD_DISPLAY_WINDOW_HEADER);
423                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
424                 DUMP_REG(DC_WIN_WIN_OPTIONS);
425                 DUMP_REG(DC_WIN_BYTE_SWAP);
426                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
427                 DUMP_REG(DC_WIN_COLOR_DEPTH);
428                 DUMP_REG(DC_WIN_POSITION);
429                 DUMP_REG(DC_WIN_SIZE);
430                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
431                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
432                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
433                 DUMP_REG(DC_WIN_DDA_INCREMENT);
434                 DUMP_REG(DC_WIN_LINE_STRIDE);
435 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
436                 DUMP_REG(DC_WIN_BUF_STRIDE);
437                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
438 #endif
439                 DUMP_REG(DC_WIN_BLEND_NOKEY);
440                 DUMP_REG(DC_WIN_BLEND_1WIN);
441                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
442                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
443                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
444                 DUMP_REG(DC_WINBUF_START_ADDR);
445                 DUMP_REG(DC_WINBUF_START_ADDR_U);
446                 DUMP_REG(DC_WINBUF_START_ADDR_V);
447                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
448                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
449                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
450                 DUMP_REG(DC_WIN_CSC_YOF);
451                 DUMP_REG(DC_WIN_CSC_KYRGB);
452                 DUMP_REG(DC_WIN_CSC_KUR);
453                 DUMP_REG(DC_WIN_CSC_KVR);
454                 DUMP_REG(DC_WIN_CSC_KUG);
455                 DUMP_REG(DC_WIN_CSC_KVG);
456                 DUMP_REG(DC_WIN_CSC_KUB);
457                 DUMP_REG(DC_WIN_CSC_KVB);
458         }
459
460         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
461         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
462         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
463         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
464         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
465         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
466         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
467         DUMP_REG(DC_DISP_M1_CONTROL);
468         DUMP_REG(DC_COM_PM1_CONTROL);
469         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
470         DUMP_REG(DC_DISP_SD_CONTROL);
471
472         tegra_dc_io_end(dc);
473         tegra_dc_release_dc_out(dc);
474         mutex_unlock(&dc->lock);
475 }
476
477 #undef DUMP_REG
478
479 #ifdef DEBUG
480 static void dump_regs_print(void *data, const char *str)
481 {
482         struct tegra_dc *dc = data;
483         dev_dbg(&dc->ndev->dev, "%s", str);
484 }
485
486 static void dump_regs(struct tegra_dc *dc)
487 {
488         _dump_regs(dc, dc, dump_regs_print);
489 }
490 #else /* !DEBUG */
491
492 static void dump_regs(struct tegra_dc *dc) {}
493
494 #endif /* DEBUG */
495
496 #ifdef CONFIG_DEBUG_FS
497
498 static void dbg_regs_print(void *data, const char *str)
499 {
500         struct seq_file *s = data;
501
502         seq_printf(s, "%s", str);
503 }
504
505 #undef DUMP_REG
506
507 static int dbg_dc_show(struct seq_file *s, void *unused)
508 {
509         struct tegra_dc *dc = s->private;
510
511         _dump_regs(dc, s, dbg_regs_print);
512
513         return 0;
514 }
515
516
517 static int dbg_dc_open(struct inode *inode, struct file *file)
518 {
519         return single_open(file, dbg_dc_show, inode->i_private);
520 }
521
522 static const struct file_operations regs_fops = {
523         .open           = dbg_dc_open,
524         .read           = seq_read,
525         .llseek         = seq_lseek,
526         .release        = single_release,
527 };
528
529 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
530 {
531         struct tegra_dc *dc = s->private;
532         struct tegra_dc_mode *m;
533
534         mutex_lock(&dc->lock);
535         m = &dc->mode;
536         seq_printf(s,
537                 "pclk: %d\n"
538                 "h_ref_to_sync: %d\n"
539                 "v_ref_to_sync: %d\n"
540                 "h_sync_width: %d\n"
541                 "v_sync_width: %d\n"
542                 "h_back_porch: %d\n"
543                 "v_back_porch: %d\n"
544                 "h_active: %d\n"
545                 "v_active: %d\n"
546                 "h_front_porch: %d\n"
547                 "v_front_porch: %d\n"
548                 "stereo_mode: %d\n",
549                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
550                 m->h_sync_width, m->v_sync_width,
551                 m->h_back_porch, m->v_back_porch,
552                 m->h_active, m->v_active,
553                 m->h_front_porch, m->v_front_porch,
554                 m->stereo_mode);
555         mutex_unlock(&dc->lock);
556         return 0;
557 }
558
559 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
560 {
561         return single_open(file, dbg_dc_mode_show, inode->i_private);
562 }
563
564 static const struct file_operations mode_fops = {
565         .open           = dbg_dc_mode_open,
566         .read           = seq_read,
567         .llseek         = seq_lseek,
568         .release        = single_release,
569 };
570
571 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
572 {
573         struct tegra_dc *dc = s->private;
574
575         mutex_lock(&dc->lock);
576         seq_printf(s,
577                 "underflows: %llu\n"
578                 "underflows_a: %llu\n"
579                 "underflows_b: %llu\n"
580                 "underflows_c: %llu\n",
581                 dc->stats.underflows,
582                 dc->stats.underflows_a,
583                 dc->stats.underflows_b,
584                 dc->stats.underflows_c);
585         mutex_unlock(&dc->lock);
586
587         return 0;
588 }
589
590 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
591 {
592         return single_open(file, dbg_dc_stats_show, inode->i_private);
593 }
594
595 static const struct file_operations stats_fops = {
596         .open           = dbg_dc_stats_open,
597         .read           = seq_read,
598         .llseek         = seq_lseek,
599         .release        = single_release,
600 };
601
602 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
603 {
604         if (dc->debugdir)
605                 debugfs_remove_recursive(dc->debugdir);
606         dc->debugdir = NULL;
607 }
608
609 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
610 {
611         struct dentry *retval;
612
613         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
614         if (!dc->debugdir)
615                 goto remove_out;
616
617         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
618                 &regs_fops);
619         if (!retval)
620                 goto remove_out;
621
622         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
623                 &mode_fops);
624         if (!retval)
625                 goto remove_out;
626
627         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
628                 &stats_fops);
629         if (!retval)
630                 goto remove_out;
631
632         return;
633 remove_out:
634         dev_err(&dc->ndev->dev, "could not create debugfs\n");
635         tegra_dc_remove_debugfs(dc);
636 }
637
638 #else /* !CONFIG_DEBUGFS */
639 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
640 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
641 #endif /* CONFIG_DEBUGFS */
642
643 static int tegra_dc_set(struct tegra_dc *dc, int index)
644 {
645         int ret = 0;
646
647         mutex_lock(&tegra_dc_lock);
648         if (index >= TEGRA_MAX_DC) {
649                 ret = -EINVAL;
650                 goto out;
651         }
652
653         if (dc != NULL && tegra_dcs[index] != NULL) {
654                 ret = -EBUSY;
655                 goto out;
656         }
657
658         tegra_dcs[index] = dc;
659
660 out:
661         mutex_unlock(&tegra_dc_lock);
662
663         return ret;
664 }
665
666 unsigned int tegra_dc_has_multiple_dc(void)
667 {
668         unsigned int idx;
669         unsigned int cnt = 0;
670         struct tegra_dc *dc;
671
672         mutex_lock(&tegra_dc_lock);
673         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
674                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
675         mutex_unlock(&tegra_dc_lock);
676
677         return (cnt > 1);
678 }
679
680 /* get the stride size of a window.
681  * return: stride size in bytes for window win. or 0 if unavailble. */
682 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
683 {
684         u32 stride;
685
686         if (!dc->enabled)
687                 return 0;
688         BUG_ON(win > DC_N_WINDOWS);
689         mutex_lock(&dc->lock);
690         tegra_dc_hold_dc_out(dc);
691         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
692                 DC_CMD_DISPLAY_WINDOW_HEADER);
693         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
694         tegra_dc_release_dc_out(dc);
695         mutex_unlock(&dc->lock);
696         return GET_LINE_STRIDE(stride);
697 }
698 EXPORT_SYMBOL(tegra_dc_get_stride);
699
700 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
701 {
702         if (idx < TEGRA_MAX_DC)
703                 return tegra_dcs[idx];
704         else
705                 return NULL;
706 }
707 EXPORT_SYMBOL(tegra_dc_get_dc);
708
709 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
710 {
711         if (win >= dc->n_windows)
712                 return NULL;
713
714         return &dc->windows[win];
715 }
716 EXPORT_SYMBOL(tegra_dc_get_window);
717
718 bool tegra_dc_get_connected(struct tegra_dc *dc)
719 {
720         return dc->connected;
721 }
722 EXPORT_SYMBOL(tegra_dc_get_connected);
723
724 bool tegra_dc_hpd(struct tegra_dc *dc)
725 {
726         int sense;
727         int level;
728
729         level = gpio_get_value(dc->out->hotplug_gpio);
730
731         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
732
733         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
734                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
735 }
736 EXPORT_SYMBOL(tegra_dc_hpd);
737
738 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
739 {
740         unsigned i;
741         unsigned v0 = 128;
742         unsigned v1 = 0;
743         /* linear horizontal and vertical filters */
744         for (i = 0; i < 16; i++) {
745                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
746                                 DC_WIN_H_FILTER_P(i));
747
748                 tegra_dc_writel(dc, v0,
749                                 DC_WIN_V_FILTER_P(i));
750                 v0 -= 8;
751                 v1 += 8;
752         }
753 }
754
755 #ifdef CONFIG_TEGRA_DC_CMU
756 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
757                                                 struct tegra_dc_cmu *src_cmu)
758 {
759         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
760 }
761
762 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
763 {
764         u32 val;
765         u32 i;
766
767         for (i = 0; i < 256; i++) {
768                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
769                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
770         }
771
772         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
773         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
774         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
775         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
776         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
777         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
778         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
779         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
780         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
781
782         for (i = 0; i < 960; i++) {
783                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
784                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
785         }
786 }
787
788 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
789 {
790         u32 val;
791         u32 i;
792         bool flags;
793
794         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
795         if (val & CMU_ENABLE)
796                 flags = true;
797
798         val &= ~CMU_ENABLE;
799         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
800         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
801         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
802
803         /*TODO: Sync up with frame end */
804         mdelay(20);
805
806         for (i = 0; i < 256; i++) {
807                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
808                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
809                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
810                 cmu->lut1[i] = LUT1_READ_DATA(val);
811         }
812
813         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
814         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
815         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
816         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
817         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
818         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
819         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
820         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
821         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
822
823         for (i = 0; i < 960; i++) {
824                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
825                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
826                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
827                 cmu->lut2[i] = LUT2_READ_DATA(val);
828         }
829 }
830 EXPORT_SYMBOL(tegra_dc_get_cmu);
831
832 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
833 {
834         mutex_lock(&dc->lock);
835
836         if (!dc->enabled) {
837                 mutex_unlock(&dc->lock);
838                 return -EFAULT;
839         }
840
841         if (cmu_enable) {
842                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
843         } else {
844                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
845                 return 0;
846         }
847
848         tegra_dc_set_cmu(dc, &dc->cmu);
849
850         mutex_unlock(&dc->lock);
851
852         return 0;
853 }
854 EXPORT_SYMBOL(tegra_dc_update_cmu);
855 #else
856 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
857 #define tegra_dc_set_cmu(dc, cmu)
858 #endif
859
860 static inline void disable_dc_irq(unsigned int irq)
861 {
862         disable_irq(irq);
863 }
864
865 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
866 {
867         return dc->syncpt[i].id;
868 }
869 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
870
871 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
872 {
873         u32 max;
874
875         mutex_lock(&dc->lock);
876         tegra_dc_hold_dc_out(dc);
877         max = nvhost_syncpt_incr_max_ext(dc->ndev,
878                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
879         dc->syncpt[i].max = max;
880         tegra_dc_release_dc_out(dc);
881         mutex_unlock(&dc->lock);
882
883         return max;
884 }
885
886 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
887 {
888         mutex_lock(&dc->lock);
889         if (dc->enabled) {
890                 tegra_dc_hold_dc_out(dc);
891                 while (dc->syncpt[i].min < val) {
892                         dc->syncpt[i].min++;
893                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
894                 }
895                 tegra_dc_release_dc_out(dc);
896         }
897         mutex_unlock(&dc->lock);
898 }
899
900 void
901 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
902 {
903         unsigned int ctrl;
904         unsigned long out_sel;
905         unsigned long cmd_state;
906
907         mutex_lock(&dc->lock);
908         if (!dc->enabled) {
909                 mutex_unlock(&dc->lock);
910                 return;
911         }
912
913         tegra_dc_hold_dc_out(dc);
914
915         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
916                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
917                 cfg->clk_select);
918
919         /* The new value should be effected immediately */
920         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
921         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
922
923         switch (cfg->which_pwm) {
924         case TEGRA_PWM_PM0:
925                 /* Select the LM0 on PM0 */
926                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
927                 out_sel &= ~(7 << 0);
928                 out_sel |= (3 << 0);
929                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
930                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
931                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
932                 break;
933         case TEGRA_PWM_PM1:
934                 /* Select the LM1 on PM1 */
935                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
936                 out_sel &= ~(7 << 4);
937                 out_sel |= (3 << 4);
938                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
939                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
940                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
941                 break;
942         default:
943                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
944                 break;
945         }
946         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
947         tegra_dc_release_dc_out(dc);
948         mutex_unlock(&dc->lock);
949 }
950 EXPORT_SYMBOL(tegra_dc_config_pwm);
951
952 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
953                                 const struct tegra_dc_out_pin *pins,
954                                 const unsigned int n_pins)
955 {
956         unsigned int i;
957
958         int name;
959         int pol;
960
961         u32 pol1, pol3;
962
963         u32 set1, unset1;
964         u32 set3, unset3;
965
966         set1 = set3 = unset1 = unset3 = 0;
967
968         for (i = 0; i < n_pins; i++) {
969                 name = (pins + i)->name;
970                 pol  = (pins + i)->pol;
971
972                 /* set polarity by name */
973                 switch (name) {
974                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
975                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
976                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
977                         else
978                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
979                         break;
980                 case TEGRA_DC_OUT_PIN_H_SYNC:
981                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
982                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
983                         else
984                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
985                         break;
986                 case TEGRA_DC_OUT_PIN_V_SYNC:
987                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
988                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
989                         else
990                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
991                         break;
992                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
993                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
994                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
995                         else
996                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
997                         break;
998                 default:
999                         printk("Invalid argument in function %s\n",
1000                                __FUNCTION__);
1001                         break;
1002                 }
1003         }
1004
1005         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1006         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1007
1008         pol1 |= set1;
1009         pol1 &= ~unset1;
1010
1011         pol3 |= set3;
1012         pol3 &= ~unset3;
1013
1014         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1015         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1016 }
1017
1018 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1019 {
1020         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1021                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1022                 dc->out->type == TEGRA_DC_OUT_DSI)
1023                 return override_disp_mode[dc->out->type].pclk ?
1024                         &override_disp_mode[dc->out->type] : NULL;
1025         else
1026                 return NULL;
1027 }
1028
1029 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1030 {
1031         struct tegra_dc_mode *mode;
1032
1033         dc->out = out;
1034         mode = tegra_dc_get_override_mode(dc);
1035
1036         if (mode)
1037                 tegra_dc_set_mode(dc, mode);
1038         else if (out->n_modes > 0)
1039                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1040
1041         switch (out->type) {
1042         case TEGRA_DC_OUT_RGB:
1043                 dc->out_ops = &tegra_dc_rgb_ops;
1044                 break;
1045
1046         case TEGRA_DC_OUT_HDMI:
1047                 dc->out_ops = &tegra_dc_hdmi_ops;
1048                 break;
1049
1050         case TEGRA_DC_OUT_DSI:
1051                 dc->out_ops = &tegra_dc_dsi_ops;
1052                 break;
1053
1054         default:
1055                 dc->out_ops = NULL;
1056                 break;
1057         }
1058
1059         if (dc->out_ops && dc->out_ops->init)
1060                 dc->out_ops->init(dc);
1061
1062 }
1063
1064 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1065 {
1066         if (dc->out)
1067                 return dc->out->height;
1068         else
1069                 return 0;
1070 }
1071 EXPORT_SYMBOL(tegra_dc_get_out_height);
1072
1073 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1074 {
1075         if (dc->out)
1076                 return dc->out->width;
1077         else
1078                 return 0;
1079 }
1080 EXPORT_SYMBOL(tegra_dc_get_out_width);
1081
1082 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1083 {
1084         if (dc->out && dc->out->max_pixclock)
1085                 return dc->out->max_pixclock;
1086         else
1087                 return 0;
1088 }
1089 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1090
1091 void tegra_dc_enable_crc(struct tegra_dc *dc)
1092 {
1093         u32 val;
1094
1095         mutex_lock(&dc->lock);
1096         tegra_dc_hold_dc_out(dc);
1097         tegra_dc_io_start(dc);
1098
1099         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1100                 CRC_ENABLE_ENABLE;
1101         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1102         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1103         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1104         tegra_dc_release_dc_out(dc);
1105         mutex_unlock(&dc->lock);
1106 }
1107
1108 void tegra_dc_disable_crc(struct tegra_dc *dc)
1109 {
1110         mutex_lock(&dc->lock);
1111         tegra_dc_hold_dc_out(dc);
1112         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1113         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1114         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1115
1116         tegra_dc_io_end(dc);
1117         tegra_dc_release_dc_out(dc);
1118         mutex_unlock(&dc->lock);
1119 }
1120
1121 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1122 {
1123         int crc = 0;
1124
1125         if (!dc) {
1126                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1127                 goto crc_error;
1128         }
1129
1130 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1131         /* TODO: Replace mdelay with code to sync VBlANK, since
1132          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1133         mdelay(TEGRA_CRC_LATCHED_DELAY);
1134 #endif
1135
1136         mutex_lock(&dc->lock);
1137         tegra_dc_hold_dc_out(dc);
1138         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1139         tegra_dc_release_dc_out(dc);
1140         mutex_unlock(&dc->lock);
1141 crc_error:
1142         return crc;
1143 }
1144
1145 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1146 {
1147 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1148         u32 val;
1149
1150         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1151         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1152             return true;
1153 #endif
1154         return false;
1155 }
1156
1157 static inline void enable_dc_irq(unsigned int irq)
1158 {
1159 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1160         enable_irq(irq);
1161 #else
1162         /* Always disable DC interrupts on FPGA. */
1163         disable_irq(irq);
1164 #endif
1165 }
1166
1167 static void tegra_dc_vblank(struct work_struct *work)
1168 {
1169         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1170         bool nvsd_updated = false;
1171
1172         mutex_lock(&dc->lock);
1173
1174         if (!dc->enabled) {
1175                 mutex_unlock(&dc->lock);
1176                 return;
1177         }
1178
1179         tegra_dc_hold_dc_out(dc);
1180         /* use the new frame's bandwidth setting instead of max(current, new),
1181          * skip this if we're using tegra_dc_one_shot_worker() */
1182         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1183                 tegra_dc_program_bandwidth(dc, true);
1184
1185         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1186         if (!tegra_dc_windows_are_dirty(dc))
1187                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1188
1189         /* Update the SD brightness */
1190         if (dc->enabled && dc->out->sd_settings) {
1191                 nvsd_updated = nvsd_update_brightness(dc);
1192                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1193                  * V_BLANK_NVSD bit of vblank ref-count. */
1194                 if (nvsd_updated) {
1195                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1196                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1197                 } else {
1198                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1199                 }
1200         }
1201
1202         /* Mask vblank interrupt if ref-count is zero. */
1203         if (!dc->vblank_ref_count)
1204                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1205
1206         tegra_dc_release_dc_out(dc);
1207         mutex_unlock(&dc->lock);
1208
1209         /* Do the actual brightness update outside of the mutex */
1210         if (nvsd_updated && dc->out->sd_settings &&
1211             dc->out->sd_settings->bl_device) {
1212
1213                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1214                 struct backlight_device *bl = platform_get_drvdata(pdev);
1215                 if (bl)
1216                         backlight_update_status(bl);
1217         }
1218 }
1219
1220 static void tegra_dc_one_shot_worker(struct work_struct *work)
1221 {
1222         struct tegra_dc *dc = container_of(
1223                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1224         mutex_lock(&dc->lock);
1225
1226         /* memory client has gone idle */
1227         tegra_dc_clear_bandwidth(dc);
1228
1229         if (dc->out_ops->idle)
1230                 dc->out_ops->idle(dc);
1231
1232         mutex_unlock(&dc->lock);
1233 }
1234
1235 /* return an arbitrarily large number if count overflow occurs.
1236  * make it a nice base-10 number to show up in stats output */
1237 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1238 {
1239         unsigned count = tegra_dc_readl(dc, reg);
1240         tegra_dc_writel(dc, 0, reg);
1241         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1242 }
1243
1244 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1245 {
1246         u32 val;
1247         int i;
1248
1249         dc->stats.underflows++;
1250         if (dc->underflow_mask & WIN_A_UF_INT) {
1251                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1252                         DC_WINBUF_AD_UFLOW_STATUS);
1253                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1254         }
1255         if (dc->underflow_mask & WIN_B_UF_INT) {
1256                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1257                         DC_WINBUF_BD_UFLOW_STATUS);
1258                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1259         }
1260         if (dc->underflow_mask & WIN_C_UF_INT) {
1261                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1262                         DC_WINBUF_CD_UFLOW_STATUS);
1263                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1264         }
1265
1266         /* Check for any underflow reset conditions */
1267         for (i = 0; i < DC_N_WINDOWS; i++) {
1268                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1269                         dc->windows[i].underflows++;
1270
1271 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1272                         if (dc->windows[i].underflows > 4) {
1273                                 schedule_work(&dc->reset_work);
1274                                 /* reset counter */
1275                                 dc->windows[i].underflows = 0;
1276                                 trace_printk("%s:Reset work scheduled for "
1277                                                 "window %c\n",
1278                                                 dc->ndev->name, (65 + i));
1279                         }
1280 #endif
1281 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1282                         if (dc->windows[i].underflows > 4) {
1283                                 trace_printk("%s:window %c in underflow state."
1284                                         " enable UF_LINE_FLUSH to clear up\n",
1285                                         dc->ndev->name, (65 + i));
1286                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1287                                                 DC_DISP_DISP_MISC_CONTROL);
1288                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1289                                                 DC_CMD_STATE_CONTROL);
1290                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1291                                                 DC_CMD_STATE_CONTROL);
1292
1293                                 tegra_dc_writel(dc, 0,
1294                                                 DC_DISP_DISP_MISC_CONTROL);
1295                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1296                                                 DC_CMD_STATE_CONTROL);
1297                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1298                                                 DC_CMD_STATE_CONTROL);
1299                         }
1300 #endif
1301                 } else {
1302                         dc->windows[i].underflows = 0;
1303                 }
1304         }
1305
1306         /* Clear the underflow mask now that we've checked it. */
1307         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1308         dc->underflow_mask = 0;
1309         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1310         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1311         print_underflow_info(dc);
1312 }
1313
1314 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1315 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1316 {
1317         if (status & V_BLANK_INT) {
1318                 /* Sync up windows. */
1319                 tegra_dc_trigger_windows(dc);
1320
1321                 /* Schedule any additional bottom-half vblank actvities. */
1322                 queue_work(system_freezable_wq, &dc->vblank_work);
1323         }
1324
1325         if (status & FRAME_END_INT) {
1326                 /* Mark the frame_end as complete. */
1327                 if (!completion_done(&dc->frame_end_complete))
1328                         complete(&dc->frame_end_complete);
1329         }
1330 }
1331
1332 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1333 {
1334         /* Schedule any additional bottom-half vblank actvities. */
1335         if (status & V_BLANK_INT)
1336                 queue_work(system_freezable_wq, &dc->vblank_work);
1337
1338         if (status & FRAME_END_INT) {
1339                 struct timespec tm = CURRENT_TIME;
1340                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1341                 wake_up(&dc->timestamp_wq);
1342
1343                 /* Mark the frame_end as complete. */
1344                 if (!completion_done(&dc->frame_end_complete))
1345                         complete(&dc->frame_end_complete);
1346
1347                 tegra_dc_trigger_windows(dc);
1348         }
1349 }
1350
1351 /* XXX: Not sure if we limit look ahead to 1 frame */
1352 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1353 {
1354         BUG_ON(!dc->frametime_ns);
1355         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1356 }
1357
1358 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1359 {
1360         BUG_ON(!dc->frametime_ns);
1361         return (((new_ts - old_ts) > dc->frametime_ns)
1362                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1363                         != div_s64((old_ts - dc->frame_end_timestamp),
1364                                 dc->frametime_ns)));
1365 }
1366 #endif
1367
1368 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1369 {
1370 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1371         struct tegra_dc *dc = ptr;
1372         unsigned long status;
1373         unsigned long underflow_mask;
1374         u32 val;
1375
1376         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1377                 WARN(1, "IRQ when DC not powered!\n");
1378                 tegra_dc_io_start(dc);
1379                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1380                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1381                 tegra_dc_io_end(dc);
1382                 return IRQ_HANDLED;
1383         }
1384
1385         /* clear all status flags except underflow, save those for the worker */
1386         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1387         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1388         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1389         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1390
1391         /*
1392          * Overlays can get thier internal state corrupted during and underflow
1393          * condition.  The only way to fix this state is to reset the DC.
1394          * if we get 4 consecutive frames with underflows, assume we're
1395          * hosed and reset.
1396          */
1397         underflow_mask = status & ALL_UF_INT;
1398
1399         /* Check underflow */
1400         if (underflow_mask) {
1401                 dc->underflow_mask |= underflow_mask;
1402                 schedule_delayed_work(&dc->underflow_work,
1403                         msecs_to_jiffies(1));
1404         }
1405
1406         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1407                 tegra_dc_one_shot_irq(dc, status);
1408         else
1409                 tegra_dc_continuous_irq(dc, status);
1410
1411         return IRQ_HANDLED;
1412 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1413         return IRQ_NONE;
1414 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1415 }
1416
1417 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1418 {
1419         u32 color_control;
1420
1421         switch (dc->out->depth) {
1422         case 3:
1423                 color_control = BASE_COLOR_SIZE111;
1424                 break;
1425
1426         case 6:
1427                 color_control = BASE_COLOR_SIZE222;
1428                 break;
1429
1430         case 8:
1431                 color_control = BASE_COLOR_SIZE332;
1432                 break;
1433
1434         case 9:
1435                 color_control = BASE_COLOR_SIZE333;
1436                 break;
1437
1438         case 12:
1439                 color_control = BASE_COLOR_SIZE444;
1440                 break;
1441
1442         case 15:
1443                 color_control = BASE_COLOR_SIZE555;
1444                 break;
1445
1446         case 16:
1447                 color_control = BASE_COLOR_SIZE565;
1448                 break;
1449
1450         case 18:
1451                 color_control = BASE_COLOR_SIZE666;
1452                 break;
1453
1454         default:
1455                 color_control = BASE_COLOR_SIZE888;
1456                 break;
1457         }
1458
1459         switch (dc->out->dither) {
1460         case TEGRA_DC_DISABLE_DITHER:
1461                 color_control |= DITHER_CONTROL_DISABLE;
1462                 break;
1463         case TEGRA_DC_ORDERED_DITHER:
1464                 color_control |= DITHER_CONTROL_ORDERED;
1465                 break;
1466         case TEGRA_DC_ERRDIFF_DITHER:
1467                 /* The line buffer for error-diffusion dither is limited
1468                  * to 1280 pixels per line. This limits the maximum
1469                  * horizontal active area size to 1280 pixels when error
1470                  * diffusion is enabled.
1471                  */
1472                 BUG_ON(dc->mode.h_active > 1280);
1473                 color_control |= DITHER_CONTROL_ERRDIFF;
1474                 break;
1475         }
1476
1477 #ifdef CONFIG_TEGRA_DC_CMU
1478         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
1479                 color_control |= CMU_ENABLE;
1480 #endif
1481
1482         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1483 }
1484
1485 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1486 {
1487         u32 syncpt_id;
1488
1489         switch (dc->ndev->id) {
1490         case 0:
1491                 switch (idx) {
1492                 case 0:
1493                         syncpt_id = NVSYNCPT_DISP0_A;
1494                         break;
1495                 case 1:
1496                         syncpt_id = NVSYNCPT_DISP0_B;
1497                         break;
1498                 case 2:
1499                         syncpt_id = NVSYNCPT_DISP0_C;
1500                         break;
1501                 default:
1502                         BUG();
1503                         break;
1504                 }
1505                 break;
1506         case 1:
1507                 switch (idx) {
1508                 case 0:
1509                         syncpt_id = NVSYNCPT_DISP1_A;
1510                         break;
1511                 case 1:
1512                         syncpt_id = NVSYNCPT_DISP1_B;
1513                         break;
1514                 case 2:
1515                         syncpt_id = NVSYNCPT_DISP1_C;
1516                         break;
1517                 default:
1518                         BUG();
1519                         break;
1520                 }
1521                 break;
1522         default:
1523                 BUG();
1524                 break;
1525         }
1526
1527         return syncpt_id;
1528 }
1529
1530 static int tegra_dc_init(struct tegra_dc *dc)
1531 {
1532         int i;
1533
1534         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1535         if (dc->ndev->id == 0) {
1536                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1537                                       TEGRA_MC_PRIO_MED);
1538                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1539                                       TEGRA_MC_PRIO_MED);
1540                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1541                                       TEGRA_MC_PRIO_MED);
1542                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1543                                       TEGRA_MC_PRIO_MED);
1544                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1545                                       TEGRA_MC_PRIO_HIGH);
1546         } else if (dc->ndev->id == 1) {
1547                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1548                                       TEGRA_MC_PRIO_MED);
1549                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1550                                       TEGRA_MC_PRIO_MED);
1551                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1552                                       TEGRA_MC_PRIO_MED);
1553                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1554                                       TEGRA_MC_PRIO_MED);
1555                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1556                                       TEGRA_MC_PRIO_HIGH);
1557         }
1558         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1559                         DC_CMD_CONT_SYNCPT_VSYNC);
1560         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1561         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1562         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1563         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1564 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1565         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1566 #endif
1567         /* enable interrupts for vblank, frame_end and underflows */
1568         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1569                 DC_CMD_INT_ENABLE);
1570         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1571
1572         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1573
1574         tegra_dc_set_color_control(dc);
1575         for (i = 0; i < DC_N_WINDOWS; i++) {
1576                 struct tegra_dc_win *win = &dc->windows[i];
1577                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1578                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1579                 tegra_dc_set_csc(dc, &win->csc);
1580                 tegra_dc_set_lut(dc, win);
1581                 tegra_dc_set_scaling_filter(dc);
1582         }
1583
1584         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
1585         tegra_dc_set_cmu(dc, &dc->cmu);
1586
1587         for (i = 0; i < dc->n_windows; i++) {
1588                 u32 syncpt = get_syncpt(dc, i);
1589
1590                 dc->syncpt[i].id = syncpt;
1591
1592                 dc->syncpt[i].min = dc->syncpt[i].max =
1593                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1594         }
1595
1596         print_mode_info(dc, dc->mode);
1597
1598         if (dc->mode.pclk)
1599                 if (tegra_dc_program_mode(dc, &dc->mode))
1600                         return -EINVAL;
1601
1602         /* Initialize SD AFTER the modeset.
1603            nvsd_init handles the sd_settings = NULL case. */
1604         nvsd_init(dc, dc->out->sd_settings);
1605
1606         return 0;
1607 }
1608
1609 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1610 {
1611         int failed_init = 0;
1612
1613         if (dc->out->enable)
1614                 dc->out->enable();
1615
1616         tegra_dc_setup_clk(dc, dc->clk);
1617         tegra_dc_clk_enable(dc);
1618
1619         /* do not accept interrupts during initialization */
1620         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1621
1622         enable_dc_irq(dc->irq);
1623
1624         failed_init = tegra_dc_init(dc);
1625         if (failed_init) {
1626                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1627                 disable_irq(dc->irq);
1628                 tegra_dc_clear_bandwidth(dc);
1629                 tegra_dc_clk_disable(dc);
1630                 if (dc->out && dc->out->disable)
1631                         dc->out->disable();
1632                 return false;
1633         }
1634
1635         if (dc->out_ops && dc->out_ops->enable)
1636                 dc->out_ops->enable(dc);
1637
1638         /* force a full blending update */
1639         dc->blend.z[0] = -1;
1640
1641         tegra_dc_ext_enable(dc->ext);
1642
1643         trace_printk("%s:enable\n", dc->ndev->name);
1644
1645         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1646         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1647
1648         if (dc->out->postpoweron)
1649                 dc->out->postpoweron();
1650
1651         return true;
1652 }
1653
1654 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1655 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1656 {
1657         bool ret = true;
1658
1659         if (dc->out->enable)
1660                 dc->out->enable();
1661
1662         tegra_dc_setup_clk(dc, dc->clk);
1663         tegra_dc_clk_enable(dc);
1664
1665         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1666                 mutex_lock(&tegra_dcs[1]->lock);
1667                 disable_irq(tegra_dcs[1]->irq);
1668         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1669                 mutex_lock(&tegra_dcs[0]->lock);
1670                 disable_irq(tegra_dcs[0]->irq);
1671         }
1672
1673         msleep(5);
1674         tegra_periph_reset_assert(dc->clk);
1675         msleep(2);
1676 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1677         tegra_periph_reset_deassert(dc->clk);
1678         msleep(1);
1679 #endif
1680
1681         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1682                 enable_dc_irq(tegra_dcs[1]->irq);
1683                 mutex_unlock(&tegra_dcs[1]->lock);
1684         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1685                 enable_dc_irq(tegra_dcs[0]->irq);
1686                 mutex_unlock(&tegra_dcs[0]->lock);
1687         }
1688
1689         enable_dc_irq(dc->irq);
1690
1691         if (tegra_dc_init(dc)) {
1692                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1693                 ret = false;
1694         }
1695
1696         if (dc->out_ops && dc->out_ops->enable)
1697                 dc->out_ops->enable(dc);
1698
1699         if (dc->out->postpoweron)
1700                 dc->out->postpoweron();
1701
1702         /* force a full blending update */
1703         dc->blend.z[0] = -1;
1704
1705         tegra_dc_ext_enable(dc->ext);
1706
1707         if (!ret) {
1708                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1709                 _tegra_dc_controller_disable(dc);
1710         }
1711
1712         trace_printk("%s:reset enable\n", dc->ndev->name);
1713         return ret;
1714 }
1715 #endif
1716
1717 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1718 {
1719         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1720 }
1721
1722 static bool _tegra_dc_enable(struct tegra_dc *dc)
1723 {
1724         if (dc->mode.pclk == 0) {
1725                 switch (dc->out->type) {
1726                 case TEGRA_DC_OUT_HDMI:
1727                 /* DC enable called but no videomode is loaded.
1728                      Check if HDMI is connected, then set fallback mdoe */
1729                 if (tegra_dc_hpd(dc)) {
1730                         if (_tegra_dc_set_default_videomode(dc))
1731                                 return false;
1732                 } else
1733                         return false;
1734
1735                 break;
1736
1737                 /* Do nothing for other outputs for now */
1738                 case TEGRA_DC_OUT_RGB:
1739
1740                 case TEGRA_DC_OUT_DSI:
1741
1742                 default:
1743                         return false;
1744                 }
1745         }
1746
1747         if (!dc->out)
1748                 return false;
1749
1750         tegra_dc_io_start(dc);
1751
1752         if (!_tegra_dc_controller_enable(dc)) {
1753                 tegra_dc_io_end(dc);
1754                 return false;
1755         }
1756         return true;
1757 }
1758
1759 void tegra_dc_enable(struct tegra_dc *dc)
1760 {
1761         mutex_lock(&dc->lock);
1762
1763         if (!dc->enabled)
1764                 dc->enabled = _tegra_dc_enable(dc);
1765
1766         mutex_unlock(&dc->lock);
1767         print_mode_info(dc, dc->mode);
1768 }
1769
1770 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1771 {
1772         unsigned i;
1773
1774         if (dc->out && dc->out->prepoweroff)
1775                 dc->out->prepoweroff();
1776
1777         if (dc->out_ops && dc->out_ops->disable)
1778                 dc->out_ops->disable(dc);
1779
1780         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1781         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1782         disable_irq(dc->irq);
1783
1784         tegra_dc_clear_bandwidth(dc);
1785         tegra_dc_clk_disable(dc);
1786
1787         if (dc->out && dc->out->disable)
1788                 dc->out->disable();
1789
1790         for (i = 0; i < dc->n_windows; i++) {
1791                 struct tegra_dc_win *w = &dc->windows[i];
1792
1793                 /* reset window bandwidth */
1794                 w->bandwidth = 0;
1795                 w->new_bandwidth = 0;
1796
1797                 /* disable windows */
1798                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1799
1800                 /* flush any pending syncpt waits */
1801                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1802                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1803                                 dc->syncpt[i].id);
1804                         dc->syncpt[i].min++;
1805                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1806                 }
1807         }
1808         trace_printk("%s:disabled\n", dc->ndev->name);
1809 }
1810
1811 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1812 {
1813 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1814         u32 val;
1815         if (dc->enabled)  {
1816                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1817                 if (enable)
1818                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1819                 else
1820                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1821                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1822         }
1823 #endif
1824 }
1825
1826 bool tegra_dc_stats_get(struct tegra_dc *dc)
1827 {
1828 #if 0 /* right now it is always enabled */
1829         u32 val;
1830         bool res;
1831
1832         if (dc->enabled)  {
1833                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1834                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1835         } else {
1836                 res = false;
1837         }
1838
1839         return res;
1840 #endif
1841         return true;
1842 }
1843
1844 /* make the screen blank by disabling all windows */
1845 void tegra_dc_blank(struct tegra_dc *dc)
1846 {
1847         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1848         unsigned i;
1849
1850         for (i = 0; i < DC_N_WINDOWS; i++) {
1851                 dcwins[i] = tegra_dc_get_window(dc, i);
1852                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1853         }
1854
1855         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1856         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1857 }
1858
1859 static void _tegra_dc_disable(struct tegra_dc *dc)
1860 {
1861         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1862                 mutex_lock(&dc->one_shot_lock);
1863                 cancel_delayed_work_sync(&dc->one_shot_work);
1864         }
1865
1866         tegra_dc_hold_dc_out(dc);
1867
1868         _tegra_dc_controller_disable(dc);
1869         tegra_dc_io_end(dc);
1870
1871         tegra_dc_release_dc_out(dc);
1872
1873         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1874                 mutex_unlock(&dc->one_shot_lock);
1875 }
1876
1877 void tegra_dc_disable(struct tegra_dc *dc)
1878 {
1879         tegra_dc_ext_disable(dc->ext);
1880
1881         /* it's important that new underflow work isn't scheduled before the
1882          * lock is acquired. */
1883         cancel_delayed_work_sync(&dc->underflow_work);
1884
1885         mutex_lock(&dc->lock);
1886
1887         if (dc->enabled) {
1888                 dc->enabled = false;
1889
1890                 if (!dc->suspended)
1891                         _tegra_dc_disable(dc);
1892         }
1893
1894 #ifdef CONFIG_SWITCH
1895         switch_set_state(&dc->modeset_switch, 0);
1896 #endif
1897
1898         mutex_unlock(&dc->lock);
1899         print_mode_info(dc, dc->mode);
1900 }
1901
1902 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1903 static void tegra_dc_reset_worker(struct work_struct *work)
1904 {
1905         struct tegra_dc *dc =
1906                 container_of(work, struct tegra_dc, reset_work);
1907
1908         unsigned long val = 0;
1909
1910         mutex_lock(&shared_lock);
1911
1912         dev_warn(&dc->ndev->dev,
1913                 "overlay stuck in underflow state.  resetting.\n");
1914
1915         tegra_dc_ext_disable(dc->ext);
1916
1917         mutex_lock(&dc->lock);
1918
1919         if (dc->enabled == false)
1920                 goto unlock;
1921
1922         dc->enabled = false;
1923
1924         /*
1925          * off host read bus
1926          */
1927         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1928         val &= ~(0x00000100);
1929         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1930
1931         /*
1932          * set DC to STOP mode
1933          */
1934         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1935
1936         msleep(10);
1937
1938         _tegra_dc_controller_disable(dc);
1939
1940         /* _tegra_dc_controller_reset_enable deasserts reset */
1941         _tegra_dc_controller_reset_enable(dc);
1942
1943         dc->enabled = true;
1944
1945         /* reopen host read bus */
1946         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1947         val &= ~(0x00000100);
1948         val |= 0x100;
1949         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1950
1951 unlock:
1952         mutex_unlock(&dc->lock);
1953         mutex_unlock(&shared_lock);
1954         trace_printk("%s:reset complete\n", dc->ndev->name);
1955 }
1956 #endif
1957
1958 static void tegra_dc_underflow_worker(struct work_struct *work)
1959 {
1960         struct tegra_dc *dc = container_of(
1961                 to_delayed_work(work), struct tegra_dc, underflow_work);
1962
1963         mutex_lock(&dc->lock);
1964         tegra_dc_hold_dc_out(dc);
1965
1966         if (dc->enabled) {
1967                 tegra_dc_underflow_handler(dc);
1968         }
1969         tegra_dc_release_dc_out(dc);
1970         mutex_unlock(&dc->lock);
1971 }
1972
1973 #ifdef CONFIG_SWITCH
1974 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1975 {
1976         struct tegra_dc *dc =
1977                 container_of(sdev, struct tegra_dc, modeset_switch);
1978
1979         if (!sdev->state)
1980                 return sprintf(buf, "offline\n");
1981
1982         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1983 }
1984 #endif
1985
1986 static int tegra_dc_probe(struct nvhost_device *ndev,
1987         struct nvhost_device_id *id_table)
1988 {
1989         struct tegra_dc *dc;
1990         struct tegra_dc_mode *mode;
1991         struct clk *clk;
1992         struct clk *emc_clk;
1993         struct resource *res;
1994         struct resource *base_res;
1995         struct resource *fb_mem = NULL;
1996         int ret = 0;
1997         void __iomem *base;
1998         int irq;
1999         int i;
2000
2001         if (!ndev->dev.platform_data) {
2002                 dev_err(&ndev->dev, "no platform data\n");
2003                 return -ENOENT;
2004         }
2005
2006         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2007         if (!dc) {
2008                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2009                 return -ENOMEM;
2010         }
2011
2012         irq = nvhost_get_irq_byname(ndev, "irq");
2013         if (irq <= 0) {
2014                 dev_err(&ndev->dev, "no irq\n");
2015                 ret = -ENOENT;
2016                 goto err_free;
2017         }
2018
2019         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2020         if (!res) {
2021                 dev_err(&ndev->dev, "no mem resource\n");
2022                 ret = -ENOENT;
2023                 goto err_free;
2024         }
2025
2026         base_res = request_mem_region(res->start, resource_size(res),
2027                 ndev->name);
2028         if (!base_res) {
2029                 dev_err(&ndev->dev, "request_mem_region failed\n");
2030                 ret = -EBUSY;
2031                 goto err_free;
2032         }
2033
2034         base = ioremap(res->start, resource_size(res));
2035         if (!base) {
2036                 dev_err(&ndev->dev, "registers can't be mapped\n");
2037                 ret = -EBUSY;
2038                 goto err_release_resource_reg;
2039         }
2040
2041         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2042
2043         clk = clk_get(&ndev->dev, NULL);
2044         if (IS_ERR_OR_NULL(clk)) {
2045                 dev_err(&ndev->dev, "can't get clock\n");
2046                 ret = -ENOENT;
2047                 goto err_iounmap_reg;
2048         }
2049
2050         emc_clk = clk_get(&ndev->dev, "emc");
2051         if (IS_ERR_OR_NULL(emc_clk)) {
2052                 dev_err(&ndev->dev, "can't get emc clock\n");
2053                 ret = -ENOENT;
2054                 goto err_put_clk;
2055         }
2056
2057         dc->clk = clk;
2058         dc->emc_clk = emc_clk;
2059         dc->shift_clk_div = 1;
2060         /* Initialize one shot work delay, it will be assigned by dsi
2061          * according to refresh rate later. */
2062         dc->one_shot_delay_ms = 40;
2063
2064         dc->base_res = base_res;
2065         dc->base = base;
2066         dc->irq = irq;
2067         dc->ndev = ndev;
2068         dc->pdata = ndev->dev.platform_data;
2069
2070         /*
2071          * The emc is a shared clock, it will be set based on
2072          * the requirements for each user on the bus.
2073          */
2074         dc->emc_clk_rate = 0;
2075
2076         mutex_init(&dc->lock);
2077         mutex_init(&dc->one_shot_lock);
2078         init_completion(&dc->frame_end_complete);
2079         init_waitqueue_head(&dc->wq);
2080         init_waitqueue_head(&dc->timestamp_wq);
2081 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2082         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2083 #endif
2084         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2085         dc->vblank_ref_count = 0;
2086         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2087         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2088
2089         tegra_dc_init_lut_defaults(&dc->fb_lut);
2090
2091         dc->n_windows = DC_N_WINDOWS;
2092         for (i = 0; i < dc->n_windows; i++) {
2093                 struct tegra_dc_win *win = &dc->windows[i];
2094                 win->idx = i;
2095                 win->dc = dc;
2096                 tegra_dc_init_csc_defaults(&win->csc);
2097                 tegra_dc_init_lut_defaults(&win->lut);
2098         }
2099
2100         ret = tegra_dc_set(dc, ndev->id);
2101         if (ret < 0) {
2102                 dev_err(&ndev->dev, "can't add dc\n");
2103                 goto err_free_irq;
2104         }
2105
2106         nvhost_set_drvdata(ndev, dc);
2107
2108 #ifdef CONFIG_SWITCH
2109         dc->modeset_switch.name = dev_name(&ndev->dev);
2110         dc->modeset_switch.state = 0;
2111         dc->modeset_switch.print_state = switch_modeset_print_mode;
2112         switch_dev_register(&dc->modeset_switch);
2113 #endif
2114
2115         tegra_dc_feature_register(dc);
2116
2117         if (dc->pdata->default_out)
2118                 tegra_dc_set_out(dc, dc->pdata->default_out);
2119         else
2120                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2121
2122         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2123                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2124
2125         dc->ext = tegra_dc_ext_register(ndev, dc);
2126         if (IS_ERR_OR_NULL(dc->ext)) {
2127                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2128                 dc->ext = NULL;
2129         }
2130
2131         mutex_lock(&dc->lock);
2132         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2133                 dc->enabled = _tegra_dc_enable(dc);
2134         mutex_unlock(&dc->lock);
2135
2136         /* interrupt handler must be registered before tegra_fb_register() */
2137         if (request_irq(irq, tegra_dc_irq, 0,
2138                         dev_name(&ndev->dev), dc)) {
2139                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2140                 ret = -EBUSY;
2141                 goto err_put_emc_clk;
2142         }
2143
2144         tegra_dc_create_debugfs(dc);
2145
2146         dev_info(&ndev->dev, "probed\n");
2147
2148         if (dc->pdata->fb) {
2149                 if (dc->pdata->fb->bits_per_pixel == -1) {
2150                         unsigned long fmt;
2151                         tegra_dc_writel(dc,
2152                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2153                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2154
2155                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2156                         dc->pdata->fb->bits_per_pixel =
2157                                 tegra_dc_fmt_bpp(fmt);
2158                 }
2159
2160                 mode = tegra_dc_get_override_mode(dc);
2161                 if (mode) {
2162                         dc->pdata->fb->xres = mode->h_active;
2163                         dc->pdata->fb->yres = mode->v_active;
2164                 }
2165
2166                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2167                 if (IS_ERR_OR_NULL(dc->fb))
2168                         dc->fb = NULL;
2169         }
2170
2171         if (dc->out && dc->out->hotplug_init)
2172                 dc->out->hotplug_init();
2173
2174         if (dc->out_ops && dc->out_ops->detect)
2175                 dc->out_ops->detect(dc);
2176         else
2177                 dc->connected = true;
2178
2179         tegra_dc_create_sysfs(&dc->ndev->dev);
2180
2181         return 0;
2182
2183 err_free_irq:
2184         free_irq(irq, dc);
2185 err_put_emc_clk:
2186         clk_put(emc_clk);
2187 err_put_clk:
2188         clk_put(clk);
2189 err_iounmap_reg:
2190         iounmap(base);
2191         if (fb_mem)
2192                 release_resource(fb_mem);
2193 err_release_resource_reg:
2194         release_resource(base_res);
2195 err_free:
2196         kfree(dc);
2197
2198         return ret;
2199 }
2200
2201 static int tegra_dc_remove(struct nvhost_device *ndev)
2202 {
2203         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2204
2205         tegra_dc_remove_sysfs(&dc->ndev->dev);
2206         tegra_dc_remove_debugfs(dc);
2207
2208         if (dc->fb) {
2209                 tegra_fb_unregister(dc->fb);
2210                 if (dc->fb_mem)
2211                         release_resource(dc->fb_mem);
2212         }
2213
2214         tegra_dc_ext_disable(dc->ext);
2215
2216         if (dc->ext)
2217                 tegra_dc_ext_unregister(dc->ext);
2218
2219         if (dc->enabled)
2220                 _tegra_dc_disable(dc);
2221
2222 #ifdef CONFIG_SWITCH
2223         switch_dev_unregister(&dc->modeset_switch);
2224 #endif
2225         free_irq(dc->irq, dc);
2226         clk_put(dc->emc_clk);
2227         clk_put(dc->clk);
2228         iounmap(dc->base);
2229         if (dc->fb_mem)
2230                 release_resource(dc->base_res);
2231         kfree(dc);
2232         tegra_dc_set(NULL, ndev->id);
2233         return 0;
2234 }
2235
2236 #ifdef CONFIG_PM
2237 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2238 {
2239         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2240
2241         trace_printk("%s:suspend\n", dc->ndev->name);
2242         dev_info(&ndev->dev, "suspend\n");
2243
2244         tegra_dc_ext_disable(dc->ext);
2245
2246         mutex_lock(&dc->lock);
2247
2248         if (dc->out_ops && dc->out_ops->suspend)
2249                 dc->out_ops->suspend(dc);
2250
2251         if (dc->enabled) {
2252                 _tegra_dc_disable(dc);
2253
2254                 dc->suspended = true;
2255         }
2256
2257         if (dc->out && dc->out->postsuspend) {
2258                 dc->out->postsuspend();
2259                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2260                         /*
2261                          * avoid resume event due to voltage falling
2262                          */
2263                         msleep(100);
2264         }
2265
2266         mutex_unlock(&dc->lock);
2267
2268         return 0;
2269 }
2270
2271 static int tegra_dc_resume(struct nvhost_device *ndev)
2272 {
2273         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2274
2275         trace_printk("%s:resume\n", dc->ndev->name);
2276         dev_info(&ndev->dev, "resume\n");
2277
2278         mutex_lock(&dc->lock);
2279         dc->suspended = false;
2280
2281         if (dc->enabled)
2282                 _tegra_dc_enable(dc);
2283
2284         if (dc->out && dc->out->hotplug_init)
2285                 dc->out->hotplug_init();
2286
2287         if (dc->out_ops && dc->out_ops->resume)
2288                 dc->out_ops->resume(dc);
2289         mutex_unlock(&dc->lock);
2290
2291         return 0;
2292 }
2293
2294 #endif /* CONFIG_PM */
2295
2296 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2297 {
2298         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2299
2300         if (!dc || !dc->enabled)
2301                 return;
2302
2303         tegra_dc_blank(dc);
2304         tegra_dc_disable(dc);
2305 }
2306
2307 extern int suspend_set(const char *val, struct kernel_param *kp)
2308 {
2309         if (!strcmp(val, "dump"))
2310                 dump_regs(tegra_dcs[0]);
2311 #ifdef CONFIG_PM
2312         else if (!strcmp(val, "suspend"))
2313                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2314         else if (!strcmp(val, "resume"))
2315                 tegra_dc_resume(tegra_dcs[0]->ndev);
2316 #endif
2317
2318         return 0;
2319 }
2320
2321 extern int suspend_get(char *buffer, struct kernel_param *kp)
2322 {
2323         return 0;
2324 }
2325
2326 int suspend;
2327
2328 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2329
2330 struct nvhost_driver tegra_dc_driver = {
2331         .driver = {
2332                 .name = "tegradc",
2333                 .owner = THIS_MODULE,
2334         },
2335         .probe = tegra_dc_probe,
2336         .remove = tegra_dc_remove,
2337 #ifdef CONFIG_PM
2338         .suspend = tegra_dc_suspend,
2339         .resume = tegra_dc_resume,
2340 #endif
2341         .shutdown = tegra_dc_shutdown,
2342 };
2343
2344 #ifndef MODULE
2345 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2346 {
2347         int i, params[11];
2348         char *p;
2349
2350         for (i = 0; i < ARRAY_SIZE(params); i++) {
2351                 if ((p = strsep(&options, ",")) != NULL) {
2352                         if (*p)
2353                                 params[i] = simple_strtoul(p, &p, 10);
2354                 } else
2355                         return -EINVAL;
2356         }
2357
2358         if ((mode->pclk = params[0]) == 0)
2359                 return -EINVAL;
2360
2361         mode->h_active      = params[1];
2362         mode->v_active      = params[2];
2363         mode->h_ref_to_sync = params[3];
2364         mode->v_ref_to_sync = params[4];
2365         mode->h_sync_width  = params[5];
2366         mode->v_sync_width  = params[6];
2367         mode->h_back_porch  = params[7];
2368         mode->v_back_porch  = params[8];
2369         mode->h_front_porch = params[9];
2370         mode->v_front_porch = params[10];
2371
2372         return 0;
2373 }
2374
2375 static int __init tegra_dc_mode_override(char *str)
2376 {
2377         char *p = str, *options;
2378
2379         if (!p || !*p)
2380                 return -EINVAL;
2381
2382         p = strstr(str, "hdmi:");
2383         if (p) {
2384                 p += 5;
2385                 options = strsep(&p, ";");
2386                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2387                         return -EINVAL;
2388         }
2389
2390         p = strstr(str, "rgb:");
2391         if (p) {
2392                 p += 4;
2393                 options = strsep(&p, ";");
2394                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2395                         return -EINVAL;
2396         }
2397
2398         p = strstr(str, "dsi:");
2399         if (p) {
2400                 p += 4;
2401                 options = strsep(&p, ";");
2402                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2403                         return -EINVAL;
2404         }
2405
2406         return 0;
2407 }
2408
2409 __setup("disp_params=", tegra_dc_mode_override);
2410 #endif
2411
2412 static int __init tegra_dc_module_init(void)
2413 {
2414         int ret = tegra_dc_ext_module_init();
2415         if (ret)
2416                 return ret;
2417         return nvhost_driver_register(&tegra_dc_driver);
2418 }
2419
2420 static void __exit tegra_dc_module_exit(void)
2421 {
2422         nvhost_driver_unregister(&tegra_dc_driver);
2423         tegra_dc_ext_module_exit();
2424 }
2425
2426 module_exit(tegra_dc_module_exit);
2427 module_init(tegra_dc_module_init);