video: tegra: dc: Powergate DISA & DISB.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
67         .refresh = 60,
68         .xres = 640,
69         .yres = 480,
70         .pixclock = KHZ2PICOS(25200),
71         .hsync_len = 96,        /* h_sync_width */
72         .vsync_len = 2,         /* v_sync_width */
73         .left_margin = 48,      /* h_back_porch */
74         .upper_margin = 33,     /* v_back_porch */
75         .right_margin = 16,     /* h_front_porch */
76         .lower_margin = 10,     /* v_front_porch */
77         .vmode = 0,
78         .sync = 0,
79 };
80
81 static struct tegra_dc_mode override_disp_mode[3];
82
83 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
84
85 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
86
87 DEFINE_MUTEX(tegra_dc_lock);
88 DEFINE_MUTEX(shared_lock);
89
90 static const struct {
91         bool h;
92         bool v;
93 } can_filter[] = {
94         /* Window A has no filtering */
95         { false, false },
96         /* Window B has both H and V filtering */
97         { true,  true  },
98         /* Window C has only H filtering */
99         { false, true  },
100 };
101
102 #ifdef CONFIG_TEGRA_DC_CMU
103 static struct tegra_dc_cmu default_cmu = {
104         /* lut1 maps sRGB to linear space. */
105         {
106                 0,    1,    2,    4,    5,    6,    7,    9,
107                 10,   11,   12,   14,   15,   16,   18,   20,
108                 21,   23,   25,   27,   29,   31,   33,   35,
109                 37,   40,   42,   45,   48,   50,   53,   56,
110                 59,   62,   66,   69,   72,   76,   79,   83,
111                 87,   91,   95,   99,   103,  107,  112,  116,
112                 121,  126,  131,  136,  141,  146,  151,  156,
113                 162,  168,  173,  179,  185,  191,  197,  204,
114                 210,  216,  223,  230,  237,  244,  251,  258,
115                 265,  273,  280,  288,  296,  304,  312,  320,
116                 329,  337,  346,  354,  363,  372,  381,  390,
117                 400,  409,  419,  428,  438,  448,  458,  469,
118                 479,  490,  500,  511,  522,  533,  544,  555,
119                 567,  578,  590,  602,  614,  626,  639,  651,
120                 664,  676,  689,  702,  715,  728,  742,  755,
121                 769,  783,  797,  811,  825,  840,  854,  869,
122                 884,  899,  914,  929,  945,  960,  976,  992,
123                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
124                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
125                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
126                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
127                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
128                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
129                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
130                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
131                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
132                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
133                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
134                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
135                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
136                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
137                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
138         },
139         /* csc */
140         {
141                 0x100, 0x0,   0x0,
142                 0x0,   0x100, 0x0,
143                 0x0,   0x0,   0x100,
144         },
145         /* lut2 maps linear space to sRGB*/
146         {
147                 0,    1,    2,    2,    3,    4,    5,    6,
148                 6,    7,    8,    9,    10,   10,   11,   12,
149                 13,   13,   14,   15,   15,   16,   16,   17,
150                 18,   18,   19,   19,   20,   20,   21,   21,
151                 22,   22,   23,   23,   23,   24,   24,   25,
152                 25,   25,   26,   26,   27,   27,   27,   28,
153                 28,   29,   29,   29,   30,   30,   30,   31,
154                 31,   31,   32,   32,   32,   33,   33,   33,
155                 34,   34,   34,   34,   35,   35,   35,   36,
156                 36,   36,   37,   37,   37,   37,   38,   38,
157                 38,   38,   39,   39,   39,   40,   40,   40,
158                 40,   41,   41,   41,   41,   42,   42,   42,
159                 42,   43,   43,   43,   43,   43,   44,   44,
160                 44,   44,   45,   45,   45,   45,   46,   46,
161                 46,   46,   46,   47,   47,   47,   47,   48,
162                 48,   48,   48,   48,   49,   49,   49,   49,
163                 49,   50,   50,   50,   50,   50,   51,   51,
164                 51,   51,   51,   52,   52,   52,   52,   52,
165                 53,   53,   53,   53,   53,   54,   54,   54,
166                 54,   54,   55,   55,   55,   55,   55,   55,
167                 56,   56,   56,   56,   56,   57,   57,   57,
168                 57,   57,   57,   58,   58,   58,   58,   58,
169                 58,   59,   59,   59,   59,   59,   59,   60,
170                 60,   60,   60,   60,   60,   61,   61,   61,
171                 61,   61,   61,   62,   62,   62,   62,   62,
172                 62,   63,   63,   63,   63,   63,   63,   64,
173                 64,   64,   64,   64,   64,   64,   65,   65,
174                 65,   65,   65,   65,   66,   66,   66,   66,
175                 66,   66,   66,   67,   67,   67,   67,   67,
176                 67,   67,   68,   68,   68,   68,   68,   68,
177                 68,   69,   69,   69,   69,   69,   69,   69,
178                 70,   70,   70,   70,   70,   70,   70,   71,
179                 71,   71,   71,   71,   71,   71,   72,   72,
180                 72,   72,   72,   72,   72,   72,   73,   73,
181                 73,   73,   73,   73,   73,   74,   74,   74,
182                 74,   74,   74,   74,   74,   75,   75,   75,
183                 75,   75,   75,   75,   75,   76,   76,   76,
184                 76,   76,   76,   76,   77,   77,   77,   77,
185                 77,   77,   77,   77,   78,   78,   78,   78,
186                 78,   78,   78,   78,   78,   79,   79,   79,
187                 79,   79,   79,   79,   79,   80,   80,   80,
188                 80,   80,   80,   80,   80,   81,   81,   81,
189                 81,   81,   81,   81,   81,   81,   82,   82,
190                 82,   82,   82,   82,   82,   82,   83,   83,
191                 83,   83,   83,   83,   83,   83,   83,   84,
192                 84,   84,   84,   84,   84,   84,   84,   84,
193                 85,   85,   85,   85,   85,   85,   85,   85,
194                 85,   86,   86,   86,   86,   86,   86,   86,
195                 86,   86,   87,   87,   87,   87,   87,   87,
196                 87,   87,   87,   88,   88,   88,   88,   88,
197                 88,   88,   88,   88,   88,   89,   89,   89,
198                 89,   89,   89,   89,   89,   89,   90,   90,
199                 90,   90,   90,   90,   90,   90,   90,   90,
200                 91,   91,   91,   91,   91,   91,   91,   91,
201                 91,   91,   92,   92,   92,   92,   92,   92,
202                 92,   92,   92,   92,   93,   93,   93,   93,
203                 93,   93,   93,   93,   93,   93,   94,   94,
204                 94,   94,   94,   94,   94,   94,   94,   94,
205                 95,   95,   95,   95,   95,   95,   95,   95,
206                 95,   95,   96,   96,   96,   96,   96,   96,
207                 96,   96,   96,   96,   96,   97,   97,   97,
208                 97,   97,   97,   97,   97,   97,   97,   98,
209                 98,   98,   98,   98,   98,   98,   98,   98,
210                 98,   98,   99,   99,   99,   99,   99,   99,
211                 99,   100,  101,  101,  102,  103,  103,  104,
212                 105,  105,  106,  107,  107,  108,  109,  109,
213                 110,  111,  111,  112,  113,  113,  114,  115,
214                 115,  116,  116,  117,  118,  118,  119,  119,
215                 120,  120,  121,  122,  122,  123,  123,  124,
216                 124,  125,  126,  126,  127,  127,  128,  128,
217                 129,  129,  130,  130,  131,  131,  132,  132,
218                 133,  133,  134,  134,  135,  135,  136,  136,
219                 137,  137,  138,  138,  139,  139,  140,  140,
220                 141,  141,  142,  142,  143,  143,  144,  144,
221                 145,  145,  145,  146,  146,  147,  147,  148,
222                 148,  149,  149,  150,  150,  150,  151,  151,
223                 152,  152,  153,  153,  153,  154,  154,  155,
224                 155,  156,  156,  156,  157,  157,  158,  158,
225                 158,  159,  159,  160,  160,  160,  161,  161,
226                 162,  162,  162,  163,  163,  164,  164,  164,
227                 165,  165,  166,  166,  166,  167,  167,  167,
228                 168,  168,  169,  169,  169,  170,  170,  170,
229                 171,  171,  172,  172,  172,  173,  173,  173,
230                 174,  174,  174,  175,  175,  176,  176,  176,
231                 177,  177,  177,  178,  178,  178,  179,  179,
232                 179,  180,  180,  180,  181,  181,  182,  182,
233                 182,  183,  183,  183,  184,  184,  184,  185,
234                 185,  185,  186,  186,  186,  187,  187,  187,
235                 188,  188,  188,  189,  189,  189,  189,  190,
236                 190,  190,  191,  191,  191,  192,  192,  192,
237                 193,  193,  193,  194,  194,  194,  195,  195,
238                 195,  196,  196,  196,  196,  197,  197,  197,
239                 198,  198,  198,  199,  199,  199,  200,  200,
240                 200,  200,  201,  201,  201,  202,  202,  202,
241                 202,  203,  203,  203,  204,  204,  204,  205,
242                 205,  205,  205,  206,  206,  206,  207,  207,
243                 207,  207,  208,  208,  208,  209,  209,  209,
244                 209,  210,  210,  210,  211,  211,  211,  211,
245                 212,  212,  212,  213,  213,  213,  213,  214,
246                 214,  214,  214,  215,  215,  215,  216,  216,
247                 216,  216,  217,  217,  217,  217,  218,  218,
248                 218,  219,  219,  219,  219,  220,  220,  220,
249                 220,  221,  221,  221,  221,  222,  222,  222,
250                 223,  223,  223,  223,  224,  224,  224,  224,
251                 225,  225,  225,  225,  226,  226,  226,  226,
252                 227,  227,  227,  227,  228,  228,  228,  228,
253                 229,  229,  229,  229,  230,  230,  230,  230,
254                 231,  231,  231,  231,  232,  232,  232,  232,
255                 233,  233,  233,  233,  234,  234,  234,  234,
256                 235,  235,  235,  235,  236,  236,  236,  236,
257                 237,  237,  237,  237,  238,  238,  238,  238,
258                 239,  239,  239,  239,  240,  240,  240,  240,
259                 240,  241,  241,  241,  241,  242,  242,  242,
260                 242,  243,  243,  243,  243,  244,  244,  244,
261                 244,  244,  245,  245,  245,  245,  246,  246,
262                 246,  246,  247,  247,  247,  247,  247,  248,
263                 248,  248,  248,  249,  249,  249,  249,  249,
264                 250,  250,  250,  250,  251,  251,  251,  251,
265                 251,  252,  252,  252,  252,  253,  253,  253,
266                 253,  253,  254,  254,  254,  254,  255,  255,
267         },
268 };
269 #endif
270
271 void tegra_dc_clk_enable(struct tegra_dc *dc)
272 {
273         if (!tegra_is_clk_enabled(dc->clk)) {
274                 clk_prepare_enable(dc->clk);
275                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
276         }
277 }
278
279 void tegra_dc_clk_disable(struct tegra_dc *dc)
280 {
281         if (tegra_is_clk_enabled(dc->clk)) {
282                 clk_disable_unprepare(dc->clk);
283                 tegra_dvfs_set_rate(dc->clk, 0);
284         }
285 }
286
287 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
288 {
289         if (dc->out_ops->hold)
290                 dc->out_ops->hold(dc);
291 }
292
293 void tegra_dc_release_dc_out(struct tegra_dc *dc)
294 {
295         if (dc->out_ops->release)
296                 dc->out_ops->release(dc);
297 }
298
299 #define DUMP_REG(a) do {                        \
300         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
301                  #a, a, tegra_dc_readl(dc, a));               \
302         print(data, buff);                                    \
303         } while (0)
304
305 static void _dump_regs(struct tegra_dc *dc, void *data,
306                        void (* print)(void *data, const char *str))
307 {
308         int i;
309         char buff[256];
310
311         mutex_lock(&dc->lock);
312         tegra_dc_io_start(dc);
313         tegra_dc_hold_dc_out(dc);
314
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
316         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE);
318         DUMP_REG(DC_CMD_INT_STATUS);
319         DUMP_REG(DC_CMD_INT_MASK);
320         DUMP_REG(DC_CMD_INT_ENABLE);
321         DUMP_REG(DC_CMD_INT_TYPE);
322         DUMP_REG(DC_CMD_INT_POLARITY);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
326         DUMP_REG(DC_CMD_STATE_ACCESS);
327         DUMP_REG(DC_CMD_STATE_CONTROL);
328         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
329         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
330
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
332         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
333         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
335         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
336         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
337         DUMP_REG(DC_DISP_REF_TO_SYNC);
338         DUMP_REG(DC_DISP_SYNC_WIDTH);
339         DUMP_REG(DC_DISP_BACK_PORCH);
340         DUMP_REG(DC_DISP_DISP_ACTIVE);
341         DUMP_REG(DC_DISP_FRONT_PORCH);
342         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
347         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
352         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
357         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
360         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
361         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
364         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
365         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
369         DUMP_REG(DC_DISP_M0_CONTROL);
370         DUMP_REG(DC_DISP_M1_CONTROL);
371         DUMP_REG(DC_DISP_DI_CONTROL);
372         DUMP_REG(DC_DISP_PP_CONTROL);
373         DUMP_REG(DC_DISP_PP_SELECT_A);
374         DUMP_REG(DC_DISP_PP_SELECT_B);
375         DUMP_REG(DC_DISP_PP_SELECT_C);
376         DUMP_REG(DC_DISP_PP_SELECT_D);
377         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
378         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
379         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
380         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
381         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
382         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
383         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
384         DUMP_REG(DC_DISP_BORDER_COLOR);
385         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
386         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
388         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
389         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
390         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
392         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
393         DUMP_REG(DC_DISP_CURSOR_POSITION);
394         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
395         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
400         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
404 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
406 #endif
407         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
408         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
409
410
411         for (i = 0; i < 3; i++) {
412                 print(data, "\n");
413                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
414                 print(data, buff);
415
416                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
417                                 DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
419                 DUMP_REG(DC_WIN_WIN_OPTIONS);
420                 DUMP_REG(DC_WIN_BYTE_SWAP);
421                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
422                 DUMP_REG(DC_WIN_COLOR_DEPTH);
423                 DUMP_REG(DC_WIN_POSITION);
424                 DUMP_REG(DC_WIN_SIZE);
425                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
426                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
428                 DUMP_REG(DC_WIN_DDA_INCREMENT);
429                 DUMP_REG(DC_WIN_LINE_STRIDE);
430 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
431                 DUMP_REG(DC_WIN_BUF_STRIDE);
432                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
433 #endif
434                 DUMP_REG(DC_WIN_BLEND_NOKEY);
435                 DUMP_REG(DC_WIN_BLEND_1WIN);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
437                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
438                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
439                 DUMP_REG(DC_WINBUF_START_ADDR);
440                 DUMP_REG(DC_WINBUF_START_ADDR_U);
441                 DUMP_REG(DC_WINBUF_START_ADDR_V);
442                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
443                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
444                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
445                 DUMP_REG(DC_WIN_CSC_YOF);
446                 DUMP_REG(DC_WIN_CSC_KYRGB);
447                 DUMP_REG(DC_WIN_CSC_KUR);
448                 DUMP_REG(DC_WIN_CSC_KVR);
449                 DUMP_REG(DC_WIN_CSC_KUG);
450                 DUMP_REG(DC_WIN_CSC_KVG);
451                 DUMP_REG(DC_WIN_CSC_KUB);
452                 DUMP_REG(DC_WIN_CSC_KVB);
453         }
454
455         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
456         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
458         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
459         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
461         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
462         DUMP_REG(DC_DISP_M1_CONTROL);
463         DUMP_REG(DC_COM_PM1_CONTROL);
464         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
465         DUMP_REG(DC_DISP_SD_CONTROL);
466
467         tegra_dc_release_dc_out(dc);
468         tegra_dc_io_end(dc);
469         mutex_unlock(&dc->lock);
470 }
471
472 #undef DUMP_REG
473
474 #ifdef DEBUG
475 static void dump_regs_print(void *data, const char *str)
476 {
477         struct tegra_dc *dc = data;
478         dev_dbg(&dc->ndev->dev, "%s", str);
479 }
480
481 static void dump_regs(struct tegra_dc *dc)
482 {
483         _dump_regs(dc, dc, dump_regs_print);
484 }
485 #else /* !DEBUG */
486
487 static void dump_regs(struct tegra_dc *dc) {}
488
489 #endif /* DEBUG */
490
491 #ifdef CONFIG_DEBUG_FS
492
493 static void dbg_regs_print(void *data, const char *str)
494 {
495         struct seq_file *s = data;
496
497         seq_printf(s, "%s", str);
498 }
499
500 #undef DUMP_REG
501
502 static int dbg_dc_show(struct seq_file *s, void *unused)
503 {
504         struct tegra_dc *dc = s->private;
505
506         _dump_regs(dc, s, dbg_regs_print);
507
508         return 0;
509 }
510
511
512 static int dbg_dc_open(struct inode *inode, struct file *file)
513 {
514         return single_open(file, dbg_dc_show, inode->i_private);
515 }
516
517 static const struct file_operations regs_fops = {
518         .open           = dbg_dc_open,
519         .read           = seq_read,
520         .llseek         = seq_lseek,
521         .release        = single_release,
522 };
523
524 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
525 {
526         struct tegra_dc *dc = s->private;
527         struct tegra_dc_mode *m;
528
529         mutex_lock(&dc->lock);
530         m = &dc->mode;
531         seq_printf(s,
532                 "pclk: %d\n"
533                 "h_ref_to_sync: %d\n"
534                 "v_ref_to_sync: %d\n"
535                 "h_sync_width: %d\n"
536                 "v_sync_width: %d\n"
537                 "h_back_porch: %d\n"
538                 "v_back_porch: %d\n"
539                 "h_active: %d\n"
540                 "v_active: %d\n"
541                 "h_front_porch: %d\n"
542                 "v_front_porch: %d\n"
543                 "stereo_mode: %d\n",
544                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
545                 m->h_sync_width, m->v_sync_width,
546                 m->h_back_porch, m->v_back_porch,
547                 m->h_active, m->v_active,
548                 m->h_front_porch, m->v_front_porch,
549                 m->stereo_mode);
550         mutex_unlock(&dc->lock);
551         return 0;
552 }
553
554 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
555 {
556         return single_open(file, dbg_dc_mode_show, inode->i_private);
557 }
558
559 static const struct file_operations mode_fops = {
560         .open           = dbg_dc_mode_open,
561         .read           = seq_read,
562         .llseek         = seq_lseek,
563         .release        = single_release,
564 };
565
566 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
567 {
568         struct tegra_dc *dc = s->private;
569
570         mutex_lock(&dc->lock);
571         seq_printf(s,
572                 "underflows: %llu\n"
573                 "underflows_a: %llu\n"
574                 "underflows_b: %llu\n"
575                 "underflows_c: %llu\n",
576                 dc->stats.underflows,
577                 dc->stats.underflows_a,
578                 dc->stats.underflows_b,
579                 dc->stats.underflows_c);
580         mutex_unlock(&dc->lock);
581
582         return 0;
583 }
584
585 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
586 {
587         return single_open(file, dbg_dc_stats_show, inode->i_private);
588 }
589
590 static const struct file_operations stats_fops = {
591         .open           = dbg_dc_stats_open,
592         .read           = seq_read,
593         .llseek         = seq_lseek,
594         .release        = single_release,
595 };
596
597 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
598 {
599         if (dc->debugdir)
600                 debugfs_remove_recursive(dc->debugdir);
601         dc->debugdir = NULL;
602 }
603
604 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
605 {
606         struct dentry *retval;
607
608         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
609         if (!dc->debugdir)
610                 goto remove_out;
611
612         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
613                 &regs_fops);
614         if (!retval)
615                 goto remove_out;
616
617         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
618                 &mode_fops);
619         if (!retval)
620                 goto remove_out;
621
622         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
623                 &stats_fops);
624         if (!retval)
625                 goto remove_out;
626
627         return;
628 remove_out:
629         dev_err(&dc->ndev->dev, "could not create debugfs\n");
630         tegra_dc_remove_debugfs(dc);
631 }
632
633 #else /* !CONFIG_DEBUGFS */
634 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
635 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
636 #endif /* CONFIG_DEBUGFS */
637
638 static int tegra_dc_set(struct tegra_dc *dc, int index)
639 {
640         int ret = 0;
641
642         mutex_lock(&tegra_dc_lock);
643         if (index >= TEGRA_MAX_DC) {
644                 ret = -EINVAL;
645                 goto out;
646         }
647
648         if (dc != NULL && tegra_dcs[index] != NULL) {
649                 ret = -EBUSY;
650                 goto out;
651         }
652
653         tegra_dcs[index] = dc;
654
655 out:
656         mutex_unlock(&tegra_dc_lock);
657
658         return ret;
659 }
660
661 unsigned int tegra_dc_has_multiple_dc(void)
662 {
663         unsigned int idx;
664         unsigned int cnt = 0;
665         struct tegra_dc *dc;
666
667         mutex_lock(&tegra_dc_lock);
668         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
669                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
670         mutex_unlock(&tegra_dc_lock);
671
672         return (cnt > 1);
673 }
674
675 /* get the stride size of a window.
676  * return: stride size in bytes for window win. or 0 if unavailble. */
677 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
678 {
679         u32 stride;
680
681         if (!dc->enabled)
682                 return 0;
683         BUG_ON(win > DC_N_WINDOWS);
684         mutex_lock(&dc->lock);
685         tegra_dc_io_start(dc);
686         tegra_dc_hold_dc_out(dc);
687         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
688                 DC_CMD_DISPLAY_WINDOW_HEADER);
689         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
690         tegra_dc_release_dc_out(dc);
691         tegra_dc_io_end(dc);
692         mutex_unlock(&dc->lock);
693         return GET_LINE_STRIDE(stride);
694 }
695 EXPORT_SYMBOL(tegra_dc_get_stride);
696
697 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
698 {
699         if (idx < TEGRA_MAX_DC)
700                 return tegra_dcs[idx];
701         else
702                 return NULL;
703 }
704 EXPORT_SYMBOL(tegra_dc_get_dc);
705
706 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
707 {
708         if (win >= dc->n_windows)
709                 return NULL;
710
711         return &dc->windows[win];
712 }
713 EXPORT_SYMBOL(tegra_dc_get_window);
714
715 bool tegra_dc_get_connected(struct tegra_dc *dc)
716 {
717         return dc->connected;
718 }
719 EXPORT_SYMBOL(tegra_dc_get_connected);
720
721 bool tegra_dc_hpd(struct tegra_dc *dc)
722 {
723         int sense;
724         int level;
725
726         level = gpio_get_value(dc->out->hotplug_gpio);
727
728         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
729
730         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
731                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
732 }
733 EXPORT_SYMBOL(tegra_dc_hpd);
734
735 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
736 {
737         unsigned i;
738         unsigned v0 = 128;
739         unsigned v1 = 0;
740
741         /* linear horizontal and vertical filters */
742         for (i = 0; i < 16; i++) {
743                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
744                                 DC_WIN_H_FILTER_P(i));
745
746                 tegra_dc_writel(dc, v0,
747                                 DC_WIN_V_FILTER_P(i));
748                 v0 -= 8;
749                 v1 += 8;
750         }
751 }
752
753 #ifdef CONFIG_TEGRA_DC_CMU
754 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
755                                         struct tegra_dc_cmu *src_cmu)
756 {
757         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
758 }
759
760 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
761 {
762         u32 val;
763         u32 i;
764
765         for (i = 0; i < 256; i++) {
766                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
767                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
768         }
769
770         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
771         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
772         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
773         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
774         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
775         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
776         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
777         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
778         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
779
780         for (i = 0; i < 960; i++) {
781                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
782                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
783         }
784 }
785
786 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
787 {
788         u32 val;
789         u32 i;
790         bool flags;
791
792         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
793         if (val & CMU_ENABLE)
794                 flags = true;
795
796         val &= ~CMU_ENABLE;
797         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
798         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
799         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
800
801         /*TODO: Sync up with frame end */
802         mdelay(20);
803
804         for (i = 0; i < 256; i++) {
805                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
806                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
807                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
808                 cmu->lut1[i] = LUT1_READ_DATA(val);
809         }
810
811         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
812         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
813         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
814         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
815         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
816         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
817         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
818         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
819         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
820
821         for (i = 0; i < 960; i++) {
822                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
823                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
824                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
825                 cmu->lut2[i] = LUT2_READ_DATA(val);
826         }
827 }
828 EXPORT_SYMBOL(tegra_dc_get_cmu);
829
830 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
831 {
832         u32 val;
833
834         if (dc->pdata->cmu_enable) {
835                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
836         } else {
837                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
838                 return 0;
839         }
840
841         if (cmu != &dc->cmu) {
842                 tegra_dc_cache_cmu(&dc->cmu, cmu);
843
844                 /* Disable CMU */
845                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
846                 if (val & CMU_ENABLE) {
847                         val &= ~CMU_ENABLE;
848                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
849                         val = GENERAL_UPDATE;
850                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
851                         val = GENERAL_ACT_REQ;
852                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
853                         /*TODO: Sync up with vsync */
854                         mdelay(20);
855                 }
856
857                 tegra_dc_set_cmu(dc, &dc->cmu);
858         }
859
860         return 0;
861 }
862 EXPORT_SYMBOL(tegra_dc_update_cmu);
863
864 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
865 {
866         clk_enable(dc->clk);
867         tegra_dc_io_start(dc);
868         dc->pdata->cmu_enable = cmu_enable;
869         tegra_dc_update_cmu(dc, &dc->cmu);
870         tegra_dc_set_color_control(dc);
871         tegra_dc_io_end(dc);
872         clk_disable(dc->clk);
873 }
874 #else
875 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
876 #define tegra_dc_set_cmu(dc, cmu)
877 #define tegra_dc_update_cmu(dc, cmu)
878 #endif
879
880 /* disable_irq() blocks until handler completes, calling this function while
881  * holding dc->lock can deadlock. */
882 static inline void disable_dc_irq(const struct tegra_dc *dc)
883 {
884         disable_irq(dc->irq);
885 }
886
887 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
888 {
889         return dc->syncpt[i].id;
890 }
891 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
892
893 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
894 {
895         u32 max;
896
897         mutex_lock(&dc->lock);
898         tegra_dc_io_start(dc);
899         tegra_dc_hold_dc_out(dc);
900         max = nvhost_syncpt_incr_max_ext(dc->ndev,
901                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
902         dc->syncpt[i].max = max;
903         tegra_dc_release_dc_out(dc);
904         tegra_dc_io_end(dc);
905         mutex_unlock(&dc->lock);
906
907         return max;
908 }
909
910 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
911 {
912         mutex_lock(&dc->lock);
913         if (dc->enabled) {
914                 tegra_dc_io_start(dc);
915                 tegra_dc_hold_dc_out(dc);
916                 while (dc->syncpt[i].min < val) {
917                         dc->syncpt[i].min++;
918                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
919                 }
920                 tegra_dc_release_dc_out(dc);
921                 tegra_dc_io_end(dc);
922         }
923         mutex_unlock(&dc->lock);
924 }
925
926 void
927 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
928 {
929         unsigned int ctrl;
930         unsigned long out_sel;
931         unsigned long cmd_state;
932
933         mutex_lock(&dc->lock);
934         if (!dc->enabled) {
935                 mutex_unlock(&dc->lock);
936                 return;
937         }
938
939         tegra_dc_io_start(dc);
940         tegra_dc_hold_dc_out(dc);
941
942         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
943                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
944                 cfg->clk_select);
945
946         /* The new value should be effected immediately */
947         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
948         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
949
950         switch (cfg->which_pwm) {
951         case TEGRA_PWM_PM0:
952                 /* Select the LM0 on PM0 */
953                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
954                 out_sel &= ~(7 << 0);
955                 out_sel |= (3 << 0);
956                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
957                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
958                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
959                 break;
960         case TEGRA_PWM_PM1:
961                 /* Select the LM1 on PM1 */
962                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
963                 out_sel &= ~(7 << 4);
964                 out_sel |= (3 << 4);
965                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
966                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
967                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
968                 break;
969         default:
970                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
971                 break;
972         }
973         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
974         tegra_dc_release_dc_out(dc);
975         tegra_dc_io_end(dc);
976         mutex_unlock(&dc->lock);
977 }
978 EXPORT_SYMBOL(tegra_dc_config_pwm);
979
980 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
981                                 const struct tegra_dc_out_pin *pins,
982                                 const unsigned int n_pins)
983 {
984         unsigned int i;
985
986         int name;
987         int pol;
988
989         u32 pol1, pol3;
990
991         u32 set1, unset1;
992         u32 set3, unset3;
993
994         set1 = set3 = unset1 = unset3 = 0;
995
996         for (i = 0; i < n_pins; i++) {
997                 name = (pins + i)->name;
998                 pol  = (pins + i)->pol;
999
1000                 /* set polarity by name */
1001                 switch (name) {
1002                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1003                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1004                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1005                         else
1006                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1007                         break;
1008                 case TEGRA_DC_OUT_PIN_H_SYNC:
1009                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1010                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1011                         else
1012                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1013                         break;
1014                 case TEGRA_DC_OUT_PIN_V_SYNC:
1015                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1016                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1017                         else
1018                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1019                         break;
1020                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1021                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1022                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1023                         else
1024                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1025                         break;
1026                 default:
1027                         printk("Invalid argument in function %s\n",
1028                                __FUNCTION__);
1029                         break;
1030                 }
1031         }
1032
1033         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1034         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1035
1036         pol1 |= set1;
1037         pol1 &= ~unset1;
1038
1039         pol3 |= set3;
1040         pol3 &= ~unset3;
1041
1042         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1043         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1044 }
1045
1046 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1047 {
1048         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1049                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1050                 dc->out->type == TEGRA_DC_OUT_DSI)
1051                 return override_disp_mode[dc->out->type].pclk ?
1052                         &override_disp_mode[dc->out->type] : NULL;
1053         else
1054                 return NULL;
1055 }
1056
1057 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1058 {
1059         struct tegra_dc_mode *mode;
1060
1061         dc->out = out;
1062         mode = tegra_dc_get_override_mode(dc);
1063
1064         if (mode)
1065                 tegra_dc_set_mode(dc, mode);
1066         else if (out->n_modes > 0)
1067                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1068
1069         switch (out->type) {
1070         case TEGRA_DC_OUT_RGB:
1071                 dc->out_ops = &tegra_dc_rgb_ops;
1072                 break;
1073
1074         case TEGRA_DC_OUT_HDMI:
1075                 dc->out_ops = &tegra_dc_hdmi_ops;
1076                 break;
1077
1078         case TEGRA_DC_OUT_DSI:
1079                 dc->out_ops = &tegra_dc_dsi_ops;
1080                 break;
1081
1082         default:
1083                 dc->out_ops = NULL;
1084                 break;
1085         }
1086
1087 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1088         if (out->type == TEGRA_DC_OUT_HDMI)
1089                 dc->powergate_id = TEGRA_POWERGATE_DISB;
1090         else
1091                 dc->powergate_id = TEGRA_POWERGATE_DISA;
1092 #endif
1093
1094         if (dc->out_ops && dc->out_ops->init)
1095                 dc->out_ops->init(dc);
1096 }
1097
1098 /* returns on error: -EINVAL
1099  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1100 int tegra_dc_get_out(const struct tegra_dc *dc)
1101 {
1102         if (dc && dc->out)
1103                 return dc->out->type;
1104         return -EINVAL;
1105 }
1106
1107 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1108 {
1109         if (dc->out)
1110                 return dc->out->height;
1111         else
1112                 return 0;
1113 }
1114 EXPORT_SYMBOL(tegra_dc_get_out_height);
1115
1116 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1117 {
1118         if (dc->out)
1119                 return dc->out->width;
1120         else
1121                 return 0;
1122 }
1123 EXPORT_SYMBOL(tegra_dc_get_out_width);
1124
1125 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1126 {
1127         if (dc->out && dc->out->max_pixclock)
1128                 return dc->out->max_pixclock;
1129         else
1130                 return 0;
1131 }
1132 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1133
1134 void tegra_dc_enable_crc(struct tegra_dc *dc)
1135 {
1136         u32 val;
1137
1138         mutex_lock(&dc->lock);
1139         tegra_dc_io_start(dc);
1140         tegra_dc_hold_dc_out(dc);
1141
1142         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1143                 CRC_ENABLE_ENABLE;
1144         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1145         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1146         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1147         tegra_dc_release_dc_out(dc);
1148         tegra_dc_io_end(dc);
1149         mutex_unlock(&dc->lock);
1150 }
1151
1152 void tegra_dc_disable_crc(struct tegra_dc *dc)
1153 {
1154         mutex_lock(&dc->lock);
1155         tegra_dc_io_start(dc);
1156         tegra_dc_hold_dc_out(dc);
1157         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1158         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1159         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1160
1161         tegra_dc_release_dc_out(dc);
1162         tegra_dc_io_end(dc);
1163         mutex_unlock(&dc->lock);
1164 }
1165
1166 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1167 {
1168         int crc = 0;
1169
1170         if (!dc) {
1171                 pr_err("Failed to get dc: NULL parameter.\n");
1172                 goto crc_error;
1173         }
1174
1175 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1176         /* TODO: Replace mdelay with code to sync VBlANK, since
1177          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1178         mdelay(TEGRA_CRC_LATCHED_DELAY);
1179 #endif
1180
1181         mutex_lock(&dc->lock);
1182         tegra_dc_io_start(dc);
1183         tegra_dc_hold_dc_out(dc);
1184         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1185         tegra_dc_release_dc_out(dc);
1186         tegra_dc_io_end(dc);
1187         mutex_unlock(&dc->lock);
1188 crc_error:
1189         return crc;
1190 }
1191
1192 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1193 {
1194 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1195         u32 val;
1196
1197         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1198         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1199             return true;
1200 #endif
1201         return false;
1202 }
1203
1204 static inline void enable_dc_irq(const struct tegra_dc *dc)
1205 {
1206 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1207         enable_irq(dc->irq);
1208 #else
1209         /* Always disable DC interrupts on FPGA. */
1210         disable_irq(dc->irq);
1211 #endif
1212 }
1213
1214 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1215 {
1216         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1217                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1218 }
1219
1220 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1221 {
1222         int ret = -ENOTTY;
1223
1224         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1225                 return ret;
1226
1227         /*
1228          * Logic is as follows
1229          * a) Indicate we need a vblank.
1230          * b) Wait for completion to be signalled from isr.
1231          * c) Initialize completion for next iteration.
1232          */
1233
1234         tegra_dc_hold_dc_out(dc);
1235         dc->out->user_needs_vblank = true;
1236
1237         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1238         init_completion(&dc->out->user_vblank_comp);
1239         tegra_dc_release_dc_out(dc);
1240
1241         return ret;
1242 }
1243
1244 static void tegra_dc_vblank(struct work_struct *work)
1245 {
1246         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1247         bool nvsd_updated = false;
1248
1249         mutex_lock(&dc->lock);
1250
1251         if (!dc->enabled) {
1252                 mutex_unlock(&dc->lock);
1253                 return;
1254         }
1255
1256         tegra_dc_io_start(dc);
1257         tegra_dc_hold_dc_out(dc);
1258         /* use the new frame's bandwidth setting instead of max(current, new),
1259          * skip this if we're using tegra_dc_one_shot_worker() */
1260         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1261                 tegra_dc_program_bandwidth(dc, true);
1262
1263         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1264         if (!tegra_dc_windows_are_dirty(dc))
1265                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1266
1267         /* Update the SD brightness */
1268         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1269                 nvsd_updated = nvsd_update_brightness(dc);
1270                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1271                  * V_BLANK_NVSD bit of vblank ref-count. */
1272                 if (nvsd_updated) {
1273                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1274                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1275                 } else {
1276                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1277                 }
1278         }
1279
1280         /* Mask vblank interrupt if ref-count is zero. */
1281         if (!dc->vblank_ref_count)
1282                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1283
1284         tegra_dc_release_dc_out(dc);
1285         tegra_dc_io_end(dc);
1286         mutex_unlock(&dc->lock);
1287
1288         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1289                 dc->out->sd_settings->bl_device_name) {
1290                 char *bl_device_name =
1291                         dc->out->sd_settings->bl_device_name;
1292                 dc->out->sd_settings->bl_device =
1293                         get_backlight_device_by_name(bl_device_name);
1294         }
1295
1296         /* Do the actual brightness update outside of the mutex */
1297         if (nvsd_updated && dc->out->sd_settings &&
1298             dc->out->sd_settings->bl_device) {
1299
1300                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1301                 backlight_update_status(bl);
1302         }
1303 }
1304
1305 static void tegra_dc_one_shot_worker(struct work_struct *work)
1306 {
1307         struct tegra_dc *dc = container_of(
1308                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1309         mutex_lock(&dc->lock);
1310
1311         /* memory client has gone idle */
1312         tegra_dc_clear_bandwidth(dc);
1313
1314         if (dc->out_ops->idle) {
1315                 tegra_dc_io_start(dc);
1316                 dc->out_ops->idle(dc);
1317                 tegra_dc_io_end(dc);
1318         }
1319
1320         mutex_unlock(&dc->lock);
1321 }
1322
1323 /* return an arbitrarily large number if count overflow occurs.
1324  * make it a nice base-10 number to show up in stats output */
1325 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1326 {
1327         unsigned count = tegra_dc_readl(dc, reg);
1328
1329         tegra_dc_writel(dc, 0, reg);
1330         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1331 }
1332
1333 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1334 {
1335         int i;
1336
1337         dc->stats.underflows++;
1338         if (dc->underflow_mask & WIN_A_UF_INT)
1339                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1340                         DC_WINBUF_AD_UFLOW_STATUS);
1341         if (dc->underflow_mask & WIN_B_UF_INT)
1342                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1343                         DC_WINBUF_BD_UFLOW_STATUS);
1344         if (dc->underflow_mask & WIN_C_UF_INT)
1345                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1346                         DC_WINBUF_CD_UFLOW_STATUS);
1347
1348         /* Check for any underflow reset conditions */
1349         for (i = 0; i < DC_N_WINDOWS; i++) {
1350                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1351                         dc->windows[i].underflows++;
1352
1353 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1354                         if (dc->windows[i].underflows > 4) {
1355                                 schedule_work(&dc->reset_work);
1356                                 /* reset counter */
1357                                 dc->windows[i].underflows = 0;
1358                                 trace_display_reset(dc);
1359                         }
1360 #endif
1361 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1362                         if (dc->windows[i].underflows > 4) {
1363                                 trace_display_reset(dc);
1364                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1365                                                 DC_DISP_DISP_MISC_CONTROL);
1366                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1367                                                 DC_CMD_STATE_CONTROL);
1368                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1369                                                 DC_CMD_STATE_CONTROL);
1370
1371                                 tegra_dc_writel(dc, 0,
1372                                                 DC_DISP_DISP_MISC_CONTROL);
1373                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1374                                                 DC_CMD_STATE_CONTROL);
1375                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1376                                                 DC_CMD_STATE_CONTROL);
1377                         }
1378 #endif
1379                 } else {
1380                         dc->windows[i].underflows = 0;
1381                 }
1382         }
1383
1384         /* Clear the underflow mask now that we've checked it. */
1385         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1386         dc->underflow_mask = 0;
1387         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1388         trace_underflow(dc);
1389 }
1390
1391 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1392 static void tegra_dc_vpulse2_locked(struct tegra_dc *dc)
1393 {
1394         bool nvsd_updated = false;
1395
1396         if (!dc->enabled)
1397                 return;
1398
1399         /* Clear the V_PULSE2_FLIP if no update */
1400         if (!tegra_dc_windows_are_dirty(dc))
1401                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1402
1403         /* Update the SD brightness */
1404         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1405                 nvsd_updated = nvsd_update_brightness(dc);
1406                 if (nvsd_updated) {
1407                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1408                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1409                 } else {
1410                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1411                 }
1412         }
1413
1414         /* Mask vpulse2 interrupt if ref-count is zero. */
1415         if (!dc->vpulse2_ref_count)
1416                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1417 }
1418 #endif
1419
1420 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1421 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1422 {
1423         /* pending user vblank, so wakeup */
1424         if ((status & (V_BLANK_INT | MSF_INT)) &&
1425             (dc->out->user_needs_vblank)) {
1426                 dc->out->user_needs_vblank = false;
1427                 complete(&dc->out->user_vblank_comp);
1428         }
1429
1430         if (status & V_BLANK_INT) {
1431                 /* Sync up windows. */
1432                 tegra_dc_trigger_windows(dc);
1433
1434                 /* Schedule any additional bottom-half vblank actvities. */
1435                 queue_work(system_freezable_wq, &dc->vblank_work);
1436         }
1437
1438         if (status & FRAME_END_INT) {
1439                 /* Mark the frame_end as complete. */
1440                 if (!completion_done(&dc->frame_end_complete))
1441                         complete(&dc->frame_end_complete);
1442         }
1443
1444 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1445         if (status & V_PULSE2_INT)
1446                 tegra_dc_vpulse2_locked(dc);
1447 #endif
1448 }
1449
1450 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1451 {
1452         /* Schedule any additional bottom-half vblank actvities. */
1453         if (status & V_BLANK_INT)
1454                 queue_work(system_freezable_wq, &dc->vblank_work);
1455
1456         if (status & FRAME_END_INT) {
1457                 struct timespec tm = CURRENT_TIME;
1458                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1459                 wake_up(&dc->timestamp_wq);
1460
1461                 /* Mark the frame_end as complete. */
1462                 if (!completion_done(&dc->frame_end_complete))
1463                         complete(&dc->frame_end_complete);
1464
1465                 tegra_dc_trigger_windows(dc);
1466         }
1467
1468 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1469         if (status & V_PULSE2_INT)
1470                 tegra_dc_vpulse2_locked(dc);
1471 #endif
1472 }
1473
1474 /* XXX: Not sure if we limit look ahead to 1 frame */
1475 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1476 {
1477         BUG_ON(!dc->frametime_ns);
1478         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1479 }
1480
1481 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1482 {
1483         BUG_ON(!dc->frametime_ns);
1484         return (((new_ts - old_ts) > dc->frametime_ns)
1485                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1486                         != div_s64((old_ts - dc->frame_end_timestamp),
1487                                 dc->frametime_ns)));
1488 }
1489 #endif
1490
1491 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1492 {
1493 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1494         struct tegra_dc *dc = ptr;
1495         unsigned long status;
1496         unsigned long underflow_mask;
1497         u32 val;
1498
1499         mutex_lock(&dc->lock);
1500         if (!dc->enabled) {
1501                 mutex_unlock(&dc->lock);
1502                 return IRQ_HANDLED;
1503         }
1504
1505         clk_enable(dc->clk);
1506         tegra_dc_io_start(dc);
1507         tegra_dc_hold_dc_out(dc);
1508
1509         if (!nvhost_module_powered_ext(dc->ndev)) {
1510                 WARN(1, "IRQ when DC not powered!\n");
1511                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1512                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1513                 tegra_dc_release_dc_out(dc);
1514                 tegra_dc_io_end(dc);
1515                 clk_disable(dc->clk);
1516                 mutex_unlock(&dc->lock);
1517                 return IRQ_HANDLED;
1518         }
1519
1520         /* clear all status flags except underflow, save those for the worker */
1521         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1522         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1523         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1524         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1525
1526         /*
1527          * Overlays can get thier internal state corrupted during and underflow
1528          * condition.  The only way to fix this state is to reset the DC.
1529          * if we get 4 consecutive frames with underflows, assume we're
1530          * hosed and reset.
1531          */
1532         underflow_mask = status & ALL_UF_INT;
1533
1534         /* Check underflow */
1535         if (underflow_mask) {
1536                 dc->underflow_mask |= underflow_mask;
1537                 schedule_delayed_work(&dc->underflow_work,
1538                         msecs_to_jiffies(1));
1539         }
1540
1541         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1542                 tegra_dc_one_shot_irq(dc, status);
1543         else
1544                 tegra_dc_continuous_irq(dc, status);
1545
1546         tegra_dc_release_dc_out(dc);
1547         tegra_dc_io_end(dc);
1548         clk_disable(dc->clk);
1549         mutex_unlock(&dc->lock);
1550
1551         return IRQ_HANDLED;
1552 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1553         return IRQ_NONE;
1554 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1555 }
1556
1557 void tegra_dc_set_color_control(struct tegra_dc *dc)
1558 {
1559         u32 color_control;
1560
1561         switch (dc->out->depth) {
1562         case 3:
1563                 color_control = BASE_COLOR_SIZE111;
1564                 break;
1565
1566         case 6:
1567                 color_control = BASE_COLOR_SIZE222;
1568                 break;
1569
1570         case 8:
1571                 color_control = BASE_COLOR_SIZE332;
1572                 break;
1573
1574         case 9:
1575                 color_control = BASE_COLOR_SIZE333;
1576                 break;
1577
1578         case 12:
1579                 color_control = BASE_COLOR_SIZE444;
1580                 break;
1581
1582         case 15:
1583                 color_control = BASE_COLOR_SIZE555;
1584                 break;
1585
1586         case 16:
1587                 color_control = BASE_COLOR_SIZE565;
1588                 break;
1589
1590         case 18:
1591                 color_control = BASE_COLOR_SIZE666;
1592                 break;
1593
1594         default:
1595                 color_control = BASE_COLOR_SIZE888;
1596                 break;
1597         }
1598
1599         switch (dc->out->dither) {
1600         case TEGRA_DC_DISABLE_DITHER:
1601                 color_control |= DITHER_CONTROL_DISABLE;
1602                 break;
1603         case TEGRA_DC_ORDERED_DITHER:
1604                 color_control |= DITHER_CONTROL_ORDERED;
1605                 break;
1606         case TEGRA_DC_ERRDIFF_DITHER:
1607                 /* The line buffer for error-diffusion dither is limited
1608                  * to 1280 pixels per line. This limits the maximum
1609                  * horizontal active area size to 1280 pixels when error
1610                  * diffusion is enabled.
1611                  */
1612                 BUG_ON(dc->mode.h_active > 1280);
1613                 color_control |= DITHER_CONTROL_ERRDIFF;
1614                 break;
1615         }
1616
1617 #ifdef CONFIG_TEGRA_DC_CMU
1618         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1619                 color_control |= CMU_ENABLE;
1620 #endif
1621
1622         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1623 }
1624
1625 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1626 {
1627         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1628                 return dc->win_syncpt[idx];
1629         BUG();
1630 }
1631
1632 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1633 {
1634 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1635         u32 start, end;
1636         unsigned long val;
1637
1638         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1639         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1640
1641         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1642                 dc->mode.v_back_porch + dc->mode.v_active;
1643         end = start + 1;
1644         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1645         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1646
1647         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1648         val |= V_PULSE2_INT;
1649         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1650
1651         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1652         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1653 #endif
1654 }
1655
1656 static int tegra_dc_init(struct tegra_dc *dc)
1657 {
1658         int i;
1659         int int_enable;
1660
1661         tegra_dc_io_start(dc);
1662         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1663         if (dc->ndev->id == 0) {
1664                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1665                                       TEGRA_MC_PRIO_MED);
1666                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1667                                       TEGRA_MC_PRIO_MED);
1668                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1669                                       TEGRA_MC_PRIO_MED);
1670 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1671                 /* only present on Tegra2 and 3 */
1672                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1673                                       TEGRA_MC_PRIO_MED);
1674 #endif
1675                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1676                                       TEGRA_MC_PRIO_HIGH);
1677         } else if (dc->ndev->id == 1) {
1678                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1679                                       TEGRA_MC_PRIO_MED);
1680                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1681                                       TEGRA_MC_PRIO_MED);
1682                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1683                                       TEGRA_MC_PRIO_MED);
1684 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1685                 /* only present on Tegra2 and 3 */
1686                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1687                                       TEGRA_MC_PRIO_MED);
1688 #endif
1689                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1690                                       TEGRA_MC_PRIO_HIGH);
1691         }
1692         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1693                         DC_CMD_CONT_SYNCPT_VSYNC);
1694
1695         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1696         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1697         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1698         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1699 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1700         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1701 #endif
1702         /* enable interrupts for vblank, frame_end and underflows */
1703         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1704         /* for panels with one-shot mode enable tearing effect interrupt */
1705         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1706                 int_enable |= MSF_INT;
1707
1708         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1709         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1710         tegra_dc_init_vpulse2_int(dc);
1711
1712         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1713
1714 #ifdef CONFIG_TEGRA_DC_CMU
1715         if (dc->pdata->cmu)
1716                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
1717         else
1718                 tegra_dc_update_cmu(dc, &default_cmu);
1719 #endif
1720         tegra_dc_set_color_control(dc);
1721         for (i = 0; i < DC_N_WINDOWS; i++) {
1722                 struct tegra_dc_win *win = &dc->windows[i];
1723                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1724                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1725                 tegra_dc_set_csc(dc, &win->csc);
1726                 tegra_dc_set_lut(dc, win);
1727                 tegra_dc_set_scaling_filter(dc);
1728         }
1729
1730         for (i = 0; i < dc->n_windows; i++) {
1731                 u32 syncpt = get_syncpt(dc, i);
1732
1733                 dc->syncpt[i].id = syncpt;
1734
1735                 dc->syncpt[i].min = dc->syncpt[i].max =
1736                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1737         }
1738
1739         trace_display_mode(dc, &dc->mode);
1740
1741         if (dc->mode.pclk) {
1742                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1743                         tegra_dc_io_end(dc);
1744                         return -EINVAL;
1745                 }
1746         }
1747
1748         /* Initialize SD AFTER the modeset.
1749            nvsd_init handles the sd_settings = NULL case. */
1750         nvsd_init(dc, dc->out->sd_settings);
1751
1752         tegra_dc_io_end(dc);
1753
1754         return 0;
1755 }
1756
1757 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1758 {
1759         int failed_init = 0;
1760
1761         tegra_dc_unpowergate_locked(dc);
1762
1763         if (dc->out->enable)
1764                 dc->out->enable(&dc->ndev->dev);
1765
1766         tegra_dc_setup_clk(dc, dc->clk);
1767         tegra_dc_clk_enable(dc);
1768         tegra_dc_io_start(dc);
1769
1770         tegra_dc_power_on(dc);
1771
1772         /* do not accept interrupts during initialization */
1773         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1774
1775         enable_dc_irq(dc);
1776
1777         failed_init = tegra_dc_init(dc);
1778         if (failed_init) {
1779                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1780                 disable_irq_nosync(dc->irq);
1781                 tegra_dc_clear_bandwidth(dc);
1782                 tegra_dc_clk_disable(dc);
1783                 if (dc->out && dc->out->disable)
1784                         dc->out->disable();
1785                 tegra_dc_io_end(dc);
1786                 return false;
1787         }
1788
1789         if (dc->out_ops && dc->out_ops->enable)
1790                 dc->out_ops->enable(dc);
1791
1792         /* force a full blending update */
1793         dc->blend.z[0] = -1;
1794
1795         tegra_dc_ext_enable(dc->ext);
1796
1797         trace_display_enable(dc);
1798
1799         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1800         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1801
1802         if (dc->out->postpoweron)
1803                 dc->out->postpoweron();
1804
1805         tegra_dc_io_end(dc);
1806         return true;
1807 }
1808
1809 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1810 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1811 {
1812         bool ret = true;
1813
1814         if (dc->out->enable)
1815                 dc->out->enable(&dc->ndev->dev);
1816
1817         tegra_dc_setup_clk(dc, dc->clk);
1818         tegra_dc_clk_enable(dc);
1819
1820         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1821                 mutex_lock(&tegra_dcs[1]->lock);
1822                 disable_irq_nosync(tegra_dcs[1]->irq);
1823         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1824                 mutex_lock(&tegra_dcs[0]->lock);
1825                 disable_irq_nosync(tegra_dcs[0]->irq);
1826         }
1827
1828         msleep(5);
1829         tegra_periph_reset_assert(dc->clk);
1830         msleep(2);
1831 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1832         tegra_periph_reset_deassert(dc->clk);
1833         msleep(1);
1834 #endif
1835
1836         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1837                 enable_dc_irq(tegra_dcs[1]);
1838                 mutex_unlock(&tegra_dcs[1]->lock);
1839         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1840                 enable_dc_irq(tegra_dcs[0]);
1841                 mutex_unlock(&tegra_dcs[0]->lock);
1842         }
1843
1844         enable_dc_irq(dc);
1845
1846         if (tegra_dc_init(dc)) {
1847                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1848                 ret = false;
1849         }
1850
1851         if (dc->out_ops && dc->out_ops->enable)
1852                 dc->out_ops->enable(dc);
1853
1854         if (dc->out->postpoweron)
1855                 dc->out->postpoweron();
1856
1857         /* force a full blending update */
1858         dc->blend.z[0] = -1;
1859
1860         tegra_dc_ext_enable(dc->ext);
1861
1862         if (!ret) {
1863                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1864                 _tegra_dc_controller_disable(dc);
1865         }
1866
1867         trace_display_reset(dc);
1868         return ret;
1869 }
1870 #endif
1871
1872 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1873 {
1874         if (dc->mode.pclk == 0) {
1875                 switch (dc->out->type) {
1876                 case TEGRA_DC_OUT_HDMI:
1877                 /* DC enable called but no videomode is loaded.
1878                      Check if HDMI is connected, then set fallback mdoe */
1879                 if (tegra_dc_hpd(dc)) {
1880                         return tegra_dc_set_fb_mode(dc,
1881                                         &tegra_dc_hdmi_fallback_mode, 0);
1882                 } else
1883                         return false;
1884
1885                 break;
1886
1887                 /* Do nothing for other outputs for now */
1888                 case TEGRA_DC_OUT_RGB:
1889
1890                 case TEGRA_DC_OUT_DSI:
1891
1892                 default:
1893                         return false;
1894                 }
1895         }
1896
1897         return false;
1898 }
1899
1900 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1901 {
1902         return _tegra_dc_set_default_videomode(dc);
1903 }
1904
1905 static bool _tegra_dc_enable(struct tegra_dc *dc)
1906 {
1907         if (dc->mode.pclk == 0)
1908                 return false;
1909
1910         if (!dc->out)
1911                 return false;
1912
1913         if (dc->enabled)
1914                 return true;
1915
1916         if (!_tegra_dc_controller_enable(dc))
1917                 return false;
1918
1919         return true;
1920 }
1921
1922 void tegra_dc_enable(struct tegra_dc *dc)
1923 {
1924         mutex_lock(&dc->lock);
1925
1926         if (!dc->enabled)
1927                 dc->enabled = _tegra_dc_enable(dc);
1928
1929         mutex_unlock(&dc->lock);
1930         trace_display_mode(dc, &dc->mode);
1931 }
1932
1933 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1934 {
1935         unsigned i;
1936
1937         tegra_dc_hold_dc_out(dc);
1938
1939         if (dc->out && dc->out->prepoweroff)
1940                 dc->out->prepoweroff();
1941
1942         if (dc->out_ops && dc->out_ops->disable)
1943                 dc->out_ops->disable(dc);
1944
1945         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1946
1947         disable_irq_nosync(dc->irq);
1948
1949         tegra_dc_clear_bandwidth(dc);
1950         if (dc->out_ops->release) /* ugly hack */
1951                 tegra_dc_release_dc_out(dc);
1952         else
1953                 tegra_dc_clk_disable(dc);
1954
1955         if (dc->out && dc->out->disable)
1956                 dc->out->disable();
1957
1958         for (i = 0; i < dc->n_windows; i++) {
1959                 struct tegra_dc_win *w = &dc->windows[i];
1960
1961                 /* reset window bandwidth */
1962                 w->bandwidth = 0;
1963                 w->new_bandwidth = 0;
1964
1965                 /* disable windows */
1966                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1967
1968                 /* flush any pending syncpt waits */
1969                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1970                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1971                                 dc->syncpt[i].min, dc->syncpt[i].max);
1972                         dc->syncpt[i].min++;
1973                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1974                 }
1975         }
1976         trace_display_disable(dc);
1977 }
1978
1979 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1980 {
1981 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1982         u32 val;
1983         if (dc->enabled)  {
1984                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1985                 if (enable)
1986                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1987                 else
1988                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1989                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1990         }
1991 #endif
1992 }
1993
1994 bool tegra_dc_stats_get(struct tegra_dc *dc)
1995 {
1996 #if 0 /* right now it is always enabled */
1997         u32 val;
1998         bool res;
1999
2000         if (dc->enabled)  {
2001                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2002                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2003         } else {
2004                 res = false;
2005         }
2006
2007         return res;
2008 #endif
2009         return true;
2010 }
2011
2012 /* make the screen blank by disabling all windows */
2013 void tegra_dc_blank(struct tegra_dc *dc)
2014 {
2015         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2016         unsigned i;
2017
2018         for (i = 0; i < DC_N_WINDOWS; i++) {
2019                 dcwins[i] = tegra_dc_get_window(dc, i);
2020                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2021         }
2022
2023         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2024         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2025 }
2026
2027 static void _tegra_dc_disable(struct tegra_dc *dc)
2028 {
2029         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2030                 mutex_lock(&dc->one_shot_lock);
2031                 cancel_delayed_work_sync(&dc->one_shot_work);
2032         }
2033
2034         tegra_dc_io_start(dc);
2035         _tegra_dc_controller_disable(dc);
2036         tegra_dc_io_end(dc);
2037
2038         tegra_dc_powergate_locked(dc);
2039
2040         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2041                 mutex_unlock(&dc->one_shot_lock);
2042 }
2043
2044 void tegra_dc_disable(struct tegra_dc *dc)
2045 {
2046         tegra_dc_ext_disable(dc->ext);
2047
2048         /* it's important that new underflow work isn't scheduled before the
2049          * lock is acquired. */
2050         cancel_delayed_work_sync(&dc->underflow_work);
2051
2052         mutex_lock(&dc->lock);
2053
2054         if (dc->enabled) {
2055                 dc->enabled = false;
2056
2057                 if (!dc->suspended)
2058                         _tegra_dc_disable(dc);
2059         }
2060
2061 #ifdef CONFIG_SWITCH
2062         switch_set_state(&dc->modeset_switch, 0);
2063 #endif
2064
2065         mutex_unlock(&dc->lock);
2066         synchronize_irq(dc->irq);
2067         trace_display_mode(dc, &dc->mode);
2068 }
2069
2070 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2071 static void tegra_dc_reset_worker(struct work_struct *work)
2072 {
2073         struct tegra_dc *dc =
2074                 container_of(work, struct tegra_dc, reset_work);
2075
2076         unsigned long val = 0;
2077
2078         mutex_lock(&shared_lock);
2079
2080         dev_warn(&dc->ndev->dev,
2081                 "overlay stuck in underflow state.  resetting.\n");
2082
2083         tegra_dc_ext_disable(dc->ext);
2084
2085         mutex_lock(&dc->lock);
2086
2087         if (dc->enabled == false)
2088                 goto unlock;
2089
2090         dc->enabled = false;
2091
2092         /*
2093          * off host read bus
2094          */
2095         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2096         val &= ~(0x00000100);
2097         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2098
2099         /*
2100          * set DC to STOP mode
2101          */
2102         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2103
2104         msleep(10);
2105
2106         _tegra_dc_controller_disable(dc);
2107
2108         /* _tegra_dc_controller_reset_enable deasserts reset */
2109         _tegra_dc_controller_reset_enable(dc);
2110
2111         dc->enabled = true;
2112
2113         /* reopen host read bus */
2114         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2115         val &= ~(0x00000100);
2116         val |= 0x100;
2117         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2118
2119 unlock:
2120         mutex_unlock(&dc->lock);
2121         mutex_unlock(&shared_lock);
2122         trace_display_reset(dc);
2123 }
2124 #endif
2125
2126 static void tegra_dc_underflow_worker(struct work_struct *work)
2127 {
2128         struct tegra_dc *dc = container_of(
2129                 to_delayed_work(work), struct tegra_dc, underflow_work);
2130
2131         mutex_lock(&dc->lock);
2132         tegra_dc_io_start(dc);
2133         tegra_dc_hold_dc_out(dc);
2134
2135         if (dc->enabled) {
2136                 tegra_dc_underflow_handler(dc);
2137         }
2138         tegra_dc_release_dc_out(dc);
2139         tegra_dc_io_end(dc);
2140         mutex_unlock(&dc->lock);
2141 }
2142
2143 #ifdef CONFIG_SWITCH
2144 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2145 {
2146         struct tegra_dc *dc =
2147                 container_of(sdev, struct tegra_dc, modeset_switch);
2148
2149         if (!sdev->state)
2150                 return sprintf(buf, "offline\n");
2151
2152         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2153 }
2154 #endif
2155
2156 static int tegra_dc_probe(struct platform_device *ndev)
2157 {
2158         struct tegra_dc *dc;
2159         struct tegra_dc_mode *mode;
2160         struct clk *clk;
2161         struct clk *emc_clk;
2162         struct resource *res;
2163         struct resource *base_res;
2164         struct resource *fb_mem = NULL;
2165         int ret = 0;
2166         void __iomem *base;
2167         int irq;
2168         int i;
2169
2170         if (!ndev->dev.platform_data) {
2171                 dev_err(&ndev->dev, "no platform data\n");
2172                 return -ENOENT;
2173         }
2174
2175         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2176         if (!dc) {
2177                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2178                 return -ENOMEM;
2179         }
2180
2181         irq = platform_get_irq_byname(ndev, "irq");
2182         if (irq <= 0) {
2183                 dev_err(&ndev->dev, "no irq\n");
2184                 ret = -ENOENT;
2185                 goto err_free;
2186         }
2187
2188         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2189         if (!res) {
2190                 dev_err(&ndev->dev, "no mem resource\n");
2191                 ret = -ENOENT;
2192                 goto err_free;
2193         }
2194
2195         base_res = request_mem_region(res->start, resource_size(res),
2196                 ndev->name);
2197         if (!base_res) {
2198                 dev_err(&ndev->dev, "request_mem_region failed\n");
2199                 ret = -EBUSY;
2200                 goto err_free;
2201         }
2202
2203         base = ioremap(res->start, resource_size(res));
2204         if (!base) {
2205                 dev_err(&ndev->dev, "registers can't be mapped\n");
2206                 ret = -EBUSY;
2207                 goto err_release_resource_reg;
2208         }
2209         if (TEGRA_DISPLAY_BASE == res->start) {
2210                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2211                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2212                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2213                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2214         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2215                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2216                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2217                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2218                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2219         } else {
2220                 dev_err(&ndev->dev,
2221                         "Unknown base address %#08x: unable to assign syncpt\n",
2222                         res->start);
2223         }
2224
2225
2226         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2227
2228         clk = clk_get(&ndev->dev, NULL);
2229         if (IS_ERR_OR_NULL(clk)) {
2230                 dev_err(&ndev->dev, "can't get clock\n");
2231                 ret = -ENOENT;
2232                 goto err_iounmap_reg;
2233         }
2234
2235         emc_clk = clk_get(&ndev->dev, "emc");
2236         if (IS_ERR_OR_NULL(emc_clk)) {
2237                 dev_err(&ndev->dev, "can't get emc clock\n");
2238                 ret = -ENOENT;
2239                 goto err_put_clk;
2240         }
2241
2242         dc->clk = clk;
2243         dc->emc_clk = emc_clk;
2244         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2245         /* Initialize one shot work delay, it will be assigned by dsi
2246          * according to refresh rate later. */
2247         dc->one_shot_delay_ms = 40;
2248
2249         dc->base_res = base_res;
2250         dc->base = base;
2251         dc->irq = irq;
2252         dc->ndev = ndev;
2253         dc->pdata = ndev->dev.platform_data;
2254
2255         /*
2256          * The emc is a shared clock, it will be set based on
2257          * the requirements for each user on the bus.
2258          */
2259         dc->emc_clk_rate = 0;
2260
2261         mutex_init(&dc->lock);
2262         mutex_init(&dc->one_shot_lock);
2263         init_completion(&dc->frame_end_complete);
2264         init_waitqueue_head(&dc->wq);
2265         init_waitqueue_head(&dc->timestamp_wq);
2266 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2267         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2268 #endif
2269         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2270         dc->vblank_ref_count = 0;
2271         dc->vpulse2_ref_count = 0;
2272         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2273         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2274
2275         tegra_dc_init_lut_defaults(&dc->fb_lut);
2276
2277         dc->n_windows = DC_N_WINDOWS;
2278         for (i = 0; i < dc->n_windows; i++) {
2279                 struct tegra_dc_win *win = &dc->windows[i];
2280                 win->idx = i;
2281                 win->dc = dc;
2282                 tegra_dc_init_csc_defaults(&win->csc);
2283                 tegra_dc_init_lut_defaults(&win->lut);
2284         }
2285
2286         ret = tegra_dc_set(dc, ndev->id);
2287         if (ret < 0) {
2288                 dev_err(&ndev->dev, "can't add dc\n");
2289                 goto err_free_irq;
2290         }
2291
2292         platform_set_drvdata(ndev, dc);
2293
2294 #ifdef CONFIG_SWITCH
2295         dc->modeset_switch.name = dev_name(&ndev->dev);
2296         dc->modeset_switch.state = 0;
2297         dc->modeset_switch.print_state = switch_modeset_print_mode;
2298         ret = switch_dev_register(&dc->modeset_switch);
2299         if (ret < 0)
2300                 dev_err(&ndev->dev, "failed to register switch driver\n");
2301 #endif
2302
2303         tegra_dc_feature_register(dc);
2304
2305         if (dc->pdata->default_out)
2306                 tegra_dc_set_out(dc, dc->pdata->default_out);
2307         else
2308                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2309
2310         dc->ext = tegra_dc_ext_register(ndev, dc);
2311         if (IS_ERR_OR_NULL(dc->ext)) {
2312                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2313                 dc->ext = NULL;
2314         }
2315
2316         /* interrupt handler must be registered before tegra_fb_register() */
2317         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2318                         dev_name(&ndev->dev), dc)) {
2319                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2320                 ret = -EBUSY;
2321                 goto err_put_emc_clk;
2322         }
2323         disable_dc_irq(dc);
2324
2325         mutex_lock(&dc->lock);
2326         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2327                 _tegra_dc_set_default_videomode(dc);
2328                 dc->enabled = _tegra_dc_enable(dc);
2329         }
2330         mutex_unlock(&dc->lock);
2331
2332         mutex_lock(&dc->lock);
2333         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2334                 _tegra_dc_set_default_videomode(dc);
2335                 dc->enabled = _tegra_dc_enable(dc);
2336         }
2337         mutex_unlock(&dc->lock);
2338
2339         tegra_dc_create_debugfs(dc);
2340
2341         dev_info(&ndev->dev, "probed\n");
2342
2343         if (dc->pdata->fb) {
2344                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2345                         unsigned long fmt;
2346                         tegra_dc_writel(dc,
2347                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2348                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2349
2350                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2351                         dc->pdata->fb->bits_per_pixel =
2352                                 tegra_dc_fmt_bpp(fmt);
2353                 }
2354
2355                 mode = tegra_dc_get_override_mode(dc);
2356                 if (mode) {
2357                         dc->pdata->fb->xres = mode->h_active;
2358                         dc->pdata->fb->yres = mode->v_active;
2359                 }
2360
2361                 tegra_dc_io_start(dc);
2362                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2363                 if (IS_ERR_OR_NULL(dc->fb))
2364                         dc->fb = NULL;
2365                 tegra_dc_io_end(dc);
2366         }
2367
2368         if (dc->out && dc->out->hotplug_init)
2369                 dc->out->hotplug_init(&ndev->dev);
2370
2371         if (dc->out_ops && dc->out_ops->detect)
2372                 dc->out_ops->detect(dc);
2373         else
2374                 dc->connected = true;
2375
2376 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2377         /* Powergate display module when it's unconnected. */
2378         if (!tegra_dc_get_connected(dc))
2379                 tegra_dc_powergate_locked(dc);
2380 #endif
2381
2382         tegra_dc_create_sysfs(&dc->ndev->dev);
2383
2384         return 0;
2385
2386 err_free_irq:
2387         free_irq(irq, dc);
2388 err_put_emc_clk:
2389         clk_put(emc_clk);
2390 err_put_clk:
2391         clk_put(clk);
2392 err_iounmap_reg:
2393         iounmap(base);
2394         if (fb_mem)
2395                 release_resource(fb_mem);
2396 err_release_resource_reg:
2397         release_resource(base_res);
2398 err_free:
2399         kfree(dc);
2400
2401         return ret;
2402 }
2403
2404 static int tegra_dc_remove(struct platform_device *ndev)
2405 {
2406         struct tegra_dc *dc = platform_get_drvdata(ndev);
2407
2408         tegra_dc_remove_sysfs(&dc->ndev->dev);
2409         tegra_dc_remove_debugfs(dc);
2410
2411         if (dc->fb) {
2412                 tegra_fb_unregister(dc->fb);
2413                 if (dc->fb_mem)
2414                         release_resource(dc->fb_mem);
2415         }
2416
2417         tegra_dc_ext_disable(dc->ext);
2418
2419         if (dc->ext)
2420                 tegra_dc_ext_unregister(dc->ext);
2421
2422         mutex_lock(&dc->lock);
2423         if (dc->enabled)
2424                 _tegra_dc_disable(dc);
2425         dc->enabled = false;
2426         mutex_unlock(&dc->lock);
2427         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2428
2429 #ifdef CONFIG_SWITCH
2430         switch_dev_unregister(&dc->modeset_switch);
2431 #endif
2432         free_irq(dc->irq, dc);
2433         clk_put(dc->emc_clk);
2434         clk_put(dc->clk);
2435         iounmap(dc->base);
2436         if (dc->fb_mem)
2437                 release_resource(dc->base_res);
2438         kfree(dc);
2439         tegra_dc_set(NULL, ndev->id);
2440
2441         return 0;
2442 }
2443
2444 #ifdef CONFIG_PM
2445 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2446 {
2447         struct tegra_dc *dc = platform_get_drvdata(ndev);
2448
2449         trace_display_suspend(dc);
2450         dev_info(&ndev->dev, "suspend\n");
2451
2452         tegra_dc_ext_disable(dc->ext);
2453
2454         mutex_lock(&dc->lock);
2455         tegra_dc_io_start(dc);
2456
2457         if (dc->out_ops && dc->out_ops->suspend)
2458                 dc->out_ops->suspend(dc);
2459
2460         if (dc->enabled) {
2461                 _tegra_dc_disable(dc);
2462
2463                 dc->suspended = true;
2464         }
2465
2466         if (dc->out && dc->out->postsuspend) {
2467                 dc->out->postsuspend();
2468                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2469                         /*
2470                          * avoid resume event due to voltage falling
2471                          */
2472                         msleep(100);
2473         }
2474
2475         tegra_dc_io_end(dc);
2476         mutex_unlock(&dc->lock);
2477         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2478
2479         return 0;
2480 }
2481
2482 static int tegra_dc_resume(struct platform_device *ndev)
2483 {
2484         struct tegra_dc *dc = platform_get_drvdata(ndev);
2485
2486         trace_display_resume(dc);
2487         dev_info(&ndev->dev, "resume\n");
2488
2489         mutex_lock(&dc->lock);
2490         dc->suspended = false;
2491
2492         if (dc->enabled) {
2493                 dc->enabled = false;
2494                 _tegra_dc_set_default_videomode(dc);
2495                 dc->enabled = _tegra_dc_enable(dc);
2496         }
2497
2498         if (dc->out && dc->out->hotplug_init)
2499                 dc->out->hotplug_init(&ndev->dev);
2500
2501         if (dc->out_ops && dc->out_ops->resume)
2502                 dc->out_ops->resume(dc);
2503         mutex_unlock(&dc->lock);
2504
2505         return 0;
2506 }
2507
2508 #endif /* CONFIG_PM */
2509
2510 static void tegra_dc_shutdown(struct platform_device *ndev)
2511 {
2512         struct tegra_dc *dc = platform_get_drvdata(ndev);
2513
2514         if (!dc || !dc->enabled)
2515                 return;
2516
2517         tegra_dc_blank(dc);
2518         tegra_dc_disable(dc);
2519 }
2520
2521 extern int suspend_set(const char *val, struct kernel_param *kp)
2522 {
2523         if (!strcmp(val, "dump"))
2524                 dump_regs(tegra_dcs[0]);
2525 #ifdef CONFIG_PM
2526         else if (!strcmp(val, "suspend"))
2527                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2528         else if (!strcmp(val, "resume"))
2529                 tegra_dc_resume(tegra_dcs[0]->ndev);
2530 #endif
2531
2532         return 0;
2533 }
2534
2535 extern int suspend_get(char *buffer, struct kernel_param *kp)
2536 {
2537         return 0;
2538 }
2539
2540 int suspend;
2541
2542 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2543
2544 struct platform_driver tegra_dc_driver = {
2545         .driver = {
2546                 .name = "tegradc",
2547                 .owner = THIS_MODULE,
2548         },
2549         .probe = tegra_dc_probe,
2550         .remove = tegra_dc_remove,
2551 #ifdef CONFIG_PM
2552         .suspend = tegra_dc_suspend,
2553         .resume = tegra_dc_resume,
2554 #endif
2555         .shutdown = tegra_dc_shutdown,
2556 };
2557
2558 #ifndef MODULE
2559 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2560 {
2561         int i, params[11];
2562         char *p;
2563
2564         for (i = 0; i < ARRAY_SIZE(params); i++) {
2565                 if ((p = strsep(&options, ",")) != NULL) {
2566                         if (*p)
2567                                 params[i] = simple_strtoul(p, &p, 10);
2568                 } else
2569                         return -EINVAL;
2570         }
2571
2572         if ((mode->pclk = params[0]) == 0)
2573                 return -EINVAL;
2574
2575         mode->h_active      = params[1];
2576         mode->v_active      = params[2];
2577         mode->h_ref_to_sync = params[3];
2578         mode->v_ref_to_sync = params[4];
2579         mode->h_sync_width  = params[5];
2580         mode->v_sync_width  = params[6];
2581         mode->h_back_porch  = params[7];
2582         mode->v_back_porch  = params[8];
2583         mode->h_front_porch = params[9];
2584         mode->v_front_porch = params[10];
2585
2586         return 0;
2587 }
2588
2589 static int __init tegra_dc_mode_override(char *str)
2590 {
2591         char *p = str, *options;
2592
2593         if (!p || !*p)
2594                 return -EINVAL;
2595
2596         p = strstr(str, "hdmi:");
2597         if (p) {
2598                 p += 5;
2599                 options = strsep(&p, ";");
2600                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2601                         return -EINVAL;
2602         }
2603
2604         p = strstr(str, "rgb:");
2605         if (p) {
2606                 p += 4;
2607                 options = strsep(&p, ";");
2608                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2609                         return -EINVAL;
2610         }
2611
2612         p = strstr(str, "dsi:");
2613         if (p) {
2614                 p += 4;
2615                 options = strsep(&p, ";");
2616                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2617                         return -EINVAL;
2618         }
2619
2620         return 0;
2621 }
2622
2623 __setup("disp_params=", tegra_dc_mode_override);
2624 #endif
2625
2626 static int __init tegra_dc_module_init(void)
2627 {
2628         int ret = tegra_dc_ext_module_init();
2629         if (ret)
2630                 return ret;
2631         return platform_driver_register(&tegra_dc_driver);
2632 }
2633
2634 static void __exit tegra_dc_module_exit(void)
2635 {
2636         platform_driver_unregister(&tegra_dc_driver);
2637         tegra_dc_ext_module_exit();
2638 }
2639
2640 module_exit(tegra_dc_module_exit);
2641 module_init(tegra_dc_module_init);