video: tegra: Use new Tegra platform types
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
63 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
64 #else
65 /* ignore underflows when on simulation and fpga platform */
66 #define ALL_UF_INT (0)
67 #endif
68
69 static int no_vsync;
70 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
71         .refresh = 60,
72         .xres = 640,
73         .yres = 480,
74         .pixclock = KHZ2PICOS(25200),
75         .hsync_len = 96,        /* h_sync_width */
76         .vsync_len = 2,         /* v_sync_width */
77         .left_margin = 48,      /* h_back_porch */
78         .upper_margin = 33,     /* v_back_porch */
79         .right_margin = 16,     /* h_front_porch */
80         .lower_margin = 10,     /* v_front_porch */
81         .vmode = 0,
82         .sync = 0,
83 };
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
88
89 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
90
91 DEFINE_MUTEX(tegra_dc_lock);
92 DEFINE_MUTEX(shared_lock);
93
94 static const struct {
95         bool h;
96         bool v;
97 } can_filter[] = {
98         /* Window A has no filtering */
99         { false, false },
100         /* Window B has both H and V filtering */
101         { true,  true  },
102         /* Window C has only H filtering */
103         { false, true  },
104 };
105
106 #ifdef CONFIG_TEGRA_DC_CMU
107 static struct tegra_dc_cmu default_cmu = {
108         /* lut1 maps sRGB to linear space. */
109         {
110                 0,    1,    2,    4,    5,    6,    7,    9,
111                 10,   11,   12,   14,   15,   16,   18,   20,
112                 21,   23,   25,   27,   29,   31,   33,   35,
113                 37,   40,   42,   45,   48,   50,   53,   56,
114                 59,   62,   66,   69,   72,   76,   79,   83,
115                 87,   91,   95,   99,   103,  107,  112,  116,
116                 121,  126,  131,  136,  141,  146,  151,  156,
117                 162,  168,  173,  179,  185,  191,  197,  204,
118                 210,  216,  223,  230,  237,  244,  251,  258,
119                 265,  273,  280,  288,  296,  304,  312,  320,
120                 329,  337,  346,  354,  363,  372,  381,  390,
121                 400,  409,  419,  428,  438,  448,  458,  469,
122                 479,  490,  500,  511,  522,  533,  544,  555,
123                 567,  578,  590,  602,  614,  626,  639,  651,
124                 664,  676,  689,  702,  715,  728,  742,  755,
125                 769,  783,  797,  811,  825,  840,  854,  869,
126                 884,  899,  914,  929,  945,  960,  976,  992,
127                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
128                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
129                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
130                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
131                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
132                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
133                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
134                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
135                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
136                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
137                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
138                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
139                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
140                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
141                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
142         },
143         /* csc */
144         {
145                 0x100, 0x0,   0x0,
146                 0x0,   0x100, 0x0,
147                 0x0,   0x0,   0x100,
148         },
149         /* lut2 maps linear space to sRGB*/
150         {
151                 0,    1,    2,    2,    3,    4,    5,    6,
152                 6,    7,    8,    9,    10,   10,   11,   12,
153                 13,   13,   14,   15,   15,   16,   16,   17,
154                 18,   18,   19,   19,   20,   20,   21,   21,
155                 22,   22,   23,   23,   23,   24,   24,   25,
156                 25,   25,   26,   26,   27,   27,   27,   28,
157                 28,   29,   29,   29,   30,   30,   30,   31,
158                 31,   31,   32,   32,   32,   33,   33,   33,
159                 34,   34,   34,   34,   35,   35,   35,   36,
160                 36,   36,   37,   37,   37,   37,   38,   38,
161                 38,   38,   39,   39,   39,   40,   40,   40,
162                 40,   41,   41,   41,   41,   42,   42,   42,
163                 42,   43,   43,   43,   43,   43,   44,   44,
164                 44,   44,   45,   45,   45,   45,   46,   46,
165                 46,   46,   46,   47,   47,   47,   47,   48,
166                 48,   48,   48,   48,   49,   49,   49,   49,
167                 49,   50,   50,   50,   50,   50,   51,   51,
168                 51,   51,   51,   52,   52,   52,   52,   52,
169                 53,   53,   53,   53,   53,   54,   54,   54,
170                 54,   54,   55,   55,   55,   55,   55,   55,
171                 56,   56,   56,   56,   56,   57,   57,   57,
172                 57,   57,   57,   58,   58,   58,   58,   58,
173                 58,   59,   59,   59,   59,   59,   59,   60,
174                 60,   60,   60,   60,   60,   61,   61,   61,
175                 61,   61,   61,   62,   62,   62,   62,   62,
176                 62,   63,   63,   63,   63,   63,   63,   64,
177                 64,   64,   64,   64,   64,   64,   65,   65,
178                 65,   65,   65,   65,   66,   66,   66,   66,
179                 66,   66,   66,   67,   67,   67,   67,   67,
180                 67,   67,   68,   68,   68,   68,   68,   68,
181                 68,   69,   69,   69,   69,   69,   69,   69,
182                 70,   70,   70,   70,   70,   70,   70,   71,
183                 71,   71,   71,   71,   71,   71,   72,   72,
184                 72,   72,   72,   72,   72,   72,   73,   73,
185                 73,   73,   73,   73,   73,   74,   74,   74,
186                 74,   74,   74,   74,   74,   75,   75,   75,
187                 75,   75,   75,   75,   75,   76,   76,   76,
188                 76,   76,   76,   76,   77,   77,   77,   77,
189                 77,   77,   77,   77,   78,   78,   78,   78,
190                 78,   78,   78,   78,   78,   79,   79,   79,
191                 79,   79,   79,   79,   79,   80,   80,   80,
192                 80,   80,   80,   80,   80,   81,   81,   81,
193                 81,   81,   81,   81,   81,   81,   82,   82,
194                 82,   82,   82,   82,   82,   82,   83,   83,
195                 83,   83,   83,   83,   83,   83,   83,   84,
196                 84,   84,   84,   84,   84,   84,   84,   84,
197                 85,   85,   85,   85,   85,   85,   85,   85,
198                 85,   86,   86,   86,   86,   86,   86,   86,
199                 86,   86,   87,   87,   87,   87,   87,   87,
200                 87,   87,   87,   88,   88,   88,   88,   88,
201                 88,   88,   88,   88,   88,   89,   89,   89,
202                 89,   89,   89,   89,   89,   89,   90,   90,
203                 90,   90,   90,   90,   90,   90,   90,   90,
204                 91,   91,   91,   91,   91,   91,   91,   91,
205                 91,   91,   92,   92,   92,   92,   92,   92,
206                 92,   92,   92,   92,   93,   93,   93,   93,
207                 93,   93,   93,   93,   93,   93,   94,   94,
208                 94,   94,   94,   94,   94,   94,   94,   94,
209                 95,   95,   95,   95,   95,   95,   95,   95,
210                 95,   95,   96,   96,   96,   96,   96,   96,
211                 96,   96,   96,   96,   96,   97,   97,   97,
212                 97,   97,   97,   97,   97,   97,   97,   98,
213                 98,   98,   98,   98,   98,   98,   98,   98,
214                 98,   98,   99,   99,   99,   99,   99,   99,
215                 99,   100,  101,  101,  102,  103,  103,  104,
216                 105,  105,  106,  107,  107,  108,  109,  109,
217                 110,  111,  111,  112,  113,  113,  114,  115,
218                 115,  116,  116,  117,  118,  118,  119,  119,
219                 120,  120,  121,  122,  122,  123,  123,  124,
220                 124,  125,  126,  126,  127,  127,  128,  128,
221                 129,  129,  130,  130,  131,  131,  132,  132,
222                 133,  133,  134,  134,  135,  135,  136,  136,
223                 137,  137,  138,  138,  139,  139,  140,  140,
224                 141,  141,  142,  142,  143,  143,  144,  144,
225                 145,  145,  145,  146,  146,  147,  147,  148,
226                 148,  149,  149,  150,  150,  150,  151,  151,
227                 152,  152,  153,  153,  153,  154,  154,  155,
228                 155,  156,  156,  156,  157,  157,  158,  158,
229                 158,  159,  159,  160,  160,  160,  161,  161,
230                 162,  162,  162,  163,  163,  164,  164,  164,
231                 165,  165,  166,  166,  166,  167,  167,  167,
232                 168,  168,  169,  169,  169,  170,  170,  170,
233                 171,  171,  172,  172,  172,  173,  173,  173,
234                 174,  174,  174,  175,  175,  176,  176,  176,
235                 177,  177,  177,  178,  178,  178,  179,  179,
236                 179,  180,  180,  180,  181,  181,  182,  182,
237                 182,  183,  183,  183,  184,  184,  184,  185,
238                 185,  185,  186,  186,  186,  187,  187,  187,
239                 188,  188,  188,  189,  189,  189,  189,  190,
240                 190,  190,  191,  191,  191,  192,  192,  192,
241                 193,  193,  193,  194,  194,  194,  195,  195,
242                 195,  196,  196,  196,  196,  197,  197,  197,
243                 198,  198,  198,  199,  199,  199,  200,  200,
244                 200,  200,  201,  201,  201,  202,  202,  202,
245                 202,  203,  203,  203,  204,  204,  204,  205,
246                 205,  205,  205,  206,  206,  206,  207,  207,
247                 207,  207,  208,  208,  208,  209,  209,  209,
248                 209,  210,  210,  210,  211,  211,  211,  211,
249                 212,  212,  212,  213,  213,  213,  213,  214,
250                 214,  214,  214,  215,  215,  215,  216,  216,
251                 216,  216,  217,  217,  217,  217,  218,  218,
252                 218,  219,  219,  219,  219,  220,  220,  220,
253                 220,  221,  221,  221,  221,  222,  222,  222,
254                 223,  223,  223,  223,  224,  224,  224,  224,
255                 225,  225,  225,  225,  226,  226,  226,  226,
256                 227,  227,  227,  227,  228,  228,  228,  228,
257                 229,  229,  229,  229,  230,  230,  230,  230,
258                 231,  231,  231,  231,  232,  232,  232,  232,
259                 233,  233,  233,  233,  234,  234,  234,  234,
260                 235,  235,  235,  235,  236,  236,  236,  236,
261                 237,  237,  237,  237,  238,  238,  238,  238,
262                 239,  239,  239,  239,  240,  240,  240,  240,
263                 240,  241,  241,  241,  241,  242,  242,  242,
264                 242,  243,  243,  243,  243,  244,  244,  244,
265                 244,  244,  245,  245,  245,  245,  246,  246,
266                 246,  246,  247,  247,  247,  247,  247,  248,
267                 248,  248,  248,  249,  249,  249,  249,  249,
268                 250,  250,  250,  250,  251,  251,  251,  251,
269                 251,  252,  252,  252,  252,  253,  253,  253,
270                 253,  253,  254,  254,  254,  254,  255,  255,
271         },
272 };
273 #endif
274
275 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
276 {
277         if (!tegra_is_clk_enabled(dc->clk)) {
278                 clk_enable(dc->clk);
279                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
280         }
281 }
282
283 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
284 {
285         if (tegra_is_clk_enabled(dc->clk)) {
286                 clk_disable(dc->clk);
287                 tegra_dvfs_set_rate(dc->clk, 0);
288         }
289 }
290
291 #define DUMP_REG(a) do {                        \
292         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
293                  #a, a, tegra_dc_readl(dc, a));               \
294         print(data, buff);                                    \
295         } while (0)
296
297 #define print_mode_info(dc, mode) do {                        \
298         trace_printk("%s:Mode settings: "                              \
299                         "ref_to_sync: H = %d V = %d, "                  \
300                         "sync_width: H = %d V = %d, "                   \
301                         "back_porch: H = %d V = %d, "                   \
302                         "active: H = %d V = %d, "                       \
303                         "front_porch: H = %d V = %d, "                  \
304                         "pclk = %d, stereo mode = %d\n",                \
305                         dc->ndev->name,                                 \
306                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
307                         mode.h_sync_width, mode.v_sync_width,           \
308                         mode.h_back_porch, mode.v_back_porch,           \
309                         mode.h_active, mode.v_active,                   \
310                         mode.h_front_porch, mode.v_front_porch,         \
311                         mode.pclk, mode.stereo_mode);                   \
312         } while (0)
313
314 #define print_underflow_info(dc) do {                 \
315         trace_printk("%s:Underflow stats: underflows : %llu, "      \
316                         "undeflows_a : %llu, "                          \
317                         "underflows_b : %llu, "                         \
318                         "underflows_c : %llu\n",                        \
319                         dc->ndev->name,                                 \
320                         dc->stats.underflows,                           \
321                         dc->stats.underflows_a, dc->stats.underflows_b, \
322                         dc->stats.underflows_c);                        \
323         } while (0)
324
325 static void _dump_regs(struct tegra_dc *dc, void *data,
326                        void (* print)(void *data, const char *str))
327 {
328         int i;
329         char buff[256];
330
331         tegra_dc_io_start(dc);
332         tegra_dc_clk_enable(dc);
333
334         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
335         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
336         DUMP_REG(DC_CMD_SIGNAL_RAISE);
337         DUMP_REG(DC_CMD_INT_STATUS);
338         DUMP_REG(DC_CMD_INT_MASK);
339         DUMP_REG(DC_CMD_INT_ENABLE);
340         DUMP_REG(DC_CMD_INT_TYPE);
341         DUMP_REG(DC_CMD_INT_POLARITY);
342         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
343         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
344         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
345         DUMP_REG(DC_CMD_STATE_ACCESS);
346         DUMP_REG(DC_CMD_STATE_CONTROL);
347         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
348         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
349
350         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
351         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
352         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
353         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
354         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
355         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
356         DUMP_REG(DC_DISP_REF_TO_SYNC);
357         DUMP_REG(DC_DISP_SYNC_WIDTH);
358         DUMP_REG(DC_DISP_BACK_PORCH);
359         DUMP_REG(DC_DISP_DISP_ACTIVE);
360         DUMP_REG(DC_DISP_FRONT_PORCH);
361         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
362         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
363         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
364         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
365         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
366         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
367         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
368         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
369         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
370         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
371         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
372         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
373         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
374         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
375         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
376         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
377         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
378         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
379         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
380         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
381         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
382         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
383         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
384         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
385         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
386         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
387         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
388         DUMP_REG(DC_DISP_M0_CONTROL);
389         DUMP_REG(DC_DISP_M1_CONTROL);
390         DUMP_REG(DC_DISP_DI_CONTROL);
391         DUMP_REG(DC_DISP_PP_CONTROL);
392         DUMP_REG(DC_DISP_PP_SELECT_A);
393         DUMP_REG(DC_DISP_PP_SELECT_B);
394         DUMP_REG(DC_DISP_PP_SELECT_C);
395         DUMP_REG(DC_DISP_PP_SELECT_D);
396         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
397         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
398         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
399         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
400         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
401         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
402         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
403         DUMP_REG(DC_DISP_BORDER_COLOR);
404         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
405         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
406         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
407         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
408         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
409         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
410         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
411         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
412         DUMP_REG(DC_DISP_CURSOR_POSITION);
413         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
414         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
415         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
416         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
417         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
418         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
419         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
420         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
421         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
422         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
423         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
424         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
425         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
426
427
428         for (i = 0; i < 3; i++) {
429                 print(data, "\n");
430                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
431                 print(data, buff);
432
433                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
434                                 DC_CMD_DISPLAY_WINDOW_HEADER);
435                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
436                 DUMP_REG(DC_WIN_WIN_OPTIONS);
437                 DUMP_REG(DC_WIN_BYTE_SWAP);
438                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
439                 DUMP_REG(DC_WIN_COLOR_DEPTH);
440                 DUMP_REG(DC_WIN_POSITION);
441                 DUMP_REG(DC_WIN_SIZE);
442                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
443                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
444                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
445                 DUMP_REG(DC_WIN_DDA_INCREMENT);
446                 DUMP_REG(DC_WIN_LINE_STRIDE);
447 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
448                 DUMP_REG(DC_WIN_BUF_STRIDE);
449                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
450 #endif
451                 DUMP_REG(DC_WIN_BLEND_NOKEY);
452                 DUMP_REG(DC_WIN_BLEND_1WIN);
453                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
454                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
455                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
456                 DUMP_REG(DC_WINBUF_START_ADDR);
457                 DUMP_REG(DC_WINBUF_START_ADDR_U);
458                 DUMP_REG(DC_WINBUF_START_ADDR_V);
459                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
460                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
461                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
462                 DUMP_REG(DC_WIN_CSC_YOF);
463                 DUMP_REG(DC_WIN_CSC_KYRGB);
464                 DUMP_REG(DC_WIN_CSC_KUR);
465                 DUMP_REG(DC_WIN_CSC_KVR);
466                 DUMP_REG(DC_WIN_CSC_KUG);
467                 DUMP_REG(DC_WIN_CSC_KVG);
468                 DUMP_REG(DC_WIN_CSC_KUB);
469                 DUMP_REG(DC_WIN_CSC_KVB);
470         }
471
472         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
473         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
474         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
475         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
476         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
477         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
478         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
479         DUMP_REG(DC_DISP_M1_CONTROL);
480         DUMP_REG(DC_COM_PM1_CONTROL);
481         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
482         DUMP_REG(DC_DISP_SD_CONTROL);
483
484         tegra_dc_clk_disable(dc->clk);
485         tegra_dc_io_end(dc);
486 }
487
488 #undef DUMP_REG
489
490 #ifdef DEBUG
491 static void dump_regs_print(void *data, const char *str)
492 {
493         struct tegra_dc *dc = data;
494         dev_dbg(&dc->ndev->dev, "%s", str);
495 }
496
497 static void dump_regs(struct tegra_dc *dc)
498 {
499         _dump_regs(dc, dc, dump_regs_print);
500 }
501 #else /* !DEBUG */
502
503 static void dump_regs(struct tegra_dc *dc) {}
504
505 #endif /* DEBUG */
506
507 #ifdef CONFIG_DEBUG_FS
508
509 static void dbg_regs_print(void *data, const char *str)
510 {
511         struct seq_file *s = data;
512
513         seq_printf(s, "%s", str);
514 }
515
516 #undef DUMP_REG
517
518 static int dbg_dc_show(struct seq_file *s, void *unused)
519 {
520         struct tegra_dc *dc = s->private;
521
522         _dump_regs(dc, s, dbg_regs_print);
523
524         return 0;
525 }
526
527
528 static int dbg_dc_open(struct inode *inode, struct file *file)
529 {
530         return single_open(file, dbg_dc_show, inode->i_private);
531 }
532
533 static const struct file_operations regs_fops = {
534         .open           = dbg_dc_open,
535         .read           = seq_read,
536         .llseek         = seq_lseek,
537         .release        = single_release,
538 };
539
540 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
541 {
542         struct tegra_dc *dc = s->private;
543         struct tegra_dc_mode *m;
544
545         mutex_lock(&dc->lock);
546         m = &dc->mode;
547         seq_printf(s,
548                 "pclk: %d\n"
549                 "h_ref_to_sync: %d\n"
550                 "v_ref_to_sync: %d\n"
551                 "h_sync_width: %d\n"
552                 "v_sync_width: %d\n"
553                 "h_back_porch: %d\n"
554                 "v_back_porch: %d\n"
555                 "h_active: %d\n"
556                 "v_active: %d\n"
557                 "h_front_porch: %d\n"
558                 "v_front_porch: %d\n"
559                 "stereo_mode: %d\n",
560                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
561                 m->h_sync_width, m->v_sync_width,
562                 m->h_back_porch, m->v_back_porch,
563                 m->h_active, m->v_active,
564                 m->h_front_porch, m->v_front_porch,
565                 m->stereo_mode);
566         mutex_unlock(&dc->lock);
567         return 0;
568 }
569
570 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
571 {
572         return single_open(file, dbg_dc_mode_show, inode->i_private);
573 }
574
575 static const struct file_operations mode_fops = {
576         .open           = dbg_dc_mode_open,
577         .read           = seq_read,
578         .llseek         = seq_lseek,
579         .release        = single_release,
580 };
581
582 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
583 {
584         struct tegra_dc *dc = s->private;
585
586         mutex_lock(&dc->lock);
587         seq_printf(s,
588                 "underflows: %llu\n"
589                 "underflows_a: %llu\n"
590                 "underflows_b: %llu\n"
591                 "underflows_c: %llu\n",
592                 dc->stats.underflows,
593                 dc->stats.underflows_a,
594                 dc->stats.underflows_b,
595                 dc->stats.underflows_c);
596         mutex_unlock(&dc->lock);
597
598         return 0;
599 }
600
601 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
602 {
603         return single_open(file, dbg_dc_stats_show, inode->i_private);
604 }
605
606 static const struct file_operations stats_fops = {
607         .open           = dbg_dc_stats_open,
608         .read           = seq_read,
609         .llseek         = seq_lseek,
610         .release        = single_release,
611 };
612
613 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
614 {
615         if (dc->debugdir)
616                 debugfs_remove_recursive(dc->debugdir);
617         dc->debugdir = NULL;
618 }
619
620 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
621 {
622         struct dentry *retval;
623
624         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
625         if (!dc->debugdir)
626                 goto remove_out;
627
628         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
629                 &regs_fops);
630         if (!retval)
631                 goto remove_out;
632
633         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
634                 &mode_fops);
635         if (!retval)
636                 goto remove_out;
637
638         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
639                 &stats_fops);
640         if (!retval)
641                 goto remove_out;
642
643         return;
644 remove_out:
645         dev_err(&dc->ndev->dev, "could not create debugfs\n");
646         tegra_dc_remove_debugfs(dc);
647 }
648
649 #else /* !CONFIG_DEBUGFS */
650 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
651 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
652 #endif /* CONFIG_DEBUGFS */
653
654 static int tegra_dc_set(struct tegra_dc *dc, int index)
655 {
656         int ret = 0;
657
658         mutex_lock(&tegra_dc_lock);
659         if (index >= TEGRA_MAX_DC) {
660                 ret = -EINVAL;
661                 goto out;
662         }
663
664         if (dc != NULL && tegra_dcs[index] != NULL) {
665                 ret = -EBUSY;
666                 goto out;
667         }
668
669         tegra_dcs[index] = dc;
670
671 out:
672         mutex_unlock(&tegra_dc_lock);
673
674         return ret;
675 }
676
677 unsigned int tegra_dc_has_multiple_dc(void)
678 {
679         unsigned int idx;
680         unsigned int cnt = 0;
681         struct tegra_dc *dc;
682
683         mutex_lock(&tegra_dc_lock);
684         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
685                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
686         mutex_unlock(&tegra_dc_lock);
687
688         return (cnt > 1);
689 }
690
691 /* get the stride size of a window.
692  * return: stride size in bytes for window win. or 0 if unavailble. */
693 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
694 {
695         u32 stride;
696
697         if (!dc->enabled)
698                 return 0;
699         BUG_ON(win > DC_N_WINDOWS);
700         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
701                 DC_CMD_DISPLAY_WINDOW_HEADER);
702         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
703         return GET_LINE_STRIDE(stride);
704 }
705 EXPORT_SYMBOL(tegra_dc_get_stride);
706
707 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
708 {
709         if (idx < TEGRA_MAX_DC)
710                 return tegra_dcs[idx];
711         else
712                 return NULL;
713 }
714 EXPORT_SYMBOL(tegra_dc_get_dc);
715
716 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
717 {
718         if (win >= dc->n_windows)
719                 return NULL;
720
721         return &dc->windows[win];
722 }
723 EXPORT_SYMBOL(tegra_dc_get_window);
724
725 static int get_topmost_window(u32 *depths, unsigned long *wins, int win_num)
726 {
727         int idx, best = -1;
728
729         for_each_set_bit(idx, wins, win_num) {
730                 if (best == -1 || depths[idx] < depths[best])
731                         best = idx;
732         }
733         clear_bit(best, wins);
734         return best;
735 }
736
737 bool tegra_dc_get_connected(struct tegra_dc *dc)
738 {
739         return dc->connected;
740 }
741 EXPORT_SYMBOL(tegra_dc_get_connected);
742
743 bool tegra_dc_hpd(struct tegra_dc *dc)
744 {
745         int sense;
746         int level;
747
748         level = gpio_get_value(dc->out->hotplug_gpio);
749
750         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
751
752         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
753                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
754 }
755 EXPORT_SYMBOL(tegra_dc_hpd);
756
757 static u32 blend_topwin(u32 flags)
758 {
759         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
760                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
761         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
762                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
763         else
764                 return BLEND(NOKEY, FIX, 0xff, 0xff);
765 }
766
767 static u32 blend_2win(int idx, unsigned long behind_mask,
768                                                 u32* flags, int xy, int win_num)
769 {
770         int other;
771
772         for (other = 0; other < win_num; other++) {
773                 if (other != idx && (xy-- == 0))
774                         break;
775         }
776         if (BIT(other) & behind_mask)
777                 return blend_topwin(flags[idx]);
778         else if (flags[other])
779                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
780         else
781                 return BLEND(NOKEY, FIX, 0x00, 0x00);
782 }
783
784 static u32 blend_3win(int idx, unsigned long behind_mask,
785                                                 u32* flags, int win_num)
786 {
787         unsigned long infront_mask;
788         int first;
789
790         infront_mask = ~(behind_mask | BIT(idx));
791         infront_mask &= (BIT(win_num) - 1);
792         first = ffs(infront_mask) - 1;
793
794         if (!infront_mask)
795                 return blend_topwin(flags[idx]);
796         else if (behind_mask && first != -1 && flags[first])
797                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
798         else
799                 return BLEND(NOKEY, FIX, 0x0, 0x0);
800 }
801
802 static void tegra_dc_set_gen1_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
803 {
804         int win_num = dc->gen1_blend_num;
805         unsigned long mask = BIT(win_num) - 1;
806
807         while (mask) {
808                 int idx = get_topmost_window(blend->z, &mask, win_num);
809
810                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
811                                 DC_CMD_DISPLAY_WINDOW_HEADER);
812                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
813                                 DC_WIN_BLEND_NOKEY);
814                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
815                                 DC_WIN_BLEND_1WIN);
816                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0,
817                                 win_num), DC_WIN_BLEND_2WIN_X);
818                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1,
819                                 win_num), DC_WIN_BLEND_2WIN_Y);
820                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags,
821                                 win_num), DC_WIN_BLEND_3WIN_XY);
822         }
823 }
824
825 static void tegra_dc_set_gen2_blending(struct tegra_dc *dc,
826                                                 struct tegra_dc_blend *blend)
827 {
828         long val;
829         int i = 0;
830
831         for (i = 0; i < DC_N_WINDOWS; i++) {
832                 if (!tegra_dc_feature_is_gen2_blender(dc, i))
833                         continue;
834
835                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
836                                 DC_CMD_DISPLAY_WINDOW_HEADER);
837
838                 if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_COVERAGE) {
839                         tegra_dc_writel(dc,
840                                         WIN_K1(0xff) |
841                                         WIN_K2(0xff) |
842                                         WIN_BLEND_ENABLE,
843                                         DC_WINBUF_BLEND_LAYER_CONTROL);
844
845                         tegra_dc_writel(dc,
846                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC |
847                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC |
848                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
849                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
850                         DC_WINBUF_BLEND_MATCH_SELECT);
851
852                         tegra_dc_writel(dc,
853                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
854                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
855                                         DC_WINBUF_BLEND_ALPHA_1BIT);
856                 } else if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_PREMULT) {
857                         tegra_dc_writel(dc,
858                                         WIN_K1(0xff) |
859                                         WIN_K2(0xff) |
860                                         WIN_BLEND_ENABLE,
861                                         DC_WINBUF_BLEND_LAYER_CONTROL);
862
863                         tegra_dc_writel(dc,
864                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 |
865                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 |
866                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
867                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
868                         DC_WINBUF_BLEND_MATCH_SELECT);
869
870                         tegra_dc_writel(dc,
871                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
872                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
873                                         DC_WINBUF_BLEND_ALPHA_1BIT);
874                 } else {
875                         tegra_dc_writel(dc,
876                                         WIN_BLEND_BYPASS,
877                                         DC_WINBUF_BLEND_LAYER_CONTROL);
878                 }
879         }
880 }
881
882 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
883 {
884         csc->yof   = 0x00f0;
885         csc->kyrgb = 0x012a;
886         csc->kur   = 0x0000;
887         csc->kvr   = 0x0198;
888         csc->kug   = 0x039b;
889         csc->kvg   = 0x032f;
890         csc->kub   = 0x0204;
891         csc->kvb   = 0x0000;
892 }
893
894 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
895 {
896         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
897         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
898         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
899         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
900         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
901         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
902         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
903         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
904 }
905
906 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
907 {
908         mutex_lock(&dc->lock);
909
910         if (!dc->enabled) {
911                 mutex_unlock(&dc->lock);
912                 return -EFAULT;
913         }
914
915         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
916                         DC_CMD_DISPLAY_WINDOW_HEADER);
917
918         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
919
920         mutex_unlock(&dc->lock);
921
922         return 0;
923 }
924 EXPORT_SYMBOL(tegra_dc_update_csc);
925
926 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
927 {
928         int i;
929         for (i = 0; i < 256; i++)
930                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
931 }
932
933 static int tegra_dc_loop_lut(struct tegra_dc *dc,
934                              struct tegra_dc_win *win,
935                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
936 {
937         struct tegra_dc_lut *lut = &win->lut;
938         struct tegra_dc_lut *global_lut = &dc->fb_lut;
939         int i;
940         for (i = 0; i < 256; i++) {
941
942                 u32 r = (u32)lut->r[i];
943                 u32 g = (u32)lut->g[i];
944                 u32 b = (u32)lut->b[i];
945
946                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
947                         r = (u32)global_lut->r[r];
948                         g = (u32)global_lut->g[g];
949                         b = (u32)global_lut->b[b];
950                 }
951
952                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
953                         return 0;
954         }
955         return 1;
956 }
957
958 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
959 {
960         if (rgb != (i | (i<<8) | (i<<16)))
961                 return 0;
962         return 1;
963 }
964
965 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
966 {
967         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
968         return 1;
969 }
970
971 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
972 {
973         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
974
975         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
976
977         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
978                 val |= CP_ENABLE;
979         else
980                 val &= ~CP_ENABLE;
981
982         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
983 }
984
985 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
986 {
987         struct tegra_dc_win *win = &dc->windows[win_idx];
988
989         mutex_lock(&dc->lock);
990
991         if (!dc->enabled) {
992                 mutex_unlock(&dc->lock);
993                 return -EFAULT;
994         }
995
996         if (fbovr > 0)
997                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
998         else if (fbovr == 0)
999                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
1000
1001         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
1002                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
1003         else
1004                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
1005
1006         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
1007                         DC_CMD_DISPLAY_WINDOW_HEADER);
1008
1009         tegra_dc_set_lut(dc, win);
1010
1011         mutex_unlock(&dc->lock);
1012
1013         tegra_dc_update_windows(&win, 1);
1014
1015         return 0;
1016 }
1017
1018 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
1019 {
1020         if (win_idx > -1)
1021                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
1022
1023         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
1024                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
1025                 if (err)
1026                         return err;
1027         }
1028
1029         return 0;
1030 }
1031 EXPORT_SYMBOL(tegra_dc_update_lut);
1032
1033 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1034 {
1035         unsigned i;
1036         unsigned v0 = 128;
1037         unsigned v1 = 0;
1038         /* linear horizontal and vertical filters */
1039         for (i = 0; i < 16; i++) {
1040                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1041                                 DC_WIN_H_FILTER_P(i));
1042
1043                 tegra_dc_writel(dc, v0,
1044                                 DC_WIN_V_FILTER_P(i));
1045                 v0 -= 8;
1046                 v1 += 8;
1047         }
1048 }
1049
1050 #ifdef CONFIG_TEGRA_DC_CMU
1051 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
1052                                                 struct tegra_dc_cmu *src_cmu)
1053 {
1054         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
1055 }
1056
1057 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1058 {
1059         u32 val;
1060         u32 i;
1061
1062         for (i = 0; i < 256; i++) {
1063                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1064                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1065         }
1066
1067         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1068         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1069         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1070         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1071         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1072         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1073         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1074         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1075         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1076
1077         for (i = 0; i < 960; i++) {
1078                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1079                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1080         }
1081 }
1082
1083 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1084 {
1085         u32 val;
1086         u32 i;
1087         bool flags;
1088
1089         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1090         if (val & CMU_ENABLE)
1091                 flags = true;
1092
1093         val &= ~CMU_ENABLE;
1094         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1095         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1096         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1097
1098         /*TODO: Sync up with frame end */
1099         mdelay(20);
1100
1101         for (i = 0; i < 256; i++) {
1102                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
1103                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
1104                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
1105                 cmu->lut1[i] = LUT1_READ_DATA(val);
1106         }
1107
1108         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
1109         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
1110         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
1111         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
1112         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
1113         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
1114         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
1115         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
1116         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
1117
1118         for (i = 0; i < 960; i++) {
1119                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
1120                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
1121                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
1122                 cmu->lut2[i] = LUT2_READ_DATA(val);
1123         }
1124 }
1125
1126 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
1127 {
1128         mutex_lock(&dc->lock);
1129
1130         if (!dc->enabled) {
1131                 mutex_unlock(&dc->lock);
1132                 return -EFAULT;
1133         }
1134
1135         if (cmu_enable) {
1136                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
1137         } else {
1138                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
1139                 return 0;
1140         }
1141
1142         tegra_dc_set_cmu(dc, &dc->cmu);
1143
1144         mutex_unlock(&dc->lock);
1145
1146         return 0;
1147 }
1148 EXPORT_SYMBOL(tegra_dc_update_cmu);
1149 #else
1150 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
1151 #define tegra_dc_set_cmu(dc, cmu)
1152 #endif
1153
1154 void tegra_dc_host_suspend(struct tegra_dc *dc)
1155 {
1156         tegra_dsi_host_suspend(dc);
1157         tegra_dc_clk_disable(dc);
1158 }
1159
1160 void tegra_dc_host_resume(struct tegra_dc *dc) {
1161         tegra_dc_clk_enable(dc);
1162         tegra_dsi_host_resume(dc);
1163 }
1164
1165 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1166                                   bool v, unsigned Bpp)
1167 {
1168         /*
1169          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1170          *           (post_scaled_size_in_pixels - 1)), MAX)
1171          * Where the value of MAX is as follows:
1172          * For V_DDA_INCREMENT: 15.0 (0xF000)
1173          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1174          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1175          */
1176
1177         fixed20_12 out = dfixed_init(out_int);
1178         u32 dda_inc;
1179         int max;
1180
1181         if (v) {
1182                 max = 15;
1183         } else {
1184                 switch (Bpp) {
1185                 default:
1186                         WARN_ON_ONCE(1);
1187                         /* fallthrough */
1188                 case 4:
1189                         max = 4;
1190                         break;
1191                 case 2:
1192                         max = 8;
1193                         break;
1194                 }
1195         }
1196
1197         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1198         in.full -= dfixed_const(1);
1199
1200         dda_inc = dfixed_div(in, out);
1201
1202         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1203
1204         return dda_inc;
1205 }
1206
1207 static inline u32 compute_initial_dda(fixed20_12 in)
1208 {
1209         return dfixed_frac(in);
1210 }
1211
1212 /* does not support updating windows on multiple dcs in one call */
1213 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1214 {
1215         struct tegra_dc *dc;
1216         unsigned long update_mask = GENERAL_ACT_REQ;
1217         unsigned long val;
1218         bool update_gen1_blend = false;
1219         bool update_gen2_blend = false;
1220         int i;
1221
1222         dc = windows[0]->dc;
1223
1224         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1225                 /* Acquire one_shot_lock to avoid race condition between
1226                  * cancellation of old delayed work and schedule of new
1227                  * delayed work. */
1228                 mutex_lock(&dc->one_shot_lock);
1229                 cancel_delayed_work_sync(&dc->one_shot_work);
1230         }
1231         mutex_lock(&dc->lock);
1232
1233         if (!dc->enabled) {
1234                 mutex_unlock(&dc->lock);
1235                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1236                         mutex_unlock(&dc->one_shot_lock);
1237                 return -EFAULT;
1238         }
1239
1240         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1241                 tegra_dc_host_resume(dc);
1242
1243         if (no_vsync)
1244                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1245         else
1246                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1247
1248         for (i = 0; i < n; i++) {
1249                 struct tegra_dc_win *win = windows[i];
1250                 unsigned h_dda;
1251                 unsigned v_dda;
1252                 fixed20_12 h_offset, v_offset;
1253                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1254                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1255                 bool yuv = tegra_dc_is_yuv(win->fmt);
1256                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1257                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1258                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1259                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1260                 const bool filter_h = win_use_h_filter(dc, win);
1261                 const bool filter_v = win_use_v_filter(dc, win);
1262
1263                 if (win->z != dc->blend.z[win->idx]) {
1264                         dc->blend.z[win->idx] = win->z;
1265                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1266                                 update_gen2_blend = true;
1267                         else
1268                                 update_gen1_blend = true;
1269                 }
1270                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1271                         dc->blend.flags[win->idx]) {
1272                         dc->blend.flags[win->idx] =
1273                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1274                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1275                                 update_gen2_blend = true;
1276                         else
1277                                 update_gen1_blend = true;
1278                 }
1279
1280                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1281                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1282
1283                 if (!no_vsync)
1284                         update_mask |= WIN_A_ACT_REQ << win->idx;
1285
1286                 if (!WIN_IS_ENABLED(win)) {
1287                         dc->windows[i].dirty = 1;
1288                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1289                         continue;
1290                 }
1291
1292                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1293                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1294
1295                 tegra_dc_writel(dc,
1296                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1297                                 DC_WIN_POSITION);
1298                 tegra_dc_writel(dc,
1299                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1300                                 DC_WIN_SIZE);
1301
1302                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
1303                         tegra_dc_writel(dc,
1304                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1305                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1306                                         DC_WIN_PRESCALED_SIZE);
1307
1308                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1309                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1310                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1311                                         DC_WIN_DDA_INCREMENT);
1312                         h_dda = compute_initial_dda(win->x);
1313                         v_dda = compute_initial_dda(win->y);
1314                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1315                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1316                 }
1317
1318 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1319                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1320                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1321 #endif
1322                 tegra_dc_writel(dc,
1323                                 (unsigned long)win->phys_addr,
1324                                 DC_WINBUF_START_ADDR);
1325
1326                 if (!yuvp) {
1327                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1328                 } else {
1329                         tegra_dc_writel(dc,
1330                                         (unsigned long)win->phys_addr_u,
1331                                         DC_WINBUF_START_ADDR_U);
1332                         tegra_dc_writel(dc,
1333                                         (unsigned long)win->phys_addr_v,
1334                                         DC_WINBUF_START_ADDR_V);
1335                         tegra_dc_writel(dc,
1336                                         LINE_STRIDE(win->stride) |
1337                                         UV_LINE_STRIDE(win->stride_uv),
1338                                         DC_WIN_LINE_STRIDE);
1339                 }
1340
1341                 h_offset = win->x;
1342                 if (invert_h) {
1343                         h_offset.full += win->w.full - dfixed_const(1);
1344                 }
1345
1346                 v_offset = win->y;
1347                 if (invert_v) {
1348                         v_offset.full += win->h.full - dfixed_const(1);
1349                 }
1350
1351                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1352                                 DC_WINBUF_ADDR_H_OFFSET);
1353                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1354                                 DC_WINBUF_ADDR_V_OFFSET);
1355
1356                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1357                         if (WIN_IS_TILED(win))
1358                                 tegra_dc_writel(dc,
1359                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1360                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1361                                                 DC_WIN_BUFFER_ADDR_MODE);
1362                         else
1363                                 tegra_dc_writel(dc,
1364                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1365                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1366                                                 DC_WIN_BUFFER_ADDR_MODE);
1367                 }
1368
1369                 val = WIN_ENABLE;
1370                 if (yuv)
1371                         val |= CSC_ENABLE;
1372                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1373                         val |= COLOR_EXPAND;
1374
1375                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1376                         val |= CP_ENABLE;
1377
1378                 if (filter_h)
1379                         val |= H_FILTER_ENABLE;
1380                 if (filter_v)
1381                         val |= V_FILTER_ENABLE;
1382
1383                 if (invert_h)
1384                         val |= H_DIRECTION_DECREMENT;
1385                 if (invert_v)
1386                         val |= V_DIRECTION_DECREMENT;
1387
1388                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1389
1390 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1391                 if (win->global_alpha == 255)
1392                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1393                 else
1394                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1395                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1396 #endif
1397
1398                 win->dirty = no_vsync ? 0 : 1;
1399
1400                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1401                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1402                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1403                         __func__, win->idx, win->z,
1404                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1405                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1406                         win->out_x, win->out_y, win->out_w, win->out_h,
1407                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1408                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1409                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1410                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1411         }
1412
1413         if (update_gen1_blend || update_gen2_blend) {
1414                 if (update_gen1_blend)
1415                         tegra_dc_set_gen1_blending(dc, &dc->blend);
1416                 if (update_gen2_blend)
1417                         tegra_dc_set_gen2_blending(dc, &dc->blend);
1418                 for (i = 0; i < DC_N_WINDOWS; i++) {
1419                         if (!no_vsync)
1420                                 dc->windows[i].dirty = 1;
1421                         update_mask |= WIN_A_ACT_REQ << i;
1422                 }
1423         }
1424
1425         tegra_dc_set_dynamic_emc(windows, n);
1426
1427         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1428
1429         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1430         if (!no_vsync) {
1431                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1432                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1433         } else {
1434                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1435                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1436         }
1437
1438         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1439                 schedule_delayed_work(&dc->one_shot_work,
1440                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1441
1442         /* update EMC clock if calculated bandwidth has changed */
1443         tegra_dc_program_bandwidth(dc, false);
1444
1445         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1446                 update_mask |= NC_HOST_TRIG;
1447
1448         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1449         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1450
1451         mutex_unlock(&dc->lock);
1452         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1453                 mutex_unlock(&dc->one_shot_lock);
1454
1455         return 0;
1456 }
1457 EXPORT_SYMBOL(tegra_dc_update_windows);
1458
1459 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1460 {
1461         return dc->syncpt[i].id;
1462 }
1463 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1464
1465 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1466 {
1467         u32 max;
1468
1469         mutex_lock(&dc->lock);
1470         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1471                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1472         dc->syncpt[i].max = max;
1473         mutex_unlock(&dc->lock);
1474
1475         return max;
1476 }
1477
1478 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1479 {
1480         mutex_lock(&dc->lock);
1481         if ( dc->enabled )
1482                 while (dc->syncpt[i].min < val) {
1483                         dc->syncpt[i].min++;
1484                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1485                 }
1486         mutex_unlock(&dc->lock);
1487 }
1488
1489 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1490                                              int n)
1491 {
1492         int i;
1493
1494         for (i = 0; i < n; i++) {
1495                 if (windows[i]->dirty)
1496                         return false;
1497         }
1498
1499         return true;
1500 }
1501
1502 /* does not support syncing windows on multiple dcs in one call */
1503 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1504 {
1505         int ret;
1506         if (n < 1 || n > DC_N_WINDOWS)
1507                 return -EINVAL;
1508
1509         if (!windows[0]->dc->enabled)
1510                 return -EFAULT;
1511
1512         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1513                         windows[0]->dc->ndev->name);
1514         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1515                                          tegra_dc_windows_are_clean(windows, n),
1516                                          HZ);
1517         trace_printk("%s:After wait_event_interruptible_timeout\n",
1518                         windows[0]->dc->ndev->name);
1519         return ret;
1520 }
1521 EXPORT_SYMBOL(tegra_dc_sync_windows);
1522
1523 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1524 {
1525 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1526         return clk_get_rate(dc->clk);
1527 #else
1528         return 27000000;
1529 #endif
1530 }
1531
1532 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1533 {
1534         unsigned long rate;
1535         unsigned long div;
1536
1537         rate = tegra_dc_clk_get_rate(dc);
1538
1539         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1540
1541         if (div < 2)
1542                 return 0;
1543
1544         return rate * 2 / div;
1545 }
1546
1547 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1548 {
1549         unsigned long rate;
1550         unsigned long div;
1551
1552         rate = clk_get_rate(parent);
1553
1554         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1555
1556         if (div < 2)
1557                 return 0;
1558
1559         return rate * 2 / div;
1560 }
1561
1562 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1563 {
1564         int pclk;
1565
1566         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1567                 unsigned long rate;
1568                 struct clk *parent_clk =
1569                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1570
1571                 if (dc->out->parent_clk_backup &&
1572                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1573                         rate = tegra_dc_pclk_predict_rate(
1574                                 parent_clk, dc->mode.pclk);
1575                         /* use pll_d as last resort */
1576                         if (rate < (dc->mode.pclk / 100 * 99) ||
1577                             rate > (dc->mode.pclk / 100 * 109))
1578                                 parent_clk = clk_get_sys(
1579                                         NULL, dc->out->parent_clk_backup);
1580                 }
1581
1582                 if (clk_get_parent(clk) != parent_clk)
1583                         clk_set_parent(clk, parent_clk);
1584
1585                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1586                         struct clk *base_clk = clk_get_parent(parent_clk);
1587
1588                         /* Assuming either pll_d or pll_d2 is used */
1589                         rate = dc->mode.pclk * 2;
1590
1591                         if (rate != clk_get_rate(base_clk))
1592                                 clk_set_rate(base_clk, rate);
1593                 }
1594         }
1595
1596         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1597                 unsigned long rate;
1598                 struct clk *parent_clk =
1599                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1600                 struct clk *base_clk = clk_get_parent(parent_clk);
1601
1602                 /*
1603                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1604                  * The required rate needs to be setup at 4x multiplier,
1605                  * as out0 is 1/2 of the actual PLL output.
1606                  */
1607
1608                 rate = dc->mode.pclk * 4;
1609                 if (rate != clk_get_rate(base_clk))
1610                         clk_set_rate(base_clk, rate);
1611
1612                 if (clk_get_parent(clk) != parent_clk)
1613                         clk_set_parent(clk, parent_clk);
1614         }
1615
1616         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1617                 unsigned long rate;
1618                 struct clk *parent_clk;
1619                 struct clk *base_clk;
1620
1621                 if (clk == dc->clk) {
1622                         parent_clk = clk_get_sys(NULL,
1623                                         dc->out->parent_clk ? : "pll_d_out0");
1624                         base_clk = clk_get_parent(parent_clk);
1625                         tegra_clk_cfg_ex(base_clk,
1626                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1627                 } else {
1628                         if (dc->pdata->default_out->dsi->dsi_instance) {
1629                                 parent_clk = clk_get_sys(NULL,
1630                                         dc->out->parent_clk ? : "pll_d2_out0");
1631                                 base_clk = clk_get_parent(parent_clk);
1632                                 tegra_clk_cfg_ex(base_clk,
1633                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1634                         } else {
1635                                 parent_clk = clk_get_sys(NULL,
1636                                         dc->out->parent_clk ? : "pll_d_out0");
1637                                 base_clk = clk_get_parent(parent_clk);
1638                                 tegra_clk_cfg_ex(base_clk,
1639                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1640                         }
1641                 }
1642
1643                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1644                 if (rate != clk_get_rate(base_clk))
1645                         clk_set_rate(base_clk, rate);
1646
1647                 if (clk_get_parent(clk) != parent_clk)
1648                         clk_set_parent(clk, parent_clk);
1649         }
1650
1651         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1652         tegra_dvfs_set_rate(clk, pclk);
1653 }
1654
1655 /* return non-zero if constraint is violated */
1656 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1657 {
1658         long a, b;
1659
1660         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1661         a = 0;
1662
1663         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1664         b = mode->h_front_porch - 1;
1665
1666         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1667         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1668                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1669         /* check Constraint 1 and 6 */
1670         if (a > b)
1671                 return 1;
1672
1673         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1674         if (mode->h_sync_width < 1)
1675                 return 4;
1676
1677         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1678         if (mode->h_active < 16)
1679                 return 7;
1680
1681         if (href) {
1682                 if (b > a && a % 2)
1683                         *href = a + 1; /* use smallest even value */
1684                 else
1685                         *href = a; /* even or only possible value */
1686         }
1687
1688         return 0;
1689 }
1690
1691 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1692 {
1693         long a;
1694         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1695
1696         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1697         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1698                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1699
1700         /* Constraint 6 */
1701         if (mode->v_front_porch < a + 1)
1702                 a = mode->v_front_porch - 1;
1703
1704         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1705         if (mode->v_sync_width < 1)
1706                 return 4;
1707
1708         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1709         if (mode->v_active < 16)
1710                 return 7;
1711
1712         if (vref)
1713                 *vref = a;
1714         return 0;
1715 }
1716
1717 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1718 {
1719         int ret;
1720         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1721         if (ret)
1722                 return ret;
1723         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1724         if (ret)
1725                 return ret;
1726
1727         return 0;
1728 }
1729
1730 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1731 {
1732         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1733         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1734                 return false;
1735
1736         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1737         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1738                 return false;
1739
1740         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1741          * (vertical blank). */
1742         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1743                 return false;
1744
1745         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1746         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1747                 return false;
1748
1749         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1750         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1751                 return false;
1752
1753         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1754          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1755         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1756                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1757                 return false;
1758
1759         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1760         if (mode->h_active < 16 || mode->v_active < 16)
1761                 return false;
1762
1763         return true;
1764 }
1765
1766 #ifdef DEBUG
1767 /* return in 1000ths of a Hertz */
1768 static int calc_refresh(const struct tegra_dc_mode *m)
1769 {
1770         long h_total, v_total, refresh;
1771         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1772                 m->h_sync_width;
1773         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1774                 m->v_sync_width;
1775         refresh = m->pclk / h_total;
1776         refresh *= 1000;
1777         refresh /= v_total;
1778         return refresh;
1779 }
1780
1781 static void print_mode(struct tegra_dc *dc,
1782                         const struct tegra_dc_mode *mode, const char *note)
1783 {
1784         if (mode) {
1785                 int refresh = calc_refresh(dc, mode);
1786                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1787                         note ? note : "",
1788                         mode->h_active, mode->v_active,
1789                         refresh / 1000, refresh % 1000,
1790                         mode->pclk);
1791         }
1792 }
1793 #else /* !DEBUG */
1794 static inline void print_mode(struct tegra_dc *dc,
1795                         const struct tegra_dc_mode *mode, const char *note) { }
1796 #endif /* DEBUG */
1797
1798 static inline void enable_dc_irq(unsigned int irq)
1799 {
1800 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1801         enable_irq(irq);
1802 #else
1803         /* Always disable DC interrupts on FPGA. */
1804         disable_irq(irq);
1805 #endif
1806 }
1807
1808 static inline void disable_dc_irq(unsigned int irq)
1809 {
1810         disable_irq(irq);
1811 }
1812
1813 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1814 {
1815         u32 val;
1816
1817         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1818         val |= int_val;
1819         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1820 }
1821
1822 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1823 {
1824         u32 val;
1825
1826         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1827         val &= ~int_val;
1828         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1829 }
1830
1831 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1832 {
1833         unsigned long val;
1834         unsigned long rate;
1835         unsigned long div;
1836         unsigned long pclk;
1837
1838         print_mode(dc, mode, __func__);
1839
1840         /* use default EMC rate when switching modes */
1841         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1842         tegra_dc_program_bandwidth(dc, true);
1843
1844         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1845         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1846                         DC_DISP_REF_TO_SYNC);
1847         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1848                         DC_DISP_SYNC_WIDTH);
1849         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1850                         DC_DISP_BACK_PORCH);
1851         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1852                         DC_DISP_DISP_ACTIVE);
1853         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1854                         DC_DISP_FRONT_PORCH);
1855
1856         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1857                         DC_DISP_DATA_ENABLE_OPTIONS);
1858
1859         /* TODO: MIPI/CRT/HDMI clock cals */
1860
1861         val = DISP_DATA_FORMAT_DF1P1C;
1862
1863         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1864                 val |= DISP_DATA_ALIGNMENT_MSB;
1865         else
1866                 val |= DISP_DATA_ALIGNMENT_LSB;
1867
1868         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1869                 val |= DISP_DATA_ORDER_RED_BLUE;
1870         else
1871                 val |= DISP_DATA_ORDER_BLUE_RED;
1872
1873         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1874
1875         rate = tegra_dc_clk_get_rate(dc);
1876
1877         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1878         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1879         if (pclk < (mode->pclk / 100 * 99) ||
1880             pclk > (mode->pclk / 100 * 109)) {
1881                 dev_err(&dc->ndev->dev,
1882                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1883                         rate, mode->pclk,
1884                         pclk, (mode->pclk / 100 * 99),
1885                         (mode->pclk / 100 * 109));
1886                 return -EINVAL;
1887         }
1888
1889         div = (rate * 2 / pclk) - 2;
1890         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1891
1892         tegra_dc_writel(dc, 0x00010001,
1893                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1894         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1895                         DC_DISP_DISP_CLOCK_CONTROL);
1896
1897 #ifdef CONFIG_SWITCH
1898         switch_set_state(&dc->modeset_switch,
1899                          (mode->h_active << 16) | mode->v_active);
1900 #endif
1901
1902         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1903         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1904
1905         print_mode_info(dc, dc->mode);
1906         return 0;
1907 }
1908
1909
1910 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1911 {
1912         memcpy(&dc->mode, mode, sizeof(dc->mode));
1913
1914         print_mode(dc, mode, __func__);
1915
1916         return 0;
1917 }
1918 EXPORT_SYMBOL(tegra_dc_set_mode);
1919
1920 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1921                 const struct fb_videomode *fbmode, bool stereo_mode)
1922 {
1923         struct tegra_dc_mode mode;
1924
1925         if (!fbmode->pixclock)
1926                 return -EINVAL;
1927
1928         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1929         mode.h_sync_width = fbmode->hsync_len;
1930         mode.v_sync_width = fbmode->vsync_len;
1931         mode.h_back_porch = fbmode->left_margin;
1932         mode.v_back_porch = fbmode->upper_margin;
1933         mode.h_active = fbmode->xres;
1934         mode.v_active = fbmode->yres;
1935         mode.h_front_porch = fbmode->right_margin;
1936         mode.v_front_porch = fbmode->lower_margin;
1937         mode.stereo_mode = stereo_mode;
1938         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1939                 /* HDMI controller requires h_ref=1, v_ref=1 */
1940                 mode.h_ref_to_sync = 1;
1941                 mode.v_ref_to_sync = 1;
1942         } else {
1943                 calc_ref_to_sync(&mode);
1944         }
1945         if (!check_ref_to_sync(&mode)) {
1946                 dev_err(&dc->ndev->dev,
1947                                 "Display timing doesn't meet restrictions.\n");
1948                 return -EINVAL;
1949         }
1950         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1951                 mode.h_active, mode.v_active, mode.pclk,
1952                 mode.h_ref_to_sync, mode.v_ref_to_sync
1953         );
1954
1955 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1956         /* Double the pixel clock and update v_active only for frame packed mode */
1957         if (mode.stereo_mode) {
1958                 mode.pclk *= 2;
1959                 /* total v_active = yres*2 + activespace */
1960                 mode.v_active = fbmode->yres*2 +
1961                                 fbmode->vsync_len +
1962                                 fbmode->upper_margin +
1963                                 fbmode->lower_margin;
1964         }
1965 #endif
1966
1967         mode.flags = 0;
1968
1969         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1970                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1971
1972         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1973                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1974
1975         return tegra_dc_set_mode(dc, &mode);
1976 }
1977 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1978
1979 void
1980 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1981 {
1982         unsigned int ctrl;
1983         unsigned long out_sel;
1984         unsigned long cmd_state;
1985
1986         mutex_lock(&dc->lock);
1987         if (!dc->enabled) {
1988                 mutex_unlock(&dc->lock);
1989                 return;
1990         }
1991
1992         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1993                 tegra_dc_host_resume(dc);
1994
1995         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1996                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1997                 cfg->clk_select);
1998
1999         /* The new value should be effected immediately */
2000         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
2001         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
2002
2003         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
2004                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
2005         else
2006                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
2007
2008         switch (cfg->which_pwm) {
2009         case TEGRA_PWM_PM0:
2010                 /* Select the LM0 on PM0 */
2011                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2012                 out_sel &= ~(7 << 0);
2013                 out_sel |= (3 << 0);
2014                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2015                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2016                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2017                 break;
2018         case TEGRA_PWM_PM1:
2019                 /* Select the LM1 on PM1 */
2020                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2021                 out_sel &= ~(7 << 4);
2022                 out_sel |= (3 << 4);
2023                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2024                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2025                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2026                 break;
2027         default:
2028                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2029                 break;
2030         }
2031         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2032         mutex_unlock(&dc->lock);
2033 }
2034 EXPORT_SYMBOL(tegra_dc_config_pwm);
2035
2036 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2037                                 const struct tegra_dc_out_pin *pins,
2038                                 const unsigned int n_pins)
2039 {
2040         unsigned int i;
2041
2042         int name;
2043         int pol;
2044
2045         u32 pol1, pol3;
2046
2047         u32 set1, unset1;
2048         u32 set3, unset3;
2049
2050         set1 = set3 = unset1 = unset3 = 0;
2051
2052         for (i = 0; i < n_pins; i++) {
2053                 name = (pins + i)->name;
2054                 pol  = (pins + i)->pol;
2055
2056                 /* set polarity by name */
2057                 switch (name) {
2058                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2059                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2060                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2061                         else
2062                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2063                         break;
2064                 case TEGRA_DC_OUT_PIN_H_SYNC:
2065                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2066                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2067                         else
2068                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2069                         break;
2070                 case TEGRA_DC_OUT_PIN_V_SYNC:
2071                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2072                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2073                         else
2074                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2075                         break;
2076                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2077                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2078                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2079                         else
2080                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2081                         break;
2082                 default:
2083                         printk("Invalid argument in function %s\n",
2084                                __FUNCTION__);
2085                         break;
2086                 }
2087         }
2088
2089         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2090         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2091
2092         pol1 |= set1;
2093         pol1 &= ~unset1;
2094
2095         pol3 |= set3;
2096         pol3 &= ~unset3;
2097
2098         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2099         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2100 }
2101
2102 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2103 {
2104         dc->out = out;
2105
2106         if (out->n_modes > 0)
2107                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2108
2109         switch (out->type) {
2110         case TEGRA_DC_OUT_RGB:
2111                 dc->out_ops = &tegra_dc_rgb_ops;
2112                 break;
2113
2114         case TEGRA_DC_OUT_HDMI:
2115                 dc->out_ops = &tegra_dc_hdmi_ops;
2116                 break;
2117
2118         case TEGRA_DC_OUT_DSI:
2119                 dc->out_ops = &tegra_dc_dsi_ops;
2120                 break;
2121
2122         default:
2123                 dc->out_ops = NULL;
2124                 break;
2125         }
2126
2127         if (dc->out_ops && dc->out_ops->init)
2128                 dc->out_ops->init(dc);
2129
2130 }
2131
2132 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2133 {
2134         if (dc->out)
2135                 return dc->out->height;
2136         else
2137                 return 0;
2138 }
2139 EXPORT_SYMBOL(tegra_dc_get_out_height);
2140
2141 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2142 {
2143         if (dc->out)
2144                 return dc->out->width;
2145         else
2146                 return 0;
2147 }
2148 EXPORT_SYMBOL(tegra_dc_get_out_width);
2149
2150 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2151 {
2152         if (dc->out && dc->out->max_pixclock)
2153                 return dc->out->max_pixclock;
2154         else
2155                 return 0;
2156 }
2157 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2158
2159 void tegra_dc_enable_crc(struct tegra_dc *dc)
2160 {
2161         u32 val;
2162         tegra_dc_io_start(dc);
2163
2164         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2165                 CRC_ENABLE_ENABLE;
2166         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2167         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2168         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2169 }
2170
2171 void tegra_dc_disable_crc(struct tegra_dc *dc)
2172 {
2173         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2174         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2175         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2176
2177         tegra_dc_io_end(dc);
2178 }
2179
2180 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2181 {
2182         int crc = 0;
2183
2184         if (!dc) {
2185                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2186                 goto crc_error;
2187         }
2188
2189 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2190         /* TODO: Replace mdelay with code to sync VBlANK, since
2191          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2192         mdelay(TEGRA_CRC_LATCHED_DELAY);
2193 #endif
2194
2195         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2196 crc_error:
2197         return crc;
2198 }
2199
2200 static void tegra_dc_vblank(struct work_struct *work)
2201 {
2202         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2203         bool nvsd_updated = false;
2204
2205         mutex_lock(&dc->lock);
2206
2207         if (!dc->enabled) {
2208                 mutex_unlock(&dc->lock);
2209                 return;
2210         }
2211
2212         /* use the new frame's bandwidth setting instead of max(current, new),
2213          * skip this if we're using tegra_dc_one_shot_worker() */
2214         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2215                 tegra_dc_program_bandwidth(dc, true);
2216
2217         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2218         if (!tegra_dc_windows_are_dirty(dc))
2219                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2220
2221         /* Update the SD brightness */
2222         if (dc->enabled && dc->out->sd_settings) {
2223                 nvsd_updated = nvsd_update_brightness(dc);
2224                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2225                  * V_BLANK_NVSD bit of vblank ref-count. */
2226                 if (nvsd_updated) {
2227                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2228                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2229                 } else {
2230                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2231                 }
2232         }
2233
2234         /* Mask vblank interrupt if ref-count is zero. */
2235         if (!dc->vblank_ref_count)
2236                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2237
2238         mutex_unlock(&dc->lock);
2239
2240         /* Do the actual brightness update outside of the mutex */
2241         if (nvsd_updated && dc->out->sd_settings &&
2242             dc->out->sd_settings->bl_device) {
2243
2244                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2245                 struct backlight_device *bl = platform_get_drvdata(pdev);
2246                 if (bl)
2247                         backlight_update_status(bl);
2248         }
2249 }
2250
2251 static void tegra_dc_one_shot_worker(struct work_struct *work)
2252 {
2253         struct tegra_dc *dc = container_of(
2254                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2255         mutex_lock(&dc->lock);
2256
2257         /* memory client has gone idle */
2258         tegra_dc_clear_bandwidth(dc);
2259
2260         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2261                 tegra_dc_host_suspend(dc);
2262
2263         mutex_unlock(&dc->lock);
2264 }
2265
2266 /* return an arbitrarily large number if count overflow occurs.
2267  * make it a nice base-10 number to show up in stats output */
2268 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2269 {
2270         unsigned count = tegra_dc_readl(dc, reg);
2271         tegra_dc_writel(dc, 0, reg);
2272         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2273 }
2274
2275 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2276 {
2277         u32 val;
2278         int i;
2279
2280         dc->stats.underflows++;
2281         if (dc->underflow_mask & WIN_A_UF_INT) {
2282                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2283                         DC_WINBUF_AD_UFLOW_STATUS);
2284                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2285         }
2286         if (dc->underflow_mask & WIN_B_UF_INT) {
2287                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2288                         DC_WINBUF_BD_UFLOW_STATUS);
2289                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2290         }
2291         if (dc->underflow_mask & WIN_C_UF_INT) {
2292                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2293                         DC_WINBUF_CD_UFLOW_STATUS);
2294                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2295         }
2296
2297         /* Check for any underflow reset conditions */
2298         for (i = 0; i < DC_N_WINDOWS; i++) {
2299                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2300                         dc->windows[i].underflows++;
2301
2302 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2303                         if (dc->windows[i].underflows > 4) {
2304                                 schedule_work(&dc->reset_work);
2305                                 /* reset counter */
2306                                 dc->windows[i].underflows = 0;
2307                                 trace_printk("%s:Reset work scheduled for "
2308                                                 "window %c\n",
2309                                                 dc->ndev->name, (65 + i));
2310                         }
2311 #endif
2312 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2313                         if (dc->windows[i].underflows > 4) {
2314                                 printk("%s:dc in underflow state."
2315                                         " enable UF_LINE_FLUSH to clear up\n",
2316                                         __func__);
2317                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2318                                                 DC_DISP_DISP_MISC_CONTROL);
2319                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2320                                                 DC_CMD_STATE_CONTROL);
2321                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2322                                                 DC_CMD_STATE_CONTROL);
2323
2324                                 tegra_dc_writel(dc, 0,
2325                                                 DC_DISP_DISP_MISC_CONTROL);
2326                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2327                                                 DC_CMD_STATE_CONTROL);
2328                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2329                                                 DC_CMD_STATE_CONTROL);
2330                         }
2331 #endif
2332                 } else {
2333                         dc->windows[i].underflows = 0;
2334                 }
2335         }
2336
2337         /* Clear the underflow mask now that we've checked it. */
2338         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2339         dc->underflow_mask = 0;
2340         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2341         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2342         print_underflow_info(dc);
2343 }
2344
2345 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2346 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2347 {
2348 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2349         u32 val;
2350
2351         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2352         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
2353             return true;
2354 #endif
2355         return false;
2356 }
2357
2358 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2359 {
2360         u32 val, i;
2361         u32 completed = 0;
2362         u32 dirty = 0;
2363
2364         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2365         for (i = 0; i < DC_N_WINDOWS; i++) {
2366                 if (!(val & (WIN_A_ACT_REQ << i))) {
2367                         dc->windows[i].dirty = 0;
2368                         completed = 1;
2369                 } else {
2370                         dirty = 1;
2371                 }
2372         }
2373
2374         if (!dirty) {
2375                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2376                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2377         }
2378
2379         if (completed)
2380                 wake_up(&dc->wq);
2381 }
2382
2383 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2384 {
2385         if (status & V_BLANK_INT) {
2386                 /* Sync up windows. */
2387                 tegra_dc_trigger_windows(dc);
2388
2389                 /* Schedule any additional bottom-half vblank actvities. */
2390                 schedule_work(&dc->vblank_work);
2391         }
2392
2393         if (status & FRAME_END_INT) {
2394                 /* Mark the frame_end as complete. */
2395                 if (!completion_done(&dc->frame_end_complete))
2396                         complete(&dc->frame_end_complete);
2397         }
2398 }
2399
2400 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2401 {
2402         /* Schedule any additional bottom-half vblank actvities. */
2403         if (status & V_BLANK_INT)
2404                 schedule_work(&dc->vblank_work);
2405
2406         if (status & FRAME_END_INT) {
2407                 /* Mark the frame_end as complete. */
2408                 if (!completion_done(&dc->frame_end_complete))
2409                         complete(&dc->frame_end_complete);
2410
2411                 tegra_dc_trigger_windows(dc);
2412         }
2413 }
2414 #endif
2415
2416 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2417 {
2418 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2419         struct tegra_dc *dc = ptr;
2420         unsigned long status;
2421         unsigned long underflow_mask;
2422         u32 val;
2423
2424         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
2425                 WARN(1, "IRQ when DC not powered!\n");
2426                 tegra_dc_io_start(dc);
2427                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2428                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2429                 tegra_dc_io_end(dc);
2430                 return IRQ_HANDLED;
2431         }
2432
2433         /* clear all status flags except underflow, save those for the worker */
2434         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2435         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2436         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2437         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2438
2439         /*
2440          * Overlays can get thier internal state corrupted during and underflow
2441          * condition.  The only way to fix this state is to reset the DC.
2442          * if we get 4 consecutive frames with underflows, assume we're
2443          * hosed and reset.
2444          */
2445         underflow_mask = status & ALL_UF_INT;
2446
2447         /* Check underflow */
2448         if (underflow_mask) {
2449                 dc->underflow_mask |= underflow_mask;
2450                 schedule_delayed_work(&dc->underflow_work,
2451                         msecs_to_jiffies(1));
2452         }
2453
2454         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2455                 tegra_dc_one_shot_irq(dc, status);
2456         else
2457                 tegra_dc_continuous_irq(dc, status);
2458
2459         return IRQ_HANDLED;
2460 #else /* CONFIG_TEGRA_SILICON_PLATFORM */
2461         return IRQ_NONE;
2462 #endif /* !CONFIG_TEGRA_SILICON_PLATFORM */
2463 }
2464
2465 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2466 {
2467         u32 color_control;
2468
2469         switch (dc->out->depth) {
2470         case 3:
2471                 color_control = BASE_COLOR_SIZE111;
2472                 break;
2473
2474         case 6:
2475                 color_control = BASE_COLOR_SIZE222;
2476                 break;
2477
2478         case 8:
2479                 color_control = BASE_COLOR_SIZE332;
2480                 break;
2481
2482         case 9:
2483                 color_control = BASE_COLOR_SIZE333;
2484                 break;
2485
2486         case 12:
2487                 color_control = BASE_COLOR_SIZE444;
2488                 break;
2489
2490         case 15:
2491                 color_control = BASE_COLOR_SIZE555;
2492                 break;
2493
2494         case 16:
2495                 color_control = BASE_COLOR_SIZE565;
2496                 break;
2497
2498         case 18:
2499                 color_control = BASE_COLOR_SIZE666;
2500                 break;
2501
2502         default:
2503                 color_control = BASE_COLOR_SIZE888;
2504                 break;
2505         }
2506
2507         switch (dc->out->dither) {
2508         case TEGRA_DC_DISABLE_DITHER:
2509                 color_control |= DITHER_CONTROL_DISABLE;
2510                 break;
2511         case TEGRA_DC_ORDERED_DITHER:
2512                 color_control |= DITHER_CONTROL_ORDERED;
2513                 break;
2514         case TEGRA_DC_ERRDIFF_DITHER:
2515                 /* The line buffer for error-diffusion dither is limited
2516                  * to 1280 pixels per line. This limits the maximum
2517                  * horizontal active area size to 1280 pixels when error
2518                  * diffusion is enabled.
2519                  */
2520                 BUG_ON(dc->mode.h_active > 1280);
2521                 color_control |= DITHER_CONTROL_ERRDIFF;
2522                 break;
2523         }
2524
2525 #ifdef CONFIG_TEGRA_DC_CMU
2526         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
2527                 color_control |= CMU_ENABLE;
2528 #endif
2529
2530         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2531 }
2532
2533 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2534 {
2535         u32 syncpt_id;
2536
2537         switch (dc->ndev->id) {
2538         case 0:
2539                 switch (idx) {
2540                 case 0:
2541                         syncpt_id = NVSYNCPT_DISP0_A;
2542                         break;
2543                 case 1:
2544                         syncpt_id = NVSYNCPT_DISP0_B;
2545                         break;
2546                 case 2:
2547                         syncpt_id = NVSYNCPT_DISP0_C;
2548                         break;
2549                 default:
2550                         BUG();
2551                         break;
2552                 }
2553                 break;
2554         case 1:
2555                 switch (idx) {
2556                 case 0:
2557                         syncpt_id = NVSYNCPT_DISP1_A;
2558                         break;
2559                 case 1:
2560                         syncpt_id = NVSYNCPT_DISP1_B;
2561                         break;
2562                 case 2:
2563                         syncpt_id = NVSYNCPT_DISP1_C;
2564                         break;
2565                 default:
2566                         BUG();
2567                         break;
2568                 }
2569                 break;
2570         default:
2571                 BUG();
2572                 break;
2573         }
2574
2575         return syncpt_id;
2576 }
2577
2578 static int tegra_dc_init(struct tegra_dc *dc)
2579 {
2580         int i;
2581
2582         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2583         if (dc->ndev->id == 0) {
2584                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2585                                       TEGRA_MC_PRIO_MED);
2586                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2587                                       TEGRA_MC_PRIO_MED);
2588                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2589                                       TEGRA_MC_PRIO_MED);
2590                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2591                                       TEGRA_MC_PRIO_MED);
2592                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2593                                       TEGRA_MC_PRIO_HIGH);
2594         } else if (dc->ndev->id == 1) {
2595                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2596                                       TEGRA_MC_PRIO_MED);
2597                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2598                                       TEGRA_MC_PRIO_MED);
2599                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2600                                       TEGRA_MC_PRIO_MED);
2601                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2602                                       TEGRA_MC_PRIO_MED);
2603                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2604                                       TEGRA_MC_PRIO_HIGH);
2605         }
2606         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2607                         DC_CMD_CONT_SYNCPT_VSYNC);
2608         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2609         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2610         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2611         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2612 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2613         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2614 #endif
2615         /* enable interrupts for vblank, frame_end and underflows */
2616         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2617                 DC_CMD_INT_ENABLE);
2618         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2619
2620         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2621
2622         tegra_dc_set_color_control(dc);
2623         for (i = 0; i < DC_N_WINDOWS; i++) {
2624                 struct tegra_dc_win *win = &dc->windows[i];
2625                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2626                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2627                 tegra_dc_set_csc(dc, &win->csc);
2628                 tegra_dc_set_lut(dc, win);
2629                 tegra_dc_set_scaling_filter(dc);
2630         }
2631
2632         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
2633         tegra_dc_set_cmu(dc, &dc->cmu);
2634
2635         for (i = 0; i < dc->n_windows; i++) {
2636                 u32 syncpt = get_syncpt(dc, i);
2637
2638                 dc->syncpt[i].id = syncpt;
2639
2640                 dc->syncpt[i].min = dc->syncpt[i].max =
2641                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
2642         }
2643
2644         print_mode(dc, &dc->mode, __func__);
2645
2646         if (dc->mode.pclk)
2647                 if (tegra_dc_program_mode(dc, &dc->mode))
2648                         return -EINVAL;
2649
2650         /* Initialize SD AFTER the modeset.
2651            nvsd_init handles the sd_settings = NULL case. */
2652         nvsd_init(dc, dc->out->sd_settings);
2653
2654         return 0;
2655 }
2656
2657 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2658 {
2659         int failed_init = 0;
2660
2661         if (dc->out->enable)
2662                 dc->out->enable();
2663
2664         tegra_dc_setup_clk(dc, dc->clk);
2665         tegra_dc_clk_enable(dc);
2666
2667         /* do not accept interrupts during initialization */
2668         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2669         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2670
2671         enable_dc_irq(dc->irq);
2672
2673         failed_init = tegra_dc_init(dc);
2674         if (failed_init) {
2675                 _tegra_dc_controller_disable(dc);
2676                 return false;
2677         }
2678
2679         if (dc->out_ops && dc->out_ops->enable)
2680                 dc->out_ops->enable(dc);
2681
2682         if (dc->out->postpoweron)
2683                 dc->out->postpoweron();
2684
2685         /* force a full blending update */
2686         dc->blend.z[0] = -1;
2687
2688         tegra_dc_ext_enable(dc->ext);
2689
2690         trace_printk("%s:enable\n", dc->ndev->name);
2691         return true;
2692 }
2693
2694 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2695 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2696 {
2697         bool ret = true;
2698
2699         if (dc->out->enable)
2700                 dc->out->enable();
2701
2702         tegra_dc_setup_clk(dc, dc->clk);
2703         tegra_dc_clk_enable(dc);
2704
2705         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2706                 mutex_lock(&tegra_dcs[1]->lock);
2707                 disable_irq(tegra_dcs[1]->irq);
2708         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2709                 mutex_lock(&tegra_dcs[0]->lock);
2710                 disable_irq(tegra_dcs[0]->irq);
2711         }
2712
2713         msleep(5);
2714         tegra_periph_reset_assert(dc->clk);
2715         msleep(2);
2716 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
2717         tegra_periph_reset_deassert(dc->clk);
2718         msleep(1);
2719 #endif
2720
2721         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2722                 enable_dc_irq(tegra_dcs[1]->irq);
2723                 mutex_unlock(&tegra_dcs[1]->lock);
2724         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2725                 enable_dc_irq(tegra_dcs[0]->irq);
2726                 mutex_unlock(&tegra_dcs[0]->lock);
2727         }
2728
2729         enable_dc_irq(dc->irq);
2730
2731         if (tegra_dc_init(dc)) {
2732                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2733                 ret = false;
2734         }
2735
2736         if (dc->out_ops && dc->out_ops->enable)
2737                 dc->out_ops->enable(dc);
2738
2739         if (dc->out->postpoweron)
2740                 dc->out->postpoweron();
2741
2742         /* force a full blending update */
2743         dc->blend.z[0] = -1;
2744
2745         tegra_dc_ext_enable(dc->ext);
2746
2747         if (!ret) {
2748                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2749                 _tegra_dc_controller_disable(dc);
2750         }
2751
2752         trace_printk("%s:reset enable\n", dc->ndev->name);
2753         return ret;
2754 }
2755 #endif
2756
2757 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2758 {
2759         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2760 }
2761
2762 static bool _tegra_dc_enable(struct tegra_dc *dc)
2763 {
2764         if (dc->mode.pclk == 0) {
2765                 switch (dc->out->type) {
2766                 case TEGRA_DC_OUT_HDMI:
2767                 /* DC enable called but no videomode is loaded.
2768                      Check if HDMI is connected, then set fallback mdoe */
2769                 if (tegra_dc_hpd(dc)) {
2770                         if (_tegra_dc_set_default_videomode(dc))
2771                                 return false;
2772                 } else
2773                         return false;
2774
2775                 break;
2776
2777                 /* Do nothing for other outputs for now */
2778                 case TEGRA_DC_OUT_RGB:
2779
2780                 case TEGRA_DC_OUT_DSI:
2781
2782                 default:
2783                         return false;
2784                 }
2785         }
2786
2787         if (!dc->out)
2788                 return false;
2789
2790         tegra_dc_io_start(dc);
2791
2792         return _tegra_dc_controller_enable(dc);
2793 }
2794
2795 void tegra_dc_enable(struct tegra_dc *dc)
2796 {
2797         mutex_lock(&dc->lock);
2798
2799         if (!dc->enabled)
2800                 dc->enabled = _tegra_dc_enable(dc);
2801
2802         mutex_unlock(&dc->lock);
2803         print_mode_info(dc, dc->mode);
2804 }
2805
2806 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2807 {
2808         unsigned i;
2809
2810         if (dc->out && dc->out->prepoweroff)
2811                 dc->out->prepoweroff();
2812
2813         if (dc->out_ops && dc->out_ops->disable)
2814                 dc->out_ops->disable(dc);
2815
2816         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2817         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2818         disable_irq(dc->irq);
2819
2820         tegra_dc_clear_bandwidth(dc);
2821         tegra_dc_clk_disable(dc);
2822
2823         if (dc->out && dc->out->disable)
2824                 dc->out->disable();
2825
2826         for (i = 0; i < dc->n_windows; i++) {
2827                 struct tegra_dc_win *w = &dc->windows[i];
2828
2829                 /* reset window bandwidth */
2830                 w->bandwidth = 0;
2831                 w->new_bandwidth = 0;
2832
2833                 /* disable windows */
2834                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2835
2836                 /* flush any pending syncpt waits */
2837                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2838                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2839                                 dc->syncpt[i].id);
2840                         dc->syncpt[i].min++;
2841                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2842                 }
2843         }
2844         trace_printk("%s:disabled\n", dc->ndev->name);
2845 }
2846
2847 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2848 {
2849 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2850         u32 val;
2851         if (dc->enabled)  {
2852                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2853                 if (enable)
2854                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2855                 else
2856                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2857                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2858         }
2859 #endif
2860 }
2861
2862 bool tegra_dc_stats_get(struct tegra_dc *dc)
2863 {
2864 #if 0 /* right now it is always enabled */
2865         u32 val;
2866         bool res;
2867
2868         if (dc->enabled)  {
2869                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2870                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2871         } else {
2872                 res = false;
2873         }
2874
2875         return res;
2876 #endif
2877         return true;
2878 }
2879
2880 /* make the screen blank by disabling all windows */
2881 void tegra_dc_blank(struct tegra_dc *dc)
2882 {
2883         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2884         unsigned i;
2885
2886         for (i = 0; i < DC_N_WINDOWS; i++) {
2887                 dcwins[i] = tegra_dc_get_window(dc, i);
2888                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2889         }
2890
2891         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2892         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2893 }
2894
2895 static void _tegra_dc_disable(struct tegra_dc *dc)
2896 {
2897         _tegra_dc_controller_disable(dc);
2898         tegra_dc_io_end(dc);
2899 }
2900
2901 void tegra_dc_disable(struct tegra_dc *dc)
2902 {
2903         tegra_dc_ext_disable(dc->ext);
2904
2905         /* it's important that new underflow work isn't scheduled before the
2906          * lock is acquired. */
2907         cancel_delayed_work_sync(&dc->underflow_work);
2908         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2909                 mutex_lock(&dc->one_shot_lock);
2910                 cancel_delayed_work_sync(&dc->one_shot_work);
2911         }
2912
2913         mutex_lock(&dc->lock);
2914
2915         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2916                 tegra_dc_host_resume(dc);
2917
2918         if (dc->enabled) {
2919                 dc->enabled = false;
2920
2921                 if (!dc->suspended)
2922                         _tegra_dc_disable(dc);
2923         }
2924
2925 #ifdef CONFIG_SWITCH
2926         switch_set_state(&dc->modeset_switch, 0);
2927 #endif
2928
2929         mutex_unlock(&dc->lock);
2930         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2931                 mutex_unlock(&dc->one_shot_lock);
2932         print_mode_info(dc, dc->mode);
2933 }
2934
2935 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2936 static void tegra_dc_reset_worker(struct work_struct *work)
2937 {
2938         struct tegra_dc *dc =
2939                 container_of(work, struct tegra_dc, reset_work);
2940
2941         unsigned long val = 0;
2942
2943         mutex_lock(&shared_lock);
2944
2945         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2946
2947         tegra_dc_ext_disable(dc->ext);
2948
2949         mutex_lock(&dc->lock);
2950
2951         if (dc->enabled == false)
2952                 goto unlock;
2953
2954         dc->enabled = false;
2955
2956         /*
2957          * off host read bus
2958          */
2959         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2960         val &= ~(0x00000100);
2961         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2962
2963         /*
2964          * set DC to STOP mode
2965          */
2966         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2967
2968         msleep(10);
2969
2970         _tegra_dc_controller_disable(dc);
2971
2972         /* _tegra_dc_controller_reset_enable deasserts reset */
2973         _tegra_dc_controller_reset_enable(dc);
2974
2975         dc->enabled = true;
2976
2977         /* reopen host read bus */
2978         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2979         val &= ~(0x00000100);
2980         val |= 0x100;
2981         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2982
2983 unlock:
2984         mutex_unlock(&dc->lock);
2985         mutex_unlock(&shared_lock);
2986         trace_printk("%s:reset complete\n", dc->ndev->name);
2987 }
2988 #endif
2989
2990 static void tegra_dc_underflow_worker(struct work_struct *work)
2991 {
2992         struct tegra_dc *dc = container_of(
2993                 to_delayed_work(work), struct tegra_dc, underflow_work);
2994
2995         mutex_lock(&dc->lock);
2996         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2997                 tegra_dc_host_resume(dc);
2998
2999         if (dc->enabled) {
3000                 tegra_dc_underflow_handler(dc);
3001         }
3002         mutex_unlock(&dc->lock);
3003 }
3004
3005 #ifdef CONFIG_SWITCH
3006 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
3007 {
3008         struct tegra_dc *dc =
3009                 container_of(sdev, struct tegra_dc, modeset_switch);
3010
3011         if (!sdev->state)
3012                 return sprintf(buf, "offline\n");
3013
3014         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
3015 }
3016 #endif
3017
3018 static int tegra_dc_probe(struct nvhost_device *ndev,
3019         struct nvhost_device_id *id_table)
3020 {
3021         struct tegra_dc *dc;
3022         struct clk *clk;
3023         struct clk *emc_clk;
3024         struct resource *res;
3025         struct resource *base_res;
3026         struct resource *fb_mem = NULL;
3027         int ret = 0;
3028         void __iomem *base;
3029         int irq;
3030         int i;
3031
3032         if (!ndev->dev.platform_data) {
3033                 dev_err(&ndev->dev, "no platform data\n");
3034                 return -ENOENT;
3035         }
3036
3037         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3038         if (!dc) {
3039                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3040                 return -ENOMEM;
3041         }
3042
3043         irq = nvhost_get_irq_byname(ndev, "irq");
3044         if (irq <= 0) {
3045                 dev_err(&ndev->dev, "no irq\n");
3046                 ret = -ENOENT;
3047                 goto err_free;
3048         }
3049
3050         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
3051         if (!res) {
3052                 dev_err(&ndev->dev, "no mem resource\n");
3053                 ret = -ENOENT;
3054                 goto err_free;
3055         }
3056
3057         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
3058         if (!base_res) {
3059                 dev_err(&ndev->dev, "request_mem_region failed\n");
3060                 ret = -EBUSY;
3061                 goto err_free;
3062         }
3063
3064         base = ioremap(res->start, resource_size(res));
3065         if (!base) {
3066                 dev_err(&ndev->dev, "registers can't be mapped\n");
3067                 ret = -EBUSY;
3068                 goto err_release_resource_reg;
3069         }
3070
3071         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
3072
3073         clk = clk_get(&ndev->dev, NULL);
3074         if (IS_ERR_OR_NULL(clk)) {
3075                 dev_err(&ndev->dev, "can't get clock\n");
3076                 ret = -ENOENT;
3077                 goto err_iounmap_reg;
3078         }
3079
3080         emc_clk = clk_get(&ndev->dev, "emc");
3081         if (IS_ERR_OR_NULL(emc_clk)) {
3082                 dev_err(&ndev->dev, "can't get emc clock\n");
3083                 ret = -ENOENT;
3084                 goto err_put_clk;
3085         }
3086
3087         dc->clk = clk;
3088         dc->emc_clk = emc_clk;
3089         dc->shift_clk_div = 1;
3090         /* Initialize one shot work delay, it will be assigned by dsi
3091          * according to refresh rate later. */
3092         dc->one_shot_delay_ms = 40;
3093
3094         dc->base_res = base_res;
3095         dc->base = base;
3096         dc->irq = irq;
3097         dc->ndev = ndev;
3098         dc->pdata = ndev->dev.platform_data;
3099
3100         /*
3101          * The emc is a shared clock, it will be set based on
3102          * the requirements for each user on the bus.
3103          */
3104         dc->emc_clk_rate = 0;
3105
3106         mutex_init(&dc->lock);
3107         mutex_init(&dc->one_shot_lock);
3108         init_completion(&dc->frame_end_complete);
3109         init_waitqueue_head(&dc->wq);
3110 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3111         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3112 #endif
3113         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3114         dc->vblank_ref_count = 0;
3115         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3116         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3117
3118         tegra_dc_init_lut_defaults(&dc->fb_lut);
3119
3120         dc->n_windows = DC_N_WINDOWS;
3121         for (i = 0; i < dc->n_windows; i++) {
3122                 struct tegra_dc_win *win = &dc->windows[i];
3123                 win->idx = i;
3124                 win->dc = dc;
3125                 tegra_dc_init_csc_defaults(&win->csc);
3126                 tegra_dc_init_lut_defaults(&win->lut);
3127         }
3128
3129         ret = tegra_dc_set(dc, ndev->id);
3130         if (ret < 0) {
3131                 dev_err(&ndev->dev, "can't add dc\n");
3132                 goto err_free_irq;
3133         }
3134
3135         nvhost_set_drvdata(ndev, dc);
3136
3137 #ifdef CONFIG_SWITCH
3138         dc->modeset_switch.name = dev_name(&ndev->dev);
3139         dc->modeset_switch.state = 0;
3140         dc->modeset_switch.print_state = switch_modeset_print_mode;
3141         switch_dev_register(&dc->modeset_switch);
3142 #endif
3143
3144         tegra_dc_feature_register(dc);
3145
3146         if (dc->pdata->default_out)
3147                 tegra_dc_set_out(dc, dc->pdata->default_out);
3148         else
3149                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3150
3151         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3152                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3153
3154         dc->ext = tegra_dc_ext_register(ndev, dc);
3155         if (IS_ERR_OR_NULL(dc->ext)) {
3156                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3157                 dc->ext = NULL;
3158         }
3159
3160         mutex_lock(&dc->lock);
3161         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
3162                 dc->enabled = _tegra_dc_enable(dc);
3163         mutex_unlock(&dc->lock);
3164
3165         /* interrupt handler must be registered before tegra_fb_register() */
3166         if (request_irq(irq, tegra_dc_irq, 0,
3167                         dev_name(&ndev->dev), dc)) {
3168                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3169                 ret = -EBUSY;
3170                 goto err_put_emc_clk;
3171         }
3172
3173         tegra_dc_create_debugfs(dc);
3174
3175         dev_info(&ndev->dev, "probed\n");
3176
3177         if (dc->pdata->fb) {
3178                 if (dc->pdata->fb->bits_per_pixel == -1) {
3179                         unsigned long fmt;
3180                         tegra_dc_writel(dc,
3181                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3182                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3183
3184                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3185                         dc->pdata->fb->bits_per_pixel =
3186                                 tegra_dc_fmt_bpp(fmt);
3187                 }
3188
3189                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3190                 if (IS_ERR_OR_NULL(dc->fb))
3191                         dc->fb = NULL;
3192         }
3193
3194         if (dc->out && dc->out->hotplug_init)
3195                 dc->out->hotplug_init();
3196
3197         if (dc->out_ops && dc->out_ops->detect)
3198                 dc->out_ops->detect(dc);
3199         else
3200                 dc->connected = true;
3201
3202         tegra_dc_create_sysfs(&dc->ndev->dev);
3203
3204         return 0;
3205
3206 err_free_irq:
3207         free_irq(irq, dc);
3208 err_put_emc_clk:
3209         clk_put(emc_clk);
3210 err_put_clk:
3211         clk_put(clk);
3212 err_iounmap_reg:
3213         iounmap(base);
3214         if (fb_mem)
3215                 release_resource(fb_mem);
3216 err_release_resource_reg:
3217         release_resource(base_res);
3218 err_free:
3219         kfree(dc);
3220
3221         return ret;
3222 }
3223
3224 static int tegra_dc_remove(struct nvhost_device *ndev)
3225 {
3226         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3227
3228         tegra_dc_remove_sysfs(&dc->ndev->dev);
3229         tegra_dc_remove_debugfs(dc);
3230
3231         if (dc->fb) {
3232                 tegra_fb_unregister(dc->fb);
3233                 if (dc->fb_mem)
3234                         release_resource(dc->fb_mem);
3235         }
3236
3237         tegra_dc_ext_disable(dc->ext);
3238
3239         if (dc->ext)
3240                 tegra_dc_ext_unregister(dc->ext);
3241
3242         if (dc->enabled)
3243                 _tegra_dc_disable(dc);
3244
3245 #ifdef CONFIG_SWITCH
3246         switch_dev_unregister(&dc->modeset_switch);
3247 #endif
3248         free_irq(dc->irq, dc);
3249         clk_put(dc->emc_clk);
3250         clk_put(dc->clk);
3251         iounmap(dc->base);
3252         if (dc->fb_mem)
3253                 release_resource(dc->base_res);
3254         kfree(dc);
3255         tegra_dc_set(NULL, ndev->id);
3256         return 0;
3257 }
3258
3259 #ifdef CONFIG_PM
3260 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3261 {
3262         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3263
3264         trace_printk("%s:suspend\n", dc->ndev->name);
3265         dev_info(&ndev->dev, "suspend\n");
3266
3267         tegra_dc_ext_disable(dc->ext);
3268
3269         mutex_lock(&dc->lock);
3270
3271         if (dc->out_ops && dc->out_ops->suspend)
3272                 dc->out_ops->suspend(dc);
3273
3274         if (dc->enabled) {
3275                 _tegra_dc_disable(dc);
3276
3277                 dc->suspended = true;
3278         }
3279
3280         if (dc->out && dc->out->postsuspend) {
3281                 dc->out->postsuspend();
3282                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3283                         /*
3284                          * avoid resume event due to voltage falling
3285                          */
3286                         msleep(100);
3287         }
3288
3289         mutex_unlock(&dc->lock);
3290
3291         return 0;
3292 }
3293
3294 static int tegra_dc_resume(struct nvhost_device *ndev)
3295 {
3296         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3297
3298         trace_printk("%s:resume\n", dc->ndev->name);
3299         dev_info(&ndev->dev, "resume\n");
3300
3301         mutex_lock(&dc->lock);
3302         dc->suspended = false;
3303
3304         if (dc->enabled)
3305                 _tegra_dc_enable(dc);
3306
3307         if (dc->out && dc->out->hotplug_init)
3308                 dc->out->hotplug_init();
3309
3310         if (dc->out_ops && dc->out_ops->resume)
3311                 dc->out_ops->resume(dc);
3312         mutex_unlock(&dc->lock);
3313
3314         return 0;
3315 }
3316
3317 #endif /* CONFIG_PM */
3318
3319 static void tegra_dc_shutdown(struct nvhost_device *ndev)
3320 {
3321         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3322
3323         if (!dc || !dc->enabled)
3324                 return;
3325
3326         tegra_dc_blank(dc);
3327         tegra_dc_disable(dc);
3328 }
3329
3330 extern int suspend_set(const char *val, struct kernel_param *kp)
3331 {
3332         if (!strcmp(val, "dump"))
3333                 dump_regs(tegra_dcs[0]);
3334 #ifdef CONFIG_PM
3335         else if (!strcmp(val, "suspend"))
3336                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3337         else if (!strcmp(val, "resume"))
3338                 tegra_dc_resume(tegra_dcs[0]->ndev);
3339 #endif
3340
3341         return 0;
3342 }
3343
3344 extern int suspend_get(char *buffer, struct kernel_param *kp)
3345 {
3346         return 0;
3347 }
3348
3349 int suspend;
3350
3351 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3352
3353 struct nvhost_driver tegra_dc_driver = {
3354         .driver = {
3355                 .name = "tegradc",
3356                 .owner = THIS_MODULE,
3357         },
3358         .probe = tegra_dc_probe,
3359         .remove = tegra_dc_remove,
3360 #ifdef CONFIG_PM
3361         .suspend = tegra_dc_suspend,
3362         .resume = tegra_dc_resume,
3363 #endif
3364         .shutdown = tegra_dc_shutdown,
3365 };
3366
3367 static int __init tegra_dc_module_init(void)
3368 {
3369         int ret = tegra_dc_ext_module_init();
3370         if (ret)
3371                 return ret;
3372         return nvhost_driver_register(&tegra_dc_driver);
3373 }
3374
3375 static void __exit tegra_dc_module_exit(void)
3376 {
3377         nvhost_driver_unregister(&tegra_dc_driver);
3378         tegra_dc_ext_module_exit();
3379 }
3380
3381 module_exit(tegra_dc_module_exit);
3382 module_init(tegra_dc_module_init);