video: tegra: dc: Add stub runtime PM support
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <video/tegrafb.h>
41 #include <drm/drm_fixed.h>
42 #ifdef CONFIG_SWITCH
43 #include <linux/switch.h>
44 #endif
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55 #include <mach/iomap.h>
56
57 #include "dc_reg.h"
58 #include "dc_config.h"
59 #include "dc_priv.h"
60 #include "dev.h"
61 #include "nvsd.h"
62
63 #define TEGRA_CRC_LATCHED_DELAY         34
64
65 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
66 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
67
68 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
69         .refresh = 60,
70         .xres = 640,
71         .yres = 480,
72         .pixclock = KHZ2PICOS(25200),
73         .hsync_len = 96,        /* h_sync_width */
74         .vsync_len = 2,         /* v_sync_width */
75         .left_margin = 48,      /* h_back_porch */
76         .upper_margin = 33,     /* v_back_porch */
77         .right_margin = 16,     /* h_front_porch */
78         .lower_margin = 10,     /* v_front_porch */
79         .vmode = 0,
80         .sync = 0,
81 };
82
83 static struct tegra_dc_mode override_disp_mode[3];
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
88
89 DEFINE_MUTEX(tegra_dc_lock);
90 DEFINE_MUTEX(shared_lock);
91
92 static const struct {
93         bool h;
94         bool v;
95 } can_filter[] = {
96         /* Window A has no filtering */
97         { false, false },
98         /* Window B has both H and V filtering */
99         { true,  true  },
100         /* Window C has only H filtering */
101         { false, true  },
102 };
103
104 #ifdef CONFIG_TEGRA_DC_CMU
105 static struct tegra_dc_cmu default_cmu = {
106         /* lut1 maps sRGB to linear space. */
107         {
108                 0,    1,    2,    4,    5,    6,    7,    9,
109                 10,   11,   12,   14,   15,   16,   18,   20,
110                 21,   23,   25,   27,   29,   31,   33,   35,
111                 37,   40,   42,   45,   48,   50,   53,   56,
112                 59,   62,   66,   69,   72,   76,   79,   83,
113                 87,   91,   95,   99,   103,  107,  112,  116,
114                 121,  126,  131,  136,  141,  146,  151,  156,
115                 162,  168,  173,  179,  185,  191,  197,  204,
116                 210,  216,  223,  230,  237,  244,  251,  258,
117                 265,  273,  280,  288,  296,  304,  312,  320,
118                 329,  337,  346,  354,  363,  372,  381,  390,
119                 400,  409,  419,  428,  438,  448,  458,  469,
120                 479,  490,  500,  511,  522,  533,  544,  555,
121                 567,  578,  590,  602,  614,  626,  639,  651,
122                 664,  676,  689,  702,  715,  728,  742,  755,
123                 769,  783,  797,  811,  825,  840,  854,  869,
124                 884,  899,  914,  929,  945,  960,  976,  992,
125                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
126                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
127                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
128                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
129                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
130                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
131                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
132                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
133                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
134                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
135                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
136                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
137                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
138                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
139                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
140         },
141         /* csc */
142         {
143                 0x100, 0x0,   0x0,
144                 0x0,   0x100, 0x0,
145                 0x0,   0x0,   0x100,
146         },
147         /* lut2 maps linear space to sRGB*/
148         {
149                 0,    1,    2,    2,    3,    4,    5,    6,
150                 6,    7,    8,    9,    10,   10,   11,   12,
151                 13,   13,   14,   15,   15,   16,   16,   17,
152                 18,   18,   19,   19,   20,   20,   21,   21,
153                 22,   22,   23,   23,   23,   24,   24,   25,
154                 25,   25,   26,   26,   27,   27,   27,   28,
155                 28,   29,   29,   29,   30,   30,   30,   31,
156                 31,   31,   32,   32,   32,   33,   33,   33,
157                 34,   34,   34,   34,   35,   35,   35,   36,
158                 36,   36,   37,   37,   37,   37,   38,   38,
159                 38,   38,   39,   39,   39,   40,   40,   40,
160                 40,   41,   41,   41,   41,   42,   42,   42,
161                 42,   43,   43,   43,   43,   43,   44,   44,
162                 44,   44,   45,   45,   45,   45,   46,   46,
163                 46,   46,   46,   47,   47,   47,   47,   48,
164                 48,   48,   48,   48,   49,   49,   49,   49,
165                 49,   50,   50,   50,   50,   50,   51,   51,
166                 51,   51,   51,   52,   52,   52,   52,   52,
167                 53,   53,   53,   53,   53,   54,   54,   54,
168                 54,   54,   55,   55,   55,   55,   55,   55,
169                 56,   56,   56,   56,   56,   57,   57,   57,
170                 57,   57,   57,   58,   58,   58,   58,   58,
171                 58,   59,   59,   59,   59,   59,   59,   60,
172                 60,   60,   60,   60,   60,   61,   61,   61,
173                 61,   61,   61,   62,   62,   62,   62,   62,
174                 62,   63,   63,   63,   63,   63,   63,   64,
175                 64,   64,   64,   64,   64,   64,   65,   65,
176                 65,   65,   65,   65,   66,   66,   66,   66,
177                 66,   66,   66,   67,   67,   67,   67,   67,
178                 67,   67,   68,   68,   68,   68,   68,   68,
179                 68,   69,   69,   69,   69,   69,   69,   69,
180                 70,   70,   70,   70,   70,   70,   70,   71,
181                 71,   71,   71,   71,   71,   71,   72,   72,
182                 72,   72,   72,   72,   72,   72,   73,   73,
183                 73,   73,   73,   73,   73,   74,   74,   74,
184                 74,   74,   74,   74,   74,   75,   75,   75,
185                 75,   75,   75,   75,   75,   76,   76,   76,
186                 76,   76,   76,   76,   77,   77,   77,   77,
187                 77,   77,   77,   77,   78,   78,   78,   78,
188                 78,   78,   78,   78,   78,   79,   79,   79,
189                 79,   79,   79,   79,   79,   80,   80,   80,
190                 80,   80,   80,   80,   80,   81,   81,   81,
191                 81,   81,   81,   81,   81,   81,   82,   82,
192                 82,   82,   82,   82,   82,   82,   83,   83,
193                 83,   83,   83,   83,   83,   83,   83,   84,
194                 84,   84,   84,   84,   84,   84,   84,   84,
195                 85,   85,   85,   85,   85,   85,   85,   85,
196                 85,   86,   86,   86,   86,   86,   86,   86,
197                 86,   86,   87,   87,   87,   87,   87,   87,
198                 87,   87,   87,   88,   88,   88,   88,   88,
199                 88,   88,   88,   88,   88,   89,   89,   89,
200                 89,   89,   89,   89,   89,   89,   90,   90,
201                 90,   90,   90,   90,   90,   90,   90,   90,
202                 91,   91,   91,   91,   91,   91,   91,   91,
203                 91,   91,   92,   92,   92,   92,   92,   92,
204                 92,   92,   92,   92,   93,   93,   93,   93,
205                 93,   93,   93,   93,   93,   93,   94,   94,
206                 94,   94,   94,   94,   94,   94,   94,   94,
207                 95,   95,   95,   95,   95,   95,   95,   95,
208                 95,   95,   96,   96,   96,   96,   96,   96,
209                 96,   96,   96,   96,   96,   97,   97,   97,
210                 97,   97,   97,   97,   97,   97,   97,   98,
211                 98,   98,   98,   98,   98,   98,   98,   98,
212                 98,   98,   99,   99,   99,   99,   99,   99,
213                 99,   100,  101,  101,  102,  103,  103,  104,
214                 105,  105,  106,  107,  107,  108,  109,  109,
215                 110,  111,  111,  112,  113,  113,  114,  115,
216                 115,  116,  116,  117,  118,  118,  119,  119,
217                 120,  120,  121,  122,  122,  123,  123,  124,
218                 124,  125,  126,  126,  127,  127,  128,  128,
219                 129,  129,  130,  130,  131,  131,  132,  132,
220                 133,  133,  134,  134,  135,  135,  136,  136,
221                 137,  137,  138,  138,  139,  139,  140,  140,
222                 141,  141,  142,  142,  143,  143,  144,  144,
223                 145,  145,  145,  146,  146,  147,  147,  148,
224                 148,  149,  149,  150,  150,  150,  151,  151,
225                 152,  152,  153,  153,  153,  154,  154,  155,
226                 155,  156,  156,  156,  157,  157,  158,  158,
227                 158,  159,  159,  160,  160,  160,  161,  161,
228                 162,  162,  162,  163,  163,  164,  164,  164,
229                 165,  165,  166,  166,  166,  167,  167,  167,
230                 168,  168,  169,  169,  169,  170,  170,  170,
231                 171,  171,  172,  172,  172,  173,  173,  173,
232                 174,  174,  174,  175,  175,  176,  176,  176,
233                 177,  177,  177,  178,  178,  178,  179,  179,
234                 179,  180,  180,  180,  181,  181,  182,  182,
235                 182,  183,  183,  183,  184,  184,  184,  185,
236                 185,  185,  186,  186,  186,  187,  187,  187,
237                 188,  188,  188,  189,  189,  189,  189,  190,
238                 190,  190,  191,  191,  191,  192,  192,  192,
239                 193,  193,  193,  194,  194,  194,  195,  195,
240                 195,  196,  196,  196,  196,  197,  197,  197,
241                 198,  198,  198,  199,  199,  199,  200,  200,
242                 200,  200,  201,  201,  201,  202,  202,  202,
243                 202,  203,  203,  203,  204,  204,  204,  205,
244                 205,  205,  205,  206,  206,  206,  207,  207,
245                 207,  207,  208,  208,  208,  209,  209,  209,
246                 209,  210,  210,  210,  211,  211,  211,  211,
247                 212,  212,  212,  213,  213,  213,  213,  214,
248                 214,  214,  214,  215,  215,  215,  216,  216,
249                 216,  216,  217,  217,  217,  217,  218,  218,
250                 218,  219,  219,  219,  219,  220,  220,  220,
251                 220,  221,  221,  221,  221,  222,  222,  222,
252                 223,  223,  223,  223,  224,  224,  224,  224,
253                 225,  225,  225,  225,  226,  226,  226,  226,
254                 227,  227,  227,  227,  228,  228,  228,  228,
255                 229,  229,  229,  229,  230,  230,  230,  230,
256                 231,  231,  231,  231,  232,  232,  232,  232,
257                 233,  233,  233,  233,  234,  234,  234,  234,
258                 235,  235,  235,  235,  236,  236,  236,  236,
259                 237,  237,  237,  237,  238,  238,  238,  238,
260                 239,  239,  239,  239,  240,  240,  240,  240,
261                 240,  241,  241,  241,  241,  242,  242,  242,
262                 242,  243,  243,  243,  243,  244,  244,  244,
263                 244,  244,  245,  245,  245,  245,  246,  246,
264                 246,  246,  247,  247,  247,  247,  247,  248,
265                 248,  248,  248,  249,  249,  249,  249,  249,
266                 250,  250,  250,  250,  251,  251,  251,  251,
267                 251,  252,  252,  252,  252,  253,  253,  253,
268                 253,  253,  254,  254,  254,  254,  255,  255,
269         },
270 };
271 #endif
272
273 void tegra_dc_clk_enable(struct tegra_dc *dc)
274 {
275         if (!tegra_is_clk_enabled(dc->clk)) {
276                 clk_prepare_enable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
278         }
279 }
280
281 void tegra_dc_clk_disable(struct tegra_dc *dc)
282 {
283         if (tegra_is_clk_enabled(dc->clk)) {
284                 clk_disable_unprepare(dc->clk);
285                 tegra_dvfs_set_rate(dc->clk, 0);
286         }
287 }
288
289 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
290 {
291         if (dc->out_ops->hold)
292                 dc->out_ops->hold(dc);
293 }
294
295 void tegra_dc_release_dc_out(struct tegra_dc *dc)
296 {
297         if (dc->out_ops->release)
298                 dc->out_ops->release(dc);
299 }
300
301 #define DUMP_REG(a) do {                        \
302         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
303                  #a, a, tegra_dc_readl(dc, a));               \
304         print(data, buff);                                    \
305         } while (0)
306
307 static void _dump_regs(struct tegra_dc *dc, void *data,
308                        void (* print)(void *data, const char *str))
309 {
310         int i;
311         char buff[256];
312
313         mutex_lock(&dc->lock);
314         tegra_dc_io_start(dc);
315         tegra_dc_hold_dc_out(dc);
316
317         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
318         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
319         DUMP_REG(DC_CMD_SIGNAL_RAISE);
320         DUMP_REG(DC_CMD_INT_STATUS);
321         DUMP_REG(DC_CMD_INT_MASK);
322         DUMP_REG(DC_CMD_INT_ENABLE);
323         DUMP_REG(DC_CMD_INT_TYPE);
324         DUMP_REG(DC_CMD_INT_POLARITY);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
326         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
327         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
328         DUMP_REG(DC_CMD_STATE_ACCESS);
329         DUMP_REG(DC_CMD_STATE_CONTROL);
330         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
331         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
332
333         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
334         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
335         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
336         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
337         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
338         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
339         DUMP_REG(DC_DISP_REF_TO_SYNC);
340         DUMP_REG(DC_DISP_SYNC_WIDTH);
341         DUMP_REG(DC_DISP_BACK_PORCH);
342         DUMP_REG(DC_DISP_DISP_ACTIVE);
343         DUMP_REG(DC_DISP_FRONT_PORCH);
344         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
347         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
348         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
349         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
352         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
353         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
354         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
357         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
358         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
359         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
360         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
361         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
362         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
363         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
364         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
365         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
366         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
367         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
369         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
370         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
371         DUMP_REG(DC_DISP_M0_CONTROL);
372         DUMP_REG(DC_DISP_M1_CONTROL);
373         DUMP_REG(DC_DISP_DI_CONTROL);
374         DUMP_REG(DC_DISP_PP_CONTROL);
375         DUMP_REG(DC_DISP_PP_SELECT_A);
376         DUMP_REG(DC_DISP_PP_SELECT_B);
377         DUMP_REG(DC_DISP_PP_SELECT_C);
378         DUMP_REG(DC_DISP_PP_SELECT_D);
379         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
380         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
381         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
382         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
383         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
384         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
385         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
386         DUMP_REG(DC_DISP_BORDER_COLOR);
387         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
388         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
389         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
390         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
391         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
392         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
393         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
394         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
395         DUMP_REG(DC_DISP_CURSOR_POSITION);
396         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
397         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
400         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
401         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
402         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
406 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
407         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
408 #endif
409         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
410         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
411
412
413         for (i = 0; i < 3; i++) {
414                 print(data, "\n");
415                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
416                 print(data, buff);
417
418                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
419                                 DC_CMD_DISPLAY_WINDOW_HEADER);
420                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
421                 DUMP_REG(DC_WIN_WIN_OPTIONS);
422                 DUMP_REG(DC_WIN_BYTE_SWAP);
423                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
424                 DUMP_REG(DC_WIN_COLOR_DEPTH);
425                 DUMP_REG(DC_WIN_POSITION);
426                 DUMP_REG(DC_WIN_SIZE);
427                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
428                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
429                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
430                 DUMP_REG(DC_WIN_DDA_INCREMENT);
431                 DUMP_REG(DC_WIN_LINE_STRIDE);
432 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
433                 DUMP_REG(DC_WIN_BUF_STRIDE);
434                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
435 #endif
436                 DUMP_REG(DC_WIN_BLEND_NOKEY);
437                 DUMP_REG(DC_WIN_BLEND_1WIN);
438                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
439                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
440                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
441                 DUMP_REG(DC_WINBUF_START_ADDR);
442                 DUMP_REG(DC_WINBUF_START_ADDR_U);
443                 DUMP_REG(DC_WINBUF_START_ADDR_V);
444                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
445                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
446                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
447                 DUMP_REG(DC_WIN_CSC_YOF);
448                 DUMP_REG(DC_WIN_CSC_KYRGB);
449                 DUMP_REG(DC_WIN_CSC_KUR);
450                 DUMP_REG(DC_WIN_CSC_KVR);
451                 DUMP_REG(DC_WIN_CSC_KUG);
452                 DUMP_REG(DC_WIN_CSC_KVG);
453                 DUMP_REG(DC_WIN_CSC_KUB);
454                 DUMP_REG(DC_WIN_CSC_KVB);
455         }
456
457         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
458         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
459         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
461         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
462         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
463         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
464         DUMP_REG(DC_DISP_M1_CONTROL);
465         DUMP_REG(DC_COM_PM1_CONTROL);
466         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
467         DUMP_REG(DC_DISP_SD_CONTROL);
468 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
469         DUMP_REG(DC_COM_CMU_CSC_KRR);
470         DUMP_REG(DC_COM_CMU_CSC_KGR);
471         DUMP_REG(DC_COM_CMU_CSC_KBR);
472         DUMP_REG(DC_COM_CMU_CSC_KRG);
473         DUMP_REG(DC_COM_CMU_CSC_KGG);
474         DUMP_REG(DC_COM_CMU_CSC_KBR);
475         DUMP_REG(DC_COM_CMU_CSC_KRB);
476         DUMP_REG(DC_COM_CMU_CSC_KGB);
477         DUMP_REG(DC_COM_CMU_CSC_KBB);
478 #endif
479
480         tegra_dc_release_dc_out(dc);
481         tegra_dc_io_end(dc);
482         mutex_unlock(&dc->lock);
483 }
484
485 #undef DUMP_REG
486
487 #ifdef DEBUG
488 static void dump_regs_print(void *data, const char *str)
489 {
490         struct tegra_dc *dc = data;
491         dev_dbg(&dc->ndev->dev, "%s", str);
492 }
493
494 static void dump_regs(struct tegra_dc *dc)
495 {
496         _dump_regs(dc, dc, dump_regs_print);
497 }
498 #else /* !DEBUG */
499
500 static void dump_regs(struct tegra_dc *dc) {}
501
502 #endif /* DEBUG */
503
504 #ifdef CONFIG_DEBUG_FS
505
506 static void dbg_regs_print(void *data, const char *str)
507 {
508         struct seq_file *s = data;
509
510         seq_printf(s, "%s", str);
511 }
512
513 #undef DUMP_REG
514
515 static int dbg_dc_show(struct seq_file *s, void *unused)
516 {
517         struct tegra_dc *dc = s->private;
518
519         _dump_regs(dc, s, dbg_regs_print);
520
521         return 0;
522 }
523
524
525 static int dbg_dc_open(struct inode *inode, struct file *file)
526 {
527         return single_open(file, dbg_dc_show, inode->i_private);
528 }
529
530 static const struct file_operations regs_fops = {
531         .open           = dbg_dc_open,
532         .read           = seq_read,
533         .llseek         = seq_lseek,
534         .release        = single_release,
535 };
536
537 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
538 {
539         struct tegra_dc *dc = s->private;
540         struct tegra_dc_mode *m;
541
542         mutex_lock(&dc->lock);
543         m = &dc->mode;
544         seq_printf(s,
545                 "pclk: %d\n"
546                 "h_ref_to_sync: %d\n"
547                 "v_ref_to_sync: %d\n"
548                 "h_sync_width: %d\n"
549                 "v_sync_width: %d\n"
550                 "h_back_porch: %d\n"
551                 "v_back_porch: %d\n"
552                 "h_active: %d\n"
553                 "v_active: %d\n"
554                 "h_front_porch: %d\n"
555                 "v_front_porch: %d\n"
556                 "stereo_mode: %d\n",
557                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
558                 m->h_sync_width, m->v_sync_width,
559                 m->h_back_porch, m->v_back_porch,
560                 m->h_active, m->v_active,
561                 m->h_front_porch, m->v_front_porch,
562                 m->stereo_mode);
563         mutex_unlock(&dc->lock);
564         return 0;
565 }
566
567 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
568 {
569         return single_open(file, dbg_dc_mode_show, inode->i_private);
570 }
571
572 static const struct file_operations mode_fops = {
573         .open           = dbg_dc_mode_open,
574         .read           = seq_read,
575         .llseek         = seq_lseek,
576         .release        = single_release,
577 };
578
579 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
580 {
581         struct tegra_dc *dc = s->private;
582
583         mutex_lock(&dc->lock);
584         seq_printf(s,
585                 "underflows: %llu\n"
586                 "underflows_a: %llu\n"
587                 "underflows_b: %llu\n"
588                 "underflows_c: %llu\n",
589                 dc->stats.underflows,
590                 dc->stats.underflows_a,
591                 dc->stats.underflows_b,
592                 dc->stats.underflows_c);
593         mutex_unlock(&dc->lock);
594
595         return 0;
596 }
597
598 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
599 {
600         return single_open(file, dbg_dc_stats_show, inode->i_private);
601 }
602
603 static const struct file_operations stats_fops = {
604         .open           = dbg_dc_stats_open,
605         .read           = seq_read,
606         .llseek         = seq_lseek,
607         .release        = single_release,
608 };
609
610 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
611 {
612         if (dc->debugdir)
613                 debugfs_remove_recursive(dc->debugdir);
614         dc->debugdir = NULL;
615 }
616
617 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
618 {
619         struct dentry *retval;
620
621         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
622         if (!dc->debugdir)
623                 goto remove_out;
624
625         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
626                 &regs_fops);
627         if (!retval)
628                 goto remove_out;
629
630         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
631                 &mode_fops);
632         if (!retval)
633                 goto remove_out;
634
635         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
636                 &stats_fops);
637         if (!retval)
638                 goto remove_out;
639
640         return;
641 remove_out:
642         dev_err(&dc->ndev->dev, "could not create debugfs\n");
643         tegra_dc_remove_debugfs(dc);
644 }
645
646 #else /* !CONFIG_DEBUGFS */
647 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
648 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
649 #endif /* CONFIG_DEBUGFS */
650
651 static int tegra_dc_set(struct tegra_dc *dc, int index)
652 {
653         int ret = 0;
654
655         mutex_lock(&tegra_dc_lock);
656         if (index >= TEGRA_MAX_DC) {
657                 ret = -EINVAL;
658                 goto out;
659         }
660
661         if (dc != NULL && tegra_dcs[index] != NULL) {
662                 ret = -EBUSY;
663                 goto out;
664         }
665
666         tegra_dcs[index] = dc;
667
668 out:
669         mutex_unlock(&tegra_dc_lock);
670
671         return ret;
672 }
673
674 unsigned int tegra_dc_has_multiple_dc(void)
675 {
676         unsigned int idx;
677         unsigned int cnt = 0;
678         struct tegra_dc *dc;
679
680         mutex_lock(&tegra_dc_lock);
681         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
682                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
683         mutex_unlock(&tegra_dc_lock);
684
685         return (cnt > 1);
686 }
687
688 /* get the stride size of a window.
689  * return: stride size in bytes for window win. or 0 if unavailble. */
690 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
691 {
692         u32 stride;
693
694         if (!dc->enabled)
695                 return 0;
696         BUG_ON(win > DC_N_WINDOWS);
697         mutex_lock(&dc->lock);
698         tegra_dc_io_start(dc);
699         tegra_dc_hold_dc_out(dc);
700         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
701                 DC_CMD_DISPLAY_WINDOW_HEADER);
702         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
703         tegra_dc_release_dc_out(dc);
704         tegra_dc_io_end(dc);
705         mutex_unlock(&dc->lock);
706         return GET_LINE_STRIDE(stride);
707 }
708 EXPORT_SYMBOL(tegra_dc_get_stride);
709
710 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
711 {
712         if (idx < TEGRA_MAX_DC)
713                 return tegra_dcs[idx];
714         else
715                 return NULL;
716 }
717 EXPORT_SYMBOL(tegra_dc_get_dc);
718
719 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
720 {
721         if (win >= dc->n_windows)
722                 return NULL;
723
724         return &dc->windows[win];
725 }
726 EXPORT_SYMBOL(tegra_dc_get_window);
727
728 bool tegra_dc_get_connected(struct tegra_dc *dc)
729 {
730         return dc->connected;
731 }
732 EXPORT_SYMBOL(tegra_dc_get_connected);
733
734 bool tegra_dc_hpd(struct tegra_dc *dc)
735 {
736         int sense;
737         int level;
738
739         level = gpio_get_value(dc->out->hotplug_gpio);
740
741         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
742
743         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
744                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
745 }
746 EXPORT_SYMBOL(tegra_dc_hpd);
747
748 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
749 {
750         unsigned i;
751         unsigned v0 = 128;
752         unsigned v1 = 0;
753
754         /* linear horizontal and vertical filters */
755         for (i = 0; i < 16; i++) {
756                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
757                                 DC_WIN_H_FILTER_P(i));
758
759                 tegra_dc_writel(dc, v0,
760                                 DC_WIN_V_FILTER_P(i));
761                 v0 -= 8;
762                 v1 += 8;
763         }
764 }
765
766 #ifdef CONFIG_TEGRA_DC_CMU
767 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
768                                         struct tegra_dc_cmu *src_cmu)
769 {
770         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
771 }
772
773 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
774 {
775         u32 val;
776         u32 i;
777
778         for (i = 0; i < 256; i++) {
779                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
780                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
781         }
782
783         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
784         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
785         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
786         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
787         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
788         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
789         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
790         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
791         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
792
793         for (i = 0; i < 960; i++) {
794                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
795                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
796         }
797 }
798
799 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
800 {
801         u32 val;
802         u32 i;
803         bool flags;
804
805         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
806         if (val & CMU_ENABLE)
807                 flags = true;
808
809         val &= ~CMU_ENABLE;
810         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
811         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
812         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
813
814         /*TODO: Sync up with frame end */
815         mdelay(20);
816
817         for (i = 0; i < 256; i++) {
818                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
819                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
820                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
821                 cmu->lut1[i] = LUT1_READ_DATA(val);
822         }
823
824         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
825         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
826         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
827         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
828         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
829         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
830         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
831         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
832         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
833
834         for (i = 0; i < 960; i++) {
835                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
836                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
837                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
838                 cmu->lut2[i] = LUT2_READ_DATA(val);
839         }
840 }
841 EXPORT_SYMBOL(tegra_dc_get_cmu);
842
843 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
844 {
845         u32 val;
846
847         if (dc->pdata->cmu_enable) {
848                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
849         } else {
850                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
851                 return 0;
852         }
853
854         if (cmu != &dc->cmu) {
855                 tegra_dc_cache_cmu(&dc->cmu, cmu);
856
857                 /* Disable CMU */
858                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
859                 if (val & CMU_ENABLE) {
860                         val &= ~CMU_ENABLE;
861                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
862                         val = GENERAL_UPDATE;
863                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
864                         val = GENERAL_ACT_REQ;
865                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
866                         /*TODO: Sync up with vsync */
867                         mdelay(20);
868                 }
869
870                 tegra_dc_set_cmu(dc, &dc->cmu);
871         }
872
873         return 0;
874 }
875
876 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
877 {
878         int ret;
879
880         mutex_lock(&dc->lock);
881         if (!dc->enabled) {
882                 mutex_unlock(&dc->lock);
883                 return 0;
884         }
885         tegra_dc_io_start(dc);
886         tegra_dc_hold_dc_out(dc);
887
888         ret = _tegra_dc_update_cmu(dc, cmu);
889         tegra_dc_set_color_control(dc);
890
891         tegra_dc_release_dc_out(dc);
892         tegra_dc_io_end(dc);
893         mutex_unlock(&dc->lock);
894
895         return ret;
896 }
897 EXPORT_SYMBOL(tegra_dc_update_cmu);
898
899 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
900 {
901         dc->pdata->cmu_enable = cmu_enable;
902         if (dc->pdata->cmu)
903                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
904         else
905                 tegra_dc_update_cmu(dc, &default_cmu);
906 }
907 #else
908 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
909 #define tegra_dc_set_cmu(dc, cmu)
910 #define tegra_dc_update_cmu(dc, cmu)
911 #endif
912
913 /* disable_irq() blocks until handler completes, calling this function while
914  * holding dc->lock can deadlock. */
915 static inline void disable_dc_irq(const struct tegra_dc *dc)
916 {
917         disable_irq(dc->irq);
918 }
919
920 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
921 {
922         return dc->syncpt[i].id;
923 }
924 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
925
926 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
927 {
928         u32 max;
929
930         mutex_lock(&dc->lock);
931         tegra_dc_io_start(dc);
932         tegra_dc_hold_dc_out(dc);
933         max = nvhost_syncpt_incr_max_ext(dc->ndev,
934                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
935         dc->syncpt[i].max = max;
936         tegra_dc_release_dc_out(dc);
937         tegra_dc_io_end(dc);
938         mutex_unlock(&dc->lock);
939
940         return max;
941 }
942
943 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
944 {
945         mutex_lock(&dc->lock);
946         if (dc->enabled) {
947                 tegra_dc_io_start(dc);
948                 tegra_dc_hold_dc_out(dc);
949                 while (dc->syncpt[i].min < val) {
950                         dc->syncpt[i].min++;
951                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
952                 }
953                 tegra_dc_release_dc_out(dc);
954                 tegra_dc_io_end(dc);
955         }
956         mutex_unlock(&dc->lock);
957 }
958
959 void
960 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
961 {
962         unsigned int ctrl;
963         unsigned long out_sel;
964         unsigned long cmd_state;
965
966         mutex_lock(&dc->lock);
967         if (!dc->enabled) {
968                 mutex_unlock(&dc->lock);
969                 return;
970         }
971
972         tegra_dc_io_start(dc);
973         tegra_dc_hold_dc_out(dc);
974
975         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
976                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
977                 cfg->clk_select);
978
979         /* The new value should be effected immediately */
980         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
981         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
982
983         switch (cfg->which_pwm) {
984         case TEGRA_PWM_PM0:
985                 /* Select the LM0 on PM0 */
986                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
987                 out_sel &= ~(7 << 0);
988                 out_sel |= (3 << 0);
989                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
990                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
991                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
992                 break;
993         case TEGRA_PWM_PM1:
994                 /* Select the LM1 on PM1 */
995                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
996                 out_sel &= ~(7 << 4);
997                 out_sel |= (3 << 4);
998                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
999                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1000                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1001                 break;
1002         default:
1003                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1004                 break;
1005         }
1006         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1007         tegra_dc_release_dc_out(dc);
1008         tegra_dc_io_end(dc);
1009         mutex_unlock(&dc->lock);
1010 }
1011 EXPORT_SYMBOL(tegra_dc_config_pwm);
1012
1013 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1014                                 const struct tegra_dc_out_pin *pins,
1015                                 const unsigned int n_pins)
1016 {
1017         unsigned int i;
1018
1019         int name;
1020         int pol;
1021
1022         u32 pol1, pol3;
1023
1024         u32 set1, unset1;
1025         u32 set3, unset3;
1026
1027         set1 = set3 = unset1 = unset3 = 0;
1028
1029         for (i = 0; i < n_pins; i++) {
1030                 name = (pins + i)->name;
1031                 pol  = (pins + i)->pol;
1032
1033                 /* set polarity by name */
1034                 switch (name) {
1035                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1036                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1037                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1038                         else
1039                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1040                         break;
1041                 case TEGRA_DC_OUT_PIN_H_SYNC:
1042                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1043                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1044                         else
1045                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1046                         break;
1047                 case TEGRA_DC_OUT_PIN_V_SYNC:
1048                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1049                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1050                         else
1051                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1052                         break;
1053                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1054                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1055                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1056                         else
1057                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1058                         break;
1059                 default:
1060                         printk("Invalid argument in function %s\n",
1061                                __FUNCTION__);
1062                         break;
1063                 }
1064         }
1065
1066         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1067         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1068
1069         pol1 |= set1;
1070         pol1 &= ~unset1;
1071
1072         pol3 |= set3;
1073         pol3 &= ~unset3;
1074
1075         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1076         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1077 }
1078
1079 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1080 {
1081         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1082                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1083                 dc->out->type == TEGRA_DC_OUT_DSI)
1084                 return override_disp_mode[dc->out->type].pclk ?
1085                         &override_disp_mode[dc->out->type] : NULL;
1086         else
1087                 return NULL;
1088 }
1089
1090 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1091 {
1092         struct tegra_dc_mode *mode;
1093
1094         dc->out = out;
1095         mode = tegra_dc_get_override_mode(dc);
1096
1097         if (mode)
1098                 tegra_dc_set_mode(dc, mode);
1099         else if (out->n_modes > 0)
1100                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1101
1102         switch (out->type) {
1103         case TEGRA_DC_OUT_RGB:
1104                 dc->out_ops = &tegra_dc_rgb_ops;
1105                 break;
1106
1107         case TEGRA_DC_OUT_HDMI:
1108                 dc->out_ops = &tegra_dc_hdmi_ops;
1109                 break;
1110
1111         case TEGRA_DC_OUT_DSI:
1112                 dc->out_ops = &tegra_dc_dsi_ops;
1113                 break;
1114
1115         default:
1116                 dc->out_ops = NULL;
1117                 break;
1118         }
1119
1120         if (dc->out_ops && dc->out_ops->init)
1121                 dc->out_ops->init(dc);
1122 }
1123
1124 /* returns on error: -EINVAL
1125  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1126 int tegra_dc_get_out(const struct tegra_dc *dc)
1127 {
1128         if (dc && dc->out)
1129                 return dc->out->type;
1130         return -EINVAL;
1131 }
1132
1133 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1134 {
1135         if (dc->out)
1136                 return dc->out->height;
1137         else
1138                 return 0;
1139 }
1140 EXPORT_SYMBOL(tegra_dc_get_out_height);
1141
1142 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1143 {
1144         if (dc->out)
1145                 return dc->out->width;
1146         else
1147                 return 0;
1148 }
1149 EXPORT_SYMBOL(tegra_dc_get_out_width);
1150
1151 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1152 {
1153         if (dc->out && dc->out->max_pixclock)
1154                 return dc->out->max_pixclock;
1155         else
1156                 return 0;
1157 }
1158 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1159
1160 void tegra_dc_enable_crc(struct tegra_dc *dc)
1161 {
1162         u32 val;
1163
1164         mutex_lock(&dc->lock);
1165         tegra_dc_io_start(dc);
1166         tegra_dc_hold_dc_out(dc);
1167
1168         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1169                 CRC_ENABLE_ENABLE;
1170         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1171         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1172         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1173         tegra_dc_release_dc_out(dc);
1174         tegra_dc_io_end(dc);
1175         mutex_unlock(&dc->lock);
1176 }
1177
1178 void tegra_dc_disable_crc(struct tegra_dc *dc)
1179 {
1180         mutex_lock(&dc->lock);
1181         tegra_dc_io_start(dc);
1182         tegra_dc_hold_dc_out(dc);
1183         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1184         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1185         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1186
1187         tegra_dc_release_dc_out(dc);
1188         tegra_dc_io_end(dc);
1189         mutex_unlock(&dc->lock);
1190 }
1191
1192 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1193 {
1194         int crc = 0;
1195
1196         if (!dc) {
1197                 pr_err("Failed to get dc: NULL parameter.\n");
1198                 goto crc_error;
1199         }
1200
1201 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1202         /* TODO: Replace mdelay with code to sync VBlANK, since
1203          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1204         mdelay(TEGRA_CRC_LATCHED_DELAY);
1205 #endif
1206
1207         mutex_lock(&dc->lock);
1208         tegra_dc_io_start(dc);
1209         tegra_dc_hold_dc_out(dc);
1210         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1211         tegra_dc_release_dc_out(dc);
1212         tegra_dc_io_end(dc);
1213         mutex_unlock(&dc->lock);
1214 crc_error:
1215         return crc;
1216 }
1217
1218 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1219 {
1220 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1221         u32 val;
1222
1223         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1224         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1225             return true;
1226 #endif
1227         return false;
1228 }
1229
1230 static inline void enable_dc_irq(const struct tegra_dc *dc)
1231 {
1232 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1233         enable_irq(dc->irq);
1234 #else
1235         /* Always disable DC interrupts on FPGA. */
1236         disable_irq(dc->irq);
1237 #endif
1238 }
1239
1240 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1241 {
1242         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1243                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1244 }
1245
1246 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1247 {
1248         int ret = -ENOTTY;
1249
1250         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1251                 return ret;
1252
1253         /*
1254          * Logic is as follows
1255          * a) Indicate we need a vblank.
1256          * b) Wait for completion to be signalled from isr.
1257          * c) Initialize completion for next iteration.
1258          */
1259
1260         tegra_dc_hold_dc_out(dc);
1261         dc->out->user_needs_vblank = true;
1262
1263         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1264         init_completion(&dc->out->user_vblank_comp);
1265         tegra_dc_release_dc_out(dc);
1266
1267         return ret;
1268 }
1269
1270 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1271 {
1272         /* Do the actual brightness update outside of the mutex dc->lock */
1273         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1274                 dc->out->sd_settings->bl_device_name) {
1275                 char *bl_device_name =
1276                         dc->out->sd_settings->bl_device_name;
1277                 dc->out->sd_settings->bl_device =
1278                         get_backlight_device_by_name(bl_device_name);
1279         }
1280
1281         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1282                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1283                 backlight_update_status(bl);
1284         }
1285 }
1286
1287 static void tegra_dc_vblank(struct work_struct *work)
1288 {
1289         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1290         bool nvsd_updated = false;
1291
1292         mutex_lock(&dc->lock);
1293
1294         if (!dc->enabled) {
1295                 mutex_unlock(&dc->lock);
1296                 return;
1297         }
1298
1299         tegra_dc_io_start(dc);
1300         tegra_dc_hold_dc_out(dc);
1301         /* use the new frame's bandwidth setting instead of max(current, new),
1302          * skip this if we're using tegra_dc_one_shot_worker() */
1303         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1304                 tegra_dc_program_bandwidth(dc, true);
1305
1306         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1307         if (!tegra_dc_windows_are_dirty(dc))
1308                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1309
1310         /* Update the SD brightness */
1311         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1312                 nvsd_updated = nvsd_update_brightness(dc);
1313                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1314                  * V_BLANK_NVSD bit of vblank ref-count. */
1315                 if (nvsd_updated) {
1316                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1317                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1318                 } else {
1319                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1320                 }
1321         }
1322
1323         /* Mask vblank interrupt if ref-count is zero. */
1324         if (!dc->vblank_ref_count)
1325                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1326
1327         tegra_dc_release_dc_out(dc);
1328         tegra_dc_io_end(dc);
1329         mutex_unlock(&dc->lock);
1330
1331         /* Do the actual brightness update outside of the mutex dc->lock */
1332         if (nvsd_updated)
1333                 tegra_dc_prism_update_backlight(dc);
1334 }
1335
1336 static void tegra_dc_one_shot_worker(struct work_struct *work)
1337 {
1338         struct tegra_dc *dc = container_of(
1339                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1340         mutex_lock(&dc->lock);
1341
1342         /* memory client has gone idle */
1343         tegra_dc_clear_bandwidth(dc);
1344
1345         if (dc->out_ops->idle) {
1346                 tegra_dc_io_start(dc);
1347                 dc->out_ops->idle(dc);
1348                 tegra_dc_io_end(dc);
1349         }
1350
1351         mutex_unlock(&dc->lock);
1352 }
1353
1354 /* return an arbitrarily large number if count overflow occurs.
1355  * make it a nice base-10 number to show up in stats output */
1356 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1357 {
1358         unsigned count = tegra_dc_readl(dc, reg);
1359
1360         tegra_dc_writel(dc, 0, reg);
1361         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1362 }
1363
1364 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1365 {
1366         int i;
1367
1368         dc->stats.underflows++;
1369         if (dc->underflow_mask & WIN_A_UF_INT)
1370                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1371                         DC_WINBUF_AD_UFLOW_STATUS);
1372         if (dc->underflow_mask & WIN_B_UF_INT)
1373                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1374                         DC_WINBUF_BD_UFLOW_STATUS);
1375         if (dc->underflow_mask & WIN_C_UF_INT)
1376                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1377                         DC_WINBUF_CD_UFLOW_STATUS);
1378
1379         /* Check for any underflow reset conditions */
1380         for (i = 0; i < DC_N_WINDOWS; i++) {
1381                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1382                         dc->windows[i].underflows++;
1383
1384 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1385                         if (dc->windows[i].underflows > 4) {
1386                                 schedule_work(&dc->reset_work);
1387                                 /* reset counter */
1388                                 dc->windows[i].underflows = 0;
1389                                 trace_display_reset(dc);
1390                         }
1391 #endif
1392 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1393                         if (dc->windows[i].underflows > 4) {
1394                                 trace_display_reset(dc);
1395                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1396                                                 DC_DISP_DISP_MISC_CONTROL);
1397                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1398                                                 DC_CMD_STATE_CONTROL);
1399                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1400                                                 DC_CMD_STATE_CONTROL);
1401
1402                                 tegra_dc_writel(dc, 0,
1403                                                 DC_DISP_DISP_MISC_CONTROL);
1404                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1405                                                 DC_CMD_STATE_CONTROL);
1406                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1407                                                 DC_CMD_STATE_CONTROL);
1408                         }
1409 #endif
1410                 } else {
1411                         dc->windows[i].underflows = 0;
1412                 }
1413         }
1414
1415         /* Clear the underflow mask now that we've checked it. */
1416         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1417         dc->underflow_mask = 0;
1418         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1419         trace_underflow(dc);
1420 }
1421
1422 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1423 static void tegra_dc_vpulse2(struct work_struct *work)
1424 {
1425         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1426         bool nvsd_updated = false;
1427
1428         mutex_lock(&dc->lock);
1429
1430         if (!dc->enabled) {
1431                 mutex_unlock(&dc->lock);
1432                 return;
1433         }
1434
1435         tegra_dc_io_start(dc);
1436         tegra_dc_hold_dc_out(dc);
1437
1438         /* Clear the V_PULSE2_FLIP if no update */
1439         if (!tegra_dc_windows_are_dirty(dc))
1440                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1441
1442         /* Update the SD brightness */
1443         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1444                 nvsd_updated = nvsd_update_brightness(dc);
1445                 if (nvsd_updated) {
1446                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1447                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1448                 } else {
1449                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1450                 }
1451         }
1452
1453         /* Mask vpulse2 interrupt if ref-count is zero. */
1454         if (!dc->vpulse2_ref_count)
1455                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1456
1457         tegra_dc_release_dc_out(dc);
1458         tegra_dc_io_end(dc);
1459         mutex_unlock(&dc->lock);
1460
1461         /* Do the actual brightness update outside of the mutex dc->lock */
1462         if (nvsd_updated)
1463                 tegra_dc_prism_update_backlight(dc);
1464 }
1465 #endif
1466
1467 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1468 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1469 {
1470         /* pending user vblank, so wakeup */
1471         if ((status & (V_BLANK_INT | MSF_INT)) &&
1472             (dc->out->user_needs_vblank)) {
1473                 dc->out->user_needs_vblank = false;
1474                 complete(&dc->out->user_vblank_comp);
1475         }
1476
1477         if (status & V_BLANK_INT) {
1478                 /* Sync up windows. */
1479                 tegra_dc_trigger_windows(dc);
1480
1481                 /* Schedule any additional bottom-half vblank actvities. */
1482                 queue_work(system_freezable_wq, &dc->vblank_work);
1483         }
1484
1485         if (status & FRAME_END_INT) {
1486                 /* Mark the frame_end as complete. */
1487                 if (!completion_done(&dc->frame_end_complete))
1488                         complete(&dc->frame_end_complete);
1489         }
1490
1491 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1492         if (status & V_PULSE2_INT)
1493                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1494 #endif
1495 }
1496
1497 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1498 {
1499         /* Schedule any additional bottom-half vblank actvities. */
1500         if (status & V_BLANK_INT)
1501                 queue_work(system_freezable_wq, &dc->vblank_work);
1502
1503         if (status & FRAME_END_INT) {
1504                 struct timespec tm = CURRENT_TIME;
1505                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1506                 wake_up(&dc->timestamp_wq);
1507
1508                 /* Mark the frame_end as complete. */
1509                 if (!completion_done(&dc->frame_end_complete))
1510                         complete(&dc->frame_end_complete);
1511
1512                 tegra_dc_trigger_windows(dc);
1513         }
1514
1515 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1516         if (status & V_PULSE2_INT)
1517                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1518 #endif
1519 }
1520
1521 /* XXX: Not sure if we limit look ahead to 1 frame */
1522 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1523 {
1524         BUG_ON(!dc->frametime_ns);
1525         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1526 }
1527
1528 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1529 {
1530         BUG_ON(!dc->frametime_ns);
1531         return (((new_ts - old_ts) > dc->frametime_ns)
1532                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1533                         != div_s64((old_ts - dc->frame_end_timestamp),
1534                                 dc->frametime_ns)));
1535 }
1536 #endif
1537
1538 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1539 {
1540 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1541         struct tegra_dc *dc = ptr;
1542         unsigned long status;
1543         unsigned long underflow_mask;
1544         u32 val;
1545         int need_disable = 0;
1546
1547         mutex_lock(&dc->lock);
1548         if (!dc->enabled) {
1549                 mutex_unlock(&dc->lock);
1550                 return IRQ_HANDLED;
1551         }
1552
1553         clk_prepare_enable(dc->clk);
1554         tegra_dc_io_start(dc);
1555         tegra_dc_hold_dc_out(dc);
1556
1557         if (!nvhost_module_powered_ext(dc->ndev)) {
1558                 WARN(1, "IRQ when DC not powered!\n");
1559                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1560                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1561                 tegra_dc_release_dc_out(dc);
1562                 tegra_dc_io_end(dc);
1563                 clk_disable_unprepare(dc->clk);
1564                 mutex_unlock(&dc->lock);
1565                 return IRQ_HANDLED;
1566         }
1567
1568         /* clear all status flags except underflow, save those for the worker */
1569         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1570         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1571         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1572         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1573
1574         /*
1575          * Overlays can get thier internal state corrupted during and underflow
1576          * condition.  The only way to fix this state is to reset the DC.
1577          * if we get 4 consecutive frames with underflows, assume we're
1578          * hosed and reset.
1579          */
1580         underflow_mask = status & ALL_UF_INT;
1581
1582         /* Check underflow */
1583         if (underflow_mask) {
1584                 dc->underflow_mask |= underflow_mask;
1585                 schedule_delayed_work(&dc->underflow_work,
1586                         msecs_to_jiffies(1));
1587         }
1588
1589         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1590                 tegra_dc_one_shot_irq(dc, status);
1591         else
1592                 tegra_dc_continuous_irq(dc, status);
1593
1594         /* update video mode if it has changed since the last frame */
1595         if (status & (FRAME_END_INT | V_BLANK_INT))
1596                 if (tegra_dc_update_mode(dc))
1597                         need_disable = 1; /* force display off on error */
1598
1599         tegra_dc_release_dc_out(dc);
1600         tegra_dc_io_end(dc);
1601         clk_disable_unprepare(dc->clk);
1602         mutex_unlock(&dc->lock);
1603
1604         if (need_disable)
1605                 tegra_dc_disable(dc);
1606         return IRQ_HANDLED;
1607 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1608         return IRQ_NONE;
1609 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1610 }
1611
1612 void tegra_dc_set_color_control(struct tegra_dc *dc)
1613 {
1614         u32 color_control;
1615
1616         switch (dc->out->depth) {
1617         case 3:
1618                 color_control = BASE_COLOR_SIZE111;
1619                 break;
1620
1621         case 6:
1622                 color_control = BASE_COLOR_SIZE222;
1623                 break;
1624
1625         case 8:
1626                 color_control = BASE_COLOR_SIZE332;
1627                 break;
1628
1629         case 9:
1630                 color_control = BASE_COLOR_SIZE333;
1631                 break;
1632
1633         case 12:
1634                 color_control = BASE_COLOR_SIZE444;
1635                 break;
1636
1637         case 15:
1638                 color_control = BASE_COLOR_SIZE555;
1639                 break;
1640
1641         case 16:
1642                 color_control = BASE_COLOR_SIZE565;
1643                 break;
1644
1645         case 18:
1646                 color_control = BASE_COLOR_SIZE666;
1647                 break;
1648
1649         default:
1650                 color_control = BASE_COLOR_SIZE888;
1651                 break;
1652         }
1653
1654         switch (dc->out->dither) {
1655         case TEGRA_DC_DISABLE_DITHER:
1656                 color_control |= DITHER_CONTROL_DISABLE;
1657                 break;
1658         case TEGRA_DC_ORDERED_DITHER:
1659                 color_control |= DITHER_CONTROL_ORDERED;
1660                 break;
1661         case TEGRA_DC_ERRDIFF_DITHER:
1662                 /* The line buffer for error-diffusion dither is limited
1663                  * to 1280 pixels per line. This limits the maximum
1664                  * horizontal active area size to 1280 pixels when error
1665                  * diffusion is enabled.
1666                  */
1667                 BUG_ON(dc->mode.h_active > 1280);
1668                 color_control |= DITHER_CONTROL_ERRDIFF;
1669                 break;
1670         }
1671
1672 #ifdef CONFIG_TEGRA_DC_CMU
1673         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1674                 color_control |= CMU_ENABLE;
1675 #endif
1676
1677         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1678 }
1679
1680 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1681 {
1682         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1683                 return dc->win_syncpt[idx];
1684         BUG();
1685 }
1686
1687 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1688 {
1689 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1690         u32 start, end;
1691         unsigned long val;
1692
1693         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1694         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1695
1696         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1697                 dc->mode.v_back_porch + dc->mode.v_active;
1698         end = start + 1;
1699         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1700         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1701
1702         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1703         val |= V_PULSE2_INT;
1704         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1705
1706         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1707         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1708 #endif
1709 }
1710
1711 static int tegra_dc_init(struct tegra_dc *dc)
1712 {
1713         int i;
1714         int int_enable;
1715
1716         tegra_dc_io_start(dc);
1717         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1718         if (dc->ndev->id == 0) {
1719                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1720                                       TEGRA_MC_PRIO_MED);
1721                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1722                                       TEGRA_MC_PRIO_MED);
1723                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1724                                       TEGRA_MC_PRIO_MED);
1725 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1726                 /* only present on Tegra2 and 3 */
1727                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1728                                       TEGRA_MC_PRIO_MED);
1729 #endif
1730                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1731                                       TEGRA_MC_PRIO_HIGH);
1732         } else if (dc->ndev->id == 1) {
1733                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1734                                       TEGRA_MC_PRIO_MED);
1735                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1736                                       TEGRA_MC_PRIO_MED);
1737                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1738                                       TEGRA_MC_PRIO_MED);
1739 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1740                 /* only present on Tegra2 and 3 */
1741                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1742                                       TEGRA_MC_PRIO_MED);
1743 #endif
1744                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1745                                       TEGRA_MC_PRIO_HIGH);
1746         }
1747         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1748                         DC_CMD_CONT_SYNCPT_VSYNC);
1749
1750         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1751         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1752         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1753         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1754 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1755         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1756 #endif
1757         /* enable interrupts for vblank, frame_end and underflows */
1758         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1759         /* for panels with one-shot mode enable tearing effect interrupt */
1760         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1761                 int_enable |= MSF_INT;
1762
1763         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1764         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1765         tegra_dc_init_vpulse2_int(dc);
1766
1767         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1768
1769 #ifdef CONFIG_TEGRA_DC_CMU
1770         if (dc->pdata->cmu)
1771                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1772         else
1773                 _tegra_dc_update_cmu(dc, &default_cmu);
1774 #endif
1775         tegra_dc_set_color_control(dc);
1776         for (i = 0; i < DC_N_WINDOWS; i++) {
1777                 struct tegra_dc_win *win = &dc->windows[i];
1778                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1779                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1780                 tegra_dc_set_csc(dc, &win->csc);
1781                 tegra_dc_set_lut(dc, win);
1782                 tegra_dc_set_scaling_filter(dc);
1783         }
1784
1785         for (i = 0; i < dc->n_windows; i++) {
1786                 u32 syncpt = get_syncpt(dc, i);
1787
1788                 dc->syncpt[i].id = syncpt;
1789
1790                 dc->syncpt[i].min = dc->syncpt[i].max =
1791                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1792         }
1793
1794         trace_display_mode(dc, &dc->mode);
1795
1796         if (dc->mode.pclk) {
1797                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1798                         tegra_dc_io_end(dc);
1799                         return -EINVAL;
1800                 }
1801         }
1802
1803         /* Initialize SD AFTER the modeset.
1804            nvsd_init handles the sd_settings = NULL case. */
1805         nvsd_init(dc, dc->out->sd_settings);
1806
1807         tegra_dc_io_end(dc);
1808
1809         return 0;
1810 }
1811
1812 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1813 {
1814         int failed_init = 0;
1815
1816         tegra_dc_unpowergate_locked(dc);
1817
1818         if (dc->out->enable)
1819                 dc->out->enable(&dc->ndev->dev);
1820
1821         tegra_dc_setup_clk(dc, dc->clk);
1822         tegra_dc_clk_enable(dc);
1823         tegra_dc_io_start(dc);
1824
1825         tegra_dc_power_on(dc);
1826
1827         /* do not accept interrupts during initialization */
1828         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1829
1830         enable_dc_irq(dc);
1831
1832         failed_init = tegra_dc_init(dc);
1833         if (failed_init) {
1834                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1835                 disable_irq_nosync(dc->irq);
1836                 tegra_dc_clear_bandwidth(dc);
1837                 tegra_dc_clk_disable(dc);
1838                 if (dc->out && dc->out->disable)
1839                         dc->out->disable();
1840                 tegra_dc_io_end(dc);
1841                 return false;
1842         }
1843
1844         if (dc->out_ops && dc->out_ops->enable)
1845                 dc->out_ops->enable(dc);
1846
1847         /* force a full blending update */
1848         dc->blend.z[0] = -1;
1849
1850         tegra_dc_ext_enable(dc->ext);
1851
1852         trace_display_enable(dc);
1853
1854         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1855         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1856
1857         if (dc->out->postpoweron)
1858                 dc->out->postpoweron();
1859
1860         tegra_dc_io_end(dc);
1861         return true;
1862 }
1863
1864 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1865 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1866 {
1867         bool ret = true;
1868
1869         if (dc->out->enable)
1870                 dc->out->enable(&dc->ndev->dev);
1871
1872         tegra_dc_setup_clk(dc, dc->clk);
1873         tegra_dc_clk_enable(dc);
1874
1875         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1876                 mutex_lock(&tegra_dcs[1]->lock);
1877                 disable_irq_nosync(tegra_dcs[1]->irq);
1878         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1879                 mutex_lock(&tegra_dcs[0]->lock);
1880                 disable_irq_nosync(tegra_dcs[0]->irq);
1881         }
1882
1883         msleep(5);
1884         tegra_periph_reset_assert(dc->clk);
1885         msleep(2);
1886 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1887         tegra_periph_reset_deassert(dc->clk);
1888         msleep(1);
1889 #endif
1890
1891         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1892                 enable_dc_irq(tegra_dcs[1]);
1893                 mutex_unlock(&tegra_dcs[1]->lock);
1894         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1895                 enable_dc_irq(tegra_dcs[0]);
1896                 mutex_unlock(&tegra_dcs[0]->lock);
1897         }
1898
1899         enable_dc_irq(dc);
1900
1901         if (tegra_dc_init(dc)) {
1902                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1903                 ret = false;
1904         }
1905
1906         if (dc->out_ops && dc->out_ops->enable)
1907                 dc->out_ops->enable(dc);
1908
1909         if (dc->out->postpoweron)
1910                 dc->out->postpoweron();
1911
1912         /* force a full blending update */
1913         dc->blend.z[0] = -1;
1914
1915         tegra_dc_ext_enable(dc->ext);
1916
1917         if (!ret) {
1918                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1919                 _tegra_dc_controller_disable(dc);
1920         }
1921
1922         trace_display_reset(dc);
1923         return ret;
1924 }
1925 #endif
1926
1927 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1928 {
1929         if (dc->mode.pclk == 0) {
1930                 switch (dc->out->type) {
1931                 case TEGRA_DC_OUT_HDMI:
1932                 /* DC enable called but no videomode is loaded.
1933                      Check if HDMI is connected, then set fallback mdoe */
1934                 if (tegra_dc_hpd(dc)) {
1935                         return tegra_dc_set_fb_mode(dc,
1936                                         &tegra_dc_hdmi_fallback_mode, 0);
1937                 } else
1938                         return false;
1939
1940                 break;
1941
1942                 /* Do nothing for other outputs for now */
1943                 case TEGRA_DC_OUT_RGB:
1944
1945                 case TEGRA_DC_OUT_DSI:
1946
1947                 default:
1948                         return false;
1949                 }
1950         }
1951
1952         return false;
1953 }
1954
1955 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1956 {
1957         return _tegra_dc_set_default_videomode(dc);
1958 }
1959
1960 static bool _tegra_dc_enable(struct tegra_dc *dc)
1961 {
1962         if (dc->mode.pclk == 0)
1963                 return false;
1964
1965         if (!dc->out)
1966                 return false;
1967
1968         if (dc->enabled)
1969                 return true;
1970
1971         pm_runtime_get_sync(&dc->ndev->dev);
1972
1973         if (!_tegra_dc_controller_enable(dc)) {
1974                 pm_runtime_put_sync(&dc->ndev->dev);
1975                 return false;
1976         }
1977
1978         return true;
1979 }
1980
1981 void tegra_dc_enable(struct tegra_dc *dc)
1982 {
1983         mutex_lock(&dc->lock);
1984
1985         if (!dc->enabled)
1986                 dc->enabled = _tegra_dc_enable(dc);
1987
1988         mutex_unlock(&dc->lock);
1989         trace_display_mode(dc, &dc->mode);
1990 }
1991
1992 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1993 {
1994         unsigned i;
1995
1996         tegra_dc_hold_dc_out(dc);
1997
1998         if (dc->out && dc->out->prepoweroff)
1999                 dc->out->prepoweroff();
2000
2001         if (dc->out_ops && dc->out_ops->disable)
2002                 dc->out_ops->disable(dc);
2003
2004         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2005
2006         disable_irq_nosync(dc->irq);
2007
2008         tegra_dc_clear_bandwidth(dc);
2009
2010         /* ugly hack */
2011         if (dc->out_ops->release &&
2012                 (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE))
2013                 tegra_dc_release_dc_out(dc);
2014         else
2015                 tegra_dc_clk_disable(dc);
2016
2017         if (dc->out && dc->out->disable)
2018                 dc->out->disable();
2019
2020         for (i = 0; i < dc->n_windows; i++) {
2021                 struct tegra_dc_win *w = &dc->windows[i];
2022
2023                 /* reset window bandwidth */
2024                 w->bandwidth = 0;
2025                 w->new_bandwidth = 0;
2026
2027                 /* disable windows */
2028                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2029
2030                 /* flush any pending syncpt waits */
2031                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2032                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2033                                 dc->syncpt[i].min, dc->syncpt[i].max);
2034                         dc->syncpt[i].min++;
2035                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2036                 }
2037         }
2038         trace_display_disable(dc);
2039 }
2040
2041 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2042 {
2043 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2044         u32 val;
2045         if (dc->enabled)  {
2046                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2047                 if (enable)
2048                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2049                 else
2050                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2051                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2052         }
2053 #endif
2054 }
2055
2056 bool tegra_dc_stats_get(struct tegra_dc *dc)
2057 {
2058 #if 0 /* right now it is always enabled */
2059         u32 val;
2060         bool res;
2061
2062         if (dc->enabled)  {
2063                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2064                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2065         } else {
2066                 res = false;
2067         }
2068
2069         return res;
2070 #endif
2071         return true;
2072 }
2073
2074 /* make the screen blank by disabling all windows */
2075 void tegra_dc_blank(struct tegra_dc *dc)
2076 {
2077         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2078         unsigned i;
2079
2080         for (i = 0; i < DC_N_WINDOWS; i++) {
2081                 dcwins[i] = tegra_dc_get_window(dc, i);
2082                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2083         }
2084
2085         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2086         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2087 }
2088
2089 static void _tegra_dc_disable(struct tegra_dc *dc)
2090 {
2091         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2092                 mutex_lock(&dc->one_shot_lock);
2093                 cancel_delayed_work_sync(&dc->one_shot_work);
2094         }
2095
2096         tegra_dc_io_start(dc);
2097         _tegra_dc_controller_disable(dc);
2098         tegra_dc_io_end(dc);
2099
2100         tegra_dc_powergate_locked(dc);
2101
2102         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2103                 mutex_unlock(&dc->one_shot_lock);
2104         pm_runtime_put(&dc->ndev->dev);
2105 }
2106
2107 void tegra_dc_disable(struct tegra_dc *dc)
2108 {
2109         tegra_dc_ext_disable(dc->ext);
2110
2111         /* it's important that new underflow work isn't scheduled before the
2112          * lock is acquired. */
2113         cancel_delayed_work_sync(&dc->underflow_work);
2114
2115         mutex_lock(&dc->lock);
2116
2117         if (dc->enabled) {
2118                 dc->enabled = false;
2119
2120                 if (!dc->suspended)
2121                         _tegra_dc_disable(dc);
2122         }
2123
2124 #ifdef CONFIG_SWITCH
2125         switch_set_state(&dc->modeset_switch, 0);
2126 #endif
2127
2128         mutex_unlock(&dc->lock);
2129         synchronize_irq(dc->irq);
2130         trace_display_mode(dc, &dc->mode);
2131 }
2132
2133 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2134 static void tegra_dc_reset_worker(struct work_struct *work)
2135 {
2136         struct tegra_dc *dc =
2137                 container_of(work, struct tegra_dc, reset_work);
2138
2139         unsigned long val = 0;
2140
2141         mutex_lock(&shared_lock);
2142
2143         dev_warn(&dc->ndev->dev,
2144                 "overlay stuck in underflow state.  resetting.\n");
2145
2146         tegra_dc_ext_disable(dc->ext);
2147
2148         mutex_lock(&dc->lock);
2149
2150         if (dc->enabled == false)
2151                 goto unlock;
2152
2153         dc->enabled = false;
2154
2155         /*
2156          * off host read bus
2157          */
2158         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2159         val &= ~(0x00000100);
2160         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2161
2162         /*
2163          * set DC to STOP mode
2164          */
2165         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2166
2167         msleep(10);
2168
2169         _tegra_dc_controller_disable(dc);
2170
2171         /* _tegra_dc_controller_reset_enable deasserts reset */
2172         _tegra_dc_controller_reset_enable(dc);
2173
2174         dc->enabled = true;
2175
2176         /* reopen host read bus */
2177         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2178         val &= ~(0x00000100);
2179         val |= 0x100;
2180         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2181
2182 unlock:
2183         mutex_unlock(&dc->lock);
2184         mutex_unlock(&shared_lock);
2185         trace_display_reset(dc);
2186 }
2187 #endif
2188
2189 static void tegra_dc_underflow_worker(struct work_struct *work)
2190 {
2191         struct tegra_dc *dc = container_of(
2192                 to_delayed_work(work), struct tegra_dc, underflow_work);
2193
2194         mutex_lock(&dc->lock);
2195         tegra_dc_io_start(dc);
2196         tegra_dc_hold_dc_out(dc);
2197
2198         if (dc->enabled) {
2199                 tegra_dc_underflow_handler(dc);
2200         }
2201         tegra_dc_release_dc_out(dc);
2202         tegra_dc_io_end(dc);
2203         mutex_unlock(&dc->lock);
2204 }
2205
2206 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2207 /* A mutex used to protect the critical section used by both DC heads. */
2208 static struct mutex tegra_dc_powergate_status_lock;
2209
2210 /* defer turning off DISA until DISB is turned off */
2211 void tegra_dc_powergate_locked(struct tegra_dc *dc)
2212 {
2213         struct tegra_dc *dc_partner;
2214
2215         mutex_lock(&tegra_dc_powergate_status_lock);
2216         /* Get the handler of the other display controller. */
2217         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2218         if (!dc_partner)
2219                 _tegra_dc_powergate_locked(dc);
2220         else if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2221                 /* If DISB is powergated, then powergate DISA. */
2222                 if (!dc_partner->powered)
2223                         _tegra_dc_powergate_locked(dc);
2224         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2225                 /* If DISA is enabled, only powergate DISB;
2226                  * otherwise, powergate DISA and DISB.
2227                  * */
2228                 if (dc_partner->enabled) {
2229                         _tegra_dc_powergate_locked(dc);
2230                 } else {
2231                         _tegra_dc_powergate_locked(dc);
2232                         _tegra_dc_powergate_locked(dc_partner);
2233                 }
2234         }
2235         mutex_unlock(&tegra_dc_powergate_status_lock);
2236 }
2237
2238
2239 /* to turn on DISB we must first power on DISA */
2240 void tegra_dc_unpowergate_locked(struct tegra_dc *dc)
2241 {
2242         mutex_lock(&tegra_dc_powergate_status_lock);
2243         if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2244                 struct tegra_dc *dc_partner;
2245
2246                 /* Get the handler of the other display controller. */
2247                 dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2248                 if (dc_partner)
2249                         _tegra_dc_unpowergate_locked(dc_partner);
2250         }
2251         _tegra_dc_unpowergate_locked(dc);
2252         mutex_unlock(&tegra_dc_powergate_status_lock);
2253 }
2254 #endif
2255
2256 #ifdef CONFIG_SWITCH
2257 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2258 {
2259         struct tegra_dc *dc =
2260                 container_of(sdev, struct tegra_dc, modeset_switch);
2261
2262         if (!sdev->state)
2263                 return sprintf(buf, "offline\n");
2264
2265         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2266 }
2267 #endif
2268
2269 static void tegra_dc_add_modes(struct tegra_dc *dc)
2270 {
2271         struct fb_monspecs specs;
2272         int i;
2273
2274         memset(&specs, 0, sizeof(specs));
2275         specs.max_x = dc->mode.h_active * 1000;
2276         specs.max_y = dc->mode.v_active * 1000;
2277         specs.modedb_len = dc->out->n_modes;
2278         specs.modedb = kzalloc(specs.modedb_len *
2279                 sizeof(struct fb_videomode), GFP_KERNEL);
2280         for (i = 0; i < dc->out->n_modes; i++)
2281                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2282                         &dc->out->modes[i]);
2283         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2284         kfree(specs.modedb);
2285 }
2286
2287 static int tegra_dc_probe(struct platform_device *ndev)
2288 {
2289         struct tegra_dc *dc;
2290         struct tegra_dc_mode *mode;
2291         struct clk *clk;
2292         struct clk *emc_clk;
2293         struct resource *res;
2294         struct resource *base_res;
2295         struct resource *fb_mem = NULL;
2296         int ret = 0;
2297         void __iomem *base;
2298         int irq;
2299         int i;
2300
2301         if (!ndev->dev.platform_data) {
2302                 dev_err(&ndev->dev, "no platform data\n");
2303                 return -ENOENT;
2304         }
2305
2306         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2307         if (!dc) {
2308                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2309                 return -ENOMEM;
2310         }
2311
2312         irq = platform_get_irq_byname(ndev, "irq");
2313         if (irq <= 0) {
2314                 dev_err(&ndev->dev, "no irq\n");
2315                 ret = -ENOENT;
2316                 goto err_free;
2317         }
2318
2319         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2320         if (!res) {
2321                 dev_err(&ndev->dev, "no mem resource\n");
2322                 ret = -ENOENT;
2323                 goto err_free;
2324         }
2325
2326         base_res = request_mem_region(res->start, resource_size(res),
2327                 ndev->name);
2328         if (!base_res) {
2329                 dev_err(&ndev->dev, "request_mem_region failed\n");
2330                 ret = -EBUSY;
2331                 goto err_free;
2332         }
2333
2334         base = ioremap(res->start, resource_size(res));
2335         if (!base) {
2336                 dev_err(&ndev->dev, "registers can't be mapped\n");
2337                 ret = -EBUSY;
2338                 goto err_release_resource_reg;
2339         }
2340         if (TEGRA_DISPLAY_BASE == res->start) {
2341                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2342                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2343                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2344                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2345                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2346         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2347                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2348                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2349                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2350                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2351                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2352         } else {
2353                 dev_err(&ndev->dev,
2354                         "Unknown base address %#08x: unable to assign syncpt\n",
2355                         res->start);
2356         }
2357
2358
2359         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2360
2361         clk = clk_get(&ndev->dev, NULL);
2362         if (IS_ERR_OR_NULL(clk)) {
2363                 dev_err(&ndev->dev, "can't get clock\n");
2364                 ret = -ENOENT;
2365                 goto err_iounmap_reg;
2366         }
2367
2368         emc_clk = clk_get(&ndev->dev, "emc");
2369         if (IS_ERR_OR_NULL(emc_clk)) {
2370                 dev_err(&ndev->dev, "can't get emc clock\n");
2371                 ret = -ENOENT;
2372                 goto err_put_clk;
2373         }
2374
2375         dc->clk = clk;
2376         dc->emc_clk = emc_clk;
2377         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2378         /* Initialize one shot work delay, it will be assigned by dsi
2379          * according to refresh rate later. */
2380         dc->one_shot_delay_ms = 40;
2381
2382         dc->base_res = base_res;
2383         dc->base = base;
2384         dc->irq = irq;
2385         dc->ndev = ndev;
2386         dc->pdata = ndev->dev.platform_data;
2387
2388         /*
2389          * The emc is a shared clock, it will be set based on
2390          * the requirements for each user on the bus.
2391          */
2392         dc->emc_clk_rate = 0;
2393
2394         mutex_init(&dc->lock);
2395         mutex_init(&dc->one_shot_lock);
2396 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2397         mutex_init(&tegra_dc_powergate_status_lock);
2398 #endif
2399         init_completion(&dc->frame_end_complete);
2400         init_waitqueue_head(&dc->wq);
2401         init_waitqueue_head(&dc->timestamp_wq);
2402 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2403         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2404 #endif
2405         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2406         dc->vblank_ref_count = 0;
2407 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2408         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2409 #endif
2410         dc->vpulse2_ref_count = 0;
2411         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2412         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2413
2414         tegra_dc_init_lut_defaults(&dc->fb_lut);
2415
2416         dc->n_windows = DC_N_WINDOWS;
2417         for (i = 0; i < dc->n_windows; i++) {
2418                 struct tegra_dc_win *win = &dc->windows[i];
2419                 win->idx = i;
2420                 win->dc = dc;
2421                 tegra_dc_init_csc_defaults(&win->csc);
2422                 tegra_dc_init_lut_defaults(&win->lut);
2423         }
2424
2425         ret = tegra_dc_set(dc, ndev->id);
2426         if (ret < 0) {
2427                 dev_err(&ndev->dev, "can't add dc\n");
2428                 goto err_put_emc_clk;
2429         }
2430
2431         platform_set_drvdata(ndev, dc);
2432
2433 #ifdef CONFIG_SWITCH
2434         dc->modeset_switch.name = dev_name(&ndev->dev);
2435         dc->modeset_switch.state = 0;
2436         dc->modeset_switch.print_state = switch_modeset_print_mode;
2437         ret = switch_dev_register(&dc->modeset_switch);
2438         if (ret < 0)
2439                 dev_err(&ndev->dev, "failed to register switch driver\n");
2440 #endif
2441
2442         tegra_dc_feature_register(dc);
2443
2444         if (dc->pdata->default_out)
2445                 tegra_dc_set_out(dc, dc->pdata->default_out);
2446         else
2447                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2448         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2449
2450         dc->ext = tegra_dc_ext_register(ndev, dc);
2451         if (IS_ERR_OR_NULL(dc->ext)) {
2452                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2453                 dc->ext = NULL;
2454         }
2455
2456         /* interrupt handler must be registered before tegra_fb_register() */
2457         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2458                         dev_name(&ndev->dev), dc)) {
2459                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2460                 ret = -EBUSY;
2461                 goto err_disable_dc;
2462         }
2463         disable_dc_irq(dc);
2464
2465         pm_runtime_use_autosuspend(&ndev->dev);
2466         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
2467         pm_runtime_enable(&ndev->dev);
2468
2469         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2470                 _tegra_dc_set_default_videomode(dc);
2471                 dc->enabled = _tegra_dc_enable(dc);
2472         }
2473
2474         tegra_dc_create_debugfs(dc);
2475
2476         dev_info(&ndev->dev, "probed\n");
2477
2478         if (dc->pdata->fb) {
2479                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2480                         unsigned long fmt;
2481                         tegra_dc_writel(dc,
2482                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2483                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2484
2485                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2486                         dc->pdata->fb->bits_per_pixel =
2487                                 tegra_dc_fmt_bpp(fmt);
2488                 }
2489
2490                 mode = tegra_dc_get_override_mode(dc);
2491                 if (mode) {
2492                         dc->pdata->fb->xres = mode->h_active;
2493                         dc->pdata->fb->yres = mode->v_active;
2494                 }
2495
2496                 tegra_dc_io_start(dc);
2497                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2498                 tegra_dc_io_end(dc);
2499                 if (IS_ERR_OR_NULL(dc->fb)) {
2500                         dc->fb = NULL;
2501                         dev_err(&ndev->dev, "failed to register fb\n");
2502                         goto err_remove_debugfs;
2503                 }
2504         }
2505
2506         if (dc->out && dc->out->n_modes)
2507                 tegra_dc_add_modes(dc);
2508
2509         if (dc->out && dc->out->hotplug_init)
2510                 dc->out->hotplug_init(&ndev->dev);
2511
2512         if (dc->out_ops && dc->out_ops->detect)
2513                 dc->out_ops->detect(dc);
2514         else
2515                 dc->connected = true;
2516
2517         /* Powergate display module when it's unconnected. */
2518         if (!tegra_dc_get_connected(dc))
2519                 tegra_dc_powergate_locked(dc);
2520
2521         tegra_dc_create_sysfs(&dc->ndev->dev);
2522
2523         return 0;
2524
2525 err_remove_debugfs:
2526         tegra_dc_remove_debugfs(dc);
2527         free_irq(irq, dc);
2528 err_disable_dc:
2529         if (dc->ext) {
2530                 tegra_dc_ext_disable(dc->ext);
2531                 tegra_dc_ext_unregister(dc->ext);
2532         }
2533         mutex_lock(&dc->lock);
2534         if (dc->enabled)
2535                 _tegra_dc_disable(dc);
2536         dc->enabled = false;
2537         mutex_unlock(&dc->lock);
2538 #ifdef CONFIG_SWITCH
2539         switch_dev_unregister(&dc->modeset_switch);
2540 #endif
2541 err_put_emc_clk:
2542         clk_put(emc_clk);
2543 err_put_clk:
2544         clk_put(clk);
2545 err_iounmap_reg:
2546         iounmap(base);
2547         if (fb_mem)
2548                 release_resource(fb_mem);
2549 err_release_resource_reg:
2550         release_resource(base_res);
2551 err_free:
2552         kfree(dc);
2553
2554         return ret;
2555 }
2556
2557 static int tegra_dc_remove(struct platform_device *ndev)
2558 {
2559         struct tegra_dc *dc = platform_get_drvdata(ndev);
2560
2561         tegra_dc_remove_sysfs(&dc->ndev->dev);
2562         tegra_dc_remove_debugfs(dc);
2563
2564         if (dc->fb) {
2565                 tegra_fb_unregister(dc->fb);
2566                 if (dc->fb_mem)
2567                         release_resource(dc->fb_mem);
2568         }
2569
2570         tegra_dc_ext_disable(dc->ext);
2571
2572         if (dc->ext)
2573                 tegra_dc_ext_unregister(dc->ext);
2574
2575         mutex_lock(&dc->lock);
2576         if (dc->enabled)
2577                 _tegra_dc_disable(dc);
2578         dc->enabled = false;
2579         mutex_unlock(&dc->lock);
2580         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2581
2582 #ifdef CONFIG_SWITCH
2583         switch_dev_unregister(&dc->modeset_switch);
2584 #endif
2585         free_irq(dc->irq, dc);
2586         clk_put(dc->emc_clk);
2587         clk_put(dc->clk);
2588         iounmap(dc->base);
2589         if (dc->fb_mem)
2590                 release_resource(dc->base_res);
2591         kfree(dc);
2592         tegra_dc_set(NULL, ndev->id);
2593
2594         return 0;
2595 }
2596
2597 #ifdef CONFIG_PM
2598 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2599 {
2600         struct tegra_dc *dc = platform_get_drvdata(ndev);
2601
2602         trace_display_suspend(dc);
2603         dev_info(&ndev->dev, "suspend\n");
2604
2605         tegra_dc_ext_disable(dc->ext);
2606
2607         mutex_lock(&dc->lock);
2608         tegra_dc_io_start(dc);
2609
2610         if (dc->out_ops && dc->out_ops->suspend)
2611                 dc->out_ops->suspend(dc);
2612
2613         if (dc->enabled) {
2614                 _tegra_dc_disable(dc);
2615
2616                 dc->suspended = true;
2617         }
2618
2619         if (dc->out && dc->out->postsuspend) {
2620                 dc->out->postsuspend();
2621                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2622                         /*
2623                          * avoid resume event due to voltage falling
2624                          */
2625                         msleep(100);
2626         }
2627
2628         tegra_dc_io_end(dc);
2629         mutex_unlock(&dc->lock);
2630         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2631
2632         return 0;
2633 }
2634
2635 static int tegra_dc_resume(struct platform_device *ndev)
2636 {
2637         struct tegra_dc *dc = platform_get_drvdata(ndev);
2638
2639         trace_display_resume(dc);
2640         dev_info(&ndev->dev, "resume\n");
2641
2642         mutex_lock(&dc->lock);
2643         dc->suspended = false;
2644
2645         if (dc->enabled) {
2646                 dc->enabled = false;
2647                 _tegra_dc_set_default_videomode(dc);
2648                 dc->enabled = _tegra_dc_enable(dc);
2649         }
2650
2651         if (dc->out && dc->out->hotplug_init)
2652                 dc->out->hotplug_init(&ndev->dev);
2653
2654         if (dc->out_ops && dc->out_ops->resume)
2655                 dc->out_ops->resume(dc);
2656         mutex_unlock(&dc->lock);
2657
2658         return 0;
2659 }
2660
2661 #endif /* CONFIG_PM */
2662
2663 static void tegra_dc_shutdown(struct platform_device *ndev)
2664 {
2665         struct tegra_dc *dc = platform_get_drvdata(ndev);
2666
2667         if (!dc || !dc->enabled)
2668                 return;
2669
2670         tegra_dc_blank(dc);
2671         tegra_dc_disable(dc);
2672 }
2673
2674 extern int suspend_set(const char *val, struct kernel_param *kp)
2675 {
2676         if (!strcmp(val, "dump"))
2677                 dump_regs(tegra_dcs[0]);
2678 #ifdef CONFIG_PM
2679         else if (!strcmp(val, "suspend"))
2680                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2681         else if (!strcmp(val, "resume"))
2682                 tegra_dc_resume(tegra_dcs[0]->ndev);
2683 #endif
2684
2685         return 0;
2686 }
2687
2688 extern int suspend_get(char *buffer, struct kernel_param *kp)
2689 {
2690         return 0;
2691 }
2692
2693 int suspend;
2694
2695 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2696
2697 struct platform_driver tegra_dc_driver = {
2698         .driver = {
2699                 .name = "tegradc",
2700                 .owner = THIS_MODULE,
2701         },
2702         .probe = tegra_dc_probe,
2703         .remove = tegra_dc_remove,
2704 #ifdef CONFIG_PM
2705         .suspend = tegra_dc_suspend,
2706         .resume = tegra_dc_resume,
2707 #endif
2708         .shutdown = tegra_dc_shutdown,
2709 };
2710
2711 #ifndef MODULE
2712 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2713 {
2714         int i, params[11];
2715         char *p;
2716
2717         for (i = 0; i < ARRAY_SIZE(params); i++) {
2718                 if ((p = strsep(&options, ",")) != NULL) {
2719                         if (*p)
2720                                 params[i] = simple_strtoul(p, &p, 10);
2721                 } else
2722                         return -EINVAL;
2723         }
2724
2725         if ((mode->pclk = params[0]) == 0)
2726                 return -EINVAL;
2727
2728         mode->h_active      = params[1];
2729         mode->v_active      = params[2];
2730         mode->h_ref_to_sync = params[3];
2731         mode->v_ref_to_sync = params[4];
2732         mode->h_sync_width  = params[5];
2733         mode->v_sync_width  = params[6];
2734         mode->h_back_porch  = params[7];
2735         mode->v_back_porch  = params[8];
2736         mode->h_front_porch = params[9];
2737         mode->v_front_porch = params[10];
2738
2739         return 0;
2740 }
2741
2742 static int __init tegra_dc_mode_override(char *str)
2743 {
2744         char *p = str, *options;
2745
2746         if (!p || !*p)
2747                 return -EINVAL;
2748
2749         p = strstr(str, "hdmi:");
2750         if (p) {
2751                 p += 5;
2752                 options = strsep(&p, ";");
2753                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2754                         return -EINVAL;
2755         }
2756
2757         p = strstr(str, "rgb:");
2758         if (p) {
2759                 p += 4;
2760                 options = strsep(&p, ";");
2761                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2762                         return -EINVAL;
2763         }
2764
2765         p = strstr(str, "dsi:");
2766         if (p) {
2767                 p += 4;
2768                 options = strsep(&p, ";");
2769                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2770                         return -EINVAL;
2771         }
2772
2773         return 0;
2774 }
2775
2776 __setup("disp_params=", tegra_dc_mode_override);
2777 #endif
2778
2779 static int __init tegra_dc_module_init(void)
2780 {
2781         int ret = tegra_dc_ext_module_init();
2782         if (ret)
2783                 return ret;
2784         return platform_driver_register(&tegra_dc_driver);
2785 }
2786
2787 static void __exit tegra_dc_module_exit(void)
2788 {
2789         platform_driver_unregister(&tegra_dc_driver);
2790         tegra_dc_ext_module_exit();
2791 }
2792
2793 module_exit(tegra_dc_module_exit);
2794 module_init(tegra_dc_module_init);