video: tegra: dc: update sd backlight on vpulse2
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
67         .refresh = 60,
68         .xres = 640,
69         .yres = 480,
70         .pixclock = KHZ2PICOS(25200),
71         .hsync_len = 96,        /* h_sync_width */
72         .vsync_len = 2,         /* v_sync_width */
73         .left_margin = 48,      /* h_back_porch */
74         .upper_margin = 33,     /* v_back_porch */
75         .right_margin = 16,     /* h_front_porch */
76         .lower_margin = 10,     /* v_front_porch */
77         .vmode = 0,
78         .sync = 0,
79 };
80
81 static struct tegra_dc_mode override_disp_mode[3];
82
83 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
84
85 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
86
87 DEFINE_MUTEX(tegra_dc_lock);
88 DEFINE_MUTEX(shared_lock);
89
90 static const struct {
91         bool h;
92         bool v;
93 } can_filter[] = {
94         /* Window A has no filtering */
95         { false, false },
96         /* Window B has both H and V filtering */
97         { true,  true  },
98         /* Window C has only H filtering */
99         { false, true  },
100 };
101
102 #ifdef CONFIG_TEGRA_DC_CMU
103 static struct tegra_dc_cmu default_cmu = {
104         /* lut1 maps sRGB to linear space. */
105         {
106                 0,    1,    2,    4,    5,    6,    7,    9,
107                 10,   11,   12,   14,   15,   16,   18,   20,
108                 21,   23,   25,   27,   29,   31,   33,   35,
109                 37,   40,   42,   45,   48,   50,   53,   56,
110                 59,   62,   66,   69,   72,   76,   79,   83,
111                 87,   91,   95,   99,   103,  107,  112,  116,
112                 121,  126,  131,  136,  141,  146,  151,  156,
113                 162,  168,  173,  179,  185,  191,  197,  204,
114                 210,  216,  223,  230,  237,  244,  251,  258,
115                 265,  273,  280,  288,  296,  304,  312,  320,
116                 329,  337,  346,  354,  363,  372,  381,  390,
117                 400,  409,  419,  428,  438,  448,  458,  469,
118                 479,  490,  500,  511,  522,  533,  544,  555,
119                 567,  578,  590,  602,  614,  626,  639,  651,
120                 664,  676,  689,  702,  715,  728,  742,  755,
121                 769,  783,  797,  811,  825,  840,  854,  869,
122                 884,  899,  914,  929,  945,  960,  976,  992,
123                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
124                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
125                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
126                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
127                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
128                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
129                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
130                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
131                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
132                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
133                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
134                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
135                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
136                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
137                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
138         },
139         /* csc */
140         {
141                 0x100, 0x0,   0x0,
142                 0x0,   0x100, 0x0,
143                 0x0,   0x0,   0x100,
144         },
145         /* lut2 maps linear space to sRGB*/
146         {
147                 0,    1,    2,    2,    3,    4,    5,    6,
148                 6,    7,    8,    9,    10,   10,   11,   12,
149                 13,   13,   14,   15,   15,   16,   16,   17,
150                 18,   18,   19,   19,   20,   20,   21,   21,
151                 22,   22,   23,   23,   23,   24,   24,   25,
152                 25,   25,   26,   26,   27,   27,   27,   28,
153                 28,   29,   29,   29,   30,   30,   30,   31,
154                 31,   31,   32,   32,   32,   33,   33,   33,
155                 34,   34,   34,   34,   35,   35,   35,   36,
156                 36,   36,   37,   37,   37,   37,   38,   38,
157                 38,   38,   39,   39,   39,   40,   40,   40,
158                 40,   41,   41,   41,   41,   42,   42,   42,
159                 42,   43,   43,   43,   43,   43,   44,   44,
160                 44,   44,   45,   45,   45,   45,   46,   46,
161                 46,   46,   46,   47,   47,   47,   47,   48,
162                 48,   48,   48,   48,   49,   49,   49,   49,
163                 49,   50,   50,   50,   50,   50,   51,   51,
164                 51,   51,   51,   52,   52,   52,   52,   52,
165                 53,   53,   53,   53,   53,   54,   54,   54,
166                 54,   54,   55,   55,   55,   55,   55,   55,
167                 56,   56,   56,   56,   56,   57,   57,   57,
168                 57,   57,   57,   58,   58,   58,   58,   58,
169                 58,   59,   59,   59,   59,   59,   59,   60,
170                 60,   60,   60,   60,   60,   61,   61,   61,
171                 61,   61,   61,   62,   62,   62,   62,   62,
172                 62,   63,   63,   63,   63,   63,   63,   64,
173                 64,   64,   64,   64,   64,   64,   65,   65,
174                 65,   65,   65,   65,   66,   66,   66,   66,
175                 66,   66,   66,   67,   67,   67,   67,   67,
176                 67,   67,   68,   68,   68,   68,   68,   68,
177                 68,   69,   69,   69,   69,   69,   69,   69,
178                 70,   70,   70,   70,   70,   70,   70,   71,
179                 71,   71,   71,   71,   71,   71,   72,   72,
180                 72,   72,   72,   72,   72,   72,   73,   73,
181                 73,   73,   73,   73,   73,   74,   74,   74,
182                 74,   74,   74,   74,   74,   75,   75,   75,
183                 75,   75,   75,   75,   75,   76,   76,   76,
184                 76,   76,   76,   76,   77,   77,   77,   77,
185                 77,   77,   77,   77,   78,   78,   78,   78,
186                 78,   78,   78,   78,   78,   79,   79,   79,
187                 79,   79,   79,   79,   79,   80,   80,   80,
188                 80,   80,   80,   80,   80,   81,   81,   81,
189                 81,   81,   81,   81,   81,   81,   82,   82,
190                 82,   82,   82,   82,   82,   82,   83,   83,
191                 83,   83,   83,   83,   83,   83,   83,   84,
192                 84,   84,   84,   84,   84,   84,   84,   84,
193                 85,   85,   85,   85,   85,   85,   85,   85,
194                 85,   86,   86,   86,   86,   86,   86,   86,
195                 86,   86,   87,   87,   87,   87,   87,   87,
196                 87,   87,   87,   88,   88,   88,   88,   88,
197                 88,   88,   88,   88,   88,   89,   89,   89,
198                 89,   89,   89,   89,   89,   89,   90,   90,
199                 90,   90,   90,   90,   90,   90,   90,   90,
200                 91,   91,   91,   91,   91,   91,   91,   91,
201                 91,   91,   92,   92,   92,   92,   92,   92,
202                 92,   92,   92,   92,   93,   93,   93,   93,
203                 93,   93,   93,   93,   93,   93,   94,   94,
204                 94,   94,   94,   94,   94,   94,   94,   94,
205                 95,   95,   95,   95,   95,   95,   95,   95,
206                 95,   95,   96,   96,   96,   96,   96,   96,
207                 96,   96,   96,   96,   96,   97,   97,   97,
208                 97,   97,   97,   97,   97,   97,   97,   98,
209                 98,   98,   98,   98,   98,   98,   98,   98,
210                 98,   98,   99,   99,   99,   99,   99,   99,
211                 99,   100,  101,  101,  102,  103,  103,  104,
212                 105,  105,  106,  107,  107,  108,  109,  109,
213                 110,  111,  111,  112,  113,  113,  114,  115,
214                 115,  116,  116,  117,  118,  118,  119,  119,
215                 120,  120,  121,  122,  122,  123,  123,  124,
216                 124,  125,  126,  126,  127,  127,  128,  128,
217                 129,  129,  130,  130,  131,  131,  132,  132,
218                 133,  133,  134,  134,  135,  135,  136,  136,
219                 137,  137,  138,  138,  139,  139,  140,  140,
220                 141,  141,  142,  142,  143,  143,  144,  144,
221                 145,  145,  145,  146,  146,  147,  147,  148,
222                 148,  149,  149,  150,  150,  150,  151,  151,
223                 152,  152,  153,  153,  153,  154,  154,  155,
224                 155,  156,  156,  156,  157,  157,  158,  158,
225                 158,  159,  159,  160,  160,  160,  161,  161,
226                 162,  162,  162,  163,  163,  164,  164,  164,
227                 165,  165,  166,  166,  166,  167,  167,  167,
228                 168,  168,  169,  169,  169,  170,  170,  170,
229                 171,  171,  172,  172,  172,  173,  173,  173,
230                 174,  174,  174,  175,  175,  176,  176,  176,
231                 177,  177,  177,  178,  178,  178,  179,  179,
232                 179,  180,  180,  180,  181,  181,  182,  182,
233                 182,  183,  183,  183,  184,  184,  184,  185,
234                 185,  185,  186,  186,  186,  187,  187,  187,
235                 188,  188,  188,  189,  189,  189,  189,  190,
236                 190,  190,  191,  191,  191,  192,  192,  192,
237                 193,  193,  193,  194,  194,  194,  195,  195,
238                 195,  196,  196,  196,  196,  197,  197,  197,
239                 198,  198,  198,  199,  199,  199,  200,  200,
240                 200,  200,  201,  201,  201,  202,  202,  202,
241                 202,  203,  203,  203,  204,  204,  204,  205,
242                 205,  205,  205,  206,  206,  206,  207,  207,
243                 207,  207,  208,  208,  208,  209,  209,  209,
244                 209,  210,  210,  210,  211,  211,  211,  211,
245                 212,  212,  212,  213,  213,  213,  213,  214,
246                 214,  214,  214,  215,  215,  215,  216,  216,
247                 216,  216,  217,  217,  217,  217,  218,  218,
248                 218,  219,  219,  219,  219,  220,  220,  220,
249                 220,  221,  221,  221,  221,  222,  222,  222,
250                 223,  223,  223,  223,  224,  224,  224,  224,
251                 225,  225,  225,  225,  226,  226,  226,  226,
252                 227,  227,  227,  227,  228,  228,  228,  228,
253                 229,  229,  229,  229,  230,  230,  230,  230,
254                 231,  231,  231,  231,  232,  232,  232,  232,
255                 233,  233,  233,  233,  234,  234,  234,  234,
256                 235,  235,  235,  235,  236,  236,  236,  236,
257                 237,  237,  237,  237,  238,  238,  238,  238,
258                 239,  239,  239,  239,  240,  240,  240,  240,
259                 240,  241,  241,  241,  241,  242,  242,  242,
260                 242,  243,  243,  243,  243,  244,  244,  244,
261                 244,  244,  245,  245,  245,  245,  246,  246,
262                 246,  246,  247,  247,  247,  247,  247,  248,
263                 248,  248,  248,  249,  249,  249,  249,  249,
264                 250,  250,  250,  250,  251,  251,  251,  251,
265                 251,  252,  252,  252,  252,  253,  253,  253,
266                 253,  253,  254,  254,  254,  254,  255,  255,
267         },
268 };
269 #endif
270
271 void tegra_dc_clk_enable(struct tegra_dc *dc)
272 {
273         if (!tegra_is_clk_enabled(dc->clk)) {
274                 clk_prepare_enable(dc->clk);
275                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
276         }
277 }
278
279 void tegra_dc_clk_disable(struct tegra_dc *dc)
280 {
281         if (tegra_is_clk_enabled(dc->clk)) {
282                 clk_disable_unprepare(dc->clk);
283                 tegra_dvfs_set_rate(dc->clk, 0);
284         }
285 }
286
287 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
288 {
289         if (dc->out_ops->hold)
290                 dc->out_ops->hold(dc);
291 }
292
293 void tegra_dc_release_dc_out(struct tegra_dc *dc)
294 {
295         if (dc->out_ops->release)
296                 dc->out_ops->release(dc);
297 }
298
299 #define DUMP_REG(a) do {                        \
300         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
301                  #a, a, tegra_dc_readl(dc, a));               \
302         print(data, buff);                                    \
303         } while (0)
304
305 static void _dump_regs(struct tegra_dc *dc, void *data,
306                        void (* print)(void *data, const char *str))
307 {
308         int i;
309         char buff[256];
310
311         mutex_lock(&dc->lock);
312         tegra_dc_io_start(dc);
313         tegra_dc_hold_dc_out(dc);
314
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
316         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE);
318         DUMP_REG(DC_CMD_INT_STATUS);
319         DUMP_REG(DC_CMD_INT_MASK);
320         DUMP_REG(DC_CMD_INT_ENABLE);
321         DUMP_REG(DC_CMD_INT_TYPE);
322         DUMP_REG(DC_CMD_INT_POLARITY);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
326         DUMP_REG(DC_CMD_STATE_ACCESS);
327         DUMP_REG(DC_CMD_STATE_CONTROL);
328         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
329         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
330
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
332         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
333         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
335         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
336         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
337         DUMP_REG(DC_DISP_REF_TO_SYNC);
338         DUMP_REG(DC_DISP_SYNC_WIDTH);
339         DUMP_REG(DC_DISP_BACK_PORCH);
340         DUMP_REG(DC_DISP_DISP_ACTIVE);
341         DUMP_REG(DC_DISP_FRONT_PORCH);
342         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
347         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
352         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
357         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
360         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
361         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
364         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
365         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
369         DUMP_REG(DC_DISP_M0_CONTROL);
370         DUMP_REG(DC_DISP_M1_CONTROL);
371         DUMP_REG(DC_DISP_DI_CONTROL);
372         DUMP_REG(DC_DISP_PP_CONTROL);
373         DUMP_REG(DC_DISP_PP_SELECT_A);
374         DUMP_REG(DC_DISP_PP_SELECT_B);
375         DUMP_REG(DC_DISP_PP_SELECT_C);
376         DUMP_REG(DC_DISP_PP_SELECT_D);
377         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
378         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
379         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
380         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
381         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
382         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
383         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
384         DUMP_REG(DC_DISP_BORDER_COLOR);
385         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
386         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
388         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
389         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
390         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
392         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
393         DUMP_REG(DC_DISP_CURSOR_POSITION);
394         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
395         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
400         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
404 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
406 #endif
407         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
408         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
409
410
411         for (i = 0; i < 3; i++) {
412                 print(data, "\n");
413                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
414                 print(data, buff);
415
416                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
417                                 DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
419                 DUMP_REG(DC_WIN_WIN_OPTIONS);
420                 DUMP_REG(DC_WIN_BYTE_SWAP);
421                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
422                 DUMP_REG(DC_WIN_COLOR_DEPTH);
423                 DUMP_REG(DC_WIN_POSITION);
424                 DUMP_REG(DC_WIN_SIZE);
425                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
426                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
428                 DUMP_REG(DC_WIN_DDA_INCREMENT);
429                 DUMP_REG(DC_WIN_LINE_STRIDE);
430 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
431                 DUMP_REG(DC_WIN_BUF_STRIDE);
432                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
433 #endif
434                 DUMP_REG(DC_WIN_BLEND_NOKEY);
435                 DUMP_REG(DC_WIN_BLEND_1WIN);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
437                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
438                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
439                 DUMP_REG(DC_WINBUF_START_ADDR);
440                 DUMP_REG(DC_WINBUF_START_ADDR_U);
441                 DUMP_REG(DC_WINBUF_START_ADDR_V);
442                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
443                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
444                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
445                 DUMP_REG(DC_WIN_CSC_YOF);
446                 DUMP_REG(DC_WIN_CSC_KYRGB);
447                 DUMP_REG(DC_WIN_CSC_KUR);
448                 DUMP_REG(DC_WIN_CSC_KVR);
449                 DUMP_REG(DC_WIN_CSC_KUG);
450                 DUMP_REG(DC_WIN_CSC_KVG);
451                 DUMP_REG(DC_WIN_CSC_KUB);
452                 DUMP_REG(DC_WIN_CSC_KVB);
453         }
454
455         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
456         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
458         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
459         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
461         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
462         DUMP_REG(DC_DISP_M1_CONTROL);
463         DUMP_REG(DC_COM_PM1_CONTROL);
464         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
465         DUMP_REG(DC_DISP_SD_CONTROL);
466 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
467         DUMP_REG(DC_COM_CMU_CSC_KRR);
468         DUMP_REG(DC_COM_CMU_CSC_KGR);
469         DUMP_REG(DC_COM_CMU_CSC_KBR);
470         DUMP_REG(DC_COM_CMU_CSC_KRG);
471         DUMP_REG(DC_COM_CMU_CSC_KGG);
472         DUMP_REG(DC_COM_CMU_CSC_KBR);
473         DUMP_REG(DC_COM_CMU_CSC_KRB);
474         DUMP_REG(DC_COM_CMU_CSC_KGB);
475         DUMP_REG(DC_COM_CMU_CSC_KBB);
476 #endif
477
478         tegra_dc_release_dc_out(dc);
479         tegra_dc_io_end(dc);
480         mutex_unlock(&dc->lock);
481 }
482
483 #undef DUMP_REG
484
485 #ifdef DEBUG
486 static void dump_regs_print(void *data, const char *str)
487 {
488         struct tegra_dc *dc = data;
489         dev_dbg(&dc->ndev->dev, "%s", str);
490 }
491
492 static void dump_regs(struct tegra_dc *dc)
493 {
494         _dump_regs(dc, dc, dump_regs_print);
495 }
496 #else /* !DEBUG */
497
498 static void dump_regs(struct tegra_dc *dc) {}
499
500 #endif /* DEBUG */
501
502 #ifdef CONFIG_DEBUG_FS
503
504 static void dbg_regs_print(void *data, const char *str)
505 {
506         struct seq_file *s = data;
507
508         seq_printf(s, "%s", str);
509 }
510
511 #undef DUMP_REG
512
513 static int dbg_dc_show(struct seq_file *s, void *unused)
514 {
515         struct tegra_dc *dc = s->private;
516
517         _dump_regs(dc, s, dbg_regs_print);
518
519         return 0;
520 }
521
522
523 static int dbg_dc_open(struct inode *inode, struct file *file)
524 {
525         return single_open(file, dbg_dc_show, inode->i_private);
526 }
527
528 static const struct file_operations regs_fops = {
529         .open           = dbg_dc_open,
530         .read           = seq_read,
531         .llseek         = seq_lseek,
532         .release        = single_release,
533 };
534
535 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
536 {
537         struct tegra_dc *dc = s->private;
538         struct tegra_dc_mode *m;
539
540         mutex_lock(&dc->lock);
541         m = &dc->mode;
542         seq_printf(s,
543                 "pclk: %d\n"
544                 "h_ref_to_sync: %d\n"
545                 "v_ref_to_sync: %d\n"
546                 "h_sync_width: %d\n"
547                 "v_sync_width: %d\n"
548                 "h_back_porch: %d\n"
549                 "v_back_porch: %d\n"
550                 "h_active: %d\n"
551                 "v_active: %d\n"
552                 "h_front_porch: %d\n"
553                 "v_front_porch: %d\n"
554                 "stereo_mode: %d\n",
555                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
556                 m->h_sync_width, m->v_sync_width,
557                 m->h_back_porch, m->v_back_porch,
558                 m->h_active, m->v_active,
559                 m->h_front_porch, m->v_front_porch,
560                 m->stereo_mode);
561         mutex_unlock(&dc->lock);
562         return 0;
563 }
564
565 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
566 {
567         return single_open(file, dbg_dc_mode_show, inode->i_private);
568 }
569
570 static const struct file_operations mode_fops = {
571         .open           = dbg_dc_mode_open,
572         .read           = seq_read,
573         .llseek         = seq_lseek,
574         .release        = single_release,
575 };
576
577 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
578 {
579         struct tegra_dc *dc = s->private;
580
581         mutex_lock(&dc->lock);
582         seq_printf(s,
583                 "underflows: %llu\n"
584                 "underflows_a: %llu\n"
585                 "underflows_b: %llu\n"
586                 "underflows_c: %llu\n",
587                 dc->stats.underflows,
588                 dc->stats.underflows_a,
589                 dc->stats.underflows_b,
590                 dc->stats.underflows_c);
591         mutex_unlock(&dc->lock);
592
593         return 0;
594 }
595
596 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
597 {
598         return single_open(file, dbg_dc_stats_show, inode->i_private);
599 }
600
601 static const struct file_operations stats_fops = {
602         .open           = dbg_dc_stats_open,
603         .read           = seq_read,
604         .llseek         = seq_lseek,
605         .release        = single_release,
606 };
607
608 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
609 {
610         if (dc->debugdir)
611                 debugfs_remove_recursive(dc->debugdir);
612         dc->debugdir = NULL;
613 }
614
615 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
616 {
617         struct dentry *retval;
618
619         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
620         if (!dc->debugdir)
621                 goto remove_out;
622
623         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
624                 &regs_fops);
625         if (!retval)
626                 goto remove_out;
627
628         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
629                 &mode_fops);
630         if (!retval)
631                 goto remove_out;
632
633         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
634                 &stats_fops);
635         if (!retval)
636                 goto remove_out;
637
638         return;
639 remove_out:
640         dev_err(&dc->ndev->dev, "could not create debugfs\n");
641         tegra_dc_remove_debugfs(dc);
642 }
643
644 #else /* !CONFIG_DEBUGFS */
645 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
646 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
647 #endif /* CONFIG_DEBUGFS */
648
649 static int tegra_dc_set(struct tegra_dc *dc, int index)
650 {
651         int ret = 0;
652
653         mutex_lock(&tegra_dc_lock);
654         if (index >= TEGRA_MAX_DC) {
655                 ret = -EINVAL;
656                 goto out;
657         }
658
659         if (dc != NULL && tegra_dcs[index] != NULL) {
660                 ret = -EBUSY;
661                 goto out;
662         }
663
664         tegra_dcs[index] = dc;
665
666 out:
667         mutex_unlock(&tegra_dc_lock);
668
669         return ret;
670 }
671
672 unsigned int tegra_dc_has_multiple_dc(void)
673 {
674         unsigned int idx;
675         unsigned int cnt = 0;
676         struct tegra_dc *dc;
677
678         mutex_lock(&tegra_dc_lock);
679         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
680                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
681         mutex_unlock(&tegra_dc_lock);
682
683         return (cnt > 1);
684 }
685
686 /* get the stride size of a window.
687  * return: stride size in bytes for window win. or 0 if unavailble. */
688 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
689 {
690         u32 stride;
691
692         if (!dc->enabled)
693                 return 0;
694         BUG_ON(win > DC_N_WINDOWS);
695         mutex_lock(&dc->lock);
696         tegra_dc_io_start(dc);
697         tegra_dc_hold_dc_out(dc);
698         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
699                 DC_CMD_DISPLAY_WINDOW_HEADER);
700         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
701         tegra_dc_release_dc_out(dc);
702         tegra_dc_io_end(dc);
703         mutex_unlock(&dc->lock);
704         return GET_LINE_STRIDE(stride);
705 }
706 EXPORT_SYMBOL(tegra_dc_get_stride);
707
708 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
709 {
710         if (idx < TEGRA_MAX_DC)
711                 return tegra_dcs[idx];
712         else
713                 return NULL;
714 }
715 EXPORT_SYMBOL(tegra_dc_get_dc);
716
717 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
718 {
719         if (win >= dc->n_windows)
720                 return NULL;
721
722         return &dc->windows[win];
723 }
724 EXPORT_SYMBOL(tegra_dc_get_window);
725
726 bool tegra_dc_get_connected(struct tegra_dc *dc)
727 {
728         return dc->connected;
729 }
730 EXPORT_SYMBOL(tegra_dc_get_connected);
731
732 bool tegra_dc_hpd(struct tegra_dc *dc)
733 {
734         int sense;
735         int level;
736
737         level = gpio_get_value(dc->out->hotplug_gpio);
738
739         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
740
741         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
742                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
743 }
744 EXPORT_SYMBOL(tegra_dc_hpd);
745
746 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
747 {
748         unsigned i;
749         unsigned v0 = 128;
750         unsigned v1 = 0;
751
752         /* linear horizontal and vertical filters */
753         for (i = 0; i < 16; i++) {
754                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
755                                 DC_WIN_H_FILTER_P(i));
756
757                 tegra_dc_writel(dc, v0,
758                                 DC_WIN_V_FILTER_P(i));
759                 v0 -= 8;
760                 v1 += 8;
761         }
762 }
763
764 #ifdef CONFIG_TEGRA_DC_CMU
765 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
766                                         struct tegra_dc_cmu *src_cmu)
767 {
768         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
769 }
770
771 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
772 {
773         u32 val;
774         u32 i;
775
776         for (i = 0; i < 256; i++) {
777                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
778                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
779         }
780
781         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
782         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
783         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
784         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
785         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
786         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
787         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
788         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
789         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
790
791         for (i = 0; i < 960; i++) {
792                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
793                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
794         }
795 }
796
797 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
798 {
799         u32 val;
800         u32 i;
801         bool flags;
802
803         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
804         if (val & CMU_ENABLE)
805                 flags = true;
806
807         val &= ~CMU_ENABLE;
808         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
809         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
810         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
811
812         /*TODO: Sync up with frame end */
813         mdelay(20);
814
815         for (i = 0; i < 256; i++) {
816                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
817                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
818                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
819                 cmu->lut1[i] = LUT1_READ_DATA(val);
820         }
821
822         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
823         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
824         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
825         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
826         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
827         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
828         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
829         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
830         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
831
832         for (i = 0; i < 960; i++) {
833                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
834                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
835                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
836                 cmu->lut2[i] = LUT2_READ_DATA(val);
837         }
838 }
839 EXPORT_SYMBOL(tegra_dc_get_cmu);
840
841 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
842 {
843         u32 val;
844
845         if (dc->pdata->cmu_enable) {
846                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
847         } else {
848                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
849                 return 0;
850         }
851
852         if (cmu != &dc->cmu) {
853                 tegra_dc_cache_cmu(&dc->cmu, cmu);
854
855                 /* Disable CMU */
856                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
857                 if (val & CMU_ENABLE) {
858                         val &= ~CMU_ENABLE;
859                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
860                         val = GENERAL_UPDATE;
861                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
862                         val = GENERAL_ACT_REQ;
863                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
864                         /*TODO: Sync up with vsync */
865                         mdelay(20);
866                 }
867
868                 tegra_dc_set_cmu(dc, &dc->cmu);
869         }
870         tegra_dc_set_color_control(dc);
871
872         return 0;
873 }
874
875 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
876 {
877         int ret;
878
879         mutex_lock(&dc->lock);
880         tegra_dc_io_start(dc);
881         tegra_dc_hold_dc_out(dc);
882
883         ret = _tegra_dc_update_cmu(dc, cmu);
884
885         tegra_dc_release_dc_out(dc);
886         tegra_dc_io_end(dc);
887         mutex_unlock(&dc->lock);
888
889         return ret;
890 }
891 EXPORT_SYMBOL(tegra_dc_update_cmu);
892
893 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
894 {
895         tegra_dc_update_cmu(dc, &dc->cmu);
896 }
897 #else
898 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
899 #define tegra_dc_set_cmu(dc, cmu)
900 #define tegra_dc_update_cmu(dc, cmu)
901 #endif
902
903 /* disable_irq() blocks until handler completes, calling this function while
904  * holding dc->lock can deadlock. */
905 static inline void disable_dc_irq(const struct tegra_dc *dc)
906 {
907         disable_irq(dc->irq);
908 }
909
910 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
911 {
912         return dc->syncpt[i].id;
913 }
914 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
915
916 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
917 {
918         u32 max;
919
920         mutex_lock(&dc->lock);
921         tegra_dc_io_start(dc);
922         tegra_dc_hold_dc_out(dc);
923         max = nvhost_syncpt_incr_max_ext(dc->ndev,
924                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
925         dc->syncpt[i].max = max;
926         tegra_dc_release_dc_out(dc);
927         tegra_dc_io_end(dc);
928         mutex_unlock(&dc->lock);
929
930         return max;
931 }
932
933 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
934 {
935         mutex_lock(&dc->lock);
936         if (dc->enabled) {
937                 tegra_dc_io_start(dc);
938                 tegra_dc_hold_dc_out(dc);
939                 while (dc->syncpt[i].min < val) {
940                         dc->syncpt[i].min++;
941                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
942                 }
943                 tegra_dc_release_dc_out(dc);
944                 tegra_dc_io_end(dc);
945         }
946         mutex_unlock(&dc->lock);
947 }
948
949 void
950 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
951 {
952         unsigned int ctrl;
953         unsigned long out_sel;
954         unsigned long cmd_state;
955
956         mutex_lock(&dc->lock);
957         if (!dc->enabled) {
958                 mutex_unlock(&dc->lock);
959                 return;
960         }
961
962         tegra_dc_io_start(dc);
963         tegra_dc_hold_dc_out(dc);
964
965         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
966                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
967                 cfg->clk_select);
968
969         /* The new value should be effected immediately */
970         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
971         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
972
973         switch (cfg->which_pwm) {
974         case TEGRA_PWM_PM0:
975                 /* Select the LM0 on PM0 */
976                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
977                 out_sel &= ~(7 << 0);
978                 out_sel |= (3 << 0);
979                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
980                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
981                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
982                 break;
983         case TEGRA_PWM_PM1:
984                 /* Select the LM1 on PM1 */
985                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
986                 out_sel &= ~(7 << 4);
987                 out_sel |= (3 << 4);
988                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
989                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
990                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
991                 break;
992         default:
993                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
994                 break;
995         }
996         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
997         tegra_dc_release_dc_out(dc);
998         tegra_dc_io_end(dc);
999         mutex_unlock(&dc->lock);
1000 }
1001 EXPORT_SYMBOL(tegra_dc_config_pwm);
1002
1003 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1004                                 const struct tegra_dc_out_pin *pins,
1005                                 const unsigned int n_pins)
1006 {
1007         unsigned int i;
1008
1009         int name;
1010         int pol;
1011
1012         u32 pol1, pol3;
1013
1014         u32 set1, unset1;
1015         u32 set3, unset3;
1016
1017         set1 = set3 = unset1 = unset3 = 0;
1018
1019         for (i = 0; i < n_pins; i++) {
1020                 name = (pins + i)->name;
1021                 pol  = (pins + i)->pol;
1022
1023                 /* set polarity by name */
1024                 switch (name) {
1025                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1026                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1027                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1028                         else
1029                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1030                         break;
1031                 case TEGRA_DC_OUT_PIN_H_SYNC:
1032                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1033                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1034                         else
1035                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1036                         break;
1037                 case TEGRA_DC_OUT_PIN_V_SYNC:
1038                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1039                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1040                         else
1041                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1042                         break;
1043                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1044                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1045                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1046                         else
1047                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1048                         break;
1049                 default:
1050                         printk("Invalid argument in function %s\n",
1051                                __FUNCTION__);
1052                         break;
1053                 }
1054         }
1055
1056         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1057         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1058
1059         pol1 |= set1;
1060         pol1 &= ~unset1;
1061
1062         pol3 |= set3;
1063         pol3 &= ~unset3;
1064
1065         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1066         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1067 }
1068
1069 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1070 {
1071         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1072                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1073                 dc->out->type == TEGRA_DC_OUT_DSI)
1074                 return override_disp_mode[dc->out->type].pclk ?
1075                         &override_disp_mode[dc->out->type] : NULL;
1076         else
1077                 return NULL;
1078 }
1079
1080 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1081 {
1082         struct tegra_dc_mode *mode;
1083
1084         dc->out = out;
1085         mode = tegra_dc_get_override_mode(dc);
1086
1087         if (mode)
1088                 tegra_dc_set_mode(dc, mode);
1089         else if (out->n_modes > 0)
1090                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1091
1092         switch (out->type) {
1093         case TEGRA_DC_OUT_RGB:
1094                 dc->out_ops = &tegra_dc_rgb_ops;
1095                 break;
1096
1097         case TEGRA_DC_OUT_HDMI:
1098                 dc->out_ops = &tegra_dc_hdmi_ops;
1099                 break;
1100
1101         case TEGRA_DC_OUT_DSI:
1102                 dc->out_ops = &tegra_dc_dsi_ops;
1103                 break;
1104
1105         default:
1106                 dc->out_ops = NULL;
1107                 break;
1108         }
1109
1110 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1111         if (out->type == TEGRA_DC_OUT_HDMI)
1112                 dc->powergate_id = TEGRA_POWERGATE_DISB;
1113         else
1114                 dc->powergate_id = TEGRA_POWERGATE_DISA;
1115 #endif
1116
1117         if (dc->out_ops && dc->out_ops->init)
1118                 dc->out_ops->init(dc);
1119 }
1120
1121 /* returns on error: -EINVAL
1122  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1123 int tegra_dc_get_out(const struct tegra_dc *dc)
1124 {
1125         if (dc && dc->out)
1126                 return dc->out->type;
1127         return -EINVAL;
1128 }
1129
1130 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1131 {
1132         if (dc->out)
1133                 return dc->out->height;
1134         else
1135                 return 0;
1136 }
1137 EXPORT_SYMBOL(tegra_dc_get_out_height);
1138
1139 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1140 {
1141         if (dc->out)
1142                 return dc->out->width;
1143         else
1144                 return 0;
1145 }
1146 EXPORT_SYMBOL(tegra_dc_get_out_width);
1147
1148 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1149 {
1150         if (dc->out && dc->out->max_pixclock)
1151                 return dc->out->max_pixclock;
1152         else
1153                 return 0;
1154 }
1155 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1156
1157 void tegra_dc_enable_crc(struct tegra_dc *dc)
1158 {
1159         u32 val;
1160
1161         mutex_lock(&dc->lock);
1162         tegra_dc_io_start(dc);
1163         tegra_dc_hold_dc_out(dc);
1164
1165         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1166                 CRC_ENABLE_ENABLE;
1167         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1168         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1169         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1170         tegra_dc_release_dc_out(dc);
1171         tegra_dc_io_end(dc);
1172         mutex_unlock(&dc->lock);
1173 }
1174
1175 void tegra_dc_disable_crc(struct tegra_dc *dc)
1176 {
1177         mutex_lock(&dc->lock);
1178         tegra_dc_io_start(dc);
1179         tegra_dc_hold_dc_out(dc);
1180         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1181         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1182         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1183
1184         tegra_dc_release_dc_out(dc);
1185         tegra_dc_io_end(dc);
1186         mutex_unlock(&dc->lock);
1187 }
1188
1189 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1190 {
1191         int crc = 0;
1192
1193         if (!dc) {
1194                 pr_err("Failed to get dc: NULL parameter.\n");
1195                 goto crc_error;
1196         }
1197
1198 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1199         /* TODO: Replace mdelay with code to sync VBlANK, since
1200          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1201         mdelay(TEGRA_CRC_LATCHED_DELAY);
1202 #endif
1203
1204         mutex_lock(&dc->lock);
1205         tegra_dc_io_start(dc);
1206         tegra_dc_hold_dc_out(dc);
1207         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1208         tegra_dc_release_dc_out(dc);
1209         tegra_dc_io_end(dc);
1210         mutex_unlock(&dc->lock);
1211 crc_error:
1212         return crc;
1213 }
1214
1215 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1216 {
1217 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1218         u32 val;
1219
1220         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1221         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1222             return true;
1223 #endif
1224         return false;
1225 }
1226
1227 static inline void enable_dc_irq(const struct tegra_dc *dc)
1228 {
1229 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1230         enable_irq(dc->irq);
1231 #else
1232         /* Always disable DC interrupts on FPGA. */
1233         disable_irq(dc->irq);
1234 #endif
1235 }
1236
1237 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1238 {
1239         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1240                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1241 }
1242
1243 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1244 {
1245         int ret = -ENOTTY;
1246
1247         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1248                 return ret;
1249
1250         /*
1251          * Logic is as follows
1252          * a) Indicate we need a vblank.
1253          * b) Wait for completion to be signalled from isr.
1254          * c) Initialize completion for next iteration.
1255          */
1256
1257         tegra_dc_hold_dc_out(dc);
1258         dc->out->user_needs_vblank = true;
1259
1260         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1261         init_completion(&dc->out->user_vblank_comp);
1262         tegra_dc_release_dc_out(dc);
1263
1264         return ret;
1265 }
1266
1267 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1268 {
1269         /* Do the actual brightness update outside of the mutex dc->lock */
1270         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1271                 dc->out->sd_settings->bl_device_name) {
1272                 char *bl_device_name =
1273                         dc->out->sd_settings->bl_device_name;
1274                 dc->out->sd_settings->bl_device =
1275                         get_backlight_device_by_name(bl_device_name);
1276         }
1277
1278         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1279                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1280                 backlight_update_status(bl);
1281         }
1282 }
1283
1284 static void tegra_dc_vblank(struct work_struct *work)
1285 {
1286         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1287         bool nvsd_updated = false;
1288
1289         mutex_lock(&dc->lock);
1290
1291         if (!dc->enabled) {
1292                 mutex_unlock(&dc->lock);
1293                 return;
1294         }
1295
1296         tegra_dc_io_start(dc);
1297         tegra_dc_hold_dc_out(dc);
1298         /* use the new frame's bandwidth setting instead of max(current, new),
1299          * skip this if we're using tegra_dc_one_shot_worker() */
1300         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1301                 tegra_dc_program_bandwidth(dc, true);
1302
1303         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1304         if (!tegra_dc_windows_are_dirty(dc))
1305                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1306
1307         /* Update the SD brightness */
1308         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1309                 nvsd_updated = nvsd_update_brightness(dc);
1310                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1311                  * V_BLANK_NVSD bit of vblank ref-count. */
1312                 if (nvsd_updated) {
1313                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1314                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1315                 } else {
1316                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1317                 }
1318         }
1319
1320         /* Mask vblank interrupt if ref-count is zero. */
1321         if (!dc->vblank_ref_count)
1322                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1323
1324         tegra_dc_release_dc_out(dc);
1325         tegra_dc_io_end(dc);
1326         mutex_unlock(&dc->lock);
1327
1328         /* Do the actual brightness update outside of the mutex dc->lock */
1329         if (nvsd_updated)
1330                 tegra_dc_prism_update_backlight(dc);
1331 }
1332
1333 static void tegra_dc_one_shot_worker(struct work_struct *work)
1334 {
1335         struct tegra_dc *dc = container_of(
1336                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1337         mutex_lock(&dc->lock);
1338
1339         /* memory client has gone idle */
1340         tegra_dc_clear_bandwidth(dc);
1341
1342         if (dc->out_ops->idle) {
1343                 tegra_dc_io_start(dc);
1344                 dc->out_ops->idle(dc);
1345                 tegra_dc_io_end(dc);
1346         }
1347
1348         mutex_unlock(&dc->lock);
1349 }
1350
1351 /* return an arbitrarily large number if count overflow occurs.
1352  * make it a nice base-10 number to show up in stats output */
1353 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1354 {
1355         unsigned count = tegra_dc_readl(dc, reg);
1356
1357         tegra_dc_writel(dc, 0, reg);
1358         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1359 }
1360
1361 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1362 {
1363         int i;
1364
1365         dc->stats.underflows++;
1366         if (dc->underflow_mask & WIN_A_UF_INT)
1367                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1368                         DC_WINBUF_AD_UFLOW_STATUS);
1369         if (dc->underflow_mask & WIN_B_UF_INT)
1370                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1371                         DC_WINBUF_BD_UFLOW_STATUS);
1372         if (dc->underflow_mask & WIN_C_UF_INT)
1373                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1374                         DC_WINBUF_CD_UFLOW_STATUS);
1375
1376         /* Check for any underflow reset conditions */
1377         for (i = 0; i < DC_N_WINDOWS; i++) {
1378                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1379                         dc->windows[i].underflows++;
1380
1381 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1382                         if (dc->windows[i].underflows > 4) {
1383                                 schedule_work(&dc->reset_work);
1384                                 /* reset counter */
1385                                 dc->windows[i].underflows = 0;
1386                                 trace_display_reset(dc);
1387                         }
1388 #endif
1389 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1390                         if (dc->windows[i].underflows > 4) {
1391                                 trace_display_reset(dc);
1392                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1393                                                 DC_DISP_DISP_MISC_CONTROL);
1394                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1395                                                 DC_CMD_STATE_CONTROL);
1396                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1397                                                 DC_CMD_STATE_CONTROL);
1398
1399                                 tegra_dc_writel(dc, 0,
1400                                                 DC_DISP_DISP_MISC_CONTROL);
1401                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1402                                                 DC_CMD_STATE_CONTROL);
1403                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1404                                                 DC_CMD_STATE_CONTROL);
1405                         }
1406 #endif
1407                 } else {
1408                         dc->windows[i].underflows = 0;
1409                 }
1410         }
1411
1412         /* Clear the underflow mask now that we've checked it. */
1413         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1414         dc->underflow_mask = 0;
1415         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1416         trace_underflow(dc);
1417 }
1418
1419 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1420 static void tegra_dc_vpulse2(struct work_struct *work)
1421 {
1422         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1423         bool nvsd_updated = false;
1424
1425         mutex_lock(&dc->lock);
1426
1427         if (!dc->enabled) {
1428                 mutex_unlock(&dc->lock);
1429                 return;
1430         }
1431
1432         tegra_dc_io_start(dc);
1433         tegra_dc_hold_dc_out(dc);
1434
1435         /* Clear the V_PULSE2_FLIP if no update */
1436         if (!tegra_dc_windows_are_dirty(dc))
1437                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1438
1439         /* Update the SD brightness */
1440         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1441                 nvsd_updated = nvsd_update_brightness(dc);
1442                 if (nvsd_updated) {
1443                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1444                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1445                 } else {
1446                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1447                 }
1448         }
1449
1450         /* Mask vpulse2 interrupt if ref-count is zero. */
1451         if (!dc->vpulse2_ref_count)
1452                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1453
1454         tegra_dc_release_dc_out(dc);
1455         tegra_dc_io_end(dc);
1456         mutex_unlock(&dc->lock);
1457
1458         /* Do the actual brightness update outside of the mutex dc->lock */
1459         if (nvsd_updated)
1460                 tegra_dc_prism_update_backlight(dc);
1461 }
1462 #endif
1463
1464 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1465 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1466 {
1467         /* pending user vblank, so wakeup */
1468         if ((status & (V_BLANK_INT | MSF_INT)) &&
1469             (dc->out->user_needs_vblank)) {
1470                 dc->out->user_needs_vblank = false;
1471                 complete(&dc->out->user_vblank_comp);
1472         }
1473
1474         if (status & V_BLANK_INT) {
1475                 /* Sync up windows. */
1476                 tegra_dc_trigger_windows(dc);
1477
1478                 /* Schedule any additional bottom-half vblank actvities. */
1479                 queue_work(system_freezable_wq, &dc->vblank_work);
1480         }
1481
1482         if (status & FRAME_END_INT) {
1483                 /* Mark the frame_end as complete. */
1484                 if (!completion_done(&dc->frame_end_complete))
1485                         complete(&dc->frame_end_complete);
1486         }
1487
1488 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1489         if (status & V_PULSE2_INT)
1490                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1491 #endif
1492 }
1493
1494 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1495 {
1496         /* Schedule any additional bottom-half vblank actvities. */
1497         if (status & V_BLANK_INT)
1498                 queue_work(system_freezable_wq, &dc->vblank_work);
1499
1500         if (status & FRAME_END_INT) {
1501                 struct timespec tm = CURRENT_TIME;
1502                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1503                 wake_up(&dc->timestamp_wq);
1504
1505                 /* Mark the frame_end as complete. */
1506                 if (!completion_done(&dc->frame_end_complete))
1507                         complete(&dc->frame_end_complete);
1508
1509                 tegra_dc_trigger_windows(dc);
1510         }
1511
1512 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1513         if (status & V_PULSE2_INT)
1514                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1515 #endif
1516 }
1517
1518 /* XXX: Not sure if we limit look ahead to 1 frame */
1519 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1520 {
1521         BUG_ON(!dc->frametime_ns);
1522         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1523 }
1524
1525 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1526 {
1527         BUG_ON(!dc->frametime_ns);
1528         return (((new_ts - old_ts) > dc->frametime_ns)
1529                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1530                         != div_s64((old_ts - dc->frame_end_timestamp),
1531                                 dc->frametime_ns)));
1532 }
1533 #endif
1534
1535 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1536 {
1537 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1538         struct tegra_dc *dc = ptr;
1539         unsigned long status;
1540         unsigned long underflow_mask;
1541         u32 val;
1542
1543         mutex_lock(&dc->lock);
1544         if (!dc->enabled) {
1545                 mutex_unlock(&dc->lock);
1546                 return IRQ_HANDLED;
1547         }
1548
1549         clk_enable(dc->clk);
1550         tegra_dc_io_start(dc);
1551         tegra_dc_hold_dc_out(dc);
1552
1553         if (!nvhost_module_powered_ext(dc->ndev)) {
1554                 WARN(1, "IRQ when DC not powered!\n");
1555                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1556                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1557                 tegra_dc_release_dc_out(dc);
1558                 tegra_dc_io_end(dc);
1559                 clk_disable(dc->clk);
1560                 mutex_unlock(&dc->lock);
1561                 return IRQ_HANDLED;
1562         }
1563
1564         /* clear all status flags except underflow, save those for the worker */
1565         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1566         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1567         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1568         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1569
1570         /*
1571          * Overlays can get thier internal state corrupted during and underflow
1572          * condition.  The only way to fix this state is to reset the DC.
1573          * if we get 4 consecutive frames with underflows, assume we're
1574          * hosed and reset.
1575          */
1576         underflow_mask = status & ALL_UF_INT;
1577
1578         /* Check underflow */
1579         if (underflow_mask) {
1580                 dc->underflow_mask |= underflow_mask;
1581                 schedule_delayed_work(&dc->underflow_work,
1582                         msecs_to_jiffies(1));
1583         }
1584
1585         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1586                 tegra_dc_one_shot_irq(dc, status);
1587         else
1588                 tegra_dc_continuous_irq(dc, status);
1589
1590         /* update video mode if it has changed since the last frame */
1591         if (status & (FRAME_END_INT | V_BLANK_INT))
1592                 tegra_dc_update_mode(dc);
1593
1594         tegra_dc_release_dc_out(dc);
1595         tegra_dc_io_end(dc);
1596         clk_disable(dc->clk);
1597         mutex_unlock(&dc->lock);
1598
1599         return IRQ_HANDLED;
1600 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1601         return IRQ_NONE;
1602 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1603 }
1604
1605 void tegra_dc_set_color_control(struct tegra_dc *dc)
1606 {
1607         u32 color_control;
1608
1609         switch (dc->out->depth) {
1610         case 3:
1611                 color_control = BASE_COLOR_SIZE111;
1612                 break;
1613
1614         case 6:
1615                 color_control = BASE_COLOR_SIZE222;
1616                 break;
1617
1618         case 8:
1619                 color_control = BASE_COLOR_SIZE332;
1620                 break;
1621
1622         case 9:
1623                 color_control = BASE_COLOR_SIZE333;
1624                 break;
1625
1626         case 12:
1627                 color_control = BASE_COLOR_SIZE444;
1628                 break;
1629
1630         case 15:
1631                 color_control = BASE_COLOR_SIZE555;
1632                 break;
1633
1634         case 16:
1635                 color_control = BASE_COLOR_SIZE565;
1636                 break;
1637
1638         case 18:
1639                 color_control = BASE_COLOR_SIZE666;
1640                 break;
1641
1642         default:
1643                 color_control = BASE_COLOR_SIZE888;
1644                 break;
1645         }
1646
1647         switch (dc->out->dither) {
1648         case TEGRA_DC_DISABLE_DITHER:
1649                 color_control |= DITHER_CONTROL_DISABLE;
1650                 break;
1651         case TEGRA_DC_ORDERED_DITHER:
1652                 color_control |= DITHER_CONTROL_ORDERED;
1653                 break;
1654         case TEGRA_DC_ERRDIFF_DITHER:
1655                 /* The line buffer for error-diffusion dither is limited
1656                  * to 1280 pixels per line. This limits the maximum
1657                  * horizontal active area size to 1280 pixels when error
1658                  * diffusion is enabled.
1659                  */
1660                 BUG_ON(dc->mode.h_active > 1280);
1661                 color_control |= DITHER_CONTROL_ERRDIFF;
1662                 break;
1663         }
1664
1665 #ifdef CONFIG_TEGRA_DC_CMU
1666         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1667                 color_control |= CMU_ENABLE;
1668 #endif
1669
1670         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1671 }
1672
1673 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1674 {
1675         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1676                 return dc->win_syncpt[idx];
1677         BUG();
1678 }
1679
1680 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1681 {
1682 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1683         u32 start, end;
1684         unsigned long val;
1685
1686         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1687         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1688
1689         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1690                 dc->mode.v_back_porch + dc->mode.v_active;
1691         end = start + 1;
1692         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1693         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1694
1695         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1696         val |= V_PULSE2_INT;
1697         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1698
1699         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1700         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1701 #endif
1702 }
1703
1704 static int tegra_dc_init(struct tegra_dc *dc)
1705 {
1706         int i;
1707         int int_enable;
1708
1709         tegra_dc_io_start(dc);
1710         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1711         if (dc->ndev->id == 0) {
1712                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1713                                       TEGRA_MC_PRIO_MED);
1714                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1715                                       TEGRA_MC_PRIO_MED);
1716                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1717                                       TEGRA_MC_PRIO_MED);
1718 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1719                 /* only present on Tegra2 and 3 */
1720                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1721                                       TEGRA_MC_PRIO_MED);
1722 #endif
1723                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1724                                       TEGRA_MC_PRIO_HIGH);
1725         } else if (dc->ndev->id == 1) {
1726                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1727                                       TEGRA_MC_PRIO_MED);
1728                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1729                                       TEGRA_MC_PRIO_MED);
1730                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1731                                       TEGRA_MC_PRIO_MED);
1732 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1733                 /* only present on Tegra2 and 3 */
1734                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1735                                       TEGRA_MC_PRIO_MED);
1736 #endif
1737                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1738                                       TEGRA_MC_PRIO_HIGH);
1739         }
1740         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1741                         DC_CMD_CONT_SYNCPT_VSYNC);
1742
1743         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1744         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1745         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1746         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1747 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1748         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1749 #endif
1750         /* enable interrupts for vblank, frame_end and underflows */
1751         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1752         /* for panels with one-shot mode enable tearing effect interrupt */
1753         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1754                 int_enable |= MSF_INT;
1755
1756         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1757         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1758         tegra_dc_init_vpulse2_int(dc);
1759
1760         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1761
1762 #ifdef CONFIG_TEGRA_DC_CMU
1763         if (dc->pdata->cmu)
1764                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1765         else
1766                 _tegra_dc_update_cmu(dc, &default_cmu);
1767 #endif
1768         tegra_dc_set_color_control(dc);
1769         for (i = 0; i < DC_N_WINDOWS; i++) {
1770                 struct tegra_dc_win *win = &dc->windows[i];
1771                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1772                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1773                 tegra_dc_set_csc(dc, &win->csc);
1774                 tegra_dc_set_lut(dc, win);
1775                 tegra_dc_set_scaling_filter(dc);
1776         }
1777
1778         for (i = 0; i < dc->n_windows; i++) {
1779                 u32 syncpt = get_syncpt(dc, i);
1780
1781                 dc->syncpt[i].id = syncpt;
1782
1783                 dc->syncpt[i].min = dc->syncpt[i].max =
1784                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1785         }
1786
1787         trace_display_mode(dc, &dc->mode);
1788
1789         if (dc->mode.pclk) {
1790                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1791                         tegra_dc_io_end(dc);
1792                         return -EINVAL;
1793                 }
1794         }
1795
1796         /* Initialize SD AFTER the modeset.
1797            nvsd_init handles the sd_settings = NULL case. */
1798         nvsd_init(dc, dc->out->sd_settings);
1799
1800         tegra_dc_io_end(dc);
1801
1802         return 0;
1803 }
1804
1805 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1806 {
1807         int failed_init = 0;
1808
1809         tegra_dc_unpowergate_locked(dc);
1810
1811         if (dc->out->enable)
1812                 dc->out->enable(&dc->ndev->dev);
1813
1814         tegra_dc_setup_clk(dc, dc->clk);
1815         tegra_dc_clk_enable(dc);
1816         tegra_dc_io_start(dc);
1817
1818         tegra_dc_power_on(dc);
1819
1820         /* do not accept interrupts during initialization */
1821         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1822
1823         enable_dc_irq(dc);
1824
1825         failed_init = tegra_dc_init(dc);
1826         if (failed_init) {
1827                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1828                 disable_irq_nosync(dc->irq);
1829                 tegra_dc_clear_bandwidth(dc);
1830                 tegra_dc_clk_disable(dc);
1831                 if (dc->out && dc->out->disable)
1832                         dc->out->disable();
1833                 tegra_dc_io_end(dc);
1834                 return false;
1835         }
1836
1837         if (dc->out_ops && dc->out_ops->enable)
1838                 dc->out_ops->enable(dc);
1839
1840         /* force a full blending update */
1841         dc->blend.z[0] = -1;
1842
1843         tegra_dc_ext_enable(dc->ext);
1844
1845         trace_display_enable(dc);
1846
1847         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1848         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1849
1850         if (dc->out->postpoweron)
1851                 dc->out->postpoweron();
1852
1853         tegra_dc_io_end(dc);
1854         return true;
1855 }
1856
1857 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1858 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1859 {
1860         bool ret = true;
1861
1862         if (dc->out->enable)
1863                 dc->out->enable(&dc->ndev->dev);
1864
1865         tegra_dc_setup_clk(dc, dc->clk);
1866         tegra_dc_clk_enable(dc);
1867
1868         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1869                 mutex_lock(&tegra_dcs[1]->lock);
1870                 disable_irq_nosync(tegra_dcs[1]->irq);
1871         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1872                 mutex_lock(&tegra_dcs[0]->lock);
1873                 disable_irq_nosync(tegra_dcs[0]->irq);
1874         }
1875
1876         msleep(5);
1877         tegra_periph_reset_assert(dc->clk);
1878         msleep(2);
1879 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1880         tegra_periph_reset_deassert(dc->clk);
1881         msleep(1);
1882 #endif
1883
1884         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1885                 enable_dc_irq(tegra_dcs[1]);
1886                 mutex_unlock(&tegra_dcs[1]->lock);
1887         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1888                 enable_dc_irq(tegra_dcs[0]);
1889                 mutex_unlock(&tegra_dcs[0]->lock);
1890         }
1891
1892         enable_dc_irq(dc);
1893
1894         if (tegra_dc_init(dc)) {
1895                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1896                 ret = false;
1897         }
1898
1899         if (dc->out_ops && dc->out_ops->enable)
1900                 dc->out_ops->enable(dc);
1901
1902         if (dc->out->postpoweron)
1903                 dc->out->postpoweron();
1904
1905         /* force a full blending update */
1906         dc->blend.z[0] = -1;
1907
1908         tegra_dc_ext_enable(dc->ext);
1909
1910         if (!ret) {
1911                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1912                 _tegra_dc_controller_disable(dc);
1913         }
1914
1915         trace_display_reset(dc);
1916         return ret;
1917 }
1918 #endif
1919
1920 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1921 {
1922         if (dc->mode.pclk == 0) {
1923                 switch (dc->out->type) {
1924                 case TEGRA_DC_OUT_HDMI:
1925                 /* DC enable called but no videomode is loaded.
1926                      Check if HDMI is connected, then set fallback mdoe */
1927                 if (tegra_dc_hpd(dc)) {
1928                         return tegra_dc_set_fb_mode(dc,
1929                                         &tegra_dc_hdmi_fallback_mode, 0);
1930                 } else
1931                         return false;
1932
1933                 break;
1934
1935                 /* Do nothing for other outputs for now */
1936                 case TEGRA_DC_OUT_RGB:
1937
1938                 case TEGRA_DC_OUT_DSI:
1939
1940                 default:
1941                         return false;
1942                 }
1943         }
1944
1945         return false;
1946 }
1947
1948 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1949 {
1950         return _tegra_dc_set_default_videomode(dc);
1951 }
1952
1953 static bool _tegra_dc_enable(struct tegra_dc *dc)
1954 {
1955         if (dc->mode.pclk == 0)
1956                 return false;
1957
1958         if (!dc->out)
1959                 return false;
1960
1961         if (dc->enabled)
1962                 return true;
1963
1964         if (!_tegra_dc_controller_enable(dc))
1965                 return false;
1966
1967         return true;
1968 }
1969
1970 void tegra_dc_enable(struct tegra_dc *dc)
1971 {
1972         mutex_lock(&dc->lock);
1973
1974         if (!dc->enabled)
1975                 dc->enabled = _tegra_dc_enable(dc);
1976
1977         mutex_unlock(&dc->lock);
1978         trace_display_mode(dc, &dc->mode);
1979 }
1980
1981 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1982 {
1983         unsigned i;
1984
1985         tegra_dc_hold_dc_out(dc);
1986
1987         if (dc->out && dc->out->prepoweroff)
1988                 dc->out->prepoweroff();
1989
1990         if (dc->out_ops && dc->out_ops->disable)
1991                 dc->out_ops->disable(dc);
1992
1993         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1994
1995         disable_irq_nosync(dc->irq);
1996
1997         tegra_dc_clear_bandwidth(dc);
1998         if (dc->out_ops->release) /* ugly hack */
1999                 tegra_dc_release_dc_out(dc);
2000         else
2001                 tegra_dc_clk_disable(dc);
2002
2003         if (dc->out && dc->out->disable)
2004                 dc->out->disable();
2005
2006         for (i = 0; i < dc->n_windows; i++) {
2007                 struct tegra_dc_win *w = &dc->windows[i];
2008
2009                 /* reset window bandwidth */
2010                 w->bandwidth = 0;
2011                 w->new_bandwidth = 0;
2012
2013                 /* disable windows */
2014                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2015
2016                 /* flush any pending syncpt waits */
2017                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2018                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2019                                 dc->syncpt[i].min, dc->syncpt[i].max);
2020                         dc->syncpt[i].min++;
2021                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2022                 }
2023         }
2024         trace_display_disable(dc);
2025 }
2026
2027 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2028 {
2029 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2030         u32 val;
2031         if (dc->enabled)  {
2032                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2033                 if (enable)
2034                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2035                 else
2036                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2037                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2038         }
2039 #endif
2040 }
2041
2042 bool tegra_dc_stats_get(struct tegra_dc *dc)
2043 {
2044 #if 0 /* right now it is always enabled */
2045         u32 val;
2046         bool res;
2047
2048         if (dc->enabled)  {
2049                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2050                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2051         } else {
2052                 res = false;
2053         }
2054
2055         return res;
2056 #endif
2057         return true;
2058 }
2059
2060 /* make the screen blank by disabling all windows */
2061 void tegra_dc_blank(struct tegra_dc *dc)
2062 {
2063         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2064         unsigned i;
2065
2066         for (i = 0; i < DC_N_WINDOWS; i++) {
2067                 dcwins[i] = tegra_dc_get_window(dc, i);
2068                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2069         }
2070
2071         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2072         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2073 }
2074
2075 static void _tegra_dc_disable(struct tegra_dc *dc)
2076 {
2077         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2078                 mutex_lock(&dc->one_shot_lock);
2079                 cancel_delayed_work_sync(&dc->one_shot_work);
2080         }
2081
2082         tegra_dc_io_start(dc);
2083         _tegra_dc_controller_disable(dc);
2084         tegra_dc_io_end(dc);
2085
2086         tegra_dc_powergate_locked(dc);
2087
2088         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2089                 mutex_unlock(&dc->one_shot_lock);
2090 }
2091
2092 void tegra_dc_disable(struct tegra_dc *dc)
2093 {
2094         tegra_dc_ext_disable(dc->ext);
2095
2096         /* it's important that new underflow work isn't scheduled before the
2097          * lock is acquired. */
2098         cancel_delayed_work_sync(&dc->underflow_work);
2099
2100         mutex_lock(&dc->lock);
2101
2102         if (dc->enabled) {
2103                 dc->enabled = false;
2104
2105                 if (!dc->suspended)
2106                         _tegra_dc_disable(dc);
2107         }
2108
2109 #ifdef CONFIG_SWITCH
2110         switch_set_state(&dc->modeset_switch, 0);
2111 #endif
2112
2113         mutex_unlock(&dc->lock);
2114         synchronize_irq(dc->irq);
2115         trace_display_mode(dc, &dc->mode);
2116 }
2117
2118 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2119 static void tegra_dc_reset_worker(struct work_struct *work)
2120 {
2121         struct tegra_dc *dc =
2122                 container_of(work, struct tegra_dc, reset_work);
2123
2124         unsigned long val = 0;
2125
2126         mutex_lock(&shared_lock);
2127
2128         dev_warn(&dc->ndev->dev,
2129                 "overlay stuck in underflow state.  resetting.\n");
2130
2131         tegra_dc_ext_disable(dc->ext);
2132
2133         mutex_lock(&dc->lock);
2134
2135         if (dc->enabled == false)
2136                 goto unlock;
2137
2138         dc->enabled = false;
2139
2140         /*
2141          * off host read bus
2142          */
2143         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2144         val &= ~(0x00000100);
2145         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2146
2147         /*
2148          * set DC to STOP mode
2149          */
2150         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2151
2152         msleep(10);
2153
2154         _tegra_dc_controller_disable(dc);
2155
2156         /* _tegra_dc_controller_reset_enable deasserts reset */
2157         _tegra_dc_controller_reset_enable(dc);
2158
2159         dc->enabled = true;
2160
2161         /* reopen host read bus */
2162         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2163         val &= ~(0x00000100);
2164         val |= 0x100;
2165         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2166
2167 unlock:
2168         mutex_unlock(&dc->lock);
2169         mutex_unlock(&shared_lock);
2170         trace_display_reset(dc);
2171 }
2172 #endif
2173
2174 static void tegra_dc_underflow_worker(struct work_struct *work)
2175 {
2176         struct tegra_dc *dc = container_of(
2177                 to_delayed_work(work), struct tegra_dc, underflow_work);
2178
2179         mutex_lock(&dc->lock);
2180         tegra_dc_io_start(dc);
2181         tegra_dc_hold_dc_out(dc);
2182
2183         if (dc->enabled) {
2184                 tegra_dc_underflow_handler(dc);
2185         }
2186         tegra_dc_release_dc_out(dc);
2187         tegra_dc_io_end(dc);
2188         mutex_unlock(&dc->lock);
2189 }
2190
2191 #ifdef CONFIG_SWITCH
2192 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2193 {
2194         struct tegra_dc *dc =
2195                 container_of(sdev, struct tegra_dc, modeset_switch);
2196
2197         if (!sdev->state)
2198                 return sprintf(buf, "offline\n");
2199
2200         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2201 }
2202 #endif
2203
2204 static void tegra_dc_add_modes(struct tegra_dc *dc)
2205 {
2206         struct fb_monspecs specs;
2207         int i;
2208
2209         memset(&specs, 0, sizeof(specs));
2210         specs.max_x = dc->mode.h_active * 1000;
2211         specs.max_y = dc->mode.v_active * 1000;
2212         specs.modedb_len = dc->out->n_modes;
2213         specs.modedb = kzalloc(specs.modedb_len *
2214                 sizeof(struct fb_videomode), GFP_KERNEL);
2215         for (i = 0; i < dc->out->n_modes; i++)
2216                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2217                         &dc->out->modes[i]);
2218         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2219         kfree(specs.modedb);
2220 }
2221
2222 static int tegra_dc_probe(struct platform_device *ndev)
2223 {
2224         struct tegra_dc *dc;
2225         struct tegra_dc_mode *mode;
2226         struct clk *clk;
2227         struct clk *emc_clk;
2228         struct resource *res;
2229         struct resource *base_res;
2230         struct resource *fb_mem = NULL;
2231         int ret = 0;
2232         void __iomem *base;
2233         int irq;
2234         int i;
2235
2236         if (!ndev->dev.platform_data) {
2237                 dev_err(&ndev->dev, "no platform data\n");
2238                 return -ENOENT;
2239         }
2240
2241         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2242         if (!dc) {
2243                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2244                 return -ENOMEM;
2245         }
2246
2247         irq = platform_get_irq_byname(ndev, "irq");
2248         if (irq <= 0) {
2249                 dev_err(&ndev->dev, "no irq\n");
2250                 ret = -ENOENT;
2251                 goto err_free;
2252         }
2253
2254         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2255         if (!res) {
2256                 dev_err(&ndev->dev, "no mem resource\n");
2257                 ret = -ENOENT;
2258                 goto err_free;
2259         }
2260
2261         base_res = request_mem_region(res->start, resource_size(res),
2262                 ndev->name);
2263         if (!base_res) {
2264                 dev_err(&ndev->dev, "request_mem_region failed\n");
2265                 ret = -EBUSY;
2266                 goto err_free;
2267         }
2268
2269         base = ioremap(res->start, resource_size(res));
2270         if (!base) {
2271                 dev_err(&ndev->dev, "registers can't be mapped\n");
2272                 ret = -EBUSY;
2273                 goto err_release_resource_reg;
2274         }
2275         if (TEGRA_DISPLAY_BASE == res->start) {
2276                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2277                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2278                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2279                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2280         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2281                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2282                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2283                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2284                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2285         } else {
2286                 dev_err(&ndev->dev,
2287                         "Unknown base address %#08x: unable to assign syncpt\n",
2288                         res->start);
2289         }
2290
2291
2292         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2293
2294         clk = clk_get(&ndev->dev, NULL);
2295         if (IS_ERR_OR_NULL(clk)) {
2296                 dev_err(&ndev->dev, "can't get clock\n");
2297                 ret = -ENOENT;
2298                 goto err_iounmap_reg;
2299         }
2300
2301         emc_clk = clk_get(&ndev->dev, "emc");
2302         if (IS_ERR_OR_NULL(emc_clk)) {
2303                 dev_err(&ndev->dev, "can't get emc clock\n");
2304                 ret = -ENOENT;
2305                 goto err_put_clk;
2306         }
2307
2308         dc->clk = clk;
2309         dc->emc_clk = emc_clk;
2310         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2311         /* Initialize one shot work delay, it will be assigned by dsi
2312          * according to refresh rate later. */
2313         dc->one_shot_delay_ms = 40;
2314
2315         dc->base_res = base_res;
2316         dc->base = base;
2317         dc->irq = irq;
2318         dc->ndev = ndev;
2319         dc->pdata = ndev->dev.platform_data;
2320
2321         /*
2322          * The emc is a shared clock, it will be set based on
2323          * the requirements for each user on the bus.
2324          */
2325         dc->emc_clk_rate = 0;
2326
2327         mutex_init(&dc->lock);
2328         mutex_init(&dc->one_shot_lock);
2329         init_completion(&dc->frame_end_complete);
2330         init_waitqueue_head(&dc->wq);
2331         init_waitqueue_head(&dc->timestamp_wq);
2332 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2333         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2334 #endif
2335         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2336         dc->vblank_ref_count = 0;
2337 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2338         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2339 #endif
2340         dc->vpulse2_ref_count = 0;
2341         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2342         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2343
2344         tegra_dc_init_lut_defaults(&dc->fb_lut);
2345
2346         dc->n_windows = DC_N_WINDOWS;
2347         for (i = 0; i < dc->n_windows; i++) {
2348                 struct tegra_dc_win *win = &dc->windows[i];
2349                 win->idx = i;
2350                 win->dc = dc;
2351                 tegra_dc_init_csc_defaults(&win->csc);
2352                 tegra_dc_init_lut_defaults(&win->lut);
2353         }
2354
2355         ret = tegra_dc_set(dc, ndev->id);
2356         if (ret < 0) {
2357                 dev_err(&ndev->dev, "can't add dc\n");
2358                 goto err_free_irq;
2359         }
2360
2361         platform_set_drvdata(ndev, dc);
2362
2363 #ifdef CONFIG_SWITCH
2364         dc->modeset_switch.name = dev_name(&ndev->dev);
2365         dc->modeset_switch.state = 0;
2366         dc->modeset_switch.print_state = switch_modeset_print_mode;
2367         ret = switch_dev_register(&dc->modeset_switch);
2368         if (ret < 0)
2369                 dev_err(&ndev->dev, "failed to register switch driver\n");
2370 #endif
2371
2372         tegra_dc_feature_register(dc);
2373
2374         if (dc->pdata->default_out)
2375                 tegra_dc_set_out(dc, dc->pdata->default_out);
2376         else
2377                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2378
2379         dc->ext = tegra_dc_ext_register(ndev, dc);
2380         if (IS_ERR_OR_NULL(dc->ext)) {
2381                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2382                 dc->ext = NULL;
2383         }
2384
2385         /* interrupt handler must be registered before tegra_fb_register() */
2386         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2387                         dev_name(&ndev->dev), dc)) {
2388                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2389                 ret = -EBUSY;
2390                 goto err_put_emc_clk;
2391         }
2392         disable_dc_irq(dc);
2393
2394         mutex_lock(&dc->lock);
2395         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2396                 _tegra_dc_set_default_videomode(dc);
2397                 dc->enabled = _tegra_dc_enable(dc);
2398         }
2399         mutex_unlock(&dc->lock);
2400
2401         tegra_dc_create_debugfs(dc);
2402
2403         dev_info(&ndev->dev, "probed\n");
2404
2405         if (dc->pdata->fb) {
2406                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2407                         unsigned long fmt;
2408                         tegra_dc_writel(dc,
2409                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2410                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2411
2412                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2413                         dc->pdata->fb->bits_per_pixel =
2414                                 tegra_dc_fmt_bpp(fmt);
2415                 }
2416
2417                 mode = tegra_dc_get_override_mode(dc);
2418                 if (mode) {
2419                         dc->pdata->fb->xres = mode->h_active;
2420                         dc->pdata->fb->yres = mode->v_active;
2421                 }
2422
2423                 tegra_dc_io_start(dc);
2424                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2425                 if (IS_ERR_OR_NULL(dc->fb))
2426                         dc->fb = NULL;
2427                 tegra_dc_io_end(dc);
2428         }
2429
2430         if (dc->out && dc->out->n_modes)
2431                 tegra_dc_add_modes(dc);
2432
2433         if (dc->out && dc->out->hotplug_init)
2434                 dc->out->hotplug_init(&ndev->dev);
2435
2436         if (dc->out_ops && dc->out_ops->detect)
2437                 dc->out_ops->detect(dc);
2438         else
2439                 dc->connected = true;
2440
2441 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2442         /* Powergate display module when it's unconnected. */
2443         if (!tegra_dc_get_connected(dc))
2444                 tegra_dc_powergate_locked(dc);
2445 #endif
2446
2447         tegra_dc_create_sysfs(&dc->ndev->dev);
2448
2449         return 0;
2450
2451 err_free_irq:
2452         free_irq(irq, dc);
2453 err_put_emc_clk:
2454         clk_put(emc_clk);
2455 err_put_clk:
2456         clk_put(clk);
2457 err_iounmap_reg:
2458         iounmap(base);
2459         if (fb_mem)
2460                 release_resource(fb_mem);
2461 err_release_resource_reg:
2462         release_resource(base_res);
2463 err_free:
2464         kfree(dc);
2465
2466         return ret;
2467 }
2468
2469 static int tegra_dc_remove(struct platform_device *ndev)
2470 {
2471         struct tegra_dc *dc = platform_get_drvdata(ndev);
2472
2473         tegra_dc_remove_sysfs(&dc->ndev->dev);
2474         tegra_dc_remove_debugfs(dc);
2475
2476         if (dc->fb) {
2477                 tegra_fb_unregister(dc->fb);
2478                 if (dc->fb_mem)
2479                         release_resource(dc->fb_mem);
2480         }
2481
2482         tegra_dc_ext_disable(dc->ext);
2483
2484         if (dc->ext)
2485                 tegra_dc_ext_unregister(dc->ext);
2486
2487         mutex_lock(&dc->lock);
2488         if (dc->enabled)
2489                 _tegra_dc_disable(dc);
2490         dc->enabled = false;
2491         mutex_unlock(&dc->lock);
2492         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2493
2494 #ifdef CONFIG_SWITCH
2495         switch_dev_unregister(&dc->modeset_switch);
2496 #endif
2497         free_irq(dc->irq, dc);
2498         clk_put(dc->emc_clk);
2499         clk_put(dc->clk);
2500         iounmap(dc->base);
2501         if (dc->fb_mem)
2502                 release_resource(dc->base_res);
2503         kfree(dc);
2504         tegra_dc_set(NULL, ndev->id);
2505
2506         return 0;
2507 }
2508
2509 #ifdef CONFIG_PM
2510 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2511 {
2512         struct tegra_dc *dc = platform_get_drvdata(ndev);
2513
2514         trace_display_suspend(dc);
2515         dev_info(&ndev->dev, "suspend\n");
2516
2517         tegra_dc_ext_disable(dc->ext);
2518
2519         mutex_lock(&dc->lock);
2520         tegra_dc_io_start(dc);
2521
2522         if (dc->out_ops && dc->out_ops->suspend)
2523                 dc->out_ops->suspend(dc);
2524
2525         if (dc->enabled) {
2526                 _tegra_dc_disable(dc);
2527
2528                 dc->suspended = true;
2529         }
2530
2531         if (dc->out && dc->out->postsuspend) {
2532                 dc->out->postsuspend();
2533                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2534                         /*
2535                          * avoid resume event due to voltage falling
2536                          */
2537                         msleep(100);
2538         }
2539
2540         tegra_dc_io_end(dc);
2541         mutex_unlock(&dc->lock);
2542         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2543
2544         return 0;
2545 }
2546
2547 static int tegra_dc_resume(struct platform_device *ndev)
2548 {
2549         struct tegra_dc *dc = platform_get_drvdata(ndev);
2550
2551         trace_display_resume(dc);
2552         dev_info(&ndev->dev, "resume\n");
2553
2554         mutex_lock(&dc->lock);
2555         dc->suspended = false;
2556
2557         if (dc->enabled) {
2558                 dc->enabled = false;
2559                 _tegra_dc_set_default_videomode(dc);
2560                 dc->enabled = _tegra_dc_enable(dc);
2561         }
2562
2563         if (dc->out && dc->out->hotplug_init)
2564                 dc->out->hotplug_init(&ndev->dev);
2565
2566         if (dc->out_ops && dc->out_ops->resume)
2567                 dc->out_ops->resume(dc);
2568         mutex_unlock(&dc->lock);
2569
2570         return 0;
2571 }
2572
2573 #endif /* CONFIG_PM */
2574
2575 static void tegra_dc_shutdown(struct platform_device *ndev)
2576 {
2577         struct tegra_dc *dc = platform_get_drvdata(ndev);
2578
2579         if (!dc || !dc->enabled)
2580                 return;
2581
2582         tegra_dc_blank(dc);
2583         tegra_dc_disable(dc);
2584 }
2585
2586 extern int suspend_set(const char *val, struct kernel_param *kp)
2587 {
2588         if (!strcmp(val, "dump"))
2589                 dump_regs(tegra_dcs[0]);
2590 #ifdef CONFIG_PM
2591         else if (!strcmp(val, "suspend"))
2592                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2593         else if (!strcmp(val, "resume"))
2594                 tegra_dc_resume(tegra_dcs[0]->ndev);
2595 #endif
2596
2597         return 0;
2598 }
2599
2600 extern int suspend_get(char *buffer, struct kernel_param *kp)
2601 {
2602         return 0;
2603 }
2604
2605 int suspend;
2606
2607 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2608
2609 struct platform_driver tegra_dc_driver = {
2610         .driver = {
2611                 .name = "tegradc",
2612                 .owner = THIS_MODULE,
2613         },
2614         .probe = tegra_dc_probe,
2615         .remove = tegra_dc_remove,
2616 #ifdef CONFIG_PM
2617         .suspend = tegra_dc_suspend,
2618         .resume = tegra_dc_resume,
2619 #endif
2620         .shutdown = tegra_dc_shutdown,
2621 };
2622
2623 #ifndef MODULE
2624 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2625 {
2626         int i, params[11];
2627         char *p;
2628
2629         for (i = 0; i < ARRAY_SIZE(params); i++) {
2630                 if ((p = strsep(&options, ",")) != NULL) {
2631                         if (*p)
2632                                 params[i] = simple_strtoul(p, &p, 10);
2633                 } else
2634                         return -EINVAL;
2635         }
2636
2637         if ((mode->pclk = params[0]) == 0)
2638                 return -EINVAL;
2639
2640         mode->h_active      = params[1];
2641         mode->v_active      = params[2];
2642         mode->h_ref_to_sync = params[3];
2643         mode->v_ref_to_sync = params[4];
2644         mode->h_sync_width  = params[5];
2645         mode->v_sync_width  = params[6];
2646         mode->h_back_porch  = params[7];
2647         mode->v_back_porch  = params[8];
2648         mode->h_front_porch = params[9];
2649         mode->v_front_porch = params[10];
2650
2651         return 0;
2652 }
2653
2654 static int __init tegra_dc_mode_override(char *str)
2655 {
2656         char *p = str, *options;
2657
2658         if (!p || !*p)
2659                 return -EINVAL;
2660
2661         p = strstr(str, "hdmi:");
2662         if (p) {
2663                 p += 5;
2664                 options = strsep(&p, ";");
2665                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2666                         return -EINVAL;
2667         }
2668
2669         p = strstr(str, "rgb:");
2670         if (p) {
2671                 p += 4;
2672                 options = strsep(&p, ";");
2673                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2674                         return -EINVAL;
2675         }
2676
2677         p = strstr(str, "dsi:");
2678         if (p) {
2679                 p += 4;
2680                 options = strsep(&p, ";");
2681                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2682                         return -EINVAL;
2683         }
2684
2685         return 0;
2686 }
2687
2688 __setup("disp_params=", tegra_dc_mode_override);
2689 #endif
2690
2691 static int __init tegra_dc_module_init(void)
2692 {
2693         int ret = tegra_dc_ext_module_init();
2694         if (ret)
2695                 return ret;
2696         return platform_driver_register(&tegra_dc_driver);
2697 }
2698
2699 static void __exit tegra_dc_module_exit(void)
2700 {
2701         platform_driver_unregister(&tegra_dc_driver);
2702         tegra_dc_ext_module_exit();
2703 }
2704
2705 module_exit(tegra_dc_module_exit);
2706 module_init(tegra_dc_module_init);