arm: tegra: roth: fix regulator in initialized mode
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2013, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <video/tegrafb.h>
41 #include <drm/drm_fixed.h>
42 #ifdef CONFIG_SWITCH
43 #include <linux/switch.h>
44 #endif
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55
56 #include "dc_reg.h"
57 #include "dc_config.h"
58 #include "dc_priv.h"
59 #include "dev.h"
60 #include "nvsd.h"
61
62 /* HACK! This needs to come from DT */
63 #include "../../../../arch/arm/mach-tegra/iomap.h"
64
65 #define TEGRA_CRC_LATCHED_DELAY         34
66
67 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
68 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
69
70 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
71         .refresh = 60,
72         .xres = 640,
73         .yres = 480,
74         .pixclock = KHZ2PICOS(25200),
75         .hsync_len = 96,        /* h_sync_width */
76         .vsync_len = 2,         /* v_sync_width */
77         .left_margin = 48,      /* h_back_porch */
78         .upper_margin = 33,     /* v_back_porch */
79         .right_margin = 16,     /* h_front_porch */
80         .lower_margin = 10,     /* v_front_porch */
81         .vmode = 0,
82         .sync = 0,
83 };
84
85 static struct tegra_dc_mode override_disp_mode[3];
86
87 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
88
89 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
90
91 DEFINE_MUTEX(tegra_dc_lock);
92 DEFINE_MUTEX(shared_lock);
93
94 static const struct {
95         bool h;
96         bool v;
97 } can_filter[] = {
98         /* Window A has no filtering */
99         { false, false },
100         /* Window B has both H and V filtering */
101         { true,  true  },
102         /* Window C has only H filtering */
103         { false, true  },
104 };
105
106 #ifdef CONFIG_TEGRA_DC_CMU
107 static struct tegra_dc_cmu default_cmu = {
108         /* lut1 maps sRGB to linear space. */
109         {
110                 0,    1,    2,    4,    5,    6,    7,    9,
111                 10,   11,   12,   14,   15,   16,   18,   20,
112                 21,   23,   25,   27,   29,   31,   33,   35,
113                 37,   40,   42,   45,   48,   50,   53,   56,
114                 59,   62,   66,   69,   72,   76,   79,   83,
115                 87,   91,   95,   99,   103,  107,  112,  116,
116                 121,  126,  131,  136,  141,  146,  151,  156,
117                 162,  168,  173,  179,  185,  191,  197,  204,
118                 210,  216,  223,  230,  237,  244,  251,  258,
119                 265,  273,  280,  288,  296,  304,  312,  320,
120                 329,  337,  346,  354,  363,  372,  381,  390,
121                 400,  409,  419,  428,  438,  448,  458,  469,
122                 479,  490,  500,  511,  522,  533,  544,  555,
123                 567,  578,  590,  602,  614,  626,  639,  651,
124                 664,  676,  689,  702,  715,  728,  742,  755,
125                 769,  783,  797,  811,  825,  840,  854,  869,
126                 884,  899,  914,  929,  945,  960,  976,  992,
127                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
128                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
129                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
130                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
131                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
132                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
133                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
134                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
135                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
136                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
137                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
138                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
139                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
140                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
141                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
142         },
143         /* csc */
144         {
145                 0x100, 0x0,   0x0,
146                 0x0,   0x100, 0x0,
147                 0x0,   0x0,   0x100,
148         },
149         /* lut2 maps linear space to sRGB*/
150         {
151                 0,    1,    2,    2,    3,    4,    5,    6,
152                 6,    7,    8,    9,    10,   10,   11,   12,
153                 13,   13,   14,   15,   15,   16,   16,   17,
154                 18,   18,   19,   19,   20,   20,   21,   21,
155                 22,   22,   23,   23,   23,   24,   24,   25,
156                 25,   25,   26,   26,   27,   27,   27,   28,
157                 28,   29,   29,   29,   30,   30,   30,   31,
158                 31,   31,   32,   32,   32,   33,   33,   33,
159                 34,   34,   34,   34,   35,   35,   35,   36,
160                 36,   36,   37,   37,   37,   37,   38,   38,
161                 38,   38,   39,   39,   39,   40,   40,   40,
162                 40,   41,   41,   41,   41,   42,   42,   42,
163                 42,   43,   43,   43,   43,   43,   44,   44,
164                 44,   44,   45,   45,   45,   45,   46,   46,
165                 46,   46,   46,   47,   47,   47,   47,   48,
166                 48,   48,   48,   48,   49,   49,   49,   49,
167                 49,   50,   50,   50,   50,   50,   51,   51,
168                 51,   51,   51,   52,   52,   52,   52,   52,
169                 53,   53,   53,   53,   53,   54,   54,   54,
170                 54,   54,   55,   55,   55,   55,   55,   55,
171                 56,   56,   56,   56,   56,   57,   57,   57,
172                 57,   57,   57,   58,   58,   58,   58,   58,
173                 58,   59,   59,   59,   59,   59,   59,   60,
174                 60,   60,   60,   60,   60,   61,   61,   61,
175                 61,   61,   61,   62,   62,   62,   62,   62,
176                 62,   63,   63,   63,   63,   63,   63,   64,
177                 64,   64,   64,   64,   64,   64,   65,   65,
178                 65,   65,   65,   65,   66,   66,   66,   66,
179                 66,   66,   66,   67,   67,   67,   67,   67,
180                 67,   67,   68,   68,   68,   68,   68,   68,
181                 68,   69,   69,   69,   69,   69,   69,   69,
182                 70,   70,   70,   70,   70,   70,   70,   71,
183                 71,   71,   71,   71,   71,   71,   72,   72,
184                 72,   72,   72,   72,   72,   72,   73,   73,
185                 73,   73,   73,   73,   73,   74,   74,   74,
186                 74,   74,   74,   74,   74,   75,   75,   75,
187                 75,   75,   75,   75,   75,   76,   76,   76,
188                 76,   76,   76,   76,   77,   77,   77,   77,
189                 77,   77,   77,   77,   78,   78,   78,   78,
190                 78,   78,   78,   78,   78,   79,   79,   79,
191                 79,   79,   79,   79,   79,   80,   80,   80,
192                 80,   80,   80,   80,   80,   81,   81,   81,
193                 81,   81,   81,   81,   81,   81,   82,   82,
194                 82,   82,   82,   82,   82,   82,   83,   83,
195                 83,   83,   83,   83,   83,   83,   83,   84,
196                 84,   84,   84,   84,   84,   84,   84,   84,
197                 85,   85,   85,   85,   85,   85,   85,   85,
198                 85,   86,   86,   86,   86,   86,   86,   86,
199                 86,   86,   87,   87,   87,   87,   87,   87,
200                 87,   87,   87,   88,   88,   88,   88,   88,
201                 88,   88,   88,   88,   88,   89,   89,   89,
202                 89,   89,   89,   89,   89,   89,   90,   90,
203                 90,   90,   90,   90,   90,   90,   90,   90,
204                 91,   91,   91,   91,   91,   91,   91,   91,
205                 91,   91,   92,   92,   92,   92,   92,   92,
206                 92,   92,   92,   92,   93,   93,   93,   93,
207                 93,   93,   93,   93,   93,   93,   94,   94,
208                 94,   94,   94,   94,   94,   94,   94,   94,
209                 95,   95,   95,   95,   95,   95,   95,   95,
210                 95,   95,   96,   96,   96,   96,   96,   96,
211                 96,   96,   96,   96,   96,   97,   97,   97,
212                 97,   97,   97,   97,   97,   97,   97,   98,
213                 98,   98,   98,   98,   98,   98,   98,   98,
214                 98,   98,   99,   99,   99,   99,   99,   99,
215                 99,   100,  101,  101,  102,  103,  103,  104,
216                 105,  105,  106,  107,  107,  108,  109,  109,
217                 110,  111,  111,  112,  113,  113,  114,  115,
218                 115,  116,  116,  117,  118,  118,  119,  119,
219                 120,  120,  121,  122,  122,  123,  123,  124,
220                 124,  125,  126,  126,  127,  127,  128,  128,
221                 129,  129,  130,  130,  131,  131,  132,  132,
222                 133,  133,  134,  134,  135,  135,  136,  136,
223                 137,  137,  138,  138,  139,  139,  140,  140,
224                 141,  141,  142,  142,  143,  143,  144,  144,
225                 145,  145,  145,  146,  146,  147,  147,  148,
226                 148,  149,  149,  150,  150,  150,  151,  151,
227                 152,  152,  153,  153,  153,  154,  154,  155,
228                 155,  156,  156,  156,  157,  157,  158,  158,
229                 158,  159,  159,  160,  160,  160,  161,  161,
230                 162,  162,  162,  163,  163,  164,  164,  164,
231                 165,  165,  166,  166,  166,  167,  167,  167,
232                 168,  168,  169,  169,  169,  170,  170,  170,
233                 171,  171,  172,  172,  172,  173,  173,  173,
234                 174,  174,  174,  175,  175,  176,  176,  176,
235                 177,  177,  177,  178,  178,  178,  179,  179,
236                 179,  180,  180,  180,  181,  181,  182,  182,
237                 182,  183,  183,  183,  184,  184,  184,  185,
238                 185,  185,  186,  186,  186,  187,  187,  187,
239                 188,  188,  188,  189,  189,  189,  189,  190,
240                 190,  190,  191,  191,  191,  192,  192,  192,
241                 193,  193,  193,  194,  194,  194,  195,  195,
242                 195,  196,  196,  196,  196,  197,  197,  197,
243                 198,  198,  198,  199,  199,  199,  200,  200,
244                 200,  200,  201,  201,  201,  202,  202,  202,
245                 202,  203,  203,  203,  204,  204,  204,  205,
246                 205,  205,  205,  206,  206,  206,  207,  207,
247                 207,  207,  208,  208,  208,  209,  209,  209,
248                 209,  210,  210,  210,  211,  211,  211,  211,
249                 212,  212,  212,  213,  213,  213,  213,  214,
250                 214,  214,  214,  215,  215,  215,  216,  216,
251                 216,  216,  217,  217,  217,  217,  218,  218,
252                 218,  219,  219,  219,  219,  220,  220,  220,
253                 220,  221,  221,  221,  221,  222,  222,  222,
254                 223,  223,  223,  223,  224,  224,  224,  224,
255                 225,  225,  225,  225,  226,  226,  226,  226,
256                 227,  227,  227,  227,  228,  228,  228,  228,
257                 229,  229,  229,  229,  230,  230,  230,  230,
258                 231,  231,  231,  231,  232,  232,  232,  232,
259                 233,  233,  233,  233,  234,  234,  234,  234,
260                 235,  235,  235,  235,  236,  236,  236,  236,
261                 237,  237,  237,  237,  238,  238,  238,  238,
262                 239,  239,  239,  239,  240,  240,  240,  240,
263                 240,  241,  241,  241,  241,  242,  242,  242,
264                 242,  243,  243,  243,  243,  244,  244,  244,
265                 244,  244,  245,  245,  245,  245,  246,  246,
266                 246,  246,  247,  247,  247,  247,  247,  248,
267                 248,  248,  248,  249,  249,  249,  249,  249,
268                 250,  250,  250,  250,  251,  251,  251,  251,
269                 251,  252,  252,  252,  252,  253,  253,  253,
270                 253,  253,  254,  254,  254,  254,  255,  255,
271         },
272 };
273 #endif
274
275 void tegra_dc_clk_enable(struct tegra_dc *dc)
276 {
277         if (!tegra_is_clk_enabled(dc->clk)) {
278                 clk_prepare_enable(dc->clk);
279                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
280         }
281 }
282
283 void tegra_dc_clk_disable(struct tegra_dc *dc)
284 {
285         if (tegra_is_clk_enabled(dc->clk)) {
286                 clk_disable_unprepare(dc->clk);
287                 tegra_dvfs_set_rate(dc->clk, 0);
288         }
289 }
290
291 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
292 {
293         /* extra reference to dc clk */
294         clk_prepare_enable(dc->clk);
295
296         if (dc->out_ops->hold)
297                 dc->out_ops->hold(dc);
298 }
299
300 void tegra_dc_release_dc_out(struct tegra_dc *dc)
301 {
302         if (dc->out_ops->release)
303                 dc->out_ops->release(dc);
304
305         /* balance extra dc clk reference */
306         clk_disable_unprepare(dc->clk);
307 }
308
309 #define DUMP_REG(a) do {                        \
310         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
311                  #a, a, tegra_dc_readl(dc, a));               \
312         print(data, buff);                                    \
313         } while (0)
314
315 static void _dump_regs(struct tegra_dc *dc, void *data,
316                        void (* print)(void *data, const char *str))
317 {
318         int i;
319         char buff[256];
320
321         mutex_lock(&dc->lock);
322         tegra_dc_io_start(dc);
323         tegra_dc_hold_dc_out(dc);
324
325         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
326         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
327         DUMP_REG(DC_CMD_SIGNAL_RAISE);
328         DUMP_REG(DC_CMD_INT_STATUS);
329         DUMP_REG(DC_CMD_INT_MASK);
330         DUMP_REG(DC_CMD_INT_ENABLE);
331         DUMP_REG(DC_CMD_INT_TYPE);
332         DUMP_REG(DC_CMD_INT_POLARITY);
333         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
334         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
335         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
336         DUMP_REG(DC_CMD_STATE_ACCESS);
337         DUMP_REG(DC_CMD_STATE_CONTROL);
338         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
339         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
340
341         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
342         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
343         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
344         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
345         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
346         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
347         DUMP_REG(DC_DISP_REF_TO_SYNC);
348         DUMP_REG(DC_DISP_SYNC_WIDTH);
349         DUMP_REG(DC_DISP_BACK_PORCH);
350         DUMP_REG(DC_DISP_DISP_ACTIVE);
351         DUMP_REG(DC_DISP_FRONT_PORCH);
352         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
353         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
354         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
355         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
356         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
357         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
358         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
359         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
360         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
361         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
362         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
363         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
364         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
365         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
366         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
367         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
369         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
370         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
371         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
372         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
373         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
374         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
375         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
376         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
377         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
378         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
379         DUMP_REG(DC_DISP_M0_CONTROL);
380         DUMP_REG(DC_DISP_M1_CONTROL);
381         DUMP_REG(DC_DISP_DI_CONTROL);
382         DUMP_REG(DC_DISP_PP_CONTROL);
383         DUMP_REG(DC_DISP_PP_SELECT_A);
384         DUMP_REG(DC_DISP_PP_SELECT_B);
385         DUMP_REG(DC_DISP_PP_SELECT_C);
386         DUMP_REG(DC_DISP_PP_SELECT_D);
387         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
388         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
389         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
390         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
391         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
392         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
393         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
394         DUMP_REG(DC_DISP_BORDER_COLOR);
395         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
396         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
397         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
398         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
399         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
400         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
401         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
402         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
403         DUMP_REG(DC_DISP_CURSOR_POSITION);
404         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
405         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
406         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
407         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
408         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
409         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
410         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
412         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
413         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
414 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
415         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
416 #endif
417         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
418         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
419
420
421         for (i = 0; i < 3; i++) {
422                 print(data, "\n");
423                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
424                 print(data, buff);
425
426                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
427                                 DC_CMD_DISPLAY_WINDOW_HEADER);
428                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
429                 DUMP_REG(DC_WIN_WIN_OPTIONS);
430                 DUMP_REG(DC_WIN_BYTE_SWAP);
431                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
432                 DUMP_REG(DC_WIN_COLOR_DEPTH);
433                 DUMP_REG(DC_WIN_POSITION);
434                 DUMP_REG(DC_WIN_SIZE);
435                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
436                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
437                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
438                 DUMP_REG(DC_WIN_DDA_INCREMENT);
439                 DUMP_REG(DC_WIN_LINE_STRIDE);
440 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
441                 DUMP_REG(DC_WIN_BUF_STRIDE);
442                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
443 #endif
444                 DUMP_REG(DC_WIN_BLEND_NOKEY);
445                 DUMP_REG(DC_WIN_BLEND_1WIN);
446                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
447                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
448                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
449                 DUMP_REG(DC_WINBUF_START_ADDR);
450                 DUMP_REG(DC_WINBUF_START_ADDR_U);
451                 DUMP_REG(DC_WINBUF_START_ADDR_V);
452                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
453                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
454                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
455                 DUMP_REG(DC_WIN_CSC_YOF);
456                 DUMP_REG(DC_WIN_CSC_KYRGB);
457                 DUMP_REG(DC_WIN_CSC_KUR);
458                 DUMP_REG(DC_WIN_CSC_KVR);
459                 DUMP_REG(DC_WIN_CSC_KUG);
460                 DUMP_REG(DC_WIN_CSC_KVG);
461                 DUMP_REG(DC_WIN_CSC_KUB);
462                 DUMP_REG(DC_WIN_CSC_KVB);
463         }
464
465         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
466         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
467         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
468         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
469         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
470         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
471         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
472         DUMP_REG(DC_DISP_M1_CONTROL);
473         DUMP_REG(DC_COM_PM1_CONTROL);
474         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
475         DUMP_REG(DC_DISP_SD_CONTROL);
476 #ifdef CONFIG_TEGRA_DC_CMU
477         DUMP_REG(DC_COM_CMU_CSC_KRR);
478         DUMP_REG(DC_COM_CMU_CSC_KGR);
479         DUMP_REG(DC_COM_CMU_CSC_KBR);
480         DUMP_REG(DC_COM_CMU_CSC_KRG);
481         DUMP_REG(DC_COM_CMU_CSC_KGG);
482         DUMP_REG(DC_COM_CMU_CSC_KBR);
483         DUMP_REG(DC_COM_CMU_CSC_KRB);
484         DUMP_REG(DC_COM_CMU_CSC_KGB);
485         DUMP_REG(DC_COM_CMU_CSC_KBB);
486 #endif
487
488         tegra_dc_release_dc_out(dc);
489         tegra_dc_io_end(dc);
490         mutex_unlock(&dc->lock);
491 }
492
493 #undef DUMP_REG
494
495 #ifdef DEBUG
496 static void dump_regs_print(void *data, const char *str)
497 {
498         struct tegra_dc *dc = data;
499         dev_dbg(&dc->ndev->dev, "%s", str);
500 }
501
502 static void dump_regs(struct tegra_dc *dc)
503 {
504         _dump_regs(dc, dc, dump_regs_print);
505 }
506 #else /* !DEBUG */
507
508 static void dump_regs(struct tegra_dc *dc) {}
509
510 #endif /* DEBUG */
511
512 #ifdef CONFIG_DEBUG_FS
513
514 static void dbg_regs_print(void *data, const char *str)
515 {
516         struct seq_file *s = data;
517
518         seq_printf(s, "%s", str);
519 }
520
521 #undef DUMP_REG
522
523 static int dbg_dc_show(struct seq_file *s, void *unused)
524 {
525         struct tegra_dc *dc = s->private;
526
527         _dump_regs(dc, s, dbg_regs_print);
528
529         return 0;
530 }
531
532
533 static int dbg_dc_open(struct inode *inode, struct file *file)
534 {
535         return single_open(file, dbg_dc_show, inode->i_private);
536 }
537
538 static const struct file_operations regs_fops = {
539         .open           = dbg_dc_open,
540         .read           = seq_read,
541         .llseek         = seq_lseek,
542         .release        = single_release,
543 };
544
545 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
546 {
547         struct tegra_dc *dc = s->private;
548         struct tegra_dc_mode *m;
549
550         mutex_lock(&dc->lock);
551         m = &dc->mode;
552         seq_printf(s,
553                 "pclk: %d\n"
554                 "h_ref_to_sync: %d\n"
555                 "v_ref_to_sync: %d\n"
556                 "h_sync_width: %d\n"
557                 "v_sync_width: %d\n"
558                 "h_back_porch: %d\n"
559                 "v_back_porch: %d\n"
560                 "h_active: %d\n"
561                 "v_active: %d\n"
562                 "h_front_porch: %d\n"
563                 "v_front_porch: %d\n"
564                 "stereo_mode: %d\n",
565                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
566                 m->h_sync_width, m->v_sync_width,
567                 m->h_back_porch, m->v_back_porch,
568                 m->h_active, m->v_active,
569                 m->h_front_porch, m->v_front_porch,
570                 m->stereo_mode);
571         mutex_unlock(&dc->lock);
572         return 0;
573 }
574
575 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
576 {
577         return single_open(file, dbg_dc_mode_show, inode->i_private);
578 }
579
580 static const struct file_operations mode_fops = {
581         .open           = dbg_dc_mode_open,
582         .read           = seq_read,
583         .llseek         = seq_lseek,
584         .release        = single_release,
585 };
586
587 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
588 {
589         struct tegra_dc *dc = s->private;
590
591         mutex_lock(&dc->lock);
592         seq_printf(s,
593                 "underflows: %llu\n"
594                 "underflows_a: %llu\n"
595                 "underflows_b: %llu\n"
596                 "underflows_c: %llu\n",
597                 dc->stats.underflows,
598                 dc->stats.underflows_a,
599                 dc->stats.underflows_b,
600                 dc->stats.underflows_c);
601         mutex_unlock(&dc->lock);
602
603         return 0;
604 }
605
606 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
607 {
608         return single_open(file, dbg_dc_stats_show, inode->i_private);
609 }
610
611 static const struct file_operations stats_fops = {
612         .open           = dbg_dc_stats_open,
613         .read           = seq_read,
614         .llseek         = seq_lseek,
615         .release        = single_release,
616 };
617
618 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
619 {
620         if (dc->debugdir)
621                 debugfs_remove_recursive(dc->debugdir);
622         dc->debugdir = NULL;
623 }
624
625 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
626 {
627         struct dentry *retval;
628
629         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
630         if (!dc->debugdir)
631                 goto remove_out;
632
633         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
634                 &regs_fops);
635         if (!retval)
636                 goto remove_out;
637
638         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
639                 &mode_fops);
640         if (!retval)
641                 goto remove_out;
642
643         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
644                 &stats_fops);
645         if (!retval)
646                 goto remove_out;
647
648         return;
649 remove_out:
650         dev_err(&dc->ndev->dev, "could not create debugfs\n");
651         tegra_dc_remove_debugfs(dc);
652 }
653
654 #else /* !CONFIG_DEBUGFS */
655 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
656 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
657 #endif /* CONFIG_DEBUGFS */
658
659 static int tegra_dc_set(struct tegra_dc *dc, int index)
660 {
661         int ret = 0;
662
663         mutex_lock(&tegra_dc_lock);
664         if (index >= TEGRA_MAX_DC) {
665                 ret = -EINVAL;
666                 goto out;
667         }
668
669         if (dc != NULL && tegra_dcs[index] != NULL) {
670                 ret = -EBUSY;
671                 goto out;
672         }
673
674         tegra_dcs[index] = dc;
675
676 out:
677         mutex_unlock(&tegra_dc_lock);
678
679         return ret;
680 }
681
682 unsigned int tegra_dc_has_multiple_dc(void)
683 {
684         unsigned int idx;
685         unsigned int cnt = 0;
686         struct tegra_dc *dc;
687
688         mutex_lock(&tegra_dc_lock);
689         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
690                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
691         mutex_unlock(&tegra_dc_lock);
692
693         return (cnt > 1);
694 }
695
696 /* get the stride size of a window.
697  * return: stride size in bytes for window win. or 0 if unavailble. */
698 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
699 {
700         u32 stride;
701
702         if (!dc->enabled)
703                 return 0;
704         BUG_ON(win > DC_N_WINDOWS);
705         mutex_lock(&dc->lock);
706         tegra_dc_io_start(dc);
707         tegra_dc_hold_dc_out(dc);
708         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
709                 DC_CMD_DISPLAY_WINDOW_HEADER);
710         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
711         tegra_dc_release_dc_out(dc);
712         tegra_dc_io_end(dc);
713         mutex_unlock(&dc->lock);
714         return GET_LINE_STRIDE(stride);
715 }
716 EXPORT_SYMBOL(tegra_dc_get_stride);
717
718 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
719 {
720         if (idx < TEGRA_MAX_DC)
721                 return tegra_dcs[idx];
722         else
723                 return NULL;
724 }
725 EXPORT_SYMBOL(tegra_dc_get_dc);
726
727 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
728 {
729         if (win >= dc->n_windows)
730                 return NULL;
731
732         return &dc->windows[win];
733 }
734 EXPORT_SYMBOL(tegra_dc_get_window);
735
736 bool tegra_dc_get_connected(struct tegra_dc *dc)
737 {
738         return dc->connected;
739 }
740 EXPORT_SYMBOL(tegra_dc_get_connected);
741
742 bool tegra_dc_hpd(struct tegra_dc *dc)
743 {
744         int sense;
745         int level;
746
747         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
748
749         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
750
751         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
752                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
753 }
754 EXPORT_SYMBOL(tegra_dc_hpd);
755
756 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
757 {
758         unsigned i;
759         unsigned v0 = 128;
760         unsigned v1 = 0;
761
762         /* linear horizontal and vertical filters */
763         for (i = 0; i < 16; i++) {
764                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
765                                 DC_WIN_H_FILTER_P(i));
766
767                 tegra_dc_writel(dc, v0,
768                                 DC_WIN_V_FILTER_P(i));
769                 v0 -= 8;
770                 v1 += 8;
771         }
772 }
773
774 #ifdef CONFIG_TEGRA_DC_CMU
775 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
776                                         struct tegra_dc_cmu *src_cmu)
777 {
778         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
779 }
780
781 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
782 {
783         u32 val;
784         u32 i;
785
786         for (i = 0; i < 256; i++) {
787                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
788                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
789         }
790
791         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
792         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
793         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
794         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
795         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
796         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
797         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
798         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
799         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
800
801         for (i = 0; i < 960; i++) {
802                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
803                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
804         }
805 }
806
807 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
808 {
809         u32 val;
810         u32 i;
811         bool flags;
812
813         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
814         if (val & CMU_ENABLE)
815                 flags = true;
816
817         val &= ~CMU_ENABLE;
818         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
819         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
820         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
821
822         /*TODO: Sync up with frame end */
823         mdelay(20);
824
825         for (i = 0; i < 256; i++) {
826                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
827                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
828                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
829                 cmu->lut1[i] = LUT1_READ_DATA(val);
830         }
831
832         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
833         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
834         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
835         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
836         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
837         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
838         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
839         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
840         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
841
842         for (i = 0; i < 960; i++) {
843                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
844                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
845                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
846                 cmu->lut2[i] = LUT2_READ_DATA(val);
847         }
848 }
849 EXPORT_SYMBOL(tegra_dc_get_cmu);
850
851 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
852 {
853         u32 val;
854
855         if (dc->pdata->cmu_enable) {
856                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
857         } else {
858                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
859                 return 0;
860         }
861
862 #ifdef CONFIG_TEGRA_DC_CMU
863         if (cmu != &dc->cmu) {
864                 tegra_dc_cache_cmu(&dc->cmu, cmu);
865
866                 /* Disable CMU */
867                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
868                 if (val & CMU_ENABLE) {
869                         val &= ~CMU_ENABLE;
870                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
871                         val = GENERAL_UPDATE;
872                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
873                         val = GENERAL_ACT_REQ;
874                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
875                         /*TODO: Sync up with vsync */
876                         mdelay(20);
877                 }
878
879                 tegra_dc_set_cmu(dc, &dc->cmu);
880         }
881 #endif
882
883         return 0;
884 }
885
886 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
887 {
888         int ret;
889
890         mutex_lock(&dc->lock);
891         if (!dc->enabled) {
892                 mutex_unlock(&dc->lock);
893                 return 0;
894         }
895         tegra_dc_io_start(dc);
896         tegra_dc_hold_dc_out(dc);
897
898         ret = _tegra_dc_update_cmu(dc, cmu);
899         tegra_dc_set_color_control(dc);
900
901         tegra_dc_release_dc_out(dc);
902         tegra_dc_io_end(dc);
903         mutex_unlock(&dc->lock);
904
905         return ret;
906 }
907 EXPORT_SYMBOL(tegra_dc_update_cmu);
908
909 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
910 {
911         dc->pdata->cmu_enable = cmu_enable;
912         if (dc->pdata->cmu)
913                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
914         else
915                 tegra_dc_update_cmu(dc, &default_cmu);
916 }
917 #else
918 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
919 #define tegra_dc_set_cmu(dc, cmu)
920 #define tegra_dc_update_cmu(dc, cmu)
921 #endif
922
923 /* disable_irq() blocks until handler completes, calling this function while
924  * holding dc->lock can deadlock. */
925 static inline void disable_dc_irq(const struct tegra_dc *dc)
926 {
927         disable_irq(dc->irq);
928 }
929
930 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
931 {
932         return dc->syncpt[i].id;
933 }
934 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
935
936 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
937 {
938         u32 max;
939
940         mutex_lock(&dc->lock);
941         tegra_dc_io_start(dc);
942         tegra_dc_hold_dc_out(dc);
943         max = nvhost_syncpt_incr_max_ext(dc->ndev,
944                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
945         dc->syncpt[i].max = max;
946         tegra_dc_release_dc_out(dc);
947         tegra_dc_io_end(dc);
948         mutex_unlock(&dc->lock);
949
950         return max;
951 }
952
953 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
954 {
955         mutex_lock(&dc->lock);
956         if (dc->enabled) {
957                 tegra_dc_io_start(dc);
958                 tegra_dc_hold_dc_out(dc);
959                 while (dc->syncpt[i].min < val) {
960                         dc->syncpt[i].min++;
961                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
962                 }
963                 tegra_dc_release_dc_out(dc);
964                 tegra_dc_io_end(dc);
965         }
966         mutex_unlock(&dc->lock);
967 }
968
969 void
970 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
971 {
972         unsigned int ctrl;
973         unsigned long out_sel;
974         unsigned long cmd_state;
975
976         mutex_lock(&dc->lock);
977         if (!dc->enabled) {
978                 mutex_unlock(&dc->lock);
979                 return;
980         }
981
982         tegra_dc_io_start(dc);
983         tegra_dc_hold_dc_out(dc);
984
985         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
986                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
987                 cfg->clk_select);
988
989         /* The new value should be effected immediately */
990         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
991         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
992
993         switch (cfg->which_pwm) {
994         case TEGRA_PWM_PM0:
995                 /* Select the LM0 on PM0 */
996                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
997                 out_sel &= ~(7 << 0);
998                 out_sel |= (3 << 0);
999                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1000                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1001                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1002                 break;
1003         case TEGRA_PWM_PM1:
1004                 /* Select the LM1 on PM1 */
1005                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1006                 out_sel &= ~(7 << 4);
1007                 out_sel |= (3 << 4);
1008                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1009                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1010                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1011                 break;
1012         default:
1013                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1014                 break;
1015         }
1016         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1017         tegra_dc_release_dc_out(dc);
1018         tegra_dc_io_end(dc);
1019         mutex_unlock(&dc->lock);
1020 }
1021 EXPORT_SYMBOL(tegra_dc_config_pwm);
1022
1023 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1024                                 const struct tegra_dc_out_pin *pins,
1025                                 const unsigned int n_pins)
1026 {
1027         unsigned int i;
1028
1029         int name;
1030         int pol;
1031
1032         u32 pol1, pol3;
1033
1034         u32 set1, unset1;
1035         u32 set3, unset3;
1036
1037         set1 = set3 = unset1 = unset3 = 0;
1038
1039         for (i = 0; i < n_pins; i++) {
1040                 name = (pins + i)->name;
1041                 pol  = (pins + i)->pol;
1042
1043                 /* set polarity by name */
1044                 switch (name) {
1045                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1046                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1047                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1048                         else
1049                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1050                         break;
1051                 case TEGRA_DC_OUT_PIN_H_SYNC:
1052                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1053                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1054                         else
1055                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1056                         break;
1057                 case TEGRA_DC_OUT_PIN_V_SYNC:
1058                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1059                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1060                         else
1061                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1062                         break;
1063                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1064                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1065                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1066                         else
1067                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1068                         break;
1069                 default:
1070                         printk("Invalid argument in function %s\n",
1071                                __FUNCTION__);
1072                         break;
1073                 }
1074         }
1075
1076         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1077         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1078
1079         pol1 |= set1;
1080         pol1 &= ~unset1;
1081
1082         pol3 |= set3;
1083         pol3 &= ~unset3;
1084
1085         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1086         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1087 }
1088
1089 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1090 {
1091         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1092                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1093                 dc->out->type == TEGRA_DC_OUT_DSI)
1094                 return override_disp_mode[dc->out->type].pclk ?
1095                         &override_disp_mode[dc->out->type] : NULL;
1096         else
1097                 return NULL;
1098 }
1099
1100 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1101 {
1102         struct tegra_dc_mode *mode;
1103
1104         dc->out = out;
1105         mode = tegra_dc_get_override_mode(dc);
1106
1107         if (mode)
1108                 tegra_dc_set_mode(dc, mode);
1109         else if (out->n_modes > 0)
1110                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1111
1112         switch (out->type) {
1113         case TEGRA_DC_OUT_RGB:
1114                 dc->out_ops = &tegra_dc_rgb_ops;
1115                 break;
1116
1117         case TEGRA_DC_OUT_HDMI:
1118                 dc->out_ops = &tegra_dc_hdmi_ops;
1119                 break;
1120
1121         case TEGRA_DC_OUT_DSI:
1122                 dc->out_ops = &tegra_dc_dsi_ops;
1123                 break;
1124
1125         default:
1126                 dc->out_ops = NULL;
1127                 break;
1128         }
1129
1130         if (dc->out_ops && dc->out_ops->init)
1131                 dc->out_ops->init(dc);
1132 }
1133
1134 /* returns on error: -EINVAL
1135  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1136 int tegra_dc_get_out(const struct tegra_dc *dc)
1137 {
1138         if (dc && dc->out)
1139                 return dc->out->type;
1140         return -EINVAL;
1141 }
1142
1143 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1144 {
1145         if (dc->out)
1146                 return dc->out->height;
1147         else
1148                 return 0;
1149 }
1150 EXPORT_SYMBOL(tegra_dc_get_out_height);
1151
1152 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1153 {
1154         if (dc->out)
1155                 return dc->out->width;
1156         else
1157                 return 0;
1158 }
1159 EXPORT_SYMBOL(tegra_dc_get_out_width);
1160
1161 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1162 {
1163         if (dc->out && dc->out->max_pixclock)
1164                 return dc->out->max_pixclock;
1165         else
1166                 return 0;
1167 }
1168 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1169
1170 void tegra_dc_enable_crc(struct tegra_dc *dc)
1171 {
1172         u32 val;
1173
1174         mutex_lock(&dc->lock);
1175         tegra_dc_io_start(dc);
1176         tegra_dc_hold_dc_out(dc);
1177
1178         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1179                 CRC_ENABLE_ENABLE;
1180         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1181         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1182         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1183         tegra_dc_release_dc_out(dc);
1184         tegra_dc_io_end(dc);
1185         mutex_unlock(&dc->lock);
1186 }
1187
1188 void tegra_dc_disable_crc(struct tegra_dc *dc)
1189 {
1190         mutex_lock(&dc->lock);
1191         tegra_dc_io_start(dc);
1192         tegra_dc_hold_dc_out(dc);
1193         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1194         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1195         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1196
1197         tegra_dc_release_dc_out(dc);
1198         tegra_dc_io_end(dc);
1199         mutex_unlock(&dc->lock);
1200 }
1201
1202 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1203 {
1204         int crc = 0;
1205
1206         if (!dc) {
1207                 pr_err("Failed to get dc: NULL parameter.\n");
1208                 goto crc_error;
1209         }
1210
1211         if (!tegra_platform_is_linsim())
1212                 /* TODO: Replace mdelay with code to sync VBlANK, since
1213                  * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1214                 mdelay(TEGRA_CRC_LATCHED_DELAY);
1215
1216         mutex_lock(&dc->lock);
1217         tegra_dc_io_start(dc);
1218         tegra_dc_hold_dc_out(dc);
1219         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1220         tegra_dc_release_dc_out(dc);
1221         tegra_dc_io_end(dc);
1222         mutex_unlock(&dc->lock);
1223 crc_error:
1224         return crc;
1225 }
1226
1227 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1228 {
1229         u32 val;
1230
1231         if (tegra_platform_is_linsim())
1232                 return false;
1233
1234         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1235         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1236             return true;
1237
1238         return false;
1239 }
1240
1241 static inline void enable_dc_irq(const struct tegra_dc *dc)
1242 {
1243         if (tegra_platform_is_fpga())
1244                 /* Always disable DC interrupts on FPGA. */
1245                 disable_irq(dc->irq);
1246         else
1247                 enable_irq(dc->irq);
1248 }
1249
1250 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1251 {
1252         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1253                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1254 }
1255
1256 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1257 {
1258         int ret = -ENOTTY;
1259
1260         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1261                 return ret;
1262
1263         /*
1264          * Logic is as follows
1265          * a) Indicate we need a vblank.
1266          * b) Wait for completion to be signalled from isr.
1267          * c) Initialize completion for next iteration.
1268          */
1269
1270         tegra_dc_hold_dc_out(dc);
1271         dc->out->user_needs_vblank = true;
1272
1273         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1274         init_completion(&dc->out->user_vblank_comp);
1275         tegra_dc_release_dc_out(dc);
1276
1277         return ret;
1278 }
1279
1280 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1281 {
1282         /* Do the actual brightness update outside of the mutex dc->lock */
1283         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1284                 dc->out->sd_settings->bl_device_name) {
1285                 char *bl_device_name =
1286                         dc->out->sd_settings->bl_device_name;
1287                 dc->out->sd_settings->bl_device =
1288                         get_backlight_device_by_name(bl_device_name);
1289         }
1290
1291         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1292                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1293                 backlight_update_status(bl);
1294         }
1295 }
1296
1297 static void tegra_dc_vblank(struct work_struct *work)
1298 {
1299         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1300         bool nvsd_updated = false;
1301
1302         mutex_lock(&dc->lock);
1303
1304         if (!dc->enabled) {
1305                 mutex_unlock(&dc->lock);
1306                 return;
1307         }
1308
1309         tegra_dc_io_start(dc);
1310         tegra_dc_hold_dc_out(dc);
1311         /* use the new frame's bandwidth setting instead of max(current, new),
1312          * skip this if we're using tegra_dc_one_shot_worker() */
1313         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1314                 tegra_dc_program_bandwidth(dc, true);
1315
1316         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1317         if (!tegra_dc_windows_are_dirty(dc))
1318                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1319
1320         /* Update the SD brightness */
1321         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1322                 nvsd_updated = nvsd_update_brightness(dc);
1323                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1324                  * V_BLANK_NVSD bit of vblank ref-count. */
1325                 if (nvsd_updated) {
1326                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1327                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1328                 } else {
1329                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1330                 }
1331         }
1332
1333         /* Mask vblank interrupt if ref-count is zero. */
1334         if (!dc->vblank_ref_count)
1335                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1336
1337         tegra_dc_release_dc_out(dc);
1338         tegra_dc_io_end(dc);
1339         mutex_unlock(&dc->lock);
1340
1341         /* Do the actual brightness update outside of the mutex dc->lock */
1342         if (nvsd_updated)
1343                 tegra_dc_prism_update_backlight(dc);
1344 }
1345
1346 static void tegra_dc_one_shot_worker(struct work_struct *work)
1347 {
1348         struct tegra_dc *dc = container_of(
1349                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1350         mutex_lock(&dc->lock);
1351
1352         /* memory client has gone idle */
1353         tegra_dc_clear_bandwidth(dc);
1354
1355         if (dc->out_ops->idle) {
1356                 tegra_dc_io_start(dc);
1357                 dc->out_ops->idle(dc);
1358                 tegra_dc_io_end(dc);
1359         }
1360
1361         mutex_unlock(&dc->lock);
1362 }
1363
1364 /* return an arbitrarily large number if count overflow occurs.
1365  * make it a nice base-10 number to show up in stats output */
1366 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1367 {
1368         unsigned count = tegra_dc_readl(dc, reg);
1369
1370         tegra_dc_writel(dc, 0, reg);
1371         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1372 }
1373
1374 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1375 {
1376         int i;
1377
1378         dc->stats.underflows++;
1379         if (dc->underflow_mask & WIN_A_UF_INT)
1380                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1381                         DC_WINBUF_AD_UFLOW_STATUS);
1382         if (dc->underflow_mask & WIN_B_UF_INT)
1383                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1384                         DC_WINBUF_BD_UFLOW_STATUS);
1385         if (dc->underflow_mask & WIN_C_UF_INT)
1386                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1387                         DC_WINBUF_CD_UFLOW_STATUS);
1388
1389         /* Check for any underflow reset conditions */
1390         for (i = 0; i < DC_N_WINDOWS; i++) {
1391                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1392                         dc->windows[i].underflows++;
1393
1394 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1395                         if (dc->windows[i].underflows > 4) {
1396                                 schedule_work(&dc->reset_work);
1397                                 /* reset counter */
1398                                 dc->windows[i].underflows = 0;
1399                                 trace_display_reset(dc);
1400                         }
1401 #endif
1402 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1403                         if (dc->windows[i].underflows > 4) {
1404                                 trace_display_reset(dc);
1405                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1406                                                 DC_DISP_DISP_MISC_CONTROL);
1407                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1408                                                 DC_CMD_STATE_CONTROL);
1409                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1410                                                 DC_CMD_STATE_CONTROL);
1411
1412                                 tegra_dc_writel(dc, 0,
1413                                                 DC_DISP_DISP_MISC_CONTROL);
1414                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1415                                                 DC_CMD_STATE_CONTROL);
1416                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1417                                                 DC_CMD_STATE_CONTROL);
1418                         }
1419 #endif
1420                 } else {
1421                         dc->windows[i].underflows = 0;
1422                 }
1423         }
1424
1425         /* Clear the underflow mask now that we've checked it. */
1426         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1427         dc->underflow_mask = 0;
1428         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
1429         trace_underflow(dc);
1430 }
1431
1432 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1433 static void tegra_dc_vpulse2(struct work_struct *work)
1434 {
1435         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1436         bool nvsd_updated = false;
1437
1438         mutex_lock(&dc->lock);
1439
1440         if (!dc->enabled) {
1441                 mutex_unlock(&dc->lock);
1442                 return;
1443         }
1444
1445         tegra_dc_io_start(dc);
1446         tegra_dc_hold_dc_out(dc);
1447
1448         /* Clear the V_PULSE2_FLIP if no update */
1449         if (!tegra_dc_windows_are_dirty(dc))
1450                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1451
1452         /* Update the SD brightness */
1453         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1454                 nvsd_updated = nvsd_update_brightness(dc);
1455                 if (nvsd_updated) {
1456                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1457                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1458                 } else {
1459                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1460                 }
1461         }
1462
1463         /* Mask vpulse2 interrupt if ref-count is zero. */
1464         if (!dc->vpulse2_ref_count)
1465                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1466
1467         tegra_dc_release_dc_out(dc);
1468         tegra_dc_io_end(dc);
1469         mutex_unlock(&dc->lock);
1470
1471         /* Do the actual brightness update outside of the mutex dc->lock */
1472         if (nvsd_updated)
1473                 tegra_dc_prism_update_backlight(dc);
1474 }
1475 #endif
1476
1477 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1478 {
1479         /* pending user vblank, so wakeup */
1480         if ((status & (V_BLANK_INT | MSF_INT)) &&
1481             (dc->out->user_needs_vblank)) {
1482                 dc->out->user_needs_vblank = false;
1483                 complete(&dc->out->user_vblank_comp);
1484         }
1485
1486         if (status & V_BLANK_INT) {
1487                 /* Sync up windows. */
1488                 tegra_dc_trigger_windows(dc);
1489
1490                 /* Schedule any additional bottom-half vblank actvities. */
1491                 queue_work(system_freezable_wq, &dc->vblank_work);
1492         }
1493
1494         if (status & FRAME_END_INT) {
1495                 /* Mark the frame_end as complete. */
1496                 if (!completion_done(&dc->frame_end_complete))
1497                         complete(&dc->frame_end_complete);
1498         }
1499
1500 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1501         if (status & V_PULSE2_INT)
1502                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1503 #endif
1504 }
1505
1506 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1507 {
1508         /* Schedule any additional bottom-half vblank actvities. */
1509         if (status & V_BLANK_INT)
1510                 queue_work(system_freezable_wq, &dc->vblank_work);
1511
1512         if (status & FRAME_END_INT) {
1513                 struct timespec tm = CURRENT_TIME;
1514                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1515                 wake_up(&dc->timestamp_wq);
1516
1517                 /* Mark the frame_end as complete. */
1518                 if (!completion_done(&dc->frame_end_complete))
1519                         complete(&dc->frame_end_complete);
1520
1521                 tegra_dc_trigger_windows(dc);
1522         }
1523
1524 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1525         if (status & V_PULSE2_INT)
1526                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1527 #endif
1528 }
1529
1530 /* XXX: Not sure if we limit look ahead to 1 frame */
1531 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1532 {
1533         BUG_ON(!dc->frametime_ns);
1534         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1535 }
1536
1537 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1538 {
1539         BUG_ON(!dc->frametime_ns);
1540         return (((new_ts - old_ts) > dc->frametime_ns)
1541                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1542                         != div_s64((old_ts - dc->frame_end_timestamp),
1543                                 dc->frametime_ns)));
1544 }
1545
1546 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1547 {
1548         struct tegra_dc *dc = ptr;
1549         unsigned long status;
1550         unsigned long underflow_mask;
1551         u32 val;
1552         int need_disable = 0;
1553
1554         if (tegra_platform_is_fpga())
1555                 return IRQ_NONE;
1556
1557         mutex_lock(&dc->lock);
1558         if (!dc->enabled) {
1559                 mutex_unlock(&dc->lock);
1560                 return IRQ_HANDLED;
1561         }
1562
1563         clk_prepare_enable(dc->clk);
1564         tegra_dc_io_start(dc);
1565         tegra_dc_hold_dc_out(dc);
1566
1567         if (!nvhost_module_powered_ext(dc->ndev)) {
1568                 WARN(1, "IRQ when DC not powered!\n");
1569                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1570                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1571                 tegra_dc_release_dc_out(dc);
1572                 tegra_dc_io_end(dc);
1573                 clk_disable_unprepare(dc->clk);
1574                 mutex_unlock(&dc->lock);
1575                 return IRQ_HANDLED;
1576         }
1577
1578         /* clear all status flags except underflow, save those for the worker */
1579         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1580         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
1581         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1582         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
1583
1584         /*
1585          * Overlays can get thier internal state corrupted during and underflow
1586          * condition.  The only way to fix this state is to reset the DC.
1587          * if we get 4 consecutive frames with underflows, assume we're
1588          * hosed and reset.
1589          */
1590         underflow_mask = status & ALL_UF_INT();
1591
1592         /* Check underflow */
1593         if (underflow_mask) {
1594                 dc->underflow_mask |= underflow_mask;
1595                 schedule_delayed_work(&dc->underflow_work,
1596                         msecs_to_jiffies(1));
1597         }
1598
1599         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1600                 tegra_dc_one_shot_irq(dc, status);
1601         else
1602                 tegra_dc_continuous_irq(dc, status);
1603
1604         /* update video mode if it has changed since the last frame */
1605         if (status & (FRAME_END_INT | V_BLANK_INT))
1606                 if (tegra_dc_update_mode(dc))
1607                         need_disable = 1; /* force display off on error */
1608
1609         tegra_dc_release_dc_out(dc);
1610         tegra_dc_io_end(dc);
1611         clk_disable_unprepare(dc->clk);
1612         mutex_unlock(&dc->lock);
1613
1614         if (need_disable)
1615                 tegra_dc_disable(dc);
1616         return IRQ_HANDLED;
1617 }
1618
1619 void tegra_dc_set_color_control(struct tegra_dc *dc)
1620 {
1621         u32 color_control;
1622
1623         switch (dc->out->depth) {
1624         case 3:
1625                 color_control = BASE_COLOR_SIZE111;
1626                 break;
1627
1628         case 6:
1629                 color_control = BASE_COLOR_SIZE222;
1630                 break;
1631
1632         case 8:
1633                 color_control = BASE_COLOR_SIZE332;
1634                 break;
1635
1636         case 9:
1637                 color_control = BASE_COLOR_SIZE333;
1638                 break;
1639
1640         case 12:
1641                 color_control = BASE_COLOR_SIZE444;
1642                 break;
1643
1644         case 15:
1645                 color_control = BASE_COLOR_SIZE555;
1646                 break;
1647
1648         case 16:
1649                 color_control = BASE_COLOR_SIZE565;
1650                 break;
1651
1652         case 18:
1653                 color_control = BASE_COLOR_SIZE666;
1654                 break;
1655
1656         default:
1657                 color_control = BASE_COLOR_SIZE888;
1658                 break;
1659         }
1660
1661         switch (dc->out->dither) {
1662         case TEGRA_DC_DISABLE_DITHER:
1663                 color_control |= DITHER_CONTROL_DISABLE;
1664                 break;
1665         case TEGRA_DC_ORDERED_DITHER:
1666                 color_control |= DITHER_CONTROL_ORDERED;
1667                 break;
1668         case TEGRA_DC_ERRDIFF_DITHER:
1669                 /* The line buffer for error-diffusion dither is limited
1670                  * to 1280 pixels per line. This limits the maximum
1671                  * horizontal active area size to 1280 pixels when error
1672                  * diffusion is enabled.
1673                  */
1674                 BUG_ON(dc->mode.h_active > 1280);
1675                 color_control |= DITHER_CONTROL_ERRDIFF;
1676                 break;
1677         }
1678
1679 #ifdef CONFIG_TEGRA_DC_CMU
1680         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1681                 color_control |= CMU_ENABLE;
1682 #endif
1683
1684         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1685 }
1686
1687 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1688 {
1689         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1690                 return dc->win_syncpt[idx];
1691         BUG();
1692 }
1693
1694 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1695 {
1696 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1697         u32 start, end;
1698         unsigned long val;
1699
1700         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1701         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1702
1703         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1704                 dc->mode.v_back_porch + dc->mode.v_active;
1705         end = start + 1;
1706         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1707         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1708
1709         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1710         val |= V_PULSE2_INT;
1711         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1712
1713         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1714         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1715 #endif
1716 }
1717
1718 static int tegra_dc_init(struct tegra_dc *dc)
1719 {
1720         int i;
1721         int int_enable;
1722
1723         tegra_dc_io_start(dc);
1724         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1725         if (dc->ndev->id == 0) {
1726                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1727                                       TEGRA_MC_PRIO_MED);
1728                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1729                                       TEGRA_MC_PRIO_MED);
1730                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1731                                       TEGRA_MC_PRIO_MED);
1732 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1733                 /* only present on Tegra2 and 3 */
1734                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1735                                       TEGRA_MC_PRIO_MED);
1736 #endif
1737                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1738                                       TEGRA_MC_PRIO_HIGH);
1739         } else if (dc->ndev->id == 1) {
1740                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1741                                       TEGRA_MC_PRIO_MED);
1742                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1743                                       TEGRA_MC_PRIO_MED);
1744                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1745                                       TEGRA_MC_PRIO_MED);
1746 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1747                 /* only present on Tegra2 and 3 */
1748                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1749                                       TEGRA_MC_PRIO_MED);
1750 #endif
1751                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1752                                       TEGRA_MC_PRIO_HIGH);
1753         }
1754         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1755                         DC_CMD_CONT_SYNCPT_VSYNC);
1756
1757         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1758         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1759         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1760         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1761 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1762         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1763 #endif
1764         /* enable interrupts for vblank, frame_end and underflows */
1765         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
1766         /* for panels with one-shot mode enable tearing effect interrupt */
1767         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1768                 int_enable |= MSF_INT;
1769
1770         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1771         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
1772         tegra_dc_init_vpulse2_int(dc);
1773
1774         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1775
1776 #ifdef CONFIG_TEGRA_DC_CMU
1777         if (dc->pdata->cmu)
1778                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1779         else
1780                 _tegra_dc_update_cmu(dc, &default_cmu);
1781 #endif
1782         tegra_dc_set_color_control(dc);
1783         for (i = 0; i < DC_N_WINDOWS; i++) {
1784                 struct tegra_dc_win *win = &dc->windows[i];
1785                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1786                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1787                 tegra_dc_set_csc(dc, &win->csc);
1788                 tegra_dc_set_lut(dc, win);
1789                 tegra_dc_set_scaling_filter(dc);
1790         }
1791
1792 #ifdef CONFIG_TEGRA_DC_WIN_H
1793         /* Window H is set to window mode by default for t14x. */
1794         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
1795                         DC_DISP_BLEND_CURSOR_CONTROL);
1796 #endif
1797
1798         for (i = 0; i < dc->n_windows; i++) {
1799                 u32 syncpt = get_syncpt(dc, i);
1800
1801                 dc->syncpt[i].id = syncpt;
1802
1803                 dc->syncpt[i].min = dc->syncpt[i].max =
1804                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1805         }
1806
1807         trace_display_mode(dc, &dc->mode);
1808
1809         if (dc->mode.pclk) {
1810                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1811                         tegra_dc_io_end(dc);
1812                         return -EINVAL;
1813                 }
1814         }
1815
1816         /* Initialize SD AFTER the modeset.
1817            nvsd_init handles the sd_settings = NULL case. */
1818         nvsd_init(dc, dc->out->sd_settings);
1819
1820         tegra_dc_io_end(dc);
1821
1822         return 0;
1823 }
1824
1825 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1826 {
1827         int failed_init = 0;
1828
1829         tegra_dc_unpowergate_locked(dc);
1830
1831         if (dc->out->enable)
1832                 dc->out->enable(&dc->ndev->dev);
1833
1834         tegra_dc_setup_clk(dc, dc->clk);
1835         tegra_dc_clk_enable(dc);
1836         tegra_dc_io_start(dc);
1837
1838         tegra_dc_power_on(dc);
1839
1840         /* do not accept interrupts during initialization */
1841         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1842
1843         enable_dc_irq(dc);
1844
1845         failed_init = tegra_dc_init(dc);
1846         if (failed_init) {
1847                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1848                 disable_irq_nosync(dc->irq);
1849                 tegra_dc_clear_bandwidth(dc);
1850                 tegra_dc_clk_disable(dc);
1851                 if (dc->out && dc->out->disable)
1852                         dc->out->disable();
1853                 tegra_dc_io_end(dc);
1854                 return false;
1855         }
1856
1857         if (dc->out_ops && dc->out_ops->enable)
1858                 dc->out_ops->enable(dc);
1859
1860         /* force a full blending update */
1861         dc->blend.z[0] = -1;
1862
1863         tegra_dc_ext_enable(dc->ext);
1864
1865         trace_display_enable(dc);
1866
1867         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1868         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1869
1870         if (dc->out->postpoweron)
1871                 dc->out->postpoweron();
1872
1873         tegra_dc_io_end(dc);
1874         return true;
1875 }
1876
1877 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1878 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1879 {
1880         bool ret = true;
1881
1882         if (dc->out->enable)
1883                 dc->out->enable(&dc->ndev->dev);
1884
1885         tegra_dc_setup_clk(dc, dc->clk);
1886         tegra_dc_clk_enable(dc);
1887
1888         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1889                 mutex_lock(&tegra_dcs[1]->lock);
1890                 disable_irq_nosync(tegra_dcs[1]->irq);
1891         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1892                 mutex_lock(&tegra_dcs[0]->lock);
1893                 disable_irq_nosync(tegra_dcs[0]->irq);
1894         }
1895
1896         msleep(5);
1897         tegra_periph_reset_assert(dc->clk);
1898         msleep(2);
1899         if (tegra_platform_is_silicon()) {
1900                 tegra_periph_reset_deassert(dc->clk);
1901                 msleep(1);
1902         }
1903
1904         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1905                 enable_dc_irq(tegra_dcs[1]);
1906                 mutex_unlock(&tegra_dcs[1]->lock);
1907         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1908                 enable_dc_irq(tegra_dcs[0]);
1909                 mutex_unlock(&tegra_dcs[0]->lock);
1910         }
1911
1912         enable_dc_irq(dc);
1913
1914         if (tegra_dc_init(dc)) {
1915                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1916                 ret = false;
1917         }
1918
1919         if (dc->out_ops && dc->out_ops->enable)
1920                 dc->out_ops->enable(dc);
1921
1922         if (dc->out->postpoweron)
1923                 dc->out->postpoweron();
1924
1925         /* force a full blending update */
1926         dc->blend.z[0] = -1;
1927
1928         tegra_dc_ext_enable(dc->ext);
1929
1930         if (!ret) {
1931                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1932                 _tegra_dc_controller_disable(dc);
1933         }
1934
1935         trace_display_reset(dc);
1936         return ret;
1937 }
1938 #endif
1939
1940 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1941 {
1942         if (dc->mode.pclk == 0) {
1943                 switch (dc->out->type) {
1944                 case TEGRA_DC_OUT_HDMI:
1945                 /* DC enable called but no videomode is loaded.
1946                      Check if HDMI is connected, then set fallback mdoe */
1947                 if (tegra_dc_hpd(dc)) {
1948                         return tegra_dc_set_fb_mode(dc,
1949                                         &tegra_dc_hdmi_fallback_mode, 0);
1950                 } else
1951                         return false;
1952
1953                 break;
1954
1955                 /* Do nothing for other outputs for now */
1956                 case TEGRA_DC_OUT_RGB:
1957
1958                 case TEGRA_DC_OUT_DSI:
1959
1960                 default:
1961                         return false;
1962                 }
1963         }
1964
1965         return false;
1966 }
1967
1968 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1969 {
1970         return _tegra_dc_set_default_videomode(dc);
1971 }
1972
1973 static bool _tegra_dc_enable(struct tegra_dc *dc)
1974 {
1975         if (dc->mode.pclk == 0)
1976                 return false;
1977
1978         if (!dc->out)
1979                 return false;
1980
1981         if (dc->enabled)
1982                 return true;
1983
1984         pm_runtime_get_sync(&dc->ndev->dev);
1985
1986         if (!_tegra_dc_controller_enable(dc)) {
1987                 pm_runtime_put_sync(&dc->ndev->dev);
1988                 return false;
1989         }
1990
1991         return true;
1992 }
1993
1994 void tegra_dc_enable(struct tegra_dc *dc)
1995 {
1996         mutex_lock(&dc->lock);
1997
1998         if (!dc->enabled)
1999                 dc->enabled = _tegra_dc_enable(dc);
2000
2001         mutex_unlock(&dc->lock);
2002         trace_display_mode(dc, &dc->mode);
2003 }
2004
2005 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2006 {
2007         unsigned i;
2008
2009         tegra_dc_hold_dc_out(dc);
2010
2011         if (dc->out && dc->out->prepoweroff)
2012                 dc->out->prepoweroff();
2013
2014         if (dc->out_ops && dc->out_ops->disable)
2015                 dc->out_ops->disable(dc);
2016
2017         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2018
2019         disable_irq_nosync(dc->irq);
2020
2021         tegra_dc_clear_bandwidth(dc);
2022
2023         if (dc->out && dc->out->disable)
2024                 dc->out->disable();
2025
2026         for (i = 0; i < dc->n_windows; i++) {
2027                 struct tegra_dc_win *w = &dc->windows[i];
2028
2029                 /* reset window bandwidth */
2030                 w->bandwidth = 0;
2031                 w->new_bandwidth = 0;
2032
2033                 /* disable windows */
2034                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2035
2036                 /* flush any pending syncpt waits */
2037                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2038                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2039                                 dc->syncpt[i].min, dc->syncpt[i].max);
2040                         dc->syncpt[i].min++;
2041                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2042                 }
2043         }
2044         trace_display_disable(dc);
2045
2046         tegra_dc_clk_disable(dc);
2047         tegra_dc_release_dc_out(dc);
2048 }
2049
2050 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2051 {
2052 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2053         u32 val;
2054         if (dc->enabled)  {
2055                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2056                 if (enable)
2057                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2058                 else
2059                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2060                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2061         }
2062 #endif
2063 }
2064
2065 bool tegra_dc_stats_get(struct tegra_dc *dc)
2066 {
2067 #if 0 /* right now it is always enabled */
2068         u32 val;
2069         bool res;
2070
2071         if (dc->enabled)  {
2072                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2073                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2074         } else {
2075                 res = false;
2076         }
2077
2078         return res;
2079 #endif
2080         return true;
2081 }
2082
2083 /* make the screen blank by disabling all windows */
2084 void tegra_dc_blank(struct tegra_dc *dc)
2085 {
2086         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2087         unsigned i;
2088
2089         for (i = 0; i < DC_N_WINDOWS; i++) {
2090                 dcwins[i] = tegra_dc_get_window(dc, i);
2091                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2092         }
2093
2094         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2095         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2096 }
2097
2098 static void _tegra_dc_disable(struct tegra_dc *dc)
2099 {
2100         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2101                 mutex_lock(&dc->one_shot_lock);
2102                 cancel_delayed_work_sync(&dc->one_shot_work);
2103         }
2104
2105         tegra_dc_io_start(dc);
2106         _tegra_dc_controller_disable(dc);
2107         tegra_dc_io_end(dc);
2108
2109         tegra_dc_powergate_locked(dc);
2110
2111         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2112                 mutex_unlock(&dc->one_shot_lock);
2113         pm_runtime_put(&dc->ndev->dev);
2114
2115         /*
2116          * We will need to reinitialize the display the next time panel
2117          * is enabled.
2118          */
2119         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2120 }
2121
2122 void tegra_dc_disable(struct tegra_dc *dc)
2123 {
2124         tegra_dc_ext_disable(dc->ext);
2125
2126         /* it's important that new underflow work isn't scheduled before the
2127          * lock is acquired. */
2128         cancel_delayed_work_sync(&dc->underflow_work);
2129
2130         mutex_lock(&dc->lock);
2131
2132         if (dc->enabled) {
2133                 dc->enabled = false;
2134
2135                 if (!dc->suspended)
2136                         _tegra_dc_disable(dc);
2137         }
2138
2139 #ifdef CONFIG_SWITCH
2140         switch_set_state(&dc->modeset_switch, 0);
2141 #endif
2142
2143         mutex_unlock(&dc->lock);
2144         synchronize_irq(dc->irq);
2145         trace_display_mode(dc, &dc->mode);
2146 }
2147
2148 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2149 static void tegra_dc_reset_worker(struct work_struct *work)
2150 {
2151         struct tegra_dc *dc =
2152                 container_of(work, struct tegra_dc, reset_work);
2153
2154         unsigned long val = 0;
2155
2156         mutex_lock(&shared_lock);
2157
2158         dev_warn(&dc->ndev->dev,
2159                 "overlay stuck in underflow state.  resetting.\n");
2160
2161         tegra_dc_ext_disable(dc->ext);
2162
2163         mutex_lock(&dc->lock);
2164
2165         if (dc->enabled == false)
2166                 goto unlock;
2167
2168         dc->enabled = false;
2169
2170         /*
2171          * off host read bus
2172          */
2173         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2174         val &= ~(0x00000100);
2175         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2176
2177         /*
2178          * set DC to STOP mode
2179          */
2180         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2181
2182         msleep(10);
2183
2184         _tegra_dc_controller_disable(dc);
2185
2186         /* _tegra_dc_controller_reset_enable deasserts reset */
2187         _tegra_dc_controller_reset_enable(dc);
2188
2189         dc->enabled = true;
2190
2191         /* reopen host read bus */
2192         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2193         val &= ~(0x00000100);
2194         val |= 0x100;
2195         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2196
2197 unlock:
2198         mutex_unlock(&dc->lock);
2199         mutex_unlock(&shared_lock);
2200         trace_display_reset(dc);
2201 }
2202 #endif
2203
2204 static void tegra_dc_underflow_worker(struct work_struct *work)
2205 {
2206         struct tegra_dc *dc = container_of(
2207                 to_delayed_work(work), struct tegra_dc, underflow_work);
2208
2209         mutex_lock(&dc->lock);
2210         tegra_dc_io_start(dc);
2211         tegra_dc_hold_dc_out(dc);
2212
2213         if (dc->enabled) {
2214                 tegra_dc_underflow_handler(dc);
2215         }
2216         tegra_dc_release_dc_out(dc);
2217         tegra_dc_io_end(dc);
2218         mutex_unlock(&dc->lock);
2219 }
2220
2221 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2222 /* A mutex used to protect the critical section used by both DC heads. */
2223 static struct mutex tegra_dc_powergate_status_lock;
2224
2225 /* defer turning off DISA until DISB is turned off */
2226 void tegra_dc_powergate_locked(struct tegra_dc *dc)
2227 {
2228         struct tegra_dc *dc_partner;
2229
2230         mutex_lock(&tegra_dc_powergate_status_lock);
2231         /* Get the handler of the other display controller. */
2232         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2233         if (!dc_partner)
2234                 _tegra_dc_powergate_locked(dc);
2235         else if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2236                 /* If DISB is powergated, then powergate DISA. */
2237                 if (!dc_partner->powered)
2238                         _tegra_dc_powergate_locked(dc);
2239         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2240                 /* If DISA is enabled, only powergate DISB;
2241                  * otherwise, powergate DISA and DISB.
2242                  * */
2243                 if (dc_partner->enabled) {
2244                         _tegra_dc_powergate_locked(dc);
2245                 } else {
2246                         _tegra_dc_powergate_locked(dc);
2247                         _tegra_dc_powergate_locked(dc_partner);
2248                 }
2249         }
2250         mutex_unlock(&tegra_dc_powergate_status_lock);
2251 }
2252
2253
2254 /* to turn on DISB we must first power on DISA */
2255 void tegra_dc_unpowergate_locked(struct tegra_dc *dc)
2256 {
2257         mutex_lock(&tegra_dc_powergate_status_lock);
2258         if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2259                 struct tegra_dc *dc_partner;
2260
2261                 /* Get the handler of the other display controller. */
2262                 dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2263                 if (dc_partner)
2264                         _tegra_dc_unpowergate_locked(dc_partner);
2265         }
2266         _tegra_dc_unpowergate_locked(dc);
2267         mutex_unlock(&tegra_dc_powergate_status_lock);
2268 }
2269 #endif
2270
2271 #ifdef CONFIG_SWITCH
2272 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2273 {
2274         struct tegra_dc *dc =
2275                 container_of(sdev, struct tegra_dc, modeset_switch);
2276
2277         if (!sdev->state)
2278                 return sprintf(buf, "offline\n");
2279
2280         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2281 }
2282 #endif
2283
2284 static void tegra_dc_add_modes(struct tegra_dc *dc)
2285 {
2286         struct fb_monspecs specs;
2287         int i;
2288
2289         memset(&specs, 0, sizeof(specs));
2290         specs.max_x = dc->mode.h_active * 1000;
2291         specs.max_y = dc->mode.v_active * 1000;
2292         specs.modedb_len = dc->out->n_modes;
2293         specs.modedb = kzalloc(specs.modedb_len *
2294                 sizeof(struct fb_videomode), GFP_KERNEL);
2295         for (i = 0; i < dc->out->n_modes; i++)
2296                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2297                         &dc->out->modes[i]);
2298         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2299         kfree(specs.modedb);
2300 }
2301
2302 static int tegra_dc_probe(struct platform_device *ndev)
2303 {
2304         struct tegra_dc *dc;
2305         struct tegra_dc_mode *mode;
2306         struct clk *clk;
2307         struct clk *emc_clk;
2308         struct resource *res;
2309         struct resource *base_res;
2310         struct resource *fb_mem = NULL;
2311         int ret = 0;
2312         void __iomem *base;
2313         int irq;
2314         int i;
2315
2316         if (!ndev->dev.platform_data) {
2317                 dev_err(&ndev->dev, "no platform data\n");
2318                 return -ENOENT;
2319         }
2320
2321         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2322         if (!dc) {
2323                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2324                 return -ENOMEM;
2325         }
2326
2327         irq = platform_get_irq_byname(ndev, "irq");
2328         if (irq <= 0) {
2329                 dev_err(&ndev->dev, "no irq\n");
2330                 ret = -ENOENT;
2331                 goto err_free;
2332         }
2333
2334         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2335         if (!res) {
2336                 dev_err(&ndev->dev, "no mem resource\n");
2337                 ret = -ENOENT;
2338                 goto err_free;
2339         }
2340
2341         base_res = request_mem_region(res->start, resource_size(res),
2342                 ndev->name);
2343         if (!base_res) {
2344                 dev_err(&ndev->dev, "request_mem_region failed\n");
2345                 ret = -EBUSY;
2346                 goto err_free;
2347         }
2348
2349         base = ioremap(res->start, resource_size(res));
2350         if (!base) {
2351                 dev_err(&ndev->dev, "registers can't be mapped\n");
2352                 ret = -EBUSY;
2353                 goto err_release_resource_reg;
2354         }
2355         if (TEGRA_DISPLAY_BASE == res->start) {
2356                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2357                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2358                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2359                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2360 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2361                 dc->win_syncpt[3] = NVSYNCPT_DISP0_D;
2362                 dc->win_syncpt[4] = NVSYNCPT_DISP0_H;
2363 #endif
2364                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2365         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2366                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2367                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2368                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2369                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2370 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2371                 dc->win_syncpt[4] = NVSYNCPT_DISP1_H;
2372 #endif
2373                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2374         } else {
2375                 dev_err(&ndev->dev,
2376                         "Unknown base address %#08x: unable to assign syncpt\n",
2377                         res->start);
2378         }
2379
2380
2381         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2382
2383         clk = clk_get(&ndev->dev, NULL);
2384         if (IS_ERR_OR_NULL(clk)) {
2385                 dev_err(&ndev->dev, "can't get clock\n");
2386                 ret = -ENOENT;
2387                 goto err_iounmap_reg;
2388         }
2389
2390         emc_clk = clk_get(&ndev->dev, "emc");
2391         if (IS_ERR_OR_NULL(emc_clk)) {
2392                 dev_err(&ndev->dev, "can't get emc clock\n");
2393                 ret = -ENOENT;
2394                 goto err_put_clk;
2395         }
2396
2397         dc->clk = clk;
2398         dc->emc_clk = emc_clk;
2399         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2400         /* Initialize one shot work delay, it will be assigned by dsi
2401          * according to refresh rate later. */
2402         dc->one_shot_delay_ms = 40;
2403
2404         dc->base_res = base_res;
2405         dc->base = base;
2406         dc->irq = irq;
2407         dc->ndev = ndev;
2408         dc->pdata = ndev->dev.platform_data;
2409
2410         /*
2411          * The emc is a shared clock, it will be set based on
2412          * the requirements for each user on the bus.
2413          */
2414         dc->emc_clk_rate = 0;
2415
2416         mutex_init(&dc->lock);
2417         mutex_init(&dc->one_shot_lock);
2418 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2419         mutex_init(&tegra_dc_powergate_status_lock);
2420 #endif
2421         init_completion(&dc->frame_end_complete);
2422         init_waitqueue_head(&dc->wq);
2423         init_waitqueue_head(&dc->timestamp_wq);
2424 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2425         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2426 #endif
2427         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2428         dc->vblank_ref_count = 0;
2429 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2430         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2431 #endif
2432         dc->vpulse2_ref_count = 0;
2433         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2434         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2435
2436         tegra_dc_init_lut_defaults(&dc->fb_lut);
2437
2438         dc->n_windows = DC_N_WINDOWS;
2439         for (i = 0; i < dc->n_windows; i++) {
2440                 struct tegra_dc_win *win = &dc->windows[i];
2441                 win->idx = i;
2442                 win->dc = dc;
2443                 tegra_dc_init_csc_defaults(&win->csc);
2444                 tegra_dc_init_lut_defaults(&win->lut);
2445         }
2446
2447         ret = tegra_dc_set(dc, ndev->id);
2448         if (ret < 0) {
2449                 dev_err(&ndev->dev, "can't add dc\n");
2450                 goto err_put_emc_clk;
2451         }
2452
2453         platform_set_drvdata(ndev, dc);
2454
2455 #ifdef CONFIG_SWITCH
2456         dc->modeset_switch.name = dev_name(&ndev->dev);
2457         dc->modeset_switch.state = 0;
2458         dc->modeset_switch.print_state = switch_modeset_print_mode;
2459         ret = switch_dev_register(&dc->modeset_switch);
2460         if (ret < 0)
2461                 dev_err(&ndev->dev, "failed to register switch driver\n");
2462 #endif
2463
2464         tegra_dc_feature_register(dc);
2465
2466         if (dc->pdata->default_out)
2467                 tegra_dc_set_out(dc, dc->pdata->default_out);
2468         else
2469                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2470         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2471
2472         dc->ext = tegra_dc_ext_register(ndev, dc);
2473         if (IS_ERR_OR_NULL(dc->ext)) {
2474                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2475                 dc->ext = NULL;
2476         }
2477
2478         /* interrupt handler must be registered before tegra_fb_register() */
2479         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2480                         dev_name(&ndev->dev), dc)) {
2481                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2482                 ret = -EBUSY;
2483                 goto err_disable_dc;
2484         }
2485         disable_dc_irq(dc);
2486
2487         pm_runtime_use_autosuspend(&ndev->dev);
2488         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
2489         pm_runtime_enable(&ndev->dev);
2490
2491         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2492                 _tegra_dc_set_default_videomode(dc);
2493                 dc->enabled = _tegra_dc_enable(dc);
2494         }
2495
2496         tegra_dc_create_debugfs(dc);
2497
2498         dev_info(&ndev->dev, "probed\n");
2499
2500         if (dc->pdata->fb) {
2501                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2502                         unsigned long fmt;
2503                         tegra_dc_writel(dc,
2504                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2505                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2506
2507                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2508                         dc->pdata->fb->bits_per_pixel =
2509                                 tegra_dc_fmt_bpp(fmt);
2510                 }
2511
2512                 mode = tegra_dc_get_override_mode(dc);
2513                 if (mode) {
2514                         dc->pdata->fb->xres = mode->h_active;
2515                         dc->pdata->fb->yres = mode->v_active;
2516                 }
2517
2518                 tegra_dc_io_start(dc);
2519                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2520                 tegra_dc_io_end(dc);
2521                 if (IS_ERR_OR_NULL(dc->fb)) {
2522                         dc->fb = NULL;
2523                         dev_err(&ndev->dev, "failed to register fb\n");
2524                         goto err_remove_debugfs;
2525                 }
2526         }
2527
2528         if (dc->out && dc->out->n_modes)
2529                 tegra_dc_add_modes(dc);
2530
2531         if (dc->out && dc->out->hotplug_init)
2532                 dc->out->hotplug_init(&ndev->dev);
2533
2534         if (dc->out_ops && dc->out_ops->detect)
2535                 dc->out_ops->detect(dc);
2536         else
2537                 dc->connected = true;
2538
2539         /* Powergate display module when it's unconnected. */
2540         if (!tegra_dc_get_connected(dc))
2541                 tegra_dc_powergate_locked(dc);
2542
2543         tegra_dc_create_sysfs(&dc->ndev->dev);
2544
2545         return 0;
2546
2547 err_remove_debugfs:
2548         tegra_dc_remove_debugfs(dc);
2549         free_irq(irq, dc);
2550 err_disable_dc:
2551         if (dc->ext) {
2552                 tegra_dc_ext_disable(dc->ext);
2553                 tegra_dc_ext_unregister(dc->ext);
2554         }
2555         mutex_lock(&dc->lock);
2556         if (dc->enabled)
2557                 _tegra_dc_disable(dc);
2558         dc->enabled = false;
2559         mutex_unlock(&dc->lock);
2560 #ifdef CONFIG_SWITCH
2561         switch_dev_unregister(&dc->modeset_switch);
2562 #endif
2563 err_put_emc_clk:
2564         clk_put(emc_clk);
2565 err_put_clk:
2566         clk_put(clk);
2567 err_iounmap_reg:
2568         iounmap(base);
2569         if (fb_mem)
2570                 release_resource(fb_mem);
2571 err_release_resource_reg:
2572         release_resource(base_res);
2573 err_free:
2574         kfree(dc);
2575
2576         return ret;
2577 }
2578
2579 static int tegra_dc_remove(struct platform_device *ndev)
2580 {
2581         struct tegra_dc *dc = platform_get_drvdata(ndev);
2582
2583         tegra_dc_remove_sysfs(&dc->ndev->dev);
2584         tegra_dc_remove_debugfs(dc);
2585
2586         if (dc->fb) {
2587                 tegra_fb_unregister(dc->fb);
2588                 if (dc->fb_mem)
2589                         release_resource(dc->fb_mem);
2590         }
2591
2592         tegra_dc_ext_disable(dc->ext);
2593
2594         if (dc->ext)
2595                 tegra_dc_ext_unregister(dc->ext);
2596
2597         mutex_lock(&dc->lock);
2598         if (dc->enabled)
2599                 _tegra_dc_disable(dc);
2600         dc->enabled = false;
2601         mutex_unlock(&dc->lock);
2602         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2603
2604 #ifdef CONFIG_SWITCH
2605         switch_dev_unregister(&dc->modeset_switch);
2606 #endif
2607         free_irq(dc->irq, dc);
2608         clk_put(dc->emc_clk);
2609         clk_put(dc->clk);
2610         iounmap(dc->base);
2611         if (dc->fb_mem)
2612                 release_resource(dc->base_res);
2613         kfree(dc);
2614         tegra_dc_set(NULL, ndev->id);
2615
2616         return 0;
2617 }
2618
2619 #ifdef CONFIG_PM
2620 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2621 {
2622         struct tegra_dc *dc = platform_get_drvdata(ndev);
2623
2624         trace_display_suspend(dc);
2625         dev_info(&ndev->dev, "suspend\n");
2626
2627         tegra_dc_ext_disable(dc->ext);
2628
2629         mutex_lock(&dc->lock);
2630         tegra_dc_io_start(dc);
2631
2632         if (dc->out_ops && dc->out_ops->suspend)
2633                 dc->out_ops->suspend(dc);
2634
2635         if (dc->enabled) {
2636                 _tegra_dc_disable(dc);
2637
2638                 dc->suspended = true;
2639         }
2640
2641         if (dc->out && dc->out->postsuspend) {
2642                 dc->out->postsuspend();
2643                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2644                         /*
2645                          * avoid resume event due to voltage falling
2646                          */
2647                         msleep(100);
2648         }
2649
2650         tegra_dc_io_end(dc);
2651         mutex_unlock(&dc->lock);
2652         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2653
2654         return 0;
2655 }
2656
2657 static int tegra_dc_resume(struct platform_device *ndev)
2658 {
2659         struct tegra_dc *dc = platform_get_drvdata(ndev);
2660
2661         trace_display_resume(dc);
2662         dev_info(&ndev->dev, "resume\n");
2663
2664         mutex_lock(&dc->lock);
2665         dc->suspended = false;
2666
2667         /* To pan the fb on resume */
2668         tegra_fb_pan_display_reset(dc->fb);
2669
2670         if (dc->enabled) {
2671                 dc->enabled = false;
2672                 _tegra_dc_set_default_videomode(dc);
2673                 dc->enabled = _tegra_dc_enable(dc);
2674         }
2675
2676         if (dc->out && dc->out->hotplug_init)
2677                 dc->out->hotplug_init(&ndev->dev);
2678
2679         if (dc->out_ops && dc->out_ops->resume)
2680                 dc->out_ops->resume(dc);
2681         mutex_unlock(&dc->lock);
2682
2683         return 0;
2684 }
2685
2686 #endif /* CONFIG_PM */
2687
2688 static void tegra_dc_shutdown(struct platform_device *ndev)
2689 {
2690         struct tegra_dc *dc = platform_get_drvdata(ndev);
2691
2692         if (!dc || !dc->enabled)
2693                 return;
2694
2695         /* Hack: no windows blanking for simulation to save shutdown time */
2696         if (!tegra_platform_is_linsim())
2697                 tegra_dc_blank(dc);
2698         tegra_dc_disable(dc);
2699 }
2700
2701 extern int suspend_set(const char *val, struct kernel_param *kp)
2702 {
2703         if (!strcmp(val, "dump"))
2704                 dump_regs(tegra_dcs[0]);
2705 #ifdef CONFIG_PM
2706         else if (!strcmp(val, "suspend"))
2707                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2708         else if (!strcmp(val, "resume"))
2709                 tegra_dc_resume(tegra_dcs[0]->ndev);
2710 #endif
2711
2712         return 0;
2713 }
2714
2715 extern int suspend_get(char *buffer, struct kernel_param *kp)
2716 {
2717         return 0;
2718 }
2719
2720 int suspend;
2721
2722 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2723
2724 struct platform_driver tegra_dc_driver = {
2725         .driver = {
2726                 .name = "tegradc",
2727                 .owner = THIS_MODULE,
2728         },
2729         .probe = tegra_dc_probe,
2730         .remove = tegra_dc_remove,
2731 #ifdef CONFIG_PM
2732         .suspend = tegra_dc_suspend,
2733         .resume = tegra_dc_resume,
2734 #endif
2735         .shutdown = tegra_dc_shutdown,
2736 };
2737
2738 #ifndef MODULE
2739 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2740 {
2741         int i, params[11];
2742         char *p;
2743
2744         for (i = 0; i < ARRAY_SIZE(params); i++) {
2745                 if ((p = strsep(&options, ",")) != NULL) {
2746                         if (*p)
2747                                 params[i] = simple_strtoul(p, &p, 10);
2748                 } else
2749                         return -EINVAL;
2750         }
2751
2752         if ((mode->pclk = params[0]) == 0)
2753                 return -EINVAL;
2754
2755         mode->h_active      = params[1];
2756         mode->v_active      = params[2];
2757         mode->h_ref_to_sync = params[3];
2758         mode->v_ref_to_sync = params[4];
2759         mode->h_sync_width  = params[5];
2760         mode->v_sync_width  = params[6];
2761         mode->h_back_porch  = params[7];
2762         mode->v_back_porch  = params[8];
2763         mode->h_front_porch = params[9];
2764         mode->v_front_porch = params[10];
2765
2766         return 0;
2767 }
2768
2769 static int __init tegra_dc_mode_override(char *str)
2770 {
2771         char *p = str, *options;
2772
2773         if (!p || !*p)
2774                 return -EINVAL;
2775
2776         p = strstr(str, "hdmi:");
2777         if (p) {
2778                 p += 5;
2779                 options = strsep(&p, ";");
2780                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2781                         return -EINVAL;
2782         }
2783
2784         p = strstr(str, "rgb:");
2785         if (p) {
2786                 p += 4;
2787                 options = strsep(&p, ";");
2788                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2789                         return -EINVAL;
2790         }
2791
2792         p = strstr(str, "dsi:");
2793         if (p) {
2794                 p += 4;
2795                 options = strsep(&p, ";");
2796                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2797                         return -EINVAL;
2798         }
2799
2800         return 0;
2801 }
2802
2803 __setup("disp_params=", tegra_dc_mode_override);
2804 #endif
2805
2806 static int __init tegra_dc_module_init(void)
2807 {
2808         int ret = tegra_dc_ext_module_init();
2809         if (ret)
2810                 return ret;
2811         return platform_driver_register(&tegra_dc_driver);
2812 }
2813
2814 static void __exit tegra_dc_module_exit(void)
2815 {
2816         platform_driver_unregister(&tegra_dc_driver);
2817         tegra_dc_ext_module_exit();
2818 }
2819
2820 module_exit(tegra_dc_module_exit);
2821 module_init(tegra_dc_module_init);