video: tegra: dc: support either DC as the primary
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
67         .refresh = 60,
68         .xres = 640,
69         .yres = 480,
70         .pixclock = KHZ2PICOS(25200),
71         .hsync_len = 96,        /* h_sync_width */
72         .vsync_len = 2,         /* v_sync_width */
73         .left_margin = 48,      /* h_back_porch */
74         .upper_margin = 33,     /* v_back_porch */
75         .right_margin = 16,     /* h_front_porch */
76         .lower_margin = 10,     /* v_front_porch */
77         .vmode = 0,
78         .sync = 0,
79 };
80
81 static struct tegra_dc_mode override_disp_mode[3];
82
83 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
84
85 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
86
87 DEFINE_MUTEX(tegra_dc_lock);
88 DEFINE_MUTEX(shared_lock);
89
90 static const struct {
91         bool h;
92         bool v;
93 } can_filter[] = {
94         /* Window A has no filtering */
95         { false, false },
96         /* Window B has both H and V filtering */
97         { true,  true  },
98         /* Window C has only H filtering */
99         { false, true  },
100 };
101
102 #ifdef CONFIG_TEGRA_DC_CMU
103 static struct tegra_dc_cmu default_cmu = {
104         /* lut1 maps sRGB to linear space. */
105         {
106                 0,    1,    2,    4,    5,    6,    7,    9,
107                 10,   11,   12,   14,   15,   16,   18,   20,
108                 21,   23,   25,   27,   29,   31,   33,   35,
109                 37,   40,   42,   45,   48,   50,   53,   56,
110                 59,   62,   66,   69,   72,   76,   79,   83,
111                 87,   91,   95,   99,   103,  107,  112,  116,
112                 121,  126,  131,  136,  141,  146,  151,  156,
113                 162,  168,  173,  179,  185,  191,  197,  204,
114                 210,  216,  223,  230,  237,  244,  251,  258,
115                 265,  273,  280,  288,  296,  304,  312,  320,
116                 329,  337,  346,  354,  363,  372,  381,  390,
117                 400,  409,  419,  428,  438,  448,  458,  469,
118                 479,  490,  500,  511,  522,  533,  544,  555,
119                 567,  578,  590,  602,  614,  626,  639,  651,
120                 664,  676,  689,  702,  715,  728,  742,  755,
121                 769,  783,  797,  811,  825,  840,  854,  869,
122                 884,  899,  914,  929,  945,  960,  976,  992,
123                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
124                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
125                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
126                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
127                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
128                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
129                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
130                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
131                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
132                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
133                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
134                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
135                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
136                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
137                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
138         },
139         /* csc */
140         {
141                 0x100, 0x0,   0x0,
142                 0x0,   0x100, 0x0,
143                 0x0,   0x0,   0x100,
144         },
145         /* lut2 maps linear space to sRGB*/
146         {
147                 0,    1,    2,    2,    3,    4,    5,    6,
148                 6,    7,    8,    9,    10,   10,   11,   12,
149                 13,   13,   14,   15,   15,   16,   16,   17,
150                 18,   18,   19,   19,   20,   20,   21,   21,
151                 22,   22,   23,   23,   23,   24,   24,   25,
152                 25,   25,   26,   26,   27,   27,   27,   28,
153                 28,   29,   29,   29,   30,   30,   30,   31,
154                 31,   31,   32,   32,   32,   33,   33,   33,
155                 34,   34,   34,   34,   35,   35,   35,   36,
156                 36,   36,   37,   37,   37,   37,   38,   38,
157                 38,   38,   39,   39,   39,   40,   40,   40,
158                 40,   41,   41,   41,   41,   42,   42,   42,
159                 42,   43,   43,   43,   43,   43,   44,   44,
160                 44,   44,   45,   45,   45,   45,   46,   46,
161                 46,   46,   46,   47,   47,   47,   47,   48,
162                 48,   48,   48,   48,   49,   49,   49,   49,
163                 49,   50,   50,   50,   50,   50,   51,   51,
164                 51,   51,   51,   52,   52,   52,   52,   52,
165                 53,   53,   53,   53,   53,   54,   54,   54,
166                 54,   54,   55,   55,   55,   55,   55,   55,
167                 56,   56,   56,   56,   56,   57,   57,   57,
168                 57,   57,   57,   58,   58,   58,   58,   58,
169                 58,   59,   59,   59,   59,   59,   59,   60,
170                 60,   60,   60,   60,   60,   61,   61,   61,
171                 61,   61,   61,   62,   62,   62,   62,   62,
172                 62,   63,   63,   63,   63,   63,   63,   64,
173                 64,   64,   64,   64,   64,   64,   65,   65,
174                 65,   65,   65,   65,   66,   66,   66,   66,
175                 66,   66,   66,   67,   67,   67,   67,   67,
176                 67,   67,   68,   68,   68,   68,   68,   68,
177                 68,   69,   69,   69,   69,   69,   69,   69,
178                 70,   70,   70,   70,   70,   70,   70,   71,
179                 71,   71,   71,   71,   71,   71,   72,   72,
180                 72,   72,   72,   72,   72,   72,   73,   73,
181                 73,   73,   73,   73,   73,   74,   74,   74,
182                 74,   74,   74,   74,   74,   75,   75,   75,
183                 75,   75,   75,   75,   75,   76,   76,   76,
184                 76,   76,   76,   76,   77,   77,   77,   77,
185                 77,   77,   77,   77,   78,   78,   78,   78,
186                 78,   78,   78,   78,   78,   79,   79,   79,
187                 79,   79,   79,   79,   79,   80,   80,   80,
188                 80,   80,   80,   80,   80,   81,   81,   81,
189                 81,   81,   81,   81,   81,   81,   82,   82,
190                 82,   82,   82,   82,   82,   82,   83,   83,
191                 83,   83,   83,   83,   83,   83,   83,   84,
192                 84,   84,   84,   84,   84,   84,   84,   84,
193                 85,   85,   85,   85,   85,   85,   85,   85,
194                 85,   86,   86,   86,   86,   86,   86,   86,
195                 86,   86,   87,   87,   87,   87,   87,   87,
196                 87,   87,   87,   88,   88,   88,   88,   88,
197                 88,   88,   88,   88,   88,   89,   89,   89,
198                 89,   89,   89,   89,   89,   89,   90,   90,
199                 90,   90,   90,   90,   90,   90,   90,   90,
200                 91,   91,   91,   91,   91,   91,   91,   91,
201                 91,   91,   92,   92,   92,   92,   92,   92,
202                 92,   92,   92,   92,   93,   93,   93,   93,
203                 93,   93,   93,   93,   93,   93,   94,   94,
204                 94,   94,   94,   94,   94,   94,   94,   94,
205                 95,   95,   95,   95,   95,   95,   95,   95,
206                 95,   95,   96,   96,   96,   96,   96,   96,
207                 96,   96,   96,   96,   96,   97,   97,   97,
208                 97,   97,   97,   97,   97,   97,   97,   98,
209                 98,   98,   98,   98,   98,   98,   98,   98,
210                 98,   98,   99,   99,   99,   99,   99,   99,
211                 99,   100,  101,  101,  102,  103,  103,  104,
212                 105,  105,  106,  107,  107,  108,  109,  109,
213                 110,  111,  111,  112,  113,  113,  114,  115,
214                 115,  116,  116,  117,  118,  118,  119,  119,
215                 120,  120,  121,  122,  122,  123,  123,  124,
216                 124,  125,  126,  126,  127,  127,  128,  128,
217                 129,  129,  130,  130,  131,  131,  132,  132,
218                 133,  133,  134,  134,  135,  135,  136,  136,
219                 137,  137,  138,  138,  139,  139,  140,  140,
220                 141,  141,  142,  142,  143,  143,  144,  144,
221                 145,  145,  145,  146,  146,  147,  147,  148,
222                 148,  149,  149,  150,  150,  150,  151,  151,
223                 152,  152,  153,  153,  153,  154,  154,  155,
224                 155,  156,  156,  156,  157,  157,  158,  158,
225                 158,  159,  159,  160,  160,  160,  161,  161,
226                 162,  162,  162,  163,  163,  164,  164,  164,
227                 165,  165,  166,  166,  166,  167,  167,  167,
228                 168,  168,  169,  169,  169,  170,  170,  170,
229                 171,  171,  172,  172,  172,  173,  173,  173,
230                 174,  174,  174,  175,  175,  176,  176,  176,
231                 177,  177,  177,  178,  178,  178,  179,  179,
232                 179,  180,  180,  180,  181,  181,  182,  182,
233                 182,  183,  183,  183,  184,  184,  184,  185,
234                 185,  185,  186,  186,  186,  187,  187,  187,
235                 188,  188,  188,  189,  189,  189,  189,  190,
236                 190,  190,  191,  191,  191,  192,  192,  192,
237                 193,  193,  193,  194,  194,  194,  195,  195,
238                 195,  196,  196,  196,  196,  197,  197,  197,
239                 198,  198,  198,  199,  199,  199,  200,  200,
240                 200,  200,  201,  201,  201,  202,  202,  202,
241                 202,  203,  203,  203,  204,  204,  204,  205,
242                 205,  205,  205,  206,  206,  206,  207,  207,
243                 207,  207,  208,  208,  208,  209,  209,  209,
244                 209,  210,  210,  210,  211,  211,  211,  211,
245                 212,  212,  212,  213,  213,  213,  213,  214,
246                 214,  214,  214,  215,  215,  215,  216,  216,
247                 216,  216,  217,  217,  217,  217,  218,  218,
248                 218,  219,  219,  219,  219,  220,  220,  220,
249                 220,  221,  221,  221,  221,  222,  222,  222,
250                 223,  223,  223,  223,  224,  224,  224,  224,
251                 225,  225,  225,  225,  226,  226,  226,  226,
252                 227,  227,  227,  227,  228,  228,  228,  228,
253                 229,  229,  229,  229,  230,  230,  230,  230,
254                 231,  231,  231,  231,  232,  232,  232,  232,
255                 233,  233,  233,  233,  234,  234,  234,  234,
256                 235,  235,  235,  235,  236,  236,  236,  236,
257                 237,  237,  237,  237,  238,  238,  238,  238,
258                 239,  239,  239,  239,  240,  240,  240,  240,
259                 240,  241,  241,  241,  241,  242,  242,  242,
260                 242,  243,  243,  243,  243,  244,  244,  244,
261                 244,  244,  245,  245,  245,  245,  246,  246,
262                 246,  246,  247,  247,  247,  247,  247,  248,
263                 248,  248,  248,  249,  249,  249,  249,  249,
264                 250,  250,  250,  250,  251,  251,  251,  251,
265                 251,  252,  252,  252,  252,  253,  253,  253,
266                 253,  253,  254,  254,  254,  254,  255,  255,
267         },
268 };
269 #endif
270
271 void tegra_dc_clk_enable(struct tegra_dc *dc)
272 {
273         if (!tegra_is_clk_enabled(dc->clk)) {
274                 clk_prepare_enable(dc->clk);
275                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
276         }
277 }
278
279 void tegra_dc_clk_disable(struct tegra_dc *dc)
280 {
281         if (tegra_is_clk_enabled(dc->clk)) {
282                 clk_disable_unprepare(dc->clk);
283                 tegra_dvfs_set_rate(dc->clk, 0);
284         }
285 }
286
287 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
288 {
289         if (dc->out_ops->hold)
290                 dc->out_ops->hold(dc);
291 }
292
293 void tegra_dc_release_dc_out(struct tegra_dc *dc)
294 {
295         if (dc->out_ops->release)
296                 dc->out_ops->release(dc);
297 }
298
299 #define DUMP_REG(a) do {                        \
300         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
301                  #a, a, tegra_dc_readl(dc, a));               \
302         print(data, buff);                                    \
303         } while (0)
304
305 static void _dump_regs(struct tegra_dc *dc, void *data,
306                        void (* print)(void *data, const char *str))
307 {
308         int i;
309         char buff[256];
310
311         mutex_lock(&dc->lock);
312         tegra_dc_io_start(dc);
313         tegra_dc_hold_dc_out(dc);
314
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
316         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE);
318         DUMP_REG(DC_CMD_INT_STATUS);
319         DUMP_REG(DC_CMD_INT_MASK);
320         DUMP_REG(DC_CMD_INT_ENABLE);
321         DUMP_REG(DC_CMD_INT_TYPE);
322         DUMP_REG(DC_CMD_INT_POLARITY);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
326         DUMP_REG(DC_CMD_STATE_ACCESS);
327         DUMP_REG(DC_CMD_STATE_CONTROL);
328         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
329         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
330
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
332         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
333         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
335         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
336         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
337         DUMP_REG(DC_DISP_REF_TO_SYNC);
338         DUMP_REG(DC_DISP_SYNC_WIDTH);
339         DUMP_REG(DC_DISP_BACK_PORCH);
340         DUMP_REG(DC_DISP_DISP_ACTIVE);
341         DUMP_REG(DC_DISP_FRONT_PORCH);
342         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
347         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
352         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
357         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
360         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
361         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
364         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
365         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
369         DUMP_REG(DC_DISP_M0_CONTROL);
370         DUMP_REG(DC_DISP_M1_CONTROL);
371         DUMP_REG(DC_DISP_DI_CONTROL);
372         DUMP_REG(DC_DISP_PP_CONTROL);
373         DUMP_REG(DC_DISP_PP_SELECT_A);
374         DUMP_REG(DC_DISP_PP_SELECT_B);
375         DUMP_REG(DC_DISP_PP_SELECT_C);
376         DUMP_REG(DC_DISP_PP_SELECT_D);
377         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
378         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
379         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
380         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
381         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
382         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
383         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
384         DUMP_REG(DC_DISP_BORDER_COLOR);
385         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
386         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
388         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
389         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
390         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
392         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
393         DUMP_REG(DC_DISP_CURSOR_POSITION);
394         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
395         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
400         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
404 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
406 #endif
407         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
408         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
409
410
411         for (i = 0; i < 3; i++) {
412                 print(data, "\n");
413                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
414                 print(data, buff);
415
416                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
417                                 DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
419                 DUMP_REG(DC_WIN_WIN_OPTIONS);
420                 DUMP_REG(DC_WIN_BYTE_SWAP);
421                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
422                 DUMP_REG(DC_WIN_COLOR_DEPTH);
423                 DUMP_REG(DC_WIN_POSITION);
424                 DUMP_REG(DC_WIN_SIZE);
425                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
426                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
428                 DUMP_REG(DC_WIN_DDA_INCREMENT);
429                 DUMP_REG(DC_WIN_LINE_STRIDE);
430 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
431                 DUMP_REG(DC_WIN_BUF_STRIDE);
432                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
433 #endif
434                 DUMP_REG(DC_WIN_BLEND_NOKEY);
435                 DUMP_REG(DC_WIN_BLEND_1WIN);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
437                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
438                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
439                 DUMP_REG(DC_WINBUF_START_ADDR);
440                 DUMP_REG(DC_WINBUF_START_ADDR_U);
441                 DUMP_REG(DC_WINBUF_START_ADDR_V);
442                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
443                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
444                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
445                 DUMP_REG(DC_WIN_CSC_YOF);
446                 DUMP_REG(DC_WIN_CSC_KYRGB);
447                 DUMP_REG(DC_WIN_CSC_KUR);
448                 DUMP_REG(DC_WIN_CSC_KVR);
449                 DUMP_REG(DC_WIN_CSC_KUG);
450                 DUMP_REG(DC_WIN_CSC_KVG);
451                 DUMP_REG(DC_WIN_CSC_KUB);
452                 DUMP_REG(DC_WIN_CSC_KVB);
453         }
454
455         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
456         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
458         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
459         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
461         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
462         DUMP_REG(DC_DISP_M1_CONTROL);
463         DUMP_REG(DC_COM_PM1_CONTROL);
464         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
465         DUMP_REG(DC_DISP_SD_CONTROL);
466
467         tegra_dc_release_dc_out(dc);
468         tegra_dc_io_end(dc);
469         mutex_unlock(&dc->lock);
470 }
471
472 #undef DUMP_REG
473
474 #ifdef DEBUG
475 static void dump_regs_print(void *data, const char *str)
476 {
477         struct tegra_dc *dc = data;
478         dev_dbg(&dc->ndev->dev, "%s", str);
479 }
480
481 static void dump_regs(struct tegra_dc *dc)
482 {
483         _dump_regs(dc, dc, dump_regs_print);
484 }
485 #else /* !DEBUG */
486
487 static void dump_regs(struct tegra_dc *dc) {}
488
489 #endif /* DEBUG */
490
491 #ifdef CONFIG_DEBUG_FS
492
493 static void dbg_regs_print(void *data, const char *str)
494 {
495         struct seq_file *s = data;
496
497         seq_printf(s, "%s", str);
498 }
499
500 #undef DUMP_REG
501
502 static int dbg_dc_show(struct seq_file *s, void *unused)
503 {
504         struct tegra_dc *dc = s->private;
505
506         _dump_regs(dc, s, dbg_regs_print);
507
508         return 0;
509 }
510
511
512 static int dbg_dc_open(struct inode *inode, struct file *file)
513 {
514         return single_open(file, dbg_dc_show, inode->i_private);
515 }
516
517 static const struct file_operations regs_fops = {
518         .open           = dbg_dc_open,
519         .read           = seq_read,
520         .llseek         = seq_lseek,
521         .release        = single_release,
522 };
523
524 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
525 {
526         struct tegra_dc *dc = s->private;
527         struct tegra_dc_mode *m;
528
529         mutex_lock(&dc->lock);
530         m = &dc->mode;
531         seq_printf(s,
532                 "pclk: %d\n"
533                 "h_ref_to_sync: %d\n"
534                 "v_ref_to_sync: %d\n"
535                 "h_sync_width: %d\n"
536                 "v_sync_width: %d\n"
537                 "h_back_porch: %d\n"
538                 "v_back_porch: %d\n"
539                 "h_active: %d\n"
540                 "v_active: %d\n"
541                 "h_front_porch: %d\n"
542                 "v_front_porch: %d\n"
543                 "stereo_mode: %d\n",
544                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
545                 m->h_sync_width, m->v_sync_width,
546                 m->h_back_porch, m->v_back_porch,
547                 m->h_active, m->v_active,
548                 m->h_front_porch, m->v_front_porch,
549                 m->stereo_mode);
550         mutex_unlock(&dc->lock);
551         return 0;
552 }
553
554 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
555 {
556         return single_open(file, dbg_dc_mode_show, inode->i_private);
557 }
558
559 static const struct file_operations mode_fops = {
560         .open           = dbg_dc_mode_open,
561         .read           = seq_read,
562         .llseek         = seq_lseek,
563         .release        = single_release,
564 };
565
566 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
567 {
568         struct tegra_dc *dc = s->private;
569
570         mutex_lock(&dc->lock);
571         seq_printf(s,
572                 "underflows: %llu\n"
573                 "underflows_a: %llu\n"
574                 "underflows_b: %llu\n"
575                 "underflows_c: %llu\n",
576                 dc->stats.underflows,
577                 dc->stats.underflows_a,
578                 dc->stats.underflows_b,
579                 dc->stats.underflows_c);
580         mutex_unlock(&dc->lock);
581
582         return 0;
583 }
584
585 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
586 {
587         return single_open(file, dbg_dc_stats_show, inode->i_private);
588 }
589
590 static const struct file_operations stats_fops = {
591         .open           = dbg_dc_stats_open,
592         .read           = seq_read,
593         .llseek         = seq_lseek,
594         .release        = single_release,
595 };
596
597 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
598 {
599         if (dc->debugdir)
600                 debugfs_remove_recursive(dc->debugdir);
601         dc->debugdir = NULL;
602 }
603
604 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
605 {
606         struct dentry *retval;
607
608         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
609         if (!dc->debugdir)
610                 goto remove_out;
611
612         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
613                 &regs_fops);
614         if (!retval)
615                 goto remove_out;
616
617         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
618                 &mode_fops);
619         if (!retval)
620                 goto remove_out;
621
622         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
623                 &stats_fops);
624         if (!retval)
625                 goto remove_out;
626
627         return;
628 remove_out:
629         dev_err(&dc->ndev->dev, "could not create debugfs\n");
630         tegra_dc_remove_debugfs(dc);
631 }
632
633 #else /* !CONFIG_DEBUGFS */
634 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
635 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
636 #endif /* CONFIG_DEBUGFS */
637
638 static int tegra_dc_set(struct tegra_dc *dc, int index)
639 {
640         int ret = 0;
641
642         mutex_lock(&tegra_dc_lock);
643         if (index >= TEGRA_MAX_DC) {
644                 ret = -EINVAL;
645                 goto out;
646         }
647
648         if (dc != NULL && tegra_dcs[index] != NULL) {
649                 ret = -EBUSY;
650                 goto out;
651         }
652
653         tegra_dcs[index] = dc;
654
655 out:
656         mutex_unlock(&tegra_dc_lock);
657
658         return ret;
659 }
660
661 unsigned int tegra_dc_has_multiple_dc(void)
662 {
663         unsigned int idx;
664         unsigned int cnt = 0;
665         struct tegra_dc *dc;
666
667         mutex_lock(&tegra_dc_lock);
668         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
669                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
670         mutex_unlock(&tegra_dc_lock);
671
672         return (cnt > 1);
673 }
674
675 /* get the stride size of a window.
676  * return: stride size in bytes for window win. or 0 if unavailble. */
677 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
678 {
679         u32 stride;
680
681         if (!dc->enabled)
682                 return 0;
683         BUG_ON(win > DC_N_WINDOWS);
684         mutex_lock(&dc->lock);
685         tegra_dc_io_start(dc);
686         tegra_dc_hold_dc_out(dc);
687         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
688                 DC_CMD_DISPLAY_WINDOW_HEADER);
689         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
690         tegra_dc_release_dc_out(dc);
691         tegra_dc_io_end(dc);
692         mutex_unlock(&dc->lock);
693         return GET_LINE_STRIDE(stride);
694 }
695 EXPORT_SYMBOL(tegra_dc_get_stride);
696
697 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
698 {
699         if (idx < TEGRA_MAX_DC)
700                 return tegra_dcs[idx];
701         else
702                 return NULL;
703 }
704 EXPORT_SYMBOL(tegra_dc_get_dc);
705
706 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
707 {
708         if (win >= dc->n_windows)
709                 return NULL;
710
711         return &dc->windows[win];
712 }
713 EXPORT_SYMBOL(tegra_dc_get_window);
714
715 bool tegra_dc_get_connected(struct tegra_dc *dc)
716 {
717         return dc->connected;
718 }
719 EXPORT_SYMBOL(tegra_dc_get_connected);
720
721 bool tegra_dc_hpd(struct tegra_dc *dc)
722 {
723         int sense;
724         int level;
725
726         level = gpio_get_value(dc->out->hotplug_gpio);
727
728         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
729
730         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
731                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
732 }
733 EXPORT_SYMBOL(tegra_dc_hpd);
734
735 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
736 {
737         unsigned i;
738         unsigned v0 = 128;
739         unsigned v1 = 0;
740
741         /* linear horizontal and vertical filters */
742         for (i = 0; i < 16; i++) {
743                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
744                                 DC_WIN_H_FILTER_P(i));
745
746                 tegra_dc_writel(dc, v0,
747                                 DC_WIN_V_FILTER_P(i));
748                 v0 -= 8;
749                 v1 += 8;
750         }
751 }
752
753 #ifdef CONFIG_TEGRA_DC_CMU
754 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
755                                         struct tegra_dc_cmu *src_cmu)
756 {
757         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
758 }
759
760 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
761 {
762         u32 val;
763         u32 i;
764
765         for (i = 0; i < 256; i++) {
766                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
767                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
768         }
769
770         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
771         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
772         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
773         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
774         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
775         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
776         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
777         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
778         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
779
780         for (i = 0; i < 960; i++) {
781                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
782                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
783         }
784 }
785
786 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
787 {
788         u32 val;
789         u32 i;
790         bool flags;
791
792         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
793         if (val & CMU_ENABLE)
794                 flags = true;
795
796         val &= ~CMU_ENABLE;
797         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
798         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
799         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
800
801         /*TODO: Sync up with frame end */
802         mdelay(20);
803
804         for (i = 0; i < 256; i++) {
805                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
806                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
807                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
808                 cmu->lut1[i] = LUT1_READ_DATA(val);
809         }
810
811         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
812         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
813         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
814         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
815         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
816         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
817         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
818         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
819         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
820
821         for (i = 0; i < 960; i++) {
822                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
823                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
824                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
825                 cmu->lut2[i] = LUT2_READ_DATA(val);
826         }
827 }
828 EXPORT_SYMBOL(tegra_dc_get_cmu);
829
830 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
831 {
832         u32 val;
833
834         if (dc->pdata->cmu_enable) {
835                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
836         } else {
837                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
838                 return 0;
839         }
840
841         if (cmu != &dc->cmu) {
842                 tegra_dc_cache_cmu(&dc->cmu, cmu);
843
844                 /* Disable CMU */
845                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
846                 if (val & CMU_ENABLE) {
847                         val &= ~CMU_ENABLE;
848                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
849                         val = GENERAL_UPDATE;
850                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
851                         val = GENERAL_ACT_REQ;
852                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
853                         /*TODO: Sync up with vsync */
854                         mdelay(20);
855                 }
856
857                 tegra_dc_set_cmu(dc, &dc->cmu);
858         }
859
860         return 0;
861 }
862 EXPORT_SYMBOL(tegra_dc_update_cmu);
863
864 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
865 {
866         clk_enable(dc->clk);
867         tegra_dc_io_start(dc);
868         dc->pdata->cmu_enable = cmu_enable;
869         tegra_dc_update_cmu(dc, &dc->cmu);
870         tegra_dc_set_color_control(dc);
871         tegra_dc_io_end(dc);
872         clk_disable(dc->clk);
873 }
874 #else
875 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
876 #define tegra_dc_set_cmu(dc, cmu)
877 #define tegra_dc_update_cmu(dc, cmu)
878 #endif
879
880 /* disable_irq() blocks until handler completes, calling this function while
881  * holding dc->lock can deadlock. */
882 static inline void disable_dc_irq(const struct tegra_dc *dc)
883 {
884         disable_irq(dc->irq);
885 }
886
887 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
888 {
889         return dc->syncpt[i].id;
890 }
891 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
892
893 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
894 {
895         u32 max;
896
897         mutex_lock(&dc->lock);
898         tegra_dc_io_start(dc);
899         tegra_dc_hold_dc_out(dc);
900         max = nvhost_syncpt_incr_max_ext(dc->ndev,
901                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
902         dc->syncpt[i].max = max;
903         tegra_dc_release_dc_out(dc);
904         tegra_dc_io_end(dc);
905         mutex_unlock(&dc->lock);
906
907         return max;
908 }
909
910 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
911 {
912         mutex_lock(&dc->lock);
913         if (dc->enabled) {
914                 tegra_dc_io_start(dc);
915                 tegra_dc_hold_dc_out(dc);
916                 while (dc->syncpt[i].min < val) {
917                         dc->syncpt[i].min++;
918                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
919                 }
920                 tegra_dc_release_dc_out(dc);
921                 tegra_dc_io_end(dc);
922         }
923         mutex_unlock(&dc->lock);
924 }
925
926 void
927 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
928 {
929         unsigned int ctrl;
930         unsigned long out_sel;
931         unsigned long cmd_state;
932
933         mutex_lock(&dc->lock);
934         if (!dc->enabled) {
935                 mutex_unlock(&dc->lock);
936                 return;
937         }
938
939         tegra_dc_io_start(dc);
940         tegra_dc_hold_dc_out(dc);
941
942         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
943                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
944                 cfg->clk_select);
945
946         /* The new value should be effected immediately */
947         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
948         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
949
950         switch (cfg->which_pwm) {
951         case TEGRA_PWM_PM0:
952                 /* Select the LM0 on PM0 */
953                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
954                 out_sel &= ~(7 << 0);
955                 out_sel |= (3 << 0);
956                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
957                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
958                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
959                 break;
960         case TEGRA_PWM_PM1:
961                 /* Select the LM1 on PM1 */
962                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
963                 out_sel &= ~(7 << 4);
964                 out_sel |= (3 << 4);
965                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
966                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
967                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
968                 break;
969         default:
970                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
971                 break;
972         }
973         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
974         tegra_dc_release_dc_out(dc);
975         tegra_dc_io_end(dc);
976         mutex_unlock(&dc->lock);
977 }
978 EXPORT_SYMBOL(tegra_dc_config_pwm);
979
980 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
981                                 const struct tegra_dc_out_pin *pins,
982                                 const unsigned int n_pins)
983 {
984         unsigned int i;
985
986         int name;
987         int pol;
988
989         u32 pol1, pol3;
990
991         u32 set1, unset1;
992         u32 set3, unset3;
993
994         set1 = set3 = unset1 = unset3 = 0;
995
996         for (i = 0; i < n_pins; i++) {
997                 name = (pins + i)->name;
998                 pol  = (pins + i)->pol;
999
1000                 /* set polarity by name */
1001                 switch (name) {
1002                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1003                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1004                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1005                         else
1006                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1007                         break;
1008                 case TEGRA_DC_OUT_PIN_H_SYNC:
1009                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1010                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1011                         else
1012                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1013                         break;
1014                 case TEGRA_DC_OUT_PIN_V_SYNC:
1015                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1016                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1017                         else
1018                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1019                         break;
1020                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1021                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1022                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1023                         else
1024                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1025                         break;
1026                 default:
1027                         printk("Invalid argument in function %s\n",
1028                                __FUNCTION__);
1029                         break;
1030                 }
1031         }
1032
1033         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1034         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1035
1036         pol1 |= set1;
1037         pol1 &= ~unset1;
1038
1039         pol3 |= set3;
1040         pol3 &= ~unset3;
1041
1042         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1043         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1044 }
1045
1046 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1047 {
1048         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1049                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1050                 dc->out->type == TEGRA_DC_OUT_DSI)
1051                 return override_disp_mode[dc->out->type].pclk ?
1052                         &override_disp_mode[dc->out->type] : NULL;
1053         else
1054                 return NULL;
1055 }
1056
1057 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1058 {
1059         struct tegra_dc_mode *mode;
1060
1061         dc->out = out;
1062         mode = tegra_dc_get_override_mode(dc);
1063
1064         if (mode)
1065                 tegra_dc_set_mode(dc, mode);
1066         else if (out->n_modes > 0)
1067                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1068
1069         switch (out->type) {
1070         case TEGRA_DC_OUT_RGB:
1071                 dc->out_ops = &tegra_dc_rgb_ops;
1072                 break;
1073
1074         case TEGRA_DC_OUT_HDMI:
1075                 dc->out_ops = &tegra_dc_hdmi_ops;
1076                 break;
1077
1078         case TEGRA_DC_OUT_DSI:
1079                 dc->out_ops = &tegra_dc_dsi_ops;
1080                 break;
1081
1082         default:
1083                 dc->out_ops = NULL;
1084                 break;
1085         }
1086
1087         if (dc->out_ops && dc->out_ops->init)
1088                 dc->out_ops->init(dc);
1089 }
1090
1091 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1092 {
1093         if (dc->out)
1094                 return dc->out->height;
1095         else
1096                 return 0;
1097 }
1098 EXPORT_SYMBOL(tegra_dc_get_out_height);
1099
1100 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1101 {
1102         if (dc->out)
1103                 return dc->out->width;
1104         else
1105                 return 0;
1106 }
1107 EXPORT_SYMBOL(tegra_dc_get_out_width);
1108
1109 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1110 {
1111         if (dc->out && dc->out->max_pixclock)
1112                 return dc->out->max_pixclock;
1113         else
1114                 return 0;
1115 }
1116 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1117
1118 void tegra_dc_enable_crc(struct tegra_dc *dc)
1119 {
1120         u32 val;
1121
1122         mutex_lock(&dc->lock);
1123         tegra_dc_io_start(dc);
1124         tegra_dc_hold_dc_out(dc);
1125
1126         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1127                 CRC_ENABLE_ENABLE;
1128         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1129         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1130         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1131         tegra_dc_release_dc_out(dc);
1132         tegra_dc_io_end(dc);
1133         mutex_unlock(&dc->lock);
1134 }
1135
1136 void tegra_dc_disable_crc(struct tegra_dc *dc)
1137 {
1138         mutex_lock(&dc->lock);
1139         tegra_dc_io_start(dc);
1140         tegra_dc_hold_dc_out(dc);
1141         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1142         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1143         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1144
1145         tegra_dc_release_dc_out(dc);
1146         tegra_dc_io_end(dc);
1147         mutex_unlock(&dc->lock);
1148 }
1149
1150 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1151 {
1152         int crc = 0;
1153
1154         if (!dc) {
1155                 pr_err("Failed to get dc: NULL parameter.\n");
1156                 goto crc_error;
1157         }
1158
1159 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1160         /* TODO: Replace mdelay with code to sync VBlANK, since
1161          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1162         mdelay(TEGRA_CRC_LATCHED_DELAY);
1163 #endif
1164
1165         mutex_lock(&dc->lock);
1166         tegra_dc_io_start(dc);
1167         tegra_dc_hold_dc_out(dc);
1168         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1169         tegra_dc_release_dc_out(dc);
1170         tegra_dc_io_end(dc);
1171         mutex_unlock(&dc->lock);
1172 crc_error:
1173         return crc;
1174 }
1175
1176 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1177 {
1178 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1179         u32 val;
1180
1181         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1182         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1183             return true;
1184 #endif
1185         return false;
1186 }
1187
1188 static inline void enable_dc_irq(const struct tegra_dc *dc)
1189 {
1190 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1191         enable_irq(dc->irq);
1192 #else
1193         /* Always disable DC interrupts on FPGA. */
1194         disable_irq(dc->irq);
1195 #endif
1196 }
1197
1198 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1199 {
1200         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1201                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1202 }
1203
1204 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1205 {
1206         int ret = -ENOTTY;
1207
1208         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1209                 return ret;
1210
1211         /*
1212          * Logic is as follows
1213          * a) Indicate we need a vblank.
1214          * b) Wait for completion to be signalled from isr.
1215          * c) Initialize completion for next iteration.
1216          */
1217
1218         tegra_dc_hold_dc_out(dc);
1219         dc->out->user_needs_vblank = true;
1220
1221         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1222         init_completion(&dc->out->user_vblank_comp);
1223         tegra_dc_release_dc_out(dc);
1224
1225         return ret;
1226 }
1227
1228 static void tegra_dc_vblank(struct work_struct *work)
1229 {
1230         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1231         bool nvsd_updated = false;
1232
1233         mutex_lock(&dc->lock);
1234
1235         if (!dc->enabled) {
1236                 mutex_unlock(&dc->lock);
1237                 return;
1238         }
1239
1240         tegra_dc_io_start(dc);
1241         tegra_dc_hold_dc_out(dc);
1242         /* use the new frame's bandwidth setting instead of max(current, new),
1243          * skip this if we're using tegra_dc_one_shot_worker() */
1244         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1245                 tegra_dc_program_bandwidth(dc, true);
1246
1247         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1248         if (!tegra_dc_windows_are_dirty(dc))
1249                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1250
1251         /* Update the SD brightness */
1252         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1253                 nvsd_updated = nvsd_update_brightness(dc);
1254                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1255                  * V_BLANK_NVSD bit of vblank ref-count. */
1256                 if (nvsd_updated) {
1257                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1258                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1259                 } else {
1260                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1261                 }
1262         }
1263
1264         /* Mask vblank interrupt if ref-count is zero. */
1265         if (!dc->vblank_ref_count)
1266                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1267
1268         tegra_dc_release_dc_out(dc);
1269         tegra_dc_io_end(dc);
1270         mutex_unlock(&dc->lock);
1271
1272         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1273                 dc->out->sd_settings->bl_device_name) {
1274                 char *bl_device_name =
1275                         dc->out->sd_settings->bl_device_name;
1276                 dc->out->sd_settings->bl_device =
1277                         get_backlight_device_by_name(bl_device_name);
1278         }
1279
1280         /* Do the actual brightness update outside of the mutex */
1281         if (nvsd_updated && dc->out->sd_settings &&
1282             dc->out->sd_settings->bl_device) {
1283
1284                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1285                 backlight_update_status(bl);
1286         }
1287 }
1288
1289 static void tegra_dc_one_shot_worker(struct work_struct *work)
1290 {
1291         struct tegra_dc *dc = container_of(
1292                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1293         mutex_lock(&dc->lock);
1294
1295         /* memory client has gone idle */
1296         tegra_dc_clear_bandwidth(dc);
1297
1298         if (dc->out_ops->idle) {
1299                 tegra_dc_io_start(dc);
1300                 dc->out_ops->idle(dc);
1301                 tegra_dc_io_end(dc);
1302         }
1303
1304         mutex_unlock(&dc->lock);
1305 }
1306
1307 /* return an arbitrarily large number if count overflow occurs.
1308  * make it a nice base-10 number to show up in stats output */
1309 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1310 {
1311         unsigned count = tegra_dc_readl(dc, reg);
1312
1313         tegra_dc_writel(dc, 0, reg);
1314         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1315 }
1316
1317 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1318 {
1319         int i;
1320
1321         dc->stats.underflows++;
1322         if (dc->underflow_mask & WIN_A_UF_INT)
1323                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1324                         DC_WINBUF_AD_UFLOW_STATUS);
1325         if (dc->underflow_mask & WIN_B_UF_INT)
1326                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1327                         DC_WINBUF_BD_UFLOW_STATUS);
1328         if (dc->underflow_mask & WIN_C_UF_INT)
1329                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1330                         DC_WINBUF_CD_UFLOW_STATUS);
1331
1332         /* Check for any underflow reset conditions */
1333         for (i = 0; i < DC_N_WINDOWS; i++) {
1334                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1335                         dc->windows[i].underflows++;
1336
1337 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1338                         if (dc->windows[i].underflows > 4) {
1339                                 schedule_work(&dc->reset_work);
1340                                 /* reset counter */
1341                                 dc->windows[i].underflows = 0;
1342                                 trace_display_reset(dc);
1343                         }
1344 #endif
1345 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1346                         if (dc->windows[i].underflows > 4) {
1347                                 trace_display_reset(dc);
1348                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1349                                                 DC_DISP_DISP_MISC_CONTROL);
1350                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1351                                                 DC_CMD_STATE_CONTROL);
1352                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1353                                                 DC_CMD_STATE_CONTROL);
1354
1355                                 tegra_dc_writel(dc, 0,
1356                                                 DC_DISP_DISP_MISC_CONTROL);
1357                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1358                                                 DC_CMD_STATE_CONTROL);
1359                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1360                                                 DC_CMD_STATE_CONTROL);
1361                         }
1362 #endif
1363                 } else {
1364                         dc->windows[i].underflows = 0;
1365                 }
1366         }
1367
1368         /* Clear the underflow mask now that we've checked it. */
1369         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1370         dc->underflow_mask = 0;
1371         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1372         trace_underflow(dc);
1373 }
1374
1375 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1376 static void tegra_dc_vpulse2_locked(struct tegra_dc *dc)
1377 {
1378         bool nvsd_updated = false;
1379
1380         if (!dc->enabled)
1381                 return;
1382
1383         /* Clear the V_PULSE2_FLIP if no update */
1384         if (!tegra_dc_windows_are_dirty(dc))
1385                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1386
1387         /* Update the SD brightness */
1388         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1389                 nvsd_updated = nvsd_update_brightness(dc);
1390                 if (nvsd_updated) {
1391                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1392                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1393                 } else {
1394                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1395                 }
1396         }
1397
1398         /* Mask vpulse2 interrupt if ref-count is zero. */
1399         if (!dc->vpulse2_ref_count)
1400                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1401 }
1402 #endif
1403
1404 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1405 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1406 {
1407         /* pending user vblank, so wakeup */
1408         if ((status & (V_BLANK_INT | MSF_INT)) &&
1409             (dc->out->user_needs_vblank)) {
1410                 dc->out->user_needs_vblank = false;
1411                 complete(&dc->out->user_vblank_comp);
1412         }
1413
1414         if (status & V_BLANK_INT) {
1415                 /* Sync up windows. */
1416                 tegra_dc_trigger_windows(dc);
1417
1418                 /* Schedule any additional bottom-half vblank actvities. */
1419                 queue_work(system_freezable_wq, &dc->vblank_work);
1420         }
1421
1422         if (status & FRAME_END_INT) {
1423                 /* Mark the frame_end as complete. */
1424                 if (!completion_done(&dc->frame_end_complete))
1425                         complete(&dc->frame_end_complete);
1426         }
1427
1428 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1429         if (status & V_PULSE2_INT)
1430                 tegra_dc_vpulse2_locked(dc);
1431 #endif
1432 }
1433
1434 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1435 {
1436         /* Schedule any additional bottom-half vblank actvities. */
1437         if (status & V_BLANK_INT)
1438                 queue_work(system_freezable_wq, &dc->vblank_work);
1439
1440         if (status & FRAME_END_INT) {
1441                 struct timespec tm = CURRENT_TIME;
1442                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1443                 wake_up(&dc->timestamp_wq);
1444
1445                 /* Mark the frame_end as complete. */
1446                 if (!completion_done(&dc->frame_end_complete))
1447                         complete(&dc->frame_end_complete);
1448
1449                 tegra_dc_trigger_windows(dc);
1450         }
1451
1452 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1453         if (status & V_PULSE2_INT)
1454                 tegra_dc_vpulse2_locked(dc);
1455 #endif
1456 }
1457
1458 /* XXX: Not sure if we limit look ahead to 1 frame */
1459 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1460 {
1461         BUG_ON(!dc->frametime_ns);
1462         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1463 }
1464
1465 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1466 {
1467         BUG_ON(!dc->frametime_ns);
1468         return (((new_ts - old_ts) > dc->frametime_ns)
1469                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1470                         != div_s64((old_ts - dc->frame_end_timestamp),
1471                                 dc->frametime_ns)));
1472 }
1473 #endif
1474
1475 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1476 {
1477 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1478         struct tegra_dc *dc = ptr;
1479         unsigned long status;
1480         unsigned long underflow_mask;
1481         u32 val;
1482
1483         mutex_lock(&dc->lock);
1484         clk_enable(dc->clk);
1485         tegra_dc_io_start(dc);
1486         tegra_dc_hold_dc_out(dc);
1487
1488         if (!nvhost_module_powered_ext(dc->ndev)) {
1489                 WARN(1, "IRQ when DC not powered!\n");
1490                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1491                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1492                 tegra_dc_release_dc_out(dc);
1493                 tegra_dc_io_end(dc);
1494                 clk_disable(dc->clk);
1495                 mutex_unlock(&dc->lock);
1496                 return IRQ_HANDLED;
1497         }
1498
1499         /* clear all status flags except underflow, save those for the worker */
1500         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1501         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1502         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1503         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1504
1505         /*
1506          * Overlays can get thier internal state corrupted during and underflow
1507          * condition.  The only way to fix this state is to reset the DC.
1508          * if we get 4 consecutive frames with underflows, assume we're
1509          * hosed and reset.
1510          */
1511         underflow_mask = status & ALL_UF_INT;
1512
1513         /* Check underflow */
1514         if (underflow_mask) {
1515                 dc->underflow_mask |= underflow_mask;
1516                 schedule_delayed_work(&dc->underflow_work,
1517                         msecs_to_jiffies(1));
1518         }
1519
1520         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1521                 tegra_dc_one_shot_irq(dc, status);
1522         else
1523                 tegra_dc_continuous_irq(dc, status);
1524
1525         tegra_dc_release_dc_out(dc);
1526         tegra_dc_io_end(dc);
1527         clk_disable(dc->clk);
1528         mutex_unlock(&dc->lock);
1529
1530         return IRQ_HANDLED;
1531 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1532         return IRQ_NONE;
1533 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1534 }
1535
1536 void tegra_dc_set_color_control(struct tegra_dc *dc)
1537 {
1538         u32 color_control;
1539
1540         switch (dc->out->depth) {
1541         case 3:
1542                 color_control = BASE_COLOR_SIZE111;
1543                 break;
1544
1545         case 6:
1546                 color_control = BASE_COLOR_SIZE222;
1547                 break;
1548
1549         case 8:
1550                 color_control = BASE_COLOR_SIZE332;
1551                 break;
1552
1553         case 9:
1554                 color_control = BASE_COLOR_SIZE333;
1555                 break;
1556
1557         case 12:
1558                 color_control = BASE_COLOR_SIZE444;
1559                 break;
1560
1561         case 15:
1562                 color_control = BASE_COLOR_SIZE555;
1563                 break;
1564
1565         case 16:
1566                 color_control = BASE_COLOR_SIZE565;
1567                 break;
1568
1569         case 18:
1570                 color_control = BASE_COLOR_SIZE666;
1571                 break;
1572
1573         default:
1574                 color_control = BASE_COLOR_SIZE888;
1575                 break;
1576         }
1577
1578         switch (dc->out->dither) {
1579         case TEGRA_DC_DISABLE_DITHER:
1580                 color_control |= DITHER_CONTROL_DISABLE;
1581                 break;
1582         case TEGRA_DC_ORDERED_DITHER:
1583                 color_control |= DITHER_CONTROL_ORDERED;
1584                 break;
1585         case TEGRA_DC_ERRDIFF_DITHER:
1586                 /* The line buffer for error-diffusion dither is limited
1587                  * to 1280 pixels per line. This limits the maximum
1588                  * horizontal active area size to 1280 pixels when error
1589                  * diffusion is enabled.
1590                  */
1591                 BUG_ON(dc->mode.h_active > 1280);
1592                 color_control |= DITHER_CONTROL_ERRDIFF;
1593                 break;
1594         }
1595
1596 #ifdef CONFIG_TEGRA_DC_CMU
1597         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1598                 color_control |= CMU_ENABLE;
1599 #endif
1600
1601         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1602 }
1603
1604 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1605 {
1606         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1607                 return dc->win_syncpt[idx];
1608         BUG();
1609 }
1610
1611 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1612 {
1613 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1614         u32 start, end;
1615         unsigned long val;
1616
1617         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1618         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1619
1620         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1621                 dc->mode.v_back_porch + dc->mode.v_active;
1622         end = start + 1;
1623         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1624         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1625
1626         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1627         val |= V_PULSE2_INT;
1628         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1629
1630         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1631         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1632 #endif
1633 }
1634
1635 static int tegra_dc_init(struct tegra_dc *dc)
1636 {
1637         int i;
1638         int int_enable;
1639
1640         tegra_dc_io_start(dc);
1641         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1642         if (dc->ndev->id == 0) {
1643                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1644                                       TEGRA_MC_PRIO_MED);
1645                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1646                                       TEGRA_MC_PRIO_MED);
1647                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1648                                       TEGRA_MC_PRIO_MED);
1649 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1650                 /* only present on Tegra2 and 3 */
1651                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1652                                       TEGRA_MC_PRIO_MED);
1653 #endif
1654                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1655                                       TEGRA_MC_PRIO_HIGH);
1656         } else if (dc->ndev->id == 1) {
1657                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1658                                       TEGRA_MC_PRIO_MED);
1659                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1660                                       TEGRA_MC_PRIO_MED);
1661                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1662                                       TEGRA_MC_PRIO_MED);
1663 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1664                 /* only present on Tegra2 and 3 */
1665                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1666                                       TEGRA_MC_PRIO_MED);
1667 #endif
1668                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1669                                       TEGRA_MC_PRIO_HIGH);
1670         }
1671         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1672                         DC_CMD_CONT_SYNCPT_VSYNC);
1673
1674         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1675         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1676         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1677         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1678 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1679         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1680 #endif
1681         /* enable interrupts for vblank, frame_end and underflows */
1682         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1683         /* for panels with one-shot mode enable tearing effect interrupt */
1684         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1685                 int_enable |= MSF_INT;
1686
1687         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1688         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1689         tegra_dc_init_vpulse2_int(dc);
1690
1691         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1692
1693 #ifdef CONFIG_TEGRA_DC_CMU
1694         if (dc->pdata->cmu)
1695                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
1696         else
1697                 tegra_dc_update_cmu(dc, &default_cmu);
1698 #endif
1699         tegra_dc_set_color_control(dc);
1700         for (i = 0; i < DC_N_WINDOWS; i++) {
1701                 struct tegra_dc_win *win = &dc->windows[i];
1702                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1703                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1704                 tegra_dc_set_csc(dc, &win->csc);
1705                 tegra_dc_set_lut(dc, win);
1706                 tegra_dc_set_scaling_filter(dc);
1707         }
1708
1709         for (i = 0; i < dc->n_windows; i++) {
1710                 u32 syncpt = get_syncpt(dc, i);
1711
1712                 dc->syncpt[i].id = syncpt;
1713
1714                 dc->syncpt[i].min = dc->syncpt[i].max =
1715                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1716         }
1717
1718         trace_display_mode(dc, &dc->mode);
1719
1720         if (dc->mode.pclk) {
1721                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1722                         tegra_dc_io_end(dc);
1723                         return -EINVAL;
1724                 }
1725         }
1726
1727         /* Initialize SD AFTER the modeset.
1728            nvsd_init handles the sd_settings = NULL case. */
1729         nvsd_init(dc, dc->out->sd_settings);
1730
1731         tegra_dc_io_end(dc);
1732
1733         return 0;
1734 }
1735
1736 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1737 {
1738         int failed_init = 0;
1739
1740         if (dc->out->enable)
1741                 dc->out->enable(&dc->ndev->dev);
1742
1743         tegra_dc_setup_clk(dc, dc->clk);
1744         tegra_dc_clk_enable(dc);
1745         tegra_dc_io_start(dc);
1746
1747         tegra_dc_power_on(dc);
1748
1749         /* do not accept interrupts during initialization */
1750         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1751
1752         enable_dc_irq(dc);
1753
1754         failed_init = tegra_dc_init(dc);
1755         if (failed_init) {
1756                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1757                 disable_irq_nosync(dc->irq);
1758                 tegra_dc_clear_bandwidth(dc);
1759                 tegra_dc_clk_disable(dc);
1760                 if (dc->out && dc->out->disable)
1761                         dc->out->disable();
1762                 tegra_dc_io_end(dc);
1763                 return false;
1764         }
1765
1766         if (dc->out_ops && dc->out_ops->enable)
1767                 dc->out_ops->enable(dc);
1768
1769         /* force a full blending update */
1770         dc->blend.z[0] = -1;
1771
1772         tegra_dc_ext_enable(dc->ext);
1773
1774         trace_display_enable(dc);
1775
1776         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1777         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1778
1779         if (dc->out->postpoweron)
1780                 dc->out->postpoweron();
1781
1782         tegra_dc_io_end(dc);
1783         return true;
1784 }
1785
1786 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1787 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1788 {
1789         bool ret = true;
1790
1791         if (dc->out->enable)
1792                 dc->out->enable(&dc->ndev->dev);
1793
1794         tegra_dc_setup_clk(dc, dc->clk);
1795         tegra_dc_clk_enable(dc);
1796
1797         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1798                 mutex_lock(&tegra_dcs[1]->lock);
1799                 disable_irq_nosync(tegra_dcs[1]->irq);
1800         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1801                 mutex_lock(&tegra_dcs[0]->lock);
1802                 disable_irq_nosync(tegra_dcs[0]->irq);
1803         }
1804
1805         msleep(5);
1806         tegra_periph_reset_assert(dc->clk);
1807         msleep(2);
1808 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1809         tegra_periph_reset_deassert(dc->clk);
1810         msleep(1);
1811 #endif
1812
1813         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1814                 enable_dc_irq(tegra_dcs[1]);
1815                 mutex_unlock(&tegra_dcs[1]->lock);
1816         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1817                 enable_dc_irq(tegra_dcs[0]);
1818                 mutex_unlock(&tegra_dcs[0]->lock);
1819         }
1820
1821         enable_dc_irq(dc);
1822
1823         if (tegra_dc_init(dc)) {
1824                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1825                 ret = false;
1826         }
1827
1828         if (dc->out_ops && dc->out_ops->enable)
1829                 dc->out_ops->enable(dc);
1830
1831         if (dc->out->postpoweron)
1832                 dc->out->postpoweron();
1833
1834         /* force a full blending update */
1835         dc->blend.z[0] = -1;
1836
1837         tegra_dc_ext_enable(dc->ext);
1838
1839         if (!ret) {
1840                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1841                 _tegra_dc_controller_disable(dc);
1842         }
1843
1844         trace_display_reset(dc);
1845         return ret;
1846 }
1847 #endif
1848
1849 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1850 {
1851         if (dc->mode.pclk == 0) {
1852                 switch (dc->out->type) {
1853                 case TEGRA_DC_OUT_HDMI:
1854                 /* DC enable called but no videomode is loaded.
1855                      Check if HDMI is connected, then set fallback mdoe */
1856                 if (tegra_dc_hpd(dc)) {
1857                         return tegra_dc_set_fb_mode(dc,
1858                                         &tegra_dc_hdmi_fallback_mode, 0);
1859                 } else
1860                         return false;
1861
1862                 break;
1863
1864                 /* Do nothing for other outputs for now */
1865                 case TEGRA_DC_OUT_RGB:
1866
1867                 case TEGRA_DC_OUT_DSI:
1868
1869                 default:
1870                         return false;
1871                 }
1872         }
1873
1874         return false;
1875 }
1876
1877 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1878 {
1879         return _tegra_dc_set_default_videomode(dc);
1880 }
1881
1882 static bool _tegra_dc_enable(struct tegra_dc *dc)
1883 {
1884         if (dc->mode.pclk == 0)
1885                 return false;
1886
1887         if (!dc->out)
1888                 return false;
1889
1890         if (dc->enabled)
1891                 return true;
1892
1893         if (!_tegra_dc_controller_enable(dc))
1894                 return false;
1895
1896         return true;
1897 }
1898
1899 void tegra_dc_enable(struct tegra_dc *dc)
1900 {
1901         mutex_lock(&dc->lock);
1902
1903         if (!dc->enabled)
1904                 dc->enabled = _tegra_dc_enable(dc);
1905
1906         mutex_unlock(&dc->lock);
1907         trace_display_mode(dc, &dc->mode);
1908 }
1909
1910 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1911 {
1912         unsigned i;
1913
1914         tegra_dc_hold_dc_out(dc);
1915
1916         if (dc->out && dc->out->prepoweroff)
1917                 dc->out->prepoweroff();
1918
1919         if (dc->out_ops && dc->out_ops->disable)
1920                 dc->out_ops->disable(dc);
1921
1922         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1923
1924         disable_irq_nosync(dc->irq);
1925
1926         tegra_dc_clear_bandwidth(dc);
1927         if (dc->out_ops->release) /* ugly hack */
1928                 tegra_dc_release_dc_out(dc);
1929         else
1930                 tegra_dc_clk_disable(dc);
1931
1932         if (dc->out && dc->out->disable)
1933                 dc->out->disable();
1934
1935         for (i = 0; i < dc->n_windows; i++) {
1936                 struct tegra_dc_win *w = &dc->windows[i];
1937
1938                 /* reset window bandwidth */
1939                 w->bandwidth = 0;
1940                 w->new_bandwidth = 0;
1941
1942                 /* disable windows */
1943                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1944
1945                 /* flush any pending syncpt waits */
1946                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1947                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1948                                 dc->syncpt[i].min, dc->syncpt[i].max);
1949                         dc->syncpt[i].min++;
1950                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1951                 }
1952         }
1953         trace_display_disable(dc);
1954 }
1955
1956 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1957 {
1958 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1959         u32 val;
1960         if (dc->enabled)  {
1961                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1962                 if (enable)
1963                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1964                 else
1965                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1966                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1967         }
1968 #endif
1969 }
1970
1971 bool tegra_dc_stats_get(struct tegra_dc *dc)
1972 {
1973 #if 0 /* right now it is always enabled */
1974         u32 val;
1975         bool res;
1976
1977         if (dc->enabled)  {
1978                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1979                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1980         } else {
1981                 res = false;
1982         }
1983
1984         return res;
1985 #endif
1986         return true;
1987 }
1988
1989 /* make the screen blank by disabling all windows */
1990 void tegra_dc_blank(struct tegra_dc *dc)
1991 {
1992         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1993         unsigned i;
1994
1995         for (i = 0; i < DC_N_WINDOWS; i++) {
1996                 dcwins[i] = tegra_dc_get_window(dc, i);
1997                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1998         }
1999
2000         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2001         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2002 }
2003
2004 static void _tegra_dc_disable(struct tegra_dc *dc)
2005 {
2006         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2007                 mutex_lock(&dc->one_shot_lock);
2008                 cancel_delayed_work_sync(&dc->one_shot_work);
2009         }
2010
2011         tegra_dc_io_start(dc);
2012         _tegra_dc_controller_disable(dc);
2013         tegra_dc_io_end(dc);
2014
2015         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2016                 mutex_unlock(&dc->one_shot_lock);
2017 }
2018
2019 void tegra_dc_disable(struct tegra_dc *dc)
2020 {
2021         tegra_dc_ext_disable(dc->ext);
2022
2023         /* it's important that new underflow work isn't scheduled before the
2024          * lock is acquired. */
2025         cancel_delayed_work_sync(&dc->underflow_work);
2026
2027         mutex_lock(&dc->lock);
2028
2029         if (dc->enabled) {
2030                 dc->enabled = false;
2031
2032                 if (!dc->suspended)
2033                         _tegra_dc_disable(dc);
2034         }
2035
2036 #ifdef CONFIG_SWITCH
2037         switch_set_state(&dc->modeset_switch, 0);
2038 #endif
2039
2040         mutex_unlock(&dc->lock);
2041         synchronize_irq(dc->irq);
2042         trace_display_mode(dc, &dc->mode);
2043 }
2044
2045 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2046 static void tegra_dc_reset_worker(struct work_struct *work)
2047 {
2048         struct tegra_dc *dc =
2049                 container_of(work, struct tegra_dc, reset_work);
2050
2051         unsigned long val = 0;
2052
2053         mutex_lock(&shared_lock);
2054
2055         dev_warn(&dc->ndev->dev,
2056                 "overlay stuck in underflow state.  resetting.\n");
2057
2058         tegra_dc_ext_disable(dc->ext);
2059
2060         mutex_lock(&dc->lock);
2061
2062         if (dc->enabled == false)
2063                 goto unlock;
2064
2065         dc->enabled = false;
2066
2067         /*
2068          * off host read bus
2069          */
2070         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2071         val &= ~(0x00000100);
2072         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2073
2074         /*
2075          * set DC to STOP mode
2076          */
2077         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2078
2079         msleep(10);
2080
2081         _tegra_dc_controller_disable(dc);
2082
2083         /* _tegra_dc_controller_reset_enable deasserts reset */
2084         _tegra_dc_controller_reset_enable(dc);
2085
2086         dc->enabled = true;
2087
2088         /* reopen host read bus */
2089         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2090         val &= ~(0x00000100);
2091         val |= 0x100;
2092         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2093
2094 unlock:
2095         mutex_unlock(&dc->lock);
2096         mutex_unlock(&shared_lock);
2097         trace_display_reset(dc);
2098 }
2099 #endif
2100
2101 static void tegra_dc_underflow_worker(struct work_struct *work)
2102 {
2103         struct tegra_dc *dc = container_of(
2104                 to_delayed_work(work), struct tegra_dc, underflow_work);
2105
2106         mutex_lock(&dc->lock);
2107         tegra_dc_io_start(dc);
2108         tegra_dc_hold_dc_out(dc);
2109
2110         if (dc->enabled) {
2111                 tegra_dc_underflow_handler(dc);
2112         }
2113         tegra_dc_release_dc_out(dc);
2114         tegra_dc_io_end(dc);
2115         mutex_unlock(&dc->lock);
2116 }
2117
2118 #ifdef CONFIG_SWITCH
2119 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2120 {
2121         struct tegra_dc *dc =
2122                 container_of(sdev, struct tegra_dc, modeset_switch);
2123
2124         if (!sdev->state)
2125                 return sprintf(buf, "offline\n");
2126
2127         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2128 }
2129 #endif
2130
2131 static int tegra_dc_probe(struct platform_device *ndev)
2132 {
2133         struct tegra_dc *dc;
2134         struct tegra_dc_mode *mode;
2135         struct clk *clk;
2136         struct clk *emc_clk;
2137         struct resource *res;
2138         struct resource *base_res;
2139         struct resource *fb_mem = NULL;
2140         int ret = 0;
2141         void __iomem *base;
2142         int irq;
2143         int i;
2144
2145         if (!ndev->dev.platform_data) {
2146                 dev_err(&ndev->dev, "no platform data\n");
2147                 return -ENOENT;
2148         }
2149
2150         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2151         if (!dc) {
2152                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2153                 return -ENOMEM;
2154         }
2155
2156         irq = platform_get_irq_byname(ndev, "irq");
2157         if (irq <= 0) {
2158                 dev_err(&ndev->dev, "no irq\n");
2159                 ret = -ENOENT;
2160                 goto err_free;
2161         }
2162
2163         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2164         if (!res) {
2165                 dev_err(&ndev->dev, "no mem resource\n");
2166                 ret = -ENOENT;
2167                 goto err_free;
2168         }
2169
2170         base_res = request_mem_region(res->start, resource_size(res),
2171                 ndev->name);
2172         if (!base_res) {
2173                 dev_err(&ndev->dev, "request_mem_region failed\n");
2174                 ret = -EBUSY;
2175                 goto err_free;
2176         }
2177
2178         base = ioremap(res->start, resource_size(res));
2179         if (!base) {
2180                 dev_err(&ndev->dev, "registers can't be mapped\n");
2181                 ret = -EBUSY;
2182                 goto err_release_resource_reg;
2183         }
2184         if (TEGRA_DISPLAY_BASE == res->start) {
2185                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2186                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2187                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2188                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2189         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2190                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2191                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2192                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2193                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2194         } else {
2195                 dev_err(&ndev->dev,
2196                         "Unknown base address %#08x: unable to assign syncpt\n",
2197                         res->start);
2198         }
2199
2200
2201         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2202
2203         clk = clk_get(&ndev->dev, NULL);
2204         if (IS_ERR_OR_NULL(clk)) {
2205                 dev_err(&ndev->dev, "can't get clock\n");
2206                 ret = -ENOENT;
2207                 goto err_iounmap_reg;
2208         }
2209
2210         emc_clk = clk_get(&ndev->dev, "emc");
2211         if (IS_ERR_OR_NULL(emc_clk)) {
2212                 dev_err(&ndev->dev, "can't get emc clock\n");
2213                 ret = -ENOENT;
2214                 goto err_put_clk;
2215         }
2216
2217         dc->clk = clk;
2218         dc->emc_clk = emc_clk;
2219         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2220         /* Initialize one shot work delay, it will be assigned by dsi
2221          * according to refresh rate later. */
2222         dc->one_shot_delay_ms = 40;
2223
2224         dc->base_res = base_res;
2225         dc->base = base;
2226         dc->irq = irq;
2227         dc->ndev = ndev;
2228         dc->pdata = ndev->dev.platform_data;
2229
2230         /*
2231          * The emc is a shared clock, it will be set based on
2232          * the requirements for each user on the bus.
2233          */
2234         dc->emc_clk_rate = 0;
2235
2236         mutex_init(&dc->lock);
2237         mutex_init(&dc->one_shot_lock);
2238         init_completion(&dc->frame_end_complete);
2239         init_waitqueue_head(&dc->wq);
2240         init_waitqueue_head(&dc->timestamp_wq);
2241 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2242         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2243 #endif
2244         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2245         dc->vblank_ref_count = 0;
2246         dc->vpulse2_ref_count = 0;
2247         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2248         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2249
2250         tegra_dc_init_lut_defaults(&dc->fb_lut);
2251
2252         dc->n_windows = DC_N_WINDOWS;
2253         for (i = 0; i < dc->n_windows; i++) {
2254                 struct tegra_dc_win *win = &dc->windows[i];
2255                 win->idx = i;
2256                 win->dc = dc;
2257                 tegra_dc_init_csc_defaults(&win->csc);
2258                 tegra_dc_init_lut_defaults(&win->lut);
2259         }
2260
2261         ret = tegra_dc_set(dc, ndev->id);
2262         if (ret < 0) {
2263                 dev_err(&ndev->dev, "can't add dc\n");
2264                 goto err_free_irq;
2265         }
2266
2267         platform_set_drvdata(ndev, dc);
2268
2269 #ifdef CONFIG_SWITCH
2270         dc->modeset_switch.name = dev_name(&ndev->dev);
2271         dc->modeset_switch.state = 0;
2272         dc->modeset_switch.print_state = switch_modeset_print_mode;
2273         ret = switch_dev_register(&dc->modeset_switch);
2274         if (ret < 0)
2275                 dev_err(&ndev->dev, "failed to register switch driver\n");
2276 #endif
2277
2278         tegra_dc_feature_register(dc);
2279
2280         if (dc->pdata->default_out)
2281                 tegra_dc_set_out(dc, dc->pdata->default_out);
2282         else
2283                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2284
2285         dc->ext = tegra_dc_ext_register(ndev, dc);
2286         if (IS_ERR_OR_NULL(dc->ext)) {
2287                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2288                 dc->ext = NULL;
2289         }
2290
2291         /* interrupt handler must be registered before tegra_fb_register() */
2292         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2293                         dev_name(&ndev->dev), dc)) {
2294                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2295                 ret = -EBUSY;
2296                 goto err_put_emc_clk;
2297         }
2298         disable_dc_irq(dc);
2299
2300         mutex_lock(&dc->lock);
2301         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2302                 _tegra_dc_set_default_videomode(dc);
2303                 dc->enabled = _tegra_dc_enable(dc);
2304         }
2305         mutex_unlock(&dc->lock);
2306
2307         mutex_lock(&dc->lock);
2308         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2309                 _tegra_dc_set_default_videomode(dc);
2310                 dc->enabled = _tegra_dc_enable(dc);
2311         }
2312         mutex_unlock(&dc->lock);
2313
2314         tegra_dc_create_debugfs(dc);
2315
2316         dev_info(&ndev->dev, "probed\n");
2317
2318         if (dc->pdata->fb) {
2319                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2320                         unsigned long fmt;
2321                         tegra_dc_writel(dc,
2322                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2323                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2324
2325                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2326                         dc->pdata->fb->bits_per_pixel =
2327                                 tegra_dc_fmt_bpp(fmt);
2328                 }
2329
2330                 mode = tegra_dc_get_override_mode(dc);
2331                 if (mode) {
2332                         dc->pdata->fb->xres = mode->h_active;
2333                         dc->pdata->fb->yres = mode->v_active;
2334                 }
2335
2336                 tegra_dc_io_start(dc);
2337                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2338                 if (IS_ERR_OR_NULL(dc->fb))
2339                         dc->fb = NULL;
2340                 tegra_dc_io_end(dc);
2341         }
2342
2343         if (dc->out && dc->out->hotplug_init)
2344                 dc->out->hotplug_init(&ndev->dev);
2345
2346         if (dc->out_ops && dc->out_ops->detect)
2347                 dc->out_ops->detect(dc);
2348         else
2349                 dc->connected = true;
2350
2351         tegra_dc_create_sysfs(&dc->ndev->dev);
2352
2353         return 0;
2354
2355 err_free_irq:
2356         free_irq(irq, dc);
2357 err_put_emc_clk:
2358         clk_put(emc_clk);
2359 err_put_clk:
2360         clk_put(clk);
2361 err_iounmap_reg:
2362         iounmap(base);
2363         if (fb_mem)
2364                 release_resource(fb_mem);
2365 err_release_resource_reg:
2366         release_resource(base_res);
2367 err_free:
2368         kfree(dc);
2369
2370         return ret;
2371 }
2372
2373 static int tegra_dc_remove(struct platform_device *ndev)
2374 {
2375         struct tegra_dc *dc = platform_get_drvdata(ndev);
2376
2377         tegra_dc_remove_sysfs(&dc->ndev->dev);
2378         tegra_dc_remove_debugfs(dc);
2379
2380         if (dc->fb) {
2381                 tegra_fb_unregister(dc->fb);
2382                 if (dc->fb_mem)
2383                         release_resource(dc->fb_mem);
2384         }
2385
2386         tegra_dc_ext_disable(dc->ext);
2387
2388         if (dc->ext)
2389                 tegra_dc_ext_unregister(dc->ext);
2390
2391         mutex_lock(&dc->lock);
2392         if (dc->enabled)
2393                 _tegra_dc_disable(dc);
2394         dc->enabled = false;
2395         mutex_unlock(&dc->lock);
2396         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2397
2398 #ifdef CONFIG_SWITCH
2399         switch_dev_unregister(&dc->modeset_switch);
2400 #endif
2401         free_irq(dc->irq, dc);
2402         clk_put(dc->emc_clk);
2403         clk_put(dc->clk);
2404         iounmap(dc->base);
2405         if (dc->fb_mem)
2406                 release_resource(dc->base_res);
2407         kfree(dc);
2408         tegra_dc_set(NULL, ndev->id);
2409
2410         return 0;
2411 }
2412
2413 #ifdef CONFIG_PM
2414 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2415 {
2416         struct tegra_dc *dc = platform_get_drvdata(ndev);
2417
2418         trace_display_suspend(dc);
2419         dev_info(&ndev->dev, "suspend\n");
2420
2421         tegra_dc_ext_disable(dc->ext);
2422
2423         mutex_lock(&dc->lock);
2424         tegra_dc_io_start(dc);
2425
2426         if (dc->out_ops && dc->out_ops->suspend)
2427                 dc->out_ops->suspend(dc);
2428
2429         if (dc->enabled) {
2430                 _tegra_dc_disable(dc);
2431
2432                 dc->suspended = true;
2433         }
2434
2435         if (dc->out && dc->out->postsuspend) {
2436                 dc->out->postsuspend();
2437                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2438                         /*
2439                          * avoid resume event due to voltage falling
2440                          */
2441                         msleep(100);
2442         }
2443
2444         tegra_dc_io_end(dc);
2445         mutex_unlock(&dc->lock);
2446         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2447
2448         return 0;
2449 }
2450
2451 static int tegra_dc_resume(struct platform_device *ndev)
2452 {
2453         struct tegra_dc *dc = platform_get_drvdata(ndev);
2454
2455         trace_display_resume(dc);
2456         dev_info(&ndev->dev, "resume\n");
2457
2458         mutex_lock(&dc->lock);
2459         dc->suspended = false;
2460
2461         if (dc->enabled) {
2462                 dc->enabled = false;
2463                 _tegra_dc_set_default_videomode(dc);
2464                 dc->enabled = _tegra_dc_enable(dc);
2465         }
2466
2467         if (dc->out && dc->out->hotplug_init)
2468                 dc->out->hotplug_init(&ndev->dev);
2469
2470         if (dc->out_ops && dc->out_ops->resume)
2471                 dc->out_ops->resume(dc);
2472         mutex_unlock(&dc->lock);
2473
2474         return 0;
2475 }
2476
2477 #endif /* CONFIG_PM */
2478
2479 static void tegra_dc_shutdown(struct platform_device *ndev)
2480 {
2481         struct tegra_dc *dc = platform_get_drvdata(ndev);
2482
2483         if (!dc || !dc->enabled)
2484                 return;
2485
2486         tegra_dc_blank(dc);
2487         tegra_dc_disable(dc);
2488 }
2489
2490 extern int suspend_set(const char *val, struct kernel_param *kp)
2491 {
2492         if (!strcmp(val, "dump"))
2493                 dump_regs(tegra_dcs[0]);
2494 #ifdef CONFIG_PM
2495         else if (!strcmp(val, "suspend"))
2496                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2497         else if (!strcmp(val, "resume"))
2498                 tegra_dc_resume(tegra_dcs[0]->ndev);
2499 #endif
2500
2501         return 0;
2502 }
2503
2504 extern int suspend_get(char *buffer, struct kernel_param *kp)
2505 {
2506         return 0;
2507 }
2508
2509 int suspend;
2510
2511 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2512
2513 struct platform_driver tegra_dc_driver = {
2514         .driver = {
2515                 .name = "tegradc",
2516                 .owner = THIS_MODULE,
2517         },
2518         .probe = tegra_dc_probe,
2519         .remove = tegra_dc_remove,
2520 #ifdef CONFIG_PM
2521         .suspend = tegra_dc_suspend,
2522         .resume = tegra_dc_resume,
2523 #endif
2524         .shutdown = tegra_dc_shutdown,
2525 };
2526
2527 #ifndef MODULE
2528 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2529 {
2530         int i, params[11];
2531         char *p;
2532
2533         for (i = 0; i < ARRAY_SIZE(params); i++) {
2534                 if ((p = strsep(&options, ",")) != NULL) {
2535                         if (*p)
2536                                 params[i] = simple_strtoul(p, &p, 10);
2537                 } else
2538                         return -EINVAL;
2539         }
2540
2541         if ((mode->pclk = params[0]) == 0)
2542                 return -EINVAL;
2543
2544         mode->h_active      = params[1];
2545         mode->v_active      = params[2];
2546         mode->h_ref_to_sync = params[3];
2547         mode->v_ref_to_sync = params[4];
2548         mode->h_sync_width  = params[5];
2549         mode->v_sync_width  = params[6];
2550         mode->h_back_porch  = params[7];
2551         mode->v_back_porch  = params[8];
2552         mode->h_front_porch = params[9];
2553         mode->v_front_porch = params[10];
2554
2555         return 0;
2556 }
2557
2558 static int __init tegra_dc_mode_override(char *str)
2559 {
2560         char *p = str, *options;
2561
2562         if (!p || !*p)
2563                 return -EINVAL;
2564
2565         p = strstr(str, "hdmi:");
2566         if (p) {
2567                 p += 5;
2568                 options = strsep(&p, ";");
2569                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2570                         return -EINVAL;
2571         }
2572
2573         p = strstr(str, "rgb:");
2574         if (p) {
2575                 p += 4;
2576                 options = strsep(&p, ";");
2577                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2578                         return -EINVAL;
2579         }
2580
2581         p = strstr(str, "dsi:");
2582         if (p) {
2583                 p += 4;
2584                 options = strsep(&p, ";");
2585                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2586                         return -EINVAL;
2587         }
2588
2589         return 0;
2590 }
2591
2592 __setup("disp_params=", tegra_dc_mode_override);
2593 #endif
2594
2595 static int __init tegra_dc_module_init(void)
2596 {
2597         int ret = tegra_dc_ext_module_init();
2598         if (ret)
2599                 return ret;
2600         return platform_driver_register(&tegra_dc_driver);
2601 }
2602
2603 static void __exit tegra_dc_module_exit(void)
2604 {
2605         platform_driver_unregister(&tegra_dc_driver);
2606         tegra_dc_ext_module_exit();
2607 }
2608
2609 module_exit(tegra_dc_module_exit);
2610 module_init(tegra_dc_module_init);