video: tegra: dc: moving to clk prepare APIs
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53
54 #include "dc_reg.h"
55 #include "dc_config.h"
56 #include "dc_priv.h"
57 #include "dev.h"
58 #include "nvsd.h"
59
60 #define TEGRA_CRC_LATCHED_DELAY         34
61
62 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
63 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
64
65 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
66         .refresh = 60,
67         .xres = 640,
68         .yres = 480,
69         .pixclock = KHZ2PICOS(25200),
70         .hsync_len = 96,        /* h_sync_width */
71         .vsync_len = 2,         /* v_sync_width */
72         .left_margin = 48,      /* h_back_porch */
73         .upper_margin = 33,     /* v_back_porch */
74         .right_margin = 16,     /* h_front_porch */
75         .lower_margin = 10,     /* v_front_porch */
76         .vmode = 0,
77         .sync = 0,
78 };
79
80 static struct tegra_dc_mode override_disp_mode[3];
81
82 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
83
84 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
85
86 DEFINE_MUTEX(tegra_dc_lock);
87 DEFINE_MUTEX(shared_lock);
88
89 static const struct {
90         bool h;
91         bool v;
92 } can_filter[] = {
93         /* Window A has no filtering */
94         { false, false },
95         /* Window B has both H and V filtering */
96         { true,  true  },
97         /* Window C has only H filtering */
98         { false, true  },
99 };
100
101 #ifdef CONFIG_TEGRA_DC_CMU
102 static struct tegra_dc_cmu default_cmu = {
103         /* lut1 maps sRGB to linear space. */
104         {
105                 0,    1,    2,    4,    5,    6,    7,    9,
106                 10,   11,   12,   14,   15,   16,   18,   20,
107                 21,   23,   25,   27,   29,   31,   33,   35,
108                 37,   40,   42,   45,   48,   50,   53,   56,
109                 59,   62,   66,   69,   72,   76,   79,   83,
110                 87,   91,   95,   99,   103,  107,  112,  116,
111                 121,  126,  131,  136,  141,  146,  151,  156,
112                 162,  168,  173,  179,  185,  191,  197,  204,
113                 210,  216,  223,  230,  237,  244,  251,  258,
114                 265,  273,  280,  288,  296,  304,  312,  320,
115                 329,  337,  346,  354,  363,  372,  381,  390,
116                 400,  409,  419,  428,  438,  448,  458,  469,
117                 479,  490,  500,  511,  522,  533,  544,  555,
118                 567,  578,  590,  602,  614,  626,  639,  651,
119                 664,  676,  689,  702,  715,  728,  742,  755,
120                 769,  783,  797,  811,  825,  840,  854,  869,
121                 884,  899,  914,  929,  945,  960,  976,  992,
122                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
123                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
124                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
125                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
126                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
127                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
128                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
129                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
130                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
131                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
132                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
133                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
134                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
135                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
136                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
137         },
138         /* csc */
139         {
140                 0x100, 0x0,   0x0,
141                 0x0,   0x100, 0x0,
142                 0x0,   0x0,   0x100,
143         },
144         /* lut2 maps linear space to sRGB*/
145         {
146                 0,    1,    2,    2,    3,    4,    5,    6,
147                 6,    7,    8,    9,    10,   10,   11,   12,
148                 13,   13,   14,   15,   15,   16,   16,   17,
149                 18,   18,   19,   19,   20,   20,   21,   21,
150                 22,   22,   23,   23,   23,   24,   24,   25,
151                 25,   25,   26,   26,   27,   27,   27,   28,
152                 28,   29,   29,   29,   30,   30,   30,   31,
153                 31,   31,   32,   32,   32,   33,   33,   33,
154                 34,   34,   34,   34,   35,   35,   35,   36,
155                 36,   36,   37,   37,   37,   37,   38,   38,
156                 38,   38,   39,   39,   39,   40,   40,   40,
157                 40,   41,   41,   41,   41,   42,   42,   42,
158                 42,   43,   43,   43,   43,   43,   44,   44,
159                 44,   44,   45,   45,   45,   45,   46,   46,
160                 46,   46,   46,   47,   47,   47,   47,   48,
161                 48,   48,   48,   48,   49,   49,   49,   49,
162                 49,   50,   50,   50,   50,   50,   51,   51,
163                 51,   51,   51,   52,   52,   52,   52,   52,
164                 53,   53,   53,   53,   53,   54,   54,   54,
165                 54,   54,   55,   55,   55,   55,   55,   55,
166                 56,   56,   56,   56,   56,   57,   57,   57,
167                 57,   57,   57,   58,   58,   58,   58,   58,
168                 58,   59,   59,   59,   59,   59,   59,   60,
169                 60,   60,   60,   60,   60,   61,   61,   61,
170                 61,   61,   61,   62,   62,   62,   62,   62,
171                 62,   63,   63,   63,   63,   63,   63,   64,
172                 64,   64,   64,   64,   64,   64,   65,   65,
173                 65,   65,   65,   65,   66,   66,   66,   66,
174                 66,   66,   66,   67,   67,   67,   67,   67,
175                 67,   67,   68,   68,   68,   68,   68,   68,
176                 68,   69,   69,   69,   69,   69,   69,   69,
177                 70,   70,   70,   70,   70,   70,   70,   71,
178                 71,   71,   71,   71,   71,   71,   72,   72,
179                 72,   72,   72,   72,   72,   72,   73,   73,
180                 73,   73,   73,   73,   73,   74,   74,   74,
181                 74,   74,   74,   74,   74,   75,   75,   75,
182                 75,   75,   75,   75,   75,   76,   76,   76,
183                 76,   76,   76,   76,   77,   77,   77,   77,
184                 77,   77,   77,   77,   78,   78,   78,   78,
185                 78,   78,   78,   78,   78,   79,   79,   79,
186                 79,   79,   79,   79,   79,   80,   80,   80,
187                 80,   80,   80,   80,   80,   81,   81,   81,
188                 81,   81,   81,   81,   81,   81,   82,   82,
189                 82,   82,   82,   82,   82,   82,   83,   83,
190                 83,   83,   83,   83,   83,   83,   83,   84,
191                 84,   84,   84,   84,   84,   84,   84,   84,
192                 85,   85,   85,   85,   85,   85,   85,   85,
193                 85,   86,   86,   86,   86,   86,   86,   86,
194                 86,   86,   87,   87,   87,   87,   87,   87,
195                 87,   87,   87,   88,   88,   88,   88,   88,
196                 88,   88,   88,   88,   88,   89,   89,   89,
197                 89,   89,   89,   89,   89,   89,   90,   90,
198                 90,   90,   90,   90,   90,   90,   90,   90,
199                 91,   91,   91,   91,   91,   91,   91,   91,
200                 91,   91,   92,   92,   92,   92,   92,   92,
201                 92,   92,   92,   92,   93,   93,   93,   93,
202                 93,   93,   93,   93,   93,   93,   94,   94,
203                 94,   94,   94,   94,   94,   94,   94,   94,
204                 95,   95,   95,   95,   95,   95,   95,   95,
205                 95,   95,   96,   96,   96,   96,   96,   96,
206                 96,   96,   96,   96,   96,   97,   97,   97,
207                 97,   97,   97,   97,   97,   97,   97,   98,
208                 98,   98,   98,   98,   98,   98,   98,   98,
209                 98,   98,   99,   99,   99,   99,   99,   99,
210                 99,   100,  101,  101,  102,  103,  103,  104,
211                 105,  105,  106,  107,  107,  108,  109,  109,
212                 110,  111,  111,  112,  113,  113,  114,  115,
213                 115,  116,  116,  117,  118,  118,  119,  119,
214                 120,  120,  121,  122,  122,  123,  123,  124,
215                 124,  125,  126,  126,  127,  127,  128,  128,
216                 129,  129,  130,  130,  131,  131,  132,  132,
217                 133,  133,  134,  134,  135,  135,  136,  136,
218                 137,  137,  138,  138,  139,  139,  140,  140,
219                 141,  141,  142,  142,  143,  143,  144,  144,
220                 145,  145,  145,  146,  146,  147,  147,  148,
221                 148,  149,  149,  150,  150,  150,  151,  151,
222                 152,  152,  153,  153,  153,  154,  154,  155,
223                 155,  156,  156,  156,  157,  157,  158,  158,
224                 158,  159,  159,  160,  160,  160,  161,  161,
225                 162,  162,  162,  163,  163,  164,  164,  164,
226                 165,  165,  166,  166,  166,  167,  167,  167,
227                 168,  168,  169,  169,  169,  170,  170,  170,
228                 171,  171,  172,  172,  172,  173,  173,  173,
229                 174,  174,  174,  175,  175,  176,  176,  176,
230                 177,  177,  177,  178,  178,  178,  179,  179,
231                 179,  180,  180,  180,  181,  181,  182,  182,
232                 182,  183,  183,  183,  184,  184,  184,  185,
233                 185,  185,  186,  186,  186,  187,  187,  187,
234                 188,  188,  188,  189,  189,  189,  189,  190,
235                 190,  190,  191,  191,  191,  192,  192,  192,
236                 193,  193,  193,  194,  194,  194,  195,  195,
237                 195,  196,  196,  196,  196,  197,  197,  197,
238                 198,  198,  198,  199,  199,  199,  200,  200,
239                 200,  200,  201,  201,  201,  202,  202,  202,
240                 202,  203,  203,  203,  204,  204,  204,  205,
241                 205,  205,  205,  206,  206,  206,  207,  207,
242                 207,  207,  208,  208,  208,  209,  209,  209,
243                 209,  210,  210,  210,  211,  211,  211,  211,
244                 212,  212,  212,  213,  213,  213,  213,  214,
245                 214,  214,  214,  215,  215,  215,  216,  216,
246                 216,  216,  217,  217,  217,  217,  218,  218,
247                 218,  219,  219,  219,  219,  220,  220,  220,
248                 220,  221,  221,  221,  221,  222,  222,  222,
249                 223,  223,  223,  223,  224,  224,  224,  224,
250                 225,  225,  225,  225,  226,  226,  226,  226,
251                 227,  227,  227,  227,  228,  228,  228,  228,
252                 229,  229,  229,  229,  230,  230,  230,  230,
253                 231,  231,  231,  231,  232,  232,  232,  232,
254                 233,  233,  233,  233,  234,  234,  234,  234,
255                 235,  235,  235,  235,  236,  236,  236,  236,
256                 237,  237,  237,  237,  238,  238,  238,  238,
257                 239,  239,  239,  239,  240,  240,  240,  240,
258                 240,  241,  241,  241,  241,  242,  242,  242,
259                 242,  243,  243,  243,  243,  244,  244,  244,
260                 244,  244,  245,  245,  245,  245,  246,  246,
261                 246,  246,  247,  247,  247,  247,  247,  248,
262                 248,  248,  248,  249,  249,  249,  249,  249,
263                 250,  250,  250,  250,  251,  251,  251,  251,
264                 251,  252,  252,  252,  252,  253,  253,  253,
265                 253,  253,  254,  254,  254,  254,  255,  255,
266         },
267 };
268 #endif
269
270 void tegra_dc_clk_enable(struct tegra_dc *dc)
271 {
272         if (!tegra_is_clk_enabled(dc->clk)) {
273                 clk_prepare_enable(dc->clk);
274                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
275         }
276 }
277
278 void tegra_dc_clk_disable(struct tegra_dc *dc)
279 {
280         if (tegra_is_clk_enabled(dc->clk)) {
281                 clk_disable_unprepare(dc->clk);
282                 tegra_dvfs_set_rate(dc->clk, 0);
283         }
284 }
285
286 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
287 {
288         if (dc->out_ops->hold)
289                 dc->out_ops->hold(dc);
290 }
291
292 void tegra_dc_release_dc_out(struct tegra_dc *dc)
293 {
294         if (dc->out_ops->release)
295                 dc->out_ops->release(dc);
296 }
297
298 #define DUMP_REG(a) do {                        \
299         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
300                  #a, a, tegra_dc_readl(dc, a));               \
301         print(data, buff);                                    \
302         } while (0)
303
304 static void _dump_regs(struct tegra_dc *dc, void *data,
305                        void (* print)(void *data, const char *str))
306 {
307         int i;
308         char buff[256];
309
310         mutex_lock(&dc->lock);
311         tegra_dc_hold_dc_out(dc);
312         tegra_dc_io_start(dc);
313
314         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE);
317         DUMP_REG(DC_CMD_INT_STATUS);
318         DUMP_REG(DC_CMD_INT_MASK);
319         DUMP_REG(DC_CMD_INT_ENABLE);
320         DUMP_REG(DC_CMD_INT_TYPE);
321         DUMP_REG(DC_CMD_INT_POLARITY);
322         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
325         DUMP_REG(DC_CMD_STATE_ACCESS);
326         DUMP_REG(DC_CMD_STATE_CONTROL);
327         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
328         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
329
330         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
332         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
333         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
335         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
336         DUMP_REG(DC_DISP_REF_TO_SYNC);
337         DUMP_REG(DC_DISP_SYNC_WIDTH);
338         DUMP_REG(DC_DISP_BACK_PORCH);
339         DUMP_REG(DC_DISP_DISP_ACTIVE);
340         DUMP_REG(DC_DISP_FRONT_PORCH);
341         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
342         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
346         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
347         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
351         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
352         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
356         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
357         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
360         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
367         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
368         DUMP_REG(DC_DISP_M0_CONTROL);
369         DUMP_REG(DC_DISP_M1_CONTROL);
370         DUMP_REG(DC_DISP_DI_CONTROL);
371         DUMP_REG(DC_DISP_PP_CONTROL);
372         DUMP_REG(DC_DISP_PP_SELECT_A);
373         DUMP_REG(DC_DISP_PP_SELECT_B);
374         DUMP_REG(DC_DISP_PP_SELECT_C);
375         DUMP_REG(DC_DISP_PP_SELECT_D);
376         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
377         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
378         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
379         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
380         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
381         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
382         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
383         DUMP_REG(DC_DISP_BORDER_COLOR);
384         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
385         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
386         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
388         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
389         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
390         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
392         DUMP_REG(DC_DISP_CURSOR_POSITION);
393         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
394         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
395         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
399         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
400         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
403 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
405 #endif
406         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
407         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
408
409
410         for (i = 0; i < 3; i++) {
411                 print(data, "\n");
412                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
413                 print(data, buff);
414
415                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
416                                 DC_CMD_DISPLAY_WINDOW_HEADER);
417                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_WIN_WIN_OPTIONS);
419                 DUMP_REG(DC_WIN_BYTE_SWAP);
420                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
421                 DUMP_REG(DC_WIN_COLOR_DEPTH);
422                 DUMP_REG(DC_WIN_POSITION);
423                 DUMP_REG(DC_WIN_SIZE);
424                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
425                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
426                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_DDA_INCREMENT);
428                 DUMP_REG(DC_WIN_LINE_STRIDE);
429 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
430                 DUMP_REG(DC_WIN_BUF_STRIDE);
431                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
432 #endif
433                 DUMP_REG(DC_WIN_BLEND_NOKEY);
434                 DUMP_REG(DC_WIN_BLEND_1WIN);
435                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
437                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
438                 DUMP_REG(DC_WINBUF_START_ADDR);
439                 DUMP_REG(DC_WINBUF_START_ADDR_U);
440                 DUMP_REG(DC_WINBUF_START_ADDR_V);
441                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
442                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
443                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
444                 DUMP_REG(DC_WIN_CSC_YOF);
445                 DUMP_REG(DC_WIN_CSC_KYRGB);
446                 DUMP_REG(DC_WIN_CSC_KUR);
447                 DUMP_REG(DC_WIN_CSC_KVR);
448                 DUMP_REG(DC_WIN_CSC_KUG);
449                 DUMP_REG(DC_WIN_CSC_KVG);
450                 DUMP_REG(DC_WIN_CSC_KUB);
451                 DUMP_REG(DC_WIN_CSC_KVB);
452         }
453
454         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
455         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
456         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
458         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
459         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
460         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
461         DUMP_REG(DC_DISP_M1_CONTROL);
462         DUMP_REG(DC_COM_PM1_CONTROL);
463         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
464         DUMP_REG(DC_DISP_SD_CONTROL);
465
466         tegra_dc_io_end(dc);
467         tegra_dc_release_dc_out(dc);
468         mutex_unlock(&dc->lock);
469 }
470
471 #undef DUMP_REG
472
473 #ifdef DEBUG
474 static void dump_regs_print(void *data, const char *str)
475 {
476         struct tegra_dc *dc = data;
477         dev_dbg(&dc->ndev->dev, "%s", str);
478 }
479
480 static void dump_regs(struct tegra_dc *dc)
481 {
482         _dump_regs(dc, dc, dump_regs_print);
483 }
484 #else /* !DEBUG */
485
486 static void dump_regs(struct tegra_dc *dc) {}
487
488 #endif /* DEBUG */
489
490 #ifdef CONFIG_DEBUG_FS
491
492 static void dbg_regs_print(void *data, const char *str)
493 {
494         struct seq_file *s = data;
495
496         seq_printf(s, "%s", str);
497 }
498
499 #undef DUMP_REG
500
501 static int dbg_dc_show(struct seq_file *s, void *unused)
502 {
503         struct tegra_dc *dc = s->private;
504
505         _dump_regs(dc, s, dbg_regs_print);
506
507         return 0;
508 }
509
510
511 static int dbg_dc_open(struct inode *inode, struct file *file)
512 {
513         return single_open(file, dbg_dc_show, inode->i_private);
514 }
515
516 static const struct file_operations regs_fops = {
517         .open           = dbg_dc_open,
518         .read           = seq_read,
519         .llseek         = seq_lseek,
520         .release        = single_release,
521 };
522
523 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
524 {
525         struct tegra_dc *dc = s->private;
526         struct tegra_dc_mode *m;
527
528         mutex_lock(&dc->lock);
529         m = &dc->mode;
530         seq_printf(s,
531                 "pclk: %d\n"
532                 "h_ref_to_sync: %d\n"
533                 "v_ref_to_sync: %d\n"
534                 "h_sync_width: %d\n"
535                 "v_sync_width: %d\n"
536                 "h_back_porch: %d\n"
537                 "v_back_porch: %d\n"
538                 "h_active: %d\n"
539                 "v_active: %d\n"
540                 "h_front_porch: %d\n"
541                 "v_front_porch: %d\n"
542                 "stereo_mode: %d\n",
543                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
544                 m->h_sync_width, m->v_sync_width,
545                 m->h_back_porch, m->v_back_porch,
546                 m->h_active, m->v_active,
547                 m->h_front_porch, m->v_front_porch,
548                 m->stereo_mode);
549         mutex_unlock(&dc->lock);
550         return 0;
551 }
552
553 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
554 {
555         return single_open(file, dbg_dc_mode_show, inode->i_private);
556 }
557
558 static const struct file_operations mode_fops = {
559         .open           = dbg_dc_mode_open,
560         .read           = seq_read,
561         .llseek         = seq_lseek,
562         .release        = single_release,
563 };
564
565 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
566 {
567         struct tegra_dc *dc = s->private;
568
569         mutex_lock(&dc->lock);
570         seq_printf(s,
571                 "underflows: %llu\n"
572                 "underflows_a: %llu\n"
573                 "underflows_b: %llu\n"
574                 "underflows_c: %llu\n",
575                 dc->stats.underflows,
576                 dc->stats.underflows_a,
577                 dc->stats.underflows_b,
578                 dc->stats.underflows_c);
579         mutex_unlock(&dc->lock);
580
581         return 0;
582 }
583
584 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
585 {
586         return single_open(file, dbg_dc_stats_show, inode->i_private);
587 }
588
589 static const struct file_operations stats_fops = {
590         .open           = dbg_dc_stats_open,
591         .read           = seq_read,
592         .llseek         = seq_lseek,
593         .release        = single_release,
594 };
595
596 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
597 {
598         if (dc->debugdir)
599                 debugfs_remove_recursive(dc->debugdir);
600         dc->debugdir = NULL;
601 }
602
603 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
604 {
605         struct dentry *retval;
606
607         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
608         if (!dc->debugdir)
609                 goto remove_out;
610
611         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
612                 &regs_fops);
613         if (!retval)
614                 goto remove_out;
615
616         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
617                 &mode_fops);
618         if (!retval)
619                 goto remove_out;
620
621         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
622                 &stats_fops);
623         if (!retval)
624                 goto remove_out;
625
626         return;
627 remove_out:
628         dev_err(&dc->ndev->dev, "could not create debugfs\n");
629         tegra_dc_remove_debugfs(dc);
630 }
631
632 #else /* !CONFIG_DEBUGFS */
633 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
634 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
635 #endif /* CONFIG_DEBUGFS */
636
637 static int tegra_dc_set(struct tegra_dc *dc, int index)
638 {
639         int ret = 0;
640
641         mutex_lock(&tegra_dc_lock);
642         if (index >= TEGRA_MAX_DC) {
643                 ret = -EINVAL;
644                 goto out;
645         }
646
647         if (dc != NULL && tegra_dcs[index] != NULL) {
648                 ret = -EBUSY;
649                 goto out;
650         }
651
652         tegra_dcs[index] = dc;
653
654 out:
655         mutex_unlock(&tegra_dc_lock);
656
657         return ret;
658 }
659
660 unsigned int tegra_dc_has_multiple_dc(void)
661 {
662         unsigned int idx;
663         unsigned int cnt = 0;
664         struct tegra_dc *dc;
665
666         mutex_lock(&tegra_dc_lock);
667         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
668                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
669         mutex_unlock(&tegra_dc_lock);
670
671         return (cnt > 1);
672 }
673
674 /* get the stride size of a window.
675  * return: stride size in bytes for window win. or 0 if unavailble. */
676 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
677 {
678         u32 stride;
679
680         if (!dc->enabled)
681                 return 0;
682         BUG_ON(win > DC_N_WINDOWS);
683         mutex_lock(&dc->lock);
684         tegra_dc_hold_dc_out(dc);
685         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
686                 DC_CMD_DISPLAY_WINDOW_HEADER);
687         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
688         tegra_dc_release_dc_out(dc);
689         mutex_unlock(&dc->lock);
690         return GET_LINE_STRIDE(stride);
691 }
692 EXPORT_SYMBOL(tegra_dc_get_stride);
693
694 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
695 {
696         if (idx < TEGRA_MAX_DC)
697                 return tegra_dcs[idx];
698         else
699                 return NULL;
700 }
701 EXPORT_SYMBOL(tegra_dc_get_dc);
702
703 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
704 {
705         if (win >= dc->n_windows)
706                 return NULL;
707
708         return &dc->windows[win];
709 }
710 EXPORT_SYMBOL(tegra_dc_get_window);
711
712 bool tegra_dc_get_connected(struct tegra_dc *dc)
713 {
714         return dc->connected;
715 }
716 EXPORT_SYMBOL(tegra_dc_get_connected);
717
718 bool tegra_dc_hpd(struct tegra_dc *dc)
719 {
720         int sense;
721         int level;
722
723         level = gpio_get_value(dc->out->hotplug_gpio);
724
725         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
726
727         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
728                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
729 }
730 EXPORT_SYMBOL(tegra_dc_hpd);
731
732 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
733 {
734         unsigned i;
735         unsigned v0 = 128;
736         unsigned v1 = 0;
737         /* linear horizontal and vertical filters */
738         for (i = 0; i < 16; i++) {
739                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
740                                 DC_WIN_H_FILTER_P(i));
741
742                 tegra_dc_writel(dc, v0,
743                                 DC_WIN_V_FILTER_P(i));
744                 v0 -= 8;
745                 v1 += 8;
746         }
747 }
748
749 #ifdef CONFIG_TEGRA_DC_CMU
750 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
751                                         struct tegra_dc_cmu *src_cmu)
752 {
753         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
754 }
755
756 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
757 {
758         u32 val;
759         u32 i;
760
761         for (i = 0; i < 256; i++) {
762                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
763                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
764         }
765
766         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
767         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
768         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
769         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
770         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
771         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
772         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
773         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
774         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
775
776         for (i = 0; i < 960; i++) {
777                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
778                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
779         }
780 }
781
782 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
783 {
784         u32 val;
785         u32 i;
786         bool flags;
787
788         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
789         if (val & CMU_ENABLE)
790                 flags = true;
791
792         val &= ~CMU_ENABLE;
793         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
794         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
795         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
796
797         /*TODO: Sync up with frame end */
798         mdelay(20);
799
800         for (i = 0; i < 256; i++) {
801                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
802                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
803                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
804                 cmu->lut1[i] = LUT1_READ_DATA(val);
805         }
806
807         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
808         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
809         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
810         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
811         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
812         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
813         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
814         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
815         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
816
817         for (i = 0; i < 960; i++) {
818                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
819                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
820                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
821                 cmu->lut2[i] = LUT2_READ_DATA(val);
822         }
823 }
824 EXPORT_SYMBOL(tegra_dc_get_cmu);
825
826 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
827 {
828         u32 val;
829
830         if (dc->pdata->cmu_enable) {
831                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
832         } else {
833                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
834                 return 0;
835         }
836
837         if (cmu != &dc->cmu) {
838                 tegra_dc_cache_cmu(&dc->cmu, cmu);
839
840                 /* Disable CMU */
841                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
842                 if (val & CMU_ENABLE) {
843                         val &= ~CMU_ENABLE;
844                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
845                         val = GENERAL_UPDATE;
846                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
847                         val = GENERAL_ACT_REQ;
848                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
849                         /*TODO: Sync up with vsync */
850                         mdelay(20);
851                 }
852
853                 tegra_dc_set_cmu(dc, &dc->cmu);
854         }
855
856         return 0;
857 }
858 EXPORT_SYMBOL(tegra_dc_update_cmu);
859
860 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
861 {
862         dc->pdata->cmu_enable = cmu_enable;
863         tegra_dc_update_cmu(dc, &dc->cmu);
864         tegra_dc_set_color_control(dc);
865 }
866 #else
867 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
868 #define tegra_dc_set_cmu(dc, cmu)
869 #define tegra_dc_update_cmu(dc, cmu)
870 #endif
871
872 static inline void disable_dc_irq(unsigned int irq)
873 {
874         disable_irq(irq);
875 }
876
877 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
878 {
879         return dc->syncpt[i].id;
880 }
881 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
882
883 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
884 {
885         u32 max;
886
887         mutex_lock(&dc->lock);
888         tegra_dc_hold_dc_out(dc);
889         max = nvhost_syncpt_incr_max_ext(dc->ndev,
890                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
891         dc->syncpt[i].max = max;
892         tegra_dc_release_dc_out(dc);
893         mutex_unlock(&dc->lock);
894
895         return max;
896 }
897
898 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
899 {
900         mutex_lock(&dc->lock);
901         if (dc->enabled) {
902                 tegra_dc_hold_dc_out(dc);
903                 while (dc->syncpt[i].min < val) {
904                         dc->syncpt[i].min++;
905                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
906                 }
907                 tegra_dc_release_dc_out(dc);
908         }
909         mutex_unlock(&dc->lock);
910 }
911
912 void
913 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
914 {
915         unsigned int ctrl;
916         unsigned long out_sel;
917         unsigned long cmd_state;
918
919         mutex_lock(&dc->lock);
920         if (!dc->enabled) {
921                 mutex_unlock(&dc->lock);
922                 return;
923         }
924
925         tegra_dc_hold_dc_out(dc);
926
927         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
928                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
929                 cfg->clk_select);
930
931         /* The new value should be effected immediately */
932         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
933         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
934
935         switch (cfg->which_pwm) {
936         case TEGRA_PWM_PM0:
937                 /* Select the LM0 on PM0 */
938                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
939                 out_sel &= ~(7 << 0);
940                 out_sel |= (3 << 0);
941                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
942                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
943                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
944                 break;
945         case TEGRA_PWM_PM1:
946                 /* Select the LM1 on PM1 */
947                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
948                 out_sel &= ~(7 << 4);
949                 out_sel |= (3 << 4);
950                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
951                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
952                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
953                 break;
954         default:
955                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
956                 break;
957         }
958         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
959         tegra_dc_release_dc_out(dc);
960         mutex_unlock(&dc->lock);
961 }
962 EXPORT_SYMBOL(tegra_dc_config_pwm);
963
964 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
965                                 const struct tegra_dc_out_pin *pins,
966                                 const unsigned int n_pins)
967 {
968         unsigned int i;
969
970         int name;
971         int pol;
972
973         u32 pol1, pol3;
974
975         u32 set1, unset1;
976         u32 set3, unset3;
977
978         set1 = set3 = unset1 = unset3 = 0;
979
980         for (i = 0; i < n_pins; i++) {
981                 name = (pins + i)->name;
982                 pol  = (pins + i)->pol;
983
984                 /* set polarity by name */
985                 switch (name) {
986                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
987                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
988                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
989                         else
990                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
991                         break;
992                 case TEGRA_DC_OUT_PIN_H_SYNC:
993                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
994                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
995                         else
996                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
997                         break;
998                 case TEGRA_DC_OUT_PIN_V_SYNC:
999                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1000                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1001                         else
1002                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1003                         break;
1004                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1005                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1006                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1007                         else
1008                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1009                         break;
1010                 default:
1011                         printk("Invalid argument in function %s\n",
1012                                __FUNCTION__);
1013                         break;
1014                 }
1015         }
1016
1017         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1018         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1019
1020         pol1 |= set1;
1021         pol1 &= ~unset1;
1022
1023         pol3 |= set3;
1024         pol3 &= ~unset3;
1025
1026         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1027         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1028 }
1029
1030 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1031 {
1032         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1033                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1034                 dc->out->type == TEGRA_DC_OUT_DSI)
1035                 return override_disp_mode[dc->out->type].pclk ?
1036                         &override_disp_mode[dc->out->type] : NULL;
1037         else
1038                 return NULL;
1039 }
1040
1041 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1042 {
1043         struct tegra_dc_mode *mode;
1044
1045         dc->out = out;
1046         mode = tegra_dc_get_override_mode(dc);
1047
1048         if (mode)
1049                 tegra_dc_set_mode(dc, mode);
1050         else if (out->n_modes > 0)
1051                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1052
1053         switch (out->type) {
1054         case TEGRA_DC_OUT_RGB:
1055                 dc->out_ops = &tegra_dc_rgb_ops;
1056                 break;
1057
1058         case TEGRA_DC_OUT_HDMI:
1059                 dc->out_ops = &tegra_dc_hdmi_ops;
1060                 break;
1061
1062         case TEGRA_DC_OUT_DSI:
1063                 dc->out_ops = &tegra_dc_dsi_ops;
1064                 break;
1065
1066         default:
1067                 dc->out_ops = NULL;
1068                 break;
1069         }
1070
1071         if (dc->out_ops && dc->out_ops->init)
1072                 dc->out_ops->init(dc);
1073
1074 }
1075
1076 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1077 {
1078         if (dc->out)
1079                 return dc->out->height;
1080         else
1081                 return 0;
1082 }
1083 EXPORT_SYMBOL(tegra_dc_get_out_height);
1084
1085 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1086 {
1087         if (dc->out)
1088                 return dc->out->width;
1089         else
1090                 return 0;
1091 }
1092 EXPORT_SYMBOL(tegra_dc_get_out_width);
1093
1094 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1095 {
1096         if (dc->out && dc->out->max_pixclock)
1097                 return dc->out->max_pixclock;
1098         else
1099                 return 0;
1100 }
1101 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1102
1103 void tegra_dc_enable_crc(struct tegra_dc *dc)
1104 {
1105         u32 val;
1106
1107         mutex_lock(&dc->lock);
1108         tegra_dc_hold_dc_out(dc);
1109         tegra_dc_io_start(dc);
1110
1111         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1112                 CRC_ENABLE_ENABLE;
1113         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1114         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1115         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1116         tegra_dc_release_dc_out(dc);
1117         mutex_unlock(&dc->lock);
1118 }
1119
1120 void tegra_dc_disable_crc(struct tegra_dc *dc)
1121 {
1122         mutex_lock(&dc->lock);
1123         tegra_dc_hold_dc_out(dc);
1124         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1125         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1126         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1127
1128         tegra_dc_io_end(dc);
1129         tegra_dc_release_dc_out(dc);
1130         mutex_unlock(&dc->lock);
1131 }
1132
1133 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1134 {
1135         int crc = 0;
1136
1137         if (!dc) {
1138                 pr_err("Failed to get dc: NULL parameter.\n");
1139                 goto crc_error;
1140         }
1141
1142 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1143         /* TODO: Replace mdelay with code to sync VBlANK, since
1144          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1145         mdelay(TEGRA_CRC_LATCHED_DELAY);
1146 #endif
1147
1148         mutex_lock(&dc->lock);
1149         tegra_dc_hold_dc_out(dc);
1150         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1151         tegra_dc_release_dc_out(dc);
1152         mutex_unlock(&dc->lock);
1153 crc_error:
1154         return crc;
1155 }
1156
1157 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1158 {
1159 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1160         u32 val;
1161
1162         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1163         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1164             return true;
1165 #endif
1166         return false;
1167 }
1168
1169 static inline void enable_dc_irq(unsigned int irq)
1170 {
1171 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1172         enable_irq(irq);
1173 #else
1174         /* Always disable DC interrupts on FPGA. */
1175         disable_irq(irq);
1176 #endif
1177 }
1178
1179 static void tegra_dc_vblank(struct work_struct *work)
1180 {
1181         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1182         bool nvsd_updated = false;
1183
1184         mutex_lock(&dc->lock);
1185
1186         if (!dc->enabled) {
1187                 mutex_unlock(&dc->lock);
1188                 return;
1189         }
1190
1191         tegra_dc_hold_dc_out(dc);
1192         /* use the new frame's bandwidth setting instead of max(current, new),
1193          * skip this if we're using tegra_dc_one_shot_worker() */
1194         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1195                 tegra_dc_program_bandwidth(dc, true);
1196
1197         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1198         if (!tegra_dc_windows_are_dirty(dc))
1199                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1200
1201         /* Update the SD brightness */
1202         if (dc->enabled && dc->out->sd_settings) {
1203                 nvsd_updated = nvsd_update_brightness(dc);
1204                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1205                  * V_BLANK_NVSD bit of vblank ref-count. */
1206                 if (nvsd_updated) {
1207                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1208                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1209                 } else {
1210                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1211                 }
1212         }
1213
1214         /* Mask vblank interrupt if ref-count is zero. */
1215         if (!dc->vblank_ref_count)
1216                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1217
1218         tegra_dc_release_dc_out(dc);
1219         mutex_unlock(&dc->lock);
1220
1221         /* Do the actual brightness update outside of the mutex */
1222         if (nvsd_updated && dc->out->sd_settings &&
1223             dc->out->sd_settings->bl_device) {
1224
1225                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1226                 struct backlight_device *bl = platform_get_drvdata(pdev);
1227                 if (bl)
1228                         backlight_update_status(bl);
1229         }
1230 }
1231
1232 static void tegra_dc_one_shot_worker(struct work_struct *work)
1233 {
1234         struct tegra_dc *dc = container_of(
1235                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1236         mutex_lock(&dc->lock);
1237
1238         /* memory client has gone idle */
1239         tegra_dc_clear_bandwidth(dc);
1240
1241         if (dc->out_ops->idle)
1242                 dc->out_ops->idle(dc);
1243
1244         mutex_unlock(&dc->lock);
1245 }
1246
1247 /* return an arbitrarily large number if count overflow occurs.
1248  * make it a nice base-10 number to show up in stats output */
1249 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1250 {
1251         unsigned count = tegra_dc_readl(dc, reg);
1252         tegra_dc_writel(dc, 0, reg);
1253         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1254 }
1255
1256 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1257 {
1258         u32 val;
1259         int i;
1260
1261         dc->stats.underflows++;
1262         if (dc->underflow_mask & WIN_A_UF_INT)
1263                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1264                         DC_WINBUF_AD_UFLOW_STATUS);
1265         if (dc->underflow_mask & WIN_B_UF_INT)
1266                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1267                         DC_WINBUF_BD_UFLOW_STATUS);
1268         if (dc->underflow_mask & WIN_C_UF_INT)
1269                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1270                         DC_WINBUF_CD_UFLOW_STATUS);
1271
1272         /* Check for any underflow reset conditions */
1273         for (i = 0; i < DC_N_WINDOWS; i++) {
1274                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1275                         dc->windows[i].underflows++;
1276
1277 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1278                         if (dc->windows[i].underflows > 4) {
1279                                 schedule_work(&dc->reset_work);
1280                                 /* reset counter */
1281                                 dc->windows[i].underflows = 0;
1282                                 trace_display_reset(dc);
1283                         }
1284 #endif
1285 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1286                         if (dc->windows[i].underflows > 4) {
1287                                 trace_display_reset(dc);
1288                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1289                                                 DC_DISP_DISP_MISC_CONTROL);
1290                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1291                                                 DC_CMD_STATE_CONTROL);
1292                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1293                                                 DC_CMD_STATE_CONTROL);
1294
1295                                 tegra_dc_writel(dc, 0,
1296                                                 DC_DISP_DISP_MISC_CONTROL);
1297                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1298                                                 DC_CMD_STATE_CONTROL);
1299                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1300                                                 DC_CMD_STATE_CONTROL);
1301                         }
1302 #endif
1303                 } else {
1304                         dc->windows[i].underflows = 0;
1305                 }
1306         }
1307
1308         /* Clear the underflow mask now that we've checked it. */
1309         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1310         dc->underflow_mask = 0;
1311         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1312         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1313         trace_underflow(dc);
1314 }
1315
1316 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1317 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1318 {
1319         if (status & V_BLANK_INT) {
1320                 /* Sync up windows. */
1321                 tegra_dc_trigger_windows(dc);
1322
1323                 /* Schedule any additional bottom-half vblank actvities. */
1324                 queue_work(system_freezable_wq, &dc->vblank_work);
1325         }
1326
1327         if (status & FRAME_END_INT) {
1328                 /* Mark the frame_end as complete. */
1329                 if (!completion_done(&dc->frame_end_complete))
1330                         complete(&dc->frame_end_complete);
1331         }
1332 }
1333
1334 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1335 {
1336         /* Schedule any additional bottom-half vblank actvities. */
1337         if (status & V_BLANK_INT)
1338                 queue_work(system_freezable_wq, &dc->vblank_work);
1339
1340         if (status & FRAME_END_INT) {
1341                 struct timespec tm = CURRENT_TIME;
1342                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1343                 wake_up(&dc->timestamp_wq);
1344
1345                 /* Mark the frame_end as complete. */
1346                 if (!completion_done(&dc->frame_end_complete))
1347                         complete(&dc->frame_end_complete);
1348
1349                 tegra_dc_trigger_windows(dc);
1350         }
1351 }
1352
1353 /* XXX: Not sure if we limit look ahead to 1 frame */
1354 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1355 {
1356         BUG_ON(!dc->frametime_ns);
1357         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1358 }
1359
1360 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1361 {
1362         BUG_ON(!dc->frametime_ns);
1363         return (((new_ts - old_ts) > dc->frametime_ns)
1364                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1365                         != div_s64((old_ts - dc->frame_end_timestamp),
1366                                 dc->frametime_ns)));
1367 }
1368 #endif
1369
1370 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1371 {
1372 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1373         struct tegra_dc *dc = ptr;
1374         unsigned long status;
1375         unsigned long underflow_mask;
1376         u32 val;
1377
1378         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1379                 WARN(1, "IRQ when DC not powered!\n");
1380                 tegra_dc_io_start(dc);
1381                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1382                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1383                 tegra_dc_io_end(dc);
1384                 return IRQ_HANDLED;
1385         }
1386
1387         /* clear all status flags except underflow, save those for the worker */
1388         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1389         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1390         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1391         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1392
1393         /*
1394          * Overlays can get thier internal state corrupted during and underflow
1395          * condition.  The only way to fix this state is to reset the DC.
1396          * if we get 4 consecutive frames with underflows, assume we're
1397          * hosed and reset.
1398          */
1399         underflow_mask = status & ALL_UF_INT;
1400
1401         /* Check underflow */
1402         if (underflow_mask) {
1403                 dc->underflow_mask |= underflow_mask;
1404                 schedule_delayed_work(&dc->underflow_work,
1405                         msecs_to_jiffies(1));
1406         }
1407
1408         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1409                 tegra_dc_one_shot_irq(dc, status);
1410         else
1411                 tegra_dc_continuous_irq(dc, status);
1412
1413         return IRQ_HANDLED;
1414 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1415         return IRQ_NONE;
1416 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1417 }
1418
1419 void tegra_dc_set_color_control(struct tegra_dc *dc)
1420 {
1421         u32 color_control;
1422
1423         switch (dc->out->depth) {
1424         case 3:
1425                 color_control = BASE_COLOR_SIZE111;
1426                 break;
1427
1428         case 6:
1429                 color_control = BASE_COLOR_SIZE222;
1430                 break;
1431
1432         case 8:
1433                 color_control = BASE_COLOR_SIZE332;
1434                 break;
1435
1436         case 9:
1437                 color_control = BASE_COLOR_SIZE333;
1438                 break;
1439
1440         case 12:
1441                 color_control = BASE_COLOR_SIZE444;
1442                 break;
1443
1444         case 15:
1445                 color_control = BASE_COLOR_SIZE555;
1446                 break;
1447
1448         case 16:
1449                 color_control = BASE_COLOR_SIZE565;
1450                 break;
1451
1452         case 18:
1453                 color_control = BASE_COLOR_SIZE666;
1454                 break;
1455
1456         default:
1457                 color_control = BASE_COLOR_SIZE888;
1458                 break;
1459         }
1460
1461         switch (dc->out->dither) {
1462         case TEGRA_DC_DISABLE_DITHER:
1463                 color_control |= DITHER_CONTROL_DISABLE;
1464                 break;
1465         case TEGRA_DC_ORDERED_DITHER:
1466                 color_control |= DITHER_CONTROL_ORDERED;
1467                 break;
1468         case TEGRA_DC_ERRDIFF_DITHER:
1469                 /* The line buffer for error-diffusion dither is limited
1470                  * to 1280 pixels per line. This limits the maximum
1471                  * horizontal active area size to 1280 pixels when error
1472                  * diffusion is enabled.
1473                  */
1474                 BUG_ON(dc->mode.h_active > 1280);
1475                 color_control |= DITHER_CONTROL_ERRDIFF;
1476                 break;
1477         }
1478
1479 #ifdef CONFIG_TEGRA_DC_CMU
1480         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1481                 color_control |= CMU_ENABLE;
1482 #endif
1483
1484         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1485 }
1486
1487 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1488 {
1489         u32 syncpt_id;
1490
1491         switch (dc->ndev->id) {
1492         case 0:
1493                 switch (idx) {
1494                 case 0:
1495                         syncpt_id = NVSYNCPT_DISP0_A;
1496                         break;
1497                 case 1:
1498                         syncpt_id = NVSYNCPT_DISP0_B;
1499                         break;
1500                 case 2:
1501                         syncpt_id = NVSYNCPT_DISP0_C;
1502                         break;
1503                 default:
1504                         BUG();
1505                         break;
1506                 }
1507                 break;
1508         case 1:
1509                 switch (idx) {
1510                 case 0:
1511                         syncpt_id = NVSYNCPT_DISP1_A;
1512                         break;
1513                 case 1:
1514                         syncpt_id = NVSYNCPT_DISP1_B;
1515                         break;
1516                 case 2:
1517                         syncpt_id = NVSYNCPT_DISP1_C;
1518                         break;
1519                 default:
1520                         BUG();
1521                         break;
1522                 }
1523                 break;
1524         default:
1525                 BUG();
1526                 break;
1527         }
1528
1529         return syncpt_id;
1530 }
1531
1532 static int tegra_dc_init(struct tegra_dc *dc)
1533 {
1534         int i;
1535
1536         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1537         if (dc->ndev->id == 0) {
1538                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1539                                       TEGRA_MC_PRIO_MED);
1540                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1541                                       TEGRA_MC_PRIO_MED);
1542                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1543                                       TEGRA_MC_PRIO_MED);
1544 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1545                 /* only present on Tegra2 and 3 */
1546                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1547                                       TEGRA_MC_PRIO_MED);
1548 #endif
1549                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1550                                       TEGRA_MC_PRIO_HIGH);
1551         } else if (dc->ndev->id == 1) {
1552                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1553                                       TEGRA_MC_PRIO_MED);
1554                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1555                                       TEGRA_MC_PRIO_MED);
1556                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1557                                       TEGRA_MC_PRIO_MED);
1558 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1559                 /* only present on Tegra2 and 3 */
1560                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1561                                       TEGRA_MC_PRIO_MED);
1562 #endif
1563                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1564                                       TEGRA_MC_PRIO_HIGH);
1565         }
1566         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1567                         DC_CMD_CONT_SYNCPT_VSYNC);
1568         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1569         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1570         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1571         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1572 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1573         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1574 #endif
1575         /* enable interrupts for vblank, frame_end and underflows */
1576         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1577                 DC_CMD_INT_ENABLE);
1578         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1579
1580         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1581
1582 #ifdef CONFIG_TEGRA_DC_CMU
1583         if (dc->pdata->cmu)
1584                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
1585         else
1586                 tegra_dc_update_cmu(dc, &default_cmu);
1587 #endif
1588
1589         tegra_dc_set_color_control(dc);
1590         for (i = 0; i < DC_N_WINDOWS; i++) {
1591                 struct tegra_dc_win *win = &dc->windows[i];
1592                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1593                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1594                 tegra_dc_set_csc(dc, &win->csc);
1595                 tegra_dc_set_lut(dc, win);
1596                 tegra_dc_set_scaling_filter(dc);
1597         }
1598
1599         for (i = 0; i < dc->n_windows; i++) {
1600                 u32 syncpt = get_syncpt(dc, i);
1601
1602                 dc->syncpt[i].id = syncpt;
1603
1604                 dc->syncpt[i].min = dc->syncpt[i].max =
1605                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1606         }
1607
1608         trace_display_mode(dc, &dc->mode);
1609
1610         if (dc->mode.pclk)
1611                 if (tegra_dc_program_mode(dc, &dc->mode))
1612                         return -EINVAL;
1613
1614         /* Initialize SD AFTER the modeset.
1615            nvsd_init handles the sd_settings = NULL case. */
1616         nvsd_init(dc, dc->out->sd_settings);
1617
1618         return 0;
1619 }
1620
1621 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1622 {
1623         int failed_init = 0;
1624
1625         if (dc->out->enable)
1626                 dc->out->enable(&dc->ndev->dev);
1627
1628         tegra_dc_setup_clk(dc, dc->clk);
1629         tegra_dc_clk_enable(dc);
1630
1631         tegra_dc_power_on(dc);
1632
1633         /* do not accept interrupts during initialization */
1634         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1635
1636         enable_dc_irq(dc->irq);
1637
1638         failed_init = tegra_dc_init(dc);
1639         if (failed_init) {
1640                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1641                 disable_irq(dc->irq);
1642                 tegra_dc_clear_bandwidth(dc);
1643                 tegra_dc_clk_disable(dc);
1644                 if (dc->out && dc->out->disable)
1645                         dc->out->disable();
1646                 return false;
1647         }
1648
1649         if (dc->out_ops && dc->out_ops->enable)
1650                 dc->out_ops->enable(dc);
1651
1652         /* force a full blending update */
1653         dc->blend.z[0] = -1;
1654
1655         tegra_dc_ext_enable(dc->ext);
1656
1657         trace_display_enable(dc);
1658
1659         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1660         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1661
1662         if (dc->out->postpoweron)
1663                 dc->out->postpoweron();
1664
1665         return true;
1666 }
1667
1668 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1669 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1670 {
1671         bool ret = true;
1672
1673         if (dc->out->enable)
1674                 dc->out->enable(&dc->ndev->dev);
1675
1676         tegra_dc_setup_clk(dc, dc->clk);
1677         tegra_dc_clk_enable(dc);
1678
1679         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1680                 mutex_lock(&tegra_dcs[1]->lock);
1681                 disable_irq(tegra_dcs[1]->irq);
1682         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1683                 mutex_lock(&tegra_dcs[0]->lock);
1684                 disable_irq(tegra_dcs[0]->irq);
1685         }
1686
1687         msleep(5);
1688         tegra_periph_reset_assert(dc->clk);
1689         msleep(2);
1690 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1691         tegra_periph_reset_deassert(dc->clk);
1692         msleep(1);
1693 #endif
1694
1695         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1696                 enable_dc_irq(tegra_dcs[1]->irq);
1697                 mutex_unlock(&tegra_dcs[1]->lock);
1698         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1699                 enable_dc_irq(tegra_dcs[0]->irq);
1700                 mutex_unlock(&tegra_dcs[0]->lock);
1701         }
1702
1703         enable_dc_irq(dc->irq);
1704
1705         if (tegra_dc_init(dc)) {
1706                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1707                 ret = false;
1708         }
1709
1710         if (dc->out_ops && dc->out_ops->enable)
1711                 dc->out_ops->enable(dc);
1712
1713         if (dc->out->postpoweron)
1714                 dc->out->postpoweron();
1715
1716         /* force a full blending update */
1717         dc->blend.z[0] = -1;
1718
1719         tegra_dc_ext_enable(dc->ext);
1720
1721         if (!ret) {
1722                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1723                 _tegra_dc_controller_disable(dc);
1724         }
1725
1726         trace_display_reset(dc);
1727         return ret;
1728 }
1729 #endif
1730
1731 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1732 {
1733         if (dc->mode.pclk == 0) {
1734                 switch (dc->out->type) {
1735                 case TEGRA_DC_OUT_HDMI:
1736                 /* DC enable called but no videomode is loaded.
1737                      Check if HDMI is connected, then set fallback mdoe */
1738                 if (tegra_dc_hpd(dc)) {
1739                         return tegra_dc_set_fb_mode(dc,
1740                                         &tegra_dc_hdmi_fallback_mode, 0);
1741                 } else
1742                         return false;
1743
1744                 break;
1745
1746                 /* Do nothing for other outputs for now */
1747                 case TEGRA_DC_OUT_RGB:
1748
1749                 case TEGRA_DC_OUT_DSI:
1750
1751                 default:
1752                         return false;
1753                 }
1754         }
1755
1756         return false;
1757 }
1758
1759 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1760 {
1761         return _tegra_dc_set_default_videomode(dc);
1762 }
1763
1764 static bool _tegra_dc_enable(struct tegra_dc *dc)
1765 {
1766         if (dc->mode.pclk == 0)
1767                 return false;
1768
1769         if (!dc->out)
1770                 return false;
1771
1772         tegra_dc_io_start(dc);
1773
1774         if (!_tegra_dc_controller_enable(dc)) {
1775                 tegra_dc_io_end(dc);
1776                 return false;
1777         }
1778         return true;
1779 }
1780
1781 void tegra_dc_enable(struct tegra_dc *dc)
1782 {
1783         mutex_lock(&dc->lock);
1784
1785         if (!dc->enabled)
1786                 dc->enabled = _tegra_dc_enable(dc);
1787
1788         mutex_unlock(&dc->lock);
1789         trace_display_mode(dc, &dc->mode);
1790 }
1791
1792 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1793 {
1794         unsigned i;
1795
1796         if (dc->out && dc->out->prepoweroff)
1797                 dc->out->prepoweroff();
1798
1799         if (dc->out_ops && dc->out_ops->disable)
1800                 dc->out_ops->disable(dc);
1801
1802         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1803         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1804         disable_irq(dc->irq);
1805
1806         tegra_dc_clear_bandwidth(dc);
1807         tegra_dc_clk_disable(dc);
1808
1809         if (dc->out && dc->out->disable)
1810                 dc->out->disable();
1811
1812         for (i = 0; i < dc->n_windows; i++) {
1813                 struct tegra_dc_win *w = &dc->windows[i];
1814
1815                 /* reset window bandwidth */
1816                 w->bandwidth = 0;
1817                 w->new_bandwidth = 0;
1818
1819                 /* disable windows */
1820                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1821
1822                 /* flush any pending syncpt waits */
1823                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1824                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1825                                 dc->syncpt[i].min, dc->syncpt[i].max);
1826                         dc->syncpt[i].min++;
1827                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1828                 }
1829         }
1830         trace_display_disable(dc);
1831 }
1832
1833 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1834 {
1835 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1836         u32 val;
1837         if (dc->enabled)  {
1838                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1839                 if (enable)
1840                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1841                 else
1842                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1843                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1844         }
1845 #endif
1846 }
1847
1848 bool tegra_dc_stats_get(struct tegra_dc *dc)
1849 {
1850 #if 0 /* right now it is always enabled */
1851         u32 val;
1852         bool res;
1853
1854         if (dc->enabled)  {
1855                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1856                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1857         } else {
1858                 res = false;
1859         }
1860
1861         return res;
1862 #endif
1863         return true;
1864 }
1865
1866 /* make the screen blank by disabling all windows */
1867 void tegra_dc_blank(struct tegra_dc *dc)
1868 {
1869         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1870         unsigned i;
1871
1872         for (i = 0; i < DC_N_WINDOWS; i++) {
1873                 dcwins[i] = tegra_dc_get_window(dc, i);
1874                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1875         }
1876
1877         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1878         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1879 }
1880
1881 static void _tegra_dc_disable(struct tegra_dc *dc)
1882 {
1883         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1884                 mutex_lock(&dc->one_shot_lock);
1885                 cancel_delayed_work_sync(&dc->one_shot_work);
1886         }
1887
1888         tegra_dc_hold_dc_out(dc);
1889
1890         _tegra_dc_controller_disable(dc);
1891         tegra_dc_io_end(dc);
1892
1893         tegra_dc_release_dc_out(dc);
1894
1895         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1896                 mutex_unlock(&dc->one_shot_lock);
1897 }
1898
1899 void tegra_dc_disable(struct tegra_dc *dc)
1900 {
1901         tegra_dc_ext_disable(dc->ext);
1902
1903         /* it's important that new underflow work isn't scheduled before the
1904          * lock is acquired. */
1905         cancel_delayed_work_sync(&dc->underflow_work);
1906
1907         mutex_lock(&dc->lock);
1908
1909         if (dc->enabled) {
1910                 dc->enabled = false;
1911
1912                 if (!dc->suspended)
1913                         _tegra_dc_disable(dc);
1914         }
1915
1916 #ifdef CONFIG_SWITCH
1917         switch_set_state(&dc->modeset_switch, 0);
1918 #endif
1919
1920         mutex_unlock(&dc->lock);
1921         trace_display_mode(dc, &dc->mode);
1922 }
1923
1924 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1925 static void tegra_dc_reset_worker(struct work_struct *work)
1926 {
1927         struct tegra_dc *dc =
1928                 container_of(work, struct tegra_dc, reset_work);
1929
1930         unsigned long val = 0;
1931
1932         mutex_lock(&shared_lock);
1933
1934         dev_warn(&dc->ndev->dev,
1935                 "overlay stuck in underflow state.  resetting.\n");
1936
1937         tegra_dc_ext_disable(dc->ext);
1938
1939         mutex_lock(&dc->lock);
1940
1941         if (dc->enabled == false)
1942                 goto unlock;
1943
1944         dc->enabled = false;
1945
1946         /*
1947          * off host read bus
1948          */
1949         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1950         val &= ~(0x00000100);
1951         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1952
1953         /*
1954          * set DC to STOP mode
1955          */
1956         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1957
1958         msleep(10);
1959
1960         _tegra_dc_controller_disable(dc);
1961
1962         /* _tegra_dc_controller_reset_enable deasserts reset */
1963         _tegra_dc_controller_reset_enable(dc);
1964
1965         dc->enabled = true;
1966
1967         /* reopen host read bus */
1968         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1969         val &= ~(0x00000100);
1970         val |= 0x100;
1971         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1972
1973 unlock:
1974         mutex_unlock(&dc->lock);
1975         mutex_unlock(&shared_lock);
1976         trace_display_reset(dc);
1977 }
1978 #endif
1979
1980 static void tegra_dc_underflow_worker(struct work_struct *work)
1981 {
1982         struct tegra_dc *dc = container_of(
1983                 to_delayed_work(work), struct tegra_dc, underflow_work);
1984
1985         mutex_lock(&dc->lock);
1986         tegra_dc_hold_dc_out(dc);
1987
1988         if (dc->enabled) {
1989                 tegra_dc_underflow_handler(dc);
1990         }
1991         tegra_dc_release_dc_out(dc);
1992         mutex_unlock(&dc->lock);
1993 }
1994
1995 #ifdef CONFIG_SWITCH
1996 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1997 {
1998         struct tegra_dc *dc =
1999                 container_of(sdev, struct tegra_dc, modeset_switch);
2000
2001         if (!sdev->state)
2002                 return sprintf(buf, "offline\n");
2003
2004         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2005 }
2006 #endif
2007
2008 static int tegra_dc_probe(struct nvhost_device *ndev,
2009         struct nvhost_device_id *id_table)
2010 {
2011         struct tegra_dc *dc;
2012         struct tegra_dc_mode *mode;
2013         struct clk *clk;
2014         struct clk *emc_clk;
2015         struct resource *res;
2016         struct resource *base_res;
2017         struct resource *fb_mem = NULL;
2018         int ret = 0;
2019         void __iomem *base;
2020         int irq;
2021         int i;
2022
2023         if (!ndev->dev.platform_data) {
2024                 dev_err(&ndev->dev, "no platform data\n");
2025                 return -ENOENT;
2026         }
2027
2028         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2029         if (!dc) {
2030                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2031                 return -ENOMEM;
2032         }
2033
2034         irq = nvhost_get_irq_byname(ndev, "irq");
2035         if (irq <= 0) {
2036                 dev_err(&ndev->dev, "no irq\n");
2037                 ret = -ENOENT;
2038                 goto err_free;
2039         }
2040
2041         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2042         if (!res) {
2043                 dev_err(&ndev->dev, "no mem resource\n");
2044                 ret = -ENOENT;
2045                 goto err_free;
2046         }
2047
2048         base_res = request_mem_region(res->start, resource_size(res),
2049                 ndev->name);
2050         if (!base_res) {
2051                 dev_err(&ndev->dev, "request_mem_region failed\n");
2052                 ret = -EBUSY;
2053                 goto err_free;
2054         }
2055
2056         base = ioremap(res->start, resource_size(res));
2057         if (!base) {
2058                 dev_err(&ndev->dev, "registers can't be mapped\n");
2059                 ret = -EBUSY;
2060                 goto err_release_resource_reg;
2061         }
2062
2063         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2064
2065         clk = clk_get(&ndev->dev, NULL);
2066         if (IS_ERR_OR_NULL(clk)) {
2067                 dev_err(&ndev->dev, "can't get clock\n");
2068                 ret = -ENOENT;
2069                 goto err_iounmap_reg;
2070         }
2071
2072         emc_clk = clk_get(&ndev->dev, "emc");
2073         if (IS_ERR_OR_NULL(emc_clk)) {
2074                 dev_err(&ndev->dev, "can't get emc clock\n");
2075                 ret = -ENOENT;
2076                 goto err_put_clk;
2077         }
2078
2079         dc->clk = clk;
2080         dc->emc_clk = emc_clk;
2081         dc->shift_clk_div = 1;
2082         /* Initialize one shot work delay, it will be assigned by dsi
2083          * according to refresh rate later. */
2084         dc->one_shot_delay_ms = 40;
2085
2086         dc->base_res = base_res;
2087         dc->base = base;
2088         dc->irq = irq;
2089         dc->ndev = ndev;
2090         dc->pdata = ndev->dev.platform_data;
2091
2092         /*
2093          * The emc is a shared clock, it will be set based on
2094          * the requirements for each user on the bus.
2095          */
2096         dc->emc_clk_rate = 0;
2097
2098         mutex_init(&dc->lock);
2099         mutex_init(&dc->one_shot_lock);
2100         init_completion(&dc->frame_end_complete);
2101         init_waitqueue_head(&dc->wq);
2102         init_waitqueue_head(&dc->timestamp_wq);
2103 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2104         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2105 #endif
2106         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2107         dc->vblank_ref_count = 0;
2108         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2109         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2110
2111         tegra_dc_init_lut_defaults(&dc->fb_lut);
2112
2113         dc->n_windows = DC_N_WINDOWS;
2114         for (i = 0; i < dc->n_windows; i++) {
2115                 struct tegra_dc_win *win = &dc->windows[i];
2116                 win->idx = i;
2117                 win->dc = dc;
2118                 tegra_dc_init_csc_defaults(&win->csc);
2119                 tegra_dc_init_lut_defaults(&win->lut);
2120         }
2121
2122         ret = tegra_dc_set(dc, ndev->id);
2123         if (ret < 0) {
2124                 dev_err(&ndev->dev, "can't add dc\n");
2125                 goto err_free_irq;
2126         }
2127
2128         nvhost_set_drvdata(ndev, dc);
2129
2130 #ifdef CONFIG_SWITCH
2131         dc->modeset_switch.name = dev_name(&ndev->dev);
2132         dc->modeset_switch.state = 0;
2133         dc->modeset_switch.print_state = switch_modeset_print_mode;
2134         ret = switch_dev_register(&dc->modeset_switch);
2135         if (ret < 0)
2136                 dev_err(&ndev->dev, "failed to register switch driver\n");
2137 #endif
2138
2139         tegra_dc_feature_register(dc);
2140
2141         if (dc->pdata->default_out)
2142                 tegra_dc_set_out(dc, dc->pdata->default_out);
2143         else
2144                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2145
2146         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2147                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2148
2149         dc->ext = tegra_dc_ext_register(ndev, dc);
2150         if (IS_ERR_OR_NULL(dc->ext)) {
2151                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2152                 dc->ext = NULL;
2153         }
2154
2155         /* interrupt handler must be registered before tegra_fb_register() */
2156         if (request_irq(irq, tegra_dc_irq, 0,
2157                         dev_name(&ndev->dev), dc)) {
2158                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2159                 ret = -EBUSY;
2160                 goto err_put_emc_clk;
2161         }
2162
2163         mutex_lock(&dc->lock);
2164         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2165                 _tegra_dc_set_default_videomode(dc);
2166                 dc->enabled = _tegra_dc_enable(dc);
2167         }
2168         mutex_unlock(&dc->lock);
2169
2170         tegra_dc_create_debugfs(dc);
2171
2172         dev_info(&ndev->dev, "probed\n");
2173
2174         if (dc->pdata->fb) {
2175                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2176                         unsigned long fmt;
2177                         tegra_dc_writel(dc,
2178                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2179                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2180
2181                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2182                         dc->pdata->fb->bits_per_pixel =
2183                                 tegra_dc_fmt_bpp(fmt);
2184                 }
2185
2186                 mode = tegra_dc_get_override_mode(dc);
2187                 if (mode) {
2188                         dc->pdata->fb->xres = mode->h_active;
2189                         dc->pdata->fb->yres = mode->v_active;
2190                 }
2191
2192                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2193                 if (IS_ERR_OR_NULL(dc->fb))
2194                         dc->fb = NULL;
2195         }
2196
2197         if (dc->out && dc->out->hotplug_init)
2198                 dc->out->hotplug_init(&ndev->dev);
2199
2200         if (dc->out_ops && dc->out_ops->detect)
2201                 dc->out_ops->detect(dc);
2202         else
2203                 dc->connected = true;
2204
2205         tegra_dc_create_sysfs(&dc->ndev->dev);
2206
2207         return 0;
2208
2209 err_free_irq:
2210         free_irq(irq, dc);
2211 err_put_emc_clk:
2212         clk_put(emc_clk);
2213 err_put_clk:
2214         clk_put(clk);
2215 err_iounmap_reg:
2216         iounmap(base);
2217         if (fb_mem)
2218                 release_resource(fb_mem);
2219 err_release_resource_reg:
2220         release_resource(base_res);
2221 err_free:
2222         kfree(dc);
2223
2224         return ret;
2225 }
2226
2227 static int tegra_dc_remove(struct nvhost_device *ndev)
2228 {
2229         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2230
2231         tegra_dc_remove_sysfs(&dc->ndev->dev);
2232         tegra_dc_remove_debugfs(dc);
2233
2234         if (dc->fb) {
2235                 tegra_fb_unregister(dc->fb);
2236                 if (dc->fb_mem)
2237                         release_resource(dc->fb_mem);
2238         }
2239
2240         tegra_dc_ext_disable(dc->ext);
2241
2242         if (dc->ext)
2243                 tegra_dc_ext_unregister(dc->ext);
2244
2245         if (dc->enabled)
2246                 _tegra_dc_disable(dc);
2247
2248 #ifdef CONFIG_SWITCH
2249         switch_dev_unregister(&dc->modeset_switch);
2250 #endif
2251         free_irq(dc->irq, dc);
2252         clk_put(dc->emc_clk);
2253         clk_put(dc->clk);
2254         iounmap(dc->base);
2255         if (dc->fb_mem)
2256                 release_resource(dc->base_res);
2257         kfree(dc);
2258         tegra_dc_set(NULL, ndev->id);
2259         return 0;
2260 }
2261
2262 #ifdef CONFIG_PM
2263 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2264 {
2265         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2266
2267         trace_display_suspend(dc);
2268         dev_info(&ndev->dev, "suspend\n");
2269
2270         tegra_dc_ext_disable(dc->ext);
2271
2272         mutex_lock(&dc->lock);
2273
2274         if (dc->out_ops && dc->out_ops->suspend)
2275                 dc->out_ops->suspend(dc);
2276
2277         if (dc->enabled) {
2278                 _tegra_dc_disable(dc);
2279
2280                 dc->suspended = true;
2281         }
2282
2283         if (dc->out && dc->out->postsuspend) {
2284                 dc->out->postsuspend();
2285                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2286                         /*
2287                          * avoid resume event due to voltage falling
2288                          */
2289                         msleep(100);
2290         }
2291
2292         mutex_unlock(&dc->lock);
2293
2294         return 0;
2295 }
2296
2297 static int tegra_dc_resume(struct nvhost_device *ndev)
2298 {
2299         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2300
2301         trace_display_resume(dc);
2302         dev_info(&ndev->dev, "resume\n");
2303
2304         mutex_lock(&dc->lock);
2305         dc->suspended = false;
2306
2307         if (dc->enabled) {
2308                 _tegra_dc_set_default_videomode(dc);
2309                 _tegra_dc_enable(dc);
2310         }
2311
2312         if (dc->out && dc->out->hotplug_init)
2313                 dc->out->hotplug_init(&ndev->dev);
2314
2315         if (dc->out_ops && dc->out_ops->resume)
2316                 dc->out_ops->resume(dc);
2317         mutex_unlock(&dc->lock);
2318
2319         return 0;
2320 }
2321
2322 #endif /* CONFIG_PM */
2323
2324 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2325 {
2326         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2327
2328         if (!dc || !dc->enabled)
2329                 return;
2330
2331         tegra_dc_blank(dc);
2332         tegra_dc_disable(dc);
2333 }
2334
2335 extern int suspend_set(const char *val, struct kernel_param *kp)
2336 {
2337         if (!strcmp(val, "dump"))
2338                 dump_regs(tegra_dcs[0]);
2339 #ifdef CONFIG_PM
2340         else if (!strcmp(val, "suspend"))
2341                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2342         else if (!strcmp(val, "resume"))
2343                 tegra_dc_resume(tegra_dcs[0]->ndev);
2344 #endif
2345
2346         return 0;
2347 }
2348
2349 extern int suspend_get(char *buffer, struct kernel_param *kp)
2350 {
2351         return 0;
2352 }
2353
2354 int suspend;
2355
2356 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2357
2358 struct nvhost_driver tegra_dc_driver = {
2359         .driver = {
2360                 .name = "tegradc",
2361                 .owner = THIS_MODULE,
2362         },
2363         .probe = tegra_dc_probe,
2364         .remove = tegra_dc_remove,
2365 #ifdef CONFIG_PM
2366         .suspend = tegra_dc_suspend,
2367         .resume = tegra_dc_resume,
2368 #endif
2369         .shutdown = tegra_dc_shutdown,
2370 };
2371
2372 #ifndef MODULE
2373 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2374 {
2375         int i, params[11];
2376         char *p;
2377
2378         for (i = 0; i < ARRAY_SIZE(params); i++) {
2379                 if ((p = strsep(&options, ",")) != NULL) {
2380                         if (*p)
2381                                 params[i] = simple_strtoul(p, &p, 10);
2382                 } else
2383                         return -EINVAL;
2384         }
2385
2386         if ((mode->pclk = params[0]) == 0)
2387                 return -EINVAL;
2388
2389         mode->h_active      = params[1];
2390         mode->v_active      = params[2];
2391         mode->h_ref_to_sync = params[3];
2392         mode->v_ref_to_sync = params[4];
2393         mode->h_sync_width  = params[5];
2394         mode->v_sync_width  = params[6];
2395         mode->h_back_porch  = params[7];
2396         mode->v_back_porch  = params[8];
2397         mode->h_front_porch = params[9];
2398         mode->v_front_porch = params[10];
2399
2400         return 0;
2401 }
2402
2403 static int __init tegra_dc_mode_override(char *str)
2404 {
2405         char *p = str, *options;
2406
2407         if (!p || !*p)
2408                 return -EINVAL;
2409
2410         p = strstr(str, "hdmi:");
2411         if (p) {
2412                 p += 5;
2413                 options = strsep(&p, ";");
2414                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2415                         return -EINVAL;
2416         }
2417
2418         p = strstr(str, "rgb:");
2419         if (p) {
2420                 p += 4;
2421                 options = strsep(&p, ";");
2422                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2423                         return -EINVAL;
2424         }
2425
2426         p = strstr(str, "dsi:");
2427         if (p) {
2428                 p += 4;
2429                 options = strsep(&p, ";");
2430                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2431                         return -EINVAL;
2432         }
2433
2434         return 0;
2435 }
2436
2437 __setup("disp_params=", tegra_dc_mode_override);
2438 #endif
2439
2440 static int __init tegra_dc_module_init(void)
2441 {
2442         int ret = tegra_dc_ext_module_init();
2443         if (ret)
2444                 return ret;
2445         return nvhost_driver_register(&tegra_dc_driver);
2446 }
2447
2448 static void __exit tegra_dc_module_exit(void)
2449 {
2450         nvhost_driver_unregister(&tegra_dc_driver);
2451         tegra_dc_ext_module_exit();
2452 }
2453
2454 module_exit(tegra_dc_module_exit);
2455 module_init(tegra_dc_module_init);