2 * drivers/video/tegra/dc/dc.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * Copyright (C) 2010-2011 NVIDIA Corporation
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <video/tegrafb.h>
37 #include <drm/drm_fixed.h>
43 #include <linux/nvhost.h>
44 #include <mach/latency_allowance.h>
51 #define TEGRA_CRC_LATCHED_DELAY 34
53 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
54 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
56 /* ignore underflows when on simulation and fpga platform */
57 #define ALL_UF_INT (0)
62 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
64 static int use_dynamic_emc = 1;
66 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
68 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
70 DEFINE_MUTEX(tegra_dc_lock);
71 DEFINE_MUTEX(shared_lock);
77 /* Window A has no filtering */
79 /* Window B has both H and V filtering */
81 /* Window C has only H filtering */
84 static inline bool win_use_v_filter(const struct tegra_dc_win *win)
86 return can_filter[win->idx].v &&
87 win->h.full != dfixed_const(win->out_h);
89 static inline bool win_use_h_filter(const struct tegra_dc_win *win)
91 return can_filter[win->idx].h &&
92 win->w.full != dfixed_const(win->out_w);
95 static inline int tegra_dc_fmt_bpp(int fmt)
98 case TEGRA_WIN_FMT_P1:
101 case TEGRA_WIN_FMT_P2:
104 case TEGRA_WIN_FMT_P4:
107 case TEGRA_WIN_FMT_P8:
110 case TEGRA_WIN_FMT_B4G4R4A4:
111 case TEGRA_WIN_FMT_B5G5R5A:
112 case TEGRA_WIN_FMT_B5G6R5:
113 case TEGRA_WIN_FMT_AB5G5R5:
116 case TEGRA_WIN_FMT_B8G8R8A8:
117 case TEGRA_WIN_FMT_R8G8B8A8:
118 case TEGRA_WIN_FMT_B6x2G6x2R6x2A8:
119 case TEGRA_WIN_FMT_R6x2G6x2B6x2A8:
122 /* for planar formats, size of the Y plane, 8bit */
123 case TEGRA_WIN_FMT_YCbCr420P:
124 case TEGRA_WIN_FMT_YUV420P:
125 case TEGRA_WIN_FMT_YCbCr422P:
126 case TEGRA_WIN_FMT_YUV422P:
129 case TEGRA_WIN_FMT_YCbCr422:
130 case TEGRA_WIN_FMT_YUV422:
131 case TEGRA_WIN_FMT_YCbCr422R:
132 case TEGRA_WIN_FMT_YUV422R:
133 case TEGRA_WIN_FMT_YCbCr422RA:
134 case TEGRA_WIN_FMT_YUV422RA:
135 /* FIXME: need to know the bpp of these formats */
141 static inline bool tegra_dc_is_yuv_planar(int fmt)
144 case TEGRA_WIN_FMT_YUV420P:
145 case TEGRA_WIN_FMT_YCbCr420P:
146 case TEGRA_WIN_FMT_YCbCr422P:
147 case TEGRA_WIN_FMT_YUV422P:
153 #define DUMP_REG(a) do { \
154 snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
155 #a, a, tegra_dc_readl(dc, a)); \
159 static void _dump_regs(struct tegra_dc *dc, void *data,
160 void (* print)(void *data, const char *str))
165 tegra_dc_io_start(dc);
168 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
169 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
170 DUMP_REG(DC_CMD_SIGNAL_RAISE);
171 DUMP_REG(DC_CMD_INT_STATUS);
172 DUMP_REG(DC_CMD_INT_MASK);
173 DUMP_REG(DC_CMD_INT_ENABLE);
174 DUMP_REG(DC_CMD_INT_TYPE);
175 DUMP_REG(DC_CMD_INT_POLARITY);
176 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
177 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
178 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
179 DUMP_REG(DC_CMD_STATE_ACCESS);
180 DUMP_REG(DC_CMD_STATE_CONTROL);
181 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
182 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
184 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
185 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
186 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
187 DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
188 DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
189 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
190 DUMP_REG(DC_DISP_REF_TO_SYNC);
191 DUMP_REG(DC_DISP_SYNC_WIDTH);
192 DUMP_REG(DC_DISP_BACK_PORCH);
193 DUMP_REG(DC_DISP_DISP_ACTIVE);
194 DUMP_REG(DC_DISP_FRONT_PORCH);
195 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
196 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
197 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
198 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
199 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
200 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
201 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
202 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
203 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
204 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
205 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
206 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
207 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
208 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
209 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
210 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
211 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
212 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
213 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
214 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
215 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
216 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
217 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
218 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
219 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
220 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
221 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
222 DUMP_REG(DC_DISP_M0_CONTROL);
223 DUMP_REG(DC_DISP_M1_CONTROL);
224 DUMP_REG(DC_DISP_DI_CONTROL);
225 DUMP_REG(DC_DISP_PP_CONTROL);
226 DUMP_REG(DC_DISP_PP_SELECT_A);
227 DUMP_REG(DC_DISP_PP_SELECT_B);
228 DUMP_REG(DC_DISP_PP_SELECT_C);
229 DUMP_REG(DC_DISP_PP_SELECT_D);
230 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
231 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
232 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
233 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
234 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
235 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
236 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
237 DUMP_REG(DC_DISP_BORDER_COLOR);
238 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
239 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
240 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
241 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
242 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
243 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
244 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
245 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
246 DUMP_REG(DC_DISP_CURSOR_POSITION);
247 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
248 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
249 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
250 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
251 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
252 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
253 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
254 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
255 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
256 DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
257 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
258 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
259 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
262 for (i = 0; i < 3; i++) {
264 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
267 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
268 DC_CMD_DISPLAY_WINDOW_HEADER);
269 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
270 DUMP_REG(DC_WIN_WIN_OPTIONS);
271 DUMP_REG(DC_WIN_BYTE_SWAP);
272 DUMP_REG(DC_WIN_BUFFER_CONTROL);
273 DUMP_REG(DC_WIN_COLOR_DEPTH);
274 DUMP_REG(DC_WIN_POSITION);
275 DUMP_REG(DC_WIN_SIZE);
276 DUMP_REG(DC_WIN_PRESCALED_SIZE);
277 DUMP_REG(DC_WIN_H_INITIAL_DDA);
278 DUMP_REG(DC_WIN_V_INITIAL_DDA);
279 DUMP_REG(DC_WIN_DDA_INCREMENT);
280 DUMP_REG(DC_WIN_LINE_STRIDE);
281 DUMP_REG(DC_WIN_BUF_STRIDE);
282 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
283 DUMP_REG(DC_WIN_BLEND_NOKEY);
284 DUMP_REG(DC_WIN_BLEND_1WIN);
285 DUMP_REG(DC_WIN_BLEND_2WIN_X);
286 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
287 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
288 DUMP_REG(DC_WINBUF_START_ADDR);
289 DUMP_REG(DC_WINBUF_START_ADDR_U);
290 DUMP_REG(DC_WINBUF_START_ADDR_V);
291 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
292 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
293 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
294 DUMP_REG(DC_WIN_CSC_YOF);
295 DUMP_REG(DC_WIN_CSC_KYRGB);
296 DUMP_REG(DC_WIN_CSC_KUR);
297 DUMP_REG(DC_WIN_CSC_KVR);
298 DUMP_REG(DC_WIN_CSC_KUG);
299 DUMP_REG(DC_WIN_CSC_KVG);
300 DUMP_REG(DC_WIN_CSC_KUB);
301 DUMP_REG(DC_WIN_CSC_KVB);
304 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
305 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
306 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
307 DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
308 DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
309 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
310 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
311 DUMP_REG(DC_DISP_M1_CONTROL);
312 DUMP_REG(DC_COM_PM1_CONTROL);
313 DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
314 DUMP_REG(DC_DISP_SD_CONTROL);
316 clk_disable(dc->clk);
323 static void dump_regs_print(void *data, const char *str)
325 struct tegra_dc *dc = data;
326 dev_dbg(&dc->ndev->dev, "%s", str);
329 static void dump_regs(struct tegra_dc *dc)
331 _dump_regs(dc, dc, dump_regs_print);
335 static void dump_regs(struct tegra_dc *dc) {}
339 #ifdef CONFIG_DEBUG_FS
341 static void dbg_regs_print(void *data, const char *str)
343 struct seq_file *s = data;
345 seq_printf(s, "%s", str);
350 static int dbg_dc_show(struct seq_file *s, void *unused)
352 struct tegra_dc *dc = s->private;
354 _dump_regs(dc, s, dbg_regs_print);
360 static int dbg_dc_open(struct inode *inode, struct file *file)
362 return single_open(file, dbg_dc_show, inode->i_private);
365 static const struct file_operations regs_fops = {
369 .release = single_release,
372 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
374 struct tegra_dc *dc = s->private;
375 struct tegra_dc_mode *m;
377 mutex_lock(&dc->lock);
381 "h_ref_to_sync: %d\n"
382 "v_ref_to_sync: %d\n"
389 "h_front_porch: %d\n"
390 "v_front_porch: %d\n"
392 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
393 m->h_sync_width, m->v_sync_width,
394 m->h_back_porch, m->v_back_porch,
395 m->h_active, m->v_active,
396 m->h_front_porch, m->v_front_porch,
398 mutex_unlock(&dc->lock);
402 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
404 return single_open(file, dbg_dc_mode_show, inode->i_private);
407 static const struct file_operations mode_fops = {
408 .open = dbg_dc_mode_open,
411 .release = single_release,
414 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
416 struct tegra_dc *dc = s->private;
418 mutex_lock(&dc->lock);
423 "underflows_c: %u\n",
424 dc->stats.underflows,
425 dc->stats.underflows_a,
426 dc->stats.underflows_b,
427 dc->stats.underflows_c);
428 mutex_unlock(&dc->lock);
433 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
435 return single_open(file, dbg_dc_stats_show, inode->i_private);
438 static const struct file_operations stats_fops = {
439 .open = dbg_dc_stats_open,
442 .release = single_release,
445 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
448 debugfs_remove_recursive(dc->debugdir);
452 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
454 struct dentry *retval;
456 dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
460 retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
465 retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
470 retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
477 dev_err(&dc->ndev->dev, "could not create debugfs\n");
478 tegra_dc_remove_debugfs(dc);
481 #else /* !CONFIG_DEBUGFS */
482 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
483 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
484 #endif /* CONFIG_DEBUGFS */
486 static int tegra_dc_set(struct tegra_dc *dc, int index)
490 mutex_lock(&tegra_dc_lock);
491 if (index >= TEGRA_MAX_DC) {
496 if (dc != NULL && tegra_dcs[index] != NULL) {
501 tegra_dcs[index] = dc;
504 mutex_unlock(&tegra_dc_lock);
509 unsigned int tegra_dc_has_multiple_dc(void)
512 unsigned int cnt = 0;
515 mutex_lock(&tegra_dc_lock);
516 for (idx = 0; idx < TEGRA_MAX_DC; idx++)
517 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
518 mutex_unlock(&tegra_dc_lock);
523 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
525 if (idx < TEGRA_MAX_DC)
526 return tegra_dcs[idx];
530 EXPORT_SYMBOL(tegra_dc_get_dc);
532 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
534 if (win >= dc->n_windows)
537 return &dc->windows[win];
539 EXPORT_SYMBOL(tegra_dc_get_window);
541 static int get_topmost_window(u32 *depths, unsigned long *wins)
545 for_each_set_bit(idx, wins, DC_N_WINDOWS) {
546 if (best == -1 || depths[idx] < depths[best])
549 clear_bit(best, wins);
553 bool tegra_dc_get_connected(struct tegra_dc *dc)
555 return dc->connected;
557 EXPORT_SYMBOL(tegra_dc_get_connected);
559 static u32 blend_topwin(u32 flags)
561 if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
562 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
563 else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
564 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
566 return BLEND(NOKEY, FIX, 0xff, 0xff);
569 static u32 blend_2win(int idx, unsigned long behind_mask, u32* flags, int xy)
573 for (other = 0; other < DC_N_WINDOWS; other++) {
574 if (other != idx && (xy-- == 0))
577 if (BIT(other) & behind_mask)
578 return blend_topwin(flags[idx]);
579 else if (flags[other])
580 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
582 return BLEND(NOKEY, FIX, 0x00, 0x00);
585 static u32 blend_3win(int idx, unsigned long behind_mask, u32* flags)
587 unsigned long infront_mask;
590 infront_mask = ~(behind_mask | BIT(idx));
591 infront_mask &= (BIT(DC_N_WINDOWS) - 1);
592 first = ffs(infront_mask) - 1;
595 return blend_topwin(flags[idx]);
596 else if (behind_mask && first != -1 && flags[first])
597 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
599 return BLEND(NOKEY, FIX, 0x0, 0x0);
602 static void tegra_dc_set_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
604 unsigned long mask = BIT(DC_N_WINDOWS) - 1;
607 int idx = get_topmost_window(blend->z, &mask);
609 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
610 DC_CMD_DISPLAY_WINDOW_HEADER);
611 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
613 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
615 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0),
616 DC_WIN_BLEND_2WIN_X);
617 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1),
618 DC_WIN_BLEND_2WIN_Y);
619 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags),
620 DC_WIN_BLEND_3WIN_XY);
624 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
636 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
638 tegra_dc_writel(dc, csc->yof, DC_WIN_CSC_YOF);
639 tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
640 tegra_dc_writel(dc, csc->kur, DC_WIN_CSC_KUR);
641 tegra_dc_writel(dc, csc->kvr, DC_WIN_CSC_KVR);
642 tegra_dc_writel(dc, csc->kug, DC_WIN_CSC_KUG);
643 tegra_dc_writel(dc, csc->kvg, DC_WIN_CSC_KVG);
644 tegra_dc_writel(dc, csc->kub, DC_WIN_CSC_KUB);
645 tegra_dc_writel(dc, csc->kvb, DC_WIN_CSC_KVB);
648 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
650 mutex_lock(&dc->lock);
653 mutex_unlock(&dc->lock);
657 tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
658 DC_CMD_DISPLAY_WINDOW_HEADER);
660 tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
662 mutex_unlock(&dc->lock);
666 EXPORT_SYMBOL(tegra_dc_update_csc);
668 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
673 /* linear horizontal and vertical filters */
674 for (i = 0; i < 16; i++) {
675 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
676 DC_WIN_H_FILTER_P(i));
678 tegra_dc_writel(dc, v0,
679 DC_WIN_V_FILTER_P(i));
685 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
686 struct tegra_dc_win *w)
688 /* windows A, B, C for first and second display */
689 static const enum tegra_la_id la_id_tab[2][3] = {
691 { TEGRA_LA_DISPLAY_0A, TEGRA_LA_DISPLAY_0B,
692 TEGRA_LA_DISPLAY_0C },
694 { TEGRA_LA_DISPLAY_0AB, TEGRA_LA_DISPLAY_0BB,
695 TEGRA_LA_DISPLAY_0CB },
697 /* window B V-filter tap for first and second display. */
698 static const enum tegra_la_id vfilter_tab[2] = {
699 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
703 BUG_ON(dc->ndev->id >= ARRAY_SIZE(la_id_tab));
704 BUG_ON(dc->ndev->id >= ARRAY_SIZE(vfilter_tab));
705 BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
707 bw = w->new_bandwidth;
709 /* tegra_dc_get_bandwidth() treats V filter windows as double
710 * bandwidth, but LA has a seperate client for V filter */
711 if (w->idx == 1 && win_use_v_filter(w))
714 /* our bandwidth is in bytes/sec, but LA takes MBps.
715 * round up bandwidth to 1MBps */
716 bw = bw / 1000000 + 1;
718 tegra_set_latency_allowance(la_id_tab[dc->ndev->id][w->idx], bw);
720 /* if window B, also set the 1B client for the 2-tap V filter. */
722 tegra_set_latency_allowance(vfilter_tab[dc->ndev->id], bw);
724 w->bandwidth = w->new_bandwidth;
727 static unsigned int tegra_dc_windows_is_overlapped(struct tegra_dc_win *a,
728 struct tegra_dc_win *b)
730 if (!WIN_IS_ENABLED(a) || !WIN_IS_ENABLED(b))
733 /* because memory access to load the fifo can overlap, only care
734 * if windows overlap vertically */
735 return ((a->out_y + a->out_h > b->out_y) && (a->out_y <= b->out_y)) ||
736 ((b->out_y + b->out_h > a->out_y) && (b->out_y <= a->out_y));
739 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
744 unsigned overlap_count;
747 WARN_ONCE(n > 3, "Code assumes at most 3 windows, bandwidth is likely"
750 /* If we had a large number of windows, we would compute adjacency
751 * graph representing 2 window overlaps, find all cliques in the graph,
752 * assign bandwidth to each clique, and then select the clique with
753 * maximum bandwidth. But because we have at most 3 windows,
754 * implementing proper Bron-Kerbosh algorithm would be an overkill,
755 * brute force will suffice.
757 * Thus: find maximum bandwidth for either single or a pair of windows
758 * and count number of window pair overlaps. If there are three
759 * pairs, all 3 window overlap.
763 for (i = 0; i < n; i++) {
768 bw1 = wins[i]->new_bandwidth;
773 for (j = i + 1; j < n; j++) {
776 if (tegra_dc_windows_is_overlapped(wins[i], wins[j])) {
777 unsigned int bw2 = wins[j]->new_bandwidth;
778 if (bw1 + bw2 > max_bw)
779 /* Window pair overlaps */
786 if (overlap_count == 3)
787 /* All three windows overlap */
788 max_bw = wins[0]->new_bandwidth + wins[1]->new_bandwidth +
789 wins[2]->new_bandwidth;
795 * Calculate peak EMC bandwidth for each enabled window =
796 * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
797 * (windows_tiling ? 2 : 1)
801 * (*) We use 2 tap V filter, so need double BW if use V filter
802 * (*) Tiling mode on T30 and DDR3 requires double BW
804 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
805 struct tegra_dc_win *w)
808 int tiled_windows_bw_multiplier;
811 if (!WIN_IS_ENABLED(w))
814 if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
815 w->out_w == 0 || w->out_h == 0)
818 tiled_windows_bw_multiplier =
819 tegra_mc_get_tiled_memory_bandwidth_multiplier();
821 /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
822 * but the size reported by tegra_dc_fmt_bpp for the planar version
823 * is of the luma plane's size only. */
824 bpp = tegra_dc_is_yuv_planar(w->fmt) ?
825 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
826 /* perform calculations with most significant bits of pixel clock
827 * to prevent overflow of long. */
828 ret = (unsigned long)(dc->pixel_clk >> 16) *
830 (win_use_v_filter(w) ? 2 : 1) * dfixed_trunc(w->w) / w->out_w *
831 (WIN_IS_TILED(w) ? tiled_windows_bw_multiplier : 1);
834 * Assuming 50% (X >> 1) efficiency: i.e. if we calculate we need 70MBps, we
835 * will request 140MBps from EMC.
837 #define MEM_EFFICIENCY_SHIFT 1
838 ret <<= MEM_EFFICIENCY_SHIFT;
839 #undef MEM_EFFICIENCY_SHIFT
842 if (ret > (1UL << 31))
845 return ret << 16; /* restore the scaling we did above */
848 unsigned long tegra_dc_get_bandwidth(struct tegra_dc_win *windows[], int n)
852 BUG_ON(n > DC_N_WINDOWS);
854 /* emc rate and latency allowance both need to know per window
856 for (i = 0; i < n; i++) {
857 struct tegra_dc_win *w = windows[i];
859 w->new_bandwidth = tegra_dc_calc_win_bandwidth(w->dc, w);
862 return tegra_dc_find_max_bandwidth(windows, n);
865 static void tegra_dc_program_bandwidth(struct tegra_dc *dc)
869 if (dc->emc_clk_rate != dc->new_emc_clk_rate) {
870 dc->emc_clk_rate = dc->new_emc_clk_rate;
871 clk_set_rate(dc->emc_clk, dc->emc_clk_rate);
874 for (i = 0; i < DC_N_WINDOWS; i++) {
875 struct tegra_dc_win *w = &dc->windows[i];
876 if (w->bandwidth != w->new_bandwidth)
877 tegra_dc_set_latency_allowance(dc, w);
881 static int tegra_dc_set_dynamic_emc(struct tegra_dc_win *windows[], int n)
883 unsigned long new_rate;
886 if (!use_dynamic_emc)
891 /* calculate the new rate based on this POST */
892 new_rate = tegra_dc_get_bandwidth(windows, n);
893 new_rate = EMC_BW_TO_FREQ(new_rate);
895 if (tegra_dc_has_multiple_dc())
896 new_rate = ULONG_MAX;
898 dc->new_emc_clk_rate = new_rate;
903 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
904 bool v, unsigned Bpp)
907 * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
908 * (post_scaled_size_in_pixels - 1)), MAX)
909 * Where the value of MAX is as follows:
910 * For V_DDA_INCREMENT: 15.0 (0xF000)
911 * For H_DDA_INCREMENT: 4.0 (0x4000) for 4 Bytes/pix formats.
912 * 8.0 (0x8000) for 2 Bytes/pix formats.
915 fixed20_12 out = dfixed_init(out_int);
935 out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
936 in.full -= dfixed_const(1);
938 dda_inc = dfixed_div(in, out);
940 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
945 static inline u32 compute_initial_dda(fixed20_12 in)
947 return dfixed_frac(in);
950 /* does not support updating windows on multiple dcs in one call */
951 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
954 unsigned long update_mask = GENERAL_ACT_REQ;
956 bool update_blend = false;
961 mutex_lock(&dc->lock);
964 mutex_unlock(&dc->lock);
969 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
971 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
973 for (i = 0; i < n; i++) {
974 struct tegra_dc_win *win = windows[i];
977 fixed20_12 h_offset, v_offset;
978 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
979 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
980 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
981 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
982 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
983 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
984 const bool filter_h = win_use_h_filter(win);
985 const bool filter_v = win_use_v_filter(win);
987 if (win->z != dc->blend.z[win->idx]) {
988 dc->blend.z[win->idx] = win->z;
991 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
992 dc->blend.flags[win->idx]) {
993 dc->blend.flags[win->idx] =
994 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
998 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
999 DC_CMD_DISPLAY_WINDOW_HEADER);
1002 update_mask |= WIN_A_ACT_REQ << win->idx;
1004 if (!WIN_IS_ENABLED(win)) {
1005 tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1009 tegra_dc_writel(dc, win->fmt, DC_WIN_COLOR_DEPTH);
1010 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
1013 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1016 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1019 V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1020 H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1021 DC_WIN_PRESCALED_SIZE);
1023 h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1024 v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1025 tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1026 DC_WIN_DDA_INCREMENT);
1027 h_dda = compute_initial_dda(win->x);
1028 v_dda = compute_initial_dda(win->y);
1029 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1030 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1032 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1033 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1035 (unsigned long)win->phys_addr +
1036 (unsigned long)win->offset,
1037 DC_WINBUF_START_ADDR);
1040 tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1043 (unsigned long)win->phys_addr +
1044 (unsigned long)win->offset_u,
1045 DC_WINBUF_START_ADDR_U);
1047 (unsigned long)win->phys_addr +
1048 (unsigned long)win->offset_v,
1049 DC_WINBUF_START_ADDR_V);
1051 LINE_STRIDE(win->stride) |
1052 UV_LINE_STRIDE(win->stride_uv),
1053 DC_WIN_LINE_STRIDE);
1058 h_offset.full += win->w.full - dfixed_const(1);
1063 v_offset.full += win->h.full - dfixed_const(1);
1066 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1067 DC_WINBUF_ADDR_H_OFFSET);
1068 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1069 DC_WINBUF_ADDR_V_OFFSET);
1071 if (WIN_IS_TILED(win))
1073 DC_WIN_BUFFER_ADDR_MODE_TILE |
1074 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1075 DC_WIN_BUFFER_ADDR_MODE);
1078 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1079 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1080 DC_WIN_BUFFER_ADDR_MODE);
1085 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1086 val |= COLOR_EXPAND;
1089 val |= H_FILTER_ENABLE;
1091 val |= V_FILTER_ENABLE;
1094 val |= H_DIRECTION_DECREMENT;
1096 val |= V_DIRECTION_DECREMENT;
1098 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1100 win->dirty = no_vsync ? 0 : 1;
1104 tegra_dc_set_blending(dc, &dc->blend);
1105 for (i = 0; i < DC_N_WINDOWS; i++) {
1107 dc->windows[i].dirty = 1;
1108 update_mask |= WIN_A_ACT_REQ << i;
1112 tegra_dc_set_dynamic_emc(windows, n);
1114 tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1117 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1118 val |= (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1119 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1121 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1122 val &= ~(FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1124 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1127 tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1129 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1130 tegra_dc_writel(dc, NC_HOST_TRIG, DC_CMD_STATE_CONTROL);
1132 mutex_unlock(&dc->lock);
1136 EXPORT_SYMBOL(tegra_dc_update_windows);
1138 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1140 return dc->syncpt[i].id;
1142 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1144 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1148 mutex_lock(&dc->lock);
1149 max = nvhost_syncpt_incr_max(&dc->ndev->host->syncpt,
1150 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1151 dc->syncpt[i].max = max;
1152 mutex_unlock(&dc->lock);
1157 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1159 mutex_lock(&dc->lock);
1161 while (dc->syncpt[i].min < val) {
1162 dc->syncpt[i].min++;
1163 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
1166 mutex_unlock(&dc->lock);
1169 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1174 for (i = 0; i < n; i++) {
1175 if (windows[i]->dirty)
1182 /* does not support syncing windows on multiple dcs in one call */
1183 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1185 if (n < 1 || n > DC_N_WINDOWS)
1188 if (!windows[0]->dc->enabled)
1191 return wait_event_interruptible_timeout(windows[0]->dc->wq,
1192 tegra_dc_windows_are_clean(windows, n),
1195 EXPORT_SYMBOL(tegra_dc_sync_windows);
1197 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1199 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1202 return clk_get_rate(dc->clk);
1206 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1211 rate = tegra_dc_clk_get_rate(dc);
1213 div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1218 return rate * 2 / div;
1221 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1225 if (dc->out->type == TEGRA_DC_OUT_RGB) {
1226 struct clk *parent_clk =
1227 clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1229 if (clk_get_parent(clk) != parent_clk)
1230 clk_set_parent(clk, parent_clk);
1233 if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1235 struct clk *parent_clk =
1236 clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1237 struct clk *base_clk = clk_get_parent(parent_clk);
1239 /* needs to match tegra_dc_hdmi_supported_modes[]
1240 and tegra_pll_d_freq_table[] */
1241 if (dc->mode.pclk > 70000000)
1243 else if (dc->mode.pclk > 25200000)
1248 if (rate != clk_get_rate(base_clk))
1249 clk_set_rate(base_clk, rate);
1251 if (clk_get_parent(clk) != parent_clk)
1252 clk_set_parent(clk, parent_clk);
1255 if (dc->out->type == TEGRA_DC_OUT_DSI) {
1257 struct clk *parent_clk;
1258 struct clk *base_clk;
1260 if (clk == dc->clk) {
1261 parent_clk = clk_get_sys(NULL,
1262 dc->out->parent_clk ? : "pll_d_out0");
1263 base_clk = clk_get_parent(parent_clk);
1264 tegra_clk_cfg_ex(base_clk,
1265 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1267 if (dc->pdata->default_out->dsi->dsi_instance) {
1268 parent_clk = clk_get_sys(NULL,
1269 dc->out->parent_clk ? : "pll_d2_out0");
1270 base_clk = clk_get_parent(parent_clk);
1271 tegra_clk_cfg_ex(base_clk,
1272 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1274 parent_clk = clk_get_sys(NULL,
1275 dc->out->parent_clk ? : "pll_d_out0");
1276 base_clk = clk_get_parent(parent_clk);
1277 tegra_clk_cfg_ex(base_clk,
1278 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1282 rate = dc->mode.pclk;
1283 if (rate != clk_get_rate(base_clk))
1284 clk_set_rate(base_clk, rate);
1286 if (clk_get_parent(clk) != parent_clk)
1287 clk_set_parent(clk, parent_clk);
1290 pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1291 tegra_dvfs_set_rate(clk, pclk);
1294 /* return non-zero if constraint is violated */
1295 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1299 /* Constraint 5: H_REF_TO_SYNC >= 0 */
1302 /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1303 b = mode->h_front_porch - 1;
1305 /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1306 if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1307 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1308 /* check Constraint 1 and 6 */
1312 /* Constraint 4: H_SYNC_WIDTH >= 1 */
1313 if (mode->h_sync_width < 1)
1316 /* Constraint 7: H_DISP_ACTIVE >= 16 */
1317 if (mode->h_active < 16)
1322 *href = a + 1; /* use smallest even value */
1324 *href = a; /* even or only possible value */
1330 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1333 a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1335 /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1336 if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1337 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1340 if (mode->v_front_porch < a + 1)
1341 a = mode->v_front_porch - 1;
1343 /* Constraint 4: V_SYNC_WIDTH >= 1 */
1344 if (mode->v_sync_width < 1)
1347 /* Constraint 7: V_DISP_ACTIVE >= 16 */
1348 if (mode->v_active < 16)
1356 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1359 ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1362 ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1369 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1371 /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1372 if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1375 /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1376 if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1379 /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1380 * (vertical blank). */
1381 if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1384 /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1385 if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1388 /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1389 if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1392 /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1393 * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1394 if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1395 mode->h_front_porch < mode->h_ref_to_sync + 1)
1398 /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1399 if (mode->h_active < 16 || mode->v_active < 16)
1406 /* return in 1000ths of a Hertz */
1407 static int calc_refresh(struct tegra_dc *dc, const struct tegra_dc_mode *m)
1409 long h_total, v_total, refresh;
1410 h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1412 v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1414 refresh = dc->pixel_clk / h_total;
1420 static void print_mode(struct tegra_dc *dc,
1421 const struct tegra_dc_mode *mode, const char *note)
1424 int refresh = calc_refresh(mode);
1425 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1427 mode->h_active, mode->v_active,
1428 refresh / 1000, refresh % 1000,
1433 static inline void print_mode(struct tegra_dc *dc,
1434 const struct tegra_dc_mode *mode, const char *note) { }
1437 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1444 print_mode(dc, mode, __func__);
1446 /* use default EMC rate when switching modes */
1447 dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1448 tegra_dc_program_bandwidth(dc);
1450 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1451 tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1452 DC_DISP_REF_TO_SYNC);
1453 tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1454 DC_DISP_SYNC_WIDTH);
1455 tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1456 DC_DISP_BACK_PORCH);
1457 tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1458 DC_DISP_DISP_ACTIVE);
1459 tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1460 DC_DISP_FRONT_PORCH);
1462 tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1463 DC_DISP_DATA_ENABLE_OPTIONS);
1465 val = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1466 if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1467 val |= PIN1_LVS_OUTPUT;
1469 val &= ~PIN1_LVS_OUTPUT;
1471 if (mode->flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1472 val |= PIN1_LHS_OUTPUT;
1474 val &= ~PIN1_LHS_OUTPUT;
1475 tegra_dc_writel(dc, val, DC_COM_PIN_OUTPUT_POLARITY1);
1477 /* TODO: MIPI/CRT/HDMI clock cals */
1479 val = DISP_DATA_FORMAT_DF1P1C;
1481 if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1482 val |= DISP_DATA_ALIGNMENT_MSB;
1484 val |= DISP_DATA_ALIGNMENT_LSB;
1486 if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1487 val |= DISP_DATA_ORDER_RED_BLUE;
1489 val |= DISP_DATA_ORDER_BLUE_RED;
1491 tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1493 rate = tegra_dc_clk_get_rate(dc);
1495 pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1496 if (pclk < (mode->pclk / 100 * 99) ||
1497 pclk > (mode->pclk / 100 * 109)) {
1498 dev_err(&dc->ndev->dev,
1499 "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1501 pclk, (mode->pclk / 100 * 99),
1502 (mode->pclk / 100 * 109));
1506 div = (rate * 2 / pclk) - 2;
1508 tegra_dc_writel(dc, 0x00010001,
1509 DC_DISP_SHIFT_CLOCK_OPTIONS);
1510 tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1511 DC_DISP_DISP_CLOCK_CONTROL);
1513 dc->pixel_clk = dc->mode.pclk;
1519 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1521 memcpy(&dc->mode, mode, sizeof(dc->mode));
1523 print_mode(dc, mode, __func__);
1527 EXPORT_SYMBOL(tegra_dc_set_mode);
1529 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1530 const struct fb_videomode *fbmode, bool stereo_mode)
1532 struct tegra_dc_mode mode;
1534 if (!fbmode->pixclock)
1537 mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1538 mode.h_sync_width = fbmode->hsync_len;
1539 mode.v_sync_width = fbmode->vsync_len;
1540 mode.h_back_porch = fbmode->left_margin;
1541 mode.v_back_porch = fbmode->upper_margin;
1542 mode.h_active = fbmode->xres;
1543 mode.v_active = fbmode->yres;
1544 mode.h_front_porch = fbmode->right_margin;
1545 mode.v_front_porch = fbmode->lower_margin;
1546 mode.stereo_mode = stereo_mode;
1547 if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1548 /* HDMI controller requires h_ref=1, v_ref=1 */
1549 mode.h_ref_to_sync = 1;
1550 mode.v_ref_to_sync = 1;
1552 calc_ref_to_sync(&mode);
1554 if (!check_ref_to_sync(&mode)) {
1555 dev_err(&dc->ndev->dev,
1556 "Display timing doesn't meet restrictions.\n");
1559 dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1560 mode.h_active, mode.v_active, mode.pclk,
1561 mode.h_ref_to_sync, mode.v_ref_to_sync
1564 if (mode.stereo_mode) {
1566 /* total v_active = yres*2 + activespace */
1567 mode.v_active = fbmode->yres*2 +
1569 fbmode->upper_margin +
1570 fbmode->lower_margin;
1575 if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1576 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1578 if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1579 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1581 return tegra_dc_set_mode(dc, &mode);
1583 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1586 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1589 unsigned long out_sel;
1590 unsigned long cmd_state;
1592 mutex_lock(&dc->lock);
1594 mutex_unlock(&dc->lock);
1598 ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1599 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1602 /* The new value should be effected immediately */
1603 cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1604 tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1606 if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1607 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1609 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1611 switch (cfg->which_pwm) {
1613 /* Select the LM0 on PM0 */
1614 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1615 out_sel &= ~(7 << 0);
1616 out_sel |= (3 << 0);
1617 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1618 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1619 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1622 /* Select the LM1 on PM1 */
1623 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1624 out_sel &= ~(7 << 4);
1625 out_sel |= (3 << 4);
1626 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1627 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1628 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1631 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1634 tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1635 mutex_unlock(&dc->lock);
1637 EXPORT_SYMBOL(tegra_dc_config_pwm);
1639 static void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1640 const struct tegra_dc_out_pin *pins,
1641 const unsigned int n_pins)
1653 set1 = set3 = unset1 = unset3 = 0;
1655 for (i = 0; i < n_pins; i++) {
1656 name = (pins + i)->name;
1657 pol = (pins + i)->pol;
1659 /* set polarity by name */
1661 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1662 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1663 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1665 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1667 case TEGRA_DC_OUT_PIN_H_SYNC:
1668 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1669 set1 |= LHS_OUTPUT_POLARITY_LOW;
1671 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1673 case TEGRA_DC_OUT_PIN_V_SYNC:
1674 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1675 set1 |= LVS_OUTPUT_POLARITY_LOW;
1677 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1679 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1680 if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1681 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1683 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1686 printk("Invalid argument in function %s\n",
1692 pol1 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY1);
1693 pol3 = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY3);
1701 tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1702 tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1705 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1709 if (out->n_modes > 0)
1710 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1712 switch (out->type) {
1713 case TEGRA_DC_OUT_RGB:
1714 dc->out_ops = &tegra_dc_rgb_ops;
1717 case TEGRA_DC_OUT_HDMI:
1718 dc->out_ops = &tegra_dc_hdmi_ops;
1721 case TEGRA_DC_OUT_DSI:
1722 dc->out_ops = &tegra_dc_dsi_ops;
1730 if (dc->out_ops && dc->out_ops->init)
1731 dc->out_ops->init(dc);
1735 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1738 return dc->out->height;
1742 EXPORT_SYMBOL(tegra_dc_get_out_height);
1744 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1747 return dc->out->width;
1751 EXPORT_SYMBOL(tegra_dc_get_out_width);
1753 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1755 if (dc->out && dc->out->max_pixclock)
1756 return dc->out->max_pixclock;
1760 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1762 void tegra_dc_enable_crc(struct tegra_dc *dc)
1765 tegra_dc_io_start(dc);
1767 val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1769 tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1770 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1771 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1774 void tegra_dc_disable_crc(struct tegra_dc *dc)
1776 tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1777 tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1778 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1780 tegra_dc_io_end(dc);
1783 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1788 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1792 /* TODO: Replace mdelay with code to sync VBlANK, since
1793 * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1794 mdelay(TEGRA_CRC_LATCHED_DELAY);
1796 crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1801 static void tegra_dc_vblank(struct work_struct *work)
1803 struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1804 bool nvsd_updated = false;
1806 mutex_lock(&dc->lock);
1808 /* update EMC clock if calculated bandwidth has changed */
1809 tegra_dc_program_bandwidth(dc);
1811 /* Update the SD brightness */
1812 nvsd_updated = nvsd_update_brightness(dc);
1814 mutex_unlock(&dc->lock);
1816 /* Do the actual brightness update outside of the mutex */
1817 if (nvsd_updated && dc->out->sd_settings &&
1818 dc->out->sd_settings->bl_device) {
1820 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1821 struct backlight_device *bl = platform_get_drvdata(pdev);
1823 backlight_update_status(bl);
1827 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1828 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1832 /* Check for any underflow reset conditions */
1833 for (i = 0; i < DC_N_WINDOWS; i++) {
1834 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1835 dc->windows[i].underflows++;
1837 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1838 if (dc->windows[i].underflows > 4)
1839 schedule_work(&dc->reset_work);
1842 dc->windows[i].underflows = 0;
1846 if (!dc->underflow_mask) {
1847 /* If we have no underflow to check, go ahead
1848 and disable the interrupt */
1849 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1850 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1851 val &= ~FRAME_END_INT;
1853 val &= ~V_BLANK_INT;
1854 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1857 /* Clear the underflow mask now that we've checked it. */
1858 dc->underflow_mask = 0;
1861 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
1867 val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1868 for (i = 0; i < DC_N_WINDOWS; i++) {
1869 if (!(val & (WIN_A_UPDATE << i))) {
1870 dc->windows[i].dirty = 0;
1878 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1879 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1880 val &= ~V_BLANK_INT;
1882 val &= ~FRAME_END_INT;
1883 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1888 /* With the last completed window, go ahead
1889 and enable the vblank interrupt for nvsd. */
1890 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1892 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1894 val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1896 tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1903 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1905 if (status & V_BLANK_INT) {
1906 /* Sync up windows. */
1907 tegra_dc_trigger_windows(dc);
1909 /* Schedule any additional bottom-half vblank actvities. */
1910 schedule_work(&dc->vblank_work);
1912 /* Mark the vblank as complete. */
1913 complete(&dc->vblank_complete);
1917 /* Check underflow at frame end */
1918 if (status & FRAME_END_INT)
1919 tegra_dc_underflow_handler(dc);
1922 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1924 if (status & V_BLANK_INT) {
1925 /* Check underflow */
1926 tegra_dc_underflow_handler(dc);
1928 /* Schedule any additional bottom-half vblank actvities. */
1929 schedule_work(&dc->vblank_work);
1931 /* Mark the vblank as complete. */
1932 complete(&dc->vblank_complete);
1935 if (status & FRAME_END_INT)
1936 tegra_dc_trigger_windows(dc);
1940 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1942 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1943 struct tegra_dc *dc = ptr;
1944 unsigned long status;
1946 unsigned long underflow_mask;
1948 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1949 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1952 * Overlays can get thier internal state corrupted during and underflow
1953 * condition. The only way to fix this state is to reset the DC.
1954 * if we get 4 consecutive frames with underflows, assume we're
1957 underflow_mask = status & ALL_UF_INT;
1959 if (underflow_mask) {
1960 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1962 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1963 dc->underflow_mask |= underflow_mask;
1964 dc->stats.underflows++;
1965 if (status & WIN_A_UF_INT)
1966 dc->stats.underflows_a++;
1967 if (status & WIN_B_UF_INT)
1968 dc->stats.underflows_b++;
1969 if (status & WIN_C_UF_INT)
1970 dc->stats.underflows_c++;
1973 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1974 tegra_dc_one_shot_irq(dc, status);
1976 tegra_dc_continuous_irq(dc, status);
1979 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1981 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1984 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1988 switch (dc->out->depth) {
1990 color_control = BASE_COLOR_SIZE111;
1994 color_control = BASE_COLOR_SIZE222;
1998 color_control = BASE_COLOR_SIZE332;
2002 color_control = BASE_COLOR_SIZE333;
2006 color_control = BASE_COLOR_SIZE444;
2010 color_control = BASE_COLOR_SIZE555;
2014 color_control = BASE_COLOR_SIZE565;
2018 color_control = BASE_COLOR_SIZE666;
2022 color_control = BASE_COLOR_SIZE888;
2026 switch (dc->out->dither) {
2027 case TEGRA_DC_DISABLE_DITHER:
2028 color_control |= DITHER_CONTROL_DISABLE;
2030 case TEGRA_DC_ORDERED_DITHER:
2031 color_control |= DITHER_CONTROL_ORDERED;
2033 case TEGRA_DC_ERRDIFF_DITHER:
2034 /* The line buffer for error-diffusion dither is limited
2035 * to 640 pixels per line. This limits the maximum
2036 * horizontal active area size to 640 pixels when error
2037 * diffusion is enabled.
2039 BUG_ON(dc->mode.h_active > 640);
2040 color_control |= DITHER_CONTROL_ERRDIFF;
2044 tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2047 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2051 switch (dc->ndev->id) {
2055 syncpt_id = NVSYNCPT_DISP0_A;
2058 syncpt_id = NVSYNCPT_DISP0_B;
2061 syncpt_id = NVSYNCPT_DISP0_C;
2071 syncpt_id = NVSYNCPT_DISP1_A;
2074 syncpt_id = NVSYNCPT_DISP1_B;
2077 syncpt_id = NVSYNCPT_DISP1_C;
2092 static void tegra_dc_init(struct tegra_dc *dc)
2096 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2097 if (dc->ndev->id == 0) {
2098 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2100 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2102 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2104 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2106 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2107 TEGRA_MC_PRIO_HIGH);
2108 } else if (dc->ndev->id == 1) {
2109 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2111 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2113 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2115 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2117 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2118 TEGRA_MC_PRIO_HIGH);
2120 tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2121 DC_CMD_CONT_SYNCPT_VSYNC);
2122 tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2123 tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2124 tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2125 tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2127 tegra_dc_writel(dc, (FRAME_END_INT |
2129 ALL_UF_INT), DC_CMD_INT_MASK);
2130 tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_ENABLE);
2132 tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2134 tegra_dc_set_color_control(dc);
2135 for (i = 0; i < DC_N_WINDOWS; i++) {
2136 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2137 DC_CMD_DISPLAY_WINDOW_HEADER);
2138 tegra_dc_init_csc_defaults(&dc->windows[i].csc);
2139 tegra_dc_set_csc(dc, &dc->windows[i].csc);
2140 tegra_dc_set_scaling_filter(dc);
2144 for (i = 0; i < dc->n_windows; i++) {
2145 u32 syncpt = get_syncpt(dc, i);
2147 dc->syncpt[i].id = syncpt;
2149 dc->syncpt[i].min = dc->syncpt[i].max =
2150 nvhost_syncpt_read(&dc->ndev->host->syncpt, syncpt);
2153 print_mode(dc, &dc->mode, __func__);
2156 tegra_dc_program_mode(dc, &dc->mode);
2158 /* Initialize SD AFTER the modeset.
2159 nvsd_init handles the sd_settings = NULL case. */
2160 nvsd_init(dc, dc->out->sd_settings);
2163 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2165 if (dc->out->enable)
2168 tegra_dc_setup_clk(dc, dc->clk);
2169 tegra_periph_reset_assert(dc->clk);
2170 clk_enable(dc->clk);
2171 clk_enable(dc->emc_clk);
2172 enable_irq(dc->irq);
2176 if (dc->out_ops && dc->out_ops->enable)
2177 dc->out_ops->enable(dc);
2179 if (dc->out->out_pins)
2180 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2181 dc->out->n_out_pins);
2183 if (dc->out->postpoweron)
2184 dc->out->postpoweron();
2186 /* force a full blending update */
2187 dc->blend.z[0] = -1;
2189 tegra_dc_ext_enable(dc->ext);
2194 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2195 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2197 if (dc->out->enable)
2200 tegra_dc_setup_clk(dc, dc->clk);
2201 clk_enable(dc->clk);
2202 clk_enable(dc->emc_clk);
2204 if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2205 mutex_lock(&tegra_dcs[1]->lock);
2206 disable_irq(tegra_dcs[1]->irq);
2207 } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2208 mutex_lock(&tegra_dcs[0]->lock);
2209 disable_irq(tegra_dcs[0]->irq);
2213 tegra_periph_reset_assert(dc->clk);
2215 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2216 tegra_periph_reset_deassert(dc->clk);
2220 if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2221 enable_irq(tegra_dcs[1]->irq);
2222 mutex_unlock(&tegra_dcs[1]->lock);
2223 } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2224 enable_irq(tegra_dcs[0]->irq);
2225 mutex_unlock(&tegra_dcs[0]->lock);
2228 enable_irq(dc->irq);
2232 if (dc->out_ops && dc->out_ops->enable)
2233 dc->out_ops->enable(dc);
2235 if (dc->out->out_pins)
2236 tegra_dc_set_out_pin_polars(dc, dc->out->out_pins,
2237 dc->out->n_out_pins);
2239 if (dc->out->postpoweron)
2240 dc->out->postpoweron();
2242 /* force a full blending update */
2243 dc->blend.z[0] = -1;
2249 static bool _tegra_dc_enable(struct tegra_dc *dc)
2251 if (dc->mode.pclk == 0)
2257 tegra_dc_io_start(dc);
2259 return _tegra_dc_controller_enable(dc);
2262 void tegra_dc_enable(struct tegra_dc *dc)
2264 mutex_lock(&dc->lock);
2267 dc->enabled = _tegra_dc_enable(dc);
2269 mutex_unlock(&dc->lock);
2272 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2276 disable_irq(dc->irq);
2278 if (dc->out_ops && dc->out_ops->disable)
2279 dc->out_ops->disable(dc);
2281 clk_disable(dc->emc_clk);
2282 clk_disable(dc->clk);
2283 tegra_dvfs_set_rate(dc->clk, 0);
2285 for (i = 0; i < DC_N_WINDOWS; i++) {
2286 struct tegra_dc_win *w = &dc->windows[i];
2288 w->new_bandwidth = 0;
2291 if (dc->out && dc->out->disable)
2294 /* flush any pending syncpt waits */
2295 for (i = 0; i < dc->n_windows; i++) {
2296 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2297 dc->syncpt[i].min++;
2298 nvhost_syncpt_cpu_incr(&dc->ndev->host->syncpt,
2304 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2306 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2309 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2311 val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2313 val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2314 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2319 bool tegra_dc_stats_get(struct tegra_dc *dc)
2321 #if 0 /* right now it is always enabled */
2326 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2327 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2337 static void _tegra_dc_disable(struct tegra_dc *dc)
2339 _tegra_dc_controller_disable(dc);
2340 tegra_dc_io_end(dc);
2343 void tegra_dc_disable(struct tegra_dc *dc)
2346 tegra_overlay_disable(dc->overlay);
2348 tegra_dc_ext_disable(dc->ext);
2350 mutex_lock(&dc->lock);
2353 dc->enabled = false;
2356 _tegra_dc_disable(dc);
2359 mutex_unlock(&dc->lock);
2362 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2363 static void tegra_dc_reset_worker(struct work_struct *work)
2365 struct tegra_dc *dc =
2366 container_of(work, struct tegra_dc, reset_work);
2368 unsigned long val = 0;
2370 dev_warn(&dc->ndev->dev, "overlay stuck in underflow state. resetting.\n");
2372 tegra_dc_ext_disable(dc->ext);
2374 mutex_lock(&shared_lock);
2375 mutex_lock(&dc->lock);
2377 if (dc->enabled == false)
2380 dc->enabled = false;
2385 val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2386 val &= ~(0x00000100);
2387 tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2390 * set DC to STOP mode
2392 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2396 _tegra_dc_controller_disable(dc);
2398 /* _tegra_dc_controller_reset_enable deasserts reset */
2399 _tegra_dc_controller_reset_enable(dc);
2403 mutex_unlock(&dc->lock);
2404 mutex_unlock(&shared_lock);
2409 static int tegra_dc_probe(struct nvhost_device *ndev)
2411 struct tegra_dc *dc;
2413 struct clk *emc_clk;
2414 struct resource *res;
2415 struct resource *base_res;
2416 struct resource *fb_mem = NULL;
2422 if (!ndev->dev.platform_data) {
2423 dev_err(&ndev->dev, "no platform data\n");
2427 dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2429 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2433 irq = nvhost_get_irq_byname(ndev, "irq");
2435 dev_err(&ndev->dev, "no irq\n");
2440 res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2442 dev_err(&ndev->dev, "no mem resource\n");
2447 base_res = request_mem_region(res->start, resource_size(res), ndev->name);
2449 dev_err(&ndev->dev, "request_mem_region failed\n");
2454 base = ioremap(res->start, resource_size(res));
2456 dev_err(&ndev->dev, "registers can't be mapped\n");
2458 goto err_release_resource_reg;
2461 fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2463 clk = clk_get(&ndev->dev, NULL);
2464 if (IS_ERR_OR_NULL(clk)) {
2465 dev_err(&ndev->dev, "can't get clock\n");
2467 goto err_iounmap_reg;
2470 emc_clk = clk_get(&ndev->dev, "emc");
2471 if (IS_ERR_OR_NULL(emc_clk)) {
2472 dev_err(&ndev->dev, "can't get emc clock\n");
2478 dc->emc_clk = emc_clk;
2480 dc->base_res = base_res;
2484 dc->pdata = ndev->dev.platform_data;
2487 * The emc is a shared clock, it will be set based on
2488 * the requirements for each user on the bus.
2490 dc->emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
2491 clk_set_rate(emc_clk, dc->emc_clk_rate);
2493 if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2496 mutex_init(&dc->lock);
2497 init_completion(&dc->vblank_complete);
2498 init_waitqueue_head(&dc->wq);
2499 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2500 INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2502 INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2504 dc->n_windows = DC_N_WINDOWS;
2505 for (i = 0; i < dc->n_windows; i++) {
2506 dc->windows[i].idx = i;
2507 dc->windows[i].dc = dc;
2510 if (request_irq(irq, tegra_dc_irq, IRQF_DISABLED,
2511 dev_name(&ndev->dev), dc)) {
2512 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2514 goto err_put_emc_clk;
2517 /* hack to ballence enable_irq calls in _tegra_dc_enable() */
2518 disable_irq(dc->irq);
2520 ret = tegra_dc_set(dc, ndev->id);
2522 dev_err(&ndev->dev, "can't add dc\n");
2526 nvhost_set_drvdata(ndev, dc);
2528 if (dc->pdata->default_out)
2529 tegra_dc_set_out(dc, dc->pdata->default_out);
2531 dev_err(&ndev->dev, "No default output specified. Leaving output disabled.\n");
2533 dc->vblank_syncpt = (dc->ndev->id == 0) ?
2534 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2536 dc->ext = tegra_dc_ext_register(ndev, dc);
2537 if (IS_ERR_OR_NULL(dc->ext)) {
2538 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2542 mutex_lock(&dc->lock);
2544 _tegra_dc_enable(dc);
2545 mutex_unlock(&dc->lock);
2547 tegra_dc_create_debugfs(dc);
2549 dev_info(&ndev->dev, "probed\n");
2551 if (dc->pdata->fb) {
2552 if (dc->pdata->fb->bits_per_pixel == -1) {
2555 WINDOW_A_SELECT << dc->pdata->fb->win,
2556 DC_CMD_DISPLAY_WINDOW_HEADER);
2558 fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2559 dc->pdata->fb->bits_per_pixel =
2560 tegra_dc_fmt_bpp(fmt);
2563 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2564 if (IS_ERR_OR_NULL(dc->fb))
2569 dc->overlay = tegra_overlay_register(ndev, dc);
2570 if (IS_ERR_OR_NULL(dc->overlay))
2574 if (dc->out && dc->out->hotplug_init)
2575 dc->out->hotplug_init();
2577 if (dc->out_ops && dc->out_ops->detect)
2578 dc->out_ops->detect(dc);
2580 dc->connected = true;
2582 tegra_dc_create_sysfs(&dc->ndev->dev);
2595 release_resource(fb_mem);
2596 err_release_resource_reg:
2597 release_resource(base_res);
2604 static int tegra_dc_remove(struct nvhost_device *ndev)
2606 struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2608 tegra_dc_remove_sysfs(&dc->ndev->dev);
2609 tegra_dc_remove_debugfs(dc);
2612 tegra_overlay_unregister(dc->overlay);
2616 tegra_fb_unregister(dc->fb);
2618 release_resource(dc->fb_mem);
2621 tegra_dc_ext_disable(dc->ext);
2624 tegra_dc_ext_unregister(dc->ext);
2627 _tegra_dc_disable(dc);
2629 free_irq(dc->irq, dc);
2630 clk_put(dc->emc_clk);
2634 release_resource(dc->base_res);
2636 tegra_dc_set(NULL, ndev->id);
2641 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2643 struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2645 dev_info(&ndev->dev, "suspend\n");
2648 tegra_overlay_disable(dc->overlay);
2650 tegra_dc_ext_disable(dc->ext);
2652 mutex_lock(&dc->lock);
2654 if (dc->out_ops && dc->out_ops->suspend)
2655 dc->out_ops->suspend(dc);
2658 _tegra_dc_disable(dc);
2660 dc->suspended = true;
2663 if (dc->out && dc->out->postsuspend) {
2664 dc->out->postsuspend();
2665 msleep(100); /* avoid resume event due to voltage falling */
2668 mutex_unlock(&dc->lock);
2673 static int tegra_dc_resume(struct nvhost_device *ndev)
2675 struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2677 dev_info(&ndev->dev, "resume\n");
2679 mutex_lock(&dc->lock);
2680 dc->suspended = false;
2683 _tegra_dc_enable(dc);
2685 if (dc->out && dc->out->hotplug_init)
2686 dc->out->hotplug_init();
2688 if (dc->out_ops && dc->out_ops->resume)
2689 dc->out_ops->resume(dc);
2690 mutex_unlock(&dc->lock);
2695 #endif /* CONFIG_PM */
2697 extern int suspend_set(const char *val, struct kernel_param *kp)
2699 if (!strcmp(val, "dump"))
2700 dump_regs(tegra_dcs[0]);
2702 else if (!strcmp(val, "suspend"))
2703 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2704 else if (!strcmp(val, "resume"))
2705 tegra_dc_resume(tegra_dcs[0]->ndev);
2711 extern int suspend_get(char *buffer, struct kernel_param *kp)
2718 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2720 struct nvhost_driver tegra_dc_driver = {
2723 .owner = THIS_MODULE,
2725 .probe = tegra_dc_probe,
2726 .remove = tegra_dc_remove,
2728 .suspend = tegra_dc_suspend,
2729 .resume = tegra_dc_resume,
2733 static int __init tegra_dc_module_init(void)
2735 int ret = tegra_dc_ext_module_init();
2738 return nvhost_driver_register(&tegra_dc_driver);
2741 static void __exit tegra_dc_module_exit(void)
2743 nvhost_driver_unregister(&tegra_dc_driver);
2744 tegra_dc_ext_module_exit();
2747 module_exit(tegra_dc_module_exit);
2748 module_init(tegra_dc_module_init);