video: tegra: dc: Powergate dependency between DCs.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 /* A mutex used to protect the critical section used by both DC heads. */
67 static struct mutex status_lock;
68
69 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
70         .refresh = 60,
71         .xres = 640,
72         .yres = 480,
73         .pixclock = KHZ2PICOS(25200),
74         .hsync_len = 96,        /* h_sync_width */
75         .vsync_len = 2,         /* v_sync_width */
76         .left_margin = 48,      /* h_back_porch */
77         .upper_margin = 33,     /* v_back_porch */
78         .right_margin = 16,     /* h_front_porch */
79         .lower_margin = 10,     /* v_front_porch */
80         .vmode = 0,
81         .sync = 0,
82 };
83
84 static struct tegra_dc_mode override_disp_mode[3];
85
86 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
87
88 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
89
90 DEFINE_MUTEX(tegra_dc_lock);
91 DEFINE_MUTEX(shared_lock);
92
93 static const struct {
94         bool h;
95         bool v;
96 } can_filter[] = {
97         /* Window A has no filtering */
98         { false, false },
99         /* Window B has both H and V filtering */
100         { true,  true  },
101         /* Window C has only H filtering */
102         { false, true  },
103 };
104
105 #ifdef CONFIG_TEGRA_DC_CMU
106 static struct tegra_dc_cmu default_cmu = {
107         /* lut1 maps sRGB to linear space. */
108         {
109                 0,    1,    2,    4,    5,    6,    7,    9,
110                 10,   11,   12,   14,   15,   16,   18,   20,
111                 21,   23,   25,   27,   29,   31,   33,   35,
112                 37,   40,   42,   45,   48,   50,   53,   56,
113                 59,   62,   66,   69,   72,   76,   79,   83,
114                 87,   91,   95,   99,   103,  107,  112,  116,
115                 121,  126,  131,  136,  141,  146,  151,  156,
116                 162,  168,  173,  179,  185,  191,  197,  204,
117                 210,  216,  223,  230,  237,  244,  251,  258,
118                 265,  273,  280,  288,  296,  304,  312,  320,
119                 329,  337,  346,  354,  363,  372,  381,  390,
120                 400,  409,  419,  428,  438,  448,  458,  469,
121                 479,  490,  500,  511,  522,  533,  544,  555,
122                 567,  578,  590,  602,  614,  626,  639,  651,
123                 664,  676,  689,  702,  715,  728,  742,  755,
124                 769,  783,  797,  811,  825,  840,  854,  869,
125                 884,  899,  914,  929,  945,  960,  976,  992,
126                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
127                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
128                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
129                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
130                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
131                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
132                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
133                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
134                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
135                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
136                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
137                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
138                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
139                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
140                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
141         },
142         /* csc */
143         {
144                 0x100, 0x0,   0x0,
145                 0x0,   0x100, 0x0,
146                 0x0,   0x0,   0x100,
147         },
148         /* lut2 maps linear space to sRGB*/
149         {
150                 0,    1,    2,    2,    3,    4,    5,    6,
151                 6,    7,    8,    9,    10,   10,   11,   12,
152                 13,   13,   14,   15,   15,   16,   16,   17,
153                 18,   18,   19,   19,   20,   20,   21,   21,
154                 22,   22,   23,   23,   23,   24,   24,   25,
155                 25,   25,   26,   26,   27,   27,   27,   28,
156                 28,   29,   29,   29,   30,   30,   30,   31,
157                 31,   31,   32,   32,   32,   33,   33,   33,
158                 34,   34,   34,   34,   35,   35,   35,   36,
159                 36,   36,   37,   37,   37,   37,   38,   38,
160                 38,   38,   39,   39,   39,   40,   40,   40,
161                 40,   41,   41,   41,   41,   42,   42,   42,
162                 42,   43,   43,   43,   43,   43,   44,   44,
163                 44,   44,   45,   45,   45,   45,   46,   46,
164                 46,   46,   46,   47,   47,   47,   47,   48,
165                 48,   48,   48,   48,   49,   49,   49,   49,
166                 49,   50,   50,   50,   50,   50,   51,   51,
167                 51,   51,   51,   52,   52,   52,   52,   52,
168                 53,   53,   53,   53,   53,   54,   54,   54,
169                 54,   54,   55,   55,   55,   55,   55,   55,
170                 56,   56,   56,   56,   56,   57,   57,   57,
171                 57,   57,   57,   58,   58,   58,   58,   58,
172                 58,   59,   59,   59,   59,   59,   59,   60,
173                 60,   60,   60,   60,   60,   61,   61,   61,
174                 61,   61,   61,   62,   62,   62,   62,   62,
175                 62,   63,   63,   63,   63,   63,   63,   64,
176                 64,   64,   64,   64,   64,   64,   65,   65,
177                 65,   65,   65,   65,   66,   66,   66,   66,
178                 66,   66,   66,   67,   67,   67,   67,   67,
179                 67,   67,   68,   68,   68,   68,   68,   68,
180                 68,   69,   69,   69,   69,   69,   69,   69,
181                 70,   70,   70,   70,   70,   70,   70,   71,
182                 71,   71,   71,   71,   71,   71,   72,   72,
183                 72,   72,   72,   72,   72,   72,   73,   73,
184                 73,   73,   73,   73,   73,   74,   74,   74,
185                 74,   74,   74,   74,   74,   75,   75,   75,
186                 75,   75,   75,   75,   75,   76,   76,   76,
187                 76,   76,   76,   76,   77,   77,   77,   77,
188                 77,   77,   77,   77,   78,   78,   78,   78,
189                 78,   78,   78,   78,   78,   79,   79,   79,
190                 79,   79,   79,   79,   79,   80,   80,   80,
191                 80,   80,   80,   80,   80,   81,   81,   81,
192                 81,   81,   81,   81,   81,   81,   82,   82,
193                 82,   82,   82,   82,   82,   82,   83,   83,
194                 83,   83,   83,   83,   83,   83,   83,   84,
195                 84,   84,   84,   84,   84,   84,   84,   84,
196                 85,   85,   85,   85,   85,   85,   85,   85,
197                 85,   86,   86,   86,   86,   86,   86,   86,
198                 86,   86,   87,   87,   87,   87,   87,   87,
199                 87,   87,   87,   88,   88,   88,   88,   88,
200                 88,   88,   88,   88,   88,   89,   89,   89,
201                 89,   89,   89,   89,   89,   89,   90,   90,
202                 90,   90,   90,   90,   90,   90,   90,   90,
203                 91,   91,   91,   91,   91,   91,   91,   91,
204                 91,   91,   92,   92,   92,   92,   92,   92,
205                 92,   92,   92,   92,   93,   93,   93,   93,
206                 93,   93,   93,   93,   93,   93,   94,   94,
207                 94,   94,   94,   94,   94,   94,   94,   94,
208                 95,   95,   95,   95,   95,   95,   95,   95,
209                 95,   95,   96,   96,   96,   96,   96,   96,
210                 96,   96,   96,   96,   96,   97,   97,   97,
211                 97,   97,   97,   97,   97,   97,   97,   98,
212                 98,   98,   98,   98,   98,   98,   98,   98,
213                 98,   98,   99,   99,   99,   99,   99,   99,
214                 99,   100,  101,  101,  102,  103,  103,  104,
215                 105,  105,  106,  107,  107,  108,  109,  109,
216                 110,  111,  111,  112,  113,  113,  114,  115,
217                 115,  116,  116,  117,  118,  118,  119,  119,
218                 120,  120,  121,  122,  122,  123,  123,  124,
219                 124,  125,  126,  126,  127,  127,  128,  128,
220                 129,  129,  130,  130,  131,  131,  132,  132,
221                 133,  133,  134,  134,  135,  135,  136,  136,
222                 137,  137,  138,  138,  139,  139,  140,  140,
223                 141,  141,  142,  142,  143,  143,  144,  144,
224                 145,  145,  145,  146,  146,  147,  147,  148,
225                 148,  149,  149,  150,  150,  150,  151,  151,
226                 152,  152,  153,  153,  153,  154,  154,  155,
227                 155,  156,  156,  156,  157,  157,  158,  158,
228                 158,  159,  159,  160,  160,  160,  161,  161,
229                 162,  162,  162,  163,  163,  164,  164,  164,
230                 165,  165,  166,  166,  166,  167,  167,  167,
231                 168,  168,  169,  169,  169,  170,  170,  170,
232                 171,  171,  172,  172,  172,  173,  173,  173,
233                 174,  174,  174,  175,  175,  176,  176,  176,
234                 177,  177,  177,  178,  178,  178,  179,  179,
235                 179,  180,  180,  180,  181,  181,  182,  182,
236                 182,  183,  183,  183,  184,  184,  184,  185,
237                 185,  185,  186,  186,  186,  187,  187,  187,
238                 188,  188,  188,  189,  189,  189,  189,  190,
239                 190,  190,  191,  191,  191,  192,  192,  192,
240                 193,  193,  193,  194,  194,  194,  195,  195,
241                 195,  196,  196,  196,  196,  197,  197,  197,
242                 198,  198,  198,  199,  199,  199,  200,  200,
243                 200,  200,  201,  201,  201,  202,  202,  202,
244                 202,  203,  203,  203,  204,  204,  204,  205,
245                 205,  205,  205,  206,  206,  206,  207,  207,
246                 207,  207,  208,  208,  208,  209,  209,  209,
247                 209,  210,  210,  210,  211,  211,  211,  211,
248                 212,  212,  212,  213,  213,  213,  213,  214,
249                 214,  214,  214,  215,  215,  215,  216,  216,
250                 216,  216,  217,  217,  217,  217,  218,  218,
251                 218,  219,  219,  219,  219,  220,  220,  220,
252                 220,  221,  221,  221,  221,  222,  222,  222,
253                 223,  223,  223,  223,  224,  224,  224,  224,
254                 225,  225,  225,  225,  226,  226,  226,  226,
255                 227,  227,  227,  227,  228,  228,  228,  228,
256                 229,  229,  229,  229,  230,  230,  230,  230,
257                 231,  231,  231,  231,  232,  232,  232,  232,
258                 233,  233,  233,  233,  234,  234,  234,  234,
259                 235,  235,  235,  235,  236,  236,  236,  236,
260                 237,  237,  237,  237,  238,  238,  238,  238,
261                 239,  239,  239,  239,  240,  240,  240,  240,
262                 240,  241,  241,  241,  241,  242,  242,  242,
263                 242,  243,  243,  243,  243,  244,  244,  244,
264                 244,  244,  245,  245,  245,  245,  246,  246,
265                 246,  246,  247,  247,  247,  247,  247,  248,
266                 248,  248,  248,  249,  249,  249,  249,  249,
267                 250,  250,  250,  250,  251,  251,  251,  251,
268                 251,  252,  252,  252,  252,  253,  253,  253,
269                 253,  253,  254,  254,  254,  254,  255,  255,
270         },
271 };
272 #endif
273
274 void tegra_dc_clk_enable(struct tegra_dc *dc)
275 {
276         if (!tegra_is_clk_enabled(dc->clk)) {
277                 clk_prepare_enable(dc->clk);
278                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
279         }
280 }
281
282 void tegra_dc_clk_disable(struct tegra_dc *dc)
283 {
284         if (tegra_is_clk_enabled(dc->clk)) {
285                 clk_disable_unprepare(dc->clk);
286                 tegra_dvfs_set_rate(dc->clk, 0);
287         }
288 }
289
290 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
291 {
292         if (dc->out_ops->hold)
293                 dc->out_ops->hold(dc);
294 }
295
296 void tegra_dc_release_dc_out(struct tegra_dc *dc)
297 {
298         if (dc->out_ops->release)
299                 dc->out_ops->release(dc);
300 }
301
302 #define DUMP_REG(a) do {                        \
303         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
304                  #a, a, tegra_dc_readl(dc, a));               \
305         print(data, buff);                                    \
306         } while (0)
307
308 static void _dump_regs(struct tegra_dc *dc, void *data,
309                        void (* print)(void *data, const char *str))
310 {
311         int i;
312         char buff[256];
313
314         mutex_lock(&dc->lock);
315         tegra_dc_io_start(dc);
316         tegra_dc_hold_dc_out(dc);
317
318         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
319         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
320         DUMP_REG(DC_CMD_SIGNAL_RAISE);
321         DUMP_REG(DC_CMD_INT_STATUS);
322         DUMP_REG(DC_CMD_INT_MASK);
323         DUMP_REG(DC_CMD_INT_ENABLE);
324         DUMP_REG(DC_CMD_INT_TYPE);
325         DUMP_REG(DC_CMD_INT_POLARITY);
326         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
327         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
328         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
329         DUMP_REG(DC_CMD_STATE_ACCESS);
330         DUMP_REG(DC_CMD_STATE_CONTROL);
331         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
332         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
333
334         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
335         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
336         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
337         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
338         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
339         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
340         DUMP_REG(DC_DISP_REF_TO_SYNC);
341         DUMP_REG(DC_DISP_SYNC_WIDTH);
342         DUMP_REG(DC_DISP_BACK_PORCH);
343         DUMP_REG(DC_DISP_DISP_ACTIVE);
344         DUMP_REG(DC_DISP_FRONT_PORCH);
345         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
347         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
348         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
349         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
350         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
352         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
353         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
354         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
355         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
357         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
358         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
359         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
360         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
367         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
368         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
369         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
370         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
371         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
372         DUMP_REG(DC_DISP_M0_CONTROL);
373         DUMP_REG(DC_DISP_M1_CONTROL);
374         DUMP_REG(DC_DISP_DI_CONTROL);
375         DUMP_REG(DC_DISP_PP_CONTROL);
376         DUMP_REG(DC_DISP_PP_SELECT_A);
377         DUMP_REG(DC_DISP_PP_SELECT_B);
378         DUMP_REG(DC_DISP_PP_SELECT_C);
379         DUMP_REG(DC_DISP_PP_SELECT_D);
380         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
381         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
382         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
383         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
384         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
385         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
386         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
387         DUMP_REG(DC_DISP_BORDER_COLOR);
388         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
389         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
390         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
391         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
392         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
393         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
394         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
395         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
396         DUMP_REG(DC_DISP_CURSOR_POSITION);
397         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
398         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
400         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
401         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
402         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
403         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
406         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
407 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
408         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
409 #endif
410         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
411         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
412
413
414         for (i = 0; i < 3; i++) {
415                 print(data, "\n");
416                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
417                 print(data, buff);
418
419                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
420                                 DC_CMD_DISPLAY_WINDOW_HEADER);
421                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
422                 DUMP_REG(DC_WIN_WIN_OPTIONS);
423                 DUMP_REG(DC_WIN_BYTE_SWAP);
424                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
425                 DUMP_REG(DC_WIN_COLOR_DEPTH);
426                 DUMP_REG(DC_WIN_POSITION);
427                 DUMP_REG(DC_WIN_SIZE);
428                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
429                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
430                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
431                 DUMP_REG(DC_WIN_DDA_INCREMENT);
432                 DUMP_REG(DC_WIN_LINE_STRIDE);
433 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
434                 DUMP_REG(DC_WIN_BUF_STRIDE);
435                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
436 #endif
437                 DUMP_REG(DC_WIN_BLEND_NOKEY);
438                 DUMP_REG(DC_WIN_BLEND_1WIN);
439                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
440                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
441                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
442                 DUMP_REG(DC_WINBUF_START_ADDR);
443                 DUMP_REG(DC_WINBUF_START_ADDR_U);
444                 DUMP_REG(DC_WINBUF_START_ADDR_V);
445                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
446                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
447                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
448                 DUMP_REG(DC_WIN_CSC_YOF);
449                 DUMP_REG(DC_WIN_CSC_KYRGB);
450                 DUMP_REG(DC_WIN_CSC_KUR);
451                 DUMP_REG(DC_WIN_CSC_KVR);
452                 DUMP_REG(DC_WIN_CSC_KUG);
453                 DUMP_REG(DC_WIN_CSC_KVG);
454                 DUMP_REG(DC_WIN_CSC_KUB);
455                 DUMP_REG(DC_WIN_CSC_KVB);
456         }
457
458         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
459         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
461         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
462         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
463         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
464         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
465         DUMP_REG(DC_DISP_M1_CONTROL);
466         DUMP_REG(DC_COM_PM1_CONTROL);
467         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
468         DUMP_REG(DC_DISP_SD_CONTROL);
469 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
470         DUMP_REG(DC_COM_CMU_CSC_KRR);
471         DUMP_REG(DC_COM_CMU_CSC_KGR);
472         DUMP_REG(DC_COM_CMU_CSC_KBR);
473         DUMP_REG(DC_COM_CMU_CSC_KRG);
474         DUMP_REG(DC_COM_CMU_CSC_KGG);
475         DUMP_REG(DC_COM_CMU_CSC_KBR);
476         DUMP_REG(DC_COM_CMU_CSC_KRB);
477         DUMP_REG(DC_COM_CMU_CSC_KGB);
478         DUMP_REG(DC_COM_CMU_CSC_KBB);
479 #endif
480
481         tegra_dc_release_dc_out(dc);
482         tegra_dc_io_end(dc);
483         mutex_unlock(&dc->lock);
484 }
485
486 #undef DUMP_REG
487
488 #ifdef DEBUG
489 static void dump_regs_print(void *data, const char *str)
490 {
491         struct tegra_dc *dc = data;
492         dev_dbg(&dc->ndev->dev, "%s", str);
493 }
494
495 static void dump_regs(struct tegra_dc *dc)
496 {
497         _dump_regs(dc, dc, dump_regs_print);
498 }
499 #else /* !DEBUG */
500
501 static void dump_regs(struct tegra_dc *dc) {}
502
503 #endif /* DEBUG */
504
505 #ifdef CONFIG_DEBUG_FS
506
507 static void dbg_regs_print(void *data, const char *str)
508 {
509         struct seq_file *s = data;
510
511         seq_printf(s, "%s", str);
512 }
513
514 #undef DUMP_REG
515
516 static int dbg_dc_show(struct seq_file *s, void *unused)
517 {
518         struct tegra_dc *dc = s->private;
519
520         _dump_regs(dc, s, dbg_regs_print);
521
522         return 0;
523 }
524
525
526 static int dbg_dc_open(struct inode *inode, struct file *file)
527 {
528         return single_open(file, dbg_dc_show, inode->i_private);
529 }
530
531 static const struct file_operations regs_fops = {
532         .open           = dbg_dc_open,
533         .read           = seq_read,
534         .llseek         = seq_lseek,
535         .release        = single_release,
536 };
537
538 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
539 {
540         struct tegra_dc *dc = s->private;
541         struct tegra_dc_mode *m;
542
543         mutex_lock(&dc->lock);
544         m = &dc->mode;
545         seq_printf(s,
546                 "pclk: %d\n"
547                 "h_ref_to_sync: %d\n"
548                 "v_ref_to_sync: %d\n"
549                 "h_sync_width: %d\n"
550                 "v_sync_width: %d\n"
551                 "h_back_porch: %d\n"
552                 "v_back_porch: %d\n"
553                 "h_active: %d\n"
554                 "v_active: %d\n"
555                 "h_front_porch: %d\n"
556                 "v_front_porch: %d\n"
557                 "stereo_mode: %d\n",
558                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
559                 m->h_sync_width, m->v_sync_width,
560                 m->h_back_porch, m->v_back_porch,
561                 m->h_active, m->v_active,
562                 m->h_front_porch, m->v_front_porch,
563                 m->stereo_mode);
564         mutex_unlock(&dc->lock);
565         return 0;
566 }
567
568 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
569 {
570         return single_open(file, dbg_dc_mode_show, inode->i_private);
571 }
572
573 static const struct file_operations mode_fops = {
574         .open           = dbg_dc_mode_open,
575         .read           = seq_read,
576         .llseek         = seq_lseek,
577         .release        = single_release,
578 };
579
580 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
581 {
582         struct tegra_dc *dc = s->private;
583
584         mutex_lock(&dc->lock);
585         seq_printf(s,
586                 "underflows: %llu\n"
587                 "underflows_a: %llu\n"
588                 "underflows_b: %llu\n"
589                 "underflows_c: %llu\n",
590                 dc->stats.underflows,
591                 dc->stats.underflows_a,
592                 dc->stats.underflows_b,
593                 dc->stats.underflows_c);
594         mutex_unlock(&dc->lock);
595
596         return 0;
597 }
598
599 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
600 {
601         return single_open(file, dbg_dc_stats_show, inode->i_private);
602 }
603
604 static const struct file_operations stats_fops = {
605         .open           = dbg_dc_stats_open,
606         .read           = seq_read,
607         .llseek         = seq_lseek,
608         .release        = single_release,
609 };
610
611 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
612 {
613         if (dc->debugdir)
614                 debugfs_remove_recursive(dc->debugdir);
615         dc->debugdir = NULL;
616 }
617
618 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
619 {
620         struct dentry *retval;
621
622         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
623         if (!dc->debugdir)
624                 goto remove_out;
625
626         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
627                 &regs_fops);
628         if (!retval)
629                 goto remove_out;
630
631         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
632                 &mode_fops);
633         if (!retval)
634                 goto remove_out;
635
636         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
637                 &stats_fops);
638         if (!retval)
639                 goto remove_out;
640
641         return;
642 remove_out:
643         dev_err(&dc->ndev->dev, "could not create debugfs\n");
644         tegra_dc_remove_debugfs(dc);
645 }
646
647 #else /* !CONFIG_DEBUGFS */
648 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
649 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
650 #endif /* CONFIG_DEBUGFS */
651
652 static int tegra_dc_set(struct tegra_dc *dc, int index)
653 {
654         int ret = 0;
655
656         mutex_lock(&tegra_dc_lock);
657         if (index >= TEGRA_MAX_DC) {
658                 ret = -EINVAL;
659                 goto out;
660         }
661
662         if (dc != NULL && tegra_dcs[index] != NULL) {
663                 ret = -EBUSY;
664                 goto out;
665         }
666
667         tegra_dcs[index] = dc;
668
669 out:
670         mutex_unlock(&tegra_dc_lock);
671
672         return ret;
673 }
674
675 unsigned int tegra_dc_has_multiple_dc(void)
676 {
677         unsigned int idx;
678         unsigned int cnt = 0;
679         struct tegra_dc *dc;
680
681         mutex_lock(&tegra_dc_lock);
682         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
683                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
684         mutex_unlock(&tegra_dc_lock);
685
686         return (cnt > 1);
687 }
688
689 /* get the stride size of a window.
690  * return: stride size in bytes for window win. or 0 if unavailble. */
691 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
692 {
693         u32 stride;
694
695         if (!dc->enabled)
696                 return 0;
697         BUG_ON(win > DC_N_WINDOWS);
698         mutex_lock(&dc->lock);
699         tegra_dc_io_start(dc);
700         tegra_dc_hold_dc_out(dc);
701         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
702                 DC_CMD_DISPLAY_WINDOW_HEADER);
703         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
704         tegra_dc_release_dc_out(dc);
705         tegra_dc_io_end(dc);
706         mutex_unlock(&dc->lock);
707         return GET_LINE_STRIDE(stride);
708 }
709 EXPORT_SYMBOL(tegra_dc_get_stride);
710
711 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
712 {
713         if (idx < TEGRA_MAX_DC)
714                 return tegra_dcs[idx];
715         else
716                 return NULL;
717 }
718 EXPORT_SYMBOL(tegra_dc_get_dc);
719
720 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
721 {
722         if (win >= dc->n_windows)
723                 return NULL;
724
725         return &dc->windows[win];
726 }
727 EXPORT_SYMBOL(tegra_dc_get_window);
728
729 bool tegra_dc_get_connected(struct tegra_dc *dc)
730 {
731         return dc->connected;
732 }
733 EXPORT_SYMBOL(tegra_dc_get_connected);
734
735 bool tegra_dc_hpd(struct tegra_dc *dc)
736 {
737         int sense;
738         int level;
739
740         level = gpio_get_value(dc->out->hotplug_gpio);
741
742         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
743
744         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
745                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
746 }
747 EXPORT_SYMBOL(tegra_dc_hpd);
748
749 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
750 {
751         unsigned i;
752         unsigned v0 = 128;
753         unsigned v1 = 0;
754
755         /* linear horizontal and vertical filters */
756         for (i = 0; i < 16; i++) {
757                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
758                                 DC_WIN_H_FILTER_P(i));
759
760                 tegra_dc_writel(dc, v0,
761                                 DC_WIN_V_FILTER_P(i));
762                 v0 -= 8;
763                 v1 += 8;
764         }
765 }
766
767 #ifdef CONFIG_TEGRA_DC_CMU
768 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
769                                         struct tegra_dc_cmu *src_cmu)
770 {
771         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
772 }
773
774 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
775 {
776         u32 val;
777         u32 i;
778
779         for (i = 0; i < 256; i++) {
780                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
781                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
782         }
783
784         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
785         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
786         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
787         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
788         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
789         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
790         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
791         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
792         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
793
794         for (i = 0; i < 960; i++) {
795                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
796                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
797         }
798 }
799
800 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
801 {
802         u32 val;
803         u32 i;
804         bool flags;
805
806         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
807         if (val & CMU_ENABLE)
808                 flags = true;
809
810         val &= ~CMU_ENABLE;
811         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
812         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
813         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
814
815         /*TODO: Sync up with frame end */
816         mdelay(20);
817
818         for (i = 0; i < 256; i++) {
819                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
820                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
821                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
822                 cmu->lut1[i] = LUT1_READ_DATA(val);
823         }
824
825         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
826         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
827         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
828         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
829         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
830         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
831         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
832         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
833         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
834
835         for (i = 0; i < 960; i++) {
836                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
837                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
838                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
839                 cmu->lut2[i] = LUT2_READ_DATA(val);
840         }
841 }
842 EXPORT_SYMBOL(tegra_dc_get_cmu);
843
844 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
845 {
846         u32 val;
847
848         if (dc->pdata->cmu_enable) {
849                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
850         } else {
851                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
852                 return 0;
853         }
854
855         if (cmu != &dc->cmu) {
856                 tegra_dc_cache_cmu(&dc->cmu, cmu);
857
858                 /* Disable CMU */
859                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
860                 if (val & CMU_ENABLE) {
861                         val &= ~CMU_ENABLE;
862                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
863                         val = GENERAL_UPDATE;
864                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
865                         val = GENERAL_ACT_REQ;
866                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
867                         /*TODO: Sync up with vsync */
868                         mdelay(20);
869                 }
870
871                 tegra_dc_set_cmu(dc, &dc->cmu);
872         }
873         tegra_dc_set_color_control(dc);
874
875         return 0;
876 }
877
878 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
879 {
880         int ret;
881
882         mutex_lock(&dc->lock);
883         tegra_dc_io_start(dc);
884         tegra_dc_hold_dc_out(dc);
885
886         ret = _tegra_dc_update_cmu(dc, cmu);
887
888         tegra_dc_release_dc_out(dc);
889         tegra_dc_io_end(dc);
890         mutex_unlock(&dc->lock);
891
892         return ret;
893 }
894 EXPORT_SYMBOL(tegra_dc_update_cmu);
895
896 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
897 {
898         tegra_dc_update_cmu(dc, &dc->cmu);
899 }
900 #else
901 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
902 #define tegra_dc_set_cmu(dc, cmu)
903 #define tegra_dc_update_cmu(dc, cmu)
904 #endif
905
906 /* disable_irq() blocks until handler completes, calling this function while
907  * holding dc->lock can deadlock. */
908 static inline void disable_dc_irq(const struct tegra_dc *dc)
909 {
910         disable_irq(dc->irq);
911 }
912
913 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
914 {
915         return dc->syncpt[i].id;
916 }
917 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
918
919 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
920 {
921         u32 max;
922
923         mutex_lock(&dc->lock);
924         tegra_dc_io_start(dc);
925         tegra_dc_hold_dc_out(dc);
926         max = nvhost_syncpt_incr_max_ext(dc->ndev,
927                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
928         dc->syncpt[i].max = max;
929         tegra_dc_release_dc_out(dc);
930         tegra_dc_io_end(dc);
931         mutex_unlock(&dc->lock);
932
933         return max;
934 }
935
936 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
937 {
938         mutex_lock(&dc->lock);
939         if (dc->enabled) {
940                 tegra_dc_io_start(dc);
941                 tegra_dc_hold_dc_out(dc);
942                 while (dc->syncpt[i].min < val) {
943                         dc->syncpt[i].min++;
944                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
945                 }
946                 tegra_dc_release_dc_out(dc);
947                 tegra_dc_io_end(dc);
948         }
949         mutex_unlock(&dc->lock);
950 }
951
952 void
953 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
954 {
955         unsigned int ctrl;
956         unsigned long out_sel;
957         unsigned long cmd_state;
958
959         mutex_lock(&dc->lock);
960         if (!dc->enabled) {
961                 mutex_unlock(&dc->lock);
962                 return;
963         }
964
965         tegra_dc_io_start(dc);
966         tegra_dc_hold_dc_out(dc);
967
968         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
969                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
970                 cfg->clk_select);
971
972         /* The new value should be effected immediately */
973         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
974         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
975
976         switch (cfg->which_pwm) {
977         case TEGRA_PWM_PM0:
978                 /* Select the LM0 on PM0 */
979                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
980                 out_sel &= ~(7 << 0);
981                 out_sel |= (3 << 0);
982                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
983                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
984                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
985                 break;
986         case TEGRA_PWM_PM1:
987                 /* Select the LM1 on PM1 */
988                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
989                 out_sel &= ~(7 << 4);
990                 out_sel |= (3 << 4);
991                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
992                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
993                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
994                 break;
995         default:
996                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
997                 break;
998         }
999         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1000         tegra_dc_release_dc_out(dc);
1001         tegra_dc_io_end(dc);
1002         mutex_unlock(&dc->lock);
1003 }
1004 EXPORT_SYMBOL(tegra_dc_config_pwm);
1005
1006 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1007                                 const struct tegra_dc_out_pin *pins,
1008                                 const unsigned int n_pins)
1009 {
1010         unsigned int i;
1011
1012         int name;
1013         int pol;
1014
1015         u32 pol1, pol3;
1016
1017         u32 set1, unset1;
1018         u32 set3, unset3;
1019
1020         set1 = set3 = unset1 = unset3 = 0;
1021
1022         for (i = 0; i < n_pins; i++) {
1023                 name = (pins + i)->name;
1024                 pol  = (pins + i)->pol;
1025
1026                 /* set polarity by name */
1027                 switch (name) {
1028                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1029                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1030                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1031                         else
1032                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1033                         break;
1034                 case TEGRA_DC_OUT_PIN_H_SYNC:
1035                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1036                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1037                         else
1038                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1039                         break;
1040                 case TEGRA_DC_OUT_PIN_V_SYNC:
1041                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1042                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1043                         else
1044                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1045                         break;
1046                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1047                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1048                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1049                         else
1050                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1051                         break;
1052                 default:
1053                         printk("Invalid argument in function %s\n",
1054                                __FUNCTION__);
1055                         break;
1056                 }
1057         }
1058
1059         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1060         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1061
1062         pol1 |= set1;
1063         pol1 &= ~unset1;
1064
1065         pol3 |= set3;
1066         pol3 &= ~unset3;
1067
1068         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1069         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1070 }
1071
1072 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1073 {
1074         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1075                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1076                 dc->out->type == TEGRA_DC_OUT_DSI)
1077                 return override_disp_mode[dc->out->type].pclk ?
1078                         &override_disp_mode[dc->out->type] : NULL;
1079         else
1080                 return NULL;
1081 }
1082
1083 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1084 {
1085         struct tegra_dc_mode *mode;
1086
1087         dc->out = out;
1088         mode = tegra_dc_get_override_mode(dc);
1089
1090         if (mode)
1091                 tegra_dc_set_mode(dc, mode);
1092         else if (out->n_modes > 0)
1093                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1094
1095         switch (out->type) {
1096         case TEGRA_DC_OUT_RGB:
1097                 dc->out_ops = &tegra_dc_rgb_ops;
1098                 break;
1099
1100         case TEGRA_DC_OUT_HDMI:
1101                 dc->out_ops = &tegra_dc_hdmi_ops;
1102                 break;
1103
1104         case TEGRA_DC_OUT_DSI:
1105                 dc->out_ops = &tegra_dc_dsi_ops;
1106                 break;
1107
1108         default:
1109                 dc->out_ops = NULL;
1110                 break;
1111         }
1112
1113         if (dc->out_ops && dc->out_ops->init)
1114                 dc->out_ops->init(dc);
1115 }
1116
1117 /* returns on error: -EINVAL
1118  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1119 int tegra_dc_get_out(const struct tegra_dc *dc)
1120 {
1121         if (dc && dc->out)
1122                 return dc->out->type;
1123         return -EINVAL;
1124 }
1125
1126 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1127 {
1128         if (dc->out)
1129                 return dc->out->height;
1130         else
1131                 return 0;
1132 }
1133 EXPORT_SYMBOL(tegra_dc_get_out_height);
1134
1135 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1136 {
1137         if (dc->out)
1138                 return dc->out->width;
1139         else
1140                 return 0;
1141 }
1142 EXPORT_SYMBOL(tegra_dc_get_out_width);
1143
1144 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1145 {
1146         if (dc->out && dc->out->max_pixclock)
1147                 return dc->out->max_pixclock;
1148         else
1149                 return 0;
1150 }
1151 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1152
1153 void tegra_dc_enable_crc(struct tegra_dc *dc)
1154 {
1155         u32 val;
1156
1157         mutex_lock(&dc->lock);
1158         tegra_dc_io_start(dc);
1159         tegra_dc_hold_dc_out(dc);
1160
1161         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1162                 CRC_ENABLE_ENABLE;
1163         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1164         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1165         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1166         tegra_dc_release_dc_out(dc);
1167         tegra_dc_io_end(dc);
1168         mutex_unlock(&dc->lock);
1169 }
1170
1171 void tegra_dc_disable_crc(struct tegra_dc *dc)
1172 {
1173         mutex_lock(&dc->lock);
1174         tegra_dc_io_start(dc);
1175         tegra_dc_hold_dc_out(dc);
1176         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1177         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1178         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1179
1180         tegra_dc_release_dc_out(dc);
1181         tegra_dc_io_end(dc);
1182         mutex_unlock(&dc->lock);
1183 }
1184
1185 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1186 {
1187         int crc = 0;
1188
1189         if (!dc) {
1190                 pr_err("Failed to get dc: NULL parameter.\n");
1191                 goto crc_error;
1192         }
1193
1194 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1195         /* TODO: Replace mdelay with code to sync VBlANK, since
1196          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1197         mdelay(TEGRA_CRC_LATCHED_DELAY);
1198 #endif
1199
1200         mutex_lock(&dc->lock);
1201         tegra_dc_io_start(dc);
1202         tegra_dc_hold_dc_out(dc);
1203         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1204         tegra_dc_release_dc_out(dc);
1205         tegra_dc_io_end(dc);
1206         mutex_unlock(&dc->lock);
1207 crc_error:
1208         return crc;
1209 }
1210
1211 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1212 {
1213 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1214         u32 val;
1215
1216         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1217         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1218             return true;
1219 #endif
1220         return false;
1221 }
1222
1223 static inline void enable_dc_irq(const struct tegra_dc *dc)
1224 {
1225 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1226         enable_irq(dc->irq);
1227 #else
1228         /* Always disable DC interrupts on FPGA. */
1229         disable_irq(dc->irq);
1230 #endif
1231 }
1232
1233 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1234 {
1235         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1236                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1237 }
1238
1239 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1240 {
1241         int ret = -ENOTTY;
1242
1243         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1244                 return ret;
1245
1246         /*
1247          * Logic is as follows
1248          * a) Indicate we need a vblank.
1249          * b) Wait for completion to be signalled from isr.
1250          * c) Initialize completion for next iteration.
1251          */
1252
1253         tegra_dc_hold_dc_out(dc);
1254         dc->out->user_needs_vblank = true;
1255
1256         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1257         init_completion(&dc->out->user_vblank_comp);
1258         tegra_dc_release_dc_out(dc);
1259
1260         return ret;
1261 }
1262
1263 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1264 {
1265         /* Do the actual brightness update outside of the mutex dc->lock */
1266         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1267                 dc->out->sd_settings->bl_device_name) {
1268                 char *bl_device_name =
1269                         dc->out->sd_settings->bl_device_name;
1270                 dc->out->sd_settings->bl_device =
1271                         get_backlight_device_by_name(bl_device_name);
1272         }
1273
1274         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1275                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1276                 backlight_update_status(bl);
1277         }
1278 }
1279
1280 static void tegra_dc_vblank(struct work_struct *work)
1281 {
1282         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1283         bool nvsd_updated = false;
1284
1285         mutex_lock(&dc->lock);
1286
1287         if (!dc->enabled) {
1288                 mutex_unlock(&dc->lock);
1289                 return;
1290         }
1291
1292         tegra_dc_io_start(dc);
1293         tegra_dc_hold_dc_out(dc);
1294         /* use the new frame's bandwidth setting instead of max(current, new),
1295          * skip this if we're using tegra_dc_one_shot_worker() */
1296         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1297                 tegra_dc_program_bandwidth(dc, true);
1298
1299         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1300         if (!tegra_dc_windows_are_dirty(dc))
1301                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1302
1303         /* Update the SD brightness */
1304         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1305                 nvsd_updated = nvsd_update_brightness(dc);
1306                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1307                  * V_BLANK_NVSD bit of vblank ref-count. */
1308                 if (nvsd_updated) {
1309                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1310                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1311                 } else {
1312                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1313                 }
1314         }
1315
1316         /* Mask vblank interrupt if ref-count is zero. */
1317         if (!dc->vblank_ref_count)
1318                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1319
1320         tegra_dc_release_dc_out(dc);
1321         tegra_dc_io_end(dc);
1322         mutex_unlock(&dc->lock);
1323
1324         /* Do the actual brightness update outside of the mutex dc->lock */
1325         if (nvsd_updated)
1326                 tegra_dc_prism_update_backlight(dc);
1327 }
1328
1329 static void tegra_dc_one_shot_worker(struct work_struct *work)
1330 {
1331         struct tegra_dc *dc = container_of(
1332                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1333         mutex_lock(&dc->lock);
1334
1335         /* memory client has gone idle */
1336         tegra_dc_clear_bandwidth(dc);
1337
1338         if (dc->out_ops->idle) {
1339                 tegra_dc_io_start(dc);
1340                 dc->out_ops->idle(dc);
1341                 tegra_dc_io_end(dc);
1342         }
1343
1344         mutex_unlock(&dc->lock);
1345 }
1346
1347 /* return an arbitrarily large number if count overflow occurs.
1348  * make it a nice base-10 number to show up in stats output */
1349 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1350 {
1351         unsigned count = tegra_dc_readl(dc, reg);
1352
1353         tegra_dc_writel(dc, 0, reg);
1354         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1355 }
1356
1357 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1358 {
1359         int i;
1360
1361         dc->stats.underflows++;
1362         if (dc->underflow_mask & WIN_A_UF_INT)
1363                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1364                         DC_WINBUF_AD_UFLOW_STATUS);
1365         if (dc->underflow_mask & WIN_B_UF_INT)
1366                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1367                         DC_WINBUF_BD_UFLOW_STATUS);
1368         if (dc->underflow_mask & WIN_C_UF_INT)
1369                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1370                         DC_WINBUF_CD_UFLOW_STATUS);
1371
1372         /* Check for any underflow reset conditions */
1373         for (i = 0; i < DC_N_WINDOWS; i++) {
1374                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1375                         dc->windows[i].underflows++;
1376
1377 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1378                         if (dc->windows[i].underflows > 4) {
1379                                 schedule_work(&dc->reset_work);
1380                                 /* reset counter */
1381                                 dc->windows[i].underflows = 0;
1382                                 trace_display_reset(dc);
1383                         }
1384 #endif
1385 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1386                         if (dc->windows[i].underflows > 4) {
1387                                 trace_display_reset(dc);
1388                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1389                                                 DC_DISP_DISP_MISC_CONTROL);
1390                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1391                                                 DC_CMD_STATE_CONTROL);
1392                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1393                                                 DC_CMD_STATE_CONTROL);
1394
1395                                 tegra_dc_writel(dc, 0,
1396                                                 DC_DISP_DISP_MISC_CONTROL);
1397                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1398                                                 DC_CMD_STATE_CONTROL);
1399                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1400                                                 DC_CMD_STATE_CONTROL);
1401                         }
1402 #endif
1403                 } else {
1404                         dc->windows[i].underflows = 0;
1405                 }
1406         }
1407
1408         /* Clear the underflow mask now that we've checked it. */
1409         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1410         dc->underflow_mask = 0;
1411         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1412         trace_underflow(dc);
1413 }
1414
1415 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1416 static void tegra_dc_vpulse2(struct work_struct *work)
1417 {
1418         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1419         bool nvsd_updated = false;
1420
1421         mutex_lock(&dc->lock);
1422
1423         if (!dc->enabled) {
1424                 mutex_unlock(&dc->lock);
1425                 return;
1426         }
1427
1428         tegra_dc_io_start(dc);
1429         tegra_dc_hold_dc_out(dc);
1430
1431         /* Clear the V_PULSE2_FLIP if no update */
1432         if (!tegra_dc_windows_are_dirty(dc))
1433                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1434
1435         /* Update the SD brightness */
1436         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1437                 nvsd_updated = nvsd_update_brightness(dc);
1438                 if (nvsd_updated) {
1439                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1440                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1441                 } else {
1442                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1443                 }
1444         }
1445
1446         /* Mask vpulse2 interrupt if ref-count is zero. */
1447         if (!dc->vpulse2_ref_count)
1448                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1449
1450         tegra_dc_release_dc_out(dc);
1451         tegra_dc_io_end(dc);
1452         mutex_unlock(&dc->lock);
1453
1454         /* Do the actual brightness update outside of the mutex dc->lock */
1455         if (nvsd_updated)
1456                 tegra_dc_prism_update_backlight(dc);
1457 }
1458 #endif
1459
1460 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1461 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1462 {
1463         /* pending user vblank, so wakeup */
1464         if ((status & (V_BLANK_INT | MSF_INT)) &&
1465             (dc->out->user_needs_vblank)) {
1466                 dc->out->user_needs_vblank = false;
1467                 complete(&dc->out->user_vblank_comp);
1468         }
1469
1470         if (status & V_BLANK_INT) {
1471                 /* Sync up windows. */
1472                 tegra_dc_trigger_windows(dc);
1473
1474                 /* Schedule any additional bottom-half vblank actvities. */
1475                 queue_work(system_freezable_wq, &dc->vblank_work);
1476         }
1477
1478         if (status & FRAME_END_INT) {
1479                 /* Mark the frame_end as complete. */
1480                 if (!completion_done(&dc->frame_end_complete))
1481                         complete(&dc->frame_end_complete);
1482         }
1483
1484 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1485         if (status & V_PULSE2_INT)
1486                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1487 #endif
1488 }
1489
1490 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1491 {
1492         /* Schedule any additional bottom-half vblank actvities. */
1493         if (status & V_BLANK_INT)
1494                 queue_work(system_freezable_wq, &dc->vblank_work);
1495
1496         if (status & FRAME_END_INT) {
1497                 struct timespec tm = CURRENT_TIME;
1498                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1499                 wake_up(&dc->timestamp_wq);
1500
1501                 /* Mark the frame_end as complete. */
1502                 if (!completion_done(&dc->frame_end_complete))
1503                         complete(&dc->frame_end_complete);
1504
1505                 tegra_dc_trigger_windows(dc);
1506         }
1507
1508 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1509         if (status & V_PULSE2_INT)
1510                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1511 #endif
1512 }
1513
1514 /* XXX: Not sure if we limit look ahead to 1 frame */
1515 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1516 {
1517         BUG_ON(!dc->frametime_ns);
1518         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1519 }
1520
1521 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1522 {
1523         BUG_ON(!dc->frametime_ns);
1524         return (((new_ts - old_ts) > dc->frametime_ns)
1525                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1526                         != div_s64((old_ts - dc->frame_end_timestamp),
1527                                 dc->frametime_ns)));
1528 }
1529 #endif
1530
1531 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1532 {
1533 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1534         struct tegra_dc *dc = ptr;
1535         unsigned long status;
1536         unsigned long underflow_mask;
1537         u32 val;
1538
1539         mutex_lock(&dc->lock);
1540         if (!dc->enabled) {
1541                 mutex_unlock(&dc->lock);
1542                 return IRQ_HANDLED;
1543         }
1544
1545         clk_enable(dc->clk);
1546         tegra_dc_io_start(dc);
1547         tegra_dc_hold_dc_out(dc);
1548
1549         if (!nvhost_module_powered_ext(dc->ndev)) {
1550                 WARN(1, "IRQ when DC not powered!\n");
1551                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1552                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1553                 tegra_dc_release_dc_out(dc);
1554                 tegra_dc_io_end(dc);
1555                 clk_disable(dc->clk);
1556                 mutex_unlock(&dc->lock);
1557                 return IRQ_HANDLED;
1558         }
1559
1560         /* clear all status flags except underflow, save those for the worker */
1561         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1562         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1563         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1564         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1565
1566         /*
1567          * Overlays can get thier internal state corrupted during and underflow
1568          * condition.  The only way to fix this state is to reset the DC.
1569          * if we get 4 consecutive frames with underflows, assume we're
1570          * hosed and reset.
1571          */
1572         underflow_mask = status & ALL_UF_INT;
1573
1574         /* Check underflow */
1575         if (underflow_mask) {
1576                 dc->underflow_mask |= underflow_mask;
1577                 schedule_delayed_work(&dc->underflow_work,
1578                         msecs_to_jiffies(1));
1579         }
1580
1581         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1582                 tegra_dc_one_shot_irq(dc, status);
1583         else
1584                 tegra_dc_continuous_irq(dc, status);
1585
1586         /* update video mode if it has changed since the last frame */
1587         if (status & (FRAME_END_INT | V_BLANK_INT))
1588                 tegra_dc_update_mode(dc);
1589
1590         tegra_dc_release_dc_out(dc);
1591         tegra_dc_io_end(dc);
1592         clk_disable(dc->clk);
1593         mutex_unlock(&dc->lock);
1594
1595         return IRQ_HANDLED;
1596 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1597         return IRQ_NONE;
1598 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1599 }
1600
1601 void tegra_dc_set_color_control(struct tegra_dc *dc)
1602 {
1603         u32 color_control;
1604
1605         switch (dc->out->depth) {
1606         case 3:
1607                 color_control = BASE_COLOR_SIZE111;
1608                 break;
1609
1610         case 6:
1611                 color_control = BASE_COLOR_SIZE222;
1612                 break;
1613
1614         case 8:
1615                 color_control = BASE_COLOR_SIZE332;
1616                 break;
1617
1618         case 9:
1619                 color_control = BASE_COLOR_SIZE333;
1620                 break;
1621
1622         case 12:
1623                 color_control = BASE_COLOR_SIZE444;
1624                 break;
1625
1626         case 15:
1627                 color_control = BASE_COLOR_SIZE555;
1628                 break;
1629
1630         case 16:
1631                 color_control = BASE_COLOR_SIZE565;
1632                 break;
1633
1634         case 18:
1635                 color_control = BASE_COLOR_SIZE666;
1636                 break;
1637
1638         default:
1639                 color_control = BASE_COLOR_SIZE888;
1640                 break;
1641         }
1642
1643         switch (dc->out->dither) {
1644         case TEGRA_DC_DISABLE_DITHER:
1645                 color_control |= DITHER_CONTROL_DISABLE;
1646                 break;
1647         case TEGRA_DC_ORDERED_DITHER:
1648                 color_control |= DITHER_CONTROL_ORDERED;
1649                 break;
1650         case TEGRA_DC_ERRDIFF_DITHER:
1651                 /* The line buffer for error-diffusion dither is limited
1652                  * to 1280 pixels per line. This limits the maximum
1653                  * horizontal active area size to 1280 pixels when error
1654                  * diffusion is enabled.
1655                  */
1656                 BUG_ON(dc->mode.h_active > 1280);
1657                 color_control |= DITHER_CONTROL_ERRDIFF;
1658                 break;
1659         }
1660
1661 #ifdef CONFIG_TEGRA_DC_CMU
1662         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1663                 color_control |= CMU_ENABLE;
1664 #endif
1665
1666         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1667 }
1668
1669 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1670 {
1671         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1672                 return dc->win_syncpt[idx];
1673         BUG();
1674 }
1675
1676 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1677 {
1678 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1679         u32 start, end;
1680         unsigned long val;
1681
1682         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1683         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1684
1685         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1686                 dc->mode.v_back_porch + dc->mode.v_active;
1687         end = start + 1;
1688         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1689         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1690
1691         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1692         val |= V_PULSE2_INT;
1693         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1694
1695         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1696         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1697 #endif
1698 }
1699
1700 static int tegra_dc_init(struct tegra_dc *dc)
1701 {
1702         int i;
1703         int int_enable;
1704
1705         tegra_dc_io_start(dc);
1706         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1707         if (dc->ndev->id == 0) {
1708                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1709                                       TEGRA_MC_PRIO_MED);
1710                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1711                                       TEGRA_MC_PRIO_MED);
1712                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1713                                       TEGRA_MC_PRIO_MED);
1714 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1715                 /* only present on Tegra2 and 3 */
1716                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1717                                       TEGRA_MC_PRIO_MED);
1718 #endif
1719                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1720                                       TEGRA_MC_PRIO_HIGH);
1721         } else if (dc->ndev->id == 1) {
1722                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1723                                       TEGRA_MC_PRIO_MED);
1724                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1725                                       TEGRA_MC_PRIO_MED);
1726                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1727                                       TEGRA_MC_PRIO_MED);
1728 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1729                 /* only present on Tegra2 and 3 */
1730                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1731                                       TEGRA_MC_PRIO_MED);
1732 #endif
1733                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1734                                       TEGRA_MC_PRIO_HIGH);
1735         }
1736         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1737                         DC_CMD_CONT_SYNCPT_VSYNC);
1738
1739         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1740         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1741         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1742         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1743 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1744         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1745 #endif
1746         /* enable interrupts for vblank, frame_end and underflows */
1747         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1748         /* for panels with one-shot mode enable tearing effect interrupt */
1749         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1750                 int_enable |= MSF_INT;
1751
1752         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1753         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1754         tegra_dc_init_vpulse2_int(dc);
1755
1756         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1757
1758 #ifdef CONFIG_TEGRA_DC_CMU
1759         if (dc->pdata->cmu)
1760                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1761         else
1762                 _tegra_dc_update_cmu(dc, &default_cmu);
1763 #endif
1764         tegra_dc_set_color_control(dc);
1765         for (i = 0; i < DC_N_WINDOWS; i++) {
1766                 struct tegra_dc_win *win = &dc->windows[i];
1767                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1768                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1769                 tegra_dc_set_csc(dc, &win->csc);
1770                 tegra_dc_set_lut(dc, win);
1771                 tegra_dc_set_scaling_filter(dc);
1772         }
1773
1774         for (i = 0; i < dc->n_windows; i++) {
1775                 u32 syncpt = get_syncpt(dc, i);
1776
1777                 dc->syncpt[i].id = syncpt;
1778
1779                 dc->syncpt[i].min = dc->syncpt[i].max =
1780                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1781         }
1782
1783         trace_display_mode(dc, &dc->mode);
1784
1785         if (dc->mode.pclk) {
1786                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1787                         tegra_dc_io_end(dc);
1788                         return -EINVAL;
1789                 }
1790         }
1791
1792         /* Initialize SD AFTER the modeset.
1793            nvsd_init handles the sd_settings = NULL case. */
1794         nvsd_init(dc, dc->out->sd_settings);
1795
1796         tegra_dc_io_end(dc);
1797
1798         return 0;
1799 }
1800
1801 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1802 {
1803         int failed_init = 0;
1804
1805         mutex_lock(&status_lock);
1806         tegra_dc_unpowergate_locked(dc);
1807         mutex_unlock(&status_lock);
1808
1809         if (dc->out->enable)
1810                 dc->out->enable(&dc->ndev->dev);
1811
1812         tegra_dc_setup_clk(dc, dc->clk);
1813         tegra_dc_clk_enable(dc);
1814         tegra_dc_io_start(dc);
1815
1816         tegra_dc_power_on(dc);
1817
1818         /* do not accept interrupts during initialization */
1819         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1820
1821         enable_dc_irq(dc);
1822
1823         failed_init = tegra_dc_init(dc);
1824         if (failed_init) {
1825                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1826                 disable_irq_nosync(dc->irq);
1827                 tegra_dc_clear_bandwidth(dc);
1828                 tegra_dc_clk_disable(dc);
1829                 if (dc->out && dc->out->disable)
1830                         dc->out->disable();
1831                 tegra_dc_io_end(dc);
1832                 return false;
1833         }
1834
1835         if (dc->out_ops && dc->out_ops->enable)
1836                 dc->out_ops->enable(dc);
1837
1838         /* force a full blending update */
1839         dc->blend.z[0] = -1;
1840
1841         tegra_dc_ext_enable(dc->ext);
1842
1843         trace_display_enable(dc);
1844
1845         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1846         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1847
1848         if (dc->out->postpoweron)
1849                 dc->out->postpoweron();
1850
1851         tegra_dc_io_end(dc);
1852         return true;
1853 }
1854
1855 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1856 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1857 {
1858         bool ret = true;
1859
1860         if (dc->out->enable)
1861                 dc->out->enable(&dc->ndev->dev);
1862
1863         tegra_dc_setup_clk(dc, dc->clk);
1864         tegra_dc_clk_enable(dc);
1865
1866         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1867                 mutex_lock(&tegra_dcs[1]->lock);
1868                 disable_irq_nosync(tegra_dcs[1]->irq);
1869         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1870                 mutex_lock(&tegra_dcs[0]->lock);
1871                 disable_irq_nosync(tegra_dcs[0]->irq);
1872         }
1873
1874         msleep(5);
1875         tegra_periph_reset_assert(dc->clk);
1876         msleep(2);
1877 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1878         tegra_periph_reset_deassert(dc->clk);
1879         msleep(1);
1880 #endif
1881
1882         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1883                 enable_dc_irq(tegra_dcs[1]);
1884                 mutex_unlock(&tegra_dcs[1]->lock);
1885         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1886                 enable_dc_irq(tegra_dcs[0]);
1887                 mutex_unlock(&tegra_dcs[0]->lock);
1888         }
1889
1890         enable_dc_irq(dc);
1891
1892         if (tegra_dc_init(dc)) {
1893                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1894                 ret = false;
1895         }
1896
1897         if (dc->out_ops && dc->out_ops->enable)
1898                 dc->out_ops->enable(dc);
1899
1900         if (dc->out->postpoweron)
1901                 dc->out->postpoweron();
1902
1903         /* force a full blending update */
1904         dc->blend.z[0] = -1;
1905
1906         tegra_dc_ext_enable(dc->ext);
1907
1908         if (!ret) {
1909                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1910                 _tegra_dc_controller_disable(dc);
1911         }
1912
1913         trace_display_reset(dc);
1914         return ret;
1915 }
1916 #endif
1917
1918 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1919 {
1920         if (dc->mode.pclk == 0) {
1921                 switch (dc->out->type) {
1922                 case TEGRA_DC_OUT_HDMI:
1923                 /* DC enable called but no videomode is loaded.
1924                      Check if HDMI is connected, then set fallback mdoe */
1925                 if (tegra_dc_hpd(dc)) {
1926                         return tegra_dc_set_fb_mode(dc,
1927                                         &tegra_dc_hdmi_fallback_mode, 0);
1928                 } else
1929                         return false;
1930
1931                 break;
1932
1933                 /* Do nothing for other outputs for now */
1934                 case TEGRA_DC_OUT_RGB:
1935
1936                 case TEGRA_DC_OUT_DSI:
1937
1938                 default:
1939                         return false;
1940                 }
1941         }
1942
1943         return false;
1944 }
1945
1946 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1947 {
1948         return _tegra_dc_set_default_videomode(dc);
1949 }
1950
1951 static bool _tegra_dc_enable(struct tegra_dc *dc)
1952 {
1953         if (dc->mode.pclk == 0)
1954                 return false;
1955
1956         if (!dc->out)
1957                 return false;
1958
1959         if (dc->enabled)
1960                 return true;
1961
1962         if (!_tegra_dc_controller_enable(dc))
1963                 return false;
1964
1965         return true;
1966 }
1967
1968 void tegra_dc_enable(struct tegra_dc *dc)
1969 {
1970         mutex_lock(&dc->lock);
1971
1972         if (!dc->enabled)
1973                 dc->enabled = _tegra_dc_enable(dc);
1974
1975         mutex_unlock(&dc->lock);
1976         trace_display_mode(dc, &dc->mode);
1977 }
1978
1979 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1980 {
1981         unsigned i;
1982
1983         tegra_dc_hold_dc_out(dc);
1984
1985         if (dc->out && dc->out->prepoweroff)
1986                 dc->out->prepoweroff();
1987
1988         if (dc->out_ops && dc->out_ops->disable)
1989                 dc->out_ops->disable(dc);
1990
1991         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1992
1993         disable_irq_nosync(dc->irq);
1994
1995         tegra_dc_clear_bandwidth(dc);
1996         if (dc->out_ops->release) /* ugly hack */
1997                 tegra_dc_release_dc_out(dc);
1998         else
1999                 tegra_dc_clk_disable(dc);
2000
2001         if (dc->out && dc->out->disable)
2002                 dc->out->disable();
2003
2004         for (i = 0; i < dc->n_windows; i++) {
2005                 struct tegra_dc_win *w = &dc->windows[i];
2006
2007                 /* reset window bandwidth */
2008                 w->bandwidth = 0;
2009                 w->new_bandwidth = 0;
2010
2011                 /* disable windows */
2012                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2013
2014                 /* flush any pending syncpt waits */
2015                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2016                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2017                                 dc->syncpt[i].min, dc->syncpt[i].max);
2018                         dc->syncpt[i].min++;
2019                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2020                 }
2021         }
2022         trace_display_disable(dc);
2023 }
2024
2025 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2026 {
2027 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2028         u32 val;
2029         if (dc->enabled)  {
2030                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2031                 if (enable)
2032                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2033                 else
2034                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2035                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2036         }
2037 #endif
2038 }
2039
2040 bool tegra_dc_stats_get(struct tegra_dc *dc)
2041 {
2042 #if 0 /* right now it is always enabled */
2043         u32 val;
2044         bool res;
2045
2046         if (dc->enabled)  {
2047                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2048                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2049         } else {
2050                 res = false;
2051         }
2052
2053         return res;
2054 #endif
2055         return true;
2056 }
2057
2058 /* make the screen blank by disabling all windows */
2059 void tegra_dc_blank(struct tegra_dc *dc)
2060 {
2061         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2062         unsigned i;
2063
2064         for (i = 0; i < DC_N_WINDOWS; i++) {
2065                 dcwins[i] = tegra_dc_get_window(dc, i);
2066                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2067         }
2068
2069         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2070         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2071 }
2072
2073 static void _tegra_dc_disable(struct tegra_dc *dc)
2074 {
2075         struct tegra_dc *dc_partner;
2076         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2077                 mutex_lock(&dc->one_shot_lock);
2078                 cancel_delayed_work_sync(&dc->one_shot_work);
2079         }
2080
2081         mutex_lock(&status_lock);
2082
2083         tegra_dc_io_start(dc);
2084         _tegra_dc_controller_disable(dc);
2085         tegra_dc_io_end(dc);
2086
2087         /* Get the handler of the other display controller. */
2088         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2089         if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2090                 /* If DISB is powergated, then powergate DISA. */
2091                 if (!dc_partner->powered)
2092                         tegra_dc_powergate_locked(dc);
2093         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2094                 /* If DISA is enabled, only powergate DISB;
2095                  * otherwise, powergate DISA and DISB.
2096                  * */
2097                 if (dc_partner->enabled) {
2098                         tegra_dc_powergate_locked(dc);
2099                 } else {
2100                         tegra_dc_powergate_locked(dc);
2101                         tegra_dc_powergate_locked(dc_partner);
2102                 }
2103         }
2104         mutex_unlock(&status_lock);
2105
2106         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2107                 mutex_unlock(&dc->one_shot_lock);
2108 }
2109
2110 void tegra_dc_disable(struct tegra_dc *dc)
2111 {
2112         tegra_dc_ext_disable(dc->ext);
2113
2114         /* it's important that new underflow work isn't scheduled before the
2115          * lock is acquired. */
2116         cancel_delayed_work_sync(&dc->underflow_work);
2117
2118         mutex_lock(&dc->lock);
2119
2120         if (dc->enabled) {
2121                 dc->enabled = false;
2122
2123                 if (!dc->suspended)
2124                         _tegra_dc_disable(dc);
2125         }
2126
2127 #ifdef CONFIG_SWITCH
2128         switch_set_state(&dc->modeset_switch, 0);
2129 #endif
2130
2131         mutex_unlock(&dc->lock);
2132         synchronize_irq(dc->irq);
2133         trace_display_mode(dc, &dc->mode);
2134 }
2135
2136 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2137 static void tegra_dc_reset_worker(struct work_struct *work)
2138 {
2139         struct tegra_dc *dc =
2140                 container_of(work, struct tegra_dc, reset_work);
2141
2142         unsigned long val = 0;
2143
2144         mutex_lock(&shared_lock);
2145
2146         dev_warn(&dc->ndev->dev,
2147                 "overlay stuck in underflow state.  resetting.\n");
2148
2149         tegra_dc_ext_disable(dc->ext);
2150
2151         mutex_lock(&dc->lock);
2152
2153         if (dc->enabled == false)
2154                 goto unlock;
2155
2156         dc->enabled = false;
2157
2158         /*
2159          * off host read bus
2160          */
2161         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2162         val &= ~(0x00000100);
2163         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2164
2165         /*
2166          * set DC to STOP mode
2167          */
2168         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2169
2170         msleep(10);
2171
2172         _tegra_dc_controller_disable(dc);
2173
2174         /* _tegra_dc_controller_reset_enable deasserts reset */
2175         _tegra_dc_controller_reset_enable(dc);
2176
2177         dc->enabled = true;
2178
2179         /* reopen host read bus */
2180         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2181         val &= ~(0x00000100);
2182         val |= 0x100;
2183         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2184
2185 unlock:
2186         mutex_unlock(&dc->lock);
2187         mutex_unlock(&shared_lock);
2188         trace_display_reset(dc);
2189 }
2190 #endif
2191
2192 static void tegra_dc_underflow_worker(struct work_struct *work)
2193 {
2194         struct tegra_dc *dc = container_of(
2195                 to_delayed_work(work), struct tegra_dc, underflow_work);
2196
2197         mutex_lock(&dc->lock);
2198         tegra_dc_io_start(dc);
2199         tegra_dc_hold_dc_out(dc);
2200
2201         if (dc->enabled) {
2202                 tegra_dc_underflow_handler(dc);
2203         }
2204         tegra_dc_release_dc_out(dc);
2205         tegra_dc_io_end(dc);
2206         mutex_unlock(&dc->lock);
2207 }
2208
2209 #ifdef CONFIG_SWITCH
2210 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2211 {
2212         struct tegra_dc *dc =
2213                 container_of(sdev, struct tegra_dc, modeset_switch);
2214
2215         if (!sdev->state)
2216                 return sprintf(buf, "offline\n");
2217
2218         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2219 }
2220 #endif
2221
2222 static void tegra_dc_add_modes(struct tegra_dc *dc)
2223 {
2224         struct fb_monspecs specs;
2225         int i;
2226
2227         memset(&specs, 0, sizeof(specs));
2228         specs.max_x = dc->mode.h_active * 1000;
2229         specs.max_y = dc->mode.v_active * 1000;
2230         specs.modedb_len = dc->out->n_modes;
2231         specs.modedb = kzalloc(specs.modedb_len *
2232                 sizeof(struct fb_videomode), GFP_KERNEL);
2233         for (i = 0; i < dc->out->n_modes; i++)
2234                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2235                         &dc->out->modes[i]);
2236         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2237         kfree(specs.modedb);
2238 }
2239
2240 static int tegra_dc_probe(struct platform_device *ndev)
2241 {
2242         struct tegra_dc *dc;
2243         struct tegra_dc_mode *mode;
2244         struct clk *clk;
2245         struct clk *emc_clk;
2246         struct resource *res;
2247         struct resource *base_res;
2248         struct resource *fb_mem = NULL;
2249         int ret = 0;
2250         void __iomem *base;
2251         int irq;
2252         int i;
2253
2254         if (!ndev->dev.platform_data) {
2255                 dev_err(&ndev->dev, "no platform data\n");
2256                 return -ENOENT;
2257         }
2258
2259         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2260         if (!dc) {
2261                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2262                 return -ENOMEM;
2263         }
2264
2265         irq = platform_get_irq_byname(ndev, "irq");
2266         if (irq <= 0) {
2267                 dev_err(&ndev->dev, "no irq\n");
2268                 ret = -ENOENT;
2269                 goto err_free;
2270         }
2271
2272         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2273         if (!res) {
2274                 dev_err(&ndev->dev, "no mem resource\n");
2275                 ret = -ENOENT;
2276                 goto err_free;
2277         }
2278
2279         base_res = request_mem_region(res->start, resource_size(res),
2280                 ndev->name);
2281         if (!base_res) {
2282                 dev_err(&ndev->dev, "request_mem_region failed\n");
2283                 ret = -EBUSY;
2284                 goto err_free;
2285         }
2286
2287         base = ioremap(res->start, resource_size(res));
2288         if (!base) {
2289                 dev_err(&ndev->dev, "registers can't be mapped\n");
2290                 ret = -EBUSY;
2291                 goto err_release_resource_reg;
2292         }
2293         if (TEGRA_DISPLAY_BASE == res->start) {
2294                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2295                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2296                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2297                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2298                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2299         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2300                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2301                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2302                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2303                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2304                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2305         } else {
2306                 dev_err(&ndev->dev,
2307                         "Unknown base address %#08x: unable to assign syncpt\n",
2308                         res->start);
2309         }
2310
2311
2312         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2313
2314         clk = clk_get(&ndev->dev, NULL);
2315         if (IS_ERR_OR_NULL(clk)) {
2316                 dev_err(&ndev->dev, "can't get clock\n");
2317                 ret = -ENOENT;
2318                 goto err_iounmap_reg;
2319         }
2320
2321         emc_clk = clk_get(&ndev->dev, "emc");
2322         if (IS_ERR_OR_NULL(emc_clk)) {
2323                 dev_err(&ndev->dev, "can't get emc clock\n");
2324                 ret = -ENOENT;
2325                 goto err_put_clk;
2326         }
2327
2328         dc->clk = clk;
2329         dc->emc_clk = emc_clk;
2330         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2331         /* Initialize one shot work delay, it will be assigned by dsi
2332          * according to refresh rate later. */
2333         dc->one_shot_delay_ms = 40;
2334
2335         dc->base_res = base_res;
2336         dc->base = base;
2337         dc->irq = irq;
2338         dc->ndev = ndev;
2339         dc->pdata = ndev->dev.platform_data;
2340
2341         /*
2342          * The emc is a shared clock, it will be set based on
2343          * the requirements for each user on the bus.
2344          */
2345         dc->emc_clk_rate = 0;
2346
2347         mutex_init(&dc->lock);
2348         mutex_init(&dc->one_shot_lock);
2349         mutex_init(&status_lock);
2350         init_completion(&dc->frame_end_complete);
2351         init_waitqueue_head(&dc->wq);
2352         init_waitqueue_head(&dc->timestamp_wq);
2353 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2354         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2355 #endif
2356         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2357         dc->vblank_ref_count = 0;
2358 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2359         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2360 #endif
2361         dc->vpulse2_ref_count = 0;
2362         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2363         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2364
2365         tegra_dc_init_lut_defaults(&dc->fb_lut);
2366
2367         dc->n_windows = DC_N_WINDOWS;
2368         for (i = 0; i < dc->n_windows; i++) {
2369                 struct tegra_dc_win *win = &dc->windows[i];
2370                 win->idx = i;
2371                 win->dc = dc;
2372                 tegra_dc_init_csc_defaults(&win->csc);
2373                 tegra_dc_init_lut_defaults(&win->lut);
2374         }
2375
2376         ret = tegra_dc_set(dc, ndev->id);
2377         if (ret < 0) {
2378                 dev_err(&ndev->dev, "can't add dc\n");
2379                 goto err_free_irq;
2380         }
2381
2382         platform_set_drvdata(ndev, dc);
2383
2384 #ifdef CONFIG_SWITCH
2385         dc->modeset_switch.name = dev_name(&ndev->dev);
2386         dc->modeset_switch.state = 0;
2387         dc->modeset_switch.print_state = switch_modeset_print_mode;
2388         ret = switch_dev_register(&dc->modeset_switch);
2389         if (ret < 0)
2390                 dev_err(&ndev->dev, "failed to register switch driver\n");
2391 #endif
2392
2393         tegra_dc_feature_register(dc);
2394
2395         if (dc->pdata->default_out)
2396                 tegra_dc_set_out(dc, dc->pdata->default_out);
2397         else
2398                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2399
2400         dc->ext = tegra_dc_ext_register(ndev, dc);
2401         if (IS_ERR_OR_NULL(dc->ext)) {
2402                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2403                 dc->ext = NULL;
2404         }
2405
2406         /* interrupt handler must be registered before tegra_fb_register() */
2407         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2408                         dev_name(&ndev->dev), dc)) {
2409                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2410                 ret = -EBUSY;
2411                 goto err_put_emc_clk;
2412         }
2413         disable_dc_irq(dc);
2414
2415         mutex_lock(&dc->lock);
2416         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2417                 _tegra_dc_set_default_videomode(dc);
2418                 dc->enabled = _tegra_dc_enable(dc);
2419         }
2420         mutex_unlock(&dc->lock);
2421
2422         tegra_dc_create_debugfs(dc);
2423
2424         dev_info(&ndev->dev, "probed\n");
2425
2426         if (dc->pdata->fb) {
2427                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2428                         unsigned long fmt;
2429                         tegra_dc_writel(dc,
2430                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2431                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2432
2433                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2434                         dc->pdata->fb->bits_per_pixel =
2435                                 tegra_dc_fmt_bpp(fmt);
2436                 }
2437
2438                 mode = tegra_dc_get_override_mode(dc);
2439                 if (mode) {
2440                         dc->pdata->fb->xres = mode->h_active;
2441                         dc->pdata->fb->yres = mode->v_active;
2442                 }
2443
2444                 tegra_dc_io_start(dc);
2445                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2446                 if (IS_ERR_OR_NULL(dc->fb))
2447                         dc->fb = NULL;
2448                 tegra_dc_io_end(dc);
2449         }
2450
2451         if (dc->out && dc->out->n_modes)
2452                 tegra_dc_add_modes(dc);
2453
2454         if (dc->out && dc->out->hotplug_init)
2455                 dc->out->hotplug_init(&ndev->dev);
2456
2457         if (dc->out_ops && dc->out_ops->detect)
2458                 dc->out_ops->detect(dc);
2459         else
2460                 dc->connected = true;
2461
2462 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2463         mutex_lock(&status_lock);
2464         /* Powergate display module when it's unconnected. */
2465         if (!tegra_dc_get_connected(dc))
2466                 tegra_dc_powergate_locked(dc);
2467         mutex_unlock(&status_lock);
2468 #endif
2469
2470         tegra_dc_create_sysfs(&dc->ndev->dev);
2471
2472         return 0;
2473
2474 err_free_irq:
2475         free_irq(irq, dc);
2476 err_put_emc_clk:
2477         clk_put(emc_clk);
2478 err_put_clk:
2479         clk_put(clk);
2480 err_iounmap_reg:
2481         iounmap(base);
2482         if (fb_mem)
2483                 release_resource(fb_mem);
2484 err_release_resource_reg:
2485         release_resource(base_res);
2486 err_free:
2487         kfree(dc);
2488
2489         return ret;
2490 }
2491
2492 static int tegra_dc_remove(struct platform_device *ndev)
2493 {
2494         struct tegra_dc *dc = platform_get_drvdata(ndev);
2495
2496         tegra_dc_remove_sysfs(&dc->ndev->dev);
2497         tegra_dc_remove_debugfs(dc);
2498
2499         if (dc->fb) {
2500                 tegra_fb_unregister(dc->fb);
2501                 if (dc->fb_mem)
2502                         release_resource(dc->fb_mem);
2503         }
2504
2505         tegra_dc_ext_disable(dc->ext);
2506
2507         if (dc->ext)
2508                 tegra_dc_ext_unregister(dc->ext);
2509
2510         mutex_lock(&dc->lock);
2511         if (dc->enabled)
2512                 _tegra_dc_disable(dc);
2513         dc->enabled = false;
2514         mutex_unlock(&dc->lock);
2515         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2516
2517 #ifdef CONFIG_SWITCH
2518         switch_dev_unregister(&dc->modeset_switch);
2519 #endif
2520         free_irq(dc->irq, dc);
2521         clk_put(dc->emc_clk);
2522         clk_put(dc->clk);
2523         iounmap(dc->base);
2524         if (dc->fb_mem)
2525                 release_resource(dc->base_res);
2526         kfree(dc);
2527         tegra_dc_set(NULL, ndev->id);
2528
2529         return 0;
2530 }
2531
2532 #ifdef CONFIG_PM
2533 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2534 {
2535         struct tegra_dc *dc = platform_get_drvdata(ndev);
2536
2537         trace_display_suspend(dc);
2538         dev_info(&ndev->dev, "suspend\n");
2539
2540         tegra_dc_ext_disable(dc->ext);
2541
2542         mutex_lock(&dc->lock);
2543         tegra_dc_io_start(dc);
2544
2545         if (dc->out_ops && dc->out_ops->suspend)
2546                 dc->out_ops->suspend(dc);
2547
2548         if (dc->enabled) {
2549                 _tegra_dc_disable(dc);
2550
2551                 dc->suspended = true;
2552         }
2553
2554         if (dc->out && dc->out->postsuspend) {
2555                 dc->out->postsuspend();
2556                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2557                         /*
2558                          * avoid resume event due to voltage falling
2559                          */
2560                         msleep(100);
2561         }
2562
2563         tegra_dc_io_end(dc);
2564         mutex_unlock(&dc->lock);
2565         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2566
2567         return 0;
2568 }
2569
2570 static int tegra_dc_resume(struct platform_device *ndev)
2571 {
2572         struct tegra_dc *dc = platform_get_drvdata(ndev);
2573
2574         trace_display_resume(dc);
2575         dev_info(&ndev->dev, "resume\n");
2576
2577         mutex_lock(&dc->lock);
2578         dc->suspended = false;
2579
2580         if (dc->enabled) {
2581                 dc->enabled = false;
2582                 _tegra_dc_set_default_videomode(dc);
2583                 dc->enabled = _tegra_dc_enable(dc);
2584         }
2585
2586         if (dc->out && dc->out->hotplug_init)
2587                 dc->out->hotplug_init(&ndev->dev);
2588
2589         if (dc->out_ops && dc->out_ops->resume)
2590                 dc->out_ops->resume(dc);
2591         mutex_unlock(&dc->lock);
2592
2593         return 0;
2594 }
2595
2596 #endif /* CONFIG_PM */
2597
2598 static void tegra_dc_shutdown(struct platform_device *ndev)
2599 {
2600         struct tegra_dc *dc = platform_get_drvdata(ndev);
2601
2602         if (!dc || !dc->enabled)
2603                 return;
2604
2605         tegra_dc_blank(dc);
2606         tegra_dc_disable(dc);
2607 }
2608
2609 extern int suspend_set(const char *val, struct kernel_param *kp)
2610 {
2611         if (!strcmp(val, "dump"))
2612                 dump_regs(tegra_dcs[0]);
2613 #ifdef CONFIG_PM
2614         else if (!strcmp(val, "suspend"))
2615                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2616         else if (!strcmp(val, "resume"))
2617                 tegra_dc_resume(tegra_dcs[0]->ndev);
2618 #endif
2619
2620         return 0;
2621 }
2622
2623 extern int suspend_get(char *buffer, struct kernel_param *kp)
2624 {
2625         return 0;
2626 }
2627
2628 int suspend;
2629
2630 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2631
2632 struct platform_driver tegra_dc_driver = {
2633         .driver = {
2634                 .name = "tegradc",
2635                 .owner = THIS_MODULE,
2636         },
2637         .probe = tegra_dc_probe,
2638         .remove = tegra_dc_remove,
2639 #ifdef CONFIG_PM
2640         .suspend = tegra_dc_suspend,
2641         .resume = tegra_dc_resume,
2642 #endif
2643         .shutdown = tegra_dc_shutdown,
2644 };
2645
2646 #ifndef MODULE
2647 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2648 {
2649         int i, params[11];
2650         char *p;
2651
2652         for (i = 0; i < ARRAY_SIZE(params); i++) {
2653                 if ((p = strsep(&options, ",")) != NULL) {
2654                         if (*p)
2655                                 params[i] = simple_strtoul(p, &p, 10);
2656                 } else
2657                         return -EINVAL;
2658         }
2659
2660         if ((mode->pclk = params[0]) == 0)
2661                 return -EINVAL;
2662
2663         mode->h_active      = params[1];
2664         mode->v_active      = params[2];
2665         mode->h_ref_to_sync = params[3];
2666         mode->v_ref_to_sync = params[4];
2667         mode->h_sync_width  = params[5];
2668         mode->v_sync_width  = params[6];
2669         mode->h_back_porch  = params[7];
2670         mode->v_back_porch  = params[8];
2671         mode->h_front_porch = params[9];
2672         mode->v_front_porch = params[10];
2673
2674         return 0;
2675 }
2676
2677 static int __init tegra_dc_mode_override(char *str)
2678 {
2679         char *p = str, *options;
2680
2681         if (!p || !*p)
2682                 return -EINVAL;
2683
2684         p = strstr(str, "hdmi:");
2685         if (p) {
2686                 p += 5;
2687                 options = strsep(&p, ";");
2688                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2689                         return -EINVAL;
2690         }
2691
2692         p = strstr(str, "rgb:");
2693         if (p) {
2694                 p += 4;
2695                 options = strsep(&p, ";");
2696                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2697                         return -EINVAL;
2698         }
2699
2700         p = strstr(str, "dsi:");
2701         if (p) {
2702                 p += 4;
2703                 options = strsep(&p, ";");
2704                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2705                         return -EINVAL;
2706         }
2707
2708         return 0;
2709 }
2710
2711 __setup("disp_params=", tegra_dc_mode_override);
2712 #endif
2713
2714 static int __init tegra_dc_module_init(void)
2715 {
2716         int ret = tegra_dc_ext_module_init();
2717         if (ret)
2718                 return ret;
2719         return platform_driver_register(&tegra_dc_driver);
2720 }
2721
2722 static void __exit tegra_dc_module_exit(void)
2723 {
2724         platform_driver_unregister(&tegra_dc_driver);
2725         tegra_dc_ext_module_exit();
2726 }
2727
2728 module_exit(tegra_dc_module_exit);
2729 module_init(tegra_dc_module_init);