video: tegra: dc: remove duplicate code
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53 #include <mach/iomap.h>
54
55 #include "dc_reg.h"
56 #include "dc_config.h"
57 #include "dc_priv.h"
58 #include "dev.h"
59 #include "nvsd.h"
60
61 #define TEGRA_CRC_LATCHED_DELAY         34
62
63 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
64 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
65
66 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
67         .refresh = 60,
68         .xres = 640,
69         .yres = 480,
70         .pixclock = KHZ2PICOS(25200),
71         .hsync_len = 96,        /* h_sync_width */
72         .vsync_len = 2,         /* v_sync_width */
73         .left_margin = 48,      /* h_back_porch */
74         .upper_margin = 33,     /* v_back_porch */
75         .right_margin = 16,     /* h_front_porch */
76         .lower_margin = 10,     /* v_front_porch */
77         .vmode = 0,
78         .sync = 0,
79 };
80
81 static struct tegra_dc_mode override_disp_mode[3];
82
83 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
84
85 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
86
87 DEFINE_MUTEX(tegra_dc_lock);
88 DEFINE_MUTEX(shared_lock);
89
90 static const struct {
91         bool h;
92         bool v;
93 } can_filter[] = {
94         /* Window A has no filtering */
95         { false, false },
96         /* Window B has both H and V filtering */
97         { true,  true  },
98         /* Window C has only H filtering */
99         { false, true  },
100 };
101
102 #ifdef CONFIG_TEGRA_DC_CMU
103 static struct tegra_dc_cmu default_cmu = {
104         /* lut1 maps sRGB to linear space. */
105         {
106                 0,    1,    2,    4,    5,    6,    7,    9,
107                 10,   11,   12,   14,   15,   16,   18,   20,
108                 21,   23,   25,   27,   29,   31,   33,   35,
109                 37,   40,   42,   45,   48,   50,   53,   56,
110                 59,   62,   66,   69,   72,   76,   79,   83,
111                 87,   91,   95,   99,   103,  107,  112,  116,
112                 121,  126,  131,  136,  141,  146,  151,  156,
113                 162,  168,  173,  179,  185,  191,  197,  204,
114                 210,  216,  223,  230,  237,  244,  251,  258,
115                 265,  273,  280,  288,  296,  304,  312,  320,
116                 329,  337,  346,  354,  363,  372,  381,  390,
117                 400,  409,  419,  428,  438,  448,  458,  469,
118                 479,  490,  500,  511,  522,  533,  544,  555,
119                 567,  578,  590,  602,  614,  626,  639,  651,
120                 664,  676,  689,  702,  715,  728,  742,  755,
121                 769,  783,  797,  811,  825,  840,  854,  869,
122                 884,  899,  914,  929,  945,  960,  976,  992,
123                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
124                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
125                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
126                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
127                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
128                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
129                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
130                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
131                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
132                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
133                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
134                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
135                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
136                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
137                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
138         },
139         /* csc */
140         {
141                 0x100, 0x0,   0x0,
142                 0x0,   0x100, 0x0,
143                 0x0,   0x0,   0x100,
144         },
145         /* lut2 maps linear space to sRGB*/
146         {
147                 0,    1,    2,    2,    3,    4,    5,    6,
148                 6,    7,    8,    9,    10,   10,   11,   12,
149                 13,   13,   14,   15,   15,   16,   16,   17,
150                 18,   18,   19,   19,   20,   20,   21,   21,
151                 22,   22,   23,   23,   23,   24,   24,   25,
152                 25,   25,   26,   26,   27,   27,   27,   28,
153                 28,   29,   29,   29,   30,   30,   30,   31,
154                 31,   31,   32,   32,   32,   33,   33,   33,
155                 34,   34,   34,   34,   35,   35,   35,   36,
156                 36,   36,   37,   37,   37,   37,   38,   38,
157                 38,   38,   39,   39,   39,   40,   40,   40,
158                 40,   41,   41,   41,   41,   42,   42,   42,
159                 42,   43,   43,   43,   43,   43,   44,   44,
160                 44,   44,   45,   45,   45,   45,   46,   46,
161                 46,   46,   46,   47,   47,   47,   47,   48,
162                 48,   48,   48,   48,   49,   49,   49,   49,
163                 49,   50,   50,   50,   50,   50,   51,   51,
164                 51,   51,   51,   52,   52,   52,   52,   52,
165                 53,   53,   53,   53,   53,   54,   54,   54,
166                 54,   54,   55,   55,   55,   55,   55,   55,
167                 56,   56,   56,   56,   56,   57,   57,   57,
168                 57,   57,   57,   58,   58,   58,   58,   58,
169                 58,   59,   59,   59,   59,   59,   59,   60,
170                 60,   60,   60,   60,   60,   61,   61,   61,
171                 61,   61,   61,   62,   62,   62,   62,   62,
172                 62,   63,   63,   63,   63,   63,   63,   64,
173                 64,   64,   64,   64,   64,   64,   65,   65,
174                 65,   65,   65,   65,   66,   66,   66,   66,
175                 66,   66,   66,   67,   67,   67,   67,   67,
176                 67,   67,   68,   68,   68,   68,   68,   68,
177                 68,   69,   69,   69,   69,   69,   69,   69,
178                 70,   70,   70,   70,   70,   70,   70,   71,
179                 71,   71,   71,   71,   71,   71,   72,   72,
180                 72,   72,   72,   72,   72,   72,   73,   73,
181                 73,   73,   73,   73,   73,   74,   74,   74,
182                 74,   74,   74,   74,   74,   75,   75,   75,
183                 75,   75,   75,   75,   75,   76,   76,   76,
184                 76,   76,   76,   76,   77,   77,   77,   77,
185                 77,   77,   77,   77,   78,   78,   78,   78,
186                 78,   78,   78,   78,   78,   79,   79,   79,
187                 79,   79,   79,   79,   79,   80,   80,   80,
188                 80,   80,   80,   80,   80,   81,   81,   81,
189                 81,   81,   81,   81,   81,   81,   82,   82,
190                 82,   82,   82,   82,   82,   82,   83,   83,
191                 83,   83,   83,   83,   83,   83,   83,   84,
192                 84,   84,   84,   84,   84,   84,   84,   84,
193                 85,   85,   85,   85,   85,   85,   85,   85,
194                 85,   86,   86,   86,   86,   86,   86,   86,
195                 86,   86,   87,   87,   87,   87,   87,   87,
196                 87,   87,   87,   88,   88,   88,   88,   88,
197                 88,   88,   88,   88,   88,   89,   89,   89,
198                 89,   89,   89,   89,   89,   89,   90,   90,
199                 90,   90,   90,   90,   90,   90,   90,   90,
200                 91,   91,   91,   91,   91,   91,   91,   91,
201                 91,   91,   92,   92,   92,   92,   92,   92,
202                 92,   92,   92,   92,   93,   93,   93,   93,
203                 93,   93,   93,   93,   93,   93,   94,   94,
204                 94,   94,   94,   94,   94,   94,   94,   94,
205                 95,   95,   95,   95,   95,   95,   95,   95,
206                 95,   95,   96,   96,   96,   96,   96,   96,
207                 96,   96,   96,   96,   96,   97,   97,   97,
208                 97,   97,   97,   97,   97,   97,   97,   98,
209                 98,   98,   98,   98,   98,   98,   98,   98,
210                 98,   98,   99,   99,   99,   99,   99,   99,
211                 99,   100,  101,  101,  102,  103,  103,  104,
212                 105,  105,  106,  107,  107,  108,  109,  109,
213                 110,  111,  111,  112,  113,  113,  114,  115,
214                 115,  116,  116,  117,  118,  118,  119,  119,
215                 120,  120,  121,  122,  122,  123,  123,  124,
216                 124,  125,  126,  126,  127,  127,  128,  128,
217                 129,  129,  130,  130,  131,  131,  132,  132,
218                 133,  133,  134,  134,  135,  135,  136,  136,
219                 137,  137,  138,  138,  139,  139,  140,  140,
220                 141,  141,  142,  142,  143,  143,  144,  144,
221                 145,  145,  145,  146,  146,  147,  147,  148,
222                 148,  149,  149,  150,  150,  150,  151,  151,
223                 152,  152,  153,  153,  153,  154,  154,  155,
224                 155,  156,  156,  156,  157,  157,  158,  158,
225                 158,  159,  159,  160,  160,  160,  161,  161,
226                 162,  162,  162,  163,  163,  164,  164,  164,
227                 165,  165,  166,  166,  166,  167,  167,  167,
228                 168,  168,  169,  169,  169,  170,  170,  170,
229                 171,  171,  172,  172,  172,  173,  173,  173,
230                 174,  174,  174,  175,  175,  176,  176,  176,
231                 177,  177,  177,  178,  178,  178,  179,  179,
232                 179,  180,  180,  180,  181,  181,  182,  182,
233                 182,  183,  183,  183,  184,  184,  184,  185,
234                 185,  185,  186,  186,  186,  187,  187,  187,
235                 188,  188,  188,  189,  189,  189,  189,  190,
236                 190,  190,  191,  191,  191,  192,  192,  192,
237                 193,  193,  193,  194,  194,  194,  195,  195,
238                 195,  196,  196,  196,  196,  197,  197,  197,
239                 198,  198,  198,  199,  199,  199,  200,  200,
240                 200,  200,  201,  201,  201,  202,  202,  202,
241                 202,  203,  203,  203,  204,  204,  204,  205,
242                 205,  205,  205,  206,  206,  206,  207,  207,
243                 207,  207,  208,  208,  208,  209,  209,  209,
244                 209,  210,  210,  210,  211,  211,  211,  211,
245                 212,  212,  212,  213,  213,  213,  213,  214,
246                 214,  214,  214,  215,  215,  215,  216,  216,
247                 216,  216,  217,  217,  217,  217,  218,  218,
248                 218,  219,  219,  219,  219,  220,  220,  220,
249                 220,  221,  221,  221,  221,  222,  222,  222,
250                 223,  223,  223,  223,  224,  224,  224,  224,
251                 225,  225,  225,  225,  226,  226,  226,  226,
252                 227,  227,  227,  227,  228,  228,  228,  228,
253                 229,  229,  229,  229,  230,  230,  230,  230,
254                 231,  231,  231,  231,  232,  232,  232,  232,
255                 233,  233,  233,  233,  234,  234,  234,  234,
256                 235,  235,  235,  235,  236,  236,  236,  236,
257                 237,  237,  237,  237,  238,  238,  238,  238,
258                 239,  239,  239,  239,  240,  240,  240,  240,
259                 240,  241,  241,  241,  241,  242,  242,  242,
260                 242,  243,  243,  243,  243,  244,  244,  244,
261                 244,  244,  245,  245,  245,  245,  246,  246,
262                 246,  246,  247,  247,  247,  247,  247,  248,
263                 248,  248,  248,  249,  249,  249,  249,  249,
264                 250,  250,  250,  250,  251,  251,  251,  251,
265                 251,  252,  252,  252,  252,  253,  253,  253,
266                 253,  253,  254,  254,  254,  254,  255,  255,
267         },
268 };
269 #endif
270
271 void tegra_dc_clk_enable(struct tegra_dc *dc)
272 {
273         if (!tegra_is_clk_enabled(dc->clk)) {
274                 clk_prepare_enable(dc->clk);
275                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
276         }
277 }
278
279 void tegra_dc_clk_disable(struct tegra_dc *dc)
280 {
281         if (tegra_is_clk_enabled(dc->clk)) {
282                 clk_disable_unprepare(dc->clk);
283                 tegra_dvfs_set_rate(dc->clk, 0);
284         }
285 }
286
287 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
288 {
289         if (dc->out_ops->hold)
290                 dc->out_ops->hold(dc);
291 }
292
293 void tegra_dc_release_dc_out(struct tegra_dc *dc)
294 {
295         if (dc->out_ops->release)
296                 dc->out_ops->release(dc);
297 }
298
299 #define DUMP_REG(a) do {                        \
300         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
301                  #a, a, tegra_dc_readl(dc, a));               \
302         print(data, buff);                                    \
303         } while (0)
304
305 static void _dump_regs(struct tegra_dc *dc, void *data,
306                        void (* print)(void *data, const char *str))
307 {
308         int i;
309         char buff[256];
310
311         mutex_lock(&dc->lock);
312         tegra_dc_io_start(dc);
313         tegra_dc_hold_dc_out(dc);
314
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
316         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE);
318         DUMP_REG(DC_CMD_INT_STATUS);
319         DUMP_REG(DC_CMD_INT_MASK);
320         DUMP_REG(DC_CMD_INT_ENABLE);
321         DUMP_REG(DC_CMD_INT_TYPE);
322         DUMP_REG(DC_CMD_INT_POLARITY);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
326         DUMP_REG(DC_CMD_STATE_ACCESS);
327         DUMP_REG(DC_CMD_STATE_CONTROL);
328         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
329         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
330
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
332         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
333         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
335         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
336         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
337         DUMP_REG(DC_DISP_REF_TO_SYNC);
338         DUMP_REG(DC_DISP_SYNC_WIDTH);
339         DUMP_REG(DC_DISP_BACK_PORCH);
340         DUMP_REG(DC_DISP_DISP_ACTIVE);
341         DUMP_REG(DC_DISP_FRONT_PORCH);
342         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
346         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
347         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
351         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
352         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
356         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
357         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
360         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
361         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
364         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
365         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
368         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
369         DUMP_REG(DC_DISP_M0_CONTROL);
370         DUMP_REG(DC_DISP_M1_CONTROL);
371         DUMP_REG(DC_DISP_DI_CONTROL);
372         DUMP_REG(DC_DISP_PP_CONTROL);
373         DUMP_REG(DC_DISP_PP_SELECT_A);
374         DUMP_REG(DC_DISP_PP_SELECT_B);
375         DUMP_REG(DC_DISP_PP_SELECT_C);
376         DUMP_REG(DC_DISP_PP_SELECT_D);
377         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
378         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
379         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
380         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
381         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
382         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
383         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
384         DUMP_REG(DC_DISP_BORDER_COLOR);
385         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
386         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
388         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
389         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
390         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
392         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
393         DUMP_REG(DC_DISP_CURSOR_POSITION);
394         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
395         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
399         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
400         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
404 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
405         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
406 #endif
407         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
408         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
409
410
411         for (i = 0; i < 3; i++) {
412                 print(data, "\n");
413                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
414                 print(data, buff);
415
416                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
417                                 DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
419                 DUMP_REG(DC_WIN_WIN_OPTIONS);
420                 DUMP_REG(DC_WIN_BYTE_SWAP);
421                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
422                 DUMP_REG(DC_WIN_COLOR_DEPTH);
423                 DUMP_REG(DC_WIN_POSITION);
424                 DUMP_REG(DC_WIN_SIZE);
425                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
426                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
428                 DUMP_REG(DC_WIN_DDA_INCREMENT);
429                 DUMP_REG(DC_WIN_LINE_STRIDE);
430 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
431                 DUMP_REG(DC_WIN_BUF_STRIDE);
432                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
433 #endif
434                 DUMP_REG(DC_WIN_BLEND_NOKEY);
435                 DUMP_REG(DC_WIN_BLEND_1WIN);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
437                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
438                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
439                 DUMP_REG(DC_WINBUF_START_ADDR);
440                 DUMP_REG(DC_WINBUF_START_ADDR_U);
441                 DUMP_REG(DC_WINBUF_START_ADDR_V);
442                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
443                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
444                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
445                 DUMP_REG(DC_WIN_CSC_YOF);
446                 DUMP_REG(DC_WIN_CSC_KYRGB);
447                 DUMP_REG(DC_WIN_CSC_KUR);
448                 DUMP_REG(DC_WIN_CSC_KVR);
449                 DUMP_REG(DC_WIN_CSC_KUG);
450                 DUMP_REG(DC_WIN_CSC_KVG);
451                 DUMP_REG(DC_WIN_CSC_KUB);
452                 DUMP_REG(DC_WIN_CSC_KVB);
453         }
454
455         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
456         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
458         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
459         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
461         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
462         DUMP_REG(DC_DISP_M1_CONTROL);
463         DUMP_REG(DC_COM_PM1_CONTROL);
464         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
465         DUMP_REG(DC_DISP_SD_CONTROL);
466 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
467         DUMP_REG(DC_COM_CMU_CSC_KRR);
468         DUMP_REG(DC_COM_CMU_CSC_KGR);
469         DUMP_REG(DC_COM_CMU_CSC_KBR);
470         DUMP_REG(DC_COM_CMU_CSC_KRG);
471         DUMP_REG(DC_COM_CMU_CSC_KGG);
472         DUMP_REG(DC_COM_CMU_CSC_KBR);
473         DUMP_REG(DC_COM_CMU_CSC_KRB);
474         DUMP_REG(DC_COM_CMU_CSC_KGB);
475         DUMP_REG(DC_COM_CMU_CSC_KBB);
476 #endif
477
478         tegra_dc_release_dc_out(dc);
479         tegra_dc_io_end(dc);
480         mutex_unlock(&dc->lock);
481 }
482
483 #undef DUMP_REG
484
485 #ifdef DEBUG
486 static void dump_regs_print(void *data, const char *str)
487 {
488         struct tegra_dc *dc = data;
489         dev_dbg(&dc->ndev->dev, "%s", str);
490 }
491
492 static void dump_regs(struct tegra_dc *dc)
493 {
494         _dump_regs(dc, dc, dump_regs_print);
495 }
496 #else /* !DEBUG */
497
498 static void dump_regs(struct tegra_dc *dc) {}
499
500 #endif /* DEBUG */
501
502 #ifdef CONFIG_DEBUG_FS
503
504 static void dbg_regs_print(void *data, const char *str)
505 {
506         struct seq_file *s = data;
507
508         seq_printf(s, "%s", str);
509 }
510
511 #undef DUMP_REG
512
513 static int dbg_dc_show(struct seq_file *s, void *unused)
514 {
515         struct tegra_dc *dc = s->private;
516
517         _dump_regs(dc, s, dbg_regs_print);
518
519         return 0;
520 }
521
522
523 static int dbg_dc_open(struct inode *inode, struct file *file)
524 {
525         return single_open(file, dbg_dc_show, inode->i_private);
526 }
527
528 static const struct file_operations regs_fops = {
529         .open           = dbg_dc_open,
530         .read           = seq_read,
531         .llseek         = seq_lseek,
532         .release        = single_release,
533 };
534
535 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
536 {
537         struct tegra_dc *dc = s->private;
538         struct tegra_dc_mode *m;
539
540         mutex_lock(&dc->lock);
541         m = &dc->mode;
542         seq_printf(s,
543                 "pclk: %d\n"
544                 "h_ref_to_sync: %d\n"
545                 "v_ref_to_sync: %d\n"
546                 "h_sync_width: %d\n"
547                 "v_sync_width: %d\n"
548                 "h_back_porch: %d\n"
549                 "v_back_porch: %d\n"
550                 "h_active: %d\n"
551                 "v_active: %d\n"
552                 "h_front_porch: %d\n"
553                 "v_front_porch: %d\n"
554                 "stereo_mode: %d\n",
555                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
556                 m->h_sync_width, m->v_sync_width,
557                 m->h_back_porch, m->v_back_porch,
558                 m->h_active, m->v_active,
559                 m->h_front_porch, m->v_front_porch,
560                 m->stereo_mode);
561         mutex_unlock(&dc->lock);
562         return 0;
563 }
564
565 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
566 {
567         return single_open(file, dbg_dc_mode_show, inode->i_private);
568 }
569
570 static const struct file_operations mode_fops = {
571         .open           = dbg_dc_mode_open,
572         .read           = seq_read,
573         .llseek         = seq_lseek,
574         .release        = single_release,
575 };
576
577 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
578 {
579         struct tegra_dc *dc = s->private;
580
581         mutex_lock(&dc->lock);
582         seq_printf(s,
583                 "underflows: %llu\n"
584                 "underflows_a: %llu\n"
585                 "underflows_b: %llu\n"
586                 "underflows_c: %llu\n",
587                 dc->stats.underflows,
588                 dc->stats.underflows_a,
589                 dc->stats.underflows_b,
590                 dc->stats.underflows_c);
591         mutex_unlock(&dc->lock);
592
593         return 0;
594 }
595
596 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
597 {
598         return single_open(file, dbg_dc_stats_show, inode->i_private);
599 }
600
601 static const struct file_operations stats_fops = {
602         .open           = dbg_dc_stats_open,
603         .read           = seq_read,
604         .llseek         = seq_lseek,
605         .release        = single_release,
606 };
607
608 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
609 {
610         if (dc->debugdir)
611                 debugfs_remove_recursive(dc->debugdir);
612         dc->debugdir = NULL;
613 }
614
615 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
616 {
617         struct dentry *retval;
618
619         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
620         if (!dc->debugdir)
621                 goto remove_out;
622
623         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
624                 &regs_fops);
625         if (!retval)
626                 goto remove_out;
627
628         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
629                 &mode_fops);
630         if (!retval)
631                 goto remove_out;
632
633         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
634                 &stats_fops);
635         if (!retval)
636                 goto remove_out;
637
638         return;
639 remove_out:
640         dev_err(&dc->ndev->dev, "could not create debugfs\n");
641         tegra_dc_remove_debugfs(dc);
642 }
643
644 #else /* !CONFIG_DEBUGFS */
645 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
646 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
647 #endif /* CONFIG_DEBUGFS */
648
649 static int tegra_dc_set(struct tegra_dc *dc, int index)
650 {
651         int ret = 0;
652
653         mutex_lock(&tegra_dc_lock);
654         if (index >= TEGRA_MAX_DC) {
655                 ret = -EINVAL;
656                 goto out;
657         }
658
659         if (dc != NULL && tegra_dcs[index] != NULL) {
660                 ret = -EBUSY;
661                 goto out;
662         }
663
664         tegra_dcs[index] = dc;
665
666 out:
667         mutex_unlock(&tegra_dc_lock);
668
669         return ret;
670 }
671
672 unsigned int tegra_dc_has_multiple_dc(void)
673 {
674         unsigned int idx;
675         unsigned int cnt = 0;
676         struct tegra_dc *dc;
677
678         mutex_lock(&tegra_dc_lock);
679         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
680                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
681         mutex_unlock(&tegra_dc_lock);
682
683         return (cnt > 1);
684 }
685
686 /* get the stride size of a window.
687  * return: stride size in bytes for window win. or 0 if unavailble. */
688 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
689 {
690         u32 stride;
691
692         if (!dc->enabled)
693                 return 0;
694         BUG_ON(win > DC_N_WINDOWS);
695         mutex_lock(&dc->lock);
696         tegra_dc_io_start(dc);
697         tegra_dc_hold_dc_out(dc);
698         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
699                 DC_CMD_DISPLAY_WINDOW_HEADER);
700         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
701         tegra_dc_release_dc_out(dc);
702         tegra_dc_io_end(dc);
703         mutex_unlock(&dc->lock);
704         return GET_LINE_STRIDE(stride);
705 }
706 EXPORT_SYMBOL(tegra_dc_get_stride);
707
708 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
709 {
710         if (idx < TEGRA_MAX_DC)
711                 return tegra_dcs[idx];
712         else
713                 return NULL;
714 }
715 EXPORT_SYMBOL(tegra_dc_get_dc);
716
717 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
718 {
719         if (win >= dc->n_windows)
720                 return NULL;
721
722         return &dc->windows[win];
723 }
724 EXPORT_SYMBOL(tegra_dc_get_window);
725
726 bool tegra_dc_get_connected(struct tegra_dc *dc)
727 {
728         return dc->connected;
729 }
730 EXPORT_SYMBOL(tegra_dc_get_connected);
731
732 bool tegra_dc_hpd(struct tegra_dc *dc)
733 {
734         int sense;
735         int level;
736
737         level = gpio_get_value(dc->out->hotplug_gpio);
738
739         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
740
741         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
742                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
743 }
744 EXPORT_SYMBOL(tegra_dc_hpd);
745
746 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
747 {
748         unsigned i;
749         unsigned v0 = 128;
750         unsigned v1 = 0;
751
752         /* linear horizontal and vertical filters */
753         for (i = 0; i < 16; i++) {
754                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
755                                 DC_WIN_H_FILTER_P(i));
756
757                 tegra_dc_writel(dc, v0,
758                                 DC_WIN_V_FILTER_P(i));
759                 v0 -= 8;
760                 v1 += 8;
761         }
762 }
763
764 #ifdef CONFIG_TEGRA_DC_CMU
765 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
766                                         struct tegra_dc_cmu *src_cmu)
767 {
768         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
769 }
770
771 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
772 {
773         u32 val;
774         u32 i;
775
776         for (i = 0; i < 256; i++) {
777                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
778                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
779         }
780
781         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
782         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
783         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
784         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
785         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
786         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
787         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
788         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
789         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
790
791         for (i = 0; i < 960; i++) {
792                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
793                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
794         }
795 }
796
797 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
798 {
799         u32 val;
800         u32 i;
801         bool flags;
802
803         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
804         if (val & CMU_ENABLE)
805                 flags = true;
806
807         val &= ~CMU_ENABLE;
808         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
809         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
810         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
811
812         /*TODO: Sync up with frame end */
813         mdelay(20);
814
815         for (i = 0; i < 256; i++) {
816                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
817                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
818                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
819                 cmu->lut1[i] = LUT1_READ_DATA(val);
820         }
821
822         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
823         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
824         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
825         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
826         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
827         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
828         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
829         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
830         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
831
832         for (i = 0; i < 960; i++) {
833                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
834                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
835                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
836                 cmu->lut2[i] = LUT2_READ_DATA(val);
837         }
838 }
839 EXPORT_SYMBOL(tegra_dc_get_cmu);
840
841 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
842 {
843         u32 val;
844
845         if (dc->pdata->cmu_enable) {
846                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
847         } else {
848                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
849                 return 0;
850         }
851
852         if (cmu != &dc->cmu) {
853                 tegra_dc_cache_cmu(&dc->cmu, cmu);
854
855                 /* Disable CMU */
856                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
857                 if (val & CMU_ENABLE) {
858                         val &= ~CMU_ENABLE;
859                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
860                         val = GENERAL_UPDATE;
861                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
862                         val = GENERAL_ACT_REQ;
863                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
864                         /*TODO: Sync up with vsync */
865                         mdelay(20);
866                 }
867
868                 tegra_dc_set_cmu(dc, &dc->cmu);
869         }
870         tegra_dc_set_color_control(dc);
871
872         return 0;
873 }
874
875 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
876 {
877         int ret;
878
879         mutex_lock(&dc->lock);
880         tegra_dc_io_start(dc);
881         tegra_dc_hold_dc_out(dc);
882
883         ret = _tegra_dc_update_cmu(dc, cmu);
884
885         tegra_dc_release_dc_out(dc);
886         tegra_dc_io_end(dc);
887         mutex_unlock(&dc->lock);
888
889         return ret;
890 }
891 EXPORT_SYMBOL(tegra_dc_update_cmu);
892
893 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
894 {
895         tegra_dc_update_cmu(dc, &dc->cmu);
896 }
897 #else
898 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
899 #define tegra_dc_set_cmu(dc, cmu)
900 #define tegra_dc_update_cmu(dc, cmu)
901 #endif
902
903 /* disable_irq() blocks until handler completes, calling this function while
904  * holding dc->lock can deadlock. */
905 static inline void disable_dc_irq(const struct tegra_dc *dc)
906 {
907         disable_irq(dc->irq);
908 }
909
910 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
911 {
912         return dc->syncpt[i].id;
913 }
914 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
915
916 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
917 {
918         u32 max;
919
920         mutex_lock(&dc->lock);
921         tegra_dc_io_start(dc);
922         tegra_dc_hold_dc_out(dc);
923         max = nvhost_syncpt_incr_max_ext(dc->ndev,
924                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
925         dc->syncpt[i].max = max;
926         tegra_dc_release_dc_out(dc);
927         tegra_dc_io_end(dc);
928         mutex_unlock(&dc->lock);
929
930         return max;
931 }
932
933 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
934 {
935         mutex_lock(&dc->lock);
936         if (dc->enabled) {
937                 tegra_dc_io_start(dc);
938                 tegra_dc_hold_dc_out(dc);
939                 while (dc->syncpt[i].min < val) {
940                         dc->syncpt[i].min++;
941                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
942                 }
943                 tegra_dc_release_dc_out(dc);
944                 tegra_dc_io_end(dc);
945         }
946         mutex_unlock(&dc->lock);
947 }
948
949 void
950 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
951 {
952         unsigned int ctrl;
953         unsigned long out_sel;
954         unsigned long cmd_state;
955
956         mutex_lock(&dc->lock);
957         if (!dc->enabled) {
958                 mutex_unlock(&dc->lock);
959                 return;
960         }
961
962         tegra_dc_io_start(dc);
963         tegra_dc_hold_dc_out(dc);
964
965         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
966                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
967                 cfg->clk_select);
968
969         /* The new value should be effected immediately */
970         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
971         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
972
973         switch (cfg->which_pwm) {
974         case TEGRA_PWM_PM0:
975                 /* Select the LM0 on PM0 */
976                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
977                 out_sel &= ~(7 << 0);
978                 out_sel |= (3 << 0);
979                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
980                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
981                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
982                 break;
983         case TEGRA_PWM_PM1:
984                 /* Select the LM1 on PM1 */
985                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
986                 out_sel &= ~(7 << 4);
987                 out_sel |= (3 << 4);
988                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
989                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
990                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
991                 break;
992         default:
993                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
994                 break;
995         }
996         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
997         tegra_dc_release_dc_out(dc);
998         tegra_dc_io_end(dc);
999         mutex_unlock(&dc->lock);
1000 }
1001 EXPORT_SYMBOL(tegra_dc_config_pwm);
1002
1003 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1004                                 const struct tegra_dc_out_pin *pins,
1005                                 const unsigned int n_pins)
1006 {
1007         unsigned int i;
1008
1009         int name;
1010         int pol;
1011
1012         u32 pol1, pol3;
1013
1014         u32 set1, unset1;
1015         u32 set3, unset3;
1016
1017         set1 = set3 = unset1 = unset3 = 0;
1018
1019         for (i = 0; i < n_pins; i++) {
1020                 name = (pins + i)->name;
1021                 pol  = (pins + i)->pol;
1022
1023                 /* set polarity by name */
1024                 switch (name) {
1025                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1026                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1027                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1028                         else
1029                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1030                         break;
1031                 case TEGRA_DC_OUT_PIN_H_SYNC:
1032                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1033                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1034                         else
1035                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1036                         break;
1037                 case TEGRA_DC_OUT_PIN_V_SYNC:
1038                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1039                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1040                         else
1041                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1042                         break;
1043                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1044                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1045                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1046                         else
1047                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1048                         break;
1049                 default:
1050                         printk("Invalid argument in function %s\n",
1051                                __FUNCTION__);
1052                         break;
1053                 }
1054         }
1055
1056         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1057         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1058
1059         pol1 |= set1;
1060         pol1 &= ~unset1;
1061
1062         pol3 |= set3;
1063         pol3 &= ~unset3;
1064
1065         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1066         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1067 }
1068
1069 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1070 {
1071         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1072                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1073                 dc->out->type == TEGRA_DC_OUT_DSI)
1074                 return override_disp_mode[dc->out->type].pclk ?
1075                         &override_disp_mode[dc->out->type] : NULL;
1076         else
1077                 return NULL;
1078 }
1079
1080 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1081 {
1082         struct tegra_dc_mode *mode;
1083
1084         dc->out = out;
1085         mode = tegra_dc_get_override_mode(dc);
1086
1087         if (mode)
1088                 tegra_dc_set_mode(dc, mode);
1089         else if (out->n_modes > 0)
1090                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1091
1092         switch (out->type) {
1093         case TEGRA_DC_OUT_RGB:
1094                 dc->out_ops = &tegra_dc_rgb_ops;
1095                 break;
1096
1097         case TEGRA_DC_OUT_HDMI:
1098                 dc->out_ops = &tegra_dc_hdmi_ops;
1099                 break;
1100
1101         case TEGRA_DC_OUT_DSI:
1102                 dc->out_ops = &tegra_dc_dsi_ops;
1103                 break;
1104
1105         default:
1106                 dc->out_ops = NULL;
1107                 break;
1108         }
1109
1110 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1111         if (out->type == TEGRA_DC_OUT_HDMI)
1112                 dc->powergate_id = TEGRA_POWERGATE_DISB;
1113         else
1114                 dc->powergate_id = TEGRA_POWERGATE_DISA;
1115 #endif
1116
1117         if (dc->out_ops && dc->out_ops->init)
1118                 dc->out_ops->init(dc);
1119 }
1120
1121 /* returns on error: -EINVAL
1122  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1123 int tegra_dc_get_out(const struct tegra_dc *dc)
1124 {
1125         if (dc && dc->out)
1126                 return dc->out->type;
1127         return -EINVAL;
1128 }
1129
1130 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1131 {
1132         if (dc->out)
1133                 return dc->out->height;
1134         else
1135                 return 0;
1136 }
1137 EXPORT_SYMBOL(tegra_dc_get_out_height);
1138
1139 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1140 {
1141         if (dc->out)
1142                 return dc->out->width;
1143         else
1144                 return 0;
1145 }
1146 EXPORT_SYMBOL(tegra_dc_get_out_width);
1147
1148 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1149 {
1150         if (dc->out && dc->out->max_pixclock)
1151                 return dc->out->max_pixclock;
1152         else
1153                 return 0;
1154 }
1155 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1156
1157 void tegra_dc_enable_crc(struct tegra_dc *dc)
1158 {
1159         u32 val;
1160
1161         mutex_lock(&dc->lock);
1162         tegra_dc_io_start(dc);
1163         tegra_dc_hold_dc_out(dc);
1164
1165         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1166                 CRC_ENABLE_ENABLE;
1167         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1168         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1169         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1170         tegra_dc_release_dc_out(dc);
1171         tegra_dc_io_end(dc);
1172         mutex_unlock(&dc->lock);
1173 }
1174
1175 void tegra_dc_disable_crc(struct tegra_dc *dc)
1176 {
1177         mutex_lock(&dc->lock);
1178         tegra_dc_io_start(dc);
1179         tegra_dc_hold_dc_out(dc);
1180         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1181         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1182         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1183
1184         tegra_dc_release_dc_out(dc);
1185         tegra_dc_io_end(dc);
1186         mutex_unlock(&dc->lock);
1187 }
1188
1189 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1190 {
1191         int crc = 0;
1192
1193         if (!dc) {
1194                 pr_err("Failed to get dc: NULL parameter.\n");
1195                 goto crc_error;
1196         }
1197
1198 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1199         /* TODO: Replace mdelay with code to sync VBlANK, since
1200          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1201         mdelay(TEGRA_CRC_LATCHED_DELAY);
1202 #endif
1203
1204         mutex_lock(&dc->lock);
1205         tegra_dc_io_start(dc);
1206         tegra_dc_hold_dc_out(dc);
1207         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1208         tegra_dc_release_dc_out(dc);
1209         tegra_dc_io_end(dc);
1210         mutex_unlock(&dc->lock);
1211 crc_error:
1212         return crc;
1213 }
1214
1215 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1216 {
1217 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1218         u32 val;
1219
1220         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1221         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1222             return true;
1223 #endif
1224         return false;
1225 }
1226
1227 static inline void enable_dc_irq(const struct tegra_dc *dc)
1228 {
1229 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1230         enable_irq(dc->irq);
1231 #else
1232         /* Always disable DC interrupts on FPGA. */
1233         disable_irq(dc->irq);
1234 #endif
1235 }
1236
1237 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1238 {
1239         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1240                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1241 }
1242
1243 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1244 {
1245         int ret = -ENOTTY;
1246
1247         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1248                 return ret;
1249
1250         /*
1251          * Logic is as follows
1252          * a) Indicate we need a vblank.
1253          * b) Wait for completion to be signalled from isr.
1254          * c) Initialize completion for next iteration.
1255          */
1256
1257         tegra_dc_hold_dc_out(dc);
1258         dc->out->user_needs_vblank = true;
1259
1260         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1261         init_completion(&dc->out->user_vblank_comp);
1262         tegra_dc_release_dc_out(dc);
1263
1264         return ret;
1265 }
1266
1267 static void tegra_dc_vblank(struct work_struct *work)
1268 {
1269         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1270         bool nvsd_updated = false;
1271
1272         mutex_lock(&dc->lock);
1273
1274         if (!dc->enabled) {
1275                 mutex_unlock(&dc->lock);
1276                 return;
1277         }
1278
1279         tegra_dc_io_start(dc);
1280         tegra_dc_hold_dc_out(dc);
1281         /* use the new frame's bandwidth setting instead of max(current, new),
1282          * skip this if we're using tegra_dc_one_shot_worker() */
1283         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1284                 tegra_dc_program_bandwidth(dc, true);
1285
1286         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1287         if (!tegra_dc_windows_are_dirty(dc))
1288                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1289
1290         /* Update the SD brightness */
1291         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1292                 nvsd_updated = nvsd_update_brightness(dc);
1293                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1294                  * V_BLANK_NVSD bit of vblank ref-count. */
1295                 if (nvsd_updated) {
1296                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1297                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1298                 } else {
1299                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1300                 }
1301         }
1302
1303         /* Mask vblank interrupt if ref-count is zero. */
1304         if (!dc->vblank_ref_count)
1305                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1306
1307         tegra_dc_release_dc_out(dc);
1308         tegra_dc_io_end(dc);
1309         mutex_unlock(&dc->lock);
1310
1311         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1312                 dc->out->sd_settings->bl_device_name) {
1313                 char *bl_device_name =
1314                         dc->out->sd_settings->bl_device_name;
1315                 dc->out->sd_settings->bl_device =
1316                         get_backlight_device_by_name(bl_device_name);
1317         }
1318
1319         /* Do the actual brightness update outside of the mutex */
1320         if (nvsd_updated && dc->out->sd_settings &&
1321             dc->out->sd_settings->bl_device) {
1322
1323                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1324                 backlight_update_status(bl);
1325         }
1326 }
1327
1328 static void tegra_dc_one_shot_worker(struct work_struct *work)
1329 {
1330         struct tegra_dc *dc = container_of(
1331                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1332         mutex_lock(&dc->lock);
1333
1334         /* memory client has gone idle */
1335         tegra_dc_clear_bandwidth(dc);
1336
1337         if (dc->out_ops->idle) {
1338                 tegra_dc_io_start(dc);
1339                 dc->out_ops->idle(dc);
1340                 tegra_dc_io_end(dc);
1341         }
1342
1343         mutex_unlock(&dc->lock);
1344 }
1345
1346 /* return an arbitrarily large number if count overflow occurs.
1347  * make it a nice base-10 number to show up in stats output */
1348 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1349 {
1350         unsigned count = tegra_dc_readl(dc, reg);
1351
1352         tegra_dc_writel(dc, 0, reg);
1353         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1354 }
1355
1356 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1357 {
1358         int i;
1359
1360         dc->stats.underflows++;
1361         if (dc->underflow_mask & WIN_A_UF_INT)
1362                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1363                         DC_WINBUF_AD_UFLOW_STATUS);
1364         if (dc->underflow_mask & WIN_B_UF_INT)
1365                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1366                         DC_WINBUF_BD_UFLOW_STATUS);
1367         if (dc->underflow_mask & WIN_C_UF_INT)
1368                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1369                         DC_WINBUF_CD_UFLOW_STATUS);
1370
1371         /* Check for any underflow reset conditions */
1372         for (i = 0; i < DC_N_WINDOWS; i++) {
1373                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1374                         dc->windows[i].underflows++;
1375
1376 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1377                         if (dc->windows[i].underflows > 4) {
1378                                 schedule_work(&dc->reset_work);
1379                                 /* reset counter */
1380                                 dc->windows[i].underflows = 0;
1381                                 trace_display_reset(dc);
1382                         }
1383 #endif
1384 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1385                         if (dc->windows[i].underflows > 4) {
1386                                 trace_display_reset(dc);
1387                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1388                                                 DC_DISP_DISP_MISC_CONTROL);
1389                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1390                                                 DC_CMD_STATE_CONTROL);
1391                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1392                                                 DC_CMD_STATE_CONTROL);
1393
1394                                 tegra_dc_writel(dc, 0,
1395                                                 DC_DISP_DISP_MISC_CONTROL);
1396                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1397                                                 DC_CMD_STATE_CONTROL);
1398                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1399                                                 DC_CMD_STATE_CONTROL);
1400                         }
1401 #endif
1402                 } else {
1403                         dc->windows[i].underflows = 0;
1404                 }
1405         }
1406
1407         /* Clear the underflow mask now that we've checked it. */
1408         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1409         dc->underflow_mask = 0;
1410         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1411         trace_underflow(dc);
1412 }
1413
1414 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1415 static void tegra_dc_vpulse2_locked(struct tegra_dc *dc)
1416 {
1417         bool nvsd_updated = false;
1418
1419         if (!dc->enabled)
1420                 return;
1421
1422         /* Clear the V_PULSE2_FLIP if no update */
1423         if (!tegra_dc_windows_are_dirty(dc))
1424                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1425
1426         /* Update the SD brightness */
1427         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1428                 nvsd_updated = nvsd_update_brightness(dc);
1429                 if (nvsd_updated) {
1430                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1431                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1432                 } else {
1433                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1434                 }
1435         }
1436
1437         /* Mask vpulse2 interrupt if ref-count is zero. */
1438         if (!dc->vpulse2_ref_count)
1439                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1440 }
1441 #endif
1442
1443 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1444 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1445 {
1446         /* pending user vblank, so wakeup */
1447         if ((status & (V_BLANK_INT | MSF_INT)) &&
1448             (dc->out->user_needs_vblank)) {
1449                 dc->out->user_needs_vblank = false;
1450                 complete(&dc->out->user_vblank_comp);
1451         }
1452
1453         if (status & V_BLANK_INT) {
1454                 /* Sync up windows. */
1455                 tegra_dc_trigger_windows(dc);
1456
1457                 /* Schedule any additional bottom-half vblank actvities. */
1458                 queue_work(system_freezable_wq, &dc->vblank_work);
1459         }
1460
1461         if (status & FRAME_END_INT) {
1462                 /* Mark the frame_end as complete. */
1463                 if (!completion_done(&dc->frame_end_complete))
1464                         complete(&dc->frame_end_complete);
1465         }
1466
1467 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1468         if (status & V_PULSE2_INT)
1469                 tegra_dc_vpulse2_locked(dc);
1470 #endif
1471 }
1472
1473 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1474 {
1475         /* Schedule any additional bottom-half vblank actvities. */
1476         if (status & V_BLANK_INT)
1477                 queue_work(system_freezable_wq, &dc->vblank_work);
1478
1479         if (status & FRAME_END_INT) {
1480                 struct timespec tm = CURRENT_TIME;
1481                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1482                 wake_up(&dc->timestamp_wq);
1483
1484                 /* Mark the frame_end as complete. */
1485                 if (!completion_done(&dc->frame_end_complete))
1486                         complete(&dc->frame_end_complete);
1487
1488                 tegra_dc_trigger_windows(dc);
1489         }
1490
1491 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1492         if (status & V_PULSE2_INT)
1493                 tegra_dc_vpulse2_locked(dc);
1494 #endif
1495 }
1496
1497 /* XXX: Not sure if we limit look ahead to 1 frame */
1498 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1499 {
1500         BUG_ON(!dc->frametime_ns);
1501         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1502 }
1503
1504 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1505 {
1506         BUG_ON(!dc->frametime_ns);
1507         return (((new_ts - old_ts) > dc->frametime_ns)
1508                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1509                         != div_s64((old_ts - dc->frame_end_timestamp),
1510                                 dc->frametime_ns)));
1511 }
1512 #endif
1513
1514 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1515 {
1516 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1517         struct tegra_dc *dc = ptr;
1518         unsigned long status;
1519         unsigned long underflow_mask;
1520         u32 val;
1521
1522         mutex_lock(&dc->lock);
1523         if (!dc->enabled) {
1524                 mutex_unlock(&dc->lock);
1525                 return IRQ_HANDLED;
1526         }
1527
1528         clk_enable(dc->clk);
1529         tegra_dc_io_start(dc);
1530         tegra_dc_hold_dc_out(dc);
1531
1532         if (!nvhost_module_powered_ext(dc->ndev)) {
1533                 WARN(1, "IRQ when DC not powered!\n");
1534                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1535                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1536                 tegra_dc_release_dc_out(dc);
1537                 tegra_dc_io_end(dc);
1538                 clk_disable(dc->clk);
1539                 mutex_unlock(&dc->lock);
1540                 return IRQ_HANDLED;
1541         }
1542
1543         /* clear all status flags except underflow, save those for the worker */
1544         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1545         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1546         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1547         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1548
1549         /*
1550          * Overlays can get thier internal state corrupted during and underflow
1551          * condition.  The only way to fix this state is to reset the DC.
1552          * if we get 4 consecutive frames with underflows, assume we're
1553          * hosed and reset.
1554          */
1555         underflow_mask = status & ALL_UF_INT;
1556
1557         /* Check underflow */
1558         if (underflow_mask) {
1559                 dc->underflow_mask |= underflow_mask;
1560                 schedule_delayed_work(&dc->underflow_work,
1561                         msecs_to_jiffies(1));
1562         }
1563
1564         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1565                 tegra_dc_one_shot_irq(dc, status);
1566         else
1567                 tegra_dc_continuous_irq(dc, status);
1568
1569         tegra_dc_release_dc_out(dc);
1570         tegra_dc_io_end(dc);
1571         clk_disable(dc->clk);
1572         mutex_unlock(&dc->lock);
1573
1574         return IRQ_HANDLED;
1575 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1576         return IRQ_NONE;
1577 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1578 }
1579
1580 void tegra_dc_set_color_control(struct tegra_dc *dc)
1581 {
1582         u32 color_control;
1583
1584         switch (dc->out->depth) {
1585         case 3:
1586                 color_control = BASE_COLOR_SIZE111;
1587                 break;
1588
1589         case 6:
1590                 color_control = BASE_COLOR_SIZE222;
1591                 break;
1592
1593         case 8:
1594                 color_control = BASE_COLOR_SIZE332;
1595                 break;
1596
1597         case 9:
1598                 color_control = BASE_COLOR_SIZE333;
1599                 break;
1600
1601         case 12:
1602                 color_control = BASE_COLOR_SIZE444;
1603                 break;
1604
1605         case 15:
1606                 color_control = BASE_COLOR_SIZE555;
1607                 break;
1608
1609         case 16:
1610                 color_control = BASE_COLOR_SIZE565;
1611                 break;
1612
1613         case 18:
1614                 color_control = BASE_COLOR_SIZE666;
1615                 break;
1616
1617         default:
1618                 color_control = BASE_COLOR_SIZE888;
1619                 break;
1620         }
1621
1622         switch (dc->out->dither) {
1623         case TEGRA_DC_DISABLE_DITHER:
1624                 color_control |= DITHER_CONTROL_DISABLE;
1625                 break;
1626         case TEGRA_DC_ORDERED_DITHER:
1627                 color_control |= DITHER_CONTROL_ORDERED;
1628                 break;
1629         case TEGRA_DC_ERRDIFF_DITHER:
1630                 /* The line buffer for error-diffusion dither is limited
1631                  * to 1280 pixels per line. This limits the maximum
1632                  * horizontal active area size to 1280 pixels when error
1633                  * diffusion is enabled.
1634                  */
1635                 BUG_ON(dc->mode.h_active > 1280);
1636                 color_control |= DITHER_CONTROL_ERRDIFF;
1637                 break;
1638         }
1639
1640 #ifdef CONFIG_TEGRA_DC_CMU
1641         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1642                 color_control |= CMU_ENABLE;
1643 #endif
1644
1645         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1646 }
1647
1648 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1649 {
1650         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1651                 return dc->win_syncpt[idx];
1652         BUG();
1653 }
1654
1655 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1656 {
1657 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
1658         u32 start, end;
1659         unsigned long val;
1660
1661         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1662         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1663
1664         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1665                 dc->mode.v_back_porch + dc->mode.v_active;
1666         end = start + 1;
1667         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1668         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1669
1670         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1671         val |= V_PULSE2_INT;
1672         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1673
1674         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1675         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1676 #endif
1677 }
1678
1679 static int tegra_dc_init(struct tegra_dc *dc)
1680 {
1681         int i;
1682         int int_enable;
1683
1684         tegra_dc_io_start(dc);
1685         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1686         if (dc->ndev->id == 0) {
1687                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1688                                       TEGRA_MC_PRIO_MED);
1689                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1690                                       TEGRA_MC_PRIO_MED);
1691                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1692                                       TEGRA_MC_PRIO_MED);
1693 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1694                 /* only present on Tegra2 and 3 */
1695                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1696                                       TEGRA_MC_PRIO_MED);
1697 #endif
1698                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1699                                       TEGRA_MC_PRIO_HIGH);
1700         } else if (dc->ndev->id == 1) {
1701                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1702                                       TEGRA_MC_PRIO_MED);
1703                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1704                                       TEGRA_MC_PRIO_MED);
1705                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1706                                       TEGRA_MC_PRIO_MED);
1707 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1708                 /* only present on Tegra2 and 3 */
1709                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1710                                       TEGRA_MC_PRIO_MED);
1711 #endif
1712                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1713                                       TEGRA_MC_PRIO_HIGH);
1714         }
1715         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1716                         DC_CMD_CONT_SYNCPT_VSYNC);
1717
1718         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1719         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1720         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1721         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1722 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1723         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1724 #endif
1725         /* enable interrupts for vblank, frame_end and underflows */
1726         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1727         /* for panels with one-shot mode enable tearing effect interrupt */
1728         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1729                 int_enable |= MSF_INT;
1730
1731         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1732         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1733         tegra_dc_init_vpulse2_int(dc);
1734
1735         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1736
1737 #ifdef CONFIG_TEGRA_DC_CMU
1738         if (dc->pdata->cmu)
1739                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1740         else
1741                 _tegra_dc_update_cmu(dc, &default_cmu);
1742 #endif
1743         tegra_dc_set_color_control(dc);
1744         for (i = 0; i < DC_N_WINDOWS; i++) {
1745                 struct tegra_dc_win *win = &dc->windows[i];
1746                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1747                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1748                 tegra_dc_set_csc(dc, &win->csc);
1749                 tegra_dc_set_lut(dc, win);
1750                 tegra_dc_set_scaling_filter(dc);
1751         }
1752
1753         for (i = 0; i < dc->n_windows; i++) {
1754                 u32 syncpt = get_syncpt(dc, i);
1755
1756                 dc->syncpt[i].id = syncpt;
1757
1758                 dc->syncpt[i].min = dc->syncpt[i].max =
1759                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1760         }
1761
1762         trace_display_mode(dc, &dc->mode);
1763
1764         if (dc->mode.pclk) {
1765                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1766                         tegra_dc_io_end(dc);
1767                         return -EINVAL;
1768                 }
1769         }
1770
1771         /* Initialize SD AFTER the modeset.
1772            nvsd_init handles the sd_settings = NULL case. */
1773         nvsd_init(dc, dc->out->sd_settings);
1774
1775         tegra_dc_io_end(dc);
1776
1777         return 0;
1778 }
1779
1780 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1781 {
1782         int failed_init = 0;
1783
1784         tegra_dc_unpowergate_locked(dc);
1785
1786         if (dc->out->enable)
1787                 dc->out->enable(&dc->ndev->dev);
1788
1789         tegra_dc_setup_clk(dc, dc->clk);
1790         tegra_dc_clk_enable(dc);
1791         tegra_dc_io_start(dc);
1792
1793         tegra_dc_power_on(dc);
1794
1795         /* do not accept interrupts during initialization */
1796         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1797
1798         enable_dc_irq(dc);
1799
1800         failed_init = tegra_dc_init(dc);
1801         if (failed_init) {
1802                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1803                 disable_irq_nosync(dc->irq);
1804                 tegra_dc_clear_bandwidth(dc);
1805                 tegra_dc_clk_disable(dc);
1806                 if (dc->out && dc->out->disable)
1807                         dc->out->disable();
1808                 tegra_dc_io_end(dc);
1809                 return false;
1810         }
1811
1812         if (dc->out_ops && dc->out_ops->enable)
1813                 dc->out_ops->enable(dc);
1814
1815         /* force a full blending update */
1816         dc->blend.z[0] = -1;
1817
1818         tegra_dc_ext_enable(dc->ext);
1819
1820         trace_display_enable(dc);
1821
1822         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1823         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1824
1825         if (dc->out->postpoweron)
1826                 dc->out->postpoweron();
1827
1828         tegra_dc_io_end(dc);
1829         return true;
1830 }
1831
1832 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1833 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1834 {
1835         bool ret = true;
1836
1837         if (dc->out->enable)
1838                 dc->out->enable(&dc->ndev->dev);
1839
1840         tegra_dc_setup_clk(dc, dc->clk);
1841         tegra_dc_clk_enable(dc);
1842
1843         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1844                 mutex_lock(&tegra_dcs[1]->lock);
1845                 disable_irq_nosync(tegra_dcs[1]->irq);
1846         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1847                 mutex_lock(&tegra_dcs[0]->lock);
1848                 disable_irq_nosync(tegra_dcs[0]->irq);
1849         }
1850
1851         msleep(5);
1852         tegra_periph_reset_assert(dc->clk);
1853         msleep(2);
1854 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1855         tegra_periph_reset_deassert(dc->clk);
1856         msleep(1);
1857 #endif
1858
1859         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1860                 enable_dc_irq(tegra_dcs[1]);
1861                 mutex_unlock(&tegra_dcs[1]->lock);
1862         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1863                 enable_dc_irq(tegra_dcs[0]);
1864                 mutex_unlock(&tegra_dcs[0]->lock);
1865         }
1866
1867         enable_dc_irq(dc);
1868
1869         if (tegra_dc_init(dc)) {
1870                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1871                 ret = false;
1872         }
1873
1874         if (dc->out_ops && dc->out_ops->enable)
1875                 dc->out_ops->enable(dc);
1876
1877         if (dc->out->postpoweron)
1878                 dc->out->postpoweron();
1879
1880         /* force a full blending update */
1881         dc->blend.z[0] = -1;
1882
1883         tegra_dc_ext_enable(dc->ext);
1884
1885         if (!ret) {
1886                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1887                 _tegra_dc_controller_disable(dc);
1888         }
1889
1890         trace_display_reset(dc);
1891         return ret;
1892 }
1893 #endif
1894
1895 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1896 {
1897         if (dc->mode.pclk == 0) {
1898                 switch (dc->out->type) {
1899                 case TEGRA_DC_OUT_HDMI:
1900                 /* DC enable called but no videomode is loaded.
1901                      Check if HDMI is connected, then set fallback mdoe */
1902                 if (tegra_dc_hpd(dc)) {
1903                         return tegra_dc_set_fb_mode(dc,
1904                                         &tegra_dc_hdmi_fallback_mode, 0);
1905                 } else
1906                         return false;
1907
1908                 break;
1909
1910                 /* Do nothing for other outputs for now */
1911                 case TEGRA_DC_OUT_RGB:
1912
1913                 case TEGRA_DC_OUT_DSI:
1914
1915                 default:
1916                         return false;
1917                 }
1918         }
1919
1920         return false;
1921 }
1922
1923 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1924 {
1925         return _tegra_dc_set_default_videomode(dc);
1926 }
1927
1928 static bool _tegra_dc_enable(struct tegra_dc *dc)
1929 {
1930         if (dc->mode.pclk == 0)
1931                 return false;
1932
1933         if (!dc->out)
1934                 return false;
1935
1936         if (dc->enabled)
1937                 return true;
1938
1939         if (!_tegra_dc_controller_enable(dc))
1940                 return false;
1941
1942         return true;
1943 }
1944
1945 void tegra_dc_enable(struct tegra_dc *dc)
1946 {
1947         mutex_lock(&dc->lock);
1948
1949         if (!dc->enabled)
1950                 dc->enabled = _tegra_dc_enable(dc);
1951
1952         mutex_unlock(&dc->lock);
1953         trace_display_mode(dc, &dc->mode);
1954 }
1955
1956 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1957 {
1958         unsigned i;
1959
1960         tegra_dc_hold_dc_out(dc);
1961
1962         if (dc->out && dc->out->prepoweroff)
1963                 dc->out->prepoweroff();
1964
1965         if (dc->out_ops && dc->out_ops->disable)
1966                 dc->out_ops->disable(dc);
1967
1968         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1969
1970         disable_irq_nosync(dc->irq);
1971
1972         tegra_dc_clear_bandwidth(dc);
1973         if (dc->out_ops->release) /* ugly hack */
1974                 tegra_dc_release_dc_out(dc);
1975         else
1976                 tegra_dc_clk_disable(dc);
1977
1978         if (dc->out && dc->out->disable)
1979                 dc->out->disable();
1980
1981         for (i = 0; i < dc->n_windows; i++) {
1982                 struct tegra_dc_win *w = &dc->windows[i];
1983
1984                 /* reset window bandwidth */
1985                 w->bandwidth = 0;
1986                 w->new_bandwidth = 0;
1987
1988                 /* disable windows */
1989                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1990
1991                 /* flush any pending syncpt waits */
1992                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1993                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1994                                 dc->syncpt[i].min, dc->syncpt[i].max);
1995                         dc->syncpt[i].min++;
1996                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1997                 }
1998         }
1999         trace_display_disable(dc);
2000 }
2001
2002 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2003 {
2004 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2005         u32 val;
2006         if (dc->enabled)  {
2007                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2008                 if (enable)
2009                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2010                 else
2011                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2012                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2013         }
2014 #endif
2015 }
2016
2017 bool tegra_dc_stats_get(struct tegra_dc *dc)
2018 {
2019 #if 0 /* right now it is always enabled */
2020         u32 val;
2021         bool res;
2022
2023         if (dc->enabled)  {
2024                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2025                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2026         } else {
2027                 res = false;
2028         }
2029
2030         return res;
2031 #endif
2032         return true;
2033 }
2034
2035 /* make the screen blank by disabling all windows */
2036 void tegra_dc_blank(struct tegra_dc *dc)
2037 {
2038         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2039         unsigned i;
2040
2041         for (i = 0; i < DC_N_WINDOWS; i++) {
2042                 dcwins[i] = tegra_dc_get_window(dc, i);
2043                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2044         }
2045
2046         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2047         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2048 }
2049
2050 static void _tegra_dc_disable(struct tegra_dc *dc)
2051 {
2052         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2053                 mutex_lock(&dc->one_shot_lock);
2054                 cancel_delayed_work_sync(&dc->one_shot_work);
2055         }
2056
2057         tegra_dc_io_start(dc);
2058         _tegra_dc_controller_disable(dc);
2059         tegra_dc_io_end(dc);
2060
2061         tegra_dc_powergate_locked(dc);
2062
2063         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2064                 mutex_unlock(&dc->one_shot_lock);
2065 }
2066
2067 void tegra_dc_disable(struct tegra_dc *dc)
2068 {
2069         tegra_dc_ext_disable(dc->ext);
2070
2071         /* it's important that new underflow work isn't scheduled before the
2072          * lock is acquired. */
2073         cancel_delayed_work_sync(&dc->underflow_work);
2074
2075         mutex_lock(&dc->lock);
2076
2077         if (dc->enabled) {
2078                 dc->enabled = false;
2079
2080                 if (!dc->suspended)
2081                         _tegra_dc_disable(dc);
2082         }
2083
2084 #ifdef CONFIG_SWITCH
2085         switch_set_state(&dc->modeset_switch, 0);
2086 #endif
2087
2088         mutex_unlock(&dc->lock);
2089         synchronize_irq(dc->irq);
2090         trace_display_mode(dc, &dc->mode);
2091 }
2092
2093 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2094 static void tegra_dc_reset_worker(struct work_struct *work)
2095 {
2096         struct tegra_dc *dc =
2097                 container_of(work, struct tegra_dc, reset_work);
2098
2099         unsigned long val = 0;
2100
2101         mutex_lock(&shared_lock);
2102
2103         dev_warn(&dc->ndev->dev,
2104                 "overlay stuck in underflow state.  resetting.\n");
2105
2106         tegra_dc_ext_disable(dc->ext);
2107
2108         mutex_lock(&dc->lock);
2109
2110         if (dc->enabled == false)
2111                 goto unlock;
2112
2113         dc->enabled = false;
2114
2115         /*
2116          * off host read bus
2117          */
2118         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2119         val &= ~(0x00000100);
2120         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2121
2122         /*
2123          * set DC to STOP mode
2124          */
2125         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2126
2127         msleep(10);
2128
2129         _tegra_dc_controller_disable(dc);
2130
2131         /* _tegra_dc_controller_reset_enable deasserts reset */
2132         _tegra_dc_controller_reset_enable(dc);
2133
2134         dc->enabled = true;
2135
2136         /* reopen host read bus */
2137         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2138         val &= ~(0x00000100);
2139         val |= 0x100;
2140         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2141
2142 unlock:
2143         mutex_unlock(&dc->lock);
2144         mutex_unlock(&shared_lock);
2145         trace_display_reset(dc);
2146 }
2147 #endif
2148
2149 static void tegra_dc_underflow_worker(struct work_struct *work)
2150 {
2151         struct tegra_dc *dc = container_of(
2152                 to_delayed_work(work), struct tegra_dc, underflow_work);
2153
2154         mutex_lock(&dc->lock);
2155         tegra_dc_io_start(dc);
2156         tegra_dc_hold_dc_out(dc);
2157
2158         if (dc->enabled) {
2159                 tegra_dc_underflow_handler(dc);
2160         }
2161         tegra_dc_release_dc_out(dc);
2162         tegra_dc_io_end(dc);
2163         mutex_unlock(&dc->lock);
2164 }
2165
2166 #ifdef CONFIG_SWITCH
2167 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2168 {
2169         struct tegra_dc *dc =
2170                 container_of(sdev, struct tegra_dc, modeset_switch);
2171
2172         if (!sdev->state)
2173                 return sprintf(buf, "offline\n");
2174
2175         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2176 }
2177 #endif
2178
2179 static int tegra_dc_probe(struct platform_device *ndev)
2180 {
2181         struct tegra_dc *dc;
2182         struct tegra_dc_mode *mode;
2183         struct clk *clk;
2184         struct clk *emc_clk;
2185         struct resource *res;
2186         struct resource *base_res;
2187         struct resource *fb_mem = NULL;
2188         int ret = 0;
2189         void __iomem *base;
2190         int irq;
2191         int i;
2192
2193         if (!ndev->dev.platform_data) {
2194                 dev_err(&ndev->dev, "no platform data\n");
2195                 return -ENOENT;
2196         }
2197
2198         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2199         if (!dc) {
2200                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2201                 return -ENOMEM;
2202         }
2203
2204         irq = platform_get_irq_byname(ndev, "irq");
2205         if (irq <= 0) {
2206                 dev_err(&ndev->dev, "no irq\n");
2207                 ret = -ENOENT;
2208                 goto err_free;
2209         }
2210
2211         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2212         if (!res) {
2213                 dev_err(&ndev->dev, "no mem resource\n");
2214                 ret = -ENOENT;
2215                 goto err_free;
2216         }
2217
2218         base_res = request_mem_region(res->start, resource_size(res),
2219                 ndev->name);
2220         if (!base_res) {
2221                 dev_err(&ndev->dev, "request_mem_region failed\n");
2222                 ret = -EBUSY;
2223                 goto err_free;
2224         }
2225
2226         base = ioremap(res->start, resource_size(res));
2227         if (!base) {
2228                 dev_err(&ndev->dev, "registers can't be mapped\n");
2229                 ret = -EBUSY;
2230                 goto err_release_resource_reg;
2231         }
2232         if (TEGRA_DISPLAY_BASE == res->start) {
2233                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2234                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2235                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2236                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2237         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2238                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2239                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2240                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2241                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2242         } else {
2243                 dev_err(&ndev->dev,
2244                         "Unknown base address %#08x: unable to assign syncpt\n",
2245                         res->start);
2246         }
2247
2248
2249         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2250
2251         clk = clk_get(&ndev->dev, NULL);
2252         if (IS_ERR_OR_NULL(clk)) {
2253                 dev_err(&ndev->dev, "can't get clock\n");
2254                 ret = -ENOENT;
2255                 goto err_iounmap_reg;
2256         }
2257
2258         emc_clk = clk_get(&ndev->dev, "emc");
2259         if (IS_ERR_OR_NULL(emc_clk)) {
2260                 dev_err(&ndev->dev, "can't get emc clock\n");
2261                 ret = -ENOENT;
2262                 goto err_put_clk;
2263         }
2264
2265         dc->clk = clk;
2266         dc->emc_clk = emc_clk;
2267         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2268         /* Initialize one shot work delay, it will be assigned by dsi
2269          * according to refresh rate later. */
2270         dc->one_shot_delay_ms = 40;
2271
2272         dc->base_res = base_res;
2273         dc->base = base;
2274         dc->irq = irq;
2275         dc->ndev = ndev;
2276         dc->pdata = ndev->dev.platform_data;
2277
2278         /*
2279          * The emc is a shared clock, it will be set based on
2280          * the requirements for each user on the bus.
2281          */
2282         dc->emc_clk_rate = 0;
2283
2284         mutex_init(&dc->lock);
2285         mutex_init(&dc->one_shot_lock);
2286         init_completion(&dc->frame_end_complete);
2287         init_waitqueue_head(&dc->wq);
2288         init_waitqueue_head(&dc->timestamp_wq);
2289 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2290         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2291 #endif
2292         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2293         dc->vblank_ref_count = 0;
2294         dc->vpulse2_ref_count = 0;
2295         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2296         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2297
2298         tegra_dc_init_lut_defaults(&dc->fb_lut);
2299
2300         dc->n_windows = DC_N_WINDOWS;
2301         for (i = 0; i < dc->n_windows; i++) {
2302                 struct tegra_dc_win *win = &dc->windows[i];
2303                 win->idx = i;
2304                 win->dc = dc;
2305                 tegra_dc_init_csc_defaults(&win->csc);
2306                 tegra_dc_init_lut_defaults(&win->lut);
2307         }
2308
2309         ret = tegra_dc_set(dc, ndev->id);
2310         if (ret < 0) {
2311                 dev_err(&ndev->dev, "can't add dc\n");
2312                 goto err_free_irq;
2313         }
2314
2315         platform_set_drvdata(ndev, dc);
2316
2317 #ifdef CONFIG_SWITCH
2318         dc->modeset_switch.name = dev_name(&ndev->dev);
2319         dc->modeset_switch.state = 0;
2320         dc->modeset_switch.print_state = switch_modeset_print_mode;
2321         ret = switch_dev_register(&dc->modeset_switch);
2322         if (ret < 0)
2323                 dev_err(&ndev->dev, "failed to register switch driver\n");
2324 #endif
2325
2326         tegra_dc_feature_register(dc);
2327
2328         if (dc->pdata->default_out)
2329                 tegra_dc_set_out(dc, dc->pdata->default_out);
2330         else
2331                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2332
2333         dc->ext = tegra_dc_ext_register(ndev, dc);
2334         if (IS_ERR_OR_NULL(dc->ext)) {
2335                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2336                 dc->ext = NULL;
2337         }
2338
2339         /* interrupt handler must be registered before tegra_fb_register() */
2340         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2341                         dev_name(&ndev->dev), dc)) {
2342                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2343                 ret = -EBUSY;
2344                 goto err_put_emc_clk;
2345         }
2346         disable_dc_irq(dc);
2347
2348         mutex_lock(&dc->lock);
2349         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2350                 _tegra_dc_set_default_videomode(dc);
2351                 dc->enabled = _tegra_dc_enable(dc);
2352         }
2353         mutex_unlock(&dc->lock);
2354
2355         tegra_dc_create_debugfs(dc);
2356
2357         dev_info(&ndev->dev, "probed\n");
2358
2359         if (dc->pdata->fb) {
2360                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2361                         unsigned long fmt;
2362                         tegra_dc_writel(dc,
2363                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2364                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2365
2366                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2367                         dc->pdata->fb->bits_per_pixel =
2368                                 tegra_dc_fmt_bpp(fmt);
2369                 }
2370
2371                 mode = tegra_dc_get_override_mode(dc);
2372                 if (mode) {
2373                         dc->pdata->fb->xres = mode->h_active;
2374                         dc->pdata->fb->yres = mode->v_active;
2375                 }
2376
2377                 tegra_dc_io_start(dc);
2378                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2379                 if (IS_ERR_OR_NULL(dc->fb))
2380                         dc->fb = NULL;
2381                 tegra_dc_io_end(dc);
2382         }
2383
2384         if (dc->out && dc->out->hotplug_init)
2385                 dc->out->hotplug_init(&ndev->dev);
2386
2387         if (dc->out_ops && dc->out_ops->detect)
2388                 dc->out_ops->detect(dc);
2389         else
2390                 dc->connected = true;
2391
2392 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2393         /* Powergate display module when it's unconnected. */
2394         if (!tegra_dc_get_connected(dc))
2395                 tegra_dc_powergate_locked(dc);
2396 #endif
2397
2398         tegra_dc_create_sysfs(&dc->ndev->dev);
2399
2400         return 0;
2401
2402 err_free_irq:
2403         free_irq(irq, dc);
2404 err_put_emc_clk:
2405         clk_put(emc_clk);
2406 err_put_clk:
2407         clk_put(clk);
2408 err_iounmap_reg:
2409         iounmap(base);
2410         if (fb_mem)
2411                 release_resource(fb_mem);
2412 err_release_resource_reg:
2413         release_resource(base_res);
2414 err_free:
2415         kfree(dc);
2416
2417         return ret;
2418 }
2419
2420 static int tegra_dc_remove(struct platform_device *ndev)
2421 {
2422         struct tegra_dc *dc = platform_get_drvdata(ndev);
2423
2424         tegra_dc_remove_sysfs(&dc->ndev->dev);
2425         tegra_dc_remove_debugfs(dc);
2426
2427         if (dc->fb) {
2428                 tegra_fb_unregister(dc->fb);
2429                 if (dc->fb_mem)
2430                         release_resource(dc->fb_mem);
2431         }
2432
2433         tegra_dc_ext_disable(dc->ext);
2434
2435         if (dc->ext)
2436                 tegra_dc_ext_unregister(dc->ext);
2437
2438         mutex_lock(&dc->lock);
2439         if (dc->enabled)
2440                 _tegra_dc_disable(dc);
2441         dc->enabled = false;
2442         mutex_unlock(&dc->lock);
2443         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2444
2445 #ifdef CONFIG_SWITCH
2446         switch_dev_unregister(&dc->modeset_switch);
2447 #endif
2448         free_irq(dc->irq, dc);
2449         clk_put(dc->emc_clk);
2450         clk_put(dc->clk);
2451         iounmap(dc->base);
2452         if (dc->fb_mem)
2453                 release_resource(dc->base_res);
2454         kfree(dc);
2455         tegra_dc_set(NULL, ndev->id);
2456
2457         return 0;
2458 }
2459
2460 #ifdef CONFIG_PM
2461 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2462 {
2463         struct tegra_dc *dc = platform_get_drvdata(ndev);
2464
2465         trace_display_suspend(dc);
2466         dev_info(&ndev->dev, "suspend\n");
2467
2468         tegra_dc_ext_disable(dc->ext);
2469
2470         mutex_lock(&dc->lock);
2471         tegra_dc_io_start(dc);
2472
2473         if (dc->out_ops && dc->out_ops->suspend)
2474                 dc->out_ops->suspend(dc);
2475
2476         if (dc->enabled) {
2477                 _tegra_dc_disable(dc);
2478
2479                 dc->suspended = true;
2480         }
2481
2482         if (dc->out && dc->out->postsuspend) {
2483                 dc->out->postsuspend();
2484                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2485                         /*
2486                          * avoid resume event due to voltage falling
2487                          */
2488                         msleep(100);
2489         }
2490
2491         tegra_dc_io_end(dc);
2492         mutex_unlock(&dc->lock);
2493         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2494
2495         return 0;
2496 }
2497
2498 static int tegra_dc_resume(struct platform_device *ndev)
2499 {
2500         struct tegra_dc *dc = platform_get_drvdata(ndev);
2501
2502         trace_display_resume(dc);
2503         dev_info(&ndev->dev, "resume\n");
2504
2505         mutex_lock(&dc->lock);
2506         dc->suspended = false;
2507
2508         if (dc->enabled) {
2509                 dc->enabled = false;
2510                 _tegra_dc_set_default_videomode(dc);
2511                 dc->enabled = _tegra_dc_enable(dc);
2512         }
2513
2514         if (dc->out && dc->out->hotplug_init)
2515                 dc->out->hotplug_init(&ndev->dev);
2516
2517         if (dc->out_ops && dc->out_ops->resume)
2518                 dc->out_ops->resume(dc);
2519         mutex_unlock(&dc->lock);
2520
2521         return 0;
2522 }
2523
2524 #endif /* CONFIG_PM */
2525
2526 static void tegra_dc_shutdown(struct platform_device *ndev)
2527 {
2528         struct tegra_dc *dc = platform_get_drvdata(ndev);
2529
2530         if (!dc || !dc->enabled)
2531                 return;
2532
2533         tegra_dc_blank(dc);
2534         tegra_dc_disable(dc);
2535 }
2536
2537 extern int suspend_set(const char *val, struct kernel_param *kp)
2538 {
2539         if (!strcmp(val, "dump"))
2540                 dump_regs(tegra_dcs[0]);
2541 #ifdef CONFIG_PM
2542         else if (!strcmp(val, "suspend"))
2543                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2544         else if (!strcmp(val, "resume"))
2545                 tegra_dc_resume(tegra_dcs[0]->ndev);
2546 #endif
2547
2548         return 0;
2549 }
2550
2551 extern int suspend_get(char *buffer, struct kernel_param *kp)
2552 {
2553         return 0;
2554 }
2555
2556 int suspend;
2557
2558 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2559
2560 struct platform_driver tegra_dc_driver = {
2561         .driver = {
2562                 .name = "tegradc",
2563                 .owner = THIS_MODULE,
2564         },
2565         .probe = tegra_dc_probe,
2566         .remove = tegra_dc_remove,
2567 #ifdef CONFIG_PM
2568         .suspend = tegra_dc_suspend,
2569         .resume = tegra_dc_resume,
2570 #endif
2571         .shutdown = tegra_dc_shutdown,
2572 };
2573
2574 #ifndef MODULE
2575 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2576 {
2577         int i, params[11];
2578         char *p;
2579
2580         for (i = 0; i < ARRAY_SIZE(params); i++) {
2581                 if ((p = strsep(&options, ",")) != NULL) {
2582                         if (*p)
2583                                 params[i] = simple_strtoul(p, &p, 10);
2584                 } else
2585                         return -EINVAL;
2586         }
2587
2588         if ((mode->pclk = params[0]) == 0)
2589                 return -EINVAL;
2590
2591         mode->h_active      = params[1];
2592         mode->v_active      = params[2];
2593         mode->h_ref_to_sync = params[3];
2594         mode->v_ref_to_sync = params[4];
2595         mode->h_sync_width  = params[5];
2596         mode->v_sync_width  = params[6];
2597         mode->h_back_porch  = params[7];
2598         mode->v_back_porch  = params[8];
2599         mode->h_front_porch = params[9];
2600         mode->v_front_porch = params[10];
2601
2602         return 0;
2603 }
2604
2605 static int __init tegra_dc_mode_override(char *str)
2606 {
2607         char *p = str, *options;
2608
2609         if (!p || !*p)
2610                 return -EINVAL;
2611
2612         p = strstr(str, "hdmi:");
2613         if (p) {
2614                 p += 5;
2615                 options = strsep(&p, ";");
2616                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2617                         return -EINVAL;
2618         }
2619
2620         p = strstr(str, "rgb:");
2621         if (p) {
2622                 p += 4;
2623                 options = strsep(&p, ";");
2624                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2625                         return -EINVAL;
2626         }
2627
2628         p = strstr(str, "dsi:");
2629         if (p) {
2630                 p += 4;
2631                 options = strsep(&p, ";");
2632                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2633                         return -EINVAL;
2634         }
2635
2636         return 0;
2637 }
2638
2639 __setup("disp_params=", tegra_dc_mode_override);
2640 #endif
2641
2642 static int __init tegra_dc_module_init(void)
2643 {
2644         int ret = tegra_dc_ext_module_init();
2645         if (ret)
2646                 return ret;
2647         return platform_driver_register(&tegra_dc_driver);
2648 }
2649
2650 static void __exit tegra_dc_module_exit(void)
2651 {
2652         platform_driver_unregister(&tegra_dc_driver);
2653         tegra_dc_ext_module_exit();
2654 }
2655
2656 module_exit(tegra_dc_module_exit);
2657 module_init(tegra_dc_module_init);