video: tegra: dc: request bandwidth from isomgr
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2013, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <video/tegrafb.h>
41 #include <drm/drm_fixed.h>
42 #ifdef CONFIG_SWITCH
43 #include <linux/switch.h>
44 #endif
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55 #include <mach/pm_domains.h>
56
57 #include "dc_reg.h"
58 #include "dc_config.h"
59 #include "dc_priv.h"
60 #include "dev.h"
61 #include "nvsd.h"
62
63 /* HACK! This needs to come from DT */
64 #include "../../../../arch/arm/mach-tegra/iomap.h"
65
66 #define TEGRA_CRC_LATCHED_DELAY         34
67
68 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
69 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
70
71 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
72         .refresh = 60,
73         .xres = 640,
74         .yres = 480,
75         .pixclock = KHZ2PICOS(25200),
76         .hsync_len = 96,        /* h_sync_width */
77         .vsync_len = 2,         /* v_sync_width */
78         .left_margin = 48,      /* h_back_porch */
79         .upper_margin = 33,     /* v_back_porch */
80         .right_margin = 16,     /* h_front_porch */
81         .lower_margin = 10,     /* v_front_porch */
82         .vmode = 0,
83         .sync = 0,
84 };
85
86 static struct tegra_dc_mode override_disp_mode[3];
87
88 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
89
90 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
91
92 DEFINE_MUTEX(tegra_dc_lock);
93 DEFINE_MUTEX(shared_lock);
94
95 static const struct {
96         bool h;
97         bool v;
98 } can_filter[] = {
99         /* Window A has no filtering */
100         { false, false },
101         /* Window B has both H and V filtering */
102         { true,  true  },
103         /* Window C has only H filtering */
104         { false, true  },
105 };
106
107 #ifdef CONFIG_TEGRA_DC_CMU
108 static struct tegra_dc_cmu default_cmu = {
109         /* lut1 maps sRGB to linear space. */
110         {
111                 0,    1,    2,    4,    5,    6,    7,    9,
112                 10,   11,   12,   14,   15,   16,   18,   20,
113                 21,   23,   25,   27,   29,   31,   33,   35,
114                 37,   40,   42,   45,   48,   50,   53,   56,
115                 59,   62,   66,   69,   72,   76,   79,   83,
116                 87,   91,   95,   99,   103,  107,  112,  116,
117                 121,  126,  131,  136,  141,  146,  151,  156,
118                 162,  168,  173,  179,  185,  191,  197,  204,
119                 210,  216,  223,  230,  237,  244,  251,  258,
120                 265,  273,  280,  288,  296,  304,  312,  320,
121                 329,  337,  346,  354,  363,  372,  381,  390,
122                 400,  409,  419,  428,  438,  448,  458,  469,
123                 479,  490,  500,  511,  522,  533,  544,  555,
124                 567,  578,  590,  602,  614,  626,  639,  651,
125                 664,  676,  689,  702,  715,  728,  742,  755,
126                 769,  783,  797,  811,  825,  840,  854,  869,
127                 884,  899,  914,  929,  945,  960,  976,  992,
128                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
129                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
130                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
131                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
132                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
133                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
134                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
135                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
136                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
137                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
138                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
139                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
140                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
141                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
142                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
143         },
144         /* csc */
145         {
146                 0x100, 0x0,   0x0,
147                 0x0,   0x100, 0x0,
148                 0x0,   0x0,   0x100,
149         },
150         /* lut2 maps linear space to sRGB*/
151         {
152                 0,    1,    2,    2,    3,    4,    5,    6,
153                 6,    7,    8,    9,    10,   10,   11,   12,
154                 13,   13,   14,   15,   15,   16,   16,   17,
155                 18,   18,   19,   19,   20,   20,   21,   21,
156                 22,   22,   23,   23,   23,   24,   24,   25,
157                 25,   25,   26,   26,   27,   27,   27,   28,
158                 28,   29,   29,   29,   30,   30,   30,   31,
159                 31,   31,   32,   32,   32,   33,   33,   33,
160                 34,   34,   34,   34,   35,   35,   35,   36,
161                 36,   36,   37,   37,   37,   37,   38,   38,
162                 38,   38,   39,   39,   39,   40,   40,   40,
163                 40,   41,   41,   41,   41,   42,   42,   42,
164                 42,   43,   43,   43,   43,   43,   44,   44,
165                 44,   44,   45,   45,   45,   45,   46,   46,
166                 46,   46,   46,   47,   47,   47,   47,   48,
167                 48,   48,   48,   48,   49,   49,   49,   49,
168                 49,   50,   50,   50,   50,   50,   51,   51,
169                 51,   51,   51,   52,   52,   52,   52,   52,
170                 53,   53,   53,   53,   53,   54,   54,   54,
171                 54,   54,   55,   55,   55,   55,   55,   55,
172                 56,   56,   56,   56,   56,   57,   57,   57,
173                 57,   57,   57,   58,   58,   58,   58,   58,
174                 58,   59,   59,   59,   59,   59,   59,   60,
175                 60,   60,   60,   60,   60,   61,   61,   61,
176                 61,   61,   61,   62,   62,   62,   62,   62,
177                 62,   63,   63,   63,   63,   63,   63,   64,
178                 64,   64,   64,   64,   64,   64,   65,   65,
179                 65,   65,   65,   65,   66,   66,   66,   66,
180                 66,   66,   66,   67,   67,   67,   67,   67,
181                 67,   67,   68,   68,   68,   68,   68,   68,
182                 68,   69,   69,   69,   69,   69,   69,   69,
183                 70,   70,   70,   70,   70,   70,   70,   71,
184                 71,   71,   71,   71,   71,   71,   72,   72,
185                 72,   72,   72,   72,   72,   72,   73,   73,
186                 73,   73,   73,   73,   73,   74,   74,   74,
187                 74,   74,   74,   74,   74,   75,   75,   75,
188                 75,   75,   75,   75,   75,   76,   76,   76,
189                 76,   76,   76,   76,   77,   77,   77,   77,
190                 77,   77,   77,   77,   78,   78,   78,   78,
191                 78,   78,   78,   78,   78,   79,   79,   79,
192                 79,   79,   79,   79,   79,   80,   80,   80,
193                 80,   80,   80,   80,   80,   81,   81,   81,
194                 81,   81,   81,   81,   81,   81,   82,   82,
195                 82,   82,   82,   82,   82,   82,   83,   83,
196                 83,   83,   83,   83,   83,   83,   83,   84,
197                 84,   84,   84,   84,   84,   84,   84,   84,
198                 85,   85,   85,   85,   85,   85,   85,   85,
199                 85,   86,   86,   86,   86,   86,   86,   86,
200                 86,   86,   87,   87,   87,   87,   87,   87,
201                 87,   87,   87,   88,   88,   88,   88,   88,
202                 88,   88,   88,   88,   88,   89,   89,   89,
203                 89,   89,   89,   89,   89,   89,   90,   90,
204                 90,   90,   90,   90,   90,   90,   90,   90,
205                 91,   91,   91,   91,   91,   91,   91,   91,
206                 91,   91,   92,   92,   92,   92,   92,   92,
207                 92,   92,   92,   92,   93,   93,   93,   93,
208                 93,   93,   93,   93,   93,   93,   94,   94,
209                 94,   94,   94,   94,   94,   94,   94,   94,
210                 95,   95,   95,   95,   95,   95,   95,   95,
211                 95,   95,   96,   96,   96,   96,   96,   96,
212                 96,   96,   96,   96,   96,   97,   97,   97,
213                 97,   97,   97,   97,   97,   97,   97,   98,
214                 98,   98,   98,   98,   98,   98,   98,   98,
215                 98,   98,   99,   99,   99,   99,   99,   99,
216                 99,   100,  101,  101,  102,  103,  103,  104,
217                 105,  105,  106,  107,  107,  108,  109,  109,
218                 110,  111,  111,  112,  113,  113,  114,  115,
219                 115,  116,  116,  117,  118,  118,  119,  119,
220                 120,  120,  121,  122,  122,  123,  123,  124,
221                 124,  125,  126,  126,  127,  127,  128,  128,
222                 129,  129,  130,  130,  131,  131,  132,  132,
223                 133,  133,  134,  134,  135,  135,  136,  136,
224                 137,  137,  138,  138,  139,  139,  140,  140,
225                 141,  141,  142,  142,  143,  143,  144,  144,
226                 145,  145,  145,  146,  146,  147,  147,  148,
227                 148,  149,  149,  150,  150,  150,  151,  151,
228                 152,  152,  153,  153,  153,  154,  154,  155,
229                 155,  156,  156,  156,  157,  157,  158,  158,
230                 158,  159,  159,  160,  160,  160,  161,  161,
231                 162,  162,  162,  163,  163,  164,  164,  164,
232                 165,  165,  166,  166,  166,  167,  167,  167,
233                 168,  168,  169,  169,  169,  170,  170,  170,
234                 171,  171,  172,  172,  172,  173,  173,  173,
235                 174,  174,  174,  175,  175,  176,  176,  176,
236                 177,  177,  177,  178,  178,  178,  179,  179,
237                 179,  180,  180,  180,  181,  181,  182,  182,
238                 182,  183,  183,  183,  184,  184,  184,  185,
239                 185,  185,  186,  186,  186,  187,  187,  187,
240                 188,  188,  188,  189,  189,  189,  189,  190,
241                 190,  190,  191,  191,  191,  192,  192,  192,
242                 193,  193,  193,  194,  194,  194,  195,  195,
243                 195,  196,  196,  196,  196,  197,  197,  197,
244                 198,  198,  198,  199,  199,  199,  200,  200,
245                 200,  200,  201,  201,  201,  202,  202,  202,
246                 202,  203,  203,  203,  204,  204,  204,  205,
247                 205,  205,  205,  206,  206,  206,  207,  207,
248                 207,  207,  208,  208,  208,  209,  209,  209,
249                 209,  210,  210,  210,  211,  211,  211,  211,
250                 212,  212,  212,  213,  213,  213,  213,  214,
251                 214,  214,  214,  215,  215,  215,  216,  216,
252                 216,  216,  217,  217,  217,  217,  218,  218,
253                 218,  219,  219,  219,  219,  220,  220,  220,
254                 220,  221,  221,  221,  221,  222,  222,  222,
255                 223,  223,  223,  223,  224,  224,  224,  224,
256                 225,  225,  225,  225,  226,  226,  226,  226,
257                 227,  227,  227,  227,  228,  228,  228,  228,
258                 229,  229,  229,  229,  230,  230,  230,  230,
259                 231,  231,  231,  231,  232,  232,  232,  232,
260                 233,  233,  233,  233,  234,  234,  234,  234,
261                 235,  235,  235,  235,  236,  236,  236,  236,
262                 237,  237,  237,  237,  238,  238,  238,  238,
263                 239,  239,  239,  239,  240,  240,  240,  240,
264                 240,  241,  241,  241,  241,  242,  242,  242,
265                 242,  243,  243,  243,  243,  244,  244,  244,
266                 244,  244,  245,  245,  245,  245,  246,  246,
267                 246,  246,  247,  247,  247,  247,  247,  248,
268                 248,  248,  248,  249,  249,  249,  249,  249,
269                 250,  250,  250,  250,  251,  251,  251,  251,
270                 251,  252,  252,  252,  252,  253,  253,  253,
271                 253,  253,  254,  254,  254,  254,  255,  255,
272         },
273 };
274 #endif
275
276 void tegra_dc_clk_enable(struct tegra_dc *dc)
277 {
278         if (!tegra_is_clk_enabled(dc->clk)) {
279                 clk_prepare_enable(dc->clk);
280                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
281         }
282 }
283
284 void tegra_dc_clk_disable(struct tegra_dc *dc)
285 {
286         if (tegra_is_clk_enabled(dc->clk)) {
287                 clk_disable_unprepare(dc->clk);
288                 tegra_dvfs_set_rate(dc->clk, 0);
289         }
290 }
291
292 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
293 {
294         /* extra reference to dc clk */
295         clk_prepare_enable(dc->clk);
296
297         if (dc->out_ops->hold)
298                 dc->out_ops->hold(dc);
299 }
300
301 void tegra_dc_release_dc_out(struct tegra_dc *dc)
302 {
303         if (dc->out_ops->release)
304                 dc->out_ops->release(dc);
305
306         /* balance extra dc clk reference */
307         clk_disable_unprepare(dc->clk);
308 }
309
310 #define DUMP_REG(a) do {                        \
311         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
312                  #a, a, tegra_dc_readl(dc, a));               \
313         print(data, buff);                                    \
314         } while (0)
315
316 static void _dump_regs(struct tegra_dc *dc, void *data,
317                        void (* print)(void *data, const char *str))
318 {
319         int i;
320         char buff[256];
321
322         mutex_lock(&dc->lock);
323         tegra_dc_io_start(dc);
324         tegra_dc_hold_dc_out(dc);
325
326         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
327         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
328         DUMP_REG(DC_CMD_SIGNAL_RAISE);
329         DUMP_REG(DC_CMD_INT_STATUS);
330         DUMP_REG(DC_CMD_INT_MASK);
331         DUMP_REG(DC_CMD_INT_ENABLE);
332         DUMP_REG(DC_CMD_INT_TYPE);
333         DUMP_REG(DC_CMD_INT_POLARITY);
334         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
335         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
336         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
337         DUMP_REG(DC_CMD_STATE_ACCESS);
338         DUMP_REG(DC_CMD_STATE_CONTROL);
339         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
340         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
341
342         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
343         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
344         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
345         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
346         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
347         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
348         DUMP_REG(DC_DISP_REF_TO_SYNC);
349         DUMP_REG(DC_DISP_SYNC_WIDTH);
350         DUMP_REG(DC_DISP_BACK_PORCH);
351         DUMP_REG(DC_DISP_DISP_ACTIVE);
352         DUMP_REG(DC_DISP_FRONT_PORCH);
353         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
354         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
355         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
356         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
357         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
358         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
359         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
360         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
361         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
362         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
363         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
364         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
365         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
366         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
367         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
368         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
369         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
370         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
371         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
372         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
373         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
374         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
375         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
376         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
377         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
378         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
379         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
380         DUMP_REG(DC_DISP_M0_CONTROL);
381         DUMP_REG(DC_DISP_M1_CONTROL);
382         DUMP_REG(DC_DISP_DI_CONTROL);
383         DUMP_REG(DC_DISP_PP_CONTROL);
384         DUMP_REG(DC_DISP_PP_SELECT_A);
385         DUMP_REG(DC_DISP_PP_SELECT_B);
386         DUMP_REG(DC_DISP_PP_SELECT_C);
387         DUMP_REG(DC_DISP_PP_SELECT_D);
388         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
389         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
390         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
391         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
392         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
393         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
394         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
395         DUMP_REG(DC_DISP_BORDER_COLOR);
396         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
397         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
398         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
399         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
400         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
401         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
402         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
403         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
404         DUMP_REG(DC_DISP_CURSOR_POSITION);
405         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
406         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
407         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
408         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
409         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
410         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
411         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
412         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
413         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
414         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
415 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
416         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
417 #endif
418         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
419         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
420
421
422         for (i = 0; i < 3; i++) {
423                 print(data, "\n");
424                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
425                 print(data, buff);
426
427                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
428                                 DC_CMD_DISPLAY_WINDOW_HEADER);
429                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
430                 DUMP_REG(DC_WIN_WIN_OPTIONS);
431                 DUMP_REG(DC_WIN_BYTE_SWAP);
432                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
433                 DUMP_REG(DC_WIN_COLOR_DEPTH);
434                 DUMP_REG(DC_WIN_POSITION);
435                 DUMP_REG(DC_WIN_SIZE);
436                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
437                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
438                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
439                 DUMP_REG(DC_WIN_DDA_INCREMENT);
440                 DUMP_REG(DC_WIN_LINE_STRIDE);
441 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
442                 DUMP_REG(DC_WIN_BUF_STRIDE);
443                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
444 #endif
445                 DUMP_REG(DC_WIN_BLEND_NOKEY);
446                 DUMP_REG(DC_WIN_BLEND_1WIN);
447                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
448                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
449                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
450                 DUMP_REG(DC_WINBUF_START_ADDR);
451                 DUMP_REG(DC_WINBUF_START_ADDR_U);
452                 DUMP_REG(DC_WINBUF_START_ADDR_V);
453                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
454                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
455                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
456                 DUMP_REG(DC_WIN_CSC_YOF);
457                 DUMP_REG(DC_WIN_CSC_KYRGB);
458                 DUMP_REG(DC_WIN_CSC_KUR);
459                 DUMP_REG(DC_WIN_CSC_KVR);
460                 DUMP_REG(DC_WIN_CSC_KUG);
461                 DUMP_REG(DC_WIN_CSC_KVG);
462                 DUMP_REG(DC_WIN_CSC_KUB);
463                 DUMP_REG(DC_WIN_CSC_KVB);
464         }
465
466         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
467         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
468         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
469         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
470         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
471         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
472         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
473         DUMP_REG(DC_DISP_M1_CONTROL);
474         DUMP_REG(DC_COM_PM1_CONTROL);
475         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
476         DUMP_REG(DC_DISP_SD_CONTROL);
477 #ifdef CONFIG_TEGRA_DC_CMU
478         DUMP_REG(DC_COM_CMU_CSC_KRR);
479         DUMP_REG(DC_COM_CMU_CSC_KGR);
480         DUMP_REG(DC_COM_CMU_CSC_KBR);
481         DUMP_REG(DC_COM_CMU_CSC_KRG);
482         DUMP_REG(DC_COM_CMU_CSC_KGG);
483         DUMP_REG(DC_COM_CMU_CSC_KBR);
484         DUMP_REG(DC_COM_CMU_CSC_KRB);
485         DUMP_REG(DC_COM_CMU_CSC_KGB);
486         DUMP_REG(DC_COM_CMU_CSC_KBB);
487 #endif
488
489         tegra_dc_release_dc_out(dc);
490         tegra_dc_io_end(dc);
491         mutex_unlock(&dc->lock);
492 }
493
494 #undef DUMP_REG
495
496 #ifdef DEBUG
497 static void dump_regs_print(void *data, const char *str)
498 {
499         struct tegra_dc *dc = data;
500         dev_dbg(&dc->ndev->dev, "%s", str);
501 }
502
503 static void dump_regs(struct tegra_dc *dc)
504 {
505         _dump_regs(dc, dc, dump_regs_print);
506 }
507 #else /* !DEBUG */
508
509 static void dump_regs(struct tegra_dc *dc) {}
510
511 #endif /* DEBUG */
512
513 #ifdef CONFIG_DEBUG_FS
514
515 static void dbg_regs_print(void *data, const char *str)
516 {
517         struct seq_file *s = data;
518
519         seq_printf(s, "%s", str);
520 }
521
522 #undef DUMP_REG
523
524 static int dbg_dc_show(struct seq_file *s, void *unused)
525 {
526         struct tegra_dc *dc = s->private;
527
528         _dump_regs(dc, s, dbg_regs_print);
529
530         return 0;
531 }
532
533
534 static int dbg_dc_open(struct inode *inode, struct file *file)
535 {
536         return single_open(file, dbg_dc_show, inode->i_private);
537 }
538
539 static const struct file_operations regs_fops = {
540         .open           = dbg_dc_open,
541         .read           = seq_read,
542         .llseek         = seq_lseek,
543         .release        = single_release,
544 };
545
546 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
547 {
548         struct tegra_dc *dc = s->private;
549         struct tegra_dc_mode *m;
550
551         mutex_lock(&dc->lock);
552         m = &dc->mode;
553         seq_printf(s,
554                 "pclk: %d\n"
555                 "h_ref_to_sync: %d\n"
556                 "v_ref_to_sync: %d\n"
557                 "h_sync_width: %d\n"
558                 "v_sync_width: %d\n"
559                 "h_back_porch: %d\n"
560                 "v_back_porch: %d\n"
561                 "h_active: %d\n"
562                 "v_active: %d\n"
563                 "h_front_porch: %d\n"
564                 "v_front_porch: %d\n"
565                 "stereo_mode: %d\n",
566                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
567                 m->h_sync_width, m->v_sync_width,
568                 m->h_back_porch, m->v_back_porch,
569                 m->h_active, m->v_active,
570                 m->h_front_porch, m->v_front_porch,
571                 m->stereo_mode);
572         mutex_unlock(&dc->lock);
573         return 0;
574 }
575
576 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
577 {
578         return single_open(file, dbg_dc_mode_show, inode->i_private);
579 }
580
581 static const struct file_operations mode_fops = {
582         .open           = dbg_dc_mode_open,
583         .read           = seq_read,
584         .llseek         = seq_lseek,
585         .release        = single_release,
586 };
587
588 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
589 {
590         struct tegra_dc *dc = s->private;
591
592         mutex_lock(&dc->lock);
593         seq_printf(s,
594                 "underflows: %llu\n"
595                 "underflows_a: %llu\n"
596                 "underflows_b: %llu\n"
597                 "underflows_c: %llu\n",
598                 dc->stats.underflows,
599                 dc->stats.underflows_a,
600                 dc->stats.underflows_b,
601                 dc->stats.underflows_c);
602 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
603         seq_printf(s,
604                 "underflows_d: %llu\n"
605                 "underflows_h: %llu\n"
606                 "underflows_t: %llu\n",
607                 dc->stats.underflows_d,
608                 dc->stats.underflows_h,
609                 dc->stats.underflows_t);
610 #endif
611         mutex_unlock(&dc->lock);
612
613         return 0;
614 }
615
616 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
617 {
618         return single_open(file, dbg_dc_stats_show, inode->i_private);
619 }
620
621 static const struct file_operations stats_fops = {
622         .open           = dbg_dc_stats_open,
623         .read           = seq_read,
624         .llseek         = seq_lseek,
625         .release        = single_release,
626 };
627
628 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
629 {
630         if (dc->debugdir)
631                 debugfs_remove_recursive(dc->debugdir);
632         dc->debugdir = NULL;
633 }
634
635 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
636 {
637         struct dentry *retval;
638
639         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
640         if (!dc->debugdir)
641                 goto remove_out;
642
643         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
644                 &regs_fops);
645         if (!retval)
646                 goto remove_out;
647
648         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
649                 &mode_fops);
650         if (!retval)
651                 goto remove_out;
652
653         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
654                 &stats_fops);
655         if (!retval)
656                 goto remove_out;
657
658         return;
659 remove_out:
660         dev_err(&dc->ndev->dev, "could not create debugfs\n");
661         tegra_dc_remove_debugfs(dc);
662 }
663
664 #else /* !CONFIG_DEBUGFS */
665 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
666 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
667 #endif /* CONFIG_DEBUGFS */
668
669 static int tegra_dc_set(struct tegra_dc *dc, int index)
670 {
671         int ret = 0;
672
673         mutex_lock(&tegra_dc_lock);
674         if (index >= TEGRA_MAX_DC) {
675                 ret = -EINVAL;
676                 goto out;
677         }
678
679         if (dc != NULL && tegra_dcs[index] != NULL) {
680                 ret = -EBUSY;
681                 goto out;
682         }
683
684         tegra_dcs[index] = dc;
685
686 out:
687         mutex_unlock(&tegra_dc_lock);
688
689         return ret;
690 }
691
692 unsigned int tegra_dc_has_multiple_dc(void)
693 {
694         unsigned int idx;
695         unsigned int cnt = 0;
696         struct tegra_dc *dc;
697
698         mutex_lock(&tegra_dc_lock);
699         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
700                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
701         mutex_unlock(&tegra_dc_lock);
702
703         return (cnt > 1);
704 }
705
706 /* get the stride size of a window.
707  * return: stride size in bytes for window win. or 0 if unavailble. */
708 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
709 {
710         u32 stride;
711
712         if (!dc->enabled)
713                 return 0;
714         BUG_ON(win > DC_N_WINDOWS);
715         mutex_lock(&dc->lock);
716         tegra_dc_io_start(dc);
717         tegra_dc_hold_dc_out(dc);
718         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
719                 DC_CMD_DISPLAY_WINDOW_HEADER);
720         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
721         tegra_dc_release_dc_out(dc);
722         tegra_dc_io_end(dc);
723         mutex_unlock(&dc->lock);
724         return GET_LINE_STRIDE(stride);
725 }
726 EXPORT_SYMBOL(tegra_dc_get_stride);
727
728 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
729 {
730         if (idx < TEGRA_MAX_DC)
731                 return tegra_dcs[idx];
732         else
733                 return NULL;
734 }
735 EXPORT_SYMBOL(tegra_dc_get_dc);
736
737 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
738 {
739         if (win >= dc->n_windows)
740                 return NULL;
741
742         return &dc->windows[win];
743 }
744 EXPORT_SYMBOL(tegra_dc_get_window);
745
746 bool tegra_dc_get_connected(struct tegra_dc *dc)
747 {
748         return dc->connected;
749 }
750 EXPORT_SYMBOL(tegra_dc_get_connected);
751
752 bool tegra_dc_hpd(struct tegra_dc *dc)
753 {
754         int sense;
755         int level;
756
757         if (WARN_ON(!dc || !dc->out))
758                 return false;
759
760         if (dc->out->hotplug_state != 0) {
761                 if (dc->out->hotplug_state == 1) /* force on */
762                         return true;
763                 if (dc->out->hotplug_state == -1) /* force off */
764                         return false;
765         }
766         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
767
768         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
769
770         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
771                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
772 }
773 EXPORT_SYMBOL(tegra_dc_hpd);
774
775 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
776 {
777         unsigned i;
778         unsigned v0 = 128;
779         unsigned v1 = 0;
780
781         /* linear horizontal and vertical filters */
782         for (i = 0; i < 16; i++) {
783                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
784                                 DC_WIN_H_FILTER_P(i));
785
786                 tegra_dc_writel(dc, v0,
787                                 DC_WIN_V_FILTER_P(i));
788                 v0 -= 8;
789                 v1 += 8;
790         }
791 }
792
793 #ifdef CONFIG_TEGRA_DC_CMU
794 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
795                                         struct tegra_dc_cmu *src_cmu)
796 {
797         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
798 }
799
800 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
801 {
802         u32 val;
803         u32 i;
804
805         for (i = 0; i < 256; i++) {
806                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
807                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
808         }
809
810         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
811         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
812         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
813         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
814         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
815         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
816         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
817         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
818         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
819
820         for (i = 0; i < 960; i++) {
821                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
822                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
823         }
824 }
825
826 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
827 {
828         u32 val;
829         u32 i;
830         bool flags;
831
832         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
833         if (val & CMU_ENABLE)
834                 flags = true;
835
836         val &= ~CMU_ENABLE;
837         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
838         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
839         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
840
841         /*TODO: Sync up with frame end */
842         mdelay(20);
843
844         for (i = 0; i < 256; i++) {
845                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
846                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
847                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
848                 cmu->lut1[i] = LUT1_READ_DATA(val);
849         }
850
851         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
852         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
853         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
854         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
855         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
856         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
857         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
858         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
859         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
860
861         for (i = 0; i < 960; i++) {
862                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
863                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
864                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
865                 cmu->lut2[i] = LUT2_READ_DATA(val);
866         }
867 }
868 EXPORT_SYMBOL(tegra_dc_get_cmu);
869
870 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
871 {
872         u32 val;
873
874         if (dc->pdata->cmu_enable) {
875                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
876         } else {
877                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
878                 return 0;
879         }
880
881 #ifdef CONFIG_TEGRA_DC_CMU
882         if (cmu != &dc->cmu) {
883                 tegra_dc_cache_cmu(&dc->cmu, cmu);
884
885                 /* Disable CMU */
886                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
887                 if (val & CMU_ENABLE) {
888                         val &= ~CMU_ENABLE;
889                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
890                         val = GENERAL_UPDATE;
891                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
892                         val = GENERAL_ACT_REQ;
893                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
894                         /*TODO: Sync up with vsync */
895                         mdelay(20);
896                 }
897
898                 tegra_dc_set_cmu(dc, &dc->cmu);
899         }
900 #endif
901
902         return 0;
903 }
904
905 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
906 {
907         int ret;
908
909         mutex_lock(&dc->lock);
910         if (!dc->enabled) {
911                 mutex_unlock(&dc->lock);
912                 return 0;
913         }
914         tegra_dc_io_start(dc);
915         tegra_dc_hold_dc_out(dc);
916
917         ret = _tegra_dc_update_cmu(dc, cmu);
918         tegra_dc_set_color_control(dc);
919
920         tegra_dc_release_dc_out(dc);
921         tegra_dc_io_end(dc);
922         mutex_unlock(&dc->lock);
923
924         return ret;
925 }
926 EXPORT_SYMBOL(tegra_dc_update_cmu);
927
928 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
929 {
930         dc->pdata->cmu_enable = cmu_enable;
931         if (dc->pdata->cmu)
932                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
933         else
934                 tegra_dc_update_cmu(dc, &default_cmu);
935 }
936 #else
937 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
938 #define tegra_dc_set_cmu(dc, cmu)
939 #define tegra_dc_update_cmu(dc, cmu)
940 #endif
941
942 /* disable_irq() blocks until handler completes, calling this function while
943  * holding dc->lock can deadlock. */
944 static inline void disable_dc_irq(const struct tegra_dc *dc)
945 {
946         disable_irq(dc->irq);
947 }
948
949 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
950 {
951         return dc->syncpt[i].id;
952 }
953 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
954
955 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
956 {
957         u32 max;
958
959         mutex_lock(&dc->lock);
960         tegra_dc_io_start(dc);
961         tegra_dc_hold_dc_out(dc);
962         max = nvhost_syncpt_incr_max_ext(dc->ndev,
963                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
964         dc->syncpt[i].max = max;
965         tegra_dc_release_dc_out(dc);
966         tegra_dc_io_end(dc);
967         mutex_unlock(&dc->lock);
968
969         return max;
970 }
971
972 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
973 {
974         mutex_lock(&dc->lock);
975         if (dc->enabled) {
976                 tegra_dc_io_start(dc);
977                 tegra_dc_hold_dc_out(dc);
978                 while (dc->syncpt[i].min < val) {
979                         dc->syncpt[i].min++;
980                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
981                 }
982                 tegra_dc_release_dc_out(dc);
983                 tegra_dc_io_end(dc);
984         }
985         mutex_unlock(&dc->lock);
986 }
987
988 void
989 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
990 {
991         unsigned int ctrl;
992         unsigned long out_sel;
993         unsigned long cmd_state;
994
995         mutex_lock(&dc->lock);
996         if (!dc->enabled) {
997                 mutex_unlock(&dc->lock);
998                 return;
999         }
1000
1001         tegra_dc_io_start(dc);
1002         tegra_dc_hold_dc_out(dc);
1003
1004         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1005                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1006                 cfg->clk_select);
1007
1008         /* The new value should be effected immediately */
1009         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1010         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1011
1012         switch (cfg->which_pwm) {
1013         case TEGRA_PWM_PM0:
1014                 /* Select the LM0 on PM0 */
1015                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1016                 out_sel &= ~(7 << 0);
1017                 out_sel |= (3 << 0);
1018                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1019                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1020                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1021                 break;
1022         case TEGRA_PWM_PM1:
1023                 /* Select the LM1 on PM1 */
1024                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1025                 out_sel &= ~(7 << 4);
1026                 out_sel |= (3 << 4);
1027                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1028                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1029                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1030                 break;
1031         default:
1032                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1033                 break;
1034         }
1035         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1036         tegra_dc_release_dc_out(dc);
1037         tegra_dc_io_end(dc);
1038         mutex_unlock(&dc->lock);
1039 }
1040 EXPORT_SYMBOL(tegra_dc_config_pwm);
1041
1042 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1043                                 const struct tegra_dc_out_pin *pins,
1044                                 const unsigned int n_pins)
1045 {
1046         unsigned int i;
1047
1048         int name;
1049         int pol;
1050
1051         u32 pol1, pol3;
1052
1053         u32 set1, unset1;
1054         u32 set3, unset3;
1055
1056         set1 = set3 = unset1 = unset3 = 0;
1057
1058         for (i = 0; i < n_pins; i++) {
1059                 name = (pins + i)->name;
1060                 pol  = (pins + i)->pol;
1061
1062                 /* set polarity by name */
1063                 switch (name) {
1064                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1065                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1066                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1067                         else
1068                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1069                         break;
1070                 case TEGRA_DC_OUT_PIN_H_SYNC:
1071                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1072                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1073                         else
1074                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1075                         break;
1076                 case TEGRA_DC_OUT_PIN_V_SYNC:
1077                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1078                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1079                         else
1080                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1081                         break;
1082                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1083                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1084                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1085                         else
1086                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1087                         break;
1088                 default:
1089                         printk("Invalid argument in function %s\n",
1090                                __FUNCTION__);
1091                         break;
1092                 }
1093         }
1094
1095         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1096         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1097
1098         pol1 |= set1;
1099         pol1 &= ~unset1;
1100
1101         pol3 |= set3;
1102         pol3 &= ~unset3;
1103
1104         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1105         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1106 }
1107
1108 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1109 {
1110         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1111                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1112                 dc->out->type == TEGRA_DC_OUT_DSI)
1113                 return override_disp_mode[dc->out->type].pclk ?
1114                         &override_disp_mode[dc->out->type] : NULL;
1115         else
1116                 return NULL;
1117 }
1118
1119 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1120 {
1121         struct tegra_dc_mode *mode;
1122
1123         dc->out = out;
1124         mode = tegra_dc_get_override_mode(dc);
1125
1126         if (mode)
1127                 tegra_dc_set_mode(dc, mode);
1128         else if (out->n_modes > 0)
1129                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1130
1131         switch (out->type) {
1132         case TEGRA_DC_OUT_RGB:
1133                 dc->out_ops = &tegra_dc_rgb_ops;
1134                 break;
1135
1136         case TEGRA_DC_OUT_HDMI:
1137                 dc->out_ops = &tegra_dc_hdmi_ops;
1138                 break;
1139
1140         case TEGRA_DC_OUT_DSI:
1141                 dc->out_ops = &tegra_dc_dsi_ops;
1142                 break;
1143
1144         default:
1145                 dc->out_ops = NULL;
1146                 break;
1147         }
1148
1149         if (dc->out_ops && dc->out_ops->init)
1150                 dc->out_ops->init(dc);
1151 }
1152
1153 /* returns on error: -EINVAL
1154  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1155 int tegra_dc_get_out(const struct tegra_dc *dc)
1156 {
1157         if (dc && dc->out)
1158                 return dc->out->type;
1159         return -EINVAL;
1160 }
1161
1162 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1163 {
1164         if (dc->out)
1165                 return dc->out->height;
1166         else
1167                 return 0;
1168 }
1169 EXPORT_SYMBOL(tegra_dc_get_out_height);
1170
1171 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1172 {
1173         if (dc->out)
1174                 return dc->out->width;
1175         else
1176                 return 0;
1177 }
1178 EXPORT_SYMBOL(tegra_dc_get_out_width);
1179
1180 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1181 {
1182         if (dc->out && dc->out->max_pixclock)
1183                 return dc->out->max_pixclock;
1184         else
1185                 return 0;
1186 }
1187 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1188
1189 void tegra_dc_enable_crc(struct tegra_dc *dc)
1190 {
1191         u32 val;
1192
1193         mutex_lock(&dc->lock);
1194         tegra_dc_io_start(dc);
1195         tegra_dc_hold_dc_out(dc);
1196
1197         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1198                 CRC_ENABLE_ENABLE;
1199         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1200         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1201         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1202         tegra_dc_release_dc_out(dc);
1203         tegra_dc_io_end(dc);
1204         mutex_unlock(&dc->lock);
1205 }
1206
1207 void tegra_dc_disable_crc(struct tegra_dc *dc)
1208 {
1209         mutex_lock(&dc->lock);
1210         tegra_dc_io_start(dc);
1211         tegra_dc_hold_dc_out(dc);
1212         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1213         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1214         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1215
1216         tegra_dc_release_dc_out(dc);
1217         tegra_dc_io_end(dc);
1218         mutex_unlock(&dc->lock);
1219 }
1220
1221 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1222 {
1223         int crc = 0;
1224
1225         if (!dc) {
1226                 pr_err("Failed to get dc: NULL parameter.\n");
1227                 goto crc_error;
1228         }
1229
1230         if (!tegra_platform_is_linsim())
1231                 /* TODO: Replace mdelay with code to sync VBlANK, since
1232                  * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1233                 mdelay(TEGRA_CRC_LATCHED_DELAY);
1234
1235         mutex_lock(&dc->lock);
1236         tegra_dc_io_start(dc);
1237         tegra_dc_hold_dc_out(dc);
1238         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1239         tegra_dc_release_dc_out(dc);
1240         tegra_dc_io_end(dc);
1241         mutex_unlock(&dc->lock);
1242 crc_error:
1243         return crc;
1244 }
1245
1246 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1247 {
1248         u32 val;
1249
1250         if (tegra_platform_is_linsim())
1251                 return false;
1252
1253         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1254         if (val & WIN_ALL_ACT_REQ)
1255                 return true;
1256
1257         return false;
1258 }
1259
1260 static inline void enable_dc_irq(const struct tegra_dc *dc)
1261 {
1262         if (tegra_platform_is_fpga())
1263                 /* Always disable DC interrupts on FPGA. */
1264                 disable_irq(dc->irq);
1265         else
1266                 enable_irq(dc->irq);
1267 }
1268
1269 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1270 {
1271         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1272                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1273 }
1274
1275 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1276 {
1277         int ret = -ENOTTY;
1278
1279         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1280                 return ret;
1281
1282         /*
1283          * Logic is as follows
1284          * a) Indicate we need a vblank.
1285          * b) Wait for completion to be signalled from isr.
1286          * c) Initialize completion for next iteration.
1287          */
1288
1289         tegra_dc_hold_dc_out(dc);
1290         dc->out->user_needs_vblank = true;
1291
1292         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1293         init_completion(&dc->out->user_vblank_comp);
1294         tegra_dc_release_dc_out(dc);
1295
1296         return ret;
1297 }
1298
1299 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1300 {
1301         /* Do the actual brightness update outside of the mutex dc->lock */
1302         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1303                 dc->out->sd_settings->bl_device_name) {
1304                 char *bl_device_name =
1305                         dc->out->sd_settings->bl_device_name;
1306                 dc->out->sd_settings->bl_device =
1307                         get_backlight_device_by_name(bl_device_name);
1308         }
1309
1310         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1311                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1312                 backlight_update_status(bl);
1313         }
1314 }
1315
1316 static void tegra_dc_vblank(struct work_struct *work)
1317 {
1318         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1319         bool nvsd_updated = false;
1320
1321         mutex_lock(&dc->lock);
1322
1323         if (!dc->enabled) {
1324                 mutex_unlock(&dc->lock);
1325                 return;
1326         }
1327
1328         tegra_dc_io_start(dc);
1329         tegra_dc_hold_dc_out(dc);
1330         /* use the new frame's bandwidth setting instead of max(current, new),
1331          * skip this if we're using tegra_dc_one_shot_worker() */
1332         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1333                 tegra_dc_program_bandwidth(dc, true);
1334
1335         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1336         if (!tegra_dc_windows_are_dirty(dc))
1337                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1338
1339         /* Update the SD brightness */
1340         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1341                 nvsd_updated = nvsd_update_brightness(dc);
1342                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1343                  * V_BLANK_NVSD bit of vblank ref-count. */
1344                 if (nvsd_updated) {
1345                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1346                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1347                 } else {
1348                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1349                 }
1350         }
1351
1352         /* Mask vblank interrupt if ref-count is zero. */
1353         if (!dc->vblank_ref_count)
1354                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1355
1356         tegra_dc_release_dc_out(dc);
1357         tegra_dc_io_end(dc);
1358         mutex_unlock(&dc->lock);
1359
1360         /* Do the actual brightness update outside of the mutex dc->lock */
1361         if (nvsd_updated)
1362                 tegra_dc_prism_update_backlight(dc);
1363 }
1364
1365 static void tegra_dc_one_shot_worker(struct work_struct *work)
1366 {
1367         struct tegra_dc *dc = container_of(
1368                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1369         mutex_lock(&dc->lock);
1370
1371         /* memory client has gone idle */
1372         tegra_dc_clear_bandwidth(dc);
1373
1374         if (dc->out_ops->idle) {
1375                 tegra_dc_io_start(dc);
1376                 dc->out_ops->idle(dc);
1377                 tegra_dc_io_end(dc);
1378         }
1379
1380         mutex_unlock(&dc->lock);
1381 }
1382
1383 /* return an arbitrarily large number if count overflow occurs.
1384  * make it a nice base-10 number to show up in stats output */
1385 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1386 {
1387         unsigned count = tegra_dc_readl(dc, reg);
1388
1389         tegra_dc_writel(dc, 0, reg);
1390         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1391 }
1392
1393 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1394 {
1395         int i;
1396
1397         dc->stats.underflows++;
1398         if (dc->underflow_mask & WIN_A_UF_INT)
1399                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1400                         DC_WINBUF_AD_UFLOW_STATUS);
1401         if (dc->underflow_mask & WIN_B_UF_INT)
1402                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1403                         DC_WINBUF_BD_UFLOW_STATUS);
1404         if (dc->underflow_mask & WIN_C_UF_INT)
1405                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1406                         DC_WINBUF_CD_UFLOW_STATUS);
1407 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1408         if (dc->underflow_mask & HC_UF_INT)
1409                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
1410                         DC_WINBUF_HD_UFLOW_STATUS);
1411         if (dc->underflow_mask & WIN_D_UF_INT)
1412                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
1413                         DC_WINBUF_DD_UFLOW_STATUS);
1414         if (dc->underflow_mask & WIN_T_UF_INT)
1415                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
1416                         DC_WINBUF_TD_UFLOW_STATUS);
1417 #endif
1418
1419         /* Check for any underflow reset conditions */
1420         for (i = 0; i < DC_N_WINDOWS; i++) {
1421                 u32 masks[] = {
1422                         WIN_A_UF_INT,
1423                         WIN_B_UF_INT,
1424                         WIN_C_UF_INT,
1425 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
1426                         WIN_D_UF_INT,
1427                         HC_UF_INT,
1428                         WIN_T_UF_INT,
1429 #endif
1430                 };
1431
1432                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
1433                         "underflow stats unsupported"))
1434                         break; /* bail if the table above is missing entries */
1435                 if (!masks[i])
1436                         continue; /* skip empty entries */
1437
1438                 if (dc->underflow_mask & masks[i]) {
1439                         dc->windows[i].underflows++;
1440
1441 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1442                         if (i < 3 && dc->windows[i].underflows > 4) {
1443                                 schedule_work(&dc->reset_work);
1444                                 /* reset counter */
1445                                 dc->windows[i].underflows = 0;
1446                                 trace_display_reset(dc);
1447                         }
1448 #endif
1449 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1450                         if (i < 3 && dc->windows[i].underflows > 4) {
1451                                 trace_display_reset(dc);
1452                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1453                                                 DC_DISP_DISP_MISC_CONTROL);
1454                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1455                                                 DC_CMD_STATE_CONTROL);
1456                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1457                                                 DC_CMD_STATE_CONTROL);
1458
1459                                 tegra_dc_writel(dc, 0,
1460                                                 DC_DISP_DISP_MISC_CONTROL);
1461                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1462                                                 DC_CMD_STATE_CONTROL);
1463                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1464                                                 DC_CMD_STATE_CONTROL);
1465                         }
1466 #endif
1467                 } else {
1468                         dc->windows[i].underflows = 0;
1469                 }
1470         }
1471
1472         /* Clear the underflow mask now that we've checked it. */
1473         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1474         dc->underflow_mask = 0;
1475         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
1476         trace_underflow(dc);
1477 }
1478
1479 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1480 static void tegra_dc_vpulse2(struct work_struct *work)
1481 {
1482         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1483         bool nvsd_updated = false;
1484
1485         mutex_lock(&dc->lock);
1486
1487         if (!dc->enabled) {
1488                 mutex_unlock(&dc->lock);
1489                 return;
1490         }
1491
1492         tegra_dc_io_start(dc);
1493         tegra_dc_hold_dc_out(dc);
1494
1495         /* Clear the V_PULSE2_FLIP if no update */
1496         if (!tegra_dc_windows_are_dirty(dc))
1497                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1498
1499         /* Update the SD brightness */
1500         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1501                 nvsd_updated = nvsd_update_brightness(dc);
1502                 if (nvsd_updated) {
1503                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1504                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1505                 } else {
1506                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1507                 }
1508         }
1509
1510         /* Mask vpulse2 interrupt if ref-count is zero. */
1511         if (!dc->vpulse2_ref_count)
1512                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1513
1514         tegra_dc_release_dc_out(dc);
1515         tegra_dc_io_end(dc);
1516         mutex_unlock(&dc->lock);
1517
1518         /* Do the actual brightness update outside of the mutex dc->lock */
1519         if (nvsd_updated)
1520                 tegra_dc_prism_update_backlight(dc);
1521 }
1522 #endif
1523
1524 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1525 {
1526         /* pending user vblank, so wakeup */
1527         if ((status & (V_BLANK_INT | MSF_INT)) &&
1528             (dc->out->user_needs_vblank)) {
1529                 dc->out->user_needs_vblank = false;
1530                 complete(&dc->out->user_vblank_comp);
1531         }
1532
1533         if (status & V_BLANK_INT) {
1534                 /* Sync up windows. */
1535                 tegra_dc_trigger_windows(dc);
1536
1537                 /* Schedule any additional bottom-half vblank actvities. */
1538                 queue_work(system_freezable_wq, &dc->vblank_work);
1539         }
1540
1541         if (status & FRAME_END_INT) {
1542                 /* Mark the frame_end as complete. */
1543                 if (!completion_done(&dc->frame_end_complete))
1544                         complete(&dc->frame_end_complete);
1545         }
1546
1547 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1548         if (status & V_PULSE2_INT)
1549                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1550 #endif
1551 }
1552
1553 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1554 {
1555         /* Schedule any additional bottom-half vblank actvities. */
1556         if (status & V_BLANK_INT)
1557                 queue_work(system_freezable_wq, &dc->vblank_work);
1558
1559         if (status & FRAME_END_INT) {
1560                 struct timespec tm = CURRENT_TIME;
1561                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1562                 wake_up(&dc->timestamp_wq);
1563
1564                 /* Mark the frame_end as complete. */
1565                 if (!completion_done(&dc->frame_end_complete))
1566                         complete(&dc->frame_end_complete);
1567
1568                 tegra_dc_trigger_windows(dc);
1569         }
1570
1571 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1572         if (status & V_PULSE2_INT)
1573                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1574 #endif
1575 }
1576
1577 /* XXX: Not sure if we limit look ahead to 1 frame */
1578 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1579 {
1580         BUG_ON(!dc->frametime_ns);
1581         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1582 }
1583
1584 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1585 {
1586         BUG_ON(!dc->frametime_ns);
1587         return (((new_ts - old_ts) > dc->frametime_ns)
1588                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1589                         != div_s64((old_ts - dc->frame_end_timestamp),
1590                                 dc->frametime_ns)));
1591 }
1592
1593 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1594 {
1595         struct tegra_dc *dc = ptr;
1596         unsigned long status;
1597         unsigned long underflow_mask;
1598         u32 val;
1599         int need_disable = 0;
1600
1601         if (tegra_platform_is_fpga())
1602                 return IRQ_NONE;
1603
1604         mutex_lock(&dc->lock);
1605         if (!dc->enabled || !tegra_dc_is_powered(dc)) {
1606                 mutex_unlock(&dc->lock);
1607                 return IRQ_HANDLED;
1608         }
1609
1610         clk_prepare_enable(dc->clk);
1611         tegra_dc_io_start(dc);
1612         tegra_dc_hold_dc_out(dc);
1613
1614         if (!nvhost_module_powered_ext(dc->ndev)) {
1615                 WARN(1, "IRQ when DC not powered!\n");
1616                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1617                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1618                 tegra_dc_release_dc_out(dc);
1619                 tegra_dc_io_end(dc);
1620                 clk_disable_unprepare(dc->clk);
1621                 mutex_unlock(&dc->lock);
1622                 return IRQ_HANDLED;
1623         }
1624
1625         /* clear all status flags except underflow, save those for the worker */
1626         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1627         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
1628         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1629         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
1630
1631         /*
1632          * Overlays can get thier internal state corrupted during and underflow
1633          * condition.  The only way to fix this state is to reset the DC.
1634          * if we get 4 consecutive frames with underflows, assume we're
1635          * hosed and reset.
1636          */
1637         underflow_mask = status & ALL_UF_INT();
1638
1639         /* Check underflow */
1640         if (underflow_mask) {
1641                 dc->underflow_mask |= underflow_mask;
1642                 schedule_delayed_work(&dc->underflow_work,
1643                         msecs_to_jiffies(1));
1644         }
1645
1646         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1647                 tegra_dc_one_shot_irq(dc, status);
1648         else
1649                 tegra_dc_continuous_irq(dc, status);
1650
1651         /* update video mode if it has changed since the last frame */
1652         if (status & (FRAME_END_INT | V_BLANK_INT))
1653                 if (tegra_dc_update_mode(dc))
1654                         need_disable = 1; /* force display off on error */
1655
1656         tegra_dc_release_dc_out(dc);
1657         tegra_dc_io_end(dc);
1658         clk_disable_unprepare(dc->clk);
1659         mutex_unlock(&dc->lock);
1660
1661         if (need_disable)
1662                 tegra_dc_disable(dc);
1663         return IRQ_HANDLED;
1664 }
1665
1666 void tegra_dc_set_color_control(struct tegra_dc *dc)
1667 {
1668         u32 color_control;
1669
1670         switch (dc->out->depth) {
1671         case 3:
1672                 color_control = BASE_COLOR_SIZE111;
1673                 break;
1674
1675         case 6:
1676                 color_control = BASE_COLOR_SIZE222;
1677                 break;
1678
1679         case 8:
1680                 color_control = BASE_COLOR_SIZE332;
1681                 break;
1682
1683         case 9:
1684                 color_control = BASE_COLOR_SIZE333;
1685                 break;
1686
1687         case 12:
1688                 color_control = BASE_COLOR_SIZE444;
1689                 break;
1690
1691         case 15:
1692                 color_control = BASE_COLOR_SIZE555;
1693                 break;
1694
1695         case 16:
1696                 color_control = BASE_COLOR_SIZE565;
1697                 break;
1698
1699         case 18:
1700                 color_control = BASE_COLOR_SIZE666;
1701                 break;
1702
1703         default:
1704                 color_control = BASE_COLOR_SIZE888;
1705                 break;
1706         }
1707
1708         switch (dc->out->dither) {
1709         case TEGRA_DC_DISABLE_DITHER:
1710                 color_control |= DITHER_CONTROL_DISABLE;
1711                 break;
1712         case TEGRA_DC_ORDERED_DITHER:
1713                 color_control |= DITHER_CONTROL_ORDERED;
1714                 break;
1715         case TEGRA_DC_ERRDIFF_DITHER:
1716                 /* The line buffer for error-diffusion dither is limited
1717                  * to 1280 pixels per line. This limits the maximum
1718                  * horizontal active area size to 1280 pixels when error
1719                  * diffusion is enabled.
1720                  */
1721                 BUG_ON(dc->mode.h_active > 1280);
1722                 color_control |= DITHER_CONTROL_ERRDIFF;
1723                 break;
1724         }
1725
1726 #ifdef CONFIG_TEGRA_DC_CMU
1727         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1728                 color_control |= CMU_ENABLE;
1729 #endif
1730
1731         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1732 }
1733
1734 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1735 {
1736         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1737                 return dc->win_syncpt[idx];
1738         BUG();
1739 }
1740
1741 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1742 {
1743 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1744         u32 start, end;
1745         unsigned long val;
1746
1747         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1748         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1749
1750         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1751                 dc->mode.v_back_porch + dc->mode.v_active;
1752         end = start + 1;
1753         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1754         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1755
1756         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1757         val |= V_PULSE2_INT;
1758         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1759
1760         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1761         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1762 #endif
1763 }
1764
1765 static int tegra_dc_init(struct tegra_dc *dc)
1766 {
1767         int i;
1768         int int_enable;
1769
1770         tegra_dc_io_start(dc);
1771         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1772         if (dc->ndev->id == 0) {
1773                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1774                                       TEGRA_MC_PRIO_MED);
1775                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1776                                       TEGRA_MC_PRIO_MED);
1777                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1778                                       TEGRA_MC_PRIO_MED);
1779 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1780                 /* only present on Tegra2 and 3 */
1781                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1782                                       TEGRA_MC_PRIO_MED);
1783 #endif
1784                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1785                                       TEGRA_MC_PRIO_HIGH);
1786         } else if (dc->ndev->id == 1) {
1787                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1788                                       TEGRA_MC_PRIO_MED);
1789                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1790                                       TEGRA_MC_PRIO_MED);
1791                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1792                                       TEGRA_MC_PRIO_MED);
1793 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1794                 /* only present on Tegra2 and 3 */
1795                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1796                                       TEGRA_MC_PRIO_MED);
1797 #endif
1798                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1799                                       TEGRA_MC_PRIO_HIGH);
1800         }
1801         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1802                         DC_CMD_CONT_SYNCPT_VSYNC);
1803
1804         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1805         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1806         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1807         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1808 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1809         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1810 #endif
1811         /* enable interrupts for vblank, frame_end and underflows */
1812         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
1813         /* for panels with one-shot mode enable tearing effect interrupt */
1814         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1815                 int_enable |= MSF_INT;
1816
1817         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1818         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
1819         tegra_dc_init_vpulse2_int(dc);
1820
1821         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1822
1823 #ifdef CONFIG_TEGRA_DC_CMU
1824         if (dc->pdata->cmu)
1825                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1826         else
1827                 _tegra_dc_update_cmu(dc, &default_cmu);
1828 #endif
1829         tegra_dc_set_color_control(dc);
1830         for (i = 0; i < DC_N_WINDOWS; i++) {
1831                 struct tegra_dc_win *win = &dc->windows[i];
1832                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1833                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1834                 tegra_dc_set_csc(dc, &win->csc);
1835                 tegra_dc_set_lut(dc, win);
1836                 tegra_dc_set_scaling_filter(dc);
1837         }
1838
1839 #ifdef CONFIG_TEGRA_DC_WIN_H
1840         /* Window H is set to window mode by default for t14x. */
1841         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
1842                         DC_DISP_BLEND_CURSOR_CONTROL);
1843 #endif
1844
1845         for (i = 0; i < dc->n_windows; i++) {
1846                 u32 syncpt = get_syncpt(dc, i);
1847
1848                 dc->syncpt[i].id = syncpt;
1849
1850                 dc->syncpt[i].min = dc->syncpt[i].max =
1851                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1852         }
1853
1854         trace_display_mode(dc, &dc->mode);
1855
1856         if (dc->mode.pclk) {
1857                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1858                         tegra_dc_io_end(dc);
1859                         return -EINVAL;
1860                 }
1861         }
1862
1863         /* Initialize SD AFTER the modeset.
1864            nvsd_init handles the sd_settings = NULL case. */
1865         nvsd_init(dc, dc->out->sd_settings);
1866
1867         tegra_dc_io_end(dc);
1868
1869         return 0;
1870 }
1871
1872 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1873 {
1874         int failed_init = 0;
1875
1876         tegra_dc_unpowergate_locked(dc);
1877
1878         if (dc->out->enable)
1879                 dc->out->enable(&dc->ndev->dev);
1880
1881         tegra_dc_setup_clk(dc, dc->clk);
1882         tegra_dc_clk_enable(dc);
1883         tegra_dc_io_start(dc);
1884
1885         tegra_dc_power_on(dc);
1886
1887         /* do not accept interrupts during initialization */
1888         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1889
1890         enable_dc_irq(dc);
1891
1892         failed_init = tegra_dc_init(dc);
1893         if (failed_init) {
1894                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1895                 disable_irq_nosync(dc->irq);
1896                 tegra_dc_clear_bandwidth(dc);
1897                 tegra_dc_clk_disable(dc);
1898                 if (dc->out && dc->out->disable)
1899                         dc->out->disable();
1900                 tegra_dc_io_end(dc);
1901                 return false;
1902         }
1903
1904         if (dc->out_ops && dc->out_ops->enable)
1905                 dc->out_ops->enable(dc);
1906
1907         /* force a full blending update */
1908         dc->blend.z[0] = -1;
1909
1910         tegra_dc_ext_enable(dc->ext);
1911
1912         trace_display_enable(dc);
1913
1914         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1915         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1916
1917         if (dc->out->postpoweron)
1918                 dc->out->postpoweron();
1919
1920         tegra_dc_io_end(dc);
1921         return true;
1922 }
1923
1924 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1925 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1926 {
1927         bool ret = true;
1928
1929         if (dc->out->enable)
1930                 dc->out->enable(&dc->ndev->dev);
1931
1932         tegra_dc_setup_clk(dc, dc->clk);
1933         tegra_dc_clk_enable(dc);
1934
1935         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1936                 mutex_lock(&tegra_dcs[1]->lock);
1937                 disable_irq_nosync(tegra_dcs[1]->irq);
1938         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1939                 mutex_lock(&tegra_dcs[0]->lock);
1940                 disable_irq_nosync(tegra_dcs[0]->irq);
1941         }
1942
1943         msleep(5);
1944         tegra_periph_reset_assert(dc->clk);
1945         msleep(2);
1946         if (tegra_platform_is_silicon()) {
1947                 tegra_periph_reset_deassert(dc->clk);
1948                 msleep(1);
1949         }
1950
1951         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1952                 enable_dc_irq(tegra_dcs[1]);
1953                 mutex_unlock(&tegra_dcs[1]->lock);
1954         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1955                 enable_dc_irq(tegra_dcs[0]);
1956                 mutex_unlock(&tegra_dcs[0]->lock);
1957         }
1958
1959         enable_dc_irq(dc);
1960
1961         if (tegra_dc_init(dc)) {
1962                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1963                 ret = false;
1964         }
1965
1966         if (dc->out_ops && dc->out_ops->enable)
1967                 dc->out_ops->enable(dc);
1968
1969         if (dc->out->postpoweron)
1970                 dc->out->postpoweron();
1971
1972         /* force a full blending update */
1973         dc->blend.z[0] = -1;
1974
1975         tegra_dc_ext_enable(dc->ext);
1976
1977         if (!ret) {
1978                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1979                 _tegra_dc_controller_disable(dc);
1980         }
1981
1982         trace_display_reset(dc);
1983         return ret;
1984 }
1985 #endif
1986
1987 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1988 {
1989         if (dc->mode.pclk == 0) {
1990                 switch (dc->out->type) {
1991                 case TEGRA_DC_OUT_HDMI:
1992                 /* DC enable called but no videomode is loaded.
1993                      Check if HDMI is connected, then set fallback mdoe */
1994                 if (tegra_dc_hpd(dc)) {
1995                         return tegra_dc_set_fb_mode(dc,
1996                                         &tegra_dc_hdmi_fallback_mode, 0);
1997                 } else
1998                         return false;
1999
2000                 break;
2001
2002                 /* Do nothing for other outputs for now */
2003                 case TEGRA_DC_OUT_RGB:
2004
2005                 case TEGRA_DC_OUT_DSI:
2006
2007                 default:
2008                         return false;
2009                 }
2010         }
2011
2012         return false;
2013 }
2014
2015 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2016 {
2017         return _tegra_dc_set_default_videomode(dc);
2018 }
2019
2020 static bool _tegra_dc_enable(struct tegra_dc *dc)
2021 {
2022         if (dc->mode.pclk == 0)
2023                 return false;
2024
2025         if (!dc->out)
2026                 return false;
2027
2028         if (dc->enabled)
2029                 return true;
2030
2031         pm_runtime_get_sync(&dc->ndev->dev);
2032
2033         if (!_tegra_dc_controller_enable(dc)) {
2034                 pm_runtime_put_sync(&dc->ndev->dev);
2035                 return false;
2036         }
2037
2038         return true;
2039 }
2040
2041 void tegra_dc_enable(struct tegra_dc *dc)
2042 {
2043         mutex_lock(&dc->lock);
2044
2045         if (!dc->enabled)
2046                 dc->enabled = _tegra_dc_enable(dc);
2047
2048         mutex_unlock(&dc->lock);
2049         trace_display_mode(dc, &dc->mode);
2050 }
2051
2052 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2053 {
2054         unsigned i;
2055
2056         tegra_dc_hold_dc_out(dc);
2057
2058         if (dc->out && dc->out->prepoweroff)
2059                 dc->out->prepoweroff();
2060
2061         if (dc->out_ops && dc->out_ops->disable)
2062                 dc->out_ops->disable(dc);
2063
2064         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2065
2066         disable_irq_nosync(dc->irq);
2067
2068         tegra_dc_clear_bandwidth(dc);
2069
2070         if (dc->out && dc->out->disable)
2071                 dc->out->disable();
2072
2073         for (i = 0; i < dc->n_windows; i++) {
2074                 struct tegra_dc_win *w = &dc->windows[i];
2075
2076                 /* reset window bandwidth */
2077                 w->bandwidth = 0;
2078                 w->new_bandwidth = 0;
2079
2080                 /* disable windows */
2081                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2082
2083                 /* flush any pending syncpt waits */
2084                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2085                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2086                                 dc->syncpt[i].min, dc->syncpt[i].max);
2087                         dc->syncpt[i].min++;
2088                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2089                 }
2090         }
2091         trace_display_disable(dc);
2092
2093         tegra_dc_clk_disable(dc);
2094         tegra_dc_release_dc_out(dc);
2095 }
2096
2097 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2098 {
2099 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2100         u32 val;
2101         if (dc->enabled)  {
2102                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2103                 if (enable)
2104                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2105                 else
2106                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2107                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2108         }
2109 #endif
2110 }
2111
2112 bool tegra_dc_stats_get(struct tegra_dc *dc)
2113 {
2114 #if 0 /* right now it is always enabled */
2115         u32 val;
2116         bool res;
2117
2118         if (dc->enabled)  {
2119                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2120                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2121         } else {
2122                 res = false;
2123         }
2124
2125         return res;
2126 #endif
2127         return true;
2128 }
2129
2130 /* make the screen blank by disabling all windows */
2131 void tegra_dc_blank(struct tegra_dc *dc)
2132 {
2133         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2134         unsigned i;
2135
2136         for (i = 0; i < DC_N_WINDOWS; i++) {
2137                 dcwins[i] = tegra_dc_get_window(dc, i);
2138                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2139         }
2140
2141         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2142         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2143 }
2144
2145 static void _tegra_dc_disable(struct tegra_dc *dc)
2146 {
2147         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2148                 mutex_lock(&dc->one_shot_lock);
2149                 cancel_delayed_work_sync(&dc->one_shot_work);
2150         }
2151
2152         tegra_dc_io_start(dc);
2153         _tegra_dc_controller_disable(dc);
2154         tegra_dc_io_end(dc);
2155
2156         tegra_dc_powergate_locked(dc);
2157
2158         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2159                 mutex_unlock(&dc->one_shot_lock);
2160         pm_runtime_put(&dc->ndev->dev);
2161
2162         /*
2163          * We will need to reinitialize the display the next time panel
2164          * is enabled.
2165          */
2166         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2167 }
2168
2169 void tegra_dc_disable(struct tegra_dc *dc)
2170 {
2171         tegra_dc_ext_disable(dc->ext);
2172
2173         /* it's important that new underflow work isn't scheduled before the
2174          * lock is acquired. */
2175         cancel_delayed_work_sync(&dc->underflow_work);
2176
2177         mutex_lock(&dc->lock);
2178
2179         if (dc->enabled) {
2180                 dc->enabled = false;
2181
2182                 if (!dc->suspended)
2183                         _tegra_dc_disable(dc);
2184         }
2185
2186 #ifdef CONFIG_SWITCH
2187         switch_set_state(&dc->modeset_switch, 0);
2188 #endif
2189
2190         mutex_unlock(&dc->lock);
2191         synchronize_irq(dc->irq);
2192         trace_display_mode(dc, &dc->mode);
2193 }
2194
2195 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2196 static void tegra_dc_reset_worker(struct work_struct *work)
2197 {
2198         struct tegra_dc *dc =
2199                 container_of(work, struct tegra_dc, reset_work);
2200
2201         unsigned long val = 0;
2202
2203         mutex_lock(&shared_lock);
2204
2205         dev_warn(&dc->ndev->dev,
2206                 "overlay stuck in underflow state.  resetting.\n");
2207
2208         tegra_dc_ext_disable(dc->ext);
2209
2210         mutex_lock(&dc->lock);
2211
2212         if (dc->enabled == false)
2213                 goto unlock;
2214
2215         dc->enabled = false;
2216
2217         /*
2218          * off host read bus
2219          */
2220         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2221         val &= ~(0x00000100);
2222         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2223
2224         /*
2225          * set DC to STOP mode
2226          */
2227         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2228
2229         msleep(10);
2230
2231         _tegra_dc_controller_disable(dc);
2232
2233         /* _tegra_dc_controller_reset_enable deasserts reset */
2234         _tegra_dc_controller_reset_enable(dc);
2235
2236         dc->enabled = true;
2237
2238         /* reopen host read bus */
2239         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2240         val &= ~(0x00000100);
2241         val |= 0x100;
2242         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2243
2244 unlock:
2245         mutex_unlock(&dc->lock);
2246         mutex_unlock(&shared_lock);
2247         trace_display_reset(dc);
2248 }
2249 #endif
2250
2251 static void tegra_dc_underflow_worker(struct work_struct *work)
2252 {
2253         struct tegra_dc *dc = container_of(
2254                 to_delayed_work(work), struct tegra_dc, underflow_work);
2255
2256         mutex_lock(&dc->lock);
2257         tegra_dc_io_start(dc);
2258         tegra_dc_hold_dc_out(dc);
2259
2260         if (dc->enabled) {
2261                 tegra_dc_underflow_handler(dc);
2262         }
2263         tegra_dc_release_dc_out(dc);
2264         tegra_dc_io_end(dc);
2265         mutex_unlock(&dc->lock);
2266 }
2267
2268 #ifdef CONFIG_SWITCH
2269 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2270 {
2271         struct tegra_dc *dc =
2272                 container_of(sdev, struct tegra_dc, modeset_switch);
2273
2274         if (!sdev->state)
2275                 return sprintf(buf, "offline\n");
2276
2277         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2278 }
2279 #endif
2280
2281 static void tegra_dc_add_modes(struct tegra_dc *dc)
2282 {
2283         struct fb_monspecs specs;
2284         int i;
2285
2286         memset(&specs, 0, sizeof(specs));
2287         specs.max_x = dc->mode.h_active * 1000;
2288         specs.max_y = dc->mode.v_active * 1000;
2289         specs.modedb_len = dc->out->n_modes;
2290         specs.modedb = kzalloc(specs.modedb_len *
2291                 sizeof(struct fb_videomode), GFP_KERNEL);
2292         for (i = 0; i < dc->out->n_modes; i++)
2293                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2294                         &dc->out->modes[i]);
2295         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2296         kfree(specs.modedb);
2297 }
2298
2299 static int tegra_dc_probe(struct platform_device *ndev)
2300 {
2301         struct tegra_dc *dc;
2302         struct tegra_dc_mode *mode;
2303         struct clk *clk;
2304 #ifndef CONFIG_TEGRA_ISOMGR
2305         struct clk *emc_clk;
2306 #endif
2307         int isomgr_client_id = -1;
2308         struct resource *res;
2309         struct resource *base_res;
2310         struct resource *fb_mem = NULL;
2311         int ret = 0;
2312         void __iomem *base;
2313         int irq;
2314         int i;
2315
2316         if (!ndev->dev.platform_data) {
2317                 dev_err(&ndev->dev, "no platform data\n");
2318                 return -ENOENT;
2319         }
2320
2321         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2322         if (!dc) {
2323                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2324                 return -ENOMEM;
2325         }
2326
2327         irq = platform_get_irq_byname(ndev, "irq");
2328         if (irq <= 0) {
2329                 dev_err(&ndev->dev, "no irq\n");
2330                 ret = -ENOENT;
2331                 goto err_free;
2332         }
2333
2334         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2335         if (!res) {
2336                 dev_err(&ndev->dev, "no mem resource\n");
2337                 ret = -ENOENT;
2338                 goto err_free;
2339         }
2340
2341         base_res = request_mem_region(res->start, resource_size(res),
2342                 ndev->name);
2343         if (!base_res) {
2344                 dev_err(&ndev->dev, "request_mem_region failed\n");
2345                 ret = -EBUSY;
2346                 goto err_free;
2347         }
2348
2349         base = ioremap(res->start, resource_size(res));
2350         if (!base) {
2351                 dev_err(&ndev->dev, "registers can't be mapped\n");
2352                 ret = -EBUSY;
2353                 goto err_release_resource_reg;
2354         }
2355         if (TEGRA_DISPLAY_BASE == res->start) {
2356                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2357                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2358                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2359                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2360 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2361                 dc->win_syncpt[3] = NVSYNCPT_DISP0_D;
2362                 dc->win_syncpt[4] = NVSYNCPT_DISP0_H;
2363 #endif
2364                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2365                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
2366         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2367                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2368                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2369                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2370                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2371 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2372                 dc->win_syncpt[4] = NVSYNCPT_DISP1_H;
2373 #endif
2374                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2375                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
2376         } else {
2377                 dev_err(&ndev->dev,
2378                         "Unknown base address %#08x: unable to assign syncpt\n",
2379                         res->start);
2380         }
2381
2382
2383         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2384
2385         clk = clk_get(&ndev->dev, NULL);
2386         if (IS_ERR_OR_NULL(clk)) {
2387                 dev_err(&ndev->dev, "can't get clock\n");
2388                 ret = -ENOENT;
2389                 goto err_iounmap_reg;
2390         }
2391
2392         dc->clk = clk;
2393         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2394         /* Initialize one shot work delay, it will be assigned by dsi
2395          * according to refresh rate later. */
2396         dc->one_shot_delay_ms = 40;
2397
2398         dc->base_res = base_res;
2399         dc->base = base;
2400         dc->irq = irq;
2401         dc->ndev = ndev;
2402         dc->pdata = ndev->dev.platform_data;
2403
2404         dc->bw_kbps = 0;
2405
2406         mutex_init(&dc->lock);
2407         mutex_init(&dc->one_shot_lock);
2408         init_completion(&dc->frame_end_complete);
2409         init_waitqueue_head(&dc->wq);
2410         init_waitqueue_head(&dc->timestamp_wq);
2411 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2412         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2413 #endif
2414         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2415         dc->vblank_ref_count = 0;
2416 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2417         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2418 #endif
2419         dc->vpulse2_ref_count = 0;
2420         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2421         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2422
2423         tegra_dc_init_lut_defaults(&dc->fb_lut);
2424
2425         dc->n_windows = DC_N_WINDOWS;
2426         for (i = 0; i < dc->n_windows; i++) {
2427                 struct tegra_dc_win *win = &dc->windows[i];
2428                 win->idx = i;
2429                 win->dc = dc;
2430                 tegra_dc_init_csc_defaults(&win->csc);
2431                 tegra_dc_init_lut_defaults(&win->lut);
2432         }
2433
2434         ret = tegra_dc_set(dc, ndev->id);
2435         if (ret < 0) {
2436                 dev_err(&ndev->dev, "can't add dc\n");
2437                 goto err_put_clk;
2438         }
2439
2440         platform_set_drvdata(ndev, dc);
2441
2442 #ifdef CONFIG_SWITCH
2443         dc->modeset_switch.name = dev_name(&ndev->dev);
2444         dc->modeset_switch.state = 0;
2445         dc->modeset_switch.print_state = switch_modeset_print_mode;
2446         ret = switch_dev_register(&dc->modeset_switch);
2447         if (ret < 0)
2448                 dev_err(&ndev->dev, "failed to register switch driver\n");
2449 #endif
2450
2451         tegra_dc_feature_register(dc);
2452
2453         if (dc->pdata->default_out)
2454                 tegra_dc_set_out(dc, dc->pdata->default_out);
2455         else
2456                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2457         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2458
2459 #ifdef CONFIG_TEGRA_ISOMGR
2460         if (isomgr_client_id == -1) {
2461                 dc->isomgr_handle = NULL;
2462         } else {
2463                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
2464                         tegra_dc_calc_min_bandwidth(dc),
2465                         tegra_dc_bandwidth_renegotiate, dc);
2466                 if (IS_ERR(dc->isomgr_handle)) {
2467                         dev_err(&dc->ndev->dev,
2468                                 "could not register isomgr. err=%ld\n",
2469                                 PTR_ERR(dc->isomgr_handle));
2470                         ret = -ENOENT;
2471                         goto err_put_clk;
2472                 }
2473         }
2474 #else
2475         /*
2476          * The emc is a shared clock, it will be set based on
2477          * the requirements for each user on the bus.
2478          */
2479         emc_clk = clk_get(&ndev->dev, "emc");
2480         if (IS_ERR_OR_NULL(emc_clk)) {
2481                 dev_err(&ndev->dev, "can't get emc clock\n");
2482                 ret = -ENOENT;
2483                 goto err_put_clk;
2484         }
2485         dc->emc_clk = emc_clk;
2486 #endif
2487
2488         dc->ext = tegra_dc_ext_register(ndev, dc);
2489         if (IS_ERR_OR_NULL(dc->ext)) {
2490                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2491                 dc->ext = NULL;
2492         }
2493
2494         /* interrupt handler must be registered before tegra_fb_register() */
2495         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2496                         dev_name(&ndev->dev), dc)) {
2497                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2498                 ret = -EBUSY;
2499                 goto err_disable_dc;
2500         }
2501         disable_dc_irq(dc);
2502
2503         tegra_pd_add_device(&tegra_mc_chain_a, &ndev->dev);
2504         pm_runtime_use_autosuspend(&ndev->dev);
2505         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
2506         pm_runtime_enable(&ndev->dev);
2507
2508         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2509                 _tegra_dc_set_default_videomode(dc);
2510                 dc->enabled = _tegra_dc_enable(dc);
2511         }
2512
2513         tegra_dc_create_debugfs(dc);
2514
2515         dev_info(&ndev->dev, "probed\n");
2516
2517         if (dc->pdata->fb) {
2518                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2519                         unsigned long fmt;
2520                         tegra_dc_writel(dc,
2521                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2522                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2523
2524                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2525                         dc->pdata->fb->bits_per_pixel =
2526                                 tegra_dc_fmt_bpp(fmt);
2527                 }
2528
2529                 mode = tegra_dc_get_override_mode(dc);
2530                 if (mode) {
2531                         dc->pdata->fb->xres = mode->h_active;
2532                         dc->pdata->fb->yres = mode->v_active;
2533                 }
2534
2535                 tegra_dc_io_start(dc);
2536                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2537                 tegra_dc_io_end(dc);
2538                 if (IS_ERR_OR_NULL(dc->fb)) {
2539                         dc->fb = NULL;
2540                         dev_err(&ndev->dev, "failed to register fb\n");
2541                         goto err_remove_debugfs;
2542                 }
2543         }
2544
2545         if (dc->out && dc->out->n_modes)
2546                 tegra_dc_add_modes(dc);
2547
2548         if (dc->out && dc->out->hotplug_init)
2549                 dc->out->hotplug_init(&ndev->dev);
2550
2551         if (dc->out_ops && dc->out_ops->detect)
2552                 dc->out_ops->detect(dc);
2553         else
2554                 dc->connected = true;
2555
2556         /* Powergate display module when it's unconnected. */
2557         if (!tegra_dc_get_connected(dc))
2558                 tegra_dc_powergate_locked(dc);
2559
2560         tegra_dc_create_sysfs(&dc->ndev->dev);
2561
2562         return 0;
2563
2564 err_remove_debugfs:
2565         tegra_dc_remove_debugfs(dc);
2566         free_irq(irq, dc);
2567 err_disable_dc:
2568         if (dc->ext) {
2569                 tegra_dc_ext_disable(dc->ext);
2570                 tegra_dc_ext_unregister(dc->ext);
2571         }
2572         mutex_lock(&dc->lock);
2573         if (dc->enabled)
2574                 _tegra_dc_disable(dc);
2575         dc->enabled = false;
2576         mutex_unlock(&dc->lock);
2577 #ifdef CONFIG_SWITCH
2578         switch_dev_unregister(&dc->modeset_switch);
2579 #endif
2580 #ifdef CONFIG_TEGRA_ISOMGR
2581         tegra_isomgr_unregister(dc->isomgr_handle);
2582 #else
2583         clk_put(emc_clk);
2584 #endif
2585 err_put_clk:
2586         clk_put(clk);
2587 err_iounmap_reg:
2588         iounmap(base);
2589         if (fb_mem)
2590                 release_resource(fb_mem);
2591 err_release_resource_reg:
2592         release_resource(base_res);
2593 err_free:
2594         kfree(dc);
2595
2596         return ret;
2597 }
2598
2599 static int tegra_dc_remove(struct platform_device *ndev)
2600 {
2601         struct tegra_dc *dc = platform_get_drvdata(ndev);
2602
2603         tegra_dc_remove_sysfs(&dc->ndev->dev);
2604         tegra_dc_remove_debugfs(dc);
2605
2606         if (dc->fb) {
2607                 tegra_fb_unregister(dc->fb);
2608                 if (dc->fb_mem)
2609                         release_resource(dc->fb_mem);
2610         }
2611
2612         tegra_dc_ext_disable(dc->ext);
2613
2614         if (dc->ext)
2615                 tegra_dc_ext_unregister(dc->ext);
2616
2617         mutex_lock(&dc->lock);
2618         if (dc->enabled)
2619                 _tegra_dc_disable(dc);
2620         dc->enabled = false;
2621         mutex_unlock(&dc->lock);
2622         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2623
2624 #ifdef CONFIG_SWITCH
2625         switch_dev_unregister(&dc->modeset_switch);
2626 #endif
2627         free_irq(dc->irq, dc);
2628 #ifdef CONFIG_TEGRA_ISOMGR
2629         if (dc->isomgr_handle) {
2630                 tegra_isomgr_unregister(dc->isomgr_handle);
2631                 dc->isomgr_handle = NULL;
2632         }
2633 #else
2634         clk_put(dc->emc_clk);
2635 #endif
2636         clk_put(dc->clk);
2637         iounmap(dc->base);
2638         if (dc->fb_mem)
2639                 release_resource(dc->base_res);
2640         kfree(dc);
2641         tegra_dc_set(NULL, ndev->id);
2642
2643         return 0;
2644 }
2645
2646 #ifdef CONFIG_PM
2647 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2648 {
2649         struct tegra_dc *dc = platform_get_drvdata(ndev);
2650
2651         trace_display_suspend(dc);
2652         dev_info(&ndev->dev, "suspend\n");
2653
2654         tegra_dc_ext_disable(dc->ext);
2655
2656         mutex_lock(&dc->lock);
2657         tegra_dc_io_start(dc);
2658
2659         if (dc->out_ops && dc->out_ops->suspend)
2660                 dc->out_ops->suspend(dc);
2661
2662         if (dc->enabled) {
2663                 _tegra_dc_disable(dc);
2664
2665                 dc->suspended = true;
2666         }
2667
2668         if (dc->out && dc->out->postsuspend) {
2669                 dc->out->postsuspend();
2670                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2671                         /*
2672                          * avoid resume event due to voltage falling
2673                          */
2674                         msleep(100);
2675         }
2676
2677         tegra_dc_io_end(dc);
2678         mutex_unlock(&dc->lock);
2679         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2680
2681         return 0;
2682 }
2683
2684 static int tegra_dc_resume(struct platform_device *ndev)
2685 {
2686         struct tegra_dc *dc = platform_get_drvdata(ndev);
2687
2688         trace_display_resume(dc);
2689         dev_info(&ndev->dev, "resume\n");
2690
2691         mutex_lock(&dc->lock);
2692         dc->suspended = false;
2693
2694         /* To pan the fb on resume */
2695         tegra_fb_pan_display_reset(dc->fb);
2696
2697         if (dc->enabled) {
2698                 dc->enabled = false;
2699                 _tegra_dc_set_default_videomode(dc);
2700                 dc->enabled = _tegra_dc_enable(dc);
2701         }
2702
2703         if (dc->out && dc->out->hotplug_init)
2704                 dc->out->hotplug_init(&ndev->dev);
2705
2706         if (dc->out_ops && dc->out_ops->resume)
2707                 dc->out_ops->resume(dc);
2708         mutex_unlock(&dc->lock);
2709
2710         return 0;
2711 }
2712
2713 #endif /* CONFIG_PM */
2714
2715 static void tegra_dc_shutdown(struct platform_device *ndev)
2716 {
2717         struct tegra_dc *dc = platform_get_drvdata(ndev);
2718
2719         if (!dc || !dc->enabled)
2720                 return;
2721
2722         /* Hack: no windows blanking for simulation to save shutdown time */
2723         if (!tegra_platform_is_linsim())
2724                 tegra_dc_blank(dc);
2725         tegra_dc_disable(dc);
2726 }
2727
2728 extern int suspend_set(const char *val, struct kernel_param *kp)
2729 {
2730         if (!strcmp(val, "dump"))
2731                 dump_regs(tegra_dcs[0]);
2732 #ifdef CONFIG_PM
2733         else if (!strcmp(val, "suspend"))
2734                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2735         else if (!strcmp(val, "resume"))
2736                 tegra_dc_resume(tegra_dcs[0]->ndev);
2737 #endif
2738
2739         return 0;
2740 }
2741
2742 extern int suspend_get(char *buffer, struct kernel_param *kp)
2743 {
2744         return 0;
2745 }
2746
2747 int suspend;
2748
2749 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2750
2751 struct platform_driver tegra_dc_driver = {
2752         .driver = {
2753                 .name = "tegradc",
2754                 .owner = THIS_MODULE,
2755         },
2756         .probe = tegra_dc_probe,
2757         .remove = tegra_dc_remove,
2758 #ifdef CONFIG_PM
2759         .suspend = tegra_dc_suspend,
2760         .resume = tegra_dc_resume,
2761 #endif
2762         .shutdown = tegra_dc_shutdown,
2763 };
2764
2765 #ifndef MODULE
2766 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2767 {
2768         int i, params[11];
2769         char *p;
2770
2771         for (i = 0; i < ARRAY_SIZE(params); i++) {
2772                 if ((p = strsep(&options, ",")) != NULL) {
2773                         if (*p)
2774                                 params[i] = simple_strtoul(p, &p, 10);
2775                 } else
2776                         return -EINVAL;
2777         }
2778
2779         if ((mode->pclk = params[0]) == 0)
2780                 return -EINVAL;
2781
2782         mode->h_active      = params[1];
2783         mode->v_active      = params[2];
2784         mode->h_ref_to_sync = params[3];
2785         mode->v_ref_to_sync = params[4];
2786         mode->h_sync_width  = params[5];
2787         mode->v_sync_width  = params[6];
2788         mode->h_back_porch  = params[7];
2789         mode->v_back_porch  = params[8];
2790         mode->h_front_porch = params[9];
2791         mode->v_front_porch = params[10];
2792
2793         return 0;
2794 }
2795
2796 static int __init tegra_dc_mode_override(char *str)
2797 {
2798         char *p = str, *options;
2799
2800         if (!p || !*p)
2801                 return -EINVAL;
2802
2803         p = strstr(str, "hdmi:");
2804         if (p) {
2805                 p += 5;
2806                 options = strsep(&p, ";");
2807                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2808                         return -EINVAL;
2809         }
2810
2811         p = strstr(str, "rgb:");
2812         if (p) {
2813                 p += 4;
2814                 options = strsep(&p, ";");
2815                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2816                         return -EINVAL;
2817         }
2818
2819         p = strstr(str, "dsi:");
2820         if (p) {
2821                 p += 4;
2822                 options = strsep(&p, ";");
2823                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2824                         return -EINVAL;
2825         }
2826
2827         return 0;
2828 }
2829
2830 __setup("disp_params=", tegra_dc_mode_override);
2831 #endif
2832
2833 static int __init tegra_dc_module_init(void)
2834 {
2835         int ret = tegra_dc_ext_module_init();
2836         if (ret)
2837                 return ret;
2838         return platform_driver_register(&tegra_dc_driver);
2839 }
2840
2841 static void __exit tegra_dc_module_exit(void)
2842 {
2843         platform_driver_unregister(&tegra_dc_driver);
2844         tegra_dc_ext_module_exit();
2845 }
2846
2847 module_exit(tegra_dc_module_exit);
2848 module_init(tegra_dc_module_init);