video: tegra: dc: Use ref-count to mask vblank interrupt.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (C) 2010-2012 NVIDIA Corporation
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <video/tegrafb.h>
38 #include <drm/drm_fixed.h>
39 #ifdef CONFIG_SWITCH
40 #include <linux/switch.h>
41 #endif
42
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "host1x/host1x_syncpt.h"
56 #include "nvsd.h"
57
58 #define TEGRA_CRC_LATCHED_DELAY         34
59
60 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
61 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
62
63 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
64 #define ALL_UF_INT (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)
65 #else
66 /* ignore underflows when on simulation and fpga platform */
67 #define ALL_UF_INT (0)
68 #endif
69
70 static int no_vsync;
71 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
72         .refresh = 60,
73         .xres = 640,
74         .yres = 480,
75         .pixclock = KHZ2PICOS(25200),
76         .hsync_len = 96,        /* h_sync_width */
77         .vsync_len = 2,         /* v_sync_width */
78         .left_margin = 48,      /* h_back_porch */
79         .upper_margin = 33,     /* v_back_porch */
80         .right_margin = 16,     /* h_front_porch */
81         .lower_margin = 10,     /* v_front_porch */
82         .vmode = 0,
83         .sync = 0,
84 };
85
86 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
87
88 module_param_named(no_vsync, no_vsync, int, S_IRUGO | S_IWUSR);
89
90 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
91
92 DEFINE_MUTEX(tegra_dc_lock);
93 DEFINE_MUTEX(shared_lock);
94
95 static const struct {
96         bool h;
97         bool v;
98 } can_filter[] = {
99         /* Window A has no filtering */
100         { false, false },
101         /* Window B has both H and V filtering */
102         { true,  true  },
103         /* Window C has only H filtering */
104         { false, true  },
105 };
106
107 #ifdef CONFIG_TEGRA_DC_CMU
108 static struct tegra_dc_cmu default_cmu = {
109         /* lut1 maps sRGB to linear space. */
110         {
111                 0,    1,    2,    4,    5,    6,    7,    9,
112                 10,   11,   12,   14,   15,   16,   18,   20,
113                 21,   23,   25,   27,   29,   31,   33,   35,
114                 37,   40,   42,   45,   48,   50,   53,   56,
115                 59,   62,   66,   69,   72,   76,   79,   83,
116                 87,   91,   95,   99,   103,  107,  112,  116,
117                 121,  126,  131,  136,  141,  146,  151,  156,
118                 162,  168,  173,  179,  185,  191,  197,  204,
119                 210,  216,  223,  230,  237,  244,  251,  258,
120                 265,  273,  280,  288,  296,  304,  312,  320,
121                 329,  337,  346,  354,  363,  372,  381,  390,
122                 400,  409,  419,  428,  438,  448,  458,  469,
123                 479,  490,  500,  511,  522,  533,  544,  555,
124                 567,  578,  590,  602,  614,  626,  639,  651,
125                 664,  676,  689,  702,  715,  728,  742,  755,
126                 769,  783,  797,  811,  825,  840,  854,  869,
127                 884,  899,  914,  929,  945,  960,  976,  992,
128                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
129                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
130                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
131                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
132                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
133                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
134                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
135                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
136                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
137                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
138                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
139                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
140                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
141                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
142                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
143         },
144         /* csc */
145         {
146                 0x100, 0x0,   0x0,
147                 0x0,   0x100, 0x0,
148                 0x0,   0x0,   0x100,
149         },
150         /* lut2 maps linear space to sRGB*/
151         {
152                 0,    1,    2,    2,    3,    4,    5,    6,
153                 6,    7,    8,    9,    10,   10,   11,   12,
154                 13,   13,   14,   15,   15,   16,   16,   17,
155                 18,   18,   19,   19,   20,   20,   21,   21,
156                 22,   22,   23,   23,   23,   24,   24,   25,
157                 25,   25,   26,   26,   27,   27,   27,   28,
158                 28,   29,   29,   29,   30,   30,   30,   31,
159                 31,   31,   32,   32,   32,   33,   33,   33,
160                 34,   34,   34,   34,   35,   35,   35,   36,
161                 36,   36,   37,   37,   37,   37,   38,   38,
162                 38,   38,   39,   39,   39,   40,   40,   40,
163                 40,   41,   41,   41,   41,   42,   42,   42,
164                 42,   43,   43,   43,   43,   43,   44,   44,
165                 44,   44,   45,   45,   45,   45,   46,   46,
166                 46,   46,   46,   47,   47,   47,   47,   48,
167                 48,   48,   48,   48,   49,   49,   49,   49,
168                 49,   50,   50,   50,   50,   50,   51,   51,
169                 51,   51,   51,   52,   52,   52,   52,   52,
170                 53,   53,   53,   53,   53,   54,   54,   54,
171                 54,   54,   55,   55,   55,   55,   55,   55,
172                 56,   56,   56,   56,   56,   57,   57,   57,
173                 57,   57,   57,   58,   58,   58,   58,   58,
174                 58,   59,   59,   59,   59,   59,   59,   60,
175                 60,   60,   60,   60,   60,   61,   61,   61,
176                 61,   61,   61,   62,   62,   62,   62,   62,
177                 62,   63,   63,   63,   63,   63,   63,   64,
178                 64,   64,   64,   64,   64,   64,   65,   65,
179                 65,   65,   65,   65,   66,   66,   66,   66,
180                 66,   66,   66,   67,   67,   67,   67,   67,
181                 67,   67,   68,   68,   68,   68,   68,   68,
182                 68,   69,   69,   69,   69,   69,   69,   69,
183                 70,   70,   70,   70,   70,   70,   70,   71,
184                 71,   71,   71,   71,   71,   71,   72,   72,
185                 72,   72,   72,   72,   72,   72,   73,   73,
186                 73,   73,   73,   73,   73,   74,   74,   74,
187                 74,   74,   74,   74,   74,   75,   75,   75,
188                 75,   75,   75,   75,   75,   76,   76,   76,
189                 76,   76,   76,   76,   77,   77,   77,   77,
190                 77,   77,   77,   77,   78,   78,   78,   78,
191                 78,   78,   78,   78,   78,   79,   79,   79,
192                 79,   79,   79,   79,   79,   80,   80,   80,
193                 80,   80,   80,   80,   80,   81,   81,   81,
194                 81,   81,   81,   81,   81,   81,   82,   82,
195                 82,   82,   82,   82,   82,   82,   83,   83,
196                 83,   83,   83,   83,   83,   83,   83,   84,
197                 84,   84,   84,   84,   84,   84,   84,   84,
198                 85,   85,   85,   85,   85,   85,   85,   85,
199                 85,   86,   86,   86,   86,   86,   86,   86,
200                 86,   86,   87,   87,   87,   87,   87,   87,
201                 87,   87,   87,   88,   88,   88,   88,   88,
202                 88,   88,   88,   88,   88,   89,   89,   89,
203                 89,   89,   89,   89,   89,   89,   90,   90,
204                 90,   90,   90,   90,   90,   90,   90,   90,
205                 91,   91,   91,   91,   91,   91,   91,   91,
206                 91,   91,   92,   92,   92,   92,   92,   92,
207                 92,   92,   92,   92,   93,   93,   93,   93,
208                 93,   93,   93,   93,   93,   93,   94,   94,
209                 94,   94,   94,   94,   94,   94,   94,   94,
210                 95,   95,   95,   95,   95,   95,   95,   95,
211                 95,   95,   96,   96,   96,   96,   96,   96,
212                 96,   96,   96,   96,   96,   97,   97,   97,
213                 97,   97,   97,   97,   97,   97,   97,   98,
214                 98,   98,   98,   98,   98,   98,   98,   98,
215                 98,   98,   99,   99,   99,   99,   99,   99,
216                 99,   100,  101,  101,  102,  103,  103,  104,
217                 105,  105,  106,  107,  107,  108,  109,  109,
218                 110,  111,  111,  112,  113,  113,  114,  115,
219                 115,  116,  116,  117,  118,  118,  119,  119,
220                 120,  120,  121,  122,  122,  123,  123,  124,
221                 124,  125,  126,  126,  127,  127,  128,  128,
222                 129,  129,  130,  130,  131,  131,  132,  132,
223                 133,  133,  134,  134,  135,  135,  136,  136,
224                 137,  137,  138,  138,  139,  139,  140,  140,
225                 141,  141,  142,  142,  143,  143,  144,  144,
226                 145,  145,  145,  146,  146,  147,  147,  148,
227                 148,  149,  149,  150,  150,  150,  151,  151,
228                 152,  152,  153,  153,  153,  154,  154,  155,
229                 155,  156,  156,  156,  157,  157,  158,  158,
230                 158,  159,  159,  160,  160,  160,  161,  161,
231                 162,  162,  162,  163,  163,  164,  164,  164,
232                 165,  165,  166,  166,  166,  167,  167,  167,
233                 168,  168,  169,  169,  169,  170,  170,  170,
234                 171,  171,  172,  172,  172,  173,  173,  173,
235                 174,  174,  174,  175,  175,  176,  176,  176,
236                 177,  177,  177,  178,  178,  178,  179,  179,
237                 179,  180,  180,  180,  181,  181,  182,  182,
238                 182,  183,  183,  183,  184,  184,  184,  185,
239                 185,  185,  186,  186,  186,  187,  187,  187,
240                 188,  188,  188,  189,  189,  189,  189,  190,
241                 190,  190,  191,  191,  191,  192,  192,  192,
242                 193,  193,  193,  194,  194,  194,  195,  195,
243                 195,  196,  196,  196,  196,  197,  197,  197,
244                 198,  198,  198,  199,  199,  199,  200,  200,
245                 200,  200,  201,  201,  201,  202,  202,  202,
246                 202,  203,  203,  203,  204,  204,  204,  205,
247                 205,  205,  205,  206,  206,  206,  207,  207,
248                 207,  207,  208,  208,  208,  209,  209,  209,
249                 209,  210,  210,  210,  211,  211,  211,  211,
250                 212,  212,  212,  213,  213,  213,  213,  214,
251                 214,  214,  214,  215,  215,  215,  216,  216,
252                 216,  216,  217,  217,  217,  217,  218,  218,
253                 218,  219,  219,  219,  219,  220,  220,  220,
254                 220,  221,  221,  221,  221,  222,  222,  222,
255                 223,  223,  223,  223,  224,  224,  224,  224,
256                 225,  225,  225,  225,  226,  226,  226,  226,
257                 227,  227,  227,  227,  228,  228,  228,  228,
258                 229,  229,  229,  229,  230,  230,  230,  230,
259                 231,  231,  231,  231,  232,  232,  232,  232,
260                 233,  233,  233,  233,  234,  234,  234,  234,
261                 235,  235,  235,  235,  236,  236,  236,  236,
262                 237,  237,  237,  237,  238,  238,  238,  238,
263                 239,  239,  239,  239,  240,  240,  240,  240,
264                 240,  241,  241,  241,  241,  242,  242,  242,
265                 242,  243,  243,  243,  243,  244,  244,  244,
266                 244,  244,  245,  245,  245,  245,  246,  246,
267                 246,  246,  247,  247,  247,  247,  247,  248,
268                 248,  248,  248,  249,  249,  249,  249,  249,
269                 250,  250,  250,  250,  251,  251,  251,  251,
270                 251,  252,  252,  252,  252,  253,  253,  253,
271                 253,  253,  254,  254,  254,  254,  255,  255,
272         },
273 };
274 #endif
275
276 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
277 {
278         if (!tegra_is_clk_enabled(dc->clk)) {
279                 clk_enable(dc->clk);
280                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
281         }
282 }
283
284 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
285 {
286         if (tegra_is_clk_enabled(dc->clk)) {
287                 clk_disable(dc->clk);
288                 tegra_dvfs_set_rate(dc->clk, 0);
289         }
290 }
291
292 #define DUMP_REG(a) do {                        \
293         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
294                  #a, a, tegra_dc_readl(dc, a));               \
295         print(data, buff);                                    \
296         } while (0)
297
298 #define print_mode_info(dc, mode) do {                        \
299         trace_printk("%s:Mode settings: "                              \
300                         "ref_to_sync: H = %d V = %d, "                  \
301                         "sync_width: H = %d V = %d, "                   \
302                         "back_porch: H = %d V = %d, "                   \
303                         "active: H = %d V = %d, "                       \
304                         "front_porch: H = %d V = %d, "                  \
305                         "pclk = %d, stereo mode = %d\n",                \
306                         dc->ndev->name,                                 \
307                         mode.h_ref_to_sync, mode.v_ref_to_sync,         \
308                         mode.h_sync_width, mode.v_sync_width,           \
309                         mode.h_back_porch, mode.v_back_porch,           \
310                         mode.h_active, mode.v_active,                   \
311                         mode.h_front_porch, mode.v_front_porch,         \
312                         mode.pclk, mode.stereo_mode);                   \
313         } while (0)
314
315 #define print_underflow_info(dc) do {                 \
316         trace_printk("%s:Underflow stats: underflows : %llu, "      \
317                         "undeflows_a : %llu, "                          \
318                         "underflows_b : %llu, "                         \
319                         "underflows_c : %llu\n",                        \
320                         dc->ndev->name,                                 \
321                         dc->stats.underflows,                           \
322                         dc->stats.underflows_a, dc->stats.underflows_b, \
323                         dc->stats.underflows_c);                        \
324         } while (0)
325
326 static void _dump_regs(struct tegra_dc *dc, void *data,
327                        void (* print)(void *data, const char *str))
328 {
329         int i;
330         char buff[256];
331
332         tegra_dc_io_start(dc);
333         tegra_dc_clk_enable(dc);
334
335         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
336         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
337         DUMP_REG(DC_CMD_SIGNAL_RAISE);
338         DUMP_REG(DC_CMD_INT_STATUS);
339         DUMP_REG(DC_CMD_INT_MASK);
340         DUMP_REG(DC_CMD_INT_ENABLE);
341         DUMP_REG(DC_CMD_INT_TYPE);
342         DUMP_REG(DC_CMD_INT_POLARITY);
343         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
344         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
345         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
346         DUMP_REG(DC_CMD_STATE_ACCESS);
347         DUMP_REG(DC_CMD_STATE_CONTROL);
348         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
349         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
350
351         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
352         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
353         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
354         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
355         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
356         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
357         DUMP_REG(DC_DISP_REF_TO_SYNC);
358         DUMP_REG(DC_DISP_SYNC_WIDTH);
359         DUMP_REG(DC_DISP_BACK_PORCH);
360         DUMP_REG(DC_DISP_DISP_ACTIVE);
361         DUMP_REG(DC_DISP_FRONT_PORCH);
362         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
363         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
364         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
365         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
366         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
367         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
368         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
369         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
370         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
371         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
372         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
373         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
374         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
375         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
376         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
377         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
378         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
379         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
380         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
381         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
382         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
383         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
384         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
385         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
386         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
387         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
388         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
389         DUMP_REG(DC_DISP_M0_CONTROL);
390         DUMP_REG(DC_DISP_M1_CONTROL);
391         DUMP_REG(DC_DISP_DI_CONTROL);
392         DUMP_REG(DC_DISP_PP_CONTROL);
393         DUMP_REG(DC_DISP_PP_SELECT_A);
394         DUMP_REG(DC_DISP_PP_SELECT_B);
395         DUMP_REG(DC_DISP_PP_SELECT_C);
396         DUMP_REG(DC_DISP_PP_SELECT_D);
397         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
398         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
399         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
400         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
401         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
402         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
403         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
404         DUMP_REG(DC_DISP_BORDER_COLOR);
405         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
406         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
407         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
408         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
409         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
410         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
411         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
412         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
413         DUMP_REG(DC_DISP_CURSOR_POSITION);
414         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
415         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
416         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
417         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
418         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
419         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
420         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
421         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
422         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
423         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
424         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
425         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
426         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
427
428
429         for (i = 0; i < 3; i++) {
430                 print(data, "\n");
431                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
432                 print(data, buff);
433
434                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
435                                 DC_CMD_DISPLAY_WINDOW_HEADER);
436                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
437                 DUMP_REG(DC_WIN_WIN_OPTIONS);
438                 DUMP_REG(DC_WIN_BYTE_SWAP);
439                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
440                 DUMP_REG(DC_WIN_COLOR_DEPTH);
441                 DUMP_REG(DC_WIN_POSITION);
442                 DUMP_REG(DC_WIN_SIZE);
443                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
444                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
445                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
446                 DUMP_REG(DC_WIN_DDA_INCREMENT);
447                 DUMP_REG(DC_WIN_LINE_STRIDE);
448 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
449                 DUMP_REG(DC_WIN_BUF_STRIDE);
450                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
451 #endif
452                 DUMP_REG(DC_WIN_BLEND_NOKEY);
453                 DUMP_REG(DC_WIN_BLEND_1WIN);
454                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
455                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
456                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
457                 DUMP_REG(DC_WINBUF_START_ADDR);
458                 DUMP_REG(DC_WINBUF_START_ADDR_U);
459                 DUMP_REG(DC_WINBUF_START_ADDR_V);
460                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
461                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
462                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
463                 DUMP_REG(DC_WIN_CSC_YOF);
464                 DUMP_REG(DC_WIN_CSC_KYRGB);
465                 DUMP_REG(DC_WIN_CSC_KUR);
466                 DUMP_REG(DC_WIN_CSC_KVR);
467                 DUMP_REG(DC_WIN_CSC_KUG);
468                 DUMP_REG(DC_WIN_CSC_KVG);
469                 DUMP_REG(DC_WIN_CSC_KUB);
470                 DUMP_REG(DC_WIN_CSC_KVB);
471         }
472
473         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
474         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
475         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
476         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
477         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
478         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
479         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
480         DUMP_REG(DC_DISP_M1_CONTROL);
481         DUMP_REG(DC_COM_PM1_CONTROL);
482         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
483         DUMP_REG(DC_DISP_SD_CONTROL);
484
485         tegra_dc_clk_disable(dc->clk);
486         tegra_dc_io_end(dc);
487 }
488
489 #undef DUMP_REG
490
491 #ifdef DEBUG
492 static void dump_regs_print(void *data, const char *str)
493 {
494         struct tegra_dc *dc = data;
495         dev_dbg(&dc->ndev->dev, "%s", str);
496 }
497
498 static void dump_regs(struct tegra_dc *dc)
499 {
500         _dump_regs(dc, dc, dump_regs_print);
501 }
502 #else /* !DEBUG */
503
504 static void dump_regs(struct tegra_dc *dc) {}
505
506 #endif /* DEBUG */
507
508 #ifdef CONFIG_DEBUG_FS
509
510 static void dbg_regs_print(void *data, const char *str)
511 {
512         struct seq_file *s = data;
513
514         seq_printf(s, "%s", str);
515 }
516
517 #undef DUMP_REG
518
519 static int dbg_dc_show(struct seq_file *s, void *unused)
520 {
521         struct tegra_dc *dc = s->private;
522
523         _dump_regs(dc, s, dbg_regs_print);
524
525         return 0;
526 }
527
528
529 static int dbg_dc_open(struct inode *inode, struct file *file)
530 {
531         return single_open(file, dbg_dc_show, inode->i_private);
532 }
533
534 static const struct file_operations regs_fops = {
535         .open           = dbg_dc_open,
536         .read           = seq_read,
537         .llseek         = seq_lseek,
538         .release        = single_release,
539 };
540
541 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
542 {
543         struct tegra_dc *dc = s->private;
544         struct tegra_dc_mode *m;
545
546         mutex_lock(&dc->lock);
547         m = &dc->mode;
548         seq_printf(s,
549                 "pclk: %d\n"
550                 "h_ref_to_sync: %d\n"
551                 "v_ref_to_sync: %d\n"
552                 "h_sync_width: %d\n"
553                 "v_sync_width: %d\n"
554                 "h_back_porch: %d\n"
555                 "v_back_porch: %d\n"
556                 "h_active: %d\n"
557                 "v_active: %d\n"
558                 "h_front_porch: %d\n"
559                 "v_front_porch: %d\n"
560                 "stereo_mode: %d\n",
561                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
562                 m->h_sync_width, m->v_sync_width,
563                 m->h_back_porch, m->v_back_porch,
564                 m->h_active, m->v_active,
565                 m->h_front_porch, m->v_front_porch,
566                 m->stereo_mode);
567         mutex_unlock(&dc->lock);
568         return 0;
569 }
570
571 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
572 {
573         return single_open(file, dbg_dc_mode_show, inode->i_private);
574 }
575
576 static const struct file_operations mode_fops = {
577         .open           = dbg_dc_mode_open,
578         .read           = seq_read,
579         .llseek         = seq_lseek,
580         .release        = single_release,
581 };
582
583 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
584 {
585         struct tegra_dc *dc = s->private;
586
587         mutex_lock(&dc->lock);
588         seq_printf(s,
589                 "underflows: %llu\n"
590                 "underflows_a: %llu\n"
591                 "underflows_b: %llu\n"
592                 "underflows_c: %llu\n",
593                 dc->stats.underflows,
594                 dc->stats.underflows_a,
595                 dc->stats.underflows_b,
596                 dc->stats.underflows_c);
597         mutex_unlock(&dc->lock);
598
599         return 0;
600 }
601
602 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
603 {
604         return single_open(file, dbg_dc_stats_show, inode->i_private);
605 }
606
607 static const struct file_operations stats_fops = {
608         .open           = dbg_dc_stats_open,
609         .read           = seq_read,
610         .llseek         = seq_lseek,
611         .release        = single_release,
612 };
613
614 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
615 {
616         if (dc->debugdir)
617                 debugfs_remove_recursive(dc->debugdir);
618         dc->debugdir = NULL;
619 }
620
621 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
622 {
623         struct dentry *retval;
624
625         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
626         if (!dc->debugdir)
627                 goto remove_out;
628
629         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
630                 &regs_fops);
631         if (!retval)
632                 goto remove_out;
633
634         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
635                 &mode_fops);
636         if (!retval)
637                 goto remove_out;
638
639         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
640                 &stats_fops);
641         if (!retval)
642                 goto remove_out;
643
644         return;
645 remove_out:
646         dev_err(&dc->ndev->dev, "could not create debugfs\n");
647         tegra_dc_remove_debugfs(dc);
648 }
649
650 #else /* !CONFIG_DEBUGFS */
651 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
652 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
653 #endif /* CONFIG_DEBUGFS */
654
655 static int tegra_dc_set(struct tegra_dc *dc, int index)
656 {
657         int ret = 0;
658
659         mutex_lock(&tegra_dc_lock);
660         if (index >= TEGRA_MAX_DC) {
661                 ret = -EINVAL;
662                 goto out;
663         }
664
665         if (dc != NULL && tegra_dcs[index] != NULL) {
666                 ret = -EBUSY;
667                 goto out;
668         }
669
670         tegra_dcs[index] = dc;
671
672 out:
673         mutex_unlock(&tegra_dc_lock);
674
675         return ret;
676 }
677
678 unsigned int tegra_dc_has_multiple_dc(void)
679 {
680         unsigned int idx;
681         unsigned int cnt = 0;
682         struct tegra_dc *dc;
683
684         mutex_lock(&tegra_dc_lock);
685         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
686                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
687         mutex_unlock(&tegra_dc_lock);
688
689         return (cnt > 1);
690 }
691
692 /* get the stride size of a window.
693  * return: stride size in bytes for window win. or 0 if unavailble. */
694 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
695 {
696         u32 stride;
697
698         if (!dc->enabled)
699                 return 0;
700         BUG_ON(win > DC_N_WINDOWS);
701         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
702                 DC_CMD_DISPLAY_WINDOW_HEADER);
703         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
704         return GET_LINE_STRIDE(stride);
705 }
706 EXPORT_SYMBOL(tegra_dc_get_stride);
707
708 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
709 {
710         if (idx < TEGRA_MAX_DC)
711                 return tegra_dcs[idx];
712         else
713                 return NULL;
714 }
715 EXPORT_SYMBOL(tegra_dc_get_dc);
716
717 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
718 {
719         if (win >= dc->n_windows)
720                 return NULL;
721
722         return &dc->windows[win];
723 }
724 EXPORT_SYMBOL(tegra_dc_get_window);
725
726 static int get_topmost_window(u32 *depths, unsigned long *wins, int win_num)
727 {
728         int idx, best = -1;
729
730         for_each_set_bit(idx, wins, win_num) {
731                 if (best == -1 || depths[idx] < depths[best])
732                         best = idx;
733         }
734         clear_bit(best, wins);
735         return best;
736 }
737
738 bool tegra_dc_get_connected(struct tegra_dc *dc)
739 {
740         return dc->connected;
741 }
742 EXPORT_SYMBOL(tegra_dc_get_connected);
743
744 bool tegra_dc_hpd(struct tegra_dc *dc)
745 {
746         int sense;
747         int level;
748
749         level = gpio_get_value(dc->out->hotplug_gpio);
750
751         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
752
753         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
754                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
755 }
756 EXPORT_SYMBOL(tegra_dc_hpd);
757
758 static u32 blend_topwin(u32 flags)
759 {
760         if (flags & TEGRA_WIN_FLAG_BLEND_COVERAGE)
761                 return BLEND(NOKEY, ALPHA, 0xff, 0xff);
762         else if (flags & TEGRA_WIN_FLAG_BLEND_PREMULT)
763                 return BLEND(NOKEY, PREMULT, 0xff, 0xff);
764         else
765                 return BLEND(NOKEY, FIX, 0xff, 0xff);
766 }
767
768 static u32 blend_2win(int idx, unsigned long behind_mask,
769                                                 u32* flags, int xy, int win_num)
770 {
771         int other;
772
773         for (other = 0; other < win_num; other++) {
774                 if (other != idx && (xy-- == 0))
775                         break;
776         }
777         if (BIT(other) & behind_mask)
778                 return blend_topwin(flags[idx]);
779         else if (flags[other])
780                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
781         else
782                 return BLEND(NOKEY, FIX, 0x00, 0x00);
783 }
784
785 static u32 blend_3win(int idx, unsigned long behind_mask,
786                                                 u32* flags, int win_num)
787 {
788         unsigned long infront_mask;
789         int first;
790
791         infront_mask = ~(behind_mask | BIT(idx));
792         infront_mask &= (BIT(win_num) - 1);
793         first = ffs(infront_mask) - 1;
794
795         if (!infront_mask)
796                 return blend_topwin(flags[idx]);
797         else if (behind_mask && first != -1 && flags[first])
798                 return BLEND(NOKEY, DEPENDANT, 0x00, 0x00);
799         else
800                 return BLEND(NOKEY, FIX, 0x0, 0x0);
801 }
802
803 static void tegra_dc_set_gen1_blending(struct tegra_dc *dc, struct tegra_dc_blend *blend)
804 {
805         int win_num = dc->gen1_blend_num;
806         unsigned long mask = BIT(win_num) - 1;
807
808         while (mask) {
809                 int idx = get_topmost_window(blend->z, &mask, win_num);
810
811                 tegra_dc_writel(dc, WINDOW_A_SELECT << idx,
812                                 DC_CMD_DISPLAY_WINDOW_HEADER);
813                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
814                                 DC_WIN_BLEND_NOKEY);
815                 tegra_dc_writel(dc, BLEND(NOKEY, FIX, 0xff, 0xff),
816                                 DC_WIN_BLEND_1WIN);
817                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 0,
818                                 win_num), DC_WIN_BLEND_2WIN_X);
819                 tegra_dc_writel(dc, blend_2win(idx, mask, blend->flags, 1,
820                                 win_num), DC_WIN_BLEND_2WIN_Y);
821                 tegra_dc_writel(dc, blend_3win(idx, mask, blend->flags,
822                                 win_num), DC_WIN_BLEND_3WIN_XY);
823         }
824 }
825
826 static void tegra_dc_set_gen2_blending(struct tegra_dc *dc,
827                                                 struct tegra_dc_blend *blend)
828 {
829         long val;
830         int i = 0;
831
832         for (i = 0; i < DC_N_WINDOWS; i++) {
833                 if (!tegra_dc_feature_is_gen2_blender(dc, i))
834                         continue;
835
836                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
837                                 DC_CMD_DISPLAY_WINDOW_HEADER);
838
839                 if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_COVERAGE) {
840                         tegra_dc_writel(dc,
841                                         WIN_K1(0xff) |
842                                         WIN_K2(0xff) |
843                                         WIN_BLEND_ENABLE,
844                                         DC_WINBUF_BLEND_LAYER_CONTROL);
845
846                         tegra_dc_writel(dc,
847                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1_TIMES_SRC |
848                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1_TIMES_SRC |
849                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
850                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
851                         DC_WINBUF_BLEND_MATCH_SELECT);
852
853                         tegra_dc_writel(dc,
854                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
855                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
856                                         DC_WINBUF_BLEND_ALPHA_1BIT);
857                 } else if (blend->flags[i] & TEGRA_WIN_FLAG_BLEND_PREMULT) {
858                         tegra_dc_writel(dc,
859                                         WIN_K1(0xff) |
860                                         WIN_K2(0xff) |
861                                         WIN_BLEND_ENABLE,
862                                         DC_WINBUF_BLEND_LAYER_CONTROL);
863
864                         tegra_dc_writel(dc,
865                         WIN_BLEND_FACT_SRC_COLOR_MATCH_SEL_K1 |
866                         WIN_BLEND_FACT_DST_COLOR_MATCH_SEL_NEG_K1 |
867                         WIN_BLEND_FACT_SRC_ALPHA_MATCH_SEL_K2 |
868                         WIN_BLEND_FACT_DST_ALPHA_MATCH_SEL_ZERO,
869                         DC_WINBUF_BLEND_MATCH_SELECT);
870
871                         tegra_dc_writel(dc,
872                                         WIN_ALPHA_1BIT_WEIGHT0(0) |
873                                         WIN_ALPHA_1BIT_WEIGHT1(0xff),
874                                         DC_WINBUF_BLEND_ALPHA_1BIT);
875                 } else {
876                         tegra_dc_writel(dc,
877                                         WIN_BLEND_BYPASS,
878                                         DC_WINBUF_BLEND_LAYER_CONTROL);
879                 }
880         }
881 }
882
883 static void tegra_dc_init_csc_defaults(struct tegra_dc_csc *csc)
884 {
885         csc->yof   = 0x00f0;
886         csc->kyrgb = 0x012a;
887         csc->kur   = 0x0000;
888         csc->kvr   = 0x0198;
889         csc->kug   = 0x039b;
890         csc->kvg   = 0x032f;
891         csc->kub   = 0x0204;
892         csc->kvb   = 0x0000;
893 }
894
895 static void tegra_dc_set_csc(struct tegra_dc *dc, struct tegra_dc_csc *csc)
896 {
897         tegra_dc_writel(dc, csc->yof,   DC_WIN_CSC_YOF);
898         tegra_dc_writel(dc, csc->kyrgb, DC_WIN_CSC_KYRGB);
899         tegra_dc_writel(dc, csc->kur,   DC_WIN_CSC_KUR);
900         tegra_dc_writel(dc, csc->kvr,   DC_WIN_CSC_KVR);
901         tegra_dc_writel(dc, csc->kug,   DC_WIN_CSC_KUG);
902         tegra_dc_writel(dc, csc->kvg,   DC_WIN_CSC_KVG);
903         tegra_dc_writel(dc, csc->kub,   DC_WIN_CSC_KUB);
904         tegra_dc_writel(dc, csc->kvb,   DC_WIN_CSC_KVB);
905 }
906
907 int tegra_dc_update_csc(struct tegra_dc *dc, int win_idx)
908 {
909         mutex_lock(&dc->lock);
910
911         if (!dc->enabled) {
912                 mutex_unlock(&dc->lock);
913                 return -EFAULT;
914         }
915
916         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
917                         DC_CMD_DISPLAY_WINDOW_HEADER);
918
919         tegra_dc_set_csc(dc, &dc->windows[win_idx].csc);
920
921         mutex_unlock(&dc->lock);
922
923         return 0;
924 }
925 EXPORT_SYMBOL(tegra_dc_update_csc);
926
927 static void tegra_dc_init_lut_defaults(struct tegra_dc_lut *lut)
928 {
929         int i;
930         for (i = 0; i < 256; i++)
931                 lut->r[i] = lut->g[i] = lut->b[i] = (u8)i;
932 }
933
934 static int tegra_dc_loop_lut(struct tegra_dc *dc,
935                              struct tegra_dc_win *win,
936                              int(*lambda)(struct tegra_dc *dc, int i, u32 rgb))
937 {
938         struct tegra_dc_lut *lut = &win->lut;
939         struct tegra_dc_lut *global_lut = &dc->fb_lut;
940         int i;
941         for (i = 0; i < 256; i++) {
942
943                 u32 r = (u32)lut->r[i];
944                 u32 g = (u32)lut->g[i];
945                 u32 b = (u32)lut->b[i];
946
947                 if (!(win->ppflags & TEGRA_WIN_PPFLAG_CP_FBOVERRIDE)) {
948                         r = (u32)global_lut->r[r];
949                         g = (u32)global_lut->g[g];
950                         b = (u32)global_lut->b[b];
951                 }
952
953                 if (!lambda(dc, i, r | (g<<8) | (b<<16)))
954                         return 0;
955         }
956         return 1;
957 }
958
959 static int tegra_dc_lut_isdefaults_lambda(struct tegra_dc *dc, int i, u32 rgb)
960 {
961         if (rgb != (i | (i<<8) | (i<<16)))
962                 return 0;
963         return 1;
964 }
965
966 static int tegra_dc_set_lut_setreg_lambda(struct tegra_dc *dc, int i, u32 rgb)
967 {
968         tegra_dc_writel(dc, rgb, DC_WIN_COLOR_PALETTE(i));
969         return 1;
970 }
971
972 static void tegra_dc_set_lut(struct tegra_dc *dc, struct tegra_dc_win* win)
973 {
974         unsigned long val = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
975
976         tegra_dc_loop_lut(dc, win, tegra_dc_set_lut_setreg_lambda);
977
978         if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
979                 val |= CP_ENABLE;
980         else
981                 val &= ~CP_ENABLE;
982
983         tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
984 }
985
986 static int tegra_dc_update_winlut(struct tegra_dc *dc, int win_idx, int fbovr)
987 {
988         struct tegra_dc_win *win = &dc->windows[win_idx];
989
990         mutex_lock(&dc->lock);
991
992         if (!dc->enabled) {
993                 mutex_unlock(&dc->lock);
994                 return -EFAULT;
995         }
996
997         if (fbovr > 0)
998                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
999         else if (fbovr == 0)
1000                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_FBOVERRIDE;
1001
1002         if (!tegra_dc_loop_lut(dc, win, tegra_dc_lut_isdefaults_lambda))
1003                 win->ppflags |= TEGRA_WIN_PPFLAG_CP_ENABLE;
1004         else
1005                 win->ppflags &= ~TEGRA_WIN_PPFLAG_CP_ENABLE;
1006
1007         tegra_dc_writel(dc, WINDOW_A_SELECT << win_idx,
1008                         DC_CMD_DISPLAY_WINDOW_HEADER);
1009
1010         tegra_dc_set_lut(dc, win);
1011
1012         mutex_unlock(&dc->lock);
1013
1014         tegra_dc_update_windows(&win, 1);
1015
1016         return 0;
1017 }
1018
1019 int tegra_dc_update_lut(struct tegra_dc *dc, int win_idx, int fboveride)
1020 {
1021         if (win_idx > -1)
1022                 return tegra_dc_update_winlut(dc, win_idx, fboveride);
1023
1024         for (win_idx = 0; win_idx < DC_N_WINDOWS; win_idx++) {
1025                 int err = tegra_dc_update_winlut(dc, win_idx, fboveride);
1026                 if (err)
1027                         return err;
1028         }
1029
1030         return 0;
1031 }
1032 EXPORT_SYMBOL(tegra_dc_update_lut);
1033
1034 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1035 {
1036         unsigned i;
1037         unsigned v0 = 128;
1038         unsigned v1 = 0;
1039         /* linear horizontal and vertical filters */
1040         for (i = 0; i < 16; i++) {
1041                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1042                                 DC_WIN_H_FILTER_P(i));
1043
1044                 tegra_dc_writel(dc, v0,
1045                                 DC_WIN_V_FILTER_P(i));
1046                 v0 -= 8;
1047                 v1 += 8;
1048         }
1049 }
1050
1051 #ifdef CONFIG_TEGRA_DC_CMU
1052 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
1053                                                 struct tegra_dc_cmu *src_cmu)
1054 {
1055         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
1056 }
1057
1058 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1059 {
1060         u32 val;
1061         u32 i;
1062
1063         for (i = 0; i < 256; i++) {
1064                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1065                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1066         }
1067
1068         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1069         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1070         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1071         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1072         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1073         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1074         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1075         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1076         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1077
1078         for (i = 0; i < 960; i++) {
1079                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1080                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1081         }
1082 }
1083
1084 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1085 {
1086         u32 val;
1087         u32 i;
1088         bool flags;
1089
1090         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1091         if (val & CMU_ENABLE)
1092                 flags = true;
1093
1094         val &= ~CMU_ENABLE;
1095         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1096         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1097         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1098
1099         /*TODO: Sync up with frame end */
1100         mdelay(20);
1101
1102         for (i = 0; i < 256; i++) {
1103                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
1104                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
1105                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
1106                 cmu->lut1[i] = LUT1_READ_DATA(val);
1107         }
1108
1109         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
1110         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
1111         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
1112         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
1113         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
1114         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
1115         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
1116         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
1117         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
1118
1119         for (i = 0; i < 960; i++) {
1120                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
1121                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
1122                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
1123                 cmu->lut2[i] = LUT2_READ_DATA(val);
1124         }
1125 }
1126
1127 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
1128 {
1129         mutex_lock(&dc->lock);
1130
1131         if (!dc->enabled) {
1132                 mutex_unlock(&dc->lock);
1133                 return -EFAULT;
1134         }
1135
1136         if (cmu_enable) {
1137                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
1138         } else {
1139                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
1140                 return 0;
1141         }
1142
1143         tegra_dc_set_cmu(dc, &dc->cmu);
1144
1145         mutex_unlock(&dc->lock);
1146
1147         return 0;
1148 }
1149 EXPORT_SYMBOL(tegra_dc_update_cmu);
1150 #else
1151 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
1152 #define tegra_dc_set_cmu(dc, cmu)
1153 #endif
1154
1155 void tegra_dc_host_suspend(struct tegra_dc *dc)
1156 {
1157         tegra_dsi_host_suspend(dc);
1158         tegra_dc_clk_disable(dc);
1159 }
1160
1161 void tegra_dc_host_resume(struct tegra_dc *dc) {
1162         tegra_dc_clk_enable(dc);
1163         tegra_dsi_host_resume(dc);
1164 }
1165
1166 static inline u32 compute_dda_inc(fixed20_12 in, unsigned out_int,
1167                                   bool v, unsigned Bpp)
1168 {
1169         /*
1170          * min(round((prescaled_size_in_pixels - 1) * 0x1000 /
1171          *           (post_scaled_size_in_pixels - 1)), MAX)
1172          * Where the value of MAX is as follows:
1173          * For V_DDA_INCREMENT: 15.0 (0xF000)
1174          * For H_DDA_INCREMENT:  4.0 (0x4000) for 4 Bytes/pix formats.
1175          *                       8.0 (0x8000) for 2 Bytes/pix formats.
1176          */
1177
1178         fixed20_12 out = dfixed_init(out_int);
1179         u32 dda_inc;
1180         int max;
1181
1182         if (v) {
1183                 max = 15;
1184         } else {
1185                 switch (Bpp) {
1186                 default:
1187                         WARN_ON_ONCE(1);
1188                         /* fallthrough */
1189                 case 4:
1190                         max = 4;
1191                         break;
1192                 case 2:
1193                         max = 8;
1194                         break;
1195                 }
1196         }
1197
1198         out.full = max_t(u32, out.full - dfixed_const(1), dfixed_const(1));
1199         in.full -= dfixed_const(1);
1200
1201         dda_inc = dfixed_div(in, out);
1202
1203         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
1204
1205         return dda_inc;
1206 }
1207
1208 static inline u32 compute_initial_dda(fixed20_12 in)
1209 {
1210         return dfixed_frac(in);
1211 }
1212
1213 /* does not support updating windows on multiple dcs in one call */
1214 int tegra_dc_update_windows(struct tegra_dc_win *windows[], int n)
1215 {
1216         struct tegra_dc *dc;
1217         unsigned long update_mask = GENERAL_ACT_REQ;
1218         unsigned long val;
1219         bool update_gen1_blend = false;
1220         bool update_gen2_blend = false;
1221         int i;
1222
1223         dc = windows[0]->dc;
1224
1225         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1226                 /* Acquire one_shot_lock to avoid race condition between
1227                  * cancellation of old delayed work and schedule of new
1228                  * delayed work. */
1229                 mutex_lock(&dc->one_shot_lock);
1230                 cancel_delayed_work_sync(&dc->one_shot_work);
1231         }
1232         mutex_lock(&dc->lock);
1233
1234         if (!dc->enabled) {
1235                 mutex_unlock(&dc->lock);
1236                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1237                         mutex_unlock(&dc->one_shot_lock);
1238                 return -EFAULT;
1239         }
1240
1241         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1242                 tegra_dc_host_resume(dc);
1243
1244         if (no_vsync)
1245                 tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE, DC_CMD_STATE_ACCESS);
1246         else
1247                 tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY, DC_CMD_STATE_ACCESS);
1248
1249         for (i = 0; i < n; i++) {
1250                 struct tegra_dc_win *win = windows[i];
1251                 unsigned h_dda;
1252                 unsigned v_dda;
1253                 fixed20_12 h_offset, v_offset;
1254                 bool invert_h = (win->flags & TEGRA_WIN_FLAG_INVERT_H) != 0;
1255                 bool invert_v = (win->flags & TEGRA_WIN_FLAG_INVERT_V) != 0;
1256                 bool yuv = tegra_dc_is_yuv(win->fmt);
1257                 bool yuvp = tegra_dc_is_yuv_planar(win->fmt);
1258                 unsigned Bpp = tegra_dc_fmt_bpp(win->fmt) / 8;
1259                 /* Bytes per pixel of bandwidth, used for dda_inc calculation */
1260                 unsigned Bpp_bw = Bpp * (yuvp ? 2 : 1);
1261                 const bool filter_h = win_use_h_filter(dc, win);
1262                 const bool filter_v = win_use_v_filter(dc, win);
1263
1264                 if (win->z != dc->blend.z[win->idx]) {
1265                         dc->blend.z[win->idx] = win->z;
1266                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1267                                 update_gen2_blend = true;
1268                         else
1269                                 update_gen1_blend = true;
1270                 }
1271                 if ((win->flags & TEGRA_WIN_BLEND_FLAGS_MASK) !=
1272                         dc->blend.flags[win->idx]) {
1273                         dc->blend.flags[win->idx] =
1274                                 win->flags & TEGRA_WIN_BLEND_FLAGS_MASK;
1275                         if (tegra_dc_feature_is_gen2_blender(dc, win->idx))
1276                                 update_gen2_blend = true;
1277                         else
1278                                 update_gen1_blend = true;
1279                 }
1280
1281                 tegra_dc_writel(dc, WINDOW_A_SELECT << win->idx,
1282                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1283
1284                 if (!no_vsync)
1285                         update_mask |= WIN_A_ACT_REQ << win->idx;
1286
1287                 if (!WIN_IS_ENABLED(win)) {
1288                         tegra_dc_writel(dc, 0, DC_WIN_WIN_OPTIONS);
1289                         continue;
1290                 }
1291
1292                 tegra_dc_writel(dc, win->fmt & 0x1f, DC_WIN_COLOR_DEPTH);
1293                 tegra_dc_writel(dc, win->fmt >> 6, DC_WIN_BYTE_SWAP);
1294
1295                 tegra_dc_writel(dc,
1296                                 V_POSITION(win->out_y) | H_POSITION(win->out_x),
1297                                 DC_WIN_POSITION);
1298                 tegra_dc_writel(dc,
1299                                 V_SIZE(win->out_h) | H_SIZE(win->out_w),
1300                                 DC_WIN_SIZE);
1301
1302                 if (tegra_dc_feature_has_scaling(dc, win->idx)) {
1303                         tegra_dc_writel(dc,
1304                                         V_PRESCALED_SIZE(dfixed_trunc(win->h)) |
1305                                         H_PRESCALED_SIZE(dfixed_trunc(win->w) * Bpp),
1306                                         DC_WIN_PRESCALED_SIZE);
1307
1308                         h_dda = compute_dda_inc(win->w, win->out_w, false, Bpp_bw);
1309                         v_dda = compute_dda_inc(win->h, win->out_h, true, Bpp_bw);
1310                         tegra_dc_writel(dc, V_DDA_INC(v_dda) | H_DDA_INC(h_dda),
1311                                         DC_WIN_DDA_INCREMENT);
1312                         h_dda = compute_initial_dda(win->x);
1313                         v_dda = compute_initial_dda(win->y);
1314                         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
1315                         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
1316                 }
1317
1318 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1319                 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
1320                 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
1321 #endif
1322                 tegra_dc_writel(dc,
1323                                 (unsigned long)win->phys_addr,
1324                                 DC_WINBUF_START_ADDR);
1325
1326                 if (!yuvp) {
1327                         tegra_dc_writel(dc, win->stride, DC_WIN_LINE_STRIDE);
1328                 } else {
1329                         tegra_dc_writel(dc,
1330                                         (unsigned long)win->phys_addr_u,
1331                                         DC_WINBUF_START_ADDR_U);
1332                         tegra_dc_writel(dc,
1333                                         (unsigned long)win->phys_addr_v,
1334                                         DC_WINBUF_START_ADDR_V);
1335                         tegra_dc_writel(dc,
1336                                         LINE_STRIDE(win->stride) |
1337                                         UV_LINE_STRIDE(win->stride_uv),
1338                                         DC_WIN_LINE_STRIDE);
1339                 }
1340
1341                 h_offset = win->x;
1342                 if (invert_h) {
1343                         h_offset.full += win->w.full - dfixed_const(1);
1344                 }
1345
1346                 v_offset = win->y;
1347                 if (invert_v) {
1348                         v_offset.full += win->h.full - dfixed_const(1);
1349                 }
1350
1351                 tegra_dc_writel(dc, dfixed_trunc(h_offset) * Bpp,
1352                                 DC_WINBUF_ADDR_H_OFFSET);
1353                 tegra_dc_writel(dc, dfixed_trunc(v_offset),
1354                                 DC_WINBUF_ADDR_V_OFFSET);
1355
1356                 if (tegra_dc_feature_has_tiling(dc, win->idx)) {
1357                         if (WIN_IS_TILED(win))
1358                                 tegra_dc_writel(dc,
1359                                                 DC_WIN_BUFFER_ADDR_MODE_TILE |
1360                                                 DC_WIN_BUFFER_ADDR_MODE_TILE_UV,
1361                                                 DC_WIN_BUFFER_ADDR_MODE);
1362                         else
1363                                 tegra_dc_writel(dc,
1364                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR |
1365                                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV,
1366                                                 DC_WIN_BUFFER_ADDR_MODE);
1367                 }
1368
1369                 val = WIN_ENABLE;
1370                 if (yuv)
1371                         val |= CSC_ENABLE;
1372                 else if (tegra_dc_fmt_bpp(win->fmt) < 24)
1373                         val |= COLOR_EXPAND;
1374
1375                 if (win->ppflags & TEGRA_WIN_PPFLAG_CP_ENABLE)
1376                         val |= CP_ENABLE;
1377
1378                 if (filter_h)
1379                         val |= H_FILTER_ENABLE;
1380                 if (filter_v)
1381                         val |= V_FILTER_ENABLE;
1382
1383                 if (invert_h)
1384                         val |= H_DIRECTION_DECREMENT;
1385                 if (invert_v)
1386                         val |= V_DIRECTION_DECREMENT;
1387
1388                 tegra_dc_writel(dc, val, DC_WIN_WIN_OPTIONS);
1389
1390 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1391                 if (win->global_alpha == 255)
1392                         tegra_dc_writel(dc, 0, DC_WIN_GLOBAL_ALPHA);
1393                 else
1394                         tegra_dc_writel(dc, GLOBAL_ALPHA_ENABLE |
1395                                 win->global_alpha, DC_WIN_GLOBAL_ALPHA);
1396 #endif
1397
1398                 win->dirty = no_vsync ? 0 : 1;
1399
1400                 dev_dbg(&dc->ndev->dev, "%s():idx=%d z=%d x=%d y=%d w=%d h=%d "
1401                         "out_x=%u out_y=%u out_w=%u out_h=%u "
1402                         "fmt=%d yuvp=%d Bpp=%u filter_h=%d filter_v=%d",
1403                         __func__, win->idx, win->z,
1404                         dfixed_trunc(win->x), dfixed_trunc(win->y),
1405                         dfixed_trunc(win->w), dfixed_trunc(win->h),
1406                         win->out_x, win->out_y, win->out_w, win->out_h,
1407                         win->fmt, yuvp, Bpp, filter_h, filter_v);
1408                 trace_printk("%s:win%u in:%ux%u out:%ux%u fmt=%d\n",
1409                         dc->ndev->name, win->idx, dfixed_trunc(win->w),
1410                         dfixed_trunc(win->h), win->out_w, win->out_h, win->fmt);
1411         }
1412
1413         if (update_gen1_blend || update_gen2_blend) {
1414                 if (update_gen1_blend)
1415                         tegra_dc_set_gen1_blending(dc, &dc->blend);
1416                 if (update_gen2_blend)
1417                         tegra_dc_set_gen2_blending(dc, &dc->blend);
1418                 for (i = 0; i < DC_N_WINDOWS; i++) {
1419                         if (!no_vsync)
1420                                 dc->windows[i].dirty = 1;
1421                         update_mask |= WIN_A_ACT_REQ << i;
1422                 }
1423         }
1424
1425         tegra_dc_set_dynamic_emc(windows, n);
1426
1427         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
1428
1429         tegra_dc_writel(dc, FRAME_END_INT | V_BLANK_INT, DC_CMD_INT_STATUS);
1430         if (!no_vsync) {
1431                 set_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1432                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1433         } else {
1434                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1435                 tegra_dc_mask_interrupt(dc, FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1436         }
1437
1438         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1439                 schedule_delayed_work(&dc->one_shot_work,
1440                                 msecs_to_jiffies(dc->one_shot_delay_ms));
1441
1442         /* update EMC clock if calculated bandwidth has changed */
1443         tegra_dc_program_bandwidth(dc);
1444
1445         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1446                 update_mask |= NC_HOST_TRIG;
1447
1448         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
1449         trace_printk("%s:update_mask=%#lx\n", dc->ndev->name, update_mask);
1450
1451         mutex_unlock(&dc->lock);
1452         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1453                 mutex_unlock(&dc->one_shot_lock);
1454
1455         return 0;
1456 }
1457 EXPORT_SYMBOL(tegra_dc_update_windows);
1458
1459 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1460 {
1461         return dc->syncpt[i].id;
1462 }
1463 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1464
1465 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1466 {
1467         u32 max;
1468
1469         mutex_lock(&dc->lock);
1470         max = nvhost_syncpt_incr_max(&nvhost_get_host(dc->ndev)->syncpt,
1471                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1472         dc->syncpt[i].max = max;
1473         mutex_unlock(&dc->lock);
1474
1475         return max;
1476 }
1477
1478 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1479 {
1480         mutex_lock(&dc->lock);
1481         if ( dc->enabled )
1482                 while (dc->syncpt[i].min < val) {
1483                         dc->syncpt[i].min++;
1484                         nvhost_syncpt_cpu_incr(
1485                                         &nvhost_get_host(dc->ndev)->syncpt,
1486                                         dc->syncpt[i].id);
1487                 }
1488         mutex_unlock(&dc->lock);
1489 }
1490
1491 static bool tegra_dc_windows_are_clean(struct tegra_dc_win *windows[],
1492                                              int n)
1493 {
1494         int i;
1495
1496         for (i = 0; i < n; i++) {
1497                 if (windows[i]->dirty)
1498                         return false;
1499         }
1500
1501         return true;
1502 }
1503
1504 /* does not support syncing windows on multiple dcs in one call */
1505 int tegra_dc_sync_windows(struct tegra_dc_win *windows[], int n)
1506 {
1507         int ret;
1508         if (n < 1 || n > DC_N_WINDOWS)
1509                 return -EINVAL;
1510
1511         if (!windows[0]->dc->enabled)
1512                 return -EFAULT;
1513
1514         trace_printk("%s:Before wait_event_interruptible_timeout\n",
1515                         windows[0]->dc->ndev->name);
1516         ret = wait_event_interruptible_timeout(windows[0]->dc->wq,
1517                                          tegra_dc_windows_are_clean(windows, n),
1518                                          HZ);
1519         trace_printk("%s:After wait_event_interruptible_timeout\n",
1520                         windows[0]->dc->ndev->name);
1521         return ret;
1522 }
1523 EXPORT_SYMBOL(tegra_dc_sync_windows);
1524
1525 static unsigned long tegra_dc_clk_get_rate(struct tegra_dc *dc)
1526 {
1527 #ifdef CONFIG_TEGRA_FPGA_PLATFORM
1528         return 27000000;
1529 #else
1530         return clk_get_rate(dc->clk);
1531 #endif
1532 }
1533
1534 static unsigned long tegra_dc_pclk_round_rate(struct tegra_dc *dc, int pclk)
1535 {
1536         unsigned long rate;
1537         unsigned long div;
1538
1539         rate = tegra_dc_clk_get_rate(dc);
1540
1541         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1542
1543         if (div < 2)
1544                 return 0;
1545
1546         return rate * 2 / div;
1547 }
1548
1549 static unsigned long tegra_dc_pclk_predict_rate(struct clk *parent, int pclk)
1550 {
1551         unsigned long rate;
1552         unsigned long div;
1553
1554         rate = clk_get_rate(parent);
1555
1556         div = DIV_ROUND_CLOSEST(rate * 2, pclk);
1557
1558         if (div < 2)
1559                 return 0;
1560
1561         return rate * 2 / div;
1562 }
1563
1564 void tegra_dc_setup_clk(struct tegra_dc *dc, struct clk *clk)
1565 {
1566         int pclk;
1567
1568         if (dc->out->type == TEGRA_DC_OUT_RGB) {
1569                 unsigned long rate;
1570                 struct clk *parent_clk =
1571                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_p");
1572
1573                 if (dc->out->parent_clk_backup &&
1574                     (parent_clk == clk_get_sys(NULL, "pll_p"))) {
1575                         rate = tegra_dc_pclk_predict_rate(
1576                                 parent_clk, dc->mode.pclk);
1577                         /* use pll_d as last resort */
1578                         if (rate < (dc->mode.pclk / 100 * 99) ||
1579                             rate > (dc->mode.pclk / 100 * 109))
1580                                 parent_clk = clk_get_sys(
1581                                         NULL, dc->out->parent_clk_backup);
1582                 }
1583
1584                 if (clk_get_parent(clk) != parent_clk)
1585                         clk_set_parent(clk, parent_clk);
1586
1587                 if (parent_clk != clk_get_sys(NULL, "pll_p")) {
1588                         struct clk *base_clk = clk_get_parent(parent_clk);
1589
1590                         /* Assuming either pll_d or pll_d2 is used */
1591                         rate = dc->mode.pclk * 2;
1592
1593                         if (rate != clk_get_rate(base_clk))
1594                                 clk_set_rate(base_clk, rate);
1595                 }
1596         }
1597
1598         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1599                 unsigned long rate;
1600                 struct clk *parent_clk =
1601                         clk_get_sys(NULL, dc->out->parent_clk ? : "pll_d_out0");
1602                 struct clk *base_clk = clk_get_parent(parent_clk);
1603
1604                 /*
1605                  * Providing dynamic frequency rate setting for T20/T30 HDMI.
1606                  * The required rate needs to be setup at 4x multiplier,
1607                  * as out0 is 1/2 of the actual PLL output.
1608                  */
1609
1610                 rate = dc->mode.pclk * 4;
1611                 if (rate != clk_get_rate(base_clk))
1612                         clk_set_rate(base_clk, rate);
1613
1614                 if (clk_get_parent(clk) != parent_clk)
1615                         clk_set_parent(clk, parent_clk);
1616         }
1617
1618         if (dc->out->type == TEGRA_DC_OUT_DSI) {
1619                 unsigned long rate;
1620                 struct clk *parent_clk;
1621                 struct clk *base_clk;
1622
1623                 if (clk == dc->clk) {
1624                         parent_clk = clk_get_sys(NULL,
1625                                         dc->out->parent_clk ? : "pll_d_out0");
1626                         base_clk = clk_get_parent(parent_clk);
1627                         tegra_clk_cfg_ex(base_clk,
1628                                         TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1629                 } else {
1630                         if (dc->pdata->default_out->dsi->dsi_instance) {
1631                                 parent_clk = clk_get_sys(NULL,
1632                                         dc->out->parent_clk ? : "pll_d2_out0");
1633                                 base_clk = clk_get_parent(parent_clk);
1634                                 tegra_clk_cfg_ex(base_clk,
1635                                                 TEGRA_CLK_PLLD_CSI_OUT_ENB, 1);
1636                         } else {
1637                                 parent_clk = clk_get_sys(NULL,
1638                                         dc->out->parent_clk ? : "pll_d_out0");
1639                                 base_clk = clk_get_parent(parent_clk);
1640                                 tegra_clk_cfg_ex(base_clk,
1641                                                 TEGRA_CLK_PLLD_DSI_OUT_ENB, 1);
1642                         }
1643                 }
1644
1645                 rate = dc->mode.pclk * dc->shift_clk_div * 2;
1646                 if (rate != clk_get_rate(base_clk))
1647                         clk_set_rate(base_clk, rate);
1648
1649                 if (clk_get_parent(clk) != parent_clk)
1650                         clk_set_parent(clk, parent_clk);
1651         }
1652
1653         pclk = tegra_dc_pclk_round_rate(dc, dc->mode.pclk);
1654         tegra_dvfs_set_rate(clk, pclk);
1655 }
1656
1657 /* return non-zero if constraint is violated */
1658 static int calc_h_ref_to_sync(const struct tegra_dc_mode *mode, int *href)
1659 {
1660         long a, b;
1661
1662         /* Constraint 5: H_REF_TO_SYNC >= 0 */
1663         a = 0;
1664
1665         /* Constraint 6: H_FRONT_PORT >= (H_REF_TO_SYNC + 1) */
1666         b = mode->h_front_porch - 1;
1667
1668         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11 */
1669         if (a + mode->h_sync_width + mode->h_back_porch <= 11)
1670                 a = 1 + 11 - mode->h_sync_width - mode->h_back_porch;
1671         /* check Constraint 1 and 6 */
1672         if (a > b)
1673                 return 1;
1674
1675         /* Constraint 4: H_SYNC_WIDTH >= 1 */
1676         if (mode->h_sync_width < 1)
1677                 return 4;
1678
1679         /* Constraint 7: H_DISP_ACTIVE >= 16 */
1680         if (mode->h_active < 16)
1681                 return 7;
1682
1683         if (href) {
1684                 if (b > a && a % 2)
1685                         *href = a + 1; /* use smallest even value */
1686                 else
1687                         *href = a; /* even or only possible value */
1688         }
1689
1690         return 0;
1691 }
1692
1693 static int calc_v_ref_to_sync(const struct tegra_dc_mode *mode, int *vref)
1694 {
1695         long a;
1696         a = 1; /* Constraint 5: V_REF_TO_SYNC >= 1 */
1697
1698         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1 */
1699         if (a + mode->v_sync_width + mode->v_back_porch <= 1)
1700                 a = 1 + 1 - mode->v_sync_width - mode->v_back_porch;
1701
1702         /* Constraint 6 */
1703         if (mode->v_front_porch < a + 1)
1704                 a = mode->v_front_porch - 1;
1705
1706         /* Constraint 4: V_SYNC_WIDTH >= 1 */
1707         if (mode->v_sync_width < 1)
1708                 return 4;
1709
1710         /* Constraint 7: V_DISP_ACTIVE >= 16 */
1711         if (mode->v_active < 16)
1712                 return 7;
1713
1714         if (vref)
1715                 *vref = a;
1716         return 0;
1717 }
1718
1719 static int calc_ref_to_sync(struct tegra_dc_mode *mode)
1720 {
1721         int ret;
1722         ret = calc_h_ref_to_sync(mode, &mode->h_ref_to_sync);
1723         if (ret)
1724                 return ret;
1725         ret = calc_v_ref_to_sync(mode, &mode->v_ref_to_sync);
1726         if (ret)
1727                 return ret;
1728
1729         return 0;
1730 }
1731
1732 static bool check_ref_to_sync(struct tegra_dc_mode *mode)
1733 {
1734         /* Constraint 1: H_REF_TO_SYNC + H_SYNC_WIDTH + H_BACK_PORCH > 11. */
1735         if (mode->h_ref_to_sync + mode->h_sync_width + mode->h_back_porch <= 11)
1736                 return false;
1737
1738         /* Constraint 2: V_REF_TO_SYNC + V_SYNC_WIDTH + V_BACK_PORCH > 1. */
1739         if (mode->v_ref_to_sync + mode->v_sync_width + mode->v_back_porch <= 1)
1740                 return false;
1741
1742         /* Constraint 3: V_FRONT_PORCH + V_SYNC_WIDTH + V_BACK_PORCH > 1
1743          * (vertical blank). */
1744         if (mode->v_front_porch + mode->v_sync_width + mode->v_back_porch <= 1)
1745                 return false;
1746
1747         /* Constraint 4: V_SYNC_WIDTH >= 1; H_SYNC_WIDTH >= 1. */
1748         if (mode->v_sync_width < 1 || mode->h_sync_width < 1)
1749                 return false;
1750
1751         /* Constraint 5: V_REF_TO_SYNC >= 1; H_REF_TO_SYNC >= 0. */
1752         if (mode->v_ref_to_sync < 1 || mode->h_ref_to_sync < 0)
1753                 return false;
1754
1755         /* Constraint 6: V_FRONT_PORT >= (V_REF_TO_SYNC + 1);
1756          * H_FRONT_PORT >= (H_REF_TO_SYNC + 1). */
1757         if (mode->v_front_porch < mode->v_ref_to_sync + 1 ||
1758                 mode->h_front_porch < mode->h_ref_to_sync + 1)
1759                 return false;
1760
1761         /* Constraint 7: H_DISP_ACTIVE >= 16; V_DISP_ACTIVE >= 16. */
1762         if (mode->h_active < 16 || mode->v_active < 16)
1763                 return false;
1764
1765         return true;
1766 }
1767
1768 #ifdef DEBUG
1769 /* return in 1000ths of a Hertz */
1770 static int calc_refresh(const struct tegra_dc_mode *m)
1771 {
1772         long h_total, v_total, refresh;
1773         h_total = m->h_active + m->h_front_porch + m->h_back_porch +
1774                 m->h_sync_width;
1775         v_total = m->v_active + m->v_front_porch + m->v_back_porch +
1776                 m->v_sync_width;
1777         refresh = m->pclk / h_total;
1778         refresh *= 1000;
1779         refresh /= v_total;
1780         return refresh;
1781 }
1782
1783 static void print_mode(struct tegra_dc *dc,
1784                         const struct tegra_dc_mode *mode, const char *note)
1785 {
1786         if (mode) {
1787                 int refresh = calc_refresh(dc, mode);
1788                 dev_info(&dc->ndev->dev, "%s():MODE:%dx%d@%d.%03uHz pclk=%d\n",
1789                         note ? note : "",
1790                         mode->h_active, mode->v_active,
1791                         refresh / 1000, refresh % 1000,
1792                         mode->pclk);
1793         }
1794 }
1795 #else /* !DEBUG */
1796 static inline void print_mode(struct tegra_dc *dc,
1797                         const struct tegra_dc_mode *mode, const char *note) { }
1798 #endif /* DEBUG */
1799
1800 static inline void tegra_dc_unmask_interrupt(struct tegra_dc *dc, u32 int_val)
1801 {
1802         u32 val;
1803
1804         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1805         val |= int_val;
1806         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1807 }
1808
1809 static inline void tegra_dc_mask_interrupt(struct tegra_dc *dc, u32 int_val)
1810 {
1811         u32 val;
1812
1813         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1814         val &= ~int_val;
1815         tegra_dc_writel(dc, val, DC_CMD_INT_MASK);
1816 }
1817
1818 static int tegra_dc_program_mode(struct tegra_dc *dc, struct tegra_dc_mode *mode)
1819 {
1820         unsigned long val;
1821         unsigned long rate;
1822         unsigned long div;
1823         unsigned long pclk;
1824
1825         print_mode(dc, mode, __func__);
1826
1827         /* use default EMC rate when switching modes */
1828         dc->new_emc_clk_rate = tegra_dc_get_default_emc_clk_rate(dc);
1829         tegra_dc_program_bandwidth(dc);
1830
1831         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
1832         tegra_dc_writel(dc, mode->h_ref_to_sync | (mode->v_ref_to_sync << 16),
1833                         DC_DISP_REF_TO_SYNC);
1834         tegra_dc_writel(dc, mode->h_sync_width | (mode->v_sync_width << 16),
1835                         DC_DISP_SYNC_WIDTH);
1836         tegra_dc_writel(dc, mode->h_back_porch | (mode->v_back_porch << 16),
1837                         DC_DISP_BACK_PORCH);
1838         tegra_dc_writel(dc, mode->h_active | (mode->v_active << 16),
1839                         DC_DISP_DISP_ACTIVE);
1840         tegra_dc_writel(dc, mode->h_front_porch | (mode->v_front_porch << 16),
1841                         DC_DISP_FRONT_PORCH);
1842
1843         tegra_dc_writel(dc, DE_SELECT_ACTIVE | DE_CONTROL_NORMAL,
1844                         DC_DISP_DATA_ENABLE_OPTIONS);
1845
1846         /* TODO: MIPI/CRT/HDMI clock cals */
1847
1848         val = DISP_DATA_FORMAT_DF1P1C;
1849
1850         if (dc->out->align == TEGRA_DC_ALIGN_MSB)
1851                 val |= DISP_DATA_ALIGNMENT_MSB;
1852         else
1853                 val |= DISP_DATA_ALIGNMENT_LSB;
1854
1855         if (dc->out->order == TEGRA_DC_ORDER_RED_BLUE)
1856                 val |= DISP_DATA_ORDER_RED_BLUE;
1857         else
1858                 val |= DISP_DATA_ORDER_BLUE_RED;
1859
1860         tegra_dc_writel(dc, val, DC_DISP_DISP_INTERFACE_CONTROL);
1861
1862         rate = tegra_dc_clk_get_rate(dc);
1863
1864         pclk = tegra_dc_pclk_round_rate(dc, mode->pclk);
1865         trace_printk("%s:pclk=%ld\n", dc->ndev->name, pclk);
1866         if (pclk < (mode->pclk / 100 * 99) ||
1867             pclk > (mode->pclk / 100 * 109)) {
1868                 dev_err(&dc->ndev->dev,
1869                         "can't divide %ld clock to %d -1/+9%% %ld %d %d\n",
1870                         rate, mode->pclk,
1871                         pclk, (mode->pclk / 100 * 99),
1872                         (mode->pclk / 100 * 109));
1873                 return -EINVAL;
1874         }
1875
1876         div = (rate * 2 / pclk) - 2;
1877         trace_printk("%s:div=%ld\n", dc->ndev->name, div);
1878
1879         tegra_dc_writel(dc, 0x00010001,
1880                         DC_DISP_SHIFT_CLOCK_OPTIONS);
1881         tegra_dc_writel(dc, PIXEL_CLK_DIVIDER_PCD1 | SHIFT_CLK_DIVIDER(div),
1882                         DC_DISP_DISP_CLOCK_CONTROL);
1883
1884 #ifdef CONFIG_SWITCH
1885         switch_set_state(&dc->modeset_switch,
1886                          (mode->h_active << 16) | mode->v_active);
1887 #endif
1888
1889         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1890         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1891
1892         print_mode_info(dc, dc->mode);
1893         return 0;
1894 }
1895
1896
1897 int tegra_dc_set_mode(struct tegra_dc *dc, const struct tegra_dc_mode *mode)
1898 {
1899         memcpy(&dc->mode, mode, sizeof(dc->mode));
1900
1901         print_mode(dc, mode, __func__);
1902
1903         return 0;
1904 }
1905 EXPORT_SYMBOL(tegra_dc_set_mode);
1906
1907 int tegra_dc_set_fb_mode(struct tegra_dc *dc,
1908                 const struct fb_videomode *fbmode, bool stereo_mode)
1909 {
1910         struct tegra_dc_mode mode;
1911
1912         if (!fbmode->pixclock)
1913                 return -EINVAL;
1914
1915         mode.pclk = PICOS2KHZ(fbmode->pixclock) * 1000;
1916         mode.h_sync_width = fbmode->hsync_len;
1917         mode.v_sync_width = fbmode->vsync_len;
1918         mode.h_back_porch = fbmode->left_margin;
1919         mode.v_back_porch = fbmode->upper_margin;
1920         mode.h_active = fbmode->xres;
1921         mode.v_active = fbmode->yres;
1922         mode.h_front_porch = fbmode->right_margin;
1923         mode.v_front_porch = fbmode->lower_margin;
1924         mode.stereo_mode = stereo_mode;
1925         if (dc->out->type == TEGRA_DC_OUT_HDMI) {
1926                 /* HDMI controller requires h_ref=1, v_ref=1 */
1927                 mode.h_ref_to_sync = 1;
1928                 mode.v_ref_to_sync = 1;
1929         } else {
1930                 calc_ref_to_sync(&mode);
1931         }
1932         if (!check_ref_to_sync(&mode)) {
1933                 dev_err(&dc->ndev->dev,
1934                                 "Display timing doesn't meet restrictions.\n");
1935                 return -EINVAL;
1936         }
1937         dev_info(&dc->ndev->dev, "Using mode %dx%d pclk=%d href=%d vref=%d\n",
1938                 mode.h_active, mode.v_active, mode.pclk,
1939                 mode.h_ref_to_sync, mode.v_ref_to_sync
1940         );
1941
1942 #ifndef CONFIG_TEGRA_HDMI_74MHZ_LIMIT
1943         /* Double the pixel clock and update v_active only for frame packed mode */
1944         if (mode.stereo_mode) {
1945                 mode.pclk *= 2;
1946                 /* total v_active = yres*2 + activespace */
1947                 mode.v_active = fbmode->yres*2 +
1948                                 fbmode->vsync_len +
1949                                 fbmode->upper_margin +
1950                                 fbmode->lower_margin;
1951         }
1952 #endif
1953
1954         mode.flags = 0;
1955
1956         if (!(fbmode->sync & FB_SYNC_HOR_HIGH_ACT))
1957                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_H_SYNC;
1958
1959         if (!(fbmode->sync & FB_SYNC_VERT_HIGH_ACT))
1960                 mode.flags |= TEGRA_DC_MODE_FLAG_NEG_V_SYNC;
1961
1962         return tegra_dc_set_mode(dc, &mode);
1963 }
1964 EXPORT_SYMBOL(tegra_dc_set_fb_mode);
1965
1966 void
1967 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1968 {
1969         unsigned int ctrl;
1970         unsigned long out_sel;
1971         unsigned long cmd_state;
1972
1973         mutex_lock(&dc->lock);
1974         if (!dc->enabled) {
1975                 mutex_unlock(&dc->lock);
1976                 return;
1977         }
1978
1979         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1980                 tegra_dc_host_resume(dc);
1981
1982         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1983                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1984                 cfg->clk_select);
1985
1986         /* The new value should be effected immediately */
1987         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1988         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1989
1990         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
1991                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
1992         else
1993                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
1994
1995         switch (cfg->which_pwm) {
1996         case TEGRA_PWM_PM0:
1997                 /* Select the LM0 on PM0 */
1998                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1999                 out_sel &= ~(7 << 0);
2000                 out_sel |= (3 << 0);
2001                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2002                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2003                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2004                 break;
2005         case TEGRA_PWM_PM1:
2006                 /* Select the LM1 on PM1 */
2007                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2008                 out_sel &= ~(7 << 4);
2009                 out_sel |= (3 << 4);
2010                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2011                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2012                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2013                 break;
2014         default:
2015                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2016                 break;
2017         }
2018         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2019         mutex_unlock(&dc->lock);
2020 }
2021 EXPORT_SYMBOL(tegra_dc_config_pwm);
2022
2023 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2024                                 const struct tegra_dc_out_pin *pins,
2025                                 const unsigned int n_pins)
2026 {
2027         unsigned int i;
2028
2029         int name;
2030         int pol;
2031
2032         u32 pol1, pol3;
2033
2034         u32 set1, unset1;
2035         u32 set3, unset3;
2036
2037         set1 = set3 = unset1 = unset3 = 0;
2038
2039         for (i = 0; i < n_pins; i++) {
2040                 name = (pins + i)->name;
2041                 pol  = (pins + i)->pol;
2042
2043                 /* set polarity by name */
2044                 switch (name) {
2045                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2046                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2047                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2048                         else
2049                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2050                         break;
2051                 case TEGRA_DC_OUT_PIN_H_SYNC:
2052                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2053                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2054                         else
2055                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2056                         break;
2057                 case TEGRA_DC_OUT_PIN_V_SYNC:
2058                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2059                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2060                         else
2061                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2062                         break;
2063                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2064                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2065                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2066                         else
2067                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2068                         break;
2069                 default:
2070                         printk("Invalid argument in function %s\n",
2071                                __FUNCTION__);
2072                         break;
2073                 }
2074         }
2075
2076         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2077         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2078
2079         pol1 |= set1;
2080         pol1 &= ~unset1;
2081
2082         pol3 |= set3;
2083         pol3 &= ~unset3;
2084
2085         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2086         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2087 }
2088
2089 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2090 {
2091         dc->out = out;
2092
2093         if (out->n_modes > 0)
2094                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
2095
2096         switch (out->type) {
2097         case TEGRA_DC_OUT_RGB:
2098                 dc->out_ops = &tegra_dc_rgb_ops;
2099                 break;
2100
2101         case TEGRA_DC_OUT_HDMI:
2102                 dc->out_ops = &tegra_dc_hdmi_ops;
2103                 break;
2104
2105         case TEGRA_DC_OUT_DSI:
2106                 dc->out_ops = &tegra_dc_dsi_ops;
2107                 break;
2108
2109         default:
2110                 dc->out_ops = NULL;
2111                 break;
2112         }
2113
2114         if (dc->out_ops && dc->out_ops->init)
2115                 dc->out_ops->init(dc);
2116
2117 }
2118
2119 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2120 {
2121         if (dc->out)
2122                 return dc->out->height;
2123         else
2124                 return 0;
2125 }
2126 EXPORT_SYMBOL(tegra_dc_get_out_height);
2127
2128 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2129 {
2130         if (dc->out)
2131                 return dc->out->width;
2132         else
2133                 return 0;
2134 }
2135 EXPORT_SYMBOL(tegra_dc_get_out_width);
2136
2137 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2138 {
2139         if (dc->out && dc->out->max_pixclock)
2140                 return dc->out->max_pixclock;
2141         else
2142                 return 0;
2143 }
2144 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2145
2146 void tegra_dc_enable_crc(struct tegra_dc *dc)
2147 {
2148         u32 val;
2149         tegra_dc_io_start(dc);
2150
2151         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2152                 CRC_ENABLE_ENABLE;
2153         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2154         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2155         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2156 }
2157
2158 void tegra_dc_disable_crc(struct tegra_dc *dc)
2159 {
2160         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2161         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
2162         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2163
2164         tegra_dc_io_end(dc);
2165 }
2166
2167 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2168 {
2169         int crc = 0;
2170
2171         if (!dc) {
2172                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
2173                 goto crc_error;
2174         }
2175
2176 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2177         /* TODO: Replace mdelay with code to sync VBlANK, since
2178          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
2179         mdelay(TEGRA_CRC_LATCHED_DELAY);
2180 #endif
2181
2182         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2183 crc_error:
2184         return crc;
2185 }
2186
2187 static void tegra_dc_vblank(struct work_struct *work)
2188 {
2189         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2190         bool nvsd_updated = false;
2191
2192         mutex_lock(&dc->lock);
2193
2194         /* use the new frame's bandwidth setting instead of max(current, new),
2195          * skip this if we're using tegra_dc_one_shot_worker() */
2196         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2197                 tegra_dc_program_bandwidth(dc);
2198
2199         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2200         if (!tegra_dc_windows_are_dirty(dc))
2201                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2202
2203         /* Update the SD brightness */
2204         if (dc->enabled && dc->out->sd_settings) {
2205                 nvsd_updated = nvsd_update_brightness(dc);
2206                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2207                  * V_BLANK_NVSD bit of vblank ref-count. */
2208                 if (nvsd_updated) {
2209                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2210                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2211                 } else {
2212                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2213                 }
2214         }
2215
2216         /* Mask vblank interrupt if ref-count is zero. */
2217         if (!dc->vblank_ref_count)
2218                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2219
2220         mutex_unlock(&dc->lock);
2221
2222         /* Do the actual brightness update outside of the mutex */
2223         if (nvsd_updated && dc->out->sd_settings &&
2224             dc->out->sd_settings->bl_device) {
2225
2226                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
2227                 struct backlight_device *bl = platform_get_drvdata(pdev);
2228                 if (bl)
2229                         backlight_update_status(bl);
2230         }
2231 }
2232
2233 static void tegra_dc_one_shot_worker(struct work_struct *work)
2234 {
2235         struct tegra_dc *dc = container_of(
2236                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2237         mutex_lock(&dc->lock);
2238
2239         /* memory client has gone idle */
2240         tegra_dc_clear_bandwidth(dc);
2241
2242         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2243                 tegra_dc_host_suspend(dc);
2244
2245         mutex_unlock(&dc->lock);
2246 }
2247
2248 /* return an arbitrarily large number if count overflow occurs.
2249  * make it a nice base-10 number to show up in stats output */
2250 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2251 {
2252         unsigned count = tegra_dc_readl(dc, reg);
2253         tegra_dc_writel(dc, 0, reg);
2254         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2255 }
2256
2257 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2258 {
2259         u32 val;
2260         int i;
2261
2262         dc->stats.underflows++;
2263         if (dc->underflow_mask & WIN_A_UF_INT) {
2264                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2265                         DC_WINBUF_AD_UFLOW_STATUS);
2266                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
2267         }
2268         if (dc->underflow_mask & WIN_B_UF_INT) {
2269                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2270                         DC_WINBUF_BD_UFLOW_STATUS);
2271                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
2272         }
2273         if (dc->underflow_mask & WIN_C_UF_INT) {
2274                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2275                         DC_WINBUF_CD_UFLOW_STATUS);
2276                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
2277         }
2278
2279         /* Check for any underflow reset conditions */
2280         for (i = 0; i < DC_N_WINDOWS; i++) {
2281                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
2282                         dc->windows[i].underflows++;
2283
2284 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2285                         if (dc->windows[i].underflows > 4) {
2286                                 schedule_work(&dc->reset_work);
2287                                 /* reset counter */
2288                                 dc->windows[i].underflows = 0;
2289                                 trace_printk("%s:Reset work scheduled for "
2290                                                 "window %c\n",
2291                                                 dc->ndev->name, (65 + i));
2292                         }
2293 #endif
2294 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2295                         if (dc->windows[i].underflows > 4) {
2296                                 printk("%s:dc in underflow state."
2297                                         " enable UF_LINE_FLUSH to clear up\n",
2298                                         __func__);
2299                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2300                                                 DC_DISP_DISP_MISC_CONTROL);
2301                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2302                                                 DC_CMD_STATE_CONTROL);
2303                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2304                                                 DC_CMD_STATE_CONTROL);
2305
2306                                 tegra_dc_writel(dc, 0,
2307                                                 DC_DISP_DISP_MISC_CONTROL);
2308                                 tegra_dc_writel(dc, GENERAL_UPDATE,
2309                                                 DC_CMD_STATE_CONTROL);
2310                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2311                                                 DC_CMD_STATE_CONTROL);
2312                         }
2313 #endif
2314                 } else {
2315                         dc->windows[i].underflows = 0;
2316                 }
2317         }
2318
2319         /* Clear the underflow mask now that we've checked it. */
2320         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2321         dc->underflow_mask = 0;
2322         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2323         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
2324         print_underflow_info(dc);
2325 }
2326
2327 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2328 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
2329 {
2330 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2331         u32 val;
2332
2333         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2334         if (val & (WIN_A_UPDATE | WIN_B_UPDATE | WIN_C_UPDATE))
2335             return true;
2336 #endif
2337         return false;
2338 }
2339
2340 static void tegra_dc_trigger_windows(struct tegra_dc *dc)
2341 {
2342         u32 val, i;
2343         u32 completed = 0;
2344         u32 dirty = 0;
2345
2346         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2347         for (i = 0; i < DC_N_WINDOWS; i++) {
2348                 if (!(val & (WIN_A_UPDATE << i))) {
2349                         dc->windows[i].dirty = 0;
2350                         completed = 1;
2351                 } else {
2352                         dirty = 1;
2353                 }
2354         }
2355
2356         if (!dirty) {
2357                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2358                         tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2359         }
2360
2361         if (completed)
2362                 wake_up(&dc->wq);
2363 }
2364
2365 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
2366 {
2367         if (status & V_BLANK_INT) {
2368                 /* Sync up windows. */
2369                 tegra_dc_trigger_windows(dc);
2370
2371                 /* Schedule any additional bottom-half vblank actvities. */
2372                 schedule_work(&dc->vblank_work);
2373         }
2374
2375         if (status & FRAME_END_INT) {
2376                 /* Mark the frame_end as complete. */
2377                 if (!completion_done(&dc->frame_end_complete))
2378                         complete(&dc->frame_end_complete);
2379         }
2380 }
2381
2382 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
2383 {
2384         /* Schedule any additional bottom-half vblank actvities. */
2385         if (status & V_BLANK_INT)
2386                 schedule_work(&dc->vblank_work);
2387
2388         if (status & FRAME_END_INT) {
2389                 /* Mark the frame_end as complete. */
2390                 if (!completion_done(&dc->frame_end_complete))
2391                         complete(&dc->frame_end_complete);
2392
2393                 tegra_dc_trigger_windows(dc);
2394         }
2395 }
2396 #endif
2397
2398 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2399 {
2400 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2401         struct tegra_dc *dc = ptr;
2402         unsigned long status;
2403         unsigned long underflow_mask;
2404         u32 val;
2405
2406         if (!nvhost_module_powered(nvhost_get_host(dc->ndev)->dev)) {
2407                 WARN(1, "IRQ when DC not powered!\n");
2408                 tegra_dc_io_start(dc);
2409                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2410                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2411                 tegra_dc_io_end(dc);
2412                 return IRQ_HANDLED;
2413         }
2414
2415         /* clear all status flags except underflow, save those for the worker */
2416         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2417         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
2418         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2419         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
2420
2421         /*
2422          * Overlays can get thier internal state corrupted during and underflow
2423          * condition.  The only way to fix this state is to reset the DC.
2424          * if we get 4 consecutive frames with underflows, assume we're
2425          * hosed and reset.
2426          */
2427         underflow_mask = status & ALL_UF_INT;
2428
2429         /* Check underflow */
2430         if (underflow_mask) {
2431                 dc->underflow_mask |= underflow_mask;
2432                 schedule_delayed_work(&dc->underflow_work,
2433                         msecs_to_jiffies(1));
2434         }
2435
2436         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2437                 tegra_dc_one_shot_irq(dc, status);
2438         else
2439                 tegra_dc_continuous_irq(dc, status);
2440
2441         return IRQ_HANDLED;
2442 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
2443         return IRQ_NONE;
2444 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
2445 }
2446
2447 static void tegra_dc_set_color_control(struct tegra_dc *dc)
2448 {
2449         u32 color_control;
2450
2451         switch (dc->out->depth) {
2452         case 3:
2453                 color_control = BASE_COLOR_SIZE111;
2454                 break;
2455
2456         case 6:
2457                 color_control = BASE_COLOR_SIZE222;
2458                 break;
2459
2460         case 8:
2461                 color_control = BASE_COLOR_SIZE332;
2462                 break;
2463
2464         case 9:
2465                 color_control = BASE_COLOR_SIZE333;
2466                 break;
2467
2468         case 12:
2469                 color_control = BASE_COLOR_SIZE444;
2470                 break;
2471
2472         case 15:
2473                 color_control = BASE_COLOR_SIZE555;
2474                 break;
2475
2476         case 16:
2477                 color_control = BASE_COLOR_SIZE565;
2478                 break;
2479
2480         case 18:
2481                 color_control = BASE_COLOR_SIZE666;
2482                 break;
2483
2484         default:
2485                 color_control = BASE_COLOR_SIZE888;
2486                 break;
2487         }
2488
2489         switch (dc->out->dither) {
2490         case TEGRA_DC_DISABLE_DITHER:
2491                 color_control |= DITHER_CONTROL_DISABLE;
2492                 break;
2493         case TEGRA_DC_ORDERED_DITHER:
2494                 color_control |= DITHER_CONTROL_ORDERED;
2495                 break;
2496         case TEGRA_DC_ERRDIFF_DITHER:
2497                 /* The line buffer for error-diffusion dither is limited
2498                  * to 1280 pixels per line. This limits the maximum
2499                  * horizontal active area size to 1280 pixels when error
2500                  * diffusion is enabled.
2501                  */
2502                 BUG_ON(dc->mode.h_active > 1280);
2503                 color_control |= DITHER_CONTROL_ERRDIFF;
2504                 break;
2505         }
2506
2507 #ifdef CONFIG_TEGRA_DC_CMU
2508         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
2509                 color_control |= CMU_ENABLE;
2510 #endif
2511
2512         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2513 }
2514
2515 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2516 {
2517         u32 syncpt_id;
2518
2519         switch (dc->ndev->id) {
2520         case 0:
2521                 switch (idx) {
2522                 case 0:
2523                         syncpt_id = NVSYNCPT_DISP0_A;
2524                         break;
2525                 case 1:
2526                         syncpt_id = NVSYNCPT_DISP0_B;
2527                         break;
2528                 case 2:
2529                         syncpt_id = NVSYNCPT_DISP0_C;
2530                         break;
2531                 default:
2532                         BUG();
2533                         break;
2534                 }
2535                 break;
2536         case 1:
2537                 switch (idx) {
2538                 case 0:
2539                         syncpt_id = NVSYNCPT_DISP1_A;
2540                         break;
2541                 case 1:
2542                         syncpt_id = NVSYNCPT_DISP1_B;
2543                         break;
2544                 case 2:
2545                         syncpt_id = NVSYNCPT_DISP1_C;
2546                         break;
2547                 default:
2548                         BUG();
2549                         break;
2550                 }
2551                 break;
2552         default:
2553                 BUG();
2554                 break;
2555         }
2556
2557         return syncpt_id;
2558 }
2559
2560 static int tegra_dc_init(struct tegra_dc *dc)
2561 {
2562         int i;
2563
2564         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2565         if (dc->ndev->id == 0) {
2566                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2567                                       TEGRA_MC_PRIO_MED);
2568                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2569                                       TEGRA_MC_PRIO_MED);
2570                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2571                                       TEGRA_MC_PRIO_MED);
2572                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2573                                       TEGRA_MC_PRIO_MED);
2574                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2575                                       TEGRA_MC_PRIO_HIGH);
2576         } else if (dc->ndev->id == 1) {
2577                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2578                                       TEGRA_MC_PRIO_MED);
2579                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2580                                       TEGRA_MC_PRIO_MED);
2581                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2582                                       TEGRA_MC_PRIO_MED);
2583                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2584                                       TEGRA_MC_PRIO_MED);
2585                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2586                                       TEGRA_MC_PRIO_HIGH);
2587         }
2588         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2589                         DC_CMD_CONT_SYNCPT_VSYNC);
2590         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2591         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
2592         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2593         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2594 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2595         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2596 #endif
2597         /* enable interrupts for vblank, frame_end and underflows */
2598         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
2599                 DC_CMD_INT_ENABLE);
2600         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
2601
2602         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2603
2604         tegra_dc_set_color_control(dc);
2605         for (i = 0; i < DC_N_WINDOWS; i++) {
2606                 struct tegra_dc_win *win = &dc->windows[i];
2607                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2608                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2609                 tegra_dc_set_csc(dc, &win->csc);
2610                 tegra_dc_set_lut(dc, win);
2611                 tegra_dc_set_scaling_filter(dc);
2612         }
2613
2614         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
2615         tegra_dc_set_cmu(dc, &dc->cmu);
2616
2617         for (i = 0; i < dc->n_windows; i++) {
2618                 u32 syncpt = get_syncpt(dc, i);
2619
2620                 dc->syncpt[i].id = syncpt;
2621
2622                 dc->syncpt[i].min = dc->syncpt[i].max =
2623                         nvhost_syncpt_read(&nvhost_get_host(dc->ndev)->syncpt,
2624                                         syncpt);
2625         }
2626
2627         print_mode(dc, &dc->mode, __func__);
2628
2629         if (dc->mode.pclk)
2630                 if (tegra_dc_program_mode(dc, &dc->mode))
2631                         return -EINVAL;
2632
2633         /* Initialize SD AFTER the modeset.
2634            nvsd_init handles the sd_settings = NULL case. */
2635         nvsd_init(dc, dc->out->sd_settings);
2636
2637         return 0;
2638 }
2639
2640 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2641 {
2642         int failed_init = 0;
2643
2644         if (dc->out->enable)
2645                 dc->out->enable();
2646
2647         tegra_dc_setup_clk(dc, dc->clk);
2648         tegra_dc_clk_enable(dc);
2649
2650         /* do not accept interrupts during initialization */
2651         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2652         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2653
2654         enable_irq(dc->irq);
2655
2656         failed_init = tegra_dc_init(dc);
2657         if (failed_init) {
2658                 _tegra_dc_controller_disable(dc);
2659                 return false;
2660         }
2661
2662         if (dc->out_ops && dc->out_ops->enable)
2663                 dc->out_ops->enable(dc);
2664
2665         if (dc->out->postpoweron)
2666                 dc->out->postpoweron();
2667
2668         /* force a full blending update */
2669         dc->blend.z[0] = -1;
2670
2671         tegra_dc_ext_enable(dc->ext);
2672
2673         trace_printk("%s:enable\n", dc->ndev->name);
2674         return true;
2675 }
2676
2677 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2678 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2679 {
2680         bool ret = true;
2681
2682         if (dc->out->enable)
2683                 dc->out->enable();
2684
2685         tegra_dc_setup_clk(dc, dc->clk);
2686         tegra_dc_clk_enable(dc);
2687
2688         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2689                 mutex_lock(&tegra_dcs[1]->lock);
2690                 disable_irq(tegra_dcs[1]->irq);
2691         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2692                 mutex_lock(&tegra_dcs[0]->lock);
2693                 disable_irq(tegra_dcs[0]->irq);
2694         }
2695
2696         msleep(5);
2697         tegra_periph_reset_assert(dc->clk);
2698         msleep(2);
2699 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
2700         tegra_periph_reset_deassert(dc->clk);
2701         msleep(1);
2702 #endif
2703
2704         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2705                 enable_irq(tegra_dcs[1]->irq);
2706                 mutex_unlock(&tegra_dcs[1]->lock);
2707         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2708                 enable_irq(tegra_dcs[0]->irq);
2709                 mutex_unlock(&tegra_dcs[0]->lock);
2710         }
2711
2712         enable_irq(dc->irq);
2713
2714         if (tegra_dc_init(dc)) {
2715                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2716                 ret = false;
2717         }
2718
2719         if (dc->out_ops && dc->out_ops->enable)
2720                 dc->out_ops->enable(dc);
2721
2722         if (dc->out->postpoweron)
2723                 dc->out->postpoweron();
2724
2725         /* force a full blending update */
2726         dc->blend.z[0] = -1;
2727
2728         tegra_dc_ext_enable(dc->ext);
2729
2730         if (!ret) {
2731                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2732                 _tegra_dc_controller_disable(dc);
2733         }
2734
2735         trace_printk("%s:reset enable\n", dc->ndev->name);
2736         return ret;
2737 }
2738 #endif
2739
2740 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2741 {
2742         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
2743 }
2744
2745 static bool _tegra_dc_enable(struct tegra_dc *dc)
2746 {
2747         if (dc->mode.pclk == 0) {
2748                 switch (dc->out->type) {
2749                 case TEGRA_DC_OUT_HDMI:
2750                 /* DC enable called but no videomode is loaded.
2751                      Check if HDMI is connected, then set fallback mdoe */
2752                 if (tegra_dc_hpd(dc)) {
2753                         if (_tegra_dc_set_default_videomode(dc))
2754                                 return false;
2755                 } else
2756                         return false;
2757
2758                 break;
2759
2760                 /* Do nothing for other outputs for now */
2761                 case TEGRA_DC_OUT_RGB:
2762
2763                 case TEGRA_DC_OUT_DSI:
2764
2765                 default:
2766                         return false;
2767                 }
2768         }
2769
2770         if (!dc->out)
2771                 return false;
2772
2773         tegra_dc_io_start(dc);
2774
2775         return _tegra_dc_controller_enable(dc);
2776 }
2777
2778 void tegra_dc_enable(struct tegra_dc *dc)
2779 {
2780         mutex_lock(&dc->lock);
2781
2782         if (!dc->enabled)
2783                 dc->enabled = _tegra_dc_enable(dc);
2784
2785         mutex_unlock(&dc->lock);
2786         print_mode_info(dc, dc->mode);
2787 }
2788
2789 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2790 {
2791         unsigned i;
2792
2793         if (dc->out_ops && dc->out_ops->disable)
2794                 dc->out_ops->disable(dc);
2795
2796         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2797         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
2798         disable_irq(dc->irq);
2799
2800         tegra_dc_clear_bandwidth(dc);
2801         tegra_dc_clk_disable(dc);
2802
2803         if (dc->out && dc->out->disable)
2804                 dc->out->disable();
2805
2806         for (i = 0; i < dc->n_windows; i++) {
2807                 struct tegra_dc_win *w = &dc->windows[i];
2808
2809                 /* reset window bandwidth */
2810                 w->bandwidth = 0;
2811                 w->new_bandwidth = 0;
2812
2813                 /* disable windows */
2814                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2815
2816                 /* flush any pending syncpt waits */
2817                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2818                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
2819                                 dc->syncpt[i].id);
2820                         dc->syncpt[i].min++;
2821                         nvhost_syncpt_cpu_incr(
2822                                 &nvhost_get_host(dc->ndev)->syncpt,
2823                                 dc->syncpt[i].id);
2824                 }
2825         }
2826         trace_printk("%s:disabled\n", dc->ndev->name);
2827 }
2828
2829 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2830 {
2831 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2832         u32 val;
2833         if (dc->enabled)  {
2834                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2835                 if (enable)
2836                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2837                 else
2838                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2839                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2840         }
2841 #endif
2842 }
2843
2844 bool tegra_dc_stats_get(struct tegra_dc *dc)
2845 {
2846 #if 0 /* right now it is always enabled */
2847         u32 val;
2848         bool res;
2849
2850         if (dc->enabled)  {
2851                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2852                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2853         } else {
2854                 res = false;
2855         }
2856
2857         return res;
2858 #endif
2859         return true;
2860 }
2861
2862 /* make the screen blank by disabling all windows */
2863 void tegra_dc_blank(struct tegra_dc *dc)
2864 {
2865         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2866         unsigned i;
2867
2868         for (i = 0; i < DC_N_WINDOWS; i++) {
2869                 dcwins[i] = tegra_dc_get_window(dc, i);
2870                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2871         }
2872
2873         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2874         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2875 }
2876
2877 static void _tegra_dc_disable(struct tegra_dc *dc)
2878 {
2879         _tegra_dc_controller_disable(dc);
2880         tegra_dc_io_end(dc);
2881 }
2882
2883 void tegra_dc_disable(struct tegra_dc *dc)
2884 {
2885         tegra_dc_ext_disable(dc->ext);
2886
2887         /* it's important that new underflow work isn't scheduled before the
2888          * lock is acquired. */
2889         cancel_delayed_work_sync(&dc->underflow_work);
2890         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2891                 mutex_lock(&dc->one_shot_lock);
2892                 cancel_delayed_work_sync(&dc->one_shot_work);
2893         }
2894
2895         mutex_lock(&dc->lock);
2896
2897         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2898                 tegra_dc_host_resume(dc);
2899
2900         if (dc->enabled) {
2901                 dc->enabled = false;
2902
2903                 if (!dc->suspended)
2904                         _tegra_dc_disable(dc);
2905         }
2906
2907 #ifdef CONFIG_SWITCH
2908         switch_set_state(&dc->modeset_switch, 0);
2909 #endif
2910
2911         mutex_unlock(&dc->lock);
2912         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2913                 mutex_unlock(&dc->one_shot_lock);
2914         print_mode_info(dc, dc->mode);
2915 }
2916
2917 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2918 static void tegra_dc_reset_worker(struct work_struct *work)
2919 {
2920         struct tegra_dc *dc =
2921                 container_of(work, struct tegra_dc, reset_work);
2922
2923         unsigned long val = 0;
2924
2925         mutex_lock(&shared_lock);
2926
2927         dev_warn(&dc->ndev->dev, "overlay stuck in underflow state.  resetting.\n");
2928
2929         tegra_dc_ext_disable(dc->ext);
2930
2931         mutex_lock(&dc->lock);
2932
2933         if (dc->enabled == false)
2934                 goto unlock;
2935
2936         dc->enabled = false;
2937
2938         /*
2939          * off host read bus
2940          */
2941         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2942         val &= ~(0x00000100);
2943         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2944
2945         /*
2946          * set DC to STOP mode
2947          */
2948         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2949
2950         msleep(10);
2951
2952         _tegra_dc_controller_disable(dc);
2953
2954         /* _tegra_dc_controller_reset_enable deasserts reset */
2955         _tegra_dc_controller_reset_enable(dc);
2956
2957         dc->enabled = true;
2958
2959         /* reopen host read bus */
2960         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2961         val &= ~(0x00000100);
2962         val |= 0x100;
2963         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2964
2965 unlock:
2966         mutex_unlock(&dc->lock);
2967         mutex_unlock(&shared_lock);
2968         trace_printk("%s:reset complete\n", dc->ndev->name);
2969 }
2970 #endif
2971
2972 static void tegra_dc_underflow_worker(struct work_struct *work)
2973 {
2974         struct tegra_dc *dc = container_of(
2975                 to_delayed_work(work), struct tegra_dc, underflow_work);
2976
2977         mutex_lock(&dc->lock);
2978         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
2979                 tegra_dc_host_resume(dc);
2980
2981         if (dc->enabled) {
2982                 tegra_dc_underflow_handler(dc);
2983         }
2984         mutex_unlock(&dc->lock);
2985 }
2986
2987 #ifdef CONFIG_SWITCH
2988 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2989 {
2990         struct tegra_dc *dc =
2991                 container_of(sdev, struct tegra_dc, modeset_switch);
2992
2993         if (!sdev->state)
2994                 return sprintf(buf, "offline\n");
2995
2996         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2997 }
2998 #endif
2999
3000 static int tegra_dc_probe(struct nvhost_device *ndev,
3001         struct nvhost_device_id *id_table)
3002 {
3003         struct tegra_dc *dc;
3004         struct clk *clk;
3005         struct clk *emc_clk;
3006         struct resource *res;
3007         struct resource *base_res;
3008         struct resource *fb_mem = NULL;
3009         int ret = 0;
3010         void __iomem *base;
3011         int irq;
3012         int i;
3013
3014         if (!ndev->dev.platform_data) {
3015                 dev_err(&ndev->dev, "no platform data\n");
3016                 return -ENOENT;
3017         }
3018
3019         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3020         if (!dc) {
3021                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3022                 return -ENOMEM;
3023         }
3024
3025         irq = nvhost_get_irq_byname(ndev, "irq");
3026         if (irq <= 0) {
3027                 dev_err(&ndev->dev, "no irq\n");
3028                 ret = -ENOENT;
3029                 goto err_free;
3030         }
3031
3032         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
3033         if (!res) {
3034                 dev_err(&ndev->dev, "no mem resource\n");
3035                 ret = -ENOENT;
3036                 goto err_free;
3037         }
3038
3039         base_res = request_mem_region(res->start, resource_size(res), ndev->name);
3040         if (!base_res) {
3041                 dev_err(&ndev->dev, "request_mem_region failed\n");
3042                 ret = -EBUSY;
3043                 goto err_free;
3044         }
3045
3046         base = ioremap(res->start, resource_size(res));
3047         if (!base) {
3048                 dev_err(&ndev->dev, "registers can't be mapped\n");
3049                 ret = -EBUSY;
3050                 goto err_release_resource_reg;
3051         }
3052
3053         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
3054
3055         clk = clk_get(&ndev->dev, NULL);
3056         if (IS_ERR_OR_NULL(clk)) {
3057                 dev_err(&ndev->dev, "can't get clock\n");
3058                 ret = -ENOENT;
3059                 goto err_iounmap_reg;
3060         }
3061
3062         emc_clk = clk_get(&ndev->dev, "emc");
3063         if (IS_ERR_OR_NULL(emc_clk)) {
3064                 dev_err(&ndev->dev, "can't get emc clock\n");
3065                 ret = -ENOENT;
3066                 goto err_put_clk;
3067         }
3068
3069         dc->clk = clk;
3070         dc->emc_clk = emc_clk;
3071         dc->shift_clk_div = 1;
3072         /* Initialize one shot work delay, it will be assigned by dsi
3073          * according to refresh rate later. */
3074         dc->one_shot_delay_ms = 40;
3075
3076         dc->base_res = base_res;
3077         dc->base = base;
3078         dc->irq = irq;
3079         dc->ndev = ndev;
3080         dc->pdata = ndev->dev.platform_data;
3081
3082         /*
3083          * The emc is a shared clock, it will be set based on
3084          * the requirements for each user on the bus.
3085          */
3086         dc->emc_clk_rate = 0;
3087
3088         mutex_init(&dc->lock);
3089         mutex_init(&dc->one_shot_lock);
3090         init_completion(&dc->frame_end_complete);
3091         init_waitqueue_head(&dc->wq);
3092 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3093         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3094 #endif
3095         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3096         dc->vblank_ref_count = 0;
3097         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3098         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3099
3100         tegra_dc_init_lut_defaults(&dc->fb_lut);
3101
3102         dc->n_windows = DC_N_WINDOWS;
3103         for (i = 0; i < dc->n_windows; i++) {
3104                 struct tegra_dc_win *win = &dc->windows[i];
3105                 win->idx = i;
3106                 win->dc = dc;
3107                 tegra_dc_init_csc_defaults(&win->csc);
3108                 tegra_dc_init_lut_defaults(&win->lut);
3109         }
3110
3111         ret = tegra_dc_set(dc, ndev->id);
3112         if (ret < 0) {
3113                 dev_err(&ndev->dev, "can't add dc\n");
3114                 goto err_free_irq;
3115         }
3116
3117         nvhost_set_drvdata(ndev, dc);
3118
3119 #ifdef CONFIG_SWITCH
3120         dc->modeset_switch.name = dev_name(&ndev->dev);
3121         dc->modeset_switch.state = 0;
3122         dc->modeset_switch.print_state = switch_modeset_print_mode;
3123         switch_dev_register(&dc->modeset_switch);
3124 #endif
3125
3126         tegra_dc_feature_register(dc);
3127
3128         if (dc->pdata->default_out)
3129                 tegra_dc_set_out(dc, dc->pdata->default_out);
3130         else
3131                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
3132
3133         dc->vblank_syncpt = (dc->ndev->id == 0) ?
3134                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
3135
3136         dc->ext = tegra_dc_ext_register(ndev, dc);
3137         if (IS_ERR_OR_NULL(dc->ext)) {
3138                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3139                 dc->ext = NULL;
3140         }
3141
3142         mutex_lock(&dc->lock);
3143         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
3144                 dc->enabled = _tegra_dc_enable(dc);
3145         mutex_unlock(&dc->lock);
3146
3147         /* interrupt handler must be registered before tegra_fb_register() */
3148         if (request_irq(irq, tegra_dc_irq, 0,
3149                         dev_name(&ndev->dev), dc)) {
3150                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3151                 ret = -EBUSY;
3152                 goto err_put_emc_clk;
3153         }
3154
3155         tegra_dc_create_debugfs(dc);
3156
3157         dev_info(&ndev->dev, "probed\n");
3158
3159         if (dc->pdata->fb) {
3160                 if (dc->pdata->fb->bits_per_pixel == -1) {
3161                         unsigned long fmt;
3162                         tegra_dc_writel(dc,
3163                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3164                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3165
3166                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3167                         dc->pdata->fb->bits_per_pixel =
3168                                 tegra_dc_fmt_bpp(fmt);
3169                 }
3170
3171                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3172                 if (IS_ERR_OR_NULL(dc->fb))
3173                         dc->fb = NULL;
3174         }
3175
3176         if (dc->out && dc->out->hotplug_init)
3177                 dc->out->hotplug_init();
3178
3179         if (dc->out_ops && dc->out_ops->detect)
3180                 dc->out_ops->detect(dc);
3181         else
3182                 dc->connected = true;
3183
3184         tegra_dc_create_sysfs(&dc->ndev->dev);
3185
3186         return 0;
3187
3188 err_free_irq:
3189         free_irq(irq, dc);
3190 err_put_emc_clk:
3191         clk_put(emc_clk);
3192 err_put_clk:
3193         clk_put(clk);
3194 err_iounmap_reg:
3195         iounmap(base);
3196         if (fb_mem)
3197                 release_resource(fb_mem);
3198 err_release_resource_reg:
3199         release_resource(base_res);
3200 err_free:
3201         kfree(dc);
3202
3203         return ret;
3204 }
3205
3206 static int tegra_dc_remove(struct nvhost_device *ndev)
3207 {
3208         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3209
3210         tegra_dc_remove_sysfs(&dc->ndev->dev);
3211         tegra_dc_remove_debugfs(dc);
3212
3213         if (dc->fb) {
3214                 tegra_fb_unregister(dc->fb);
3215                 if (dc->fb_mem)
3216                         release_resource(dc->fb_mem);
3217         }
3218
3219         tegra_dc_ext_disable(dc->ext);
3220
3221         if (dc->ext)
3222                 tegra_dc_ext_unregister(dc->ext);
3223
3224         if (dc->enabled)
3225                 _tegra_dc_disable(dc);
3226
3227 #ifdef CONFIG_SWITCH
3228         switch_dev_unregister(&dc->modeset_switch);
3229 #endif
3230         free_irq(dc->irq, dc);
3231         clk_put(dc->emc_clk);
3232         clk_put(dc->clk);
3233         iounmap(dc->base);
3234         if (dc->fb_mem)
3235                 release_resource(dc->base_res);
3236         kfree(dc);
3237         tegra_dc_set(NULL, ndev->id);
3238         return 0;
3239 }
3240
3241 #ifdef CONFIG_PM
3242 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
3243 {
3244         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3245
3246         trace_printk("%s:suspend\n", dc->ndev->name);
3247         dev_info(&ndev->dev, "suspend\n");
3248
3249         tegra_dc_ext_disable(dc->ext);
3250
3251         mutex_lock(&dc->lock);
3252
3253         if (dc->out_ops && dc->out_ops->suspend)
3254                 dc->out_ops->suspend(dc);
3255
3256         if (dc->enabled) {
3257                 _tegra_dc_disable(dc);
3258
3259                 dc->suspended = true;
3260         }
3261
3262         if (dc->out && dc->out->postsuspend) {
3263                 dc->out->postsuspend();
3264                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
3265                         /*
3266                          * avoid resume event due to voltage falling
3267                          */
3268                         msleep(100);
3269         }
3270
3271         mutex_unlock(&dc->lock);
3272
3273         return 0;
3274 }
3275
3276 static int tegra_dc_resume(struct nvhost_device *ndev)
3277 {
3278         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3279
3280         trace_printk("%s:resume\n", dc->ndev->name);
3281         dev_info(&ndev->dev, "resume\n");
3282
3283         mutex_lock(&dc->lock);
3284         dc->suspended = false;
3285
3286         if (dc->enabled)
3287                 _tegra_dc_enable(dc);
3288
3289         if (dc->out && dc->out->hotplug_init)
3290                 dc->out->hotplug_init();
3291
3292         if (dc->out_ops && dc->out_ops->resume)
3293                 dc->out_ops->resume(dc);
3294         mutex_unlock(&dc->lock);
3295
3296         return 0;
3297 }
3298
3299 #endif /* CONFIG_PM */
3300
3301 static void tegra_dc_shutdown(struct nvhost_device *ndev)
3302 {
3303         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
3304
3305         if (!dc || !dc->enabled)
3306                 return;
3307
3308         tegra_dc_blank(dc);
3309         tegra_dc_disable(dc);
3310 }
3311
3312 extern int suspend_set(const char *val, struct kernel_param *kp)
3313 {
3314         if (!strcmp(val, "dump"))
3315                 dump_regs(tegra_dcs[0]);
3316 #ifdef CONFIG_PM
3317         else if (!strcmp(val, "suspend"))
3318                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3319         else if (!strcmp(val, "resume"))
3320                 tegra_dc_resume(tegra_dcs[0]->ndev);
3321 #endif
3322
3323         return 0;
3324 }
3325
3326 extern int suspend_get(char *buffer, struct kernel_param *kp)
3327 {
3328         return 0;
3329 }
3330
3331 int suspend;
3332
3333 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3334
3335 struct nvhost_driver tegra_dc_driver = {
3336         .driver = {
3337                 .name = "tegradc",
3338                 .owner = THIS_MODULE,
3339         },
3340         .probe = tegra_dc_probe,
3341         .remove = tegra_dc_remove,
3342 #ifdef CONFIG_PM
3343         .suspend = tegra_dc_suspend,
3344         .resume = tegra_dc_resume,
3345 #endif
3346         .shutdown = tegra_dc_shutdown,
3347 };
3348
3349 static int __init tegra_dc_module_init(void)
3350 {
3351         int ret = tegra_dc_ext_module_init();
3352         if (ret)
3353                 return ret;
3354         return nvhost_driver_register(&tegra_dc_driver);
3355 }
3356
3357 static void __exit tegra_dc_module_exit(void)
3358 {
3359         nvhost_driver_unregister(&tegra_dc_driver);
3360         tegra_dc_ext_module_exit();
3361 }
3362
3363 module_exit(tegra_dc_module_exit);
3364 module_init(tegra_dc_module_init);