tegra:dc: Init default mode on HDMI
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53
54 #include "dc_reg.h"
55 #include "dc_config.h"
56 #include "dc_priv.h"
57 #include "dev.h"
58 #include "nvsd.h"
59
60 #define TEGRA_CRC_LATCHED_DELAY         34
61
62 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
63 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
64
65 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
66         .refresh = 60,
67         .xres = 640,
68         .yres = 480,
69         .pixclock = KHZ2PICOS(25200),
70         .hsync_len = 96,        /* h_sync_width */
71         .vsync_len = 2,         /* v_sync_width */
72         .left_margin = 48,      /* h_back_porch */
73         .upper_margin = 33,     /* v_back_porch */
74         .right_margin = 16,     /* h_front_porch */
75         .lower_margin = 10,     /* v_front_porch */
76         .vmode = 0,
77         .sync = 0,
78 };
79
80 static struct tegra_dc_mode override_disp_mode[3];
81
82 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
83
84 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
85
86 DEFINE_MUTEX(tegra_dc_lock);
87 DEFINE_MUTEX(shared_lock);
88
89 static const struct {
90         bool h;
91         bool v;
92 } can_filter[] = {
93         /* Window A has no filtering */
94         { false, false },
95         /* Window B has both H and V filtering */
96         { true,  true  },
97         /* Window C has only H filtering */
98         { false, true  },
99 };
100
101 #ifdef CONFIG_TEGRA_DC_CMU
102 static struct tegra_dc_cmu default_cmu = {
103         /* lut1 maps sRGB to linear space. */
104         {
105                 0,    1,    2,    4,    5,    6,    7,    9,
106                 10,   11,   12,   14,   15,   16,   18,   20,
107                 21,   23,   25,   27,   29,   31,   33,   35,
108                 37,   40,   42,   45,   48,   50,   53,   56,
109                 59,   62,   66,   69,   72,   76,   79,   83,
110                 87,   91,   95,   99,   103,  107,  112,  116,
111                 121,  126,  131,  136,  141,  146,  151,  156,
112                 162,  168,  173,  179,  185,  191,  197,  204,
113                 210,  216,  223,  230,  237,  244,  251,  258,
114                 265,  273,  280,  288,  296,  304,  312,  320,
115                 329,  337,  346,  354,  363,  372,  381,  390,
116                 400,  409,  419,  428,  438,  448,  458,  469,
117                 479,  490,  500,  511,  522,  533,  544,  555,
118                 567,  578,  590,  602,  614,  626,  639,  651,
119                 664,  676,  689,  702,  715,  728,  742,  755,
120                 769,  783,  797,  811,  825,  840,  854,  869,
121                 884,  899,  914,  929,  945,  960,  976,  992,
122                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
123                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
124                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
125                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
126                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
127                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
128                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
129                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
130                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
131                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
132                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
133                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
134                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
135                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
136                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
137         },
138         /* csc */
139         {
140                 0x100, 0x0,   0x0,
141                 0x0,   0x100, 0x0,
142                 0x0,   0x0,   0x100,
143         },
144         /* lut2 maps linear space to sRGB*/
145         {
146                 0,    1,    2,    2,    3,    4,    5,    6,
147                 6,    7,    8,    9,    10,   10,   11,   12,
148                 13,   13,   14,   15,   15,   16,   16,   17,
149                 18,   18,   19,   19,   20,   20,   21,   21,
150                 22,   22,   23,   23,   23,   24,   24,   25,
151                 25,   25,   26,   26,   27,   27,   27,   28,
152                 28,   29,   29,   29,   30,   30,   30,   31,
153                 31,   31,   32,   32,   32,   33,   33,   33,
154                 34,   34,   34,   34,   35,   35,   35,   36,
155                 36,   36,   37,   37,   37,   37,   38,   38,
156                 38,   38,   39,   39,   39,   40,   40,   40,
157                 40,   41,   41,   41,   41,   42,   42,   42,
158                 42,   43,   43,   43,   43,   43,   44,   44,
159                 44,   44,   45,   45,   45,   45,   46,   46,
160                 46,   46,   46,   47,   47,   47,   47,   48,
161                 48,   48,   48,   48,   49,   49,   49,   49,
162                 49,   50,   50,   50,   50,   50,   51,   51,
163                 51,   51,   51,   52,   52,   52,   52,   52,
164                 53,   53,   53,   53,   53,   54,   54,   54,
165                 54,   54,   55,   55,   55,   55,   55,   55,
166                 56,   56,   56,   56,   56,   57,   57,   57,
167                 57,   57,   57,   58,   58,   58,   58,   58,
168                 58,   59,   59,   59,   59,   59,   59,   60,
169                 60,   60,   60,   60,   60,   61,   61,   61,
170                 61,   61,   61,   62,   62,   62,   62,   62,
171                 62,   63,   63,   63,   63,   63,   63,   64,
172                 64,   64,   64,   64,   64,   64,   65,   65,
173                 65,   65,   65,   65,   66,   66,   66,   66,
174                 66,   66,   66,   67,   67,   67,   67,   67,
175                 67,   67,   68,   68,   68,   68,   68,   68,
176                 68,   69,   69,   69,   69,   69,   69,   69,
177                 70,   70,   70,   70,   70,   70,   70,   71,
178                 71,   71,   71,   71,   71,   71,   72,   72,
179                 72,   72,   72,   72,   72,   72,   73,   73,
180                 73,   73,   73,   73,   73,   74,   74,   74,
181                 74,   74,   74,   74,   74,   75,   75,   75,
182                 75,   75,   75,   75,   75,   76,   76,   76,
183                 76,   76,   76,   76,   77,   77,   77,   77,
184                 77,   77,   77,   77,   78,   78,   78,   78,
185                 78,   78,   78,   78,   78,   79,   79,   79,
186                 79,   79,   79,   79,   79,   80,   80,   80,
187                 80,   80,   80,   80,   80,   81,   81,   81,
188                 81,   81,   81,   81,   81,   81,   82,   82,
189                 82,   82,   82,   82,   82,   82,   83,   83,
190                 83,   83,   83,   83,   83,   83,   83,   84,
191                 84,   84,   84,   84,   84,   84,   84,   84,
192                 85,   85,   85,   85,   85,   85,   85,   85,
193                 85,   86,   86,   86,   86,   86,   86,   86,
194                 86,   86,   87,   87,   87,   87,   87,   87,
195                 87,   87,   87,   88,   88,   88,   88,   88,
196                 88,   88,   88,   88,   88,   89,   89,   89,
197                 89,   89,   89,   89,   89,   89,   90,   90,
198                 90,   90,   90,   90,   90,   90,   90,   90,
199                 91,   91,   91,   91,   91,   91,   91,   91,
200                 91,   91,   92,   92,   92,   92,   92,   92,
201                 92,   92,   92,   92,   93,   93,   93,   93,
202                 93,   93,   93,   93,   93,   93,   94,   94,
203                 94,   94,   94,   94,   94,   94,   94,   94,
204                 95,   95,   95,   95,   95,   95,   95,   95,
205                 95,   95,   96,   96,   96,   96,   96,   96,
206                 96,   96,   96,   96,   96,   97,   97,   97,
207                 97,   97,   97,   97,   97,   97,   97,   98,
208                 98,   98,   98,   98,   98,   98,   98,   98,
209                 98,   98,   99,   99,   99,   99,   99,   99,
210                 99,   100,  101,  101,  102,  103,  103,  104,
211                 105,  105,  106,  107,  107,  108,  109,  109,
212                 110,  111,  111,  112,  113,  113,  114,  115,
213                 115,  116,  116,  117,  118,  118,  119,  119,
214                 120,  120,  121,  122,  122,  123,  123,  124,
215                 124,  125,  126,  126,  127,  127,  128,  128,
216                 129,  129,  130,  130,  131,  131,  132,  132,
217                 133,  133,  134,  134,  135,  135,  136,  136,
218                 137,  137,  138,  138,  139,  139,  140,  140,
219                 141,  141,  142,  142,  143,  143,  144,  144,
220                 145,  145,  145,  146,  146,  147,  147,  148,
221                 148,  149,  149,  150,  150,  150,  151,  151,
222                 152,  152,  153,  153,  153,  154,  154,  155,
223                 155,  156,  156,  156,  157,  157,  158,  158,
224                 158,  159,  159,  160,  160,  160,  161,  161,
225                 162,  162,  162,  163,  163,  164,  164,  164,
226                 165,  165,  166,  166,  166,  167,  167,  167,
227                 168,  168,  169,  169,  169,  170,  170,  170,
228                 171,  171,  172,  172,  172,  173,  173,  173,
229                 174,  174,  174,  175,  175,  176,  176,  176,
230                 177,  177,  177,  178,  178,  178,  179,  179,
231                 179,  180,  180,  180,  181,  181,  182,  182,
232                 182,  183,  183,  183,  184,  184,  184,  185,
233                 185,  185,  186,  186,  186,  187,  187,  187,
234                 188,  188,  188,  189,  189,  189,  189,  190,
235                 190,  190,  191,  191,  191,  192,  192,  192,
236                 193,  193,  193,  194,  194,  194,  195,  195,
237                 195,  196,  196,  196,  196,  197,  197,  197,
238                 198,  198,  198,  199,  199,  199,  200,  200,
239                 200,  200,  201,  201,  201,  202,  202,  202,
240                 202,  203,  203,  203,  204,  204,  204,  205,
241                 205,  205,  205,  206,  206,  206,  207,  207,
242                 207,  207,  208,  208,  208,  209,  209,  209,
243                 209,  210,  210,  210,  211,  211,  211,  211,
244                 212,  212,  212,  213,  213,  213,  213,  214,
245                 214,  214,  214,  215,  215,  215,  216,  216,
246                 216,  216,  217,  217,  217,  217,  218,  218,
247                 218,  219,  219,  219,  219,  220,  220,  220,
248                 220,  221,  221,  221,  221,  222,  222,  222,
249                 223,  223,  223,  223,  224,  224,  224,  224,
250                 225,  225,  225,  225,  226,  226,  226,  226,
251                 227,  227,  227,  227,  228,  228,  228,  228,
252                 229,  229,  229,  229,  230,  230,  230,  230,
253                 231,  231,  231,  231,  232,  232,  232,  232,
254                 233,  233,  233,  233,  234,  234,  234,  234,
255                 235,  235,  235,  235,  236,  236,  236,  236,
256                 237,  237,  237,  237,  238,  238,  238,  238,
257                 239,  239,  239,  239,  240,  240,  240,  240,
258                 240,  241,  241,  241,  241,  242,  242,  242,
259                 242,  243,  243,  243,  243,  244,  244,  244,
260                 244,  244,  245,  245,  245,  245,  246,  246,
261                 246,  246,  247,  247,  247,  247,  247,  248,
262                 248,  248,  248,  249,  249,  249,  249,  249,
263                 250,  250,  250,  250,  251,  251,  251,  251,
264                 251,  252,  252,  252,  252,  253,  253,  253,
265                 253,  253,  254,  254,  254,  254,  255,  255,
266         },
267 };
268 #endif
269
270 void tegra_dc_clk_enable(struct tegra_dc *dc)
271 {
272         if (!tegra_is_clk_enabled(dc->clk)) {
273                 clk_enable(dc->clk);
274                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
275         }
276 }
277
278 void tegra_dc_clk_disable(struct tegra_dc *dc)
279 {
280         if (tegra_is_clk_enabled(dc->clk)) {
281                 clk_disable(dc->clk);
282                 tegra_dvfs_set_rate(dc->clk, 0);
283         }
284 }
285
286 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
287 {
288         if (dc->out_ops->hold)
289                 dc->out_ops->hold(dc);
290 }
291
292 void tegra_dc_release_dc_out(struct tegra_dc *dc)
293 {
294         if (dc->out_ops->release)
295                 dc->out_ops->release(dc);
296 }
297
298 #define DUMP_REG(a) do {                        \
299         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
300                  #a, a, tegra_dc_readl(dc, a));               \
301         print(data, buff);                                    \
302         } while (0)
303
304 static void _dump_regs(struct tegra_dc *dc, void *data,
305                        void (* print)(void *data, const char *str))
306 {
307         int i;
308         char buff[256];
309
310         mutex_lock(&dc->lock);
311         tegra_dc_hold_dc_out(dc);
312         tegra_dc_io_start(dc);
313
314         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE);
317         DUMP_REG(DC_CMD_INT_STATUS);
318         DUMP_REG(DC_CMD_INT_MASK);
319         DUMP_REG(DC_CMD_INT_ENABLE);
320         DUMP_REG(DC_CMD_INT_TYPE);
321         DUMP_REG(DC_CMD_INT_POLARITY);
322         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
325         DUMP_REG(DC_CMD_STATE_ACCESS);
326         DUMP_REG(DC_CMD_STATE_CONTROL);
327         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
328         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
329
330         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
332         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
333         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
335         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
336         DUMP_REG(DC_DISP_REF_TO_SYNC);
337         DUMP_REG(DC_DISP_SYNC_WIDTH);
338         DUMP_REG(DC_DISP_BACK_PORCH);
339         DUMP_REG(DC_DISP_DISP_ACTIVE);
340         DUMP_REG(DC_DISP_FRONT_PORCH);
341         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
342         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
346         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
347         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
351         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
352         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
356         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
357         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
360         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
367         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
368         DUMP_REG(DC_DISP_M0_CONTROL);
369         DUMP_REG(DC_DISP_M1_CONTROL);
370         DUMP_REG(DC_DISP_DI_CONTROL);
371         DUMP_REG(DC_DISP_PP_CONTROL);
372         DUMP_REG(DC_DISP_PP_SELECT_A);
373         DUMP_REG(DC_DISP_PP_SELECT_B);
374         DUMP_REG(DC_DISP_PP_SELECT_C);
375         DUMP_REG(DC_DISP_PP_SELECT_D);
376         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
377         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
378         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
379         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
380         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
381         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
382         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
383         DUMP_REG(DC_DISP_BORDER_COLOR);
384         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
385         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
386         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
388         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
389         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
390         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
392         DUMP_REG(DC_DISP_CURSOR_POSITION);
393         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
394         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
395         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
399         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
400         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
403         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
404         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
405         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
406
407
408         for (i = 0; i < 3; i++) {
409                 print(data, "\n");
410                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
411                 print(data, buff);
412
413                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
414                                 DC_CMD_DISPLAY_WINDOW_HEADER);
415                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
416                 DUMP_REG(DC_WIN_WIN_OPTIONS);
417                 DUMP_REG(DC_WIN_BYTE_SWAP);
418                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
419                 DUMP_REG(DC_WIN_COLOR_DEPTH);
420                 DUMP_REG(DC_WIN_POSITION);
421                 DUMP_REG(DC_WIN_SIZE);
422                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
423                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
424                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
425                 DUMP_REG(DC_WIN_DDA_INCREMENT);
426                 DUMP_REG(DC_WIN_LINE_STRIDE);
427 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
428                 DUMP_REG(DC_WIN_BUF_STRIDE);
429                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
430 #endif
431                 DUMP_REG(DC_WIN_BLEND_NOKEY);
432                 DUMP_REG(DC_WIN_BLEND_1WIN);
433                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
434                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
435                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
436                 DUMP_REG(DC_WINBUF_START_ADDR);
437                 DUMP_REG(DC_WINBUF_START_ADDR_U);
438                 DUMP_REG(DC_WINBUF_START_ADDR_V);
439                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
440                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
441                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
442                 DUMP_REG(DC_WIN_CSC_YOF);
443                 DUMP_REG(DC_WIN_CSC_KYRGB);
444                 DUMP_REG(DC_WIN_CSC_KUR);
445                 DUMP_REG(DC_WIN_CSC_KVR);
446                 DUMP_REG(DC_WIN_CSC_KUG);
447                 DUMP_REG(DC_WIN_CSC_KVG);
448                 DUMP_REG(DC_WIN_CSC_KUB);
449                 DUMP_REG(DC_WIN_CSC_KVB);
450         }
451
452         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
453         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
454         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
455         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
456         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
458         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
459         DUMP_REG(DC_DISP_M1_CONTROL);
460         DUMP_REG(DC_COM_PM1_CONTROL);
461         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
462         DUMP_REG(DC_DISP_SD_CONTROL);
463
464         tegra_dc_io_end(dc);
465         tegra_dc_release_dc_out(dc);
466         mutex_unlock(&dc->lock);
467 }
468
469 #undef DUMP_REG
470
471 #ifdef DEBUG
472 static void dump_regs_print(void *data, const char *str)
473 {
474         struct tegra_dc *dc = data;
475         dev_dbg(&dc->ndev->dev, "%s", str);
476 }
477
478 static void dump_regs(struct tegra_dc *dc)
479 {
480         _dump_regs(dc, dc, dump_regs_print);
481 }
482 #else /* !DEBUG */
483
484 static void dump_regs(struct tegra_dc *dc) {}
485
486 #endif /* DEBUG */
487
488 #ifdef CONFIG_DEBUG_FS
489
490 static void dbg_regs_print(void *data, const char *str)
491 {
492         struct seq_file *s = data;
493
494         seq_printf(s, "%s", str);
495 }
496
497 #undef DUMP_REG
498
499 static int dbg_dc_show(struct seq_file *s, void *unused)
500 {
501         struct tegra_dc *dc = s->private;
502
503         _dump_regs(dc, s, dbg_regs_print);
504
505         return 0;
506 }
507
508
509 static int dbg_dc_open(struct inode *inode, struct file *file)
510 {
511         return single_open(file, dbg_dc_show, inode->i_private);
512 }
513
514 static const struct file_operations regs_fops = {
515         .open           = dbg_dc_open,
516         .read           = seq_read,
517         .llseek         = seq_lseek,
518         .release        = single_release,
519 };
520
521 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
522 {
523         struct tegra_dc *dc = s->private;
524         struct tegra_dc_mode *m;
525
526         mutex_lock(&dc->lock);
527         m = &dc->mode;
528         seq_printf(s,
529                 "pclk: %d\n"
530                 "h_ref_to_sync: %d\n"
531                 "v_ref_to_sync: %d\n"
532                 "h_sync_width: %d\n"
533                 "v_sync_width: %d\n"
534                 "h_back_porch: %d\n"
535                 "v_back_porch: %d\n"
536                 "h_active: %d\n"
537                 "v_active: %d\n"
538                 "h_front_porch: %d\n"
539                 "v_front_porch: %d\n"
540                 "stereo_mode: %d\n",
541                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
542                 m->h_sync_width, m->v_sync_width,
543                 m->h_back_porch, m->v_back_porch,
544                 m->h_active, m->v_active,
545                 m->h_front_porch, m->v_front_porch,
546                 m->stereo_mode);
547         mutex_unlock(&dc->lock);
548         return 0;
549 }
550
551 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
552 {
553         return single_open(file, dbg_dc_mode_show, inode->i_private);
554 }
555
556 static const struct file_operations mode_fops = {
557         .open           = dbg_dc_mode_open,
558         .read           = seq_read,
559         .llseek         = seq_lseek,
560         .release        = single_release,
561 };
562
563 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
564 {
565         struct tegra_dc *dc = s->private;
566
567         mutex_lock(&dc->lock);
568         seq_printf(s,
569                 "underflows: %llu\n"
570                 "underflows_a: %llu\n"
571                 "underflows_b: %llu\n"
572                 "underflows_c: %llu\n",
573                 dc->stats.underflows,
574                 dc->stats.underflows_a,
575                 dc->stats.underflows_b,
576                 dc->stats.underflows_c);
577         mutex_unlock(&dc->lock);
578
579         return 0;
580 }
581
582 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
583 {
584         return single_open(file, dbg_dc_stats_show, inode->i_private);
585 }
586
587 static const struct file_operations stats_fops = {
588         .open           = dbg_dc_stats_open,
589         .read           = seq_read,
590         .llseek         = seq_lseek,
591         .release        = single_release,
592 };
593
594 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
595 {
596         if (dc->debugdir)
597                 debugfs_remove_recursive(dc->debugdir);
598         dc->debugdir = NULL;
599 }
600
601 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
602 {
603         struct dentry *retval;
604
605         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
606         if (!dc->debugdir)
607                 goto remove_out;
608
609         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
610                 &regs_fops);
611         if (!retval)
612                 goto remove_out;
613
614         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
615                 &mode_fops);
616         if (!retval)
617                 goto remove_out;
618
619         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
620                 &stats_fops);
621         if (!retval)
622                 goto remove_out;
623
624         return;
625 remove_out:
626         dev_err(&dc->ndev->dev, "could not create debugfs\n");
627         tegra_dc_remove_debugfs(dc);
628 }
629
630 #else /* !CONFIG_DEBUGFS */
631 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
632 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
633 #endif /* CONFIG_DEBUGFS */
634
635 static int tegra_dc_set(struct tegra_dc *dc, int index)
636 {
637         int ret = 0;
638
639         mutex_lock(&tegra_dc_lock);
640         if (index >= TEGRA_MAX_DC) {
641                 ret = -EINVAL;
642                 goto out;
643         }
644
645         if (dc != NULL && tegra_dcs[index] != NULL) {
646                 ret = -EBUSY;
647                 goto out;
648         }
649
650         tegra_dcs[index] = dc;
651
652 out:
653         mutex_unlock(&tegra_dc_lock);
654
655         return ret;
656 }
657
658 unsigned int tegra_dc_has_multiple_dc(void)
659 {
660         unsigned int idx;
661         unsigned int cnt = 0;
662         struct tegra_dc *dc;
663
664         mutex_lock(&tegra_dc_lock);
665         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
666                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
667         mutex_unlock(&tegra_dc_lock);
668
669         return (cnt > 1);
670 }
671
672 /* get the stride size of a window.
673  * return: stride size in bytes for window win. or 0 if unavailble. */
674 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
675 {
676         u32 stride;
677
678         if (!dc->enabled)
679                 return 0;
680         BUG_ON(win > DC_N_WINDOWS);
681         mutex_lock(&dc->lock);
682         tegra_dc_hold_dc_out(dc);
683         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
684                 DC_CMD_DISPLAY_WINDOW_HEADER);
685         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
686         tegra_dc_release_dc_out(dc);
687         mutex_unlock(&dc->lock);
688         return GET_LINE_STRIDE(stride);
689 }
690 EXPORT_SYMBOL(tegra_dc_get_stride);
691
692 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
693 {
694         if (idx < TEGRA_MAX_DC)
695                 return tegra_dcs[idx];
696         else
697                 return NULL;
698 }
699 EXPORT_SYMBOL(tegra_dc_get_dc);
700
701 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
702 {
703         if (win >= dc->n_windows)
704                 return NULL;
705
706         return &dc->windows[win];
707 }
708 EXPORT_SYMBOL(tegra_dc_get_window);
709
710 bool tegra_dc_get_connected(struct tegra_dc *dc)
711 {
712         return dc->connected;
713 }
714 EXPORT_SYMBOL(tegra_dc_get_connected);
715
716 bool tegra_dc_hpd(struct tegra_dc *dc)
717 {
718         int sense;
719         int level;
720
721         level = gpio_get_value(dc->out->hotplug_gpio);
722
723         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
724
725         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
726                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
727 }
728 EXPORT_SYMBOL(tegra_dc_hpd);
729
730 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
731 {
732         unsigned i;
733         unsigned v0 = 128;
734         unsigned v1 = 0;
735         /* linear horizontal and vertical filters */
736         for (i = 0; i < 16; i++) {
737                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
738                                 DC_WIN_H_FILTER_P(i));
739
740                 tegra_dc_writel(dc, v0,
741                                 DC_WIN_V_FILTER_P(i));
742                 v0 -= 8;
743                 v1 += 8;
744         }
745 }
746
747 #ifdef CONFIG_TEGRA_DC_CMU
748 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
749                                                 struct tegra_dc_cmu *src_cmu)
750 {
751         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
752 }
753
754 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
755 {
756         u32 val;
757         u32 i;
758
759         for (i = 0; i < 256; i++) {
760                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
761                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
762         }
763
764         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
765         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
766         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
767         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
768         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
769         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
770         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
771         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
772         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
773
774         for (i = 0; i < 960; i++) {
775                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
776                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
777         }
778 }
779
780 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
781 {
782         u32 val;
783         u32 i;
784         bool flags;
785
786         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
787         if (val & CMU_ENABLE)
788                 flags = true;
789
790         val &= ~CMU_ENABLE;
791         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
792         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
793         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
794
795         /*TODO: Sync up with frame end */
796         mdelay(20);
797
798         for (i = 0; i < 256; i++) {
799                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
800                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
801                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
802                 cmu->lut1[i] = LUT1_READ_DATA(val);
803         }
804
805         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
806         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
807         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
808         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
809         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
810         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
811         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
812         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
813         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
814
815         for (i = 0; i < 960; i++) {
816                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
817                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
818                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
819                 cmu->lut2[i] = LUT2_READ_DATA(val);
820         }
821 }
822 EXPORT_SYMBOL(tegra_dc_get_cmu);
823
824 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
825 {
826         mutex_lock(&dc->lock);
827
828         if (!dc->enabled) {
829                 mutex_unlock(&dc->lock);
830                 return -EFAULT;
831         }
832
833         if (cmu_enable) {
834                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
835         } else {
836                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
837                 return 0;
838         }
839
840         tegra_dc_set_cmu(dc, &dc->cmu);
841
842         mutex_unlock(&dc->lock);
843
844         return 0;
845 }
846 EXPORT_SYMBOL(tegra_dc_update_cmu);
847 #else
848 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
849 #define tegra_dc_set_cmu(dc, cmu)
850 #endif
851
852 static inline void disable_dc_irq(unsigned int irq)
853 {
854         disable_irq(irq);
855 }
856
857 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
858 {
859         return dc->syncpt[i].id;
860 }
861 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
862
863 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
864 {
865         u32 max;
866
867         mutex_lock(&dc->lock);
868         tegra_dc_hold_dc_out(dc);
869         max = nvhost_syncpt_incr_max_ext(dc->ndev,
870                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
871         dc->syncpt[i].max = max;
872         tegra_dc_release_dc_out(dc);
873         mutex_unlock(&dc->lock);
874
875         return max;
876 }
877
878 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
879 {
880         mutex_lock(&dc->lock);
881         if (dc->enabled) {
882                 tegra_dc_hold_dc_out(dc);
883                 while (dc->syncpt[i].min < val) {
884                         dc->syncpt[i].min++;
885                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
886                 }
887                 tegra_dc_release_dc_out(dc);
888         }
889         mutex_unlock(&dc->lock);
890 }
891
892 void
893 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
894 {
895         unsigned int ctrl;
896         unsigned long out_sel;
897         unsigned long cmd_state;
898
899         mutex_lock(&dc->lock);
900         if (!dc->enabled) {
901                 mutex_unlock(&dc->lock);
902                 return;
903         }
904
905         tegra_dc_hold_dc_out(dc);
906
907         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
908                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
909                 cfg->clk_select);
910
911         /* The new value should be effected immediately */
912         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
913         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
914
915         switch (cfg->which_pwm) {
916         case TEGRA_PWM_PM0:
917                 /* Select the LM0 on PM0 */
918                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
919                 out_sel &= ~(7 << 0);
920                 out_sel |= (3 << 0);
921                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
922                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
923                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
924                 break;
925         case TEGRA_PWM_PM1:
926                 /* Select the LM1 on PM1 */
927                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
928                 out_sel &= ~(7 << 4);
929                 out_sel |= (3 << 4);
930                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
931                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
932                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
933                 break;
934         default:
935                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
936                 break;
937         }
938         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
939         tegra_dc_release_dc_out(dc);
940         mutex_unlock(&dc->lock);
941 }
942 EXPORT_SYMBOL(tegra_dc_config_pwm);
943
944 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
945                                 const struct tegra_dc_out_pin *pins,
946                                 const unsigned int n_pins)
947 {
948         unsigned int i;
949
950         int name;
951         int pol;
952
953         u32 pol1, pol3;
954
955         u32 set1, unset1;
956         u32 set3, unset3;
957
958         set1 = set3 = unset1 = unset3 = 0;
959
960         for (i = 0; i < n_pins; i++) {
961                 name = (pins + i)->name;
962                 pol  = (pins + i)->pol;
963
964                 /* set polarity by name */
965                 switch (name) {
966                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
967                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
968                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
969                         else
970                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
971                         break;
972                 case TEGRA_DC_OUT_PIN_H_SYNC:
973                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
974                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
975                         else
976                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
977                         break;
978                 case TEGRA_DC_OUT_PIN_V_SYNC:
979                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
980                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
981                         else
982                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
983                         break;
984                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
985                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
986                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
987                         else
988                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
989                         break;
990                 default:
991                         printk("Invalid argument in function %s\n",
992                                __FUNCTION__);
993                         break;
994                 }
995         }
996
997         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
998         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
999
1000         pol1 |= set1;
1001         pol1 &= ~unset1;
1002
1003         pol3 |= set3;
1004         pol3 &= ~unset3;
1005
1006         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1007         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1008 }
1009
1010 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1011 {
1012         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1013                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1014                 dc->out->type == TEGRA_DC_OUT_DSI)
1015                 return override_disp_mode[dc->out->type].pclk ?
1016                         &override_disp_mode[dc->out->type] : NULL;
1017         else
1018                 return NULL;
1019 }
1020
1021 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1022 {
1023         struct tegra_dc_mode *mode;
1024
1025         dc->out = out;
1026         mode = tegra_dc_get_override_mode(dc);
1027
1028         if (mode)
1029                 tegra_dc_set_mode(dc, mode);
1030         else if (out->n_modes > 0)
1031                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1032
1033         switch (out->type) {
1034         case TEGRA_DC_OUT_RGB:
1035                 dc->out_ops = &tegra_dc_rgb_ops;
1036                 break;
1037
1038         case TEGRA_DC_OUT_HDMI:
1039                 dc->out_ops = &tegra_dc_hdmi_ops;
1040                 break;
1041
1042         case TEGRA_DC_OUT_DSI:
1043                 dc->out_ops = &tegra_dc_dsi_ops;
1044                 break;
1045
1046         default:
1047                 dc->out_ops = NULL;
1048                 break;
1049         }
1050
1051         if (dc->out_ops && dc->out_ops->init)
1052                 dc->out_ops->init(dc);
1053
1054 }
1055
1056 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1057 {
1058         if (dc->out)
1059                 return dc->out->height;
1060         else
1061                 return 0;
1062 }
1063 EXPORT_SYMBOL(tegra_dc_get_out_height);
1064
1065 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1066 {
1067         if (dc->out)
1068                 return dc->out->width;
1069         else
1070                 return 0;
1071 }
1072 EXPORT_SYMBOL(tegra_dc_get_out_width);
1073
1074 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1075 {
1076         if (dc->out && dc->out->max_pixclock)
1077                 return dc->out->max_pixclock;
1078         else
1079                 return 0;
1080 }
1081 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1082
1083 void tegra_dc_enable_crc(struct tegra_dc *dc)
1084 {
1085         u32 val;
1086
1087         mutex_lock(&dc->lock);
1088         tegra_dc_hold_dc_out(dc);
1089         tegra_dc_io_start(dc);
1090
1091         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1092                 CRC_ENABLE_ENABLE;
1093         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1094         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1095         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1096         tegra_dc_release_dc_out(dc);
1097         mutex_unlock(&dc->lock);
1098 }
1099
1100 void tegra_dc_disable_crc(struct tegra_dc *dc)
1101 {
1102         mutex_lock(&dc->lock);
1103         tegra_dc_hold_dc_out(dc);
1104         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1105         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1106         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1107
1108         tegra_dc_io_end(dc);
1109         tegra_dc_release_dc_out(dc);
1110         mutex_unlock(&dc->lock);
1111 }
1112
1113 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1114 {
1115         int crc = 0;
1116
1117         if (!dc) {
1118                 pr_err("Failed to get dc: NULL parameter.\n");
1119                 goto crc_error;
1120         }
1121
1122 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1123         /* TODO: Replace mdelay with code to sync VBlANK, since
1124          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1125         mdelay(TEGRA_CRC_LATCHED_DELAY);
1126 #endif
1127
1128         mutex_lock(&dc->lock);
1129         tegra_dc_hold_dc_out(dc);
1130         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1131         tegra_dc_release_dc_out(dc);
1132         mutex_unlock(&dc->lock);
1133 crc_error:
1134         return crc;
1135 }
1136
1137 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1138 {
1139 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1140         u32 val;
1141
1142         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1143         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1144             return true;
1145 #endif
1146         return false;
1147 }
1148
1149 static inline void enable_dc_irq(unsigned int irq)
1150 {
1151 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1152         enable_irq(irq);
1153 #else
1154         /* Always disable DC interrupts on FPGA. */
1155         disable_irq(irq);
1156 #endif
1157 }
1158
1159 static void tegra_dc_vblank(struct work_struct *work)
1160 {
1161         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1162         bool nvsd_updated = false;
1163
1164         mutex_lock(&dc->lock);
1165
1166         if (!dc->enabled) {
1167                 mutex_unlock(&dc->lock);
1168                 return;
1169         }
1170
1171         tegra_dc_hold_dc_out(dc);
1172         /* use the new frame's bandwidth setting instead of max(current, new),
1173          * skip this if we're using tegra_dc_one_shot_worker() */
1174         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1175                 tegra_dc_program_bandwidth(dc, true);
1176
1177         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1178         if (!tegra_dc_windows_are_dirty(dc))
1179                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1180
1181         /* Update the SD brightness */
1182         if (dc->enabled && dc->out->sd_settings) {
1183                 nvsd_updated = nvsd_update_brightness(dc);
1184                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1185                  * V_BLANK_NVSD bit of vblank ref-count. */
1186                 if (nvsd_updated) {
1187                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1188                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1189                 } else {
1190                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1191                 }
1192         }
1193
1194         /* Mask vblank interrupt if ref-count is zero. */
1195         if (!dc->vblank_ref_count)
1196                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1197
1198         tegra_dc_release_dc_out(dc);
1199         mutex_unlock(&dc->lock);
1200
1201         /* Do the actual brightness update outside of the mutex */
1202         if (nvsd_updated && dc->out->sd_settings &&
1203             dc->out->sd_settings->bl_device) {
1204
1205                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1206                 struct backlight_device *bl = platform_get_drvdata(pdev);
1207                 if (bl)
1208                         backlight_update_status(bl);
1209         }
1210 }
1211
1212 static void tegra_dc_one_shot_worker(struct work_struct *work)
1213 {
1214         struct tegra_dc *dc = container_of(
1215                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1216         mutex_lock(&dc->lock);
1217
1218         /* memory client has gone idle */
1219         tegra_dc_clear_bandwidth(dc);
1220
1221         if (dc->out_ops->idle)
1222                 dc->out_ops->idle(dc);
1223
1224         mutex_unlock(&dc->lock);
1225 }
1226
1227 /* return an arbitrarily large number if count overflow occurs.
1228  * make it a nice base-10 number to show up in stats output */
1229 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1230 {
1231         unsigned count = tegra_dc_readl(dc, reg);
1232         tegra_dc_writel(dc, 0, reg);
1233         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1234 }
1235
1236 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1237 {
1238         u32 val;
1239         int i;
1240
1241         dc->stats.underflows++;
1242         if (dc->underflow_mask & WIN_A_UF_INT)
1243                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1244                         DC_WINBUF_AD_UFLOW_STATUS);
1245         if (dc->underflow_mask & WIN_B_UF_INT)
1246                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1247                         DC_WINBUF_BD_UFLOW_STATUS);
1248         if (dc->underflow_mask & WIN_C_UF_INT)
1249                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1250                         DC_WINBUF_CD_UFLOW_STATUS);
1251
1252         /* Check for any underflow reset conditions */
1253         for (i = 0; i < DC_N_WINDOWS; i++) {
1254                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1255                         dc->windows[i].underflows++;
1256
1257 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1258                         if (dc->windows[i].underflows > 4) {
1259                                 schedule_work(&dc->reset_work);
1260                                 /* reset counter */
1261                                 dc->windows[i].underflows = 0;
1262                                 trace_display_reset(dc);
1263                         }
1264 #endif
1265 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1266                         if (dc->windows[i].underflows > 4) {
1267                                 trace_display_reset(dc);
1268                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1269                                                 DC_DISP_DISP_MISC_CONTROL);
1270                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1271                                                 DC_CMD_STATE_CONTROL);
1272                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1273                                                 DC_CMD_STATE_CONTROL);
1274
1275                                 tegra_dc_writel(dc, 0,
1276                                                 DC_DISP_DISP_MISC_CONTROL);
1277                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1278                                                 DC_CMD_STATE_CONTROL);
1279                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1280                                                 DC_CMD_STATE_CONTROL);
1281                         }
1282 #endif
1283                 } else {
1284                         dc->windows[i].underflows = 0;
1285                 }
1286         }
1287
1288         /* Clear the underflow mask now that we've checked it. */
1289         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1290         dc->underflow_mask = 0;
1291         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1292         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1293         trace_underflow(dc);
1294 }
1295
1296 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1297 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1298 {
1299         if (status & V_BLANK_INT) {
1300                 /* Sync up windows. */
1301                 tegra_dc_trigger_windows(dc);
1302
1303                 /* Schedule any additional bottom-half vblank actvities. */
1304                 queue_work(system_freezable_wq, &dc->vblank_work);
1305         }
1306
1307         if (status & FRAME_END_INT) {
1308                 /* Mark the frame_end as complete. */
1309                 if (!completion_done(&dc->frame_end_complete))
1310                         complete(&dc->frame_end_complete);
1311         }
1312 }
1313
1314 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1315 {
1316         /* Schedule any additional bottom-half vblank actvities. */
1317         if (status & V_BLANK_INT)
1318                 queue_work(system_freezable_wq, &dc->vblank_work);
1319
1320         if (status & FRAME_END_INT) {
1321                 struct timespec tm = CURRENT_TIME;
1322                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1323                 wake_up(&dc->timestamp_wq);
1324
1325                 /* Mark the frame_end as complete. */
1326                 if (!completion_done(&dc->frame_end_complete))
1327                         complete(&dc->frame_end_complete);
1328
1329                 tegra_dc_trigger_windows(dc);
1330         }
1331 }
1332
1333 /* XXX: Not sure if we limit look ahead to 1 frame */
1334 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1335 {
1336         BUG_ON(!dc->frametime_ns);
1337         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1338 }
1339
1340 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1341 {
1342         BUG_ON(!dc->frametime_ns);
1343         return (((new_ts - old_ts) > dc->frametime_ns)
1344                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1345                         != div_s64((old_ts - dc->frame_end_timestamp),
1346                                 dc->frametime_ns)));
1347 }
1348 #endif
1349
1350 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1351 {
1352 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1353         struct tegra_dc *dc = ptr;
1354         unsigned long status;
1355         unsigned long underflow_mask;
1356         u32 val;
1357
1358         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1359                 WARN(1, "IRQ when DC not powered!\n");
1360                 tegra_dc_io_start(dc);
1361                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1362                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1363                 tegra_dc_io_end(dc);
1364                 return IRQ_HANDLED;
1365         }
1366
1367         /* clear all status flags except underflow, save those for the worker */
1368         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1369         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1370         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1371         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1372
1373         /*
1374          * Overlays can get thier internal state corrupted during and underflow
1375          * condition.  The only way to fix this state is to reset the DC.
1376          * if we get 4 consecutive frames with underflows, assume we're
1377          * hosed and reset.
1378          */
1379         underflow_mask = status & ALL_UF_INT;
1380
1381         /* Check underflow */
1382         if (underflow_mask) {
1383                 dc->underflow_mask |= underflow_mask;
1384                 schedule_delayed_work(&dc->underflow_work,
1385                         msecs_to_jiffies(1));
1386         }
1387
1388         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1389                 tegra_dc_one_shot_irq(dc, status);
1390         else
1391                 tegra_dc_continuous_irq(dc, status);
1392
1393         return IRQ_HANDLED;
1394 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1395         return IRQ_NONE;
1396 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1397 }
1398
1399 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1400 {
1401         u32 color_control;
1402
1403         switch (dc->out->depth) {
1404         case 3:
1405                 color_control = BASE_COLOR_SIZE111;
1406                 break;
1407
1408         case 6:
1409                 color_control = BASE_COLOR_SIZE222;
1410                 break;
1411
1412         case 8:
1413                 color_control = BASE_COLOR_SIZE332;
1414                 break;
1415
1416         case 9:
1417                 color_control = BASE_COLOR_SIZE333;
1418                 break;
1419
1420         case 12:
1421                 color_control = BASE_COLOR_SIZE444;
1422                 break;
1423
1424         case 15:
1425                 color_control = BASE_COLOR_SIZE555;
1426                 break;
1427
1428         case 16:
1429                 color_control = BASE_COLOR_SIZE565;
1430                 break;
1431
1432         case 18:
1433                 color_control = BASE_COLOR_SIZE666;
1434                 break;
1435
1436         default:
1437                 color_control = BASE_COLOR_SIZE888;
1438                 break;
1439         }
1440
1441         switch (dc->out->dither) {
1442         case TEGRA_DC_DISABLE_DITHER:
1443                 color_control |= DITHER_CONTROL_DISABLE;
1444                 break;
1445         case TEGRA_DC_ORDERED_DITHER:
1446                 color_control |= DITHER_CONTROL_ORDERED;
1447                 break;
1448         case TEGRA_DC_ERRDIFF_DITHER:
1449                 /* The line buffer for error-diffusion dither is limited
1450                  * to 1280 pixels per line. This limits the maximum
1451                  * horizontal active area size to 1280 pixels when error
1452                  * diffusion is enabled.
1453                  */
1454                 BUG_ON(dc->mode.h_active > 1280);
1455                 color_control |= DITHER_CONTROL_ERRDIFF;
1456                 break;
1457         }
1458
1459 #ifdef CONFIG_TEGRA_DC_CMU
1460         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
1461                 color_control |= CMU_ENABLE;
1462 #endif
1463
1464         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1465 }
1466
1467 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1468 {
1469         u32 syncpt_id;
1470
1471         switch (dc->ndev->id) {
1472         case 0:
1473                 switch (idx) {
1474                 case 0:
1475                         syncpt_id = NVSYNCPT_DISP0_A;
1476                         break;
1477                 case 1:
1478                         syncpt_id = NVSYNCPT_DISP0_B;
1479                         break;
1480                 case 2:
1481                         syncpt_id = NVSYNCPT_DISP0_C;
1482                         break;
1483                 default:
1484                         BUG();
1485                         break;
1486                 }
1487                 break;
1488         case 1:
1489                 switch (idx) {
1490                 case 0:
1491                         syncpt_id = NVSYNCPT_DISP1_A;
1492                         break;
1493                 case 1:
1494                         syncpt_id = NVSYNCPT_DISP1_B;
1495                         break;
1496                 case 2:
1497                         syncpt_id = NVSYNCPT_DISP1_C;
1498                         break;
1499                 default:
1500                         BUG();
1501                         break;
1502                 }
1503                 break;
1504         default:
1505                 BUG();
1506                 break;
1507         }
1508
1509         return syncpt_id;
1510 }
1511
1512 static int tegra_dc_init(struct tegra_dc *dc)
1513 {
1514         int i;
1515
1516         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1517         if (dc->ndev->id == 0) {
1518                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1519                                       TEGRA_MC_PRIO_MED);
1520                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1521                                       TEGRA_MC_PRIO_MED);
1522                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1523                                       TEGRA_MC_PRIO_MED);
1524                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1525                                       TEGRA_MC_PRIO_MED);
1526                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1527                                       TEGRA_MC_PRIO_HIGH);
1528         } else if (dc->ndev->id == 1) {
1529                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1530                                       TEGRA_MC_PRIO_MED);
1531                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1532                                       TEGRA_MC_PRIO_MED);
1533                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1534                                       TEGRA_MC_PRIO_MED);
1535                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1536                                       TEGRA_MC_PRIO_MED);
1537                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1538                                       TEGRA_MC_PRIO_HIGH);
1539         }
1540         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1541                         DC_CMD_CONT_SYNCPT_VSYNC);
1542         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1543         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1544         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1545         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1546 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1547         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1548 #endif
1549         /* enable interrupts for vblank, frame_end and underflows */
1550         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1551                 DC_CMD_INT_ENABLE);
1552         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1553
1554         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1555
1556         tegra_dc_set_color_control(dc);
1557         for (i = 0; i < DC_N_WINDOWS; i++) {
1558                 struct tegra_dc_win *win = &dc->windows[i];
1559                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1560                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1561                 tegra_dc_set_csc(dc, &win->csc);
1562                 tegra_dc_set_lut(dc, win);
1563                 tegra_dc_set_scaling_filter(dc);
1564         }
1565
1566         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
1567         tegra_dc_set_cmu(dc, &dc->cmu);
1568
1569         for (i = 0; i < dc->n_windows; i++) {
1570                 u32 syncpt = get_syncpt(dc, i);
1571
1572                 dc->syncpt[i].id = syncpt;
1573
1574                 dc->syncpt[i].min = dc->syncpt[i].max =
1575                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1576         }
1577
1578         trace_display_mode(dc, &dc->mode);
1579
1580         if (dc->mode.pclk)
1581                 if (tegra_dc_program_mode(dc, &dc->mode))
1582                         return -EINVAL;
1583
1584         /* Initialize SD AFTER the modeset.
1585            nvsd_init handles the sd_settings = NULL case. */
1586         nvsd_init(dc, dc->out->sd_settings);
1587
1588         return 0;
1589 }
1590
1591 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1592 {
1593         int failed_init = 0;
1594
1595         if (dc->out->enable)
1596                 dc->out->enable();
1597
1598         tegra_dc_setup_clk(dc, dc->clk);
1599         tegra_dc_clk_enable(dc);
1600
1601         /* do not accept interrupts during initialization */
1602         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1603
1604         enable_dc_irq(dc->irq);
1605
1606         failed_init = tegra_dc_init(dc);
1607         if (failed_init) {
1608                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1609                 disable_irq(dc->irq);
1610                 tegra_dc_clear_bandwidth(dc);
1611                 tegra_dc_clk_disable(dc);
1612                 if (dc->out && dc->out->disable)
1613                         dc->out->disable();
1614                 return false;
1615         }
1616
1617         if (dc->out_ops && dc->out_ops->enable)
1618                 dc->out_ops->enable(dc);
1619
1620         /* force a full blending update */
1621         dc->blend.z[0] = -1;
1622
1623         tegra_dc_ext_enable(dc->ext);
1624
1625         trace_display_enable(dc);
1626
1627         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1628         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1629
1630         if (dc->out->postpoweron)
1631                 dc->out->postpoweron();
1632
1633         return true;
1634 }
1635
1636 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1637 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1638 {
1639         bool ret = true;
1640
1641         if (dc->out->enable)
1642                 dc->out->enable();
1643
1644         tegra_dc_setup_clk(dc, dc->clk);
1645         tegra_dc_clk_enable(dc);
1646
1647         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1648                 mutex_lock(&tegra_dcs[1]->lock);
1649                 disable_irq(tegra_dcs[1]->irq);
1650         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1651                 mutex_lock(&tegra_dcs[0]->lock);
1652                 disable_irq(tegra_dcs[0]->irq);
1653         }
1654
1655         msleep(5);
1656         tegra_periph_reset_assert(dc->clk);
1657         msleep(2);
1658 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1659         tegra_periph_reset_deassert(dc->clk);
1660         msleep(1);
1661 #endif
1662
1663         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1664                 enable_dc_irq(tegra_dcs[1]->irq);
1665                 mutex_unlock(&tegra_dcs[1]->lock);
1666         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1667                 enable_dc_irq(tegra_dcs[0]->irq);
1668                 mutex_unlock(&tegra_dcs[0]->lock);
1669         }
1670
1671         enable_dc_irq(dc->irq);
1672
1673         if (tegra_dc_init(dc)) {
1674                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1675                 ret = false;
1676         }
1677
1678         if (dc->out_ops && dc->out_ops->enable)
1679                 dc->out_ops->enable(dc);
1680
1681         if (dc->out->postpoweron)
1682                 dc->out->postpoweron();
1683
1684         /* force a full blending update */
1685         dc->blend.z[0] = -1;
1686
1687         tegra_dc_ext_enable(dc->ext);
1688
1689         if (!ret) {
1690                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1691                 _tegra_dc_controller_disable(dc);
1692         }
1693
1694         trace_display_reset(dc);
1695         return ret;
1696 }
1697 #endif
1698
1699 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1700 {
1701         if (dc->mode.pclk == 0) {
1702                 switch (dc->out->type) {
1703                 case TEGRA_DC_OUT_HDMI:
1704                 /* DC enable called but no videomode is loaded.
1705                      Check if HDMI is connected, then set fallback mdoe */
1706                 if (tegra_dc_hpd(dc)) {
1707                         return tegra_dc_set_fb_mode(dc,
1708                                         &tegra_dc_hdmi_fallback_mode, 0);
1709                 } else
1710                         return false;
1711
1712                 break;
1713
1714                 /* Do nothing for other outputs for now */
1715                 case TEGRA_DC_OUT_RGB:
1716
1717                 case TEGRA_DC_OUT_DSI:
1718
1719                 default:
1720                         return false;
1721                 }
1722         }
1723
1724         return false;
1725 }
1726
1727 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1728 {
1729         return _tegra_dc_set_default_videomode(dc);
1730 }
1731
1732 static bool _tegra_dc_enable(struct tegra_dc *dc)
1733 {
1734         if (dc->mode.pclk == 0)
1735                 return false;
1736
1737         if (!dc->out)
1738                 return false;
1739
1740         tegra_dc_io_start(dc);
1741
1742         if (!_tegra_dc_controller_enable(dc)) {
1743                 tegra_dc_io_end(dc);
1744                 return false;
1745         }
1746         return true;
1747 }
1748
1749 void tegra_dc_enable(struct tegra_dc *dc)
1750 {
1751         mutex_lock(&dc->lock);
1752
1753         if (!dc->enabled)
1754                 dc->enabled = _tegra_dc_enable(dc);
1755
1756         mutex_unlock(&dc->lock);
1757         trace_display_mode(dc, &dc->mode);
1758 }
1759
1760 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1761 {
1762         unsigned i;
1763
1764         if (dc->out && dc->out->prepoweroff)
1765                 dc->out->prepoweroff();
1766
1767         if (dc->out_ops && dc->out_ops->disable)
1768                 dc->out_ops->disable(dc);
1769
1770         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1771         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1772         disable_irq(dc->irq);
1773
1774         tegra_dc_clear_bandwidth(dc);
1775         tegra_dc_clk_disable(dc);
1776
1777         if (dc->out && dc->out->disable)
1778                 dc->out->disable();
1779
1780         for (i = 0; i < dc->n_windows; i++) {
1781                 struct tegra_dc_win *w = &dc->windows[i];
1782
1783                 /* reset window bandwidth */
1784                 w->bandwidth = 0;
1785                 w->new_bandwidth = 0;
1786
1787                 /* disable windows */
1788                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1789
1790                 /* flush any pending syncpt waits */
1791                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1792                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1793                                 dc->syncpt[i].min, dc->syncpt[i].max);
1794                         dc->syncpt[i].min++;
1795                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1796                 }
1797         }
1798         trace_display_disable(dc);
1799 }
1800
1801 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1802 {
1803 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1804         u32 val;
1805         if (dc->enabled)  {
1806                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1807                 if (enable)
1808                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1809                 else
1810                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1811                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1812         }
1813 #endif
1814 }
1815
1816 bool tegra_dc_stats_get(struct tegra_dc *dc)
1817 {
1818 #if 0 /* right now it is always enabled */
1819         u32 val;
1820         bool res;
1821
1822         if (dc->enabled)  {
1823                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1824                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1825         } else {
1826                 res = false;
1827         }
1828
1829         return res;
1830 #endif
1831         return true;
1832 }
1833
1834 /* make the screen blank by disabling all windows */
1835 void tegra_dc_blank(struct tegra_dc *dc)
1836 {
1837         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1838         unsigned i;
1839
1840         for (i = 0; i < DC_N_WINDOWS; i++) {
1841                 dcwins[i] = tegra_dc_get_window(dc, i);
1842                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1843         }
1844
1845         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1846         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1847 }
1848
1849 static void _tegra_dc_disable(struct tegra_dc *dc)
1850 {
1851         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1852                 mutex_lock(&dc->one_shot_lock);
1853                 cancel_delayed_work_sync(&dc->one_shot_work);
1854         }
1855
1856         tegra_dc_hold_dc_out(dc);
1857
1858         _tegra_dc_controller_disable(dc);
1859         tegra_dc_io_end(dc);
1860
1861         tegra_dc_release_dc_out(dc);
1862
1863         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1864                 mutex_unlock(&dc->one_shot_lock);
1865 }
1866
1867 void tegra_dc_disable(struct tegra_dc *dc)
1868 {
1869         tegra_dc_ext_disable(dc->ext);
1870
1871         /* it's important that new underflow work isn't scheduled before the
1872          * lock is acquired. */
1873         cancel_delayed_work_sync(&dc->underflow_work);
1874
1875         mutex_lock(&dc->lock);
1876
1877         if (dc->enabled) {
1878                 dc->enabled = false;
1879
1880                 if (!dc->suspended)
1881                         _tegra_dc_disable(dc);
1882         }
1883
1884 #ifdef CONFIG_SWITCH
1885         switch_set_state(&dc->modeset_switch, 0);
1886 #endif
1887
1888         mutex_unlock(&dc->lock);
1889         trace_display_mode(dc, &dc->mode);
1890 }
1891
1892 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1893 static void tegra_dc_reset_worker(struct work_struct *work)
1894 {
1895         struct tegra_dc *dc =
1896                 container_of(work, struct tegra_dc, reset_work);
1897
1898         unsigned long val = 0;
1899
1900         mutex_lock(&shared_lock);
1901
1902         dev_warn(&dc->ndev->dev,
1903                 "overlay stuck in underflow state.  resetting.\n");
1904
1905         tegra_dc_ext_disable(dc->ext);
1906
1907         mutex_lock(&dc->lock);
1908
1909         if (dc->enabled == false)
1910                 goto unlock;
1911
1912         dc->enabled = false;
1913
1914         /*
1915          * off host read bus
1916          */
1917         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1918         val &= ~(0x00000100);
1919         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1920
1921         /*
1922          * set DC to STOP mode
1923          */
1924         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1925
1926         msleep(10);
1927
1928         _tegra_dc_controller_disable(dc);
1929
1930         /* _tegra_dc_controller_reset_enable deasserts reset */
1931         _tegra_dc_controller_reset_enable(dc);
1932
1933         dc->enabled = true;
1934
1935         /* reopen host read bus */
1936         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1937         val &= ~(0x00000100);
1938         val |= 0x100;
1939         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1940
1941 unlock:
1942         mutex_unlock(&dc->lock);
1943         mutex_unlock(&shared_lock);
1944         trace_display_reset(dc);
1945 }
1946 #endif
1947
1948 static void tegra_dc_underflow_worker(struct work_struct *work)
1949 {
1950         struct tegra_dc *dc = container_of(
1951                 to_delayed_work(work), struct tegra_dc, underflow_work);
1952
1953         mutex_lock(&dc->lock);
1954         tegra_dc_hold_dc_out(dc);
1955
1956         if (dc->enabled) {
1957                 tegra_dc_underflow_handler(dc);
1958         }
1959         tegra_dc_release_dc_out(dc);
1960         mutex_unlock(&dc->lock);
1961 }
1962
1963 #ifdef CONFIG_SWITCH
1964 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1965 {
1966         struct tegra_dc *dc =
1967                 container_of(sdev, struct tegra_dc, modeset_switch);
1968
1969         if (!sdev->state)
1970                 return sprintf(buf, "offline\n");
1971
1972         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1973 }
1974 #endif
1975
1976 static int tegra_dc_probe(struct nvhost_device *ndev,
1977         struct nvhost_device_id *id_table)
1978 {
1979         struct tegra_dc *dc;
1980         struct tegra_dc_mode *mode;
1981         struct clk *clk;
1982         struct clk *emc_clk;
1983         struct resource *res;
1984         struct resource *base_res;
1985         struct resource *fb_mem = NULL;
1986         int ret = 0;
1987         void __iomem *base;
1988         int irq;
1989         int i;
1990
1991         if (!ndev->dev.platform_data) {
1992                 dev_err(&ndev->dev, "no platform data\n");
1993                 return -ENOENT;
1994         }
1995
1996         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1997         if (!dc) {
1998                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1999                 return -ENOMEM;
2000         }
2001
2002         irq = nvhost_get_irq_byname(ndev, "irq");
2003         if (irq <= 0) {
2004                 dev_err(&ndev->dev, "no irq\n");
2005                 ret = -ENOENT;
2006                 goto err_free;
2007         }
2008
2009         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2010         if (!res) {
2011                 dev_err(&ndev->dev, "no mem resource\n");
2012                 ret = -ENOENT;
2013                 goto err_free;
2014         }
2015
2016         base_res = request_mem_region(res->start, resource_size(res),
2017                 ndev->name);
2018         if (!base_res) {
2019                 dev_err(&ndev->dev, "request_mem_region failed\n");
2020                 ret = -EBUSY;
2021                 goto err_free;
2022         }
2023
2024         base = ioremap(res->start, resource_size(res));
2025         if (!base) {
2026                 dev_err(&ndev->dev, "registers can't be mapped\n");
2027                 ret = -EBUSY;
2028                 goto err_release_resource_reg;
2029         }
2030
2031         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2032
2033         clk = clk_get(&ndev->dev, NULL);
2034         if (IS_ERR_OR_NULL(clk)) {
2035                 dev_err(&ndev->dev, "can't get clock\n");
2036                 ret = -ENOENT;
2037                 goto err_iounmap_reg;
2038         }
2039
2040         emc_clk = clk_get(&ndev->dev, "emc");
2041         if (IS_ERR_OR_NULL(emc_clk)) {
2042                 dev_err(&ndev->dev, "can't get emc clock\n");
2043                 ret = -ENOENT;
2044                 goto err_put_clk;
2045         }
2046
2047         dc->clk = clk;
2048         dc->emc_clk = emc_clk;
2049         dc->shift_clk_div = 1;
2050         /* Initialize one shot work delay, it will be assigned by dsi
2051          * according to refresh rate later. */
2052         dc->one_shot_delay_ms = 40;
2053
2054         dc->base_res = base_res;
2055         dc->base = base;
2056         dc->irq = irq;
2057         dc->ndev = ndev;
2058         dc->pdata = ndev->dev.platform_data;
2059
2060         /*
2061          * The emc is a shared clock, it will be set based on
2062          * the requirements for each user on the bus.
2063          */
2064         dc->emc_clk_rate = 0;
2065
2066         mutex_init(&dc->lock);
2067         mutex_init(&dc->one_shot_lock);
2068         init_completion(&dc->frame_end_complete);
2069         init_waitqueue_head(&dc->wq);
2070         init_waitqueue_head(&dc->timestamp_wq);
2071 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2072         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2073 #endif
2074         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2075         dc->vblank_ref_count = 0;
2076         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2077         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2078
2079         tegra_dc_init_lut_defaults(&dc->fb_lut);
2080
2081         dc->n_windows = DC_N_WINDOWS;
2082         for (i = 0; i < dc->n_windows; i++) {
2083                 struct tegra_dc_win *win = &dc->windows[i];
2084                 win->idx = i;
2085                 win->dc = dc;
2086                 tegra_dc_init_csc_defaults(&win->csc);
2087                 tegra_dc_init_lut_defaults(&win->lut);
2088         }
2089
2090         ret = tegra_dc_set(dc, ndev->id);
2091         if (ret < 0) {
2092                 dev_err(&ndev->dev, "can't add dc\n");
2093                 goto err_free_irq;
2094         }
2095
2096         nvhost_set_drvdata(ndev, dc);
2097
2098 #ifdef CONFIG_SWITCH
2099         dc->modeset_switch.name = dev_name(&ndev->dev);
2100         dc->modeset_switch.state = 0;
2101         dc->modeset_switch.print_state = switch_modeset_print_mode;
2102         switch_dev_register(&dc->modeset_switch);
2103 #endif
2104
2105         tegra_dc_feature_register(dc);
2106
2107         if (dc->pdata->default_out)
2108                 tegra_dc_set_out(dc, dc->pdata->default_out);
2109         else
2110                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2111
2112         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2113                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2114
2115         dc->ext = tegra_dc_ext_register(ndev, dc);
2116         if (IS_ERR_OR_NULL(dc->ext)) {
2117                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2118                 dc->ext = NULL;
2119         }
2120
2121         mutex_lock(&dc->lock);
2122         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2123                 _tegra_dc_set_default_videomode(dc);
2124                 dc->enabled = _tegra_dc_enable(dc);
2125         }
2126         mutex_unlock(&dc->lock);
2127
2128         /* interrupt handler must be registered before tegra_fb_register() */
2129         if (request_irq(irq, tegra_dc_irq, 0,
2130                         dev_name(&ndev->dev), dc)) {
2131                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2132                 ret = -EBUSY;
2133                 goto err_put_emc_clk;
2134         }
2135
2136         tegra_dc_create_debugfs(dc);
2137
2138         dev_info(&ndev->dev, "probed\n");
2139
2140         if (dc->pdata->fb) {
2141                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2142                         unsigned long fmt;
2143                         tegra_dc_writel(dc,
2144                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2145                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2146
2147                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2148                         dc->pdata->fb->bits_per_pixel =
2149                                 tegra_dc_fmt_bpp(fmt);
2150                 }
2151
2152                 mode = tegra_dc_get_override_mode(dc);
2153                 if (mode) {
2154                         dc->pdata->fb->xres = mode->h_active;
2155                         dc->pdata->fb->yres = mode->v_active;
2156                 }
2157
2158                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2159                 if (IS_ERR_OR_NULL(dc->fb))
2160                         dc->fb = NULL;
2161         }
2162
2163         if (dc->out && dc->out->hotplug_init)
2164                 dc->out->hotplug_init();
2165
2166         if (dc->out_ops && dc->out_ops->detect)
2167                 dc->out_ops->detect(dc);
2168         else
2169                 dc->connected = true;
2170
2171         tegra_dc_create_sysfs(&dc->ndev->dev);
2172
2173         return 0;
2174
2175 err_free_irq:
2176         free_irq(irq, dc);
2177 err_put_emc_clk:
2178         clk_put(emc_clk);
2179 err_put_clk:
2180         clk_put(clk);
2181 err_iounmap_reg:
2182         iounmap(base);
2183         if (fb_mem)
2184                 release_resource(fb_mem);
2185 err_release_resource_reg:
2186         release_resource(base_res);
2187 err_free:
2188         kfree(dc);
2189
2190         return ret;
2191 }
2192
2193 static int tegra_dc_remove(struct nvhost_device *ndev)
2194 {
2195         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2196
2197         tegra_dc_remove_sysfs(&dc->ndev->dev);
2198         tegra_dc_remove_debugfs(dc);
2199
2200         if (dc->fb) {
2201                 tegra_fb_unregister(dc->fb);
2202                 if (dc->fb_mem)
2203                         release_resource(dc->fb_mem);
2204         }
2205
2206         tegra_dc_ext_disable(dc->ext);
2207
2208         if (dc->ext)
2209                 tegra_dc_ext_unregister(dc->ext);
2210
2211         if (dc->enabled)
2212                 _tegra_dc_disable(dc);
2213
2214 #ifdef CONFIG_SWITCH
2215         switch_dev_unregister(&dc->modeset_switch);
2216 #endif
2217         free_irq(dc->irq, dc);
2218         clk_put(dc->emc_clk);
2219         clk_put(dc->clk);
2220         iounmap(dc->base);
2221         if (dc->fb_mem)
2222                 release_resource(dc->base_res);
2223         kfree(dc);
2224         tegra_dc_set(NULL, ndev->id);
2225         return 0;
2226 }
2227
2228 #ifdef CONFIG_PM
2229 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2230 {
2231         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2232
2233         trace_display_suspend(dc);
2234         dev_info(&ndev->dev, "suspend\n");
2235
2236         tegra_dc_ext_disable(dc->ext);
2237
2238         mutex_lock(&dc->lock);
2239
2240         if (dc->out_ops && dc->out_ops->suspend)
2241                 dc->out_ops->suspend(dc);
2242
2243         if (dc->enabled) {
2244                 _tegra_dc_disable(dc);
2245
2246                 dc->suspended = true;
2247         }
2248
2249         if (dc->out && dc->out->postsuspend) {
2250                 dc->out->postsuspend();
2251                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2252                         /*
2253                          * avoid resume event due to voltage falling
2254                          */
2255                         msleep(100);
2256         }
2257
2258         mutex_unlock(&dc->lock);
2259
2260         return 0;
2261 }
2262
2263 static int tegra_dc_resume(struct nvhost_device *ndev)
2264 {
2265         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2266
2267         trace_display_resume(dc);
2268         dev_info(&ndev->dev, "resume\n");
2269
2270         mutex_lock(&dc->lock);
2271         dc->suspended = false;
2272
2273         if (dc->enabled) {
2274                 _tegra_dc_set_default_videomode(dc);
2275                 _tegra_dc_enable(dc);
2276         }
2277
2278         if (dc->out && dc->out->hotplug_init)
2279                 dc->out->hotplug_init();
2280
2281         if (dc->out_ops && dc->out_ops->resume)
2282                 dc->out_ops->resume(dc);
2283         mutex_unlock(&dc->lock);
2284
2285         return 0;
2286 }
2287
2288 #endif /* CONFIG_PM */
2289
2290 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2291 {
2292         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2293
2294         if (!dc || !dc->enabled)
2295                 return;
2296
2297         tegra_dc_blank(dc);
2298         tegra_dc_disable(dc);
2299 }
2300
2301 extern int suspend_set(const char *val, struct kernel_param *kp)
2302 {
2303         if (!strcmp(val, "dump"))
2304                 dump_regs(tegra_dcs[0]);
2305 #ifdef CONFIG_PM
2306         else if (!strcmp(val, "suspend"))
2307                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2308         else if (!strcmp(val, "resume"))
2309                 tegra_dc_resume(tegra_dcs[0]->ndev);
2310 #endif
2311
2312         return 0;
2313 }
2314
2315 extern int suspend_get(char *buffer, struct kernel_param *kp)
2316 {
2317         return 0;
2318 }
2319
2320 int suspend;
2321
2322 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2323
2324 struct nvhost_driver tegra_dc_driver = {
2325         .driver = {
2326                 .name = "tegradc",
2327                 .owner = THIS_MODULE,
2328         },
2329         .probe = tegra_dc_probe,
2330         .remove = tegra_dc_remove,
2331 #ifdef CONFIG_PM
2332         .suspend = tegra_dc_suspend,
2333         .resume = tegra_dc_resume,
2334 #endif
2335         .shutdown = tegra_dc_shutdown,
2336 };
2337
2338 #ifndef MODULE
2339 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2340 {
2341         int i, params[11];
2342         char *p;
2343
2344         for (i = 0; i < ARRAY_SIZE(params); i++) {
2345                 if ((p = strsep(&options, ",")) != NULL) {
2346                         if (*p)
2347                                 params[i] = simple_strtoul(p, &p, 10);
2348                 } else
2349                         return -EINVAL;
2350         }
2351
2352         if ((mode->pclk = params[0]) == 0)
2353                 return -EINVAL;
2354
2355         mode->h_active      = params[1];
2356         mode->v_active      = params[2];
2357         mode->h_ref_to_sync = params[3];
2358         mode->v_ref_to_sync = params[4];
2359         mode->h_sync_width  = params[5];
2360         mode->v_sync_width  = params[6];
2361         mode->h_back_porch  = params[7];
2362         mode->v_back_porch  = params[8];
2363         mode->h_front_porch = params[9];
2364         mode->v_front_porch = params[10];
2365
2366         return 0;
2367 }
2368
2369 static int __init tegra_dc_mode_override(char *str)
2370 {
2371         char *p = str, *options;
2372
2373         if (!p || !*p)
2374                 return -EINVAL;
2375
2376         p = strstr(str, "hdmi:");
2377         if (p) {
2378                 p += 5;
2379                 options = strsep(&p, ";");
2380                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2381                         return -EINVAL;
2382         }
2383
2384         p = strstr(str, "rgb:");
2385         if (p) {
2386                 p += 4;
2387                 options = strsep(&p, ";");
2388                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2389                         return -EINVAL;
2390         }
2391
2392         p = strstr(str, "dsi:");
2393         if (p) {
2394                 p += 4;
2395                 options = strsep(&p, ";");
2396                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2397                         return -EINVAL;
2398         }
2399
2400         return 0;
2401 }
2402
2403 __setup("disp_params=", tegra_dc_mode_override);
2404 #endif
2405
2406 static int __init tegra_dc_module_init(void)
2407 {
2408         int ret = tegra_dc_ext_module_init();
2409         if (ret)
2410                 return ret;
2411         return nvhost_driver_register(&tegra_dc_driver);
2412 }
2413
2414 static void __exit tegra_dc_module_exit(void)
2415 {
2416         nvhost_driver_unregister(&tegra_dc_driver);
2417         tegra_dc_ext_module_exit();
2418 }
2419
2420 module_exit(tegra_dc_module_exit);
2421 module_init(tegra_dc_module_init);