video: tegra: dsi: Fix dynamic suspend/resume
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <video/tegrafb.h>
41 #include <drm/drm_fixed.h>
42 #ifdef CONFIG_SWITCH
43 #include <linux/switch.h>
44 #endif
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55 #include <mach/iomap.h>
56
57 #include "dc_reg.h"
58 #include "dc_config.h"
59 #include "dc_priv.h"
60 #include "dev.h"
61 #include "nvsd.h"
62
63 #define TEGRA_CRC_LATCHED_DELAY         34
64
65 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
66 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
67
68 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
69         .refresh = 60,
70         .xres = 640,
71         .yres = 480,
72         .pixclock = KHZ2PICOS(25200),
73         .hsync_len = 96,        /* h_sync_width */
74         .vsync_len = 2,         /* v_sync_width */
75         .left_margin = 48,      /* h_back_porch */
76         .upper_margin = 33,     /* v_back_porch */
77         .right_margin = 16,     /* h_front_porch */
78         .lower_margin = 10,     /* v_front_porch */
79         .vmode = 0,
80         .sync = 0,
81 };
82
83 static struct tegra_dc_mode override_disp_mode[3];
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
88
89 DEFINE_MUTEX(tegra_dc_lock);
90 DEFINE_MUTEX(shared_lock);
91
92 static const struct {
93         bool h;
94         bool v;
95 } can_filter[] = {
96         /* Window A has no filtering */
97         { false, false },
98         /* Window B has both H and V filtering */
99         { true,  true  },
100         /* Window C has only H filtering */
101         { false, true  },
102 };
103
104 #ifdef CONFIG_TEGRA_DC_CMU
105 static struct tegra_dc_cmu default_cmu = {
106         /* lut1 maps sRGB to linear space. */
107         {
108                 0,    1,    2,    4,    5,    6,    7,    9,
109                 10,   11,   12,   14,   15,   16,   18,   20,
110                 21,   23,   25,   27,   29,   31,   33,   35,
111                 37,   40,   42,   45,   48,   50,   53,   56,
112                 59,   62,   66,   69,   72,   76,   79,   83,
113                 87,   91,   95,   99,   103,  107,  112,  116,
114                 121,  126,  131,  136,  141,  146,  151,  156,
115                 162,  168,  173,  179,  185,  191,  197,  204,
116                 210,  216,  223,  230,  237,  244,  251,  258,
117                 265,  273,  280,  288,  296,  304,  312,  320,
118                 329,  337,  346,  354,  363,  372,  381,  390,
119                 400,  409,  419,  428,  438,  448,  458,  469,
120                 479,  490,  500,  511,  522,  533,  544,  555,
121                 567,  578,  590,  602,  614,  626,  639,  651,
122                 664,  676,  689,  702,  715,  728,  742,  755,
123                 769,  783,  797,  811,  825,  840,  854,  869,
124                 884,  899,  914,  929,  945,  960,  976,  992,
125                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
126                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
127                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
128                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
129                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
130                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
131                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
132                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
133                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
134                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
135                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
136                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
137                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
138                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
139                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
140         },
141         /* csc */
142         {
143                 0x100, 0x0,   0x0,
144                 0x0,   0x100, 0x0,
145                 0x0,   0x0,   0x100,
146         },
147         /* lut2 maps linear space to sRGB*/
148         {
149                 0,    1,    2,    2,    3,    4,    5,    6,
150                 6,    7,    8,    9,    10,   10,   11,   12,
151                 13,   13,   14,   15,   15,   16,   16,   17,
152                 18,   18,   19,   19,   20,   20,   21,   21,
153                 22,   22,   23,   23,   23,   24,   24,   25,
154                 25,   25,   26,   26,   27,   27,   27,   28,
155                 28,   29,   29,   29,   30,   30,   30,   31,
156                 31,   31,   32,   32,   32,   33,   33,   33,
157                 34,   34,   34,   34,   35,   35,   35,   36,
158                 36,   36,   37,   37,   37,   37,   38,   38,
159                 38,   38,   39,   39,   39,   40,   40,   40,
160                 40,   41,   41,   41,   41,   42,   42,   42,
161                 42,   43,   43,   43,   43,   43,   44,   44,
162                 44,   44,   45,   45,   45,   45,   46,   46,
163                 46,   46,   46,   47,   47,   47,   47,   48,
164                 48,   48,   48,   48,   49,   49,   49,   49,
165                 49,   50,   50,   50,   50,   50,   51,   51,
166                 51,   51,   51,   52,   52,   52,   52,   52,
167                 53,   53,   53,   53,   53,   54,   54,   54,
168                 54,   54,   55,   55,   55,   55,   55,   55,
169                 56,   56,   56,   56,   56,   57,   57,   57,
170                 57,   57,   57,   58,   58,   58,   58,   58,
171                 58,   59,   59,   59,   59,   59,   59,   60,
172                 60,   60,   60,   60,   60,   61,   61,   61,
173                 61,   61,   61,   62,   62,   62,   62,   62,
174                 62,   63,   63,   63,   63,   63,   63,   64,
175                 64,   64,   64,   64,   64,   64,   65,   65,
176                 65,   65,   65,   65,   66,   66,   66,   66,
177                 66,   66,   66,   67,   67,   67,   67,   67,
178                 67,   67,   68,   68,   68,   68,   68,   68,
179                 68,   69,   69,   69,   69,   69,   69,   69,
180                 70,   70,   70,   70,   70,   70,   70,   71,
181                 71,   71,   71,   71,   71,   71,   72,   72,
182                 72,   72,   72,   72,   72,   72,   73,   73,
183                 73,   73,   73,   73,   73,   74,   74,   74,
184                 74,   74,   74,   74,   74,   75,   75,   75,
185                 75,   75,   75,   75,   75,   76,   76,   76,
186                 76,   76,   76,   76,   77,   77,   77,   77,
187                 77,   77,   77,   77,   78,   78,   78,   78,
188                 78,   78,   78,   78,   78,   79,   79,   79,
189                 79,   79,   79,   79,   79,   80,   80,   80,
190                 80,   80,   80,   80,   80,   81,   81,   81,
191                 81,   81,   81,   81,   81,   81,   82,   82,
192                 82,   82,   82,   82,   82,   82,   83,   83,
193                 83,   83,   83,   83,   83,   83,   83,   84,
194                 84,   84,   84,   84,   84,   84,   84,   84,
195                 85,   85,   85,   85,   85,   85,   85,   85,
196                 85,   86,   86,   86,   86,   86,   86,   86,
197                 86,   86,   87,   87,   87,   87,   87,   87,
198                 87,   87,   87,   88,   88,   88,   88,   88,
199                 88,   88,   88,   88,   88,   89,   89,   89,
200                 89,   89,   89,   89,   89,   89,   90,   90,
201                 90,   90,   90,   90,   90,   90,   90,   90,
202                 91,   91,   91,   91,   91,   91,   91,   91,
203                 91,   91,   92,   92,   92,   92,   92,   92,
204                 92,   92,   92,   92,   93,   93,   93,   93,
205                 93,   93,   93,   93,   93,   93,   94,   94,
206                 94,   94,   94,   94,   94,   94,   94,   94,
207                 95,   95,   95,   95,   95,   95,   95,   95,
208                 95,   95,   96,   96,   96,   96,   96,   96,
209                 96,   96,   96,   96,   96,   97,   97,   97,
210                 97,   97,   97,   97,   97,   97,   97,   98,
211                 98,   98,   98,   98,   98,   98,   98,   98,
212                 98,   98,   99,   99,   99,   99,   99,   99,
213                 99,   100,  101,  101,  102,  103,  103,  104,
214                 105,  105,  106,  107,  107,  108,  109,  109,
215                 110,  111,  111,  112,  113,  113,  114,  115,
216                 115,  116,  116,  117,  118,  118,  119,  119,
217                 120,  120,  121,  122,  122,  123,  123,  124,
218                 124,  125,  126,  126,  127,  127,  128,  128,
219                 129,  129,  130,  130,  131,  131,  132,  132,
220                 133,  133,  134,  134,  135,  135,  136,  136,
221                 137,  137,  138,  138,  139,  139,  140,  140,
222                 141,  141,  142,  142,  143,  143,  144,  144,
223                 145,  145,  145,  146,  146,  147,  147,  148,
224                 148,  149,  149,  150,  150,  150,  151,  151,
225                 152,  152,  153,  153,  153,  154,  154,  155,
226                 155,  156,  156,  156,  157,  157,  158,  158,
227                 158,  159,  159,  160,  160,  160,  161,  161,
228                 162,  162,  162,  163,  163,  164,  164,  164,
229                 165,  165,  166,  166,  166,  167,  167,  167,
230                 168,  168,  169,  169,  169,  170,  170,  170,
231                 171,  171,  172,  172,  172,  173,  173,  173,
232                 174,  174,  174,  175,  175,  176,  176,  176,
233                 177,  177,  177,  178,  178,  178,  179,  179,
234                 179,  180,  180,  180,  181,  181,  182,  182,
235                 182,  183,  183,  183,  184,  184,  184,  185,
236                 185,  185,  186,  186,  186,  187,  187,  187,
237                 188,  188,  188,  189,  189,  189,  189,  190,
238                 190,  190,  191,  191,  191,  192,  192,  192,
239                 193,  193,  193,  194,  194,  194,  195,  195,
240                 195,  196,  196,  196,  196,  197,  197,  197,
241                 198,  198,  198,  199,  199,  199,  200,  200,
242                 200,  200,  201,  201,  201,  202,  202,  202,
243                 202,  203,  203,  203,  204,  204,  204,  205,
244                 205,  205,  205,  206,  206,  206,  207,  207,
245                 207,  207,  208,  208,  208,  209,  209,  209,
246                 209,  210,  210,  210,  211,  211,  211,  211,
247                 212,  212,  212,  213,  213,  213,  213,  214,
248                 214,  214,  214,  215,  215,  215,  216,  216,
249                 216,  216,  217,  217,  217,  217,  218,  218,
250                 218,  219,  219,  219,  219,  220,  220,  220,
251                 220,  221,  221,  221,  221,  222,  222,  222,
252                 223,  223,  223,  223,  224,  224,  224,  224,
253                 225,  225,  225,  225,  226,  226,  226,  226,
254                 227,  227,  227,  227,  228,  228,  228,  228,
255                 229,  229,  229,  229,  230,  230,  230,  230,
256                 231,  231,  231,  231,  232,  232,  232,  232,
257                 233,  233,  233,  233,  234,  234,  234,  234,
258                 235,  235,  235,  235,  236,  236,  236,  236,
259                 237,  237,  237,  237,  238,  238,  238,  238,
260                 239,  239,  239,  239,  240,  240,  240,  240,
261                 240,  241,  241,  241,  241,  242,  242,  242,
262                 242,  243,  243,  243,  243,  244,  244,  244,
263                 244,  244,  245,  245,  245,  245,  246,  246,
264                 246,  246,  247,  247,  247,  247,  247,  248,
265                 248,  248,  248,  249,  249,  249,  249,  249,
266                 250,  250,  250,  250,  251,  251,  251,  251,
267                 251,  252,  252,  252,  252,  253,  253,  253,
268                 253,  253,  254,  254,  254,  254,  255,  255,
269         },
270 };
271 #endif
272
273 void tegra_dc_clk_enable(struct tegra_dc *dc)
274 {
275         if (!tegra_is_clk_enabled(dc->clk)) {
276                 clk_prepare_enable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
278         }
279 }
280
281 void tegra_dc_clk_disable(struct tegra_dc *dc)
282 {
283         if (tegra_is_clk_enabled(dc->clk)) {
284                 clk_disable_unprepare(dc->clk);
285                 tegra_dvfs_set_rate(dc->clk, 0);
286         }
287 }
288
289 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
290 {
291         /* extra reference to dc clk */
292         clk_prepare_enable(dc->clk);
293
294         if (dc->out_ops->hold)
295                 dc->out_ops->hold(dc);
296 }
297
298 void tegra_dc_release_dc_out(struct tegra_dc *dc)
299 {
300         if (dc->out_ops->release)
301                 dc->out_ops->release(dc);
302
303         /* balance extra dc clk reference */
304         clk_disable_unprepare(dc->clk);
305 }
306
307 #define DUMP_REG(a) do {                        \
308         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
309                  #a, a, tegra_dc_readl(dc, a));               \
310         print(data, buff);                                    \
311         } while (0)
312
313 static void _dump_regs(struct tegra_dc *dc, void *data,
314                        void (* print)(void *data, const char *str))
315 {
316         int i;
317         char buff[256];
318
319         mutex_lock(&dc->lock);
320         tegra_dc_io_start(dc);
321         tegra_dc_hold_dc_out(dc);
322
323         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
324         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE);
326         DUMP_REG(DC_CMD_INT_STATUS);
327         DUMP_REG(DC_CMD_INT_MASK);
328         DUMP_REG(DC_CMD_INT_ENABLE);
329         DUMP_REG(DC_CMD_INT_TYPE);
330         DUMP_REG(DC_CMD_INT_POLARITY);
331         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
332         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
333         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
334         DUMP_REG(DC_CMD_STATE_ACCESS);
335         DUMP_REG(DC_CMD_STATE_CONTROL);
336         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
337         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
338
339         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
340         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
341         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
342         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
343         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
344         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
345         DUMP_REG(DC_DISP_REF_TO_SYNC);
346         DUMP_REG(DC_DISP_SYNC_WIDTH);
347         DUMP_REG(DC_DISP_BACK_PORCH);
348         DUMP_REG(DC_DISP_DISP_ACTIVE);
349         DUMP_REG(DC_DISP_FRONT_PORCH);
350         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
351         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
352         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
353         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
354         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
355         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
356         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
357         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
358         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
359         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
360         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
361         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
362         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
363         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
364         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
365         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
368         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
369         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
370         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
371         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
372         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
373         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
374         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
375         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
376         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
377         DUMP_REG(DC_DISP_M0_CONTROL);
378         DUMP_REG(DC_DISP_M1_CONTROL);
379         DUMP_REG(DC_DISP_DI_CONTROL);
380         DUMP_REG(DC_DISP_PP_CONTROL);
381         DUMP_REG(DC_DISP_PP_SELECT_A);
382         DUMP_REG(DC_DISP_PP_SELECT_B);
383         DUMP_REG(DC_DISP_PP_SELECT_C);
384         DUMP_REG(DC_DISP_PP_SELECT_D);
385         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
386         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
387         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
388         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
389         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
390         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
391         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
392         DUMP_REG(DC_DISP_BORDER_COLOR);
393         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
394         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
395         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
396         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
397         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
398         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
399         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
400         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
401         DUMP_REG(DC_DISP_CURSOR_POSITION);
402         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
403         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
404         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
405         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
406         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
407         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
408         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
409         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
410         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
412 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
413         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
414 #endif
415         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
416         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
417
418
419         for (i = 0; i < 3; i++) {
420                 print(data, "\n");
421                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
422                 print(data, buff);
423
424                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
425                                 DC_CMD_DISPLAY_WINDOW_HEADER);
426                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
427                 DUMP_REG(DC_WIN_WIN_OPTIONS);
428                 DUMP_REG(DC_WIN_BYTE_SWAP);
429                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
430                 DUMP_REG(DC_WIN_COLOR_DEPTH);
431                 DUMP_REG(DC_WIN_POSITION);
432                 DUMP_REG(DC_WIN_SIZE);
433                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
434                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
435                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
436                 DUMP_REG(DC_WIN_DDA_INCREMENT);
437                 DUMP_REG(DC_WIN_LINE_STRIDE);
438 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
439                 DUMP_REG(DC_WIN_BUF_STRIDE);
440                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
441 #endif
442                 DUMP_REG(DC_WIN_BLEND_NOKEY);
443                 DUMP_REG(DC_WIN_BLEND_1WIN);
444                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
445                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
446                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
447                 DUMP_REG(DC_WINBUF_START_ADDR);
448                 DUMP_REG(DC_WINBUF_START_ADDR_U);
449                 DUMP_REG(DC_WINBUF_START_ADDR_V);
450                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
451                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
452                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
453                 DUMP_REG(DC_WIN_CSC_YOF);
454                 DUMP_REG(DC_WIN_CSC_KYRGB);
455                 DUMP_REG(DC_WIN_CSC_KUR);
456                 DUMP_REG(DC_WIN_CSC_KVR);
457                 DUMP_REG(DC_WIN_CSC_KUG);
458                 DUMP_REG(DC_WIN_CSC_KVG);
459                 DUMP_REG(DC_WIN_CSC_KUB);
460                 DUMP_REG(DC_WIN_CSC_KVB);
461         }
462
463         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
464         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
465         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
466         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
467         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
468         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
469         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
470         DUMP_REG(DC_DISP_M1_CONTROL);
471         DUMP_REG(DC_COM_PM1_CONTROL);
472         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
473         DUMP_REG(DC_DISP_SD_CONTROL);
474 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
475         DUMP_REG(DC_COM_CMU_CSC_KRR);
476         DUMP_REG(DC_COM_CMU_CSC_KGR);
477         DUMP_REG(DC_COM_CMU_CSC_KBR);
478         DUMP_REG(DC_COM_CMU_CSC_KRG);
479         DUMP_REG(DC_COM_CMU_CSC_KGG);
480         DUMP_REG(DC_COM_CMU_CSC_KBR);
481         DUMP_REG(DC_COM_CMU_CSC_KRB);
482         DUMP_REG(DC_COM_CMU_CSC_KGB);
483         DUMP_REG(DC_COM_CMU_CSC_KBB);
484 #endif
485
486         tegra_dc_release_dc_out(dc);
487         tegra_dc_io_end(dc);
488         mutex_unlock(&dc->lock);
489 }
490
491 #undef DUMP_REG
492
493 #ifdef DEBUG
494 static void dump_regs_print(void *data, const char *str)
495 {
496         struct tegra_dc *dc = data;
497         dev_dbg(&dc->ndev->dev, "%s", str);
498 }
499
500 static void dump_regs(struct tegra_dc *dc)
501 {
502         _dump_regs(dc, dc, dump_regs_print);
503 }
504 #else /* !DEBUG */
505
506 static void dump_regs(struct tegra_dc *dc) {}
507
508 #endif /* DEBUG */
509
510 #ifdef CONFIG_DEBUG_FS
511
512 static void dbg_regs_print(void *data, const char *str)
513 {
514         struct seq_file *s = data;
515
516         seq_printf(s, "%s", str);
517 }
518
519 #undef DUMP_REG
520
521 static int dbg_dc_show(struct seq_file *s, void *unused)
522 {
523         struct tegra_dc *dc = s->private;
524
525         _dump_regs(dc, s, dbg_regs_print);
526
527         return 0;
528 }
529
530
531 static int dbg_dc_open(struct inode *inode, struct file *file)
532 {
533         return single_open(file, dbg_dc_show, inode->i_private);
534 }
535
536 static const struct file_operations regs_fops = {
537         .open           = dbg_dc_open,
538         .read           = seq_read,
539         .llseek         = seq_lseek,
540         .release        = single_release,
541 };
542
543 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
544 {
545         struct tegra_dc *dc = s->private;
546         struct tegra_dc_mode *m;
547
548         mutex_lock(&dc->lock);
549         m = &dc->mode;
550         seq_printf(s,
551                 "pclk: %d\n"
552                 "h_ref_to_sync: %d\n"
553                 "v_ref_to_sync: %d\n"
554                 "h_sync_width: %d\n"
555                 "v_sync_width: %d\n"
556                 "h_back_porch: %d\n"
557                 "v_back_porch: %d\n"
558                 "h_active: %d\n"
559                 "v_active: %d\n"
560                 "h_front_porch: %d\n"
561                 "v_front_porch: %d\n"
562                 "stereo_mode: %d\n",
563                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
564                 m->h_sync_width, m->v_sync_width,
565                 m->h_back_porch, m->v_back_porch,
566                 m->h_active, m->v_active,
567                 m->h_front_porch, m->v_front_porch,
568                 m->stereo_mode);
569         mutex_unlock(&dc->lock);
570         return 0;
571 }
572
573 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
574 {
575         return single_open(file, dbg_dc_mode_show, inode->i_private);
576 }
577
578 static const struct file_operations mode_fops = {
579         .open           = dbg_dc_mode_open,
580         .read           = seq_read,
581         .llseek         = seq_lseek,
582         .release        = single_release,
583 };
584
585 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
586 {
587         struct tegra_dc *dc = s->private;
588
589         mutex_lock(&dc->lock);
590         seq_printf(s,
591                 "underflows: %llu\n"
592                 "underflows_a: %llu\n"
593                 "underflows_b: %llu\n"
594                 "underflows_c: %llu\n",
595                 dc->stats.underflows,
596                 dc->stats.underflows_a,
597                 dc->stats.underflows_b,
598                 dc->stats.underflows_c);
599         mutex_unlock(&dc->lock);
600
601         return 0;
602 }
603
604 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
605 {
606         return single_open(file, dbg_dc_stats_show, inode->i_private);
607 }
608
609 static const struct file_operations stats_fops = {
610         .open           = dbg_dc_stats_open,
611         .read           = seq_read,
612         .llseek         = seq_lseek,
613         .release        = single_release,
614 };
615
616 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
617 {
618         if (dc->debugdir)
619                 debugfs_remove_recursive(dc->debugdir);
620         dc->debugdir = NULL;
621 }
622
623 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
624 {
625         struct dentry *retval;
626
627         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
628         if (!dc->debugdir)
629                 goto remove_out;
630
631         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
632                 &regs_fops);
633         if (!retval)
634                 goto remove_out;
635
636         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
637                 &mode_fops);
638         if (!retval)
639                 goto remove_out;
640
641         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
642                 &stats_fops);
643         if (!retval)
644                 goto remove_out;
645
646         return;
647 remove_out:
648         dev_err(&dc->ndev->dev, "could not create debugfs\n");
649         tegra_dc_remove_debugfs(dc);
650 }
651
652 #else /* !CONFIG_DEBUGFS */
653 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
654 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
655 #endif /* CONFIG_DEBUGFS */
656
657 static int tegra_dc_set(struct tegra_dc *dc, int index)
658 {
659         int ret = 0;
660
661         mutex_lock(&tegra_dc_lock);
662         if (index >= TEGRA_MAX_DC) {
663                 ret = -EINVAL;
664                 goto out;
665         }
666
667         if (dc != NULL && tegra_dcs[index] != NULL) {
668                 ret = -EBUSY;
669                 goto out;
670         }
671
672         tegra_dcs[index] = dc;
673
674 out:
675         mutex_unlock(&tegra_dc_lock);
676
677         return ret;
678 }
679
680 unsigned int tegra_dc_has_multiple_dc(void)
681 {
682         unsigned int idx;
683         unsigned int cnt = 0;
684         struct tegra_dc *dc;
685
686         mutex_lock(&tegra_dc_lock);
687         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
688                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
689         mutex_unlock(&tegra_dc_lock);
690
691         return (cnt > 1);
692 }
693
694 /* get the stride size of a window.
695  * return: stride size in bytes for window win. or 0 if unavailble. */
696 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
697 {
698         u32 stride;
699
700         if (!dc->enabled)
701                 return 0;
702         BUG_ON(win > DC_N_WINDOWS);
703         mutex_lock(&dc->lock);
704         tegra_dc_io_start(dc);
705         tegra_dc_hold_dc_out(dc);
706         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
707                 DC_CMD_DISPLAY_WINDOW_HEADER);
708         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
709         tegra_dc_release_dc_out(dc);
710         tegra_dc_io_end(dc);
711         mutex_unlock(&dc->lock);
712         return GET_LINE_STRIDE(stride);
713 }
714 EXPORT_SYMBOL(tegra_dc_get_stride);
715
716 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
717 {
718         if (idx < TEGRA_MAX_DC)
719                 return tegra_dcs[idx];
720         else
721                 return NULL;
722 }
723 EXPORT_SYMBOL(tegra_dc_get_dc);
724
725 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
726 {
727         if (win >= dc->n_windows)
728                 return NULL;
729
730         return &dc->windows[win];
731 }
732 EXPORT_SYMBOL(tegra_dc_get_window);
733
734 bool tegra_dc_get_connected(struct tegra_dc *dc)
735 {
736         return dc->connected;
737 }
738 EXPORT_SYMBOL(tegra_dc_get_connected);
739
740 bool tegra_dc_hpd(struct tegra_dc *dc)
741 {
742         int sense;
743         int level;
744
745         level = gpio_get_value(dc->out->hotplug_gpio);
746
747         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
748
749         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
750                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
751 }
752 EXPORT_SYMBOL(tegra_dc_hpd);
753
754 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
755 {
756         unsigned i;
757         unsigned v0 = 128;
758         unsigned v1 = 0;
759
760         /* linear horizontal and vertical filters */
761         for (i = 0; i < 16; i++) {
762                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
763                                 DC_WIN_H_FILTER_P(i));
764
765                 tegra_dc_writel(dc, v0,
766                                 DC_WIN_V_FILTER_P(i));
767                 v0 -= 8;
768                 v1 += 8;
769         }
770 }
771
772 #ifdef CONFIG_TEGRA_DC_CMU
773 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
774                                         struct tegra_dc_cmu *src_cmu)
775 {
776         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
777 }
778
779 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
780 {
781         u32 val;
782         u32 i;
783
784         for (i = 0; i < 256; i++) {
785                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
786                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
787         }
788
789         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
790         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
791         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
792         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
793         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
794         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
795         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
796         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
797         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
798
799         for (i = 0; i < 960; i++) {
800                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
801                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
802         }
803 }
804
805 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
806 {
807         u32 val;
808         u32 i;
809         bool flags;
810
811         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
812         if (val & CMU_ENABLE)
813                 flags = true;
814
815         val &= ~CMU_ENABLE;
816         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
817         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
818         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
819
820         /*TODO: Sync up with frame end */
821         mdelay(20);
822
823         for (i = 0; i < 256; i++) {
824                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
825                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
826                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
827                 cmu->lut1[i] = LUT1_READ_DATA(val);
828         }
829
830         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
831         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
832         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
833         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
834         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
835         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
836         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
837         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
838         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
839
840         for (i = 0; i < 960; i++) {
841                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
842                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
843                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
844                 cmu->lut2[i] = LUT2_READ_DATA(val);
845         }
846 }
847 EXPORT_SYMBOL(tegra_dc_get_cmu);
848
849 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
850 {
851         u32 val;
852
853         if (dc->pdata->cmu_enable) {
854                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
855         } else {
856                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
857                 return 0;
858         }
859
860         if (cmu != &dc->cmu) {
861                 tegra_dc_cache_cmu(&dc->cmu, cmu);
862
863                 /* Disable CMU */
864                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
865                 if (val & CMU_ENABLE) {
866                         val &= ~CMU_ENABLE;
867                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
868                         val = GENERAL_UPDATE;
869                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
870                         val = GENERAL_ACT_REQ;
871                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
872                         /*TODO: Sync up with vsync */
873                         mdelay(20);
874                 }
875
876                 tegra_dc_set_cmu(dc, &dc->cmu);
877         }
878
879         return 0;
880 }
881
882 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
883 {
884         int ret;
885
886         mutex_lock(&dc->lock);
887         if (!dc->enabled) {
888                 mutex_unlock(&dc->lock);
889                 return 0;
890         }
891         tegra_dc_io_start(dc);
892         tegra_dc_hold_dc_out(dc);
893
894         ret = _tegra_dc_update_cmu(dc, cmu);
895         tegra_dc_set_color_control(dc);
896
897         tegra_dc_release_dc_out(dc);
898         tegra_dc_io_end(dc);
899         mutex_unlock(&dc->lock);
900
901         return ret;
902 }
903 EXPORT_SYMBOL(tegra_dc_update_cmu);
904
905 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
906 {
907         dc->pdata->cmu_enable = cmu_enable;
908         if (dc->pdata->cmu)
909                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
910         else
911                 tegra_dc_update_cmu(dc, &default_cmu);
912 }
913 #else
914 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
915 #define tegra_dc_set_cmu(dc, cmu)
916 #define tegra_dc_update_cmu(dc, cmu)
917 #endif
918
919 /* disable_irq() blocks until handler completes, calling this function while
920  * holding dc->lock can deadlock. */
921 static inline void disable_dc_irq(const struct tegra_dc *dc)
922 {
923         disable_irq(dc->irq);
924 }
925
926 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
927 {
928         return dc->syncpt[i].id;
929 }
930 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
931
932 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
933 {
934         u32 max;
935
936         mutex_lock(&dc->lock);
937         tegra_dc_io_start(dc);
938         tegra_dc_hold_dc_out(dc);
939         max = nvhost_syncpt_incr_max_ext(dc->ndev,
940                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
941         dc->syncpt[i].max = max;
942         tegra_dc_release_dc_out(dc);
943         tegra_dc_io_end(dc);
944         mutex_unlock(&dc->lock);
945
946         return max;
947 }
948
949 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
950 {
951         mutex_lock(&dc->lock);
952         if (dc->enabled) {
953                 tegra_dc_io_start(dc);
954                 tegra_dc_hold_dc_out(dc);
955                 while (dc->syncpt[i].min < val) {
956                         dc->syncpt[i].min++;
957                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
958                 }
959                 tegra_dc_release_dc_out(dc);
960                 tegra_dc_io_end(dc);
961         }
962         mutex_unlock(&dc->lock);
963 }
964
965 void
966 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
967 {
968         unsigned int ctrl;
969         unsigned long out_sel;
970         unsigned long cmd_state;
971
972         mutex_lock(&dc->lock);
973         if (!dc->enabled) {
974                 mutex_unlock(&dc->lock);
975                 return;
976         }
977
978         tegra_dc_io_start(dc);
979         tegra_dc_hold_dc_out(dc);
980
981         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
982                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
983                 cfg->clk_select);
984
985         /* The new value should be effected immediately */
986         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
987         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
988
989         switch (cfg->which_pwm) {
990         case TEGRA_PWM_PM0:
991                 /* Select the LM0 on PM0 */
992                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
993                 out_sel &= ~(7 << 0);
994                 out_sel |= (3 << 0);
995                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
996                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
997                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
998                 break;
999         case TEGRA_PWM_PM1:
1000                 /* Select the LM1 on PM1 */
1001                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1002                 out_sel &= ~(7 << 4);
1003                 out_sel |= (3 << 4);
1004                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1005                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1006                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1007                 break;
1008         default:
1009                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1010                 break;
1011         }
1012         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1013         tegra_dc_release_dc_out(dc);
1014         tegra_dc_io_end(dc);
1015         mutex_unlock(&dc->lock);
1016 }
1017 EXPORT_SYMBOL(tegra_dc_config_pwm);
1018
1019 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1020                                 const struct tegra_dc_out_pin *pins,
1021                                 const unsigned int n_pins)
1022 {
1023         unsigned int i;
1024
1025         int name;
1026         int pol;
1027
1028         u32 pol1, pol3;
1029
1030         u32 set1, unset1;
1031         u32 set3, unset3;
1032
1033         set1 = set3 = unset1 = unset3 = 0;
1034
1035         for (i = 0; i < n_pins; i++) {
1036                 name = (pins + i)->name;
1037                 pol  = (pins + i)->pol;
1038
1039                 /* set polarity by name */
1040                 switch (name) {
1041                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1042                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1043                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1044                         else
1045                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1046                         break;
1047                 case TEGRA_DC_OUT_PIN_H_SYNC:
1048                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1049                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1050                         else
1051                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1052                         break;
1053                 case TEGRA_DC_OUT_PIN_V_SYNC:
1054                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1055                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1056                         else
1057                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1058                         break;
1059                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1060                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1061                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1062                         else
1063                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1064                         break;
1065                 default:
1066                         printk("Invalid argument in function %s\n",
1067                                __FUNCTION__);
1068                         break;
1069                 }
1070         }
1071
1072         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1073         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1074
1075         pol1 |= set1;
1076         pol1 &= ~unset1;
1077
1078         pol3 |= set3;
1079         pol3 &= ~unset3;
1080
1081         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1082         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1083 }
1084
1085 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1086 {
1087         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1088                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1089                 dc->out->type == TEGRA_DC_OUT_DSI)
1090                 return override_disp_mode[dc->out->type].pclk ?
1091                         &override_disp_mode[dc->out->type] : NULL;
1092         else
1093                 return NULL;
1094 }
1095
1096 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1097 {
1098         struct tegra_dc_mode *mode;
1099
1100         dc->out = out;
1101         mode = tegra_dc_get_override_mode(dc);
1102
1103         if (mode)
1104                 tegra_dc_set_mode(dc, mode);
1105         else if (out->n_modes > 0)
1106                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1107
1108         switch (out->type) {
1109         case TEGRA_DC_OUT_RGB:
1110                 dc->out_ops = &tegra_dc_rgb_ops;
1111                 break;
1112
1113         case TEGRA_DC_OUT_HDMI:
1114                 dc->out_ops = &tegra_dc_hdmi_ops;
1115                 break;
1116
1117         case TEGRA_DC_OUT_DSI:
1118                 dc->out_ops = &tegra_dc_dsi_ops;
1119                 break;
1120
1121         default:
1122                 dc->out_ops = NULL;
1123                 break;
1124         }
1125
1126         if (dc->out_ops && dc->out_ops->init)
1127                 dc->out_ops->init(dc);
1128 }
1129
1130 /* returns on error: -EINVAL
1131  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1132 int tegra_dc_get_out(const struct tegra_dc *dc)
1133 {
1134         if (dc && dc->out)
1135                 return dc->out->type;
1136         return -EINVAL;
1137 }
1138
1139 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1140 {
1141         if (dc->out)
1142                 return dc->out->height;
1143         else
1144                 return 0;
1145 }
1146 EXPORT_SYMBOL(tegra_dc_get_out_height);
1147
1148 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1149 {
1150         if (dc->out)
1151                 return dc->out->width;
1152         else
1153                 return 0;
1154 }
1155 EXPORT_SYMBOL(tegra_dc_get_out_width);
1156
1157 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1158 {
1159         if (dc->out && dc->out->max_pixclock)
1160                 return dc->out->max_pixclock;
1161         else
1162                 return 0;
1163 }
1164 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1165
1166 void tegra_dc_enable_crc(struct tegra_dc *dc)
1167 {
1168         u32 val;
1169
1170         mutex_lock(&dc->lock);
1171         tegra_dc_io_start(dc);
1172         tegra_dc_hold_dc_out(dc);
1173
1174         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1175                 CRC_ENABLE_ENABLE;
1176         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1177         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1178         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1179         tegra_dc_release_dc_out(dc);
1180         tegra_dc_io_end(dc);
1181         mutex_unlock(&dc->lock);
1182 }
1183
1184 void tegra_dc_disable_crc(struct tegra_dc *dc)
1185 {
1186         mutex_lock(&dc->lock);
1187         tegra_dc_io_start(dc);
1188         tegra_dc_hold_dc_out(dc);
1189         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1190         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1191         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1192
1193         tegra_dc_release_dc_out(dc);
1194         tegra_dc_io_end(dc);
1195         mutex_unlock(&dc->lock);
1196 }
1197
1198 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1199 {
1200         int crc = 0;
1201
1202         if (!dc) {
1203                 pr_err("Failed to get dc: NULL parameter.\n");
1204                 goto crc_error;
1205         }
1206
1207 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1208         /* TODO: Replace mdelay with code to sync VBlANK, since
1209          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1210         mdelay(TEGRA_CRC_LATCHED_DELAY);
1211 #endif
1212
1213         mutex_lock(&dc->lock);
1214         tegra_dc_io_start(dc);
1215         tegra_dc_hold_dc_out(dc);
1216         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1217         tegra_dc_release_dc_out(dc);
1218         tegra_dc_io_end(dc);
1219         mutex_unlock(&dc->lock);
1220 crc_error:
1221         return crc;
1222 }
1223
1224 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1225 {
1226 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1227         u32 val;
1228
1229         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1230         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1231             return true;
1232 #endif
1233         return false;
1234 }
1235
1236 static inline void enable_dc_irq(const struct tegra_dc *dc)
1237 {
1238 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1239         enable_irq(dc->irq);
1240 #else
1241         /* Always disable DC interrupts on FPGA. */
1242         disable_irq(dc->irq);
1243 #endif
1244 }
1245
1246 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1247 {
1248         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1249                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1250 }
1251
1252 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1253 {
1254         int ret = -ENOTTY;
1255
1256         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1257                 return ret;
1258
1259         /*
1260          * Logic is as follows
1261          * a) Indicate we need a vblank.
1262          * b) Wait for completion to be signalled from isr.
1263          * c) Initialize completion for next iteration.
1264          */
1265
1266         tegra_dc_hold_dc_out(dc);
1267         dc->out->user_needs_vblank = true;
1268
1269         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1270         init_completion(&dc->out->user_vblank_comp);
1271         tegra_dc_release_dc_out(dc);
1272
1273         return ret;
1274 }
1275
1276 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1277 {
1278         /* Do the actual brightness update outside of the mutex dc->lock */
1279         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1280                 dc->out->sd_settings->bl_device_name) {
1281                 char *bl_device_name =
1282                         dc->out->sd_settings->bl_device_name;
1283                 dc->out->sd_settings->bl_device =
1284                         get_backlight_device_by_name(bl_device_name);
1285         }
1286
1287         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1288                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1289                 backlight_update_status(bl);
1290         }
1291 }
1292
1293 static void tegra_dc_vblank(struct work_struct *work)
1294 {
1295         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1296         bool nvsd_updated = false;
1297
1298         mutex_lock(&dc->lock);
1299
1300         if (!dc->enabled) {
1301                 mutex_unlock(&dc->lock);
1302                 return;
1303         }
1304
1305         tegra_dc_io_start(dc);
1306         tegra_dc_hold_dc_out(dc);
1307         /* use the new frame's bandwidth setting instead of max(current, new),
1308          * skip this if we're using tegra_dc_one_shot_worker() */
1309         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1310                 tegra_dc_program_bandwidth(dc, true);
1311
1312         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1313         if (!tegra_dc_windows_are_dirty(dc))
1314                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1315
1316         /* Update the SD brightness */
1317         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1318                 nvsd_updated = nvsd_update_brightness(dc);
1319                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1320                  * V_BLANK_NVSD bit of vblank ref-count. */
1321                 if (nvsd_updated) {
1322                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1323                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1324                 } else {
1325                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1326                 }
1327         }
1328
1329         /* Mask vblank interrupt if ref-count is zero. */
1330         if (!dc->vblank_ref_count)
1331                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1332
1333         tegra_dc_release_dc_out(dc);
1334         tegra_dc_io_end(dc);
1335         mutex_unlock(&dc->lock);
1336
1337         /* Do the actual brightness update outside of the mutex dc->lock */
1338         if (nvsd_updated)
1339                 tegra_dc_prism_update_backlight(dc);
1340 }
1341
1342 static void tegra_dc_one_shot_worker(struct work_struct *work)
1343 {
1344         struct tegra_dc *dc = container_of(
1345                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1346         mutex_lock(&dc->lock);
1347
1348         /* memory client has gone idle */
1349         tegra_dc_clear_bandwidth(dc);
1350
1351         if (dc->out_ops->idle) {
1352                 tegra_dc_io_start(dc);
1353                 dc->out_ops->idle(dc);
1354                 tegra_dc_io_end(dc);
1355         }
1356
1357         mutex_unlock(&dc->lock);
1358 }
1359
1360 /* return an arbitrarily large number if count overflow occurs.
1361  * make it a nice base-10 number to show up in stats output */
1362 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1363 {
1364         unsigned count = tegra_dc_readl(dc, reg);
1365
1366         tegra_dc_writel(dc, 0, reg);
1367         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1368 }
1369
1370 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1371 {
1372         int i;
1373
1374         dc->stats.underflows++;
1375         if (dc->underflow_mask & WIN_A_UF_INT)
1376                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1377                         DC_WINBUF_AD_UFLOW_STATUS);
1378         if (dc->underflow_mask & WIN_B_UF_INT)
1379                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1380                         DC_WINBUF_BD_UFLOW_STATUS);
1381         if (dc->underflow_mask & WIN_C_UF_INT)
1382                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1383                         DC_WINBUF_CD_UFLOW_STATUS);
1384
1385         /* Check for any underflow reset conditions */
1386         for (i = 0; i < DC_N_WINDOWS; i++) {
1387                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1388                         dc->windows[i].underflows++;
1389
1390 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1391                         if (dc->windows[i].underflows > 4) {
1392                                 schedule_work(&dc->reset_work);
1393                                 /* reset counter */
1394                                 dc->windows[i].underflows = 0;
1395                                 trace_display_reset(dc);
1396                         }
1397 #endif
1398 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1399                         if (dc->windows[i].underflows > 4) {
1400                                 trace_display_reset(dc);
1401                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1402                                                 DC_DISP_DISP_MISC_CONTROL);
1403                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1404                                                 DC_CMD_STATE_CONTROL);
1405                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1406                                                 DC_CMD_STATE_CONTROL);
1407
1408                                 tegra_dc_writel(dc, 0,
1409                                                 DC_DISP_DISP_MISC_CONTROL);
1410                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1411                                                 DC_CMD_STATE_CONTROL);
1412                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1413                                                 DC_CMD_STATE_CONTROL);
1414                         }
1415 #endif
1416                 } else {
1417                         dc->windows[i].underflows = 0;
1418                 }
1419         }
1420
1421         /* Clear the underflow mask now that we've checked it. */
1422         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1423         dc->underflow_mask = 0;
1424         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1425         trace_underflow(dc);
1426 }
1427
1428 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1429 static void tegra_dc_vpulse2(struct work_struct *work)
1430 {
1431         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1432         bool nvsd_updated = false;
1433
1434         mutex_lock(&dc->lock);
1435
1436         if (!dc->enabled) {
1437                 mutex_unlock(&dc->lock);
1438                 return;
1439         }
1440
1441         tegra_dc_io_start(dc);
1442         tegra_dc_hold_dc_out(dc);
1443
1444         /* Clear the V_PULSE2_FLIP if no update */
1445         if (!tegra_dc_windows_are_dirty(dc))
1446                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1447
1448         /* Update the SD brightness */
1449         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1450                 nvsd_updated = nvsd_update_brightness(dc);
1451                 if (nvsd_updated) {
1452                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1453                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1454                 } else {
1455                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1456                 }
1457         }
1458
1459         /* Mask vpulse2 interrupt if ref-count is zero. */
1460         if (!dc->vpulse2_ref_count)
1461                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1462
1463         tegra_dc_release_dc_out(dc);
1464         tegra_dc_io_end(dc);
1465         mutex_unlock(&dc->lock);
1466
1467         /* Do the actual brightness update outside of the mutex dc->lock */
1468         if (nvsd_updated)
1469                 tegra_dc_prism_update_backlight(dc);
1470 }
1471 #endif
1472
1473 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1474 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1475 {
1476         /* pending user vblank, so wakeup */
1477         if ((status & (V_BLANK_INT | MSF_INT)) &&
1478             (dc->out->user_needs_vblank)) {
1479                 dc->out->user_needs_vblank = false;
1480                 complete(&dc->out->user_vblank_comp);
1481         }
1482
1483         if (status & V_BLANK_INT) {
1484                 /* Sync up windows. */
1485                 tegra_dc_trigger_windows(dc);
1486
1487                 /* Schedule any additional bottom-half vblank actvities. */
1488                 queue_work(system_freezable_wq, &dc->vblank_work);
1489         }
1490
1491         if (status & FRAME_END_INT) {
1492                 /* Mark the frame_end as complete. */
1493                 if (!completion_done(&dc->frame_end_complete))
1494                         complete(&dc->frame_end_complete);
1495         }
1496
1497 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1498         if (status & V_PULSE2_INT)
1499                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1500 #endif
1501 }
1502
1503 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1504 {
1505         /* Schedule any additional bottom-half vblank actvities. */
1506         if (status & V_BLANK_INT)
1507                 queue_work(system_freezable_wq, &dc->vblank_work);
1508
1509         if (status & FRAME_END_INT) {
1510                 struct timespec tm = CURRENT_TIME;
1511                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1512                 wake_up(&dc->timestamp_wq);
1513
1514                 /* Mark the frame_end as complete. */
1515                 if (!completion_done(&dc->frame_end_complete))
1516                         complete(&dc->frame_end_complete);
1517
1518                 tegra_dc_trigger_windows(dc);
1519         }
1520
1521 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1522         if (status & V_PULSE2_INT)
1523                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1524 #endif
1525 }
1526
1527 /* XXX: Not sure if we limit look ahead to 1 frame */
1528 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1529 {
1530         BUG_ON(!dc->frametime_ns);
1531         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1532 }
1533
1534 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1535 {
1536         BUG_ON(!dc->frametime_ns);
1537         return (((new_ts - old_ts) > dc->frametime_ns)
1538                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1539                         != div_s64((old_ts - dc->frame_end_timestamp),
1540                                 dc->frametime_ns)));
1541 }
1542 #endif
1543
1544 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1545 {
1546 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1547         struct tegra_dc *dc = ptr;
1548         unsigned long status;
1549         unsigned long underflow_mask;
1550         u32 val;
1551         int need_disable = 0;
1552
1553         mutex_lock(&dc->lock);
1554         if (!dc->enabled) {
1555                 mutex_unlock(&dc->lock);
1556                 return IRQ_HANDLED;
1557         }
1558
1559         clk_prepare_enable(dc->clk);
1560         tegra_dc_io_start(dc);
1561         tegra_dc_hold_dc_out(dc);
1562
1563         if (!nvhost_module_powered_ext(dc->ndev)) {
1564                 WARN(1, "IRQ when DC not powered!\n");
1565                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1566                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1567                 tegra_dc_release_dc_out(dc);
1568                 tegra_dc_io_end(dc);
1569                 clk_disable_unprepare(dc->clk);
1570                 mutex_unlock(&dc->lock);
1571                 return IRQ_HANDLED;
1572         }
1573
1574         /* clear all status flags except underflow, save those for the worker */
1575         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1576         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1577         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1578         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1579
1580         /*
1581          * Overlays can get thier internal state corrupted during and underflow
1582          * condition.  The only way to fix this state is to reset the DC.
1583          * if we get 4 consecutive frames with underflows, assume we're
1584          * hosed and reset.
1585          */
1586         underflow_mask = status & ALL_UF_INT;
1587
1588         /* Check underflow */
1589         if (underflow_mask) {
1590                 dc->underflow_mask |= underflow_mask;
1591                 schedule_delayed_work(&dc->underflow_work,
1592                         msecs_to_jiffies(1));
1593         }
1594
1595         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1596                 tegra_dc_one_shot_irq(dc, status);
1597         else
1598                 tegra_dc_continuous_irq(dc, status);
1599
1600         /* update video mode if it has changed since the last frame */
1601         if (status & (FRAME_END_INT | V_BLANK_INT))
1602                 if (tegra_dc_update_mode(dc))
1603                         need_disable = 1; /* force display off on error */
1604
1605         tegra_dc_release_dc_out(dc);
1606         tegra_dc_io_end(dc);
1607         clk_disable_unprepare(dc->clk);
1608         mutex_unlock(&dc->lock);
1609
1610         if (need_disable)
1611                 tegra_dc_disable(dc);
1612         return IRQ_HANDLED;
1613 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1614         return IRQ_NONE;
1615 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1616 }
1617
1618 void tegra_dc_set_color_control(struct tegra_dc *dc)
1619 {
1620         u32 color_control;
1621
1622         switch (dc->out->depth) {
1623         case 3:
1624                 color_control = BASE_COLOR_SIZE111;
1625                 break;
1626
1627         case 6:
1628                 color_control = BASE_COLOR_SIZE222;
1629                 break;
1630
1631         case 8:
1632                 color_control = BASE_COLOR_SIZE332;
1633                 break;
1634
1635         case 9:
1636                 color_control = BASE_COLOR_SIZE333;
1637                 break;
1638
1639         case 12:
1640                 color_control = BASE_COLOR_SIZE444;
1641                 break;
1642
1643         case 15:
1644                 color_control = BASE_COLOR_SIZE555;
1645                 break;
1646
1647         case 16:
1648                 color_control = BASE_COLOR_SIZE565;
1649                 break;
1650
1651         case 18:
1652                 color_control = BASE_COLOR_SIZE666;
1653                 break;
1654
1655         default:
1656                 color_control = BASE_COLOR_SIZE888;
1657                 break;
1658         }
1659
1660         switch (dc->out->dither) {
1661         case TEGRA_DC_DISABLE_DITHER:
1662                 color_control |= DITHER_CONTROL_DISABLE;
1663                 break;
1664         case TEGRA_DC_ORDERED_DITHER:
1665                 color_control |= DITHER_CONTROL_ORDERED;
1666                 break;
1667         case TEGRA_DC_ERRDIFF_DITHER:
1668                 /* The line buffer for error-diffusion dither is limited
1669                  * to 1280 pixels per line. This limits the maximum
1670                  * horizontal active area size to 1280 pixels when error
1671                  * diffusion is enabled.
1672                  */
1673                 BUG_ON(dc->mode.h_active > 1280);
1674                 color_control |= DITHER_CONTROL_ERRDIFF;
1675                 break;
1676         }
1677
1678 #ifdef CONFIG_TEGRA_DC_CMU
1679         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1680                 color_control |= CMU_ENABLE;
1681 #endif
1682
1683         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1684 }
1685
1686 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1687 {
1688         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1689                 return dc->win_syncpt[idx];
1690         BUG();
1691 }
1692
1693 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1694 {
1695 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1696         u32 start, end;
1697         unsigned long val;
1698
1699         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1700         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1701
1702         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1703                 dc->mode.v_back_porch + dc->mode.v_active;
1704         end = start + 1;
1705         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1706         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1707
1708         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1709         val |= V_PULSE2_INT;
1710         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1711
1712         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1713         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1714 #endif
1715 }
1716
1717 static int tegra_dc_init(struct tegra_dc *dc)
1718 {
1719         int i;
1720         int int_enable;
1721
1722         tegra_dc_io_start(dc);
1723         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1724         if (dc->ndev->id == 0) {
1725                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1726                                       TEGRA_MC_PRIO_MED);
1727                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1728                                       TEGRA_MC_PRIO_MED);
1729                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1730                                       TEGRA_MC_PRIO_MED);
1731 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1732                 /* only present on Tegra2 and 3 */
1733                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1734                                       TEGRA_MC_PRIO_MED);
1735 #endif
1736                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1737                                       TEGRA_MC_PRIO_HIGH);
1738         } else if (dc->ndev->id == 1) {
1739                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1740                                       TEGRA_MC_PRIO_MED);
1741                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1742                                       TEGRA_MC_PRIO_MED);
1743                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1744                                       TEGRA_MC_PRIO_MED);
1745 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1746                 /* only present on Tegra2 and 3 */
1747                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1748                                       TEGRA_MC_PRIO_MED);
1749 #endif
1750                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1751                                       TEGRA_MC_PRIO_HIGH);
1752         }
1753         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1754                         DC_CMD_CONT_SYNCPT_VSYNC);
1755
1756         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1757         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1758         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1759         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1760 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1761         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1762 #endif
1763         /* enable interrupts for vblank, frame_end and underflows */
1764         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1765         /* for panels with one-shot mode enable tearing effect interrupt */
1766         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1767                 int_enable |= MSF_INT;
1768
1769         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1770         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1771         tegra_dc_init_vpulse2_int(dc);
1772
1773         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1774
1775 #ifdef CONFIG_TEGRA_DC_CMU
1776         if (dc->pdata->cmu)
1777                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1778         else
1779                 _tegra_dc_update_cmu(dc, &default_cmu);
1780 #endif
1781         tegra_dc_set_color_control(dc);
1782         for (i = 0; i < DC_N_WINDOWS; i++) {
1783                 struct tegra_dc_win *win = &dc->windows[i];
1784                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1785                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1786                 tegra_dc_set_csc(dc, &win->csc);
1787                 tegra_dc_set_lut(dc, win);
1788                 tegra_dc_set_scaling_filter(dc);
1789         }
1790
1791         for (i = 0; i < dc->n_windows; i++) {
1792                 u32 syncpt = get_syncpt(dc, i);
1793
1794                 dc->syncpt[i].id = syncpt;
1795
1796                 dc->syncpt[i].min = dc->syncpt[i].max =
1797                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1798         }
1799
1800         trace_display_mode(dc, &dc->mode);
1801
1802         if (dc->mode.pclk) {
1803                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1804                         tegra_dc_io_end(dc);
1805                         return -EINVAL;
1806                 }
1807         }
1808
1809         /* Initialize SD AFTER the modeset.
1810            nvsd_init handles the sd_settings = NULL case. */
1811         nvsd_init(dc, dc->out->sd_settings);
1812
1813         tegra_dc_io_end(dc);
1814
1815         return 0;
1816 }
1817
1818 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1819 {
1820         int failed_init = 0;
1821
1822         tegra_dc_unpowergate_locked(dc);
1823
1824         if (dc->out->enable)
1825                 dc->out->enable(&dc->ndev->dev);
1826
1827         tegra_dc_setup_clk(dc, dc->clk);
1828         tegra_dc_clk_enable(dc);
1829         tegra_dc_io_start(dc);
1830
1831         tegra_dc_power_on(dc);
1832
1833         /* do not accept interrupts during initialization */
1834         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1835
1836         enable_dc_irq(dc);
1837
1838         failed_init = tegra_dc_init(dc);
1839         if (failed_init) {
1840                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1841                 disable_irq_nosync(dc->irq);
1842                 tegra_dc_clear_bandwidth(dc);
1843                 tegra_dc_clk_disable(dc);
1844                 if (dc->out && dc->out->disable)
1845                         dc->out->disable();
1846                 tegra_dc_io_end(dc);
1847                 return false;
1848         }
1849
1850         if (dc->out_ops && dc->out_ops->enable)
1851                 dc->out_ops->enable(dc);
1852
1853         /* force a full blending update */
1854         dc->blend.z[0] = -1;
1855
1856         tegra_dc_ext_enable(dc->ext);
1857
1858         trace_display_enable(dc);
1859
1860         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1861         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1862
1863         if (dc->out->postpoweron)
1864                 dc->out->postpoweron();
1865
1866         tegra_dc_io_end(dc);
1867         return true;
1868 }
1869
1870 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1871 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1872 {
1873         bool ret = true;
1874
1875         if (dc->out->enable)
1876                 dc->out->enable(&dc->ndev->dev);
1877
1878         tegra_dc_setup_clk(dc, dc->clk);
1879         tegra_dc_clk_enable(dc);
1880
1881         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1882                 mutex_lock(&tegra_dcs[1]->lock);
1883                 disable_irq_nosync(tegra_dcs[1]->irq);
1884         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1885                 mutex_lock(&tegra_dcs[0]->lock);
1886                 disable_irq_nosync(tegra_dcs[0]->irq);
1887         }
1888
1889         msleep(5);
1890         tegra_periph_reset_assert(dc->clk);
1891         msleep(2);
1892 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1893         tegra_periph_reset_deassert(dc->clk);
1894         msleep(1);
1895 #endif
1896
1897         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1898                 enable_dc_irq(tegra_dcs[1]);
1899                 mutex_unlock(&tegra_dcs[1]->lock);
1900         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1901                 enable_dc_irq(tegra_dcs[0]);
1902                 mutex_unlock(&tegra_dcs[0]->lock);
1903         }
1904
1905         enable_dc_irq(dc);
1906
1907         if (tegra_dc_init(dc)) {
1908                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1909                 ret = false;
1910         }
1911
1912         if (dc->out_ops && dc->out_ops->enable)
1913                 dc->out_ops->enable(dc);
1914
1915         if (dc->out->postpoweron)
1916                 dc->out->postpoweron();
1917
1918         /* force a full blending update */
1919         dc->blend.z[0] = -1;
1920
1921         tegra_dc_ext_enable(dc->ext);
1922
1923         if (!ret) {
1924                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1925                 _tegra_dc_controller_disable(dc);
1926         }
1927
1928         trace_display_reset(dc);
1929         return ret;
1930 }
1931 #endif
1932
1933 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1934 {
1935         if (dc->mode.pclk == 0) {
1936                 switch (dc->out->type) {
1937                 case TEGRA_DC_OUT_HDMI:
1938                 /* DC enable called but no videomode is loaded.
1939                      Check if HDMI is connected, then set fallback mdoe */
1940                 if (tegra_dc_hpd(dc)) {
1941                         return tegra_dc_set_fb_mode(dc,
1942                                         &tegra_dc_hdmi_fallback_mode, 0);
1943                 } else
1944                         return false;
1945
1946                 break;
1947
1948                 /* Do nothing for other outputs for now */
1949                 case TEGRA_DC_OUT_RGB:
1950
1951                 case TEGRA_DC_OUT_DSI:
1952
1953                 default:
1954                         return false;
1955                 }
1956         }
1957
1958         return false;
1959 }
1960
1961 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1962 {
1963         return _tegra_dc_set_default_videomode(dc);
1964 }
1965
1966 static bool _tegra_dc_enable(struct tegra_dc *dc)
1967 {
1968         if (dc->mode.pclk == 0)
1969                 return false;
1970
1971         if (!dc->out)
1972                 return false;
1973
1974         if (dc->enabled)
1975                 return true;
1976
1977         pm_runtime_get_sync(&dc->ndev->dev);
1978
1979         if (!_tegra_dc_controller_enable(dc)) {
1980                 pm_runtime_put_sync(&dc->ndev->dev);
1981                 return false;
1982         }
1983
1984         return true;
1985 }
1986
1987 void tegra_dc_enable(struct tegra_dc *dc)
1988 {
1989         mutex_lock(&dc->lock);
1990
1991         if (!dc->enabled)
1992                 dc->enabled = _tegra_dc_enable(dc);
1993
1994         mutex_unlock(&dc->lock);
1995         trace_display_mode(dc, &dc->mode);
1996 }
1997
1998 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1999 {
2000         unsigned i;
2001
2002         tegra_dc_hold_dc_out(dc);
2003
2004         if (dc->out && dc->out->prepoweroff)
2005                 dc->out->prepoweroff();
2006
2007         if (dc->out_ops && dc->out_ops->disable)
2008                 dc->out_ops->disable(dc);
2009
2010         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2011
2012         disable_irq_nosync(dc->irq);
2013
2014         tegra_dc_clear_bandwidth(dc);
2015
2016         /* ugly hack */
2017         if (dc->out_ops->release &&
2018                 (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE))
2019                 tegra_dc_release_dc_out(dc);
2020         else
2021                 tegra_dc_clk_disable(dc);
2022
2023         if (dc->out && dc->out->disable)
2024                 dc->out->disable();
2025
2026         for (i = 0; i < dc->n_windows; i++) {
2027                 struct tegra_dc_win *w = &dc->windows[i];
2028
2029                 /* reset window bandwidth */
2030                 w->bandwidth = 0;
2031                 w->new_bandwidth = 0;
2032
2033                 /* disable windows */
2034                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2035
2036                 /* flush any pending syncpt waits */
2037                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2038                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2039                                 dc->syncpt[i].min, dc->syncpt[i].max);
2040                         dc->syncpt[i].min++;
2041                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2042                 }
2043         }
2044         trace_display_disable(dc);
2045 }
2046
2047 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2048 {
2049 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2050         u32 val;
2051         if (dc->enabled)  {
2052                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2053                 if (enable)
2054                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2055                 else
2056                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2057                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2058         }
2059 #endif
2060 }
2061
2062 bool tegra_dc_stats_get(struct tegra_dc *dc)
2063 {
2064 #if 0 /* right now it is always enabled */
2065         u32 val;
2066         bool res;
2067
2068         if (dc->enabled)  {
2069                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2070                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2071         } else {
2072                 res = false;
2073         }
2074
2075         return res;
2076 #endif
2077         return true;
2078 }
2079
2080 /* make the screen blank by disabling all windows */
2081 void tegra_dc_blank(struct tegra_dc *dc)
2082 {
2083         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2084         unsigned i;
2085
2086         for (i = 0; i < DC_N_WINDOWS; i++) {
2087                 dcwins[i] = tegra_dc_get_window(dc, i);
2088                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2089         }
2090
2091         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2092         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2093 }
2094
2095 static void _tegra_dc_disable(struct tegra_dc *dc)
2096 {
2097         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2098                 mutex_lock(&dc->one_shot_lock);
2099                 cancel_delayed_work_sync(&dc->one_shot_work);
2100         }
2101
2102         tegra_dc_io_start(dc);
2103         _tegra_dc_controller_disable(dc);
2104         tegra_dc_io_end(dc);
2105
2106         tegra_dc_powergate_locked(dc);
2107
2108         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2109                 mutex_unlock(&dc->one_shot_lock);
2110         pm_runtime_put(&dc->ndev->dev);
2111 }
2112
2113 void tegra_dc_disable(struct tegra_dc *dc)
2114 {
2115         tegra_dc_ext_disable(dc->ext);
2116
2117         /* it's important that new underflow work isn't scheduled before the
2118          * lock is acquired. */
2119         cancel_delayed_work_sync(&dc->underflow_work);
2120
2121         mutex_lock(&dc->lock);
2122
2123         if (dc->enabled) {
2124                 dc->enabled = false;
2125
2126                 if (!dc->suspended)
2127                         _tegra_dc_disable(dc);
2128         }
2129
2130 #ifdef CONFIG_SWITCH
2131         switch_set_state(&dc->modeset_switch, 0);
2132 #endif
2133
2134         mutex_unlock(&dc->lock);
2135         synchronize_irq(dc->irq);
2136         trace_display_mode(dc, &dc->mode);
2137 }
2138
2139 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2140 static void tegra_dc_reset_worker(struct work_struct *work)
2141 {
2142         struct tegra_dc *dc =
2143                 container_of(work, struct tegra_dc, reset_work);
2144
2145         unsigned long val = 0;
2146
2147         mutex_lock(&shared_lock);
2148
2149         dev_warn(&dc->ndev->dev,
2150                 "overlay stuck in underflow state.  resetting.\n");
2151
2152         tegra_dc_ext_disable(dc->ext);
2153
2154         mutex_lock(&dc->lock);
2155
2156         if (dc->enabled == false)
2157                 goto unlock;
2158
2159         dc->enabled = false;
2160
2161         /*
2162          * off host read bus
2163          */
2164         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2165         val &= ~(0x00000100);
2166         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2167
2168         /*
2169          * set DC to STOP mode
2170          */
2171         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2172
2173         msleep(10);
2174
2175         _tegra_dc_controller_disable(dc);
2176
2177         /* _tegra_dc_controller_reset_enable deasserts reset */
2178         _tegra_dc_controller_reset_enable(dc);
2179
2180         dc->enabled = true;
2181
2182         /* reopen host read bus */
2183         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2184         val &= ~(0x00000100);
2185         val |= 0x100;
2186         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2187
2188 unlock:
2189         mutex_unlock(&dc->lock);
2190         mutex_unlock(&shared_lock);
2191         trace_display_reset(dc);
2192 }
2193 #endif
2194
2195 static void tegra_dc_underflow_worker(struct work_struct *work)
2196 {
2197         struct tegra_dc *dc = container_of(
2198                 to_delayed_work(work), struct tegra_dc, underflow_work);
2199
2200         mutex_lock(&dc->lock);
2201         tegra_dc_io_start(dc);
2202         tegra_dc_hold_dc_out(dc);
2203
2204         if (dc->enabled) {
2205                 tegra_dc_underflow_handler(dc);
2206         }
2207         tegra_dc_release_dc_out(dc);
2208         tegra_dc_io_end(dc);
2209         mutex_unlock(&dc->lock);
2210 }
2211
2212 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2213 /* A mutex used to protect the critical section used by both DC heads. */
2214 static struct mutex tegra_dc_powergate_status_lock;
2215
2216 /* defer turning off DISA until DISB is turned off */
2217 void tegra_dc_powergate_locked(struct tegra_dc *dc)
2218 {
2219         struct tegra_dc *dc_partner;
2220
2221         mutex_lock(&tegra_dc_powergate_status_lock);
2222         /* Get the handler of the other display controller. */
2223         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2224         if (!dc_partner)
2225                 _tegra_dc_powergate_locked(dc);
2226         else if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2227                 /* If DISB is powergated, then powergate DISA. */
2228                 if (!dc_partner->powered)
2229                         _tegra_dc_powergate_locked(dc);
2230         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2231                 /* If DISA is enabled, only powergate DISB;
2232                  * otherwise, powergate DISA and DISB.
2233                  * */
2234                 if (dc_partner->enabled) {
2235                         _tegra_dc_powergate_locked(dc);
2236                 } else {
2237                         _tegra_dc_powergate_locked(dc);
2238                         _tegra_dc_powergate_locked(dc_partner);
2239                 }
2240         }
2241         mutex_unlock(&tegra_dc_powergate_status_lock);
2242 }
2243
2244
2245 /* to turn on DISB we must first power on DISA */
2246 void tegra_dc_unpowergate_locked(struct tegra_dc *dc)
2247 {
2248         mutex_lock(&tegra_dc_powergate_status_lock);
2249         if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2250                 struct tegra_dc *dc_partner;
2251
2252                 /* Get the handler of the other display controller. */
2253                 dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2254                 if (dc_partner)
2255                         _tegra_dc_unpowergate_locked(dc_partner);
2256         }
2257         _tegra_dc_unpowergate_locked(dc);
2258         mutex_unlock(&tegra_dc_powergate_status_lock);
2259 }
2260 #endif
2261
2262 #ifdef CONFIG_SWITCH
2263 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2264 {
2265         struct tegra_dc *dc =
2266                 container_of(sdev, struct tegra_dc, modeset_switch);
2267
2268         if (!sdev->state)
2269                 return sprintf(buf, "offline\n");
2270
2271         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2272 }
2273 #endif
2274
2275 static void tegra_dc_add_modes(struct tegra_dc *dc)
2276 {
2277         struct fb_monspecs specs;
2278         int i;
2279
2280         memset(&specs, 0, sizeof(specs));
2281         specs.max_x = dc->mode.h_active * 1000;
2282         specs.max_y = dc->mode.v_active * 1000;
2283         specs.modedb_len = dc->out->n_modes;
2284         specs.modedb = kzalloc(specs.modedb_len *
2285                 sizeof(struct fb_videomode), GFP_KERNEL);
2286         for (i = 0; i < dc->out->n_modes; i++)
2287                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2288                         &dc->out->modes[i]);
2289         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2290         kfree(specs.modedb);
2291 }
2292
2293 static int tegra_dc_probe(struct platform_device *ndev)
2294 {
2295         struct tegra_dc *dc;
2296         struct tegra_dc_mode *mode;
2297         struct clk *clk;
2298         struct clk *emc_clk;
2299         struct resource *res;
2300         struct resource *base_res;
2301         struct resource *fb_mem = NULL;
2302         int ret = 0;
2303         void __iomem *base;
2304         int irq;
2305         int i;
2306
2307         if (!ndev->dev.platform_data) {
2308                 dev_err(&ndev->dev, "no platform data\n");
2309                 return -ENOENT;
2310         }
2311
2312         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2313         if (!dc) {
2314                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2315                 return -ENOMEM;
2316         }
2317
2318         irq = platform_get_irq_byname(ndev, "irq");
2319         if (irq <= 0) {
2320                 dev_err(&ndev->dev, "no irq\n");
2321                 ret = -ENOENT;
2322                 goto err_free;
2323         }
2324
2325         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2326         if (!res) {
2327                 dev_err(&ndev->dev, "no mem resource\n");
2328                 ret = -ENOENT;
2329                 goto err_free;
2330         }
2331
2332         base_res = request_mem_region(res->start, resource_size(res),
2333                 ndev->name);
2334         if (!base_res) {
2335                 dev_err(&ndev->dev, "request_mem_region failed\n");
2336                 ret = -EBUSY;
2337                 goto err_free;
2338         }
2339
2340         base = ioremap(res->start, resource_size(res));
2341         if (!base) {
2342                 dev_err(&ndev->dev, "registers can't be mapped\n");
2343                 ret = -EBUSY;
2344                 goto err_release_resource_reg;
2345         }
2346         if (TEGRA_DISPLAY_BASE == res->start) {
2347                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2348                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2349                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2350                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2351                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2352         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2353                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2354                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2355                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2356                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2357                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2358         } else {
2359                 dev_err(&ndev->dev,
2360                         "Unknown base address %#08x: unable to assign syncpt\n",
2361                         res->start);
2362         }
2363
2364
2365         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2366
2367         clk = clk_get(&ndev->dev, NULL);
2368         if (IS_ERR_OR_NULL(clk)) {
2369                 dev_err(&ndev->dev, "can't get clock\n");
2370                 ret = -ENOENT;
2371                 goto err_iounmap_reg;
2372         }
2373
2374         emc_clk = clk_get(&ndev->dev, "emc");
2375         if (IS_ERR_OR_NULL(emc_clk)) {
2376                 dev_err(&ndev->dev, "can't get emc clock\n");
2377                 ret = -ENOENT;
2378                 goto err_put_clk;
2379         }
2380
2381         dc->clk = clk;
2382         dc->emc_clk = emc_clk;
2383         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2384         /* Initialize one shot work delay, it will be assigned by dsi
2385          * according to refresh rate later. */
2386         dc->one_shot_delay_ms = 40;
2387
2388         dc->base_res = base_res;
2389         dc->base = base;
2390         dc->irq = irq;
2391         dc->ndev = ndev;
2392         dc->pdata = ndev->dev.platform_data;
2393
2394         /*
2395          * The emc is a shared clock, it will be set based on
2396          * the requirements for each user on the bus.
2397          */
2398         dc->emc_clk_rate = 0;
2399
2400         mutex_init(&dc->lock);
2401         mutex_init(&dc->one_shot_lock);
2402 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2403         mutex_init(&tegra_dc_powergate_status_lock);
2404 #endif
2405         init_completion(&dc->frame_end_complete);
2406         init_waitqueue_head(&dc->wq);
2407         init_waitqueue_head(&dc->timestamp_wq);
2408 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2409         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2410 #endif
2411         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2412         dc->vblank_ref_count = 0;
2413 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2414         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2415 #endif
2416         dc->vpulse2_ref_count = 0;
2417         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2418         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2419
2420         tegra_dc_init_lut_defaults(&dc->fb_lut);
2421
2422         dc->n_windows = DC_N_WINDOWS;
2423         for (i = 0; i < dc->n_windows; i++) {
2424                 struct tegra_dc_win *win = &dc->windows[i];
2425                 win->idx = i;
2426                 win->dc = dc;
2427                 tegra_dc_init_csc_defaults(&win->csc);
2428                 tegra_dc_init_lut_defaults(&win->lut);
2429         }
2430
2431         ret = tegra_dc_set(dc, ndev->id);
2432         if (ret < 0) {
2433                 dev_err(&ndev->dev, "can't add dc\n");
2434                 goto err_put_emc_clk;
2435         }
2436
2437         platform_set_drvdata(ndev, dc);
2438
2439 #ifdef CONFIG_SWITCH
2440         dc->modeset_switch.name = dev_name(&ndev->dev);
2441         dc->modeset_switch.state = 0;
2442         dc->modeset_switch.print_state = switch_modeset_print_mode;
2443         ret = switch_dev_register(&dc->modeset_switch);
2444         if (ret < 0)
2445                 dev_err(&ndev->dev, "failed to register switch driver\n");
2446 #endif
2447
2448         tegra_dc_feature_register(dc);
2449
2450         if (dc->pdata->default_out)
2451                 tegra_dc_set_out(dc, dc->pdata->default_out);
2452         else
2453                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2454         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2455
2456         dc->ext = tegra_dc_ext_register(ndev, dc);
2457         if (IS_ERR_OR_NULL(dc->ext)) {
2458                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2459                 dc->ext = NULL;
2460         }
2461
2462         /* interrupt handler must be registered before tegra_fb_register() */
2463         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2464                         dev_name(&ndev->dev), dc)) {
2465                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2466                 ret = -EBUSY;
2467                 goto err_disable_dc;
2468         }
2469         disable_dc_irq(dc);
2470
2471         pm_runtime_use_autosuspend(&ndev->dev);
2472         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
2473         pm_runtime_enable(&ndev->dev);
2474
2475         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2476                 _tegra_dc_set_default_videomode(dc);
2477                 dc->enabled = _tegra_dc_enable(dc);
2478         }
2479
2480         tegra_dc_create_debugfs(dc);
2481
2482         dev_info(&ndev->dev, "probed\n");
2483
2484         if (dc->pdata->fb) {
2485                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2486                         unsigned long fmt;
2487                         tegra_dc_writel(dc,
2488                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2489                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2490
2491                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2492                         dc->pdata->fb->bits_per_pixel =
2493                                 tegra_dc_fmt_bpp(fmt);
2494                 }
2495
2496                 mode = tegra_dc_get_override_mode(dc);
2497                 if (mode) {
2498                         dc->pdata->fb->xres = mode->h_active;
2499                         dc->pdata->fb->yres = mode->v_active;
2500                 }
2501
2502                 tegra_dc_io_start(dc);
2503                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2504                 tegra_dc_io_end(dc);
2505                 if (IS_ERR_OR_NULL(dc->fb)) {
2506                         dc->fb = NULL;
2507                         dev_err(&ndev->dev, "failed to register fb\n");
2508                         goto err_remove_debugfs;
2509                 }
2510         }
2511
2512         if (dc->out && dc->out->n_modes)
2513                 tegra_dc_add_modes(dc);
2514
2515         if (dc->out && dc->out->hotplug_init)
2516                 dc->out->hotplug_init(&ndev->dev);
2517
2518         if (dc->out_ops && dc->out_ops->detect)
2519                 dc->out_ops->detect(dc);
2520         else
2521                 dc->connected = true;
2522
2523         /* Powergate display module when it's unconnected. */
2524         if (!tegra_dc_get_connected(dc))
2525                 tegra_dc_powergate_locked(dc);
2526
2527         tegra_dc_create_sysfs(&dc->ndev->dev);
2528
2529         return 0;
2530
2531 err_remove_debugfs:
2532         tegra_dc_remove_debugfs(dc);
2533         free_irq(irq, dc);
2534 err_disable_dc:
2535         if (dc->ext) {
2536                 tegra_dc_ext_disable(dc->ext);
2537                 tegra_dc_ext_unregister(dc->ext);
2538         }
2539         mutex_lock(&dc->lock);
2540         if (dc->enabled)
2541                 _tegra_dc_disable(dc);
2542         dc->enabled = false;
2543         mutex_unlock(&dc->lock);
2544 #ifdef CONFIG_SWITCH
2545         switch_dev_unregister(&dc->modeset_switch);
2546 #endif
2547 err_put_emc_clk:
2548         clk_put(emc_clk);
2549 err_put_clk:
2550         clk_put(clk);
2551 err_iounmap_reg:
2552         iounmap(base);
2553         if (fb_mem)
2554                 release_resource(fb_mem);
2555 err_release_resource_reg:
2556         release_resource(base_res);
2557 err_free:
2558         kfree(dc);
2559
2560         return ret;
2561 }
2562
2563 static int tegra_dc_remove(struct platform_device *ndev)
2564 {
2565         struct tegra_dc *dc = platform_get_drvdata(ndev);
2566
2567         tegra_dc_remove_sysfs(&dc->ndev->dev);
2568         tegra_dc_remove_debugfs(dc);
2569
2570         if (dc->fb) {
2571                 tegra_fb_unregister(dc->fb);
2572                 if (dc->fb_mem)
2573                         release_resource(dc->fb_mem);
2574         }
2575
2576         tegra_dc_ext_disable(dc->ext);
2577
2578         if (dc->ext)
2579                 tegra_dc_ext_unregister(dc->ext);
2580
2581         mutex_lock(&dc->lock);
2582         if (dc->enabled)
2583                 _tegra_dc_disable(dc);
2584         dc->enabled = false;
2585         mutex_unlock(&dc->lock);
2586         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2587
2588 #ifdef CONFIG_SWITCH
2589         switch_dev_unregister(&dc->modeset_switch);
2590 #endif
2591         free_irq(dc->irq, dc);
2592         clk_put(dc->emc_clk);
2593         clk_put(dc->clk);
2594         iounmap(dc->base);
2595         if (dc->fb_mem)
2596                 release_resource(dc->base_res);
2597         kfree(dc);
2598         tegra_dc_set(NULL, ndev->id);
2599
2600         return 0;
2601 }
2602
2603 #ifdef CONFIG_PM
2604 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2605 {
2606         struct tegra_dc *dc = platform_get_drvdata(ndev);
2607
2608         trace_display_suspend(dc);
2609         dev_info(&ndev->dev, "suspend\n");
2610
2611         tegra_dc_ext_disable(dc->ext);
2612
2613         mutex_lock(&dc->lock);
2614         tegra_dc_io_start(dc);
2615
2616         if (dc->out_ops && dc->out_ops->suspend)
2617                 dc->out_ops->suspend(dc);
2618
2619         if (dc->enabled) {
2620                 _tegra_dc_disable(dc);
2621
2622                 dc->suspended = true;
2623         }
2624
2625         if (dc->out && dc->out->postsuspend) {
2626                 dc->out->postsuspend();
2627                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2628                         /*
2629                          * avoid resume event due to voltage falling
2630                          */
2631                         msleep(100);
2632         }
2633
2634         tegra_dc_io_end(dc);
2635         mutex_unlock(&dc->lock);
2636         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2637
2638         return 0;
2639 }
2640
2641 static int tegra_dc_resume(struct platform_device *ndev)
2642 {
2643         struct tegra_dc *dc = platform_get_drvdata(ndev);
2644
2645         trace_display_resume(dc);
2646         dev_info(&ndev->dev, "resume\n");
2647
2648         mutex_lock(&dc->lock);
2649         dc->suspended = false;
2650
2651         if (dc->enabled) {
2652                 dc->enabled = false;
2653                 _tegra_dc_set_default_videomode(dc);
2654                 dc->enabled = _tegra_dc_enable(dc);
2655         }
2656
2657         if (dc->out && dc->out->hotplug_init)
2658                 dc->out->hotplug_init(&ndev->dev);
2659
2660         if (dc->out_ops && dc->out_ops->resume)
2661                 dc->out_ops->resume(dc);
2662         mutex_unlock(&dc->lock);
2663
2664         return 0;
2665 }
2666
2667 #endif /* CONFIG_PM */
2668
2669 static void tegra_dc_shutdown(struct platform_device *ndev)
2670 {
2671         struct tegra_dc *dc = platform_get_drvdata(ndev);
2672
2673         if (!dc || !dc->enabled)
2674                 return;
2675
2676         tegra_dc_blank(dc);
2677         tegra_dc_disable(dc);
2678 }
2679
2680 extern int suspend_set(const char *val, struct kernel_param *kp)
2681 {
2682         if (!strcmp(val, "dump"))
2683                 dump_regs(tegra_dcs[0]);
2684 #ifdef CONFIG_PM
2685         else if (!strcmp(val, "suspend"))
2686                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2687         else if (!strcmp(val, "resume"))
2688                 tegra_dc_resume(tegra_dcs[0]->ndev);
2689 #endif
2690
2691         return 0;
2692 }
2693
2694 extern int suspend_get(char *buffer, struct kernel_param *kp)
2695 {
2696         return 0;
2697 }
2698
2699 int suspend;
2700
2701 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2702
2703 struct platform_driver tegra_dc_driver = {
2704         .driver = {
2705                 .name = "tegradc",
2706                 .owner = THIS_MODULE,
2707         },
2708         .probe = tegra_dc_probe,
2709         .remove = tegra_dc_remove,
2710 #ifdef CONFIG_PM
2711         .suspend = tegra_dc_suspend,
2712         .resume = tegra_dc_resume,
2713 #endif
2714         .shutdown = tegra_dc_shutdown,
2715 };
2716
2717 #ifndef MODULE
2718 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2719 {
2720         int i, params[11];
2721         char *p;
2722
2723         for (i = 0; i < ARRAY_SIZE(params); i++) {
2724                 if ((p = strsep(&options, ",")) != NULL) {
2725                         if (*p)
2726                                 params[i] = simple_strtoul(p, &p, 10);
2727                 } else
2728                         return -EINVAL;
2729         }
2730
2731         if ((mode->pclk = params[0]) == 0)
2732                 return -EINVAL;
2733
2734         mode->h_active      = params[1];
2735         mode->v_active      = params[2];
2736         mode->h_ref_to_sync = params[3];
2737         mode->v_ref_to_sync = params[4];
2738         mode->h_sync_width  = params[5];
2739         mode->v_sync_width  = params[6];
2740         mode->h_back_porch  = params[7];
2741         mode->v_back_porch  = params[8];
2742         mode->h_front_porch = params[9];
2743         mode->v_front_porch = params[10];
2744
2745         return 0;
2746 }
2747
2748 static int __init tegra_dc_mode_override(char *str)
2749 {
2750         char *p = str, *options;
2751
2752         if (!p || !*p)
2753                 return -EINVAL;
2754
2755         p = strstr(str, "hdmi:");
2756         if (p) {
2757                 p += 5;
2758                 options = strsep(&p, ";");
2759                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2760                         return -EINVAL;
2761         }
2762
2763         p = strstr(str, "rgb:");
2764         if (p) {
2765                 p += 4;
2766                 options = strsep(&p, ";");
2767                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2768                         return -EINVAL;
2769         }
2770
2771         p = strstr(str, "dsi:");
2772         if (p) {
2773                 p += 4;
2774                 options = strsep(&p, ";");
2775                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2776                         return -EINVAL;
2777         }
2778
2779         return 0;
2780 }
2781
2782 __setup("disp_params=", tegra_dc_mode_override);
2783 #endif
2784
2785 static int __init tegra_dc_module_init(void)
2786 {
2787         int ret = tegra_dc_ext_module_init();
2788         if (ret)
2789                 return ret;
2790         return platform_driver_register(&tegra_dc_driver);
2791 }
2792
2793 static void __exit tegra_dc_module_exit(void)
2794 {
2795         platform_driver_unregister(&tegra_dc_driver);
2796         tegra_dc_ext_module_exit();
2797 }
2798
2799 module_exit(tegra_dc_module_exit);
2800 module_init(tegra_dc_module_init);