ecdda6ca001fbe99154cee415d7dd02b0d1877e7
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #include <mach/clk.h>
45 #include <mach/dc.h>
46 #include <mach/fb.h>
47 #include <mach/mc.h>
48 #include <linux/nvhost.h>
49 #include <mach/latency_allowance.h>
50
51 #include "dc_reg.h"
52 #include "dc_config.h"
53 #include "dc_priv.h"
54 #include "dev.h"
55 #include "nvsd.h"
56
57 #define TEGRA_CRC_LATCHED_DELAY         34
58
59 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
60 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
61
62 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
63         .refresh = 60,
64         .xres = 640,
65         .yres = 480,
66         .pixclock = KHZ2PICOS(25200),
67         .hsync_len = 96,        /* h_sync_width */
68         .vsync_len = 2,         /* v_sync_width */
69         .left_margin = 48,      /* h_back_porch */
70         .upper_margin = 33,     /* v_back_porch */
71         .right_margin = 16,     /* h_front_porch */
72         .lower_margin = 10,     /* v_front_porch */
73         .vmode = 0,
74         .sync = 0,
75 };
76
77 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
78
79 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
80
81 DEFINE_MUTEX(tegra_dc_lock);
82 DEFINE_MUTEX(shared_lock);
83
84 static const struct {
85         bool h;
86         bool v;
87 } can_filter[] = {
88         /* Window A has no filtering */
89         { false, false },
90         /* Window B has both H and V filtering */
91         { true,  true  },
92         /* Window C has only H filtering */
93         { false, true  },
94 };
95
96 #ifdef CONFIG_TEGRA_DC_CMU
97 static struct tegra_dc_cmu default_cmu = {
98         /* lut1 maps sRGB to linear space. */
99         {
100                 0,    1,    2,    4,    5,    6,    7,    9,
101                 10,   11,   12,   14,   15,   16,   18,   20,
102                 21,   23,   25,   27,   29,   31,   33,   35,
103                 37,   40,   42,   45,   48,   50,   53,   56,
104                 59,   62,   66,   69,   72,   76,   79,   83,
105                 87,   91,   95,   99,   103,  107,  112,  116,
106                 121,  126,  131,  136,  141,  146,  151,  156,
107                 162,  168,  173,  179,  185,  191,  197,  204,
108                 210,  216,  223,  230,  237,  244,  251,  258,
109                 265,  273,  280,  288,  296,  304,  312,  320,
110                 329,  337,  346,  354,  363,  372,  381,  390,
111                 400,  409,  419,  428,  438,  448,  458,  469,
112                 479,  490,  500,  511,  522,  533,  544,  555,
113                 567,  578,  590,  602,  614,  626,  639,  651,
114                 664,  676,  689,  702,  715,  728,  742,  755,
115                 769,  783,  797,  811,  825,  840,  854,  869,
116                 884,  899,  914,  929,  945,  960,  976,  992,
117                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
118                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
119                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
120                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
121                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
122                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
123                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
124                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
125                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
126                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
127                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
128                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
129                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
130                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
131                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
132         },
133         /* csc */
134         {
135                 0x100, 0x0,   0x0,
136                 0x0,   0x100, 0x0,
137                 0x0,   0x0,   0x100,
138         },
139         /* lut2 maps linear space to sRGB*/
140         {
141                 0,    1,    2,    2,    3,    4,    5,    6,
142                 6,    7,    8,    9,    10,   10,   11,   12,
143                 13,   13,   14,   15,   15,   16,   16,   17,
144                 18,   18,   19,   19,   20,   20,   21,   21,
145                 22,   22,   23,   23,   23,   24,   24,   25,
146                 25,   25,   26,   26,   27,   27,   27,   28,
147                 28,   29,   29,   29,   30,   30,   30,   31,
148                 31,   31,   32,   32,   32,   33,   33,   33,
149                 34,   34,   34,   34,   35,   35,   35,   36,
150                 36,   36,   37,   37,   37,   37,   38,   38,
151                 38,   38,   39,   39,   39,   40,   40,   40,
152                 40,   41,   41,   41,   41,   42,   42,   42,
153                 42,   43,   43,   43,   43,   43,   44,   44,
154                 44,   44,   45,   45,   45,   45,   46,   46,
155                 46,   46,   46,   47,   47,   47,   47,   48,
156                 48,   48,   48,   48,   49,   49,   49,   49,
157                 49,   50,   50,   50,   50,   50,   51,   51,
158                 51,   51,   51,   52,   52,   52,   52,   52,
159                 53,   53,   53,   53,   53,   54,   54,   54,
160                 54,   54,   55,   55,   55,   55,   55,   55,
161                 56,   56,   56,   56,   56,   57,   57,   57,
162                 57,   57,   57,   58,   58,   58,   58,   58,
163                 58,   59,   59,   59,   59,   59,   59,   60,
164                 60,   60,   60,   60,   60,   61,   61,   61,
165                 61,   61,   61,   62,   62,   62,   62,   62,
166                 62,   63,   63,   63,   63,   63,   63,   64,
167                 64,   64,   64,   64,   64,   64,   65,   65,
168                 65,   65,   65,   65,   66,   66,   66,   66,
169                 66,   66,   66,   67,   67,   67,   67,   67,
170                 67,   67,   68,   68,   68,   68,   68,   68,
171                 68,   69,   69,   69,   69,   69,   69,   69,
172                 70,   70,   70,   70,   70,   70,   70,   71,
173                 71,   71,   71,   71,   71,   71,   72,   72,
174                 72,   72,   72,   72,   72,   72,   73,   73,
175                 73,   73,   73,   73,   73,   74,   74,   74,
176                 74,   74,   74,   74,   74,   75,   75,   75,
177                 75,   75,   75,   75,   75,   76,   76,   76,
178                 76,   76,   76,   76,   77,   77,   77,   77,
179                 77,   77,   77,   77,   78,   78,   78,   78,
180                 78,   78,   78,   78,   78,   79,   79,   79,
181                 79,   79,   79,   79,   79,   80,   80,   80,
182                 80,   80,   80,   80,   80,   81,   81,   81,
183                 81,   81,   81,   81,   81,   81,   82,   82,
184                 82,   82,   82,   82,   82,   82,   83,   83,
185                 83,   83,   83,   83,   83,   83,   83,   84,
186                 84,   84,   84,   84,   84,   84,   84,   84,
187                 85,   85,   85,   85,   85,   85,   85,   85,
188                 85,   86,   86,   86,   86,   86,   86,   86,
189                 86,   86,   87,   87,   87,   87,   87,   87,
190                 87,   87,   87,   88,   88,   88,   88,   88,
191                 88,   88,   88,   88,   88,   89,   89,   89,
192                 89,   89,   89,   89,   89,   89,   90,   90,
193                 90,   90,   90,   90,   90,   90,   90,   90,
194                 91,   91,   91,   91,   91,   91,   91,   91,
195                 91,   91,   92,   92,   92,   92,   92,   92,
196                 92,   92,   92,   92,   93,   93,   93,   93,
197                 93,   93,   93,   93,   93,   93,   94,   94,
198                 94,   94,   94,   94,   94,   94,   94,   94,
199                 95,   95,   95,   95,   95,   95,   95,   95,
200                 95,   95,   96,   96,   96,   96,   96,   96,
201                 96,   96,   96,   96,   96,   97,   97,   97,
202                 97,   97,   97,   97,   97,   97,   97,   98,
203                 98,   98,   98,   98,   98,   98,   98,   98,
204                 98,   98,   99,   99,   99,   99,   99,   99,
205                 99,   100,  101,  101,  102,  103,  103,  104,
206                 105,  105,  106,  107,  107,  108,  109,  109,
207                 110,  111,  111,  112,  113,  113,  114,  115,
208                 115,  116,  116,  117,  118,  118,  119,  119,
209                 120,  120,  121,  122,  122,  123,  123,  124,
210                 124,  125,  126,  126,  127,  127,  128,  128,
211                 129,  129,  130,  130,  131,  131,  132,  132,
212                 133,  133,  134,  134,  135,  135,  136,  136,
213                 137,  137,  138,  138,  139,  139,  140,  140,
214                 141,  141,  142,  142,  143,  143,  144,  144,
215                 145,  145,  145,  146,  146,  147,  147,  148,
216                 148,  149,  149,  150,  150,  150,  151,  151,
217                 152,  152,  153,  153,  153,  154,  154,  155,
218                 155,  156,  156,  156,  157,  157,  158,  158,
219                 158,  159,  159,  160,  160,  160,  161,  161,
220                 162,  162,  162,  163,  163,  164,  164,  164,
221                 165,  165,  166,  166,  166,  167,  167,  167,
222                 168,  168,  169,  169,  169,  170,  170,  170,
223                 171,  171,  172,  172,  172,  173,  173,  173,
224                 174,  174,  174,  175,  175,  176,  176,  176,
225                 177,  177,  177,  178,  178,  178,  179,  179,
226                 179,  180,  180,  180,  181,  181,  182,  182,
227                 182,  183,  183,  183,  184,  184,  184,  185,
228                 185,  185,  186,  186,  186,  187,  187,  187,
229                 188,  188,  188,  189,  189,  189,  189,  190,
230                 190,  190,  191,  191,  191,  192,  192,  192,
231                 193,  193,  193,  194,  194,  194,  195,  195,
232                 195,  196,  196,  196,  196,  197,  197,  197,
233                 198,  198,  198,  199,  199,  199,  200,  200,
234                 200,  200,  201,  201,  201,  202,  202,  202,
235                 202,  203,  203,  203,  204,  204,  204,  205,
236                 205,  205,  205,  206,  206,  206,  207,  207,
237                 207,  207,  208,  208,  208,  209,  209,  209,
238                 209,  210,  210,  210,  211,  211,  211,  211,
239                 212,  212,  212,  213,  213,  213,  213,  214,
240                 214,  214,  214,  215,  215,  215,  216,  216,
241                 216,  216,  217,  217,  217,  217,  218,  218,
242                 218,  219,  219,  219,  219,  220,  220,  220,
243                 220,  221,  221,  221,  221,  222,  222,  222,
244                 223,  223,  223,  223,  224,  224,  224,  224,
245                 225,  225,  225,  225,  226,  226,  226,  226,
246                 227,  227,  227,  227,  228,  228,  228,  228,
247                 229,  229,  229,  229,  230,  230,  230,  230,
248                 231,  231,  231,  231,  232,  232,  232,  232,
249                 233,  233,  233,  233,  234,  234,  234,  234,
250                 235,  235,  235,  235,  236,  236,  236,  236,
251                 237,  237,  237,  237,  238,  238,  238,  238,
252                 239,  239,  239,  239,  240,  240,  240,  240,
253                 240,  241,  241,  241,  241,  242,  242,  242,
254                 242,  243,  243,  243,  243,  244,  244,  244,
255                 244,  244,  245,  245,  245,  245,  246,  246,
256                 246,  246,  247,  247,  247,  247,  247,  248,
257                 248,  248,  248,  249,  249,  249,  249,  249,
258                 250,  250,  250,  250,  251,  251,  251,  251,
259                 251,  252,  252,  252,  252,  253,  253,  253,
260                 253,  253,  254,  254,  254,  254,  255,  255,
261         },
262 };
263 #endif
264
265 static inline void tegra_dc_clk_enable(struct tegra_dc *dc)
266 {
267         if (!tegra_is_clk_enabled(dc->clk)) {
268                 clk_enable(dc->clk);
269                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
270         }
271 }
272
273 static inline void tegra_dc_clk_disable(struct tegra_dc *dc)
274 {
275         if (tegra_is_clk_enabled(dc->clk)) {
276                 clk_disable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, 0);
278         }
279 }
280
281 #define DUMP_REG(a) do {                        \
282         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n", \
283                  #a, a, tegra_dc_readl(dc, a));               \
284         print(data, buff);                                    \
285         } while (0)
286
287 #define print_underflow_info(dc) do {                 \
288         trace_printk("%s:Underflow stats: underflows : %llu, "      \
289                         "undeflows_a : %llu, "                          \
290                         "underflows_b : %llu, "                         \
291                         "underflows_c : %llu\n",                        \
292                         dc->ndev->name,                                 \
293                         dc->stats.underflows,                           \
294                         dc->stats.underflows_a, dc->stats.underflows_b, \
295                         dc->stats.underflows_c);                        \
296         } while (0)
297
298 static void _dump_regs(struct tegra_dc *dc, void *data,
299                        void (* print)(void *data, const char *str))
300 {
301         int i;
302         char buff[256];
303
304         tegra_dc_io_start(dc);
305         tegra_dc_clk_enable(dc);
306
307         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
308         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
309         DUMP_REG(DC_CMD_SIGNAL_RAISE);
310         DUMP_REG(DC_CMD_INT_STATUS);
311         DUMP_REG(DC_CMD_INT_MASK);
312         DUMP_REG(DC_CMD_INT_ENABLE);
313         DUMP_REG(DC_CMD_INT_TYPE);
314         DUMP_REG(DC_CMD_INT_POLARITY);
315         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
317         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
318         DUMP_REG(DC_CMD_STATE_ACCESS);
319         DUMP_REG(DC_CMD_STATE_CONTROL);
320         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
321         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
322
323         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
324         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
325         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
326         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
327         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
328         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
329         DUMP_REG(DC_DISP_REF_TO_SYNC);
330         DUMP_REG(DC_DISP_SYNC_WIDTH);
331         DUMP_REG(DC_DISP_BACK_PORCH);
332         DUMP_REG(DC_DISP_DISP_ACTIVE);
333         DUMP_REG(DC_DISP_FRONT_PORCH);
334         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
335         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
336         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
337         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
338         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
339         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
340         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
341         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
342         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
343         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
344         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
345         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
346         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
347         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
348         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
349         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
350         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
351         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
352         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
353         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
354         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
355         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
356         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
357         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
358         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
359         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
360         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
361         DUMP_REG(DC_DISP_M0_CONTROL);
362         DUMP_REG(DC_DISP_M1_CONTROL);
363         DUMP_REG(DC_DISP_DI_CONTROL);
364         DUMP_REG(DC_DISP_PP_CONTROL);
365         DUMP_REG(DC_DISP_PP_SELECT_A);
366         DUMP_REG(DC_DISP_PP_SELECT_B);
367         DUMP_REG(DC_DISP_PP_SELECT_C);
368         DUMP_REG(DC_DISP_PP_SELECT_D);
369         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
370         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
371         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
372         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
373         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
374         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
375         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
376         DUMP_REG(DC_DISP_BORDER_COLOR);
377         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
378         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
379         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
380         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
381         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
382         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
383         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
384         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
385         DUMP_REG(DC_DISP_CURSOR_POSITION);
386         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
387         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
388         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
389         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
390         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
391         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
392         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
393         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
394         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
395         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
396         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
397         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
398         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
399
400
401         for (i = 0; i < 3; i++) {
402                 print(data, "\n");
403                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
404                 print(data, buff);
405
406                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
407                                 DC_CMD_DISPLAY_WINDOW_HEADER);
408                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
409                 DUMP_REG(DC_WIN_WIN_OPTIONS);
410                 DUMP_REG(DC_WIN_BYTE_SWAP);
411                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
412                 DUMP_REG(DC_WIN_COLOR_DEPTH);
413                 DUMP_REG(DC_WIN_POSITION);
414                 DUMP_REG(DC_WIN_SIZE);
415                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
416                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
417                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
418                 DUMP_REG(DC_WIN_DDA_INCREMENT);
419                 DUMP_REG(DC_WIN_LINE_STRIDE);
420 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
421                 DUMP_REG(DC_WIN_BUF_STRIDE);
422                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
423 #endif
424                 DUMP_REG(DC_WIN_BLEND_NOKEY);
425                 DUMP_REG(DC_WIN_BLEND_1WIN);
426                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
427                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
428                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
429                 DUMP_REG(DC_WINBUF_START_ADDR);
430                 DUMP_REG(DC_WINBUF_START_ADDR_U);
431                 DUMP_REG(DC_WINBUF_START_ADDR_V);
432                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
433                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
434                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
435                 DUMP_REG(DC_WIN_CSC_YOF);
436                 DUMP_REG(DC_WIN_CSC_KYRGB);
437                 DUMP_REG(DC_WIN_CSC_KUR);
438                 DUMP_REG(DC_WIN_CSC_KVR);
439                 DUMP_REG(DC_WIN_CSC_KUG);
440                 DUMP_REG(DC_WIN_CSC_KVG);
441                 DUMP_REG(DC_WIN_CSC_KUB);
442                 DUMP_REG(DC_WIN_CSC_KVB);
443         }
444
445         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
446         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
447         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
448         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
449         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
450         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
451         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
452         DUMP_REG(DC_DISP_M1_CONTROL);
453         DUMP_REG(DC_COM_PM1_CONTROL);
454         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
455         DUMP_REG(DC_DISP_SD_CONTROL);
456
457         tegra_dc_clk_disable(dc);
458         tegra_dc_io_end(dc);
459 }
460
461 #undef DUMP_REG
462
463 #ifdef DEBUG
464 static void dump_regs_print(void *data, const char *str)
465 {
466         struct tegra_dc *dc = data;
467         dev_dbg(&dc->ndev->dev, "%s", str);
468 }
469
470 static void dump_regs(struct tegra_dc *dc)
471 {
472         _dump_regs(dc, dc, dump_regs_print);
473 }
474 #else /* !DEBUG */
475
476 static void dump_regs(struct tegra_dc *dc) {}
477
478 #endif /* DEBUG */
479
480 #ifdef CONFIG_DEBUG_FS
481
482 static void dbg_regs_print(void *data, const char *str)
483 {
484         struct seq_file *s = data;
485
486         seq_printf(s, "%s", str);
487 }
488
489 #undef DUMP_REG
490
491 static int dbg_dc_show(struct seq_file *s, void *unused)
492 {
493         struct tegra_dc *dc = s->private;
494
495         _dump_regs(dc, s, dbg_regs_print);
496
497         return 0;
498 }
499
500
501 static int dbg_dc_open(struct inode *inode, struct file *file)
502 {
503         return single_open(file, dbg_dc_show, inode->i_private);
504 }
505
506 static const struct file_operations regs_fops = {
507         .open           = dbg_dc_open,
508         .read           = seq_read,
509         .llseek         = seq_lseek,
510         .release        = single_release,
511 };
512
513 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
514 {
515         struct tegra_dc *dc = s->private;
516         struct tegra_dc_mode *m;
517
518         mutex_lock(&dc->lock);
519         m = &dc->mode;
520         seq_printf(s,
521                 "pclk: %d\n"
522                 "h_ref_to_sync: %d\n"
523                 "v_ref_to_sync: %d\n"
524                 "h_sync_width: %d\n"
525                 "v_sync_width: %d\n"
526                 "h_back_porch: %d\n"
527                 "v_back_porch: %d\n"
528                 "h_active: %d\n"
529                 "v_active: %d\n"
530                 "h_front_porch: %d\n"
531                 "v_front_porch: %d\n"
532                 "stereo_mode: %d\n",
533                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
534                 m->h_sync_width, m->v_sync_width,
535                 m->h_back_porch, m->v_back_porch,
536                 m->h_active, m->v_active,
537                 m->h_front_porch, m->v_front_porch,
538                 m->stereo_mode);
539         mutex_unlock(&dc->lock);
540         return 0;
541 }
542
543 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
544 {
545         return single_open(file, dbg_dc_mode_show, inode->i_private);
546 }
547
548 static const struct file_operations mode_fops = {
549         .open           = dbg_dc_mode_open,
550         .read           = seq_read,
551         .llseek         = seq_lseek,
552         .release        = single_release,
553 };
554
555 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
556 {
557         struct tegra_dc *dc = s->private;
558
559         mutex_lock(&dc->lock);
560         seq_printf(s,
561                 "underflows: %llu\n"
562                 "underflows_a: %llu\n"
563                 "underflows_b: %llu\n"
564                 "underflows_c: %llu\n",
565                 dc->stats.underflows,
566                 dc->stats.underflows_a,
567                 dc->stats.underflows_b,
568                 dc->stats.underflows_c);
569         mutex_unlock(&dc->lock);
570
571         return 0;
572 }
573
574 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
575 {
576         return single_open(file, dbg_dc_stats_show, inode->i_private);
577 }
578
579 static const struct file_operations stats_fops = {
580         .open           = dbg_dc_stats_open,
581         .read           = seq_read,
582         .llseek         = seq_lseek,
583         .release        = single_release,
584 };
585
586 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
587 {
588         if (dc->debugdir)
589                 debugfs_remove_recursive(dc->debugdir);
590         dc->debugdir = NULL;
591 }
592
593 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
594 {
595         struct dentry *retval;
596
597         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
598         if (!dc->debugdir)
599                 goto remove_out;
600
601         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
602                 &regs_fops);
603         if (!retval)
604                 goto remove_out;
605
606         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
607                 &mode_fops);
608         if (!retval)
609                 goto remove_out;
610
611         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
612                 &stats_fops);
613         if (!retval)
614                 goto remove_out;
615
616         return;
617 remove_out:
618         dev_err(&dc->ndev->dev, "could not create debugfs\n");
619         tegra_dc_remove_debugfs(dc);
620 }
621
622 #else /* !CONFIG_DEBUGFS */
623 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
624 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
625 #endif /* CONFIG_DEBUGFS */
626
627 static int tegra_dc_set(struct tegra_dc *dc, int index)
628 {
629         int ret = 0;
630
631         mutex_lock(&tegra_dc_lock);
632         if (index >= TEGRA_MAX_DC) {
633                 ret = -EINVAL;
634                 goto out;
635         }
636
637         if (dc != NULL && tegra_dcs[index] != NULL) {
638                 ret = -EBUSY;
639                 goto out;
640         }
641
642         tegra_dcs[index] = dc;
643
644 out:
645         mutex_unlock(&tegra_dc_lock);
646
647         return ret;
648 }
649
650 unsigned int tegra_dc_has_multiple_dc(void)
651 {
652         unsigned int idx;
653         unsigned int cnt = 0;
654         struct tegra_dc *dc;
655
656         mutex_lock(&tegra_dc_lock);
657         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
658                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
659         mutex_unlock(&tegra_dc_lock);
660
661         return (cnt > 1);
662 }
663
664 /* get the stride size of a window.
665  * return: stride size in bytes for window win. or 0 if unavailble. */
666 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
667 {
668         u32 stride;
669
670         if (!dc->enabled)
671                 return 0;
672         BUG_ON(win > DC_N_WINDOWS);
673         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
674                 DC_CMD_DISPLAY_WINDOW_HEADER);
675         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
676         return GET_LINE_STRIDE(stride);
677 }
678 EXPORT_SYMBOL(tegra_dc_get_stride);
679
680 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
681 {
682         if (idx < TEGRA_MAX_DC)
683                 return tegra_dcs[idx];
684         else
685                 return NULL;
686 }
687 EXPORT_SYMBOL(tegra_dc_get_dc);
688
689 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
690 {
691         if (win >= dc->n_windows)
692                 return NULL;
693
694         return &dc->windows[win];
695 }
696 EXPORT_SYMBOL(tegra_dc_get_window);
697
698 bool tegra_dc_get_connected(struct tegra_dc *dc)
699 {
700         return dc->connected;
701 }
702 EXPORT_SYMBOL(tegra_dc_get_connected);
703
704 bool tegra_dc_hpd(struct tegra_dc *dc)
705 {
706         int sense;
707         int level;
708
709         level = gpio_get_value(dc->out->hotplug_gpio);
710
711         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
712
713         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
714                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
715 }
716 EXPORT_SYMBOL(tegra_dc_hpd);
717
718 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
719 {
720         unsigned i;
721         unsigned v0 = 128;
722         unsigned v1 = 0;
723         /* linear horizontal and vertical filters */
724         for (i = 0; i < 16; i++) {
725                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
726                                 DC_WIN_H_FILTER_P(i));
727
728                 tegra_dc_writel(dc, v0,
729                                 DC_WIN_V_FILTER_P(i));
730                 v0 -= 8;
731                 v1 += 8;
732         }
733 }
734
735 #ifdef CONFIG_TEGRA_DC_CMU
736 static void tegra_dc_init_cmu_defaults(struct tegra_dc_cmu *dst_cmu,
737                                                 struct tegra_dc_cmu *src_cmu)
738 {
739         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
740 }
741
742 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
743 {
744         u32 val;
745         u32 i;
746
747         for (i = 0; i < 256; i++) {
748                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
749                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
750         }
751
752         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
753         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
754         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
755         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
756         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
757         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
758         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
759         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
760         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
761
762         for (i = 0; i < 960; i++) {
763                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
764                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
765         }
766 }
767
768 static void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
769 {
770         u32 val;
771         u32 i;
772         bool flags;
773
774         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
775         if (val & CMU_ENABLE)
776                 flags = true;
777
778         val &= ~CMU_ENABLE;
779         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
780         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
781         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
782
783         /*TODO: Sync up with frame end */
784         mdelay(20);
785
786         for (i = 0; i < 256; i++) {
787                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
788                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
789                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
790                 cmu->lut1[i] = LUT1_READ_DATA(val);
791         }
792
793         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
794         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
795         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
796         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
797         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
798         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
799         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
800         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
801         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
802
803         for (i = 0; i < 960; i++) {
804                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
805                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
806                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
807                 cmu->lut2[i] = LUT2_READ_DATA(val);
808         }
809 }
810
811 static int tegra_dc_update_cmu(struct tegra_dc *dc, bool cmu_enable)
812 {
813         mutex_lock(&dc->lock);
814
815         if (!dc->enabled) {
816                 mutex_unlock(&dc->lock);
817                 return -EFAULT;
818         }
819
820         if (cmu_enable) {
821                 dc->out->flags |= TEGRA_DC_OUT_CMU_ENABLE;
822         } else {
823                 dc->out->flags &= ~TEGRA_DC_OUT_CMU_ENABLE;
824                 return 0;
825         }
826
827         tegra_dc_set_cmu(dc, &dc->cmu);
828
829         mutex_unlock(&dc->lock);
830
831         return 0;
832 }
833 EXPORT_SYMBOL(tegra_dc_update_cmu);
834 #else
835 #define tegra_dc_init_cmu_defaults(dst_cmu, src_cmu)
836 #define tegra_dc_set_cmu(dc, cmu)
837 #endif
838
839 void tegra_dc_host_suspend(struct tegra_dc *dc)
840 {
841         tegra_dsi_host_suspend(dc);
842         tegra_dc_clk_disable(dc);
843 }
844
845 void tegra_dc_host_resume(struct tegra_dc *dc) {
846         tegra_dc_clk_enable(dc);
847         tegra_dsi_host_resume(dc);
848 }
849
850 static inline void disable_dc_irq(unsigned int irq)
851 {
852         disable_irq(irq);
853 }
854
855 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
856 {
857         return dc->syncpt[i].id;
858 }
859 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
860
861 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
862 {
863         u32 max;
864
865         mutex_lock(&dc->lock);
866         max = nvhost_syncpt_incr_max_ext(dc->ndev,
867                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
868         dc->syncpt[i].max = max;
869         mutex_unlock(&dc->lock);
870
871         return max;
872 }
873
874 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
875 {
876         mutex_lock(&dc->lock);
877         if ( dc->enabled )
878                 while (dc->syncpt[i].min < val) {
879                         dc->syncpt[i].min++;
880                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
881                 }
882         mutex_unlock(&dc->lock);
883 }
884
885 void
886 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
887 {
888         unsigned int ctrl;
889         unsigned long out_sel;
890         unsigned long cmd_state;
891
892         mutex_lock(&dc->lock);
893         if (!dc->enabled) {
894                 mutex_unlock(&dc->lock);
895                 return;
896         }
897
898         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
899                 tegra_dc_host_resume(dc);
900
901         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
902                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
903                 cfg->clk_select);
904
905         /* The new value should be effected immediately */
906         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
907         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
908
909         if (cfg->switch_to_sfio && cfg->gpio_conf_to_sfio)
910                 cfg->switch_to_sfio(cfg->gpio_conf_to_sfio);
911         else
912                 dev_err(&dc->ndev->dev, "Error: Need gpio_conf_to_sfio\n");
913
914         switch (cfg->which_pwm) {
915         case TEGRA_PWM_PM0:
916                 /* Select the LM0 on PM0 */
917                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
918                 out_sel &= ~(7 << 0);
919                 out_sel |= (3 << 0);
920                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
921                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
922                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
923                 break;
924         case TEGRA_PWM_PM1:
925                 /* Select the LM1 on PM1 */
926                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
927                 out_sel &= ~(7 << 4);
928                 out_sel |= (3 << 4);
929                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
930                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
931                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
932                 break;
933         default:
934                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
935                 break;
936         }
937         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
938         mutex_unlock(&dc->lock);
939 }
940 EXPORT_SYMBOL(tegra_dc_config_pwm);
941
942 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
943                                 const struct tegra_dc_out_pin *pins,
944                                 const unsigned int n_pins)
945 {
946         unsigned int i;
947
948         int name;
949         int pol;
950
951         u32 pol1, pol3;
952
953         u32 set1, unset1;
954         u32 set3, unset3;
955
956         set1 = set3 = unset1 = unset3 = 0;
957
958         for (i = 0; i < n_pins; i++) {
959                 name = (pins + i)->name;
960                 pol  = (pins + i)->pol;
961
962                 /* set polarity by name */
963                 switch (name) {
964                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
965                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
966                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
967                         else
968                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
969                         break;
970                 case TEGRA_DC_OUT_PIN_H_SYNC:
971                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
972                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
973                         else
974                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
975                         break;
976                 case TEGRA_DC_OUT_PIN_V_SYNC:
977                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
978                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
979                         else
980                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
981                         break;
982                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
983                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
984                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
985                         else
986                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
987                         break;
988                 default:
989                         printk("Invalid argument in function %s\n",
990                                __FUNCTION__);
991                         break;
992                 }
993         }
994
995         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
996         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
997
998         pol1 |= set1;
999         pol1 &= ~unset1;
1000
1001         pol3 |= set3;
1002         pol3 &= ~unset3;
1003
1004         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1005         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1006 }
1007
1008 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1009 {
1010         dc->out = out;
1011
1012         if (out->n_modes > 0)
1013                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1014
1015         switch (out->type) {
1016         case TEGRA_DC_OUT_RGB:
1017                 dc->out_ops = &tegra_dc_rgb_ops;
1018                 break;
1019
1020         case TEGRA_DC_OUT_HDMI:
1021                 dc->out_ops = &tegra_dc_hdmi_ops;
1022                 break;
1023
1024         case TEGRA_DC_OUT_DSI:
1025                 dc->out_ops = &tegra_dc_dsi_ops;
1026                 break;
1027
1028         default:
1029                 dc->out_ops = NULL;
1030                 break;
1031         }
1032
1033         if (dc->out_ops && dc->out_ops->init)
1034                 dc->out_ops->init(dc);
1035
1036 }
1037
1038 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1039 {
1040         if (dc->out)
1041                 return dc->out->height;
1042         else
1043                 return 0;
1044 }
1045 EXPORT_SYMBOL(tegra_dc_get_out_height);
1046
1047 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1048 {
1049         if (dc->out)
1050                 return dc->out->width;
1051         else
1052                 return 0;
1053 }
1054 EXPORT_SYMBOL(tegra_dc_get_out_width);
1055
1056 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1057 {
1058         if (dc->out && dc->out->max_pixclock)
1059                 return dc->out->max_pixclock;
1060         else
1061                 return 0;
1062 }
1063 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1064
1065 void tegra_dc_enable_crc(struct tegra_dc *dc)
1066 {
1067         u32 val;
1068         tegra_dc_io_start(dc);
1069
1070         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1071                 CRC_ENABLE_ENABLE;
1072         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1073         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1074         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1075 }
1076
1077 void tegra_dc_disable_crc(struct tegra_dc *dc)
1078 {
1079         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1080         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1081         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1082
1083         tegra_dc_io_end(dc);
1084 }
1085
1086 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1087 {
1088         int crc = 0;
1089
1090         if (!dc) {
1091                 dev_err(&dc->ndev->dev, "Failed to get dc.\n");
1092                 goto crc_error;
1093         }
1094
1095 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1096         /* TODO: Replace mdelay with code to sync VBlANK, since
1097          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1098         mdelay(TEGRA_CRC_LATCHED_DELAY);
1099 #endif
1100
1101         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1102 crc_error:
1103         return crc;
1104 }
1105
1106 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1107 {
1108 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1109         u32 val;
1110
1111         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1112         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1113             return true;
1114 #endif
1115         return false;
1116 }
1117
1118 static inline void enable_dc_irq(unsigned int irq)
1119 {
1120 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1121         enable_irq(irq);
1122 #else
1123         /* Always disable DC interrupts on FPGA. */
1124         disable_irq(irq);
1125 #endif
1126 }
1127
1128 static void tegra_dc_vblank(struct work_struct *work)
1129 {
1130         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1131         bool nvsd_updated = false;
1132
1133         mutex_lock(&dc->lock);
1134
1135         if (!dc->enabled) {
1136                 mutex_unlock(&dc->lock);
1137                 return;
1138         }
1139
1140         /* use the new frame's bandwidth setting instead of max(current, new),
1141          * skip this if we're using tegra_dc_one_shot_worker() */
1142         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1143                 tegra_dc_program_bandwidth(dc, true);
1144
1145         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1146         if (!tegra_dc_windows_are_dirty(dc))
1147                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1148
1149         /* Update the SD brightness */
1150         if (dc->enabled && dc->out->sd_settings) {
1151                 nvsd_updated = nvsd_update_brightness(dc);
1152                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1153                  * V_BLANK_NVSD bit of vblank ref-count. */
1154                 if (nvsd_updated) {
1155                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1156                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1157                 } else {
1158                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1159                 }
1160         }
1161
1162         /* Mask vblank interrupt if ref-count is zero. */
1163         if (!dc->vblank_ref_count)
1164                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1165
1166         mutex_unlock(&dc->lock);
1167
1168         /* Do the actual brightness update outside of the mutex */
1169         if (nvsd_updated && dc->out->sd_settings &&
1170             dc->out->sd_settings->bl_device) {
1171
1172                 struct platform_device *pdev = dc->out->sd_settings->bl_device;
1173                 struct backlight_device *bl = platform_get_drvdata(pdev);
1174                 if (bl)
1175                         backlight_update_status(bl);
1176         }
1177 }
1178
1179 static void tegra_dc_one_shot_worker(struct work_struct *work)
1180 {
1181         struct tegra_dc *dc = container_of(
1182                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1183         mutex_lock(&dc->lock);
1184
1185         /* memory client has gone idle */
1186         tegra_dc_clear_bandwidth(dc);
1187
1188         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1189                 tegra_dc_host_suspend(dc);
1190
1191         mutex_unlock(&dc->lock);
1192 }
1193
1194 /* return an arbitrarily large number if count overflow occurs.
1195  * make it a nice base-10 number to show up in stats output */
1196 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1197 {
1198         unsigned count = tegra_dc_readl(dc, reg);
1199         tegra_dc_writel(dc, 0, reg);
1200         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1201 }
1202
1203 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1204 {
1205         u32 val;
1206         int i;
1207
1208         dc->stats.underflows++;
1209         if (dc->underflow_mask & WIN_A_UF_INT) {
1210                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1211                         DC_WINBUF_AD_UFLOW_STATUS);
1212                 trace_printk("%s:Window A Underflow\n", dc->ndev->name);
1213         }
1214         if (dc->underflow_mask & WIN_B_UF_INT) {
1215                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1216                         DC_WINBUF_BD_UFLOW_STATUS);
1217                 trace_printk("%s:Window B Underflow\n", dc->ndev->name);
1218         }
1219         if (dc->underflow_mask & WIN_C_UF_INT) {
1220                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1221                         DC_WINBUF_CD_UFLOW_STATUS);
1222                 trace_printk("%s:Window C Underflow\n", dc->ndev->name);
1223         }
1224
1225         /* Check for any underflow reset conditions */
1226         for (i = 0; i < DC_N_WINDOWS; i++) {
1227                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1228                         dc->windows[i].underflows++;
1229
1230 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1231                         if (dc->windows[i].underflows > 4) {
1232                                 schedule_work(&dc->reset_work);
1233                                 /* reset counter */
1234                                 dc->windows[i].underflows = 0;
1235                                 trace_printk("%s:Reset work scheduled for "
1236                                                 "window %c\n",
1237                                                 dc->ndev->name, (65 + i));
1238                         }
1239 #endif
1240 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1241                         if (dc->windows[i].underflows > 4) {
1242                                 printk("%s:dc in underflow state."
1243                                         " enable UF_LINE_FLUSH to clear up\n",
1244                                         __func__);
1245                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1246                                                 DC_DISP_DISP_MISC_CONTROL);
1247                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1248                                                 DC_CMD_STATE_CONTROL);
1249                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1250                                                 DC_CMD_STATE_CONTROL);
1251
1252                                 tegra_dc_writel(dc, 0,
1253                                                 DC_DISP_DISP_MISC_CONTROL);
1254                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1255                                                 DC_CMD_STATE_CONTROL);
1256                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1257                                                 DC_CMD_STATE_CONTROL);
1258                         }
1259 #endif
1260                 } else {
1261                         dc->windows[i].underflows = 0;
1262                 }
1263         }
1264
1265         /* Clear the underflow mask now that we've checked it. */
1266         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1267         dc->underflow_mask = 0;
1268         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1269         tegra_dc_writel(dc, val | ALL_UF_INT, DC_CMD_INT_MASK);
1270         print_underflow_info(dc);
1271 }
1272
1273 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1274 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1275 {
1276         if (status & V_BLANK_INT) {
1277                 /* Sync up windows. */
1278                 tegra_dc_trigger_windows(dc);
1279
1280                 /* Schedule any additional bottom-half vblank actvities. */
1281                 schedule_work(&dc->vblank_work);
1282         }
1283
1284         if (status & FRAME_END_INT) {
1285                 /* Mark the frame_end as complete. */
1286                 if (!completion_done(&dc->frame_end_complete))
1287                         complete(&dc->frame_end_complete);
1288         }
1289 }
1290
1291 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1292 {
1293         /* Schedule any additional bottom-half vblank actvities. */
1294         if (status & V_BLANK_INT)
1295                 schedule_work(&dc->vblank_work);
1296
1297         if (status & FRAME_END_INT) {
1298                 /* Mark the frame_end as complete. */
1299                 if (!completion_done(&dc->frame_end_complete))
1300                         complete(&dc->frame_end_complete);
1301
1302                 tegra_dc_trigger_windows(dc);
1303         }
1304 }
1305 #endif
1306
1307 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1308 {
1309 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1310         struct tegra_dc *dc = ptr;
1311         unsigned long status;
1312         unsigned long underflow_mask;
1313         u32 val;
1314
1315         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1316                 WARN(1, "IRQ when DC not powered!\n");
1317                 tegra_dc_io_start(dc);
1318                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1319                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1320                 tegra_dc_io_end(dc);
1321                 return IRQ_HANDLED;
1322         }
1323
1324         /* clear all status flags except underflow, save those for the worker */
1325         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1326         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1327         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1328         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1329
1330         /*
1331          * Overlays can get thier internal state corrupted during and underflow
1332          * condition.  The only way to fix this state is to reset the DC.
1333          * if we get 4 consecutive frames with underflows, assume we're
1334          * hosed and reset.
1335          */
1336         underflow_mask = status & ALL_UF_INT;
1337
1338         /* Check underflow */
1339         if (underflow_mask) {
1340                 dc->underflow_mask |= underflow_mask;
1341                 schedule_delayed_work(&dc->underflow_work,
1342                         msecs_to_jiffies(1));
1343         }
1344
1345         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1346                 tegra_dc_one_shot_irq(dc, status);
1347         else
1348                 tegra_dc_continuous_irq(dc, status);
1349
1350         return IRQ_HANDLED;
1351 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1352         return IRQ_NONE;
1353 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1354 }
1355
1356 static void tegra_dc_set_color_control(struct tegra_dc *dc)
1357 {
1358         u32 color_control;
1359
1360         switch (dc->out->depth) {
1361         case 3:
1362                 color_control = BASE_COLOR_SIZE111;
1363                 break;
1364
1365         case 6:
1366                 color_control = BASE_COLOR_SIZE222;
1367                 break;
1368
1369         case 8:
1370                 color_control = BASE_COLOR_SIZE332;
1371                 break;
1372
1373         case 9:
1374                 color_control = BASE_COLOR_SIZE333;
1375                 break;
1376
1377         case 12:
1378                 color_control = BASE_COLOR_SIZE444;
1379                 break;
1380
1381         case 15:
1382                 color_control = BASE_COLOR_SIZE555;
1383                 break;
1384
1385         case 16:
1386                 color_control = BASE_COLOR_SIZE565;
1387                 break;
1388
1389         case 18:
1390                 color_control = BASE_COLOR_SIZE666;
1391                 break;
1392
1393         default:
1394                 color_control = BASE_COLOR_SIZE888;
1395                 break;
1396         }
1397
1398         switch (dc->out->dither) {
1399         case TEGRA_DC_DISABLE_DITHER:
1400                 color_control |= DITHER_CONTROL_DISABLE;
1401                 break;
1402         case TEGRA_DC_ORDERED_DITHER:
1403                 color_control |= DITHER_CONTROL_ORDERED;
1404                 break;
1405         case TEGRA_DC_ERRDIFF_DITHER:
1406                 /* The line buffer for error-diffusion dither is limited
1407                  * to 1280 pixels per line. This limits the maximum
1408                  * horizontal active area size to 1280 pixels when error
1409                  * diffusion is enabled.
1410                  */
1411                 BUG_ON(dc->mode.h_active > 1280);
1412                 color_control |= DITHER_CONTROL_ERRDIFF;
1413                 break;
1414         }
1415
1416 #ifdef CONFIG_TEGRA_DC_CMU
1417         if (dc->out->flags & TEGRA_DC_OUT_CMU_ENABLE)
1418                 color_control |= CMU_ENABLE;
1419 #endif
1420
1421         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1422 }
1423
1424 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1425 {
1426         u32 syncpt_id;
1427
1428         switch (dc->ndev->id) {
1429         case 0:
1430                 switch (idx) {
1431                 case 0:
1432                         syncpt_id = NVSYNCPT_DISP0_A;
1433                         break;
1434                 case 1:
1435                         syncpt_id = NVSYNCPT_DISP0_B;
1436                         break;
1437                 case 2:
1438                         syncpt_id = NVSYNCPT_DISP0_C;
1439                         break;
1440                 default:
1441                         BUG();
1442                         break;
1443                 }
1444                 break;
1445         case 1:
1446                 switch (idx) {
1447                 case 0:
1448                         syncpt_id = NVSYNCPT_DISP1_A;
1449                         break;
1450                 case 1:
1451                         syncpt_id = NVSYNCPT_DISP1_B;
1452                         break;
1453                 case 2:
1454                         syncpt_id = NVSYNCPT_DISP1_C;
1455                         break;
1456                 default:
1457                         BUG();
1458                         break;
1459                 }
1460                 break;
1461         default:
1462                 BUG();
1463                 break;
1464         }
1465
1466         return syncpt_id;
1467 }
1468
1469 static int tegra_dc_init(struct tegra_dc *dc)
1470 {
1471         int i;
1472
1473         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1474         if (dc->ndev->id == 0) {
1475                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1476                                       TEGRA_MC_PRIO_MED);
1477                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1478                                       TEGRA_MC_PRIO_MED);
1479                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1480                                       TEGRA_MC_PRIO_MED);
1481                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1482                                       TEGRA_MC_PRIO_MED);
1483                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1484                                       TEGRA_MC_PRIO_HIGH);
1485         } else if (dc->ndev->id == 1) {
1486                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1487                                       TEGRA_MC_PRIO_MED);
1488                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1489                                       TEGRA_MC_PRIO_MED);
1490                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1491                                       TEGRA_MC_PRIO_MED);
1492                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1493                                       TEGRA_MC_PRIO_MED);
1494                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1495                                       TEGRA_MC_PRIO_HIGH);
1496         }
1497         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1498                         DC_CMD_CONT_SYNCPT_VSYNC);
1499         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1500         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1501         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1502         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1503 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1504         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1505 #endif
1506         /* enable interrupts for vblank, frame_end and underflows */
1507         tegra_dc_writel(dc, (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT),
1508                 DC_CMD_INT_ENABLE);
1509         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1510
1511         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1512
1513         tegra_dc_set_color_control(dc);
1514         for (i = 0; i < DC_N_WINDOWS; i++) {
1515                 struct tegra_dc_win *win = &dc->windows[i];
1516                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1517                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1518                 tegra_dc_set_csc(dc, &win->csc);
1519                 tegra_dc_set_lut(dc, win);
1520                 tegra_dc_set_scaling_filter(dc);
1521         }
1522
1523         tegra_dc_init_cmu_defaults(&dc->cmu, &default_cmu);
1524         tegra_dc_set_cmu(dc, &dc->cmu);
1525
1526         for (i = 0; i < dc->n_windows; i++) {
1527                 u32 syncpt = get_syncpt(dc, i);
1528
1529                 dc->syncpt[i].id = syncpt;
1530
1531                 dc->syncpt[i].min = dc->syncpt[i].max =
1532                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1533         }
1534
1535         print_mode_info(dc, dc->mode);
1536
1537         if (dc->mode.pclk)
1538                 if (tegra_dc_program_mode(dc, &dc->mode))
1539                         return -EINVAL;
1540
1541         /* Initialize SD AFTER the modeset.
1542            nvsd_init handles the sd_settings = NULL case. */
1543         nvsd_init(dc, dc->out->sd_settings);
1544
1545         return 0;
1546 }
1547
1548 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1549 {
1550         int failed_init = 0;
1551
1552         if (dc->out->enable)
1553                 dc->out->enable();
1554
1555         tegra_dc_setup_clk(dc, dc->clk);
1556         tegra_dc_clk_enable(dc);
1557
1558         /* do not accept interrupts during initialization */
1559         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1560         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1561
1562         enable_dc_irq(dc->irq);
1563
1564         failed_init = tegra_dc_init(dc);
1565         if (failed_init) {
1566                 _tegra_dc_controller_disable(dc);
1567                 return false;
1568         }
1569
1570         if (dc->out_ops && dc->out_ops->enable)
1571                 dc->out_ops->enable(dc);
1572
1573         if (dc->out->postpoweron)
1574                 dc->out->postpoweron();
1575
1576         /* force a full blending update */
1577         dc->blend.z[0] = -1;
1578
1579         tegra_dc_ext_enable(dc->ext);
1580
1581         trace_printk("%s:enable\n", dc->ndev->name);
1582         return true;
1583 }
1584
1585 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1586 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1587 {
1588         bool ret = true;
1589
1590         if (dc->out->enable)
1591                 dc->out->enable();
1592
1593         tegra_dc_setup_clk(dc, dc->clk);
1594         tegra_dc_clk_enable(dc);
1595
1596         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1597                 mutex_lock(&tegra_dcs[1]->lock);
1598                 disable_irq(tegra_dcs[1]->irq);
1599         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1600                 mutex_lock(&tegra_dcs[0]->lock);
1601                 disable_irq(tegra_dcs[0]->irq);
1602         }
1603
1604         msleep(5);
1605         tegra_periph_reset_assert(dc->clk);
1606         msleep(2);
1607 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1608         tegra_periph_reset_deassert(dc->clk);
1609         msleep(1);
1610 #endif
1611
1612         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1613                 enable_dc_irq(tegra_dcs[1]->irq);
1614                 mutex_unlock(&tegra_dcs[1]->lock);
1615         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1616                 enable_dc_irq(tegra_dcs[0]->irq);
1617                 mutex_unlock(&tegra_dcs[0]->lock);
1618         }
1619
1620         enable_dc_irq(dc->irq);
1621
1622         if (tegra_dc_init(dc)) {
1623                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1624                 ret = false;
1625         }
1626
1627         if (dc->out_ops && dc->out_ops->enable)
1628                 dc->out_ops->enable(dc);
1629
1630         if (dc->out->postpoweron)
1631                 dc->out->postpoweron();
1632
1633         /* force a full blending update */
1634         dc->blend.z[0] = -1;
1635
1636         tegra_dc_ext_enable(dc->ext);
1637
1638         if (!ret) {
1639                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1640                 _tegra_dc_controller_disable(dc);
1641         }
1642
1643         trace_printk("%s:reset enable\n", dc->ndev->name);
1644         return ret;
1645 }
1646 #endif
1647
1648 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1649 {
1650         return tegra_dc_set_fb_mode(dc, &tegra_dc_hdmi_fallback_mode, 0);
1651 }
1652
1653 static bool _tegra_dc_enable(struct tegra_dc *dc)
1654 {
1655         if (dc->mode.pclk == 0) {
1656                 switch (dc->out->type) {
1657                 case TEGRA_DC_OUT_HDMI:
1658                 /* DC enable called but no videomode is loaded.
1659                      Check if HDMI is connected, then set fallback mdoe */
1660                 if (tegra_dc_hpd(dc)) {
1661                         if (_tegra_dc_set_default_videomode(dc))
1662                                 return false;
1663                 } else
1664                         return false;
1665
1666                 break;
1667
1668                 /* Do nothing for other outputs for now */
1669                 case TEGRA_DC_OUT_RGB:
1670
1671                 case TEGRA_DC_OUT_DSI:
1672
1673                 default:
1674                         return false;
1675                 }
1676         }
1677
1678         if (!dc->out)
1679                 return false;
1680
1681         tegra_dc_io_start(dc);
1682
1683         return _tegra_dc_controller_enable(dc);
1684 }
1685
1686 void tegra_dc_enable(struct tegra_dc *dc)
1687 {
1688         mutex_lock(&dc->lock);
1689
1690         if (!dc->enabled)
1691                 dc->enabled = _tegra_dc_enable(dc);
1692
1693         mutex_unlock(&dc->lock);
1694         print_mode_info(dc, dc->mode);
1695 }
1696
1697 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1698 {
1699         unsigned i;
1700
1701         if (dc->out && dc->out->prepoweroff)
1702                 dc->out->prepoweroff();
1703
1704         if (dc->out_ops && dc->out_ops->disable)
1705                 dc->out_ops->disable(dc);
1706
1707         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1708         tegra_dc_writel(dc, 0, DC_CMD_INT_ENABLE);
1709         disable_irq(dc->irq);
1710
1711         tegra_dc_clear_bandwidth(dc);
1712         tegra_dc_clk_disable(dc);
1713
1714         if (dc->out && dc->out->disable)
1715                 dc->out->disable();
1716
1717         for (i = 0; i < dc->n_windows; i++) {
1718                 struct tegra_dc_win *w = &dc->windows[i];
1719
1720                 /* reset window bandwidth */
1721                 w->bandwidth = 0;
1722                 w->new_bandwidth = 0;
1723
1724                 /* disable windows */
1725                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1726
1727                 /* flush any pending syncpt waits */
1728                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1729                         trace_printk("%s:syncpt flush id=%d\n", dc->ndev->name,
1730                                 dc->syncpt[i].id);
1731                         dc->syncpt[i].min++;
1732                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1733                 }
1734         }
1735         trace_printk("%s:disabled\n", dc->ndev->name);
1736 }
1737
1738 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1739 {
1740 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1741         u32 val;
1742         if (dc->enabled)  {
1743                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1744                 if (enable)
1745                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1746                 else
1747                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1748                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1749         }
1750 #endif
1751 }
1752
1753 bool tegra_dc_stats_get(struct tegra_dc *dc)
1754 {
1755 #if 0 /* right now it is always enabled */
1756         u32 val;
1757         bool res;
1758
1759         if (dc->enabled)  {
1760                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1761                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1762         } else {
1763                 res = false;
1764         }
1765
1766         return res;
1767 #endif
1768         return true;
1769 }
1770
1771 /* make the screen blank by disabling all windows */
1772 void tegra_dc_blank(struct tegra_dc *dc)
1773 {
1774         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1775         unsigned i;
1776
1777         for (i = 0; i < DC_N_WINDOWS; i++) {
1778                 dcwins[i] = tegra_dc_get_window(dc, i);
1779                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1780         }
1781
1782         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1783         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1784 }
1785
1786 static void _tegra_dc_disable(struct tegra_dc *dc)
1787 {
1788         _tegra_dc_controller_disable(dc);
1789         tegra_dc_io_end(dc);
1790 }
1791
1792 void tegra_dc_disable(struct tegra_dc *dc)
1793 {
1794         tegra_dc_ext_disable(dc->ext);
1795
1796         /* it's important that new underflow work isn't scheduled before the
1797          * lock is acquired. */
1798         cancel_delayed_work_sync(&dc->underflow_work);
1799         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1800                 mutex_lock(&dc->one_shot_lock);
1801                 cancel_delayed_work_sync(&dc->one_shot_work);
1802         }
1803
1804         mutex_lock(&dc->lock);
1805
1806         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1807                 tegra_dc_host_resume(dc);
1808
1809         if (dc->enabled) {
1810                 dc->enabled = false;
1811
1812                 if (!dc->suspended)
1813                         _tegra_dc_disable(dc);
1814         }
1815
1816 #ifdef CONFIG_SWITCH
1817         switch_set_state(&dc->modeset_switch, 0);
1818 #endif
1819
1820         mutex_unlock(&dc->lock);
1821         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1822                 mutex_unlock(&dc->one_shot_lock);
1823         print_mode_info(dc, dc->mode);
1824 }
1825
1826 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1827 static void tegra_dc_reset_worker(struct work_struct *work)
1828 {
1829         struct tegra_dc *dc =
1830                 container_of(work, struct tegra_dc, reset_work);
1831
1832         unsigned long val = 0;
1833
1834         mutex_lock(&shared_lock);
1835
1836         dev_warn(&dc->ndev->dev,
1837                 "overlay stuck in underflow state.  resetting.\n");
1838
1839         tegra_dc_ext_disable(dc->ext);
1840
1841         mutex_lock(&dc->lock);
1842
1843         if (dc->enabled == false)
1844                 goto unlock;
1845
1846         dc->enabled = false;
1847
1848         /*
1849          * off host read bus
1850          */
1851         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1852         val &= ~(0x00000100);
1853         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1854
1855         /*
1856          * set DC to STOP mode
1857          */
1858         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1859
1860         msleep(10);
1861
1862         _tegra_dc_controller_disable(dc);
1863
1864         /* _tegra_dc_controller_reset_enable deasserts reset */
1865         _tegra_dc_controller_reset_enable(dc);
1866
1867         dc->enabled = true;
1868
1869         /* reopen host read bus */
1870         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
1871         val &= ~(0x00000100);
1872         val |= 0x100;
1873         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
1874
1875 unlock:
1876         mutex_unlock(&dc->lock);
1877         mutex_unlock(&shared_lock);
1878         trace_printk("%s:reset complete\n", dc->ndev->name);
1879 }
1880 #endif
1881
1882 static void tegra_dc_underflow_worker(struct work_struct *work)
1883 {
1884         struct tegra_dc *dc = container_of(
1885                 to_delayed_work(work), struct tegra_dc, underflow_work);
1886
1887         mutex_lock(&dc->lock);
1888         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_LP_MODE)
1889                 tegra_dc_host_resume(dc);
1890
1891         if (dc->enabled) {
1892                 tegra_dc_underflow_handler(dc);
1893         }
1894         mutex_unlock(&dc->lock);
1895 }
1896
1897 #ifdef CONFIG_SWITCH
1898 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
1899 {
1900         struct tegra_dc *dc =
1901                 container_of(sdev, struct tegra_dc, modeset_switch);
1902
1903         if (!sdev->state)
1904                 return sprintf(buf, "offline\n");
1905
1906         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
1907 }
1908 #endif
1909
1910 static int tegra_dc_probe(struct nvhost_device *ndev,
1911         struct nvhost_device_id *id_table)
1912 {
1913         struct tegra_dc *dc;
1914         struct clk *clk;
1915         struct clk *emc_clk;
1916         struct resource *res;
1917         struct resource *base_res;
1918         struct resource *fb_mem = NULL;
1919         int ret = 0;
1920         void __iomem *base;
1921         int irq;
1922         int i;
1923
1924         if (!ndev->dev.platform_data) {
1925                 dev_err(&ndev->dev, "no platform data\n");
1926                 return -ENOENT;
1927         }
1928
1929         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
1930         if (!dc) {
1931                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
1932                 return -ENOMEM;
1933         }
1934
1935         irq = nvhost_get_irq_byname(ndev, "irq");
1936         if (irq <= 0) {
1937                 dev_err(&ndev->dev, "no irq\n");
1938                 ret = -ENOENT;
1939                 goto err_free;
1940         }
1941
1942         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
1943         if (!res) {
1944                 dev_err(&ndev->dev, "no mem resource\n");
1945                 ret = -ENOENT;
1946                 goto err_free;
1947         }
1948
1949         base_res = request_mem_region(res->start, resource_size(res),
1950                 ndev->name);
1951         if (!base_res) {
1952                 dev_err(&ndev->dev, "request_mem_region failed\n");
1953                 ret = -EBUSY;
1954                 goto err_free;
1955         }
1956
1957         base = ioremap(res->start, resource_size(res));
1958         if (!base) {
1959                 dev_err(&ndev->dev, "registers can't be mapped\n");
1960                 ret = -EBUSY;
1961                 goto err_release_resource_reg;
1962         }
1963
1964         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
1965
1966         clk = clk_get(&ndev->dev, NULL);
1967         if (IS_ERR_OR_NULL(clk)) {
1968                 dev_err(&ndev->dev, "can't get clock\n");
1969                 ret = -ENOENT;
1970                 goto err_iounmap_reg;
1971         }
1972
1973         emc_clk = clk_get(&ndev->dev, "emc");
1974         if (IS_ERR_OR_NULL(emc_clk)) {
1975                 dev_err(&ndev->dev, "can't get emc clock\n");
1976                 ret = -ENOENT;
1977                 goto err_put_clk;
1978         }
1979
1980         dc->clk = clk;
1981         dc->emc_clk = emc_clk;
1982         dc->shift_clk_div = 1;
1983         /* Initialize one shot work delay, it will be assigned by dsi
1984          * according to refresh rate later. */
1985         dc->one_shot_delay_ms = 40;
1986
1987         dc->base_res = base_res;
1988         dc->base = base;
1989         dc->irq = irq;
1990         dc->ndev = ndev;
1991         dc->pdata = ndev->dev.platform_data;
1992
1993         /*
1994          * The emc is a shared clock, it will be set based on
1995          * the requirements for each user on the bus.
1996          */
1997         dc->emc_clk_rate = 0;
1998
1999         mutex_init(&dc->lock);
2000         mutex_init(&dc->one_shot_lock);
2001         init_completion(&dc->frame_end_complete);
2002         init_waitqueue_head(&dc->wq);
2003 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2004         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2005 #endif
2006         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2007         dc->vblank_ref_count = 0;
2008         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2009         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2010
2011         tegra_dc_init_lut_defaults(&dc->fb_lut);
2012
2013         dc->n_windows = DC_N_WINDOWS;
2014         for (i = 0; i < dc->n_windows; i++) {
2015                 struct tegra_dc_win *win = &dc->windows[i];
2016                 win->idx = i;
2017                 win->dc = dc;
2018                 tegra_dc_init_csc_defaults(&win->csc);
2019                 tegra_dc_init_lut_defaults(&win->lut);
2020         }
2021
2022         ret = tegra_dc_set(dc, ndev->id);
2023         if (ret < 0) {
2024                 dev_err(&ndev->dev, "can't add dc\n");
2025                 goto err_free_irq;
2026         }
2027
2028         nvhost_set_drvdata(ndev, dc);
2029
2030 #ifdef CONFIG_SWITCH
2031         dc->modeset_switch.name = dev_name(&ndev->dev);
2032         dc->modeset_switch.state = 0;
2033         dc->modeset_switch.print_state = switch_modeset_print_mode;
2034         switch_dev_register(&dc->modeset_switch);
2035 #endif
2036
2037         tegra_dc_feature_register(dc);
2038
2039         if (dc->pdata->default_out)
2040                 tegra_dc_set_out(dc, dc->pdata->default_out);
2041         else
2042                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2043
2044         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2045                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2046
2047         dc->ext = tegra_dc_ext_register(ndev, dc);
2048         if (IS_ERR_OR_NULL(dc->ext)) {
2049                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2050                 dc->ext = NULL;
2051         }
2052
2053         mutex_lock(&dc->lock);
2054         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED)
2055                 dc->enabled = _tegra_dc_enable(dc);
2056         mutex_unlock(&dc->lock);
2057
2058         /* interrupt handler must be registered before tegra_fb_register() */
2059         if (request_irq(irq, tegra_dc_irq, 0,
2060                         dev_name(&ndev->dev), dc)) {
2061                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2062                 ret = -EBUSY;
2063                 goto err_put_emc_clk;
2064         }
2065
2066         tegra_dc_create_debugfs(dc);
2067
2068         dev_info(&ndev->dev, "probed\n");
2069
2070         if (dc->pdata->fb) {
2071                 if (dc->pdata->fb->bits_per_pixel == -1) {
2072                         unsigned long fmt;
2073                         tegra_dc_writel(dc,
2074                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2075                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2076
2077                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2078                         dc->pdata->fb->bits_per_pixel =
2079                                 tegra_dc_fmt_bpp(fmt);
2080                 }
2081
2082                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2083                 if (IS_ERR_OR_NULL(dc->fb))
2084                         dc->fb = NULL;
2085         }
2086
2087         if (dc->out && dc->out->hotplug_init)
2088                 dc->out->hotplug_init();
2089
2090         if (dc->out_ops && dc->out_ops->detect)
2091                 dc->out_ops->detect(dc);
2092         else
2093                 dc->connected = true;
2094
2095         tegra_dc_create_sysfs(&dc->ndev->dev);
2096
2097         return 0;
2098
2099 err_free_irq:
2100         free_irq(irq, dc);
2101 err_put_emc_clk:
2102         clk_put(emc_clk);
2103 err_put_clk:
2104         clk_put(clk);
2105 err_iounmap_reg:
2106         iounmap(base);
2107         if (fb_mem)
2108                 release_resource(fb_mem);
2109 err_release_resource_reg:
2110         release_resource(base_res);
2111 err_free:
2112         kfree(dc);
2113
2114         return ret;
2115 }
2116
2117 static int tegra_dc_remove(struct nvhost_device *ndev)
2118 {
2119         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2120
2121         tegra_dc_remove_sysfs(&dc->ndev->dev);
2122         tegra_dc_remove_debugfs(dc);
2123
2124         if (dc->fb) {
2125                 tegra_fb_unregister(dc->fb);
2126                 if (dc->fb_mem)
2127                         release_resource(dc->fb_mem);
2128         }
2129
2130         tegra_dc_ext_disable(dc->ext);
2131
2132         if (dc->ext)
2133                 tegra_dc_ext_unregister(dc->ext);
2134
2135         if (dc->enabled)
2136                 _tegra_dc_disable(dc);
2137
2138 #ifdef CONFIG_SWITCH
2139         switch_dev_unregister(&dc->modeset_switch);
2140 #endif
2141         free_irq(dc->irq, dc);
2142         clk_put(dc->emc_clk);
2143         clk_put(dc->clk);
2144         iounmap(dc->base);
2145         if (dc->fb_mem)
2146                 release_resource(dc->base_res);
2147         kfree(dc);
2148         tegra_dc_set(NULL, ndev->id);
2149         return 0;
2150 }
2151
2152 #ifdef CONFIG_PM
2153 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2154 {
2155         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2156
2157         trace_printk("%s:suspend\n", dc->ndev->name);
2158         dev_info(&ndev->dev, "suspend\n");
2159
2160         tegra_dc_ext_disable(dc->ext);
2161
2162         mutex_lock(&dc->lock);
2163
2164         if (dc->out_ops && dc->out_ops->suspend)
2165                 dc->out_ops->suspend(dc);
2166
2167         if (dc->enabled) {
2168                 _tegra_dc_disable(dc);
2169
2170                 dc->suspended = true;
2171         }
2172
2173         if (dc->out && dc->out->postsuspend) {
2174                 dc->out->postsuspend();
2175                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2176                         /*
2177                          * avoid resume event due to voltage falling
2178                          */
2179                         msleep(100);
2180         }
2181
2182         mutex_unlock(&dc->lock);
2183
2184         return 0;
2185 }
2186
2187 static int tegra_dc_resume(struct nvhost_device *ndev)
2188 {
2189         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2190
2191         trace_printk("%s:resume\n", dc->ndev->name);
2192         dev_info(&ndev->dev, "resume\n");
2193
2194         mutex_lock(&dc->lock);
2195         dc->suspended = false;
2196
2197         if (dc->enabled)
2198                 _tegra_dc_enable(dc);
2199
2200         if (dc->out && dc->out->hotplug_init)
2201                 dc->out->hotplug_init();
2202
2203         if (dc->out_ops && dc->out_ops->resume)
2204                 dc->out_ops->resume(dc);
2205         mutex_unlock(&dc->lock);
2206
2207         return 0;
2208 }
2209
2210 #endif /* CONFIG_PM */
2211
2212 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2213 {
2214         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2215
2216         if (!dc || !dc->enabled)
2217                 return;
2218
2219         tegra_dc_blank(dc);
2220         tegra_dc_disable(dc);
2221 }
2222
2223 extern int suspend_set(const char *val, struct kernel_param *kp)
2224 {
2225         if (!strcmp(val, "dump"))
2226                 dump_regs(tegra_dcs[0]);
2227 #ifdef CONFIG_PM
2228         else if (!strcmp(val, "suspend"))
2229                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2230         else if (!strcmp(val, "resume"))
2231                 tegra_dc_resume(tegra_dcs[0]->ndev);
2232 #endif
2233
2234         return 0;
2235 }
2236
2237 extern int suspend_get(char *buffer, struct kernel_param *kp)
2238 {
2239         return 0;
2240 }
2241
2242 int suspend;
2243
2244 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2245
2246 struct nvhost_driver tegra_dc_driver = {
2247         .driver = {
2248                 .name = "tegradc",
2249                 .owner = THIS_MODULE,
2250         },
2251         .probe = tegra_dc_probe,
2252         .remove = tegra_dc_remove,
2253 #ifdef CONFIG_PM
2254         .suspend = tegra_dc_suspend,
2255         .resume = tegra_dc_resume,
2256 #endif
2257         .shutdown = tegra_dc_shutdown,
2258 };
2259
2260 static int __init tegra_dc_module_init(void)
2261 {
2262         int ret = tegra_dc_ext_module_init();
2263         if (ret)
2264                 return ret;
2265         return nvhost_driver_register(&tegra_dc_driver);
2266 }
2267
2268 static void __exit tegra_dc_module_exit(void)
2269 {
2270         nvhost_driver_unregister(&tegra_dc_driver);
2271         tegra_dc_ext_module_exit();
2272 }
2273
2274 module_exit(tegra_dc_module_exit);
2275 module_init(tegra_dc_module_init);