video: tegra: dc: add support to window d & h.
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <video/tegrafb.h>
41 #include <drm/drm_fixed.h>
42 #ifdef CONFIG_SWITCH
43 #include <linux/switch.h>
44 #endif
45
46 #define CREATE_TRACE_POINTS
47 #include <trace/events/display.h>
48
49 #include <mach/clk.h>
50 #include <mach/dc.h>
51 #include <mach/fb.h>
52 #include <mach/mc.h>
53 #include <linux/nvhost.h>
54 #include <mach/latency_allowance.h>
55 #include <mach/iomap.h>
56
57 #include "dc_reg.h"
58 #include "dc_config.h"
59 #include "dc_priv.h"
60 #include "dev.h"
61 #include "nvsd.h"
62
63 #define TEGRA_CRC_LATCHED_DELAY         34
64
65 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
66 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
67
68 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
69         .refresh = 60,
70         .xres = 640,
71         .yres = 480,
72         .pixclock = KHZ2PICOS(25200),
73         .hsync_len = 96,        /* h_sync_width */
74         .vsync_len = 2,         /* v_sync_width */
75         .left_margin = 48,      /* h_back_porch */
76         .upper_margin = 33,     /* v_back_porch */
77         .right_margin = 16,     /* h_front_porch */
78         .lower_margin = 10,     /* v_front_porch */
79         .vmode = 0,
80         .sync = 0,
81 };
82
83 static struct tegra_dc_mode override_disp_mode[3];
84
85 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
86
87 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
88
89 DEFINE_MUTEX(tegra_dc_lock);
90 DEFINE_MUTEX(shared_lock);
91
92 static const struct {
93         bool h;
94         bool v;
95 } can_filter[] = {
96         /* Window A has no filtering */
97         { false, false },
98         /* Window B has both H and V filtering */
99         { true,  true  },
100         /* Window C has only H filtering */
101         { false, true  },
102 };
103
104 #ifdef CONFIG_TEGRA_DC_CMU
105 static struct tegra_dc_cmu default_cmu = {
106         /* lut1 maps sRGB to linear space. */
107         {
108                 0,    1,    2,    4,    5,    6,    7,    9,
109                 10,   11,   12,   14,   15,   16,   18,   20,
110                 21,   23,   25,   27,   29,   31,   33,   35,
111                 37,   40,   42,   45,   48,   50,   53,   56,
112                 59,   62,   66,   69,   72,   76,   79,   83,
113                 87,   91,   95,   99,   103,  107,  112,  116,
114                 121,  126,  131,  136,  141,  146,  151,  156,
115                 162,  168,  173,  179,  185,  191,  197,  204,
116                 210,  216,  223,  230,  237,  244,  251,  258,
117                 265,  273,  280,  288,  296,  304,  312,  320,
118                 329,  337,  346,  354,  363,  372,  381,  390,
119                 400,  409,  419,  428,  438,  448,  458,  469,
120                 479,  490,  500,  511,  522,  533,  544,  555,
121                 567,  578,  590,  602,  614,  626,  639,  651,
122                 664,  676,  689,  702,  715,  728,  742,  755,
123                 769,  783,  797,  811,  825,  840,  854,  869,
124                 884,  899,  914,  929,  945,  960,  976,  992,
125                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
126                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
127                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
128                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
129                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
130                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
131                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
132                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
133                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
134                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
135                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
136                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
137                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
138                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
139                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
140         },
141         /* csc */
142         {
143                 0x100, 0x0,   0x0,
144                 0x0,   0x100, 0x0,
145                 0x0,   0x0,   0x100,
146         },
147         /* lut2 maps linear space to sRGB*/
148         {
149                 0,    1,    2,    2,    3,    4,    5,    6,
150                 6,    7,    8,    9,    10,   10,   11,   12,
151                 13,   13,   14,   15,   15,   16,   16,   17,
152                 18,   18,   19,   19,   20,   20,   21,   21,
153                 22,   22,   23,   23,   23,   24,   24,   25,
154                 25,   25,   26,   26,   27,   27,   27,   28,
155                 28,   29,   29,   29,   30,   30,   30,   31,
156                 31,   31,   32,   32,   32,   33,   33,   33,
157                 34,   34,   34,   34,   35,   35,   35,   36,
158                 36,   36,   37,   37,   37,   37,   38,   38,
159                 38,   38,   39,   39,   39,   40,   40,   40,
160                 40,   41,   41,   41,   41,   42,   42,   42,
161                 42,   43,   43,   43,   43,   43,   44,   44,
162                 44,   44,   45,   45,   45,   45,   46,   46,
163                 46,   46,   46,   47,   47,   47,   47,   48,
164                 48,   48,   48,   48,   49,   49,   49,   49,
165                 49,   50,   50,   50,   50,   50,   51,   51,
166                 51,   51,   51,   52,   52,   52,   52,   52,
167                 53,   53,   53,   53,   53,   54,   54,   54,
168                 54,   54,   55,   55,   55,   55,   55,   55,
169                 56,   56,   56,   56,   56,   57,   57,   57,
170                 57,   57,   57,   58,   58,   58,   58,   58,
171                 58,   59,   59,   59,   59,   59,   59,   60,
172                 60,   60,   60,   60,   60,   61,   61,   61,
173                 61,   61,   61,   62,   62,   62,   62,   62,
174                 62,   63,   63,   63,   63,   63,   63,   64,
175                 64,   64,   64,   64,   64,   64,   65,   65,
176                 65,   65,   65,   65,   66,   66,   66,   66,
177                 66,   66,   66,   67,   67,   67,   67,   67,
178                 67,   67,   68,   68,   68,   68,   68,   68,
179                 68,   69,   69,   69,   69,   69,   69,   69,
180                 70,   70,   70,   70,   70,   70,   70,   71,
181                 71,   71,   71,   71,   71,   71,   72,   72,
182                 72,   72,   72,   72,   72,   72,   73,   73,
183                 73,   73,   73,   73,   73,   74,   74,   74,
184                 74,   74,   74,   74,   74,   75,   75,   75,
185                 75,   75,   75,   75,   75,   76,   76,   76,
186                 76,   76,   76,   76,   77,   77,   77,   77,
187                 77,   77,   77,   77,   78,   78,   78,   78,
188                 78,   78,   78,   78,   78,   79,   79,   79,
189                 79,   79,   79,   79,   79,   80,   80,   80,
190                 80,   80,   80,   80,   80,   81,   81,   81,
191                 81,   81,   81,   81,   81,   81,   82,   82,
192                 82,   82,   82,   82,   82,   82,   83,   83,
193                 83,   83,   83,   83,   83,   83,   83,   84,
194                 84,   84,   84,   84,   84,   84,   84,   84,
195                 85,   85,   85,   85,   85,   85,   85,   85,
196                 85,   86,   86,   86,   86,   86,   86,   86,
197                 86,   86,   87,   87,   87,   87,   87,   87,
198                 87,   87,   87,   88,   88,   88,   88,   88,
199                 88,   88,   88,   88,   88,   89,   89,   89,
200                 89,   89,   89,   89,   89,   89,   90,   90,
201                 90,   90,   90,   90,   90,   90,   90,   90,
202                 91,   91,   91,   91,   91,   91,   91,   91,
203                 91,   91,   92,   92,   92,   92,   92,   92,
204                 92,   92,   92,   92,   93,   93,   93,   93,
205                 93,   93,   93,   93,   93,   93,   94,   94,
206                 94,   94,   94,   94,   94,   94,   94,   94,
207                 95,   95,   95,   95,   95,   95,   95,   95,
208                 95,   95,   96,   96,   96,   96,   96,   96,
209                 96,   96,   96,   96,   96,   97,   97,   97,
210                 97,   97,   97,   97,   97,   97,   97,   98,
211                 98,   98,   98,   98,   98,   98,   98,   98,
212                 98,   98,   99,   99,   99,   99,   99,   99,
213                 99,   100,  101,  101,  102,  103,  103,  104,
214                 105,  105,  106,  107,  107,  108,  109,  109,
215                 110,  111,  111,  112,  113,  113,  114,  115,
216                 115,  116,  116,  117,  118,  118,  119,  119,
217                 120,  120,  121,  122,  122,  123,  123,  124,
218                 124,  125,  126,  126,  127,  127,  128,  128,
219                 129,  129,  130,  130,  131,  131,  132,  132,
220                 133,  133,  134,  134,  135,  135,  136,  136,
221                 137,  137,  138,  138,  139,  139,  140,  140,
222                 141,  141,  142,  142,  143,  143,  144,  144,
223                 145,  145,  145,  146,  146,  147,  147,  148,
224                 148,  149,  149,  150,  150,  150,  151,  151,
225                 152,  152,  153,  153,  153,  154,  154,  155,
226                 155,  156,  156,  156,  157,  157,  158,  158,
227                 158,  159,  159,  160,  160,  160,  161,  161,
228                 162,  162,  162,  163,  163,  164,  164,  164,
229                 165,  165,  166,  166,  166,  167,  167,  167,
230                 168,  168,  169,  169,  169,  170,  170,  170,
231                 171,  171,  172,  172,  172,  173,  173,  173,
232                 174,  174,  174,  175,  175,  176,  176,  176,
233                 177,  177,  177,  178,  178,  178,  179,  179,
234                 179,  180,  180,  180,  181,  181,  182,  182,
235                 182,  183,  183,  183,  184,  184,  184,  185,
236                 185,  185,  186,  186,  186,  187,  187,  187,
237                 188,  188,  188,  189,  189,  189,  189,  190,
238                 190,  190,  191,  191,  191,  192,  192,  192,
239                 193,  193,  193,  194,  194,  194,  195,  195,
240                 195,  196,  196,  196,  196,  197,  197,  197,
241                 198,  198,  198,  199,  199,  199,  200,  200,
242                 200,  200,  201,  201,  201,  202,  202,  202,
243                 202,  203,  203,  203,  204,  204,  204,  205,
244                 205,  205,  205,  206,  206,  206,  207,  207,
245                 207,  207,  208,  208,  208,  209,  209,  209,
246                 209,  210,  210,  210,  211,  211,  211,  211,
247                 212,  212,  212,  213,  213,  213,  213,  214,
248                 214,  214,  214,  215,  215,  215,  216,  216,
249                 216,  216,  217,  217,  217,  217,  218,  218,
250                 218,  219,  219,  219,  219,  220,  220,  220,
251                 220,  221,  221,  221,  221,  222,  222,  222,
252                 223,  223,  223,  223,  224,  224,  224,  224,
253                 225,  225,  225,  225,  226,  226,  226,  226,
254                 227,  227,  227,  227,  228,  228,  228,  228,
255                 229,  229,  229,  229,  230,  230,  230,  230,
256                 231,  231,  231,  231,  232,  232,  232,  232,
257                 233,  233,  233,  233,  234,  234,  234,  234,
258                 235,  235,  235,  235,  236,  236,  236,  236,
259                 237,  237,  237,  237,  238,  238,  238,  238,
260                 239,  239,  239,  239,  240,  240,  240,  240,
261                 240,  241,  241,  241,  241,  242,  242,  242,
262                 242,  243,  243,  243,  243,  244,  244,  244,
263                 244,  244,  245,  245,  245,  245,  246,  246,
264                 246,  246,  247,  247,  247,  247,  247,  248,
265                 248,  248,  248,  249,  249,  249,  249,  249,
266                 250,  250,  250,  250,  251,  251,  251,  251,
267                 251,  252,  252,  252,  252,  253,  253,  253,
268                 253,  253,  254,  254,  254,  254,  255,  255,
269         },
270 };
271 #endif
272
273 void tegra_dc_clk_enable(struct tegra_dc *dc)
274 {
275         if (!tegra_is_clk_enabled(dc->clk)) {
276                 clk_prepare_enable(dc->clk);
277                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
278         }
279 }
280
281 void tegra_dc_clk_disable(struct tegra_dc *dc)
282 {
283         if (tegra_is_clk_enabled(dc->clk)) {
284                 clk_disable_unprepare(dc->clk);
285                 tegra_dvfs_set_rate(dc->clk, 0);
286         }
287 }
288
289 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
290 {
291         /* extra reference to dc clk */
292         clk_prepare_enable(dc->clk);
293
294         if (dc->out_ops->hold)
295                 dc->out_ops->hold(dc);
296 }
297
298 void tegra_dc_release_dc_out(struct tegra_dc *dc)
299 {
300         if (dc->out_ops->release)
301                 dc->out_ops->release(dc);
302
303         /* balance extra dc clk reference */
304         clk_disable_unprepare(dc->clk);
305 }
306
307 #define DUMP_REG(a) do {                        \
308         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
309                  #a, a, tegra_dc_readl(dc, a));               \
310         print(data, buff);                                    \
311         } while (0)
312
313 static void _dump_regs(struct tegra_dc *dc, void *data,
314                        void (* print)(void *data, const char *str))
315 {
316         int i;
317         char buff[256];
318
319         mutex_lock(&dc->lock);
320         tegra_dc_io_start(dc);
321         tegra_dc_hold_dc_out(dc);
322
323         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
324         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
325         DUMP_REG(DC_CMD_SIGNAL_RAISE);
326         DUMP_REG(DC_CMD_INT_STATUS);
327         DUMP_REG(DC_CMD_INT_MASK);
328         DUMP_REG(DC_CMD_INT_ENABLE);
329         DUMP_REG(DC_CMD_INT_TYPE);
330         DUMP_REG(DC_CMD_INT_POLARITY);
331         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
332         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
333         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
334         DUMP_REG(DC_CMD_STATE_ACCESS);
335         DUMP_REG(DC_CMD_STATE_CONTROL);
336         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
337         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
338
339         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
340         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
341         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
342         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
343         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
344         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
345         DUMP_REG(DC_DISP_REF_TO_SYNC);
346         DUMP_REG(DC_DISP_SYNC_WIDTH);
347         DUMP_REG(DC_DISP_BACK_PORCH);
348         DUMP_REG(DC_DISP_DISP_ACTIVE);
349         DUMP_REG(DC_DISP_FRONT_PORCH);
350         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
351         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
352         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
353         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
354         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
355         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
356         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
357         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
358         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
359         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
360         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
361         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
362         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
363         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
364         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
365         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
366         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
367         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
368         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
369         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
370         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
371         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
372         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
373         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
374         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
375         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
376         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
377         DUMP_REG(DC_DISP_M0_CONTROL);
378         DUMP_REG(DC_DISP_M1_CONTROL);
379         DUMP_REG(DC_DISP_DI_CONTROL);
380         DUMP_REG(DC_DISP_PP_CONTROL);
381         DUMP_REG(DC_DISP_PP_SELECT_A);
382         DUMP_REG(DC_DISP_PP_SELECT_B);
383         DUMP_REG(DC_DISP_PP_SELECT_C);
384         DUMP_REG(DC_DISP_PP_SELECT_D);
385         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
386         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
387         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
388         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
389         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
390         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
391         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
392         DUMP_REG(DC_DISP_BORDER_COLOR);
393         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
394         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
395         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
396         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
397         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
398         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
399         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
400         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
401         DUMP_REG(DC_DISP_CURSOR_POSITION);
402         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
403         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
404         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
405         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
406         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
407         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
408         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
409         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
410         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
411         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
412 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
413         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
414 #endif
415         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
416         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
417
418
419         for (i = 0; i < 3; i++) {
420                 print(data, "\n");
421                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
422                 print(data, buff);
423
424                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
425                                 DC_CMD_DISPLAY_WINDOW_HEADER);
426                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
427                 DUMP_REG(DC_WIN_WIN_OPTIONS);
428                 DUMP_REG(DC_WIN_BYTE_SWAP);
429                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
430                 DUMP_REG(DC_WIN_COLOR_DEPTH);
431                 DUMP_REG(DC_WIN_POSITION);
432                 DUMP_REG(DC_WIN_SIZE);
433                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
434                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
435                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
436                 DUMP_REG(DC_WIN_DDA_INCREMENT);
437                 DUMP_REG(DC_WIN_LINE_STRIDE);
438 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
439                 DUMP_REG(DC_WIN_BUF_STRIDE);
440                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
441 #endif
442                 DUMP_REG(DC_WIN_BLEND_NOKEY);
443                 DUMP_REG(DC_WIN_BLEND_1WIN);
444                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
445                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
446                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
447                 DUMP_REG(DC_WINBUF_START_ADDR);
448                 DUMP_REG(DC_WINBUF_START_ADDR_U);
449                 DUMP_REG(DC_WINBUF_START_ADDR_V);
450                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
451                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
452                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
453                 DUMP_REG(DC_WIN_CSC_YOF);
454                 DUMP_REG(DC_WIN_CSC_KYRGB);
455                 DUMP_REG(DC_WIN_CSC_KUR);
456                 DUMP_REG(DC_WIN_CSC_KVR);
457                 DUMP_REG(DC_WIN_CSC_KUG);
458                 DUMP_REG(DC_WIN_CSC_KVG);
459                 DUMP_REG(DC_WIN_CSC_KUB);
460                 DUMP_REG(DC_WIN_CSC_KVB);
461         }
462
463         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
464         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
465         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
466         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
467         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
468         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
469         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
470         DUMP_REG(DC_DISP_M1_CONTROL);
471         DUMP_REG(DC_COM_PM1_CONTROL);
472         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
473         DUMP_REG(DC_DISP_SD_CONTROL);
474 #ifdef CONFIG_TEGRA_DC_CMU
475         DUMP_REG(DC_COM_CMU_CSC_KRR);
476         DUMP_REG(DC_COM_CMU_CSC_KGR);
477         DUMP_REG(DC_COM_CMU_CSC_KBR);
478         DUMP_REG(DC_COM_CMU_CSC_KRG);
479         DUMP_REG(DC_COM_CMU_CSC_KGG);
480         DUMP_REG(DC_COM_CMU_CSC_KBR);
481         DUMP_REG(DC_COM_CMU_CSC_KRB);
482         DUMP_REG(DC_COM_CMU_CSC_KGB);
483         DUMP_REG(DC_COM_CMU_CSC_KBB);
484 #endif
485
486         tegra_dc_release_dc_out(dc);
487         tegra_dc_io_end(dc);
488         mutex_unlock(&dc->lock);
489 }
490
491 #undef DUMP_REG
492
493 #ifdef DEBUG
494 static void dump_regs_print(void *data, const char *str)
495 {
496         struct tegra_dc *dc = data;
497         dev_dbg(&dc->ndev->dev, "%s", str);
498 }
499
500 static void dump_regs(struct tegra_dc *dc)
501 {
502         _dump_regs(dc, dc, dump_regs_print);
503 }
504 #else /* !DEBUG */
505
506 static void dump_regs(struct tegra_dc *dc) {}
507
508 #endif /* DEBUG */
509
510 #ifdef CONFIG_DEBUG_FS
511
512 static void dbg_regs_print(void *data, const char *str)
513 {
514         struct seq_file *s = data;
515
516         seq_printf(s, "%s", str);
517 }
518
519 #undef DUMP_REG
520
521 static int dbg_dc_show(struct seq_file *s, void *unused)
522 {
523         struct tegra_dc *dc = s->private;
524
525         _dump_regs(dc, s, dbg_regs_print);
526
527         return 0;
528 }
529
530
531 static int dbg_dc_open(struct inode *inode, struct file *file)
532 {
533         return single_open(file, dbg_dc_show, inode->i_private);
534 }
535
536 static const struct file_operations regs_fops = {
537         .open           = dbg_dc_open,
538         .read           = seq_read,
539         .llseek         = seq_lseek,
540         .release        = single_release,
541 };
542
543 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
544 {
545         struct tegra_dc *dc = s->private;
546         struct tegra_dc_mode *m;
547
548         mutex_lock(&dc->lock);
549         m = &dc->mode;
550         seq_printf(s,
551                 "pclk: %d\n"
552                 "h_ref_to_sync: %d\n"
553                 "v_ref_to_sync: %d\n"
554                 "h_sync_width: %d\n"
555                 "v_sync_width: %d\n"
556                 "h_back_porch: %d\n"
557                 "v_back_porch: %d\n"
558                 "h_active: %d\n"
559                 "v_active: %d\n"
560                 "h_front_porch: %d\n"
561                 "v_front_porch: %d\n"
562                 "stereo_mode: %d\n",
563                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
564                 m->h_sync_width, m->v_sync_width,
565                 m->h_back_porch, m->v_back_porch,
566                 m->h_active, m->v_active,
567                 m->h_front_porch, m->v_front_porch,
568                 m->stereo_mode);
569         mutex_unlock(&dc->lock);
570         return 0;
571 }
572
573 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
574 {
575         return single_open(file, dbg_dc_mode_show, inode->i_private);
576 }
577
578 static const struct file_operations mode_fops = {
579         .open           = dbg_dc_mode_open,
580         .read           = seq_read,
581         .llseek         = seq_lseek,
582         .release        = single_release,
583 };
584
585 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
586 {
587         struct tegra_dc *dc = s->private;
588
589         mutex_lock(&dc->lock);
590         seq_printf(s,
591                 "underflows: %llu\n"
592                 "underflows_a: %llu\n"
593                 "underflows_b: %llu\n"
594                 "underflows_c: %llu\n",
595                 dc->stats.underflows,
596                 dc->stats.underflows_a,
597                 dc->stats.underflows_b,
598                 dc->stats.underflows_c);
599         mutex_unlock(&dc->lock);
600
601         return 0;
602 }
603
604 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
605 {
606         return single_open(file, dbg_dc_stats_show, inode->i_private);
607 }
608
609 static const struct file_operations stats_fops = {
610         .open           = dbg_dc_stats_open,
611         .read           = seq_read,
612         .llseek         = seq_lseek,
613         .release        = single_release,
614 };
615
616 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
617 {
618         if (dc->debugdir)
619                 debugfs_remove_recursive(dc->debugdir);
620         dc->debugdir = NULL;
621 }
622
623 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
624 {
625         struct dentry *retval;
626
627         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
628         if (!dc->debugdir)
629                 goto remove_out;
630
631         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
632                 &regs_fops);
633         if (!retval)
634                 goto remove_out;
635
636         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
637                 &mode_fops);
638         if (!retval)
639                 goto remove_out;
640
641         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
642                 &stats_fops);
643         if (!retval)
644                 goto remove_out;
645
646         return;
647 remove_out:
648         dev_err(&dc->ndev->dev, "could not create debugfs\n");
649         tegra_dc_remove_debugfs(dc);
650 }
651
652 #else /* !CONFIG_DEBUGFS */
653 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
654 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
655 #endif /* CONFIG_DEBUGFS */
656
657 static int tegra_dc_set(struct tegra_dc *dc, int index)
658 {
659         int ret = 0;
660
661         mutex_lock(&tegra_dc_lock);
662         if (index >= TEGRA_MAX_DC) {
663                 ret = -EINVAL;
664                 goto out;
665         }
666
667         if (dc != NULL && tegra_dcs[index] != NULL) {
668                 ret = -EBUSY;
669                 goto out;
670         }
671
672         tegra_dcs[index] = dc;
673
674 out:
675         mutex_unlock(&tegra_dc_lock);
676
677         return ret;
678 }
679
680 unsigned int tegra_dc_has_multiple_dc(void)
681 {
682         unsigned int idx;
683         unsigned int cnt = 0;
684         struct tegra_dc *dc;
685
686         mutex_lock(&tegra_dc_lock);
687         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
688                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
689         mutex_unlock(&tegra_dc_lock);
690
691         return (cnt > 1);
692 }
693
694 /* get the stride size of a window.
695  * return: stride size in bytes for window win. or 0 if unavailble. */
696 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
697 {
698         u32 stride;
699
700         if (!dc->enabled)
701                 return 0;
702         BUG_ON(win > DC_N_WINDOWS);
703         mutex_lock(&dc->lock);
704         tegra_dc_io_start(dc);
705         tegra_dc_hold_dc_out(dc);
706         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
707                 DC_CMD_DISPLAY_WINDOW_HEADER);
708         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
709         tegra_dc_release_dc_out(dc);
710         tegra_dc_io_end(dc);
711         mutex_unlock(&dc->lock);
712         return GET_LINE_STRIDE(stride);
713 }
714 EXPORT_SYMBOL(tegra_dc_get_stride);
715
716 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
717 {
718         if (idx < TEGRA_MAX_DC)
719                 return tegra_dcs[idx];
720         else
721                 return NULL;
722 }
723 EXPORT_SYMBOL(tegra_dc_get_dc);
724
725 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
726 {
727         if (win >= dc->n_windows)
728                 return NULL;
729
730         return &dc->windows[win];
731 }
732 EXPORT_SYMBOL(tegra_dc_get_window);
733
734 bool tegra_dc_get_connected(struct tegra_dc *dc)
735 {
736         return dc->connected;
737 }
738 EXPORT_SYMBOL(tegra_dc_get_connected);
739
740 bool tegra_dc_hpd(struct tegra_dc *dc)
741 {
742         int sense;
743         int level;
744
745         level = gpio_get_value(dc->out->hotplug_gpio);
746
747         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
748
749         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
750                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
751 }
752 EXPORT_SYMBOL(tegra_dc_hpd);
753
754 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
755 {
756         unsigned i;
757         unsigned v0 = 128;
758         unsigned v1 = 0;
759
760         /* linear horizontal and vertical filters */
761         for (i = 0; i < 16; i++) {
762                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
763                                 DC_WIN_H_FILTER_P(i));
764
765                 tegra_dc_writel(dc, v0,
766                                 DC_WIN_V_FILTER_P(i));
767                 v0 -= 8;
768                 v1 += 8;
769         }
770 }
771
772 #ifdef CONFIG_TEGRA_DC_CMU
773 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
774                                         struct tegra_dc_cmu *src_cmu)
775 {
776         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
777 }
778
779 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
780 {
781         u32 val;
782         u32 i;
783
784         for (i = 0; i < 256; i++) {
785                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
786                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
787         }
788
789         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
790         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
791         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
792         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
793         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
794         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
795         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
796         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
797         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
798
799         for (i = 0; i < 960; i++) {
800                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
801                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
802         }
803 }
804
805 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
806 {
807         u32 val;
808         u32 i;
809         bool flags;
810
811         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
812         if (val & CMU_ENABLE)
813                 flags = true;
814
815         val &= ~CMU_ENABLE;
816         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
817         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
818         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
819
820         /*TODO: Sync up with frame end */
821         mdelay(20);
822
823         for (i = 0; i < 256; i++) {
824                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
825                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
826                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
827                 cmu->lut1[i] = LUT1_READ_DATA(val);
828         }
829
830         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
831         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
832         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
833         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
834         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
835         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
836         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
837         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
838         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
839
840         for (i = 0; i < 960; i++) {
841                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
842                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
843                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
844                 cmu->lut2[i] = LUT2_READ_DATA(val);
845         }
846 }
847 EXPORT_SYMBOL(tegra_dc_get_cmu);
848
849 int _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
850 {
851         u32 val;
852
853         if (dc->pdata->cmu_enable) {
854                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
855         } else {
856                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
857                 return 0;
858         }
859
860 #ifdef CONFIG_TEGRA_DC_CMU
861         if (cmu != &dc->cmu) {
862                 tegra_dc_cache_cmu(&dc->cmu, cmu);
863
864                 /* Disable CMU */
865                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
866                 if (val & CMU_ENABLE) {
867                         val &= ~CMU_ENABLE;
868                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
869                         val = GENERAL_UPDATE;
870                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
871                         val = GENERAL_ACT_REQ;
872                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
873                         /*TODO: Sync up with vsync */
874                         mdelay(20);
875                 }
876
877                 tegra_dc_set_cmu(dc, &dc->cmu);
878         }
879 #endif
880
881         return 0;
882 }
883
884 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
885 {
886         int ret;
887
888         mutex_lock(&dc->lock);
889         if (!dc->enabled) {
890                 mutex_unlock(&dc->lock);
891                 return 0;
892         }
893         tegra_dc_io_start(dc);
894         tegra_dc_hold_dc_out(dc);
895
896         ret = _tegra_dc_update_cmu(dc, cmu);
897         tegra_dc_set_color_control(dc);
898
899         tegra_dc_release_dc_out(dc);
900         tegra_dc_io_end(dc);
901         mutex_unlock(&dc->lock);
902
903         return ret;
904 }
905 EXPORT_SYMBOL(tegra_dc_update_cmu);
906
907 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
908 {
909         dc->pdata->cmu_enable = cmu_enable;
910         if (dc->pdata->cmu)
911                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
912         else
913                 tegra_dc_update_cmu(dc, &default_cmu);
914 }
915 #else
916 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
917 #define tegra_dc_set_cmu(dc, cmu)
918 #define tegra_dc_update_cmu(dc, cmu)
919 #endif
920
921 /* disable_irq() blocks until handler completes, calling this function while
922  * holding dc->lock can deadlock. */
923 static inline void disable_dc_irq(const struct tegra_dc *dc)
924 {
925         disable_irq(dc->irq);
926 }
927
928 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
929 {
930         return dc->syncpt[i].id;
931 }
932 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
933
934 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
935 {
936         u32 max;
937
938         mutex_lock(&dc->lock);
939         tegra_dc_io_start(dc);
940         tegra_dc_hold_dc_out(dc);
941         max = nvhost_syncpt_incr_max_ext(dc->ndev,
942                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
943         dc->syncpt[i].max = max;
944         tegra_dc_release_dc_out(dc);
945         tegra_dc_io_end(dc);
946         mutex_unlock(&dc->lock);
947
948         return max;
949 }
950
951 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
952 {
953         mutex_lock(&dc->lock);
954         if (dc->enabled) {
955                 tegra_dc_io_start(dc);
956                 tegra_dc_hold_dc_out(dc);
957                 while (dc->syncpt[i].min < val) {
958                         dc->syncpt[i].min++;
959                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
960                 }
961                 tegra_dc_release_dc_out(dc);
962                 tegra_dc_io_end(dc);
963         }
964         mutex_unlock(&dc->lock);
965 }
966
967 void
968 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
969 {
970         unsigned int ctrl;
971         unsigned long out_sel;
972         unsigned long cmd_state;
973
974         mutex_lock(&dc->lock);
975         if (!dc->enabled) {
976                 mutex_unlock(&dc->lock);
977                 return;
978         }
979
980         tegra_dc_io_start(dc);
981         tegra_dc_hold_dc_out(dc);
982
983         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
984                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
985                 cfg->clk_select);
986
987         /* The new value should be effected immediately */
988         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
989         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
990
991         switch (cfg->which_pwm) {
992         case TEGRA_PWM_PM0:
993                 /* Select the LM0 on PM0 */
994                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
995                 out_sel &= ~(7 << 0);
996                 out_sel |= (3 << 0);
997                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
998                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
999                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1000                 break;
1001         case TEGRA_PWM_PM1:
1002                 /* Select the LM1 on PM1 */
1003                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1004                 out_sel &= ~(7 << 4);
1005                 out_sel |= (3 << 4);
1006                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1007                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1008                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1009                 break;
1010         default:
1011                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1012                 break;
1013         }
1014         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1015         tegra_dc_release_dc_out(dc);
1016         tegra_dc_io_end(dc);
1017         mutex_unlock(&dc->lock);
1018 }
1019 EXPORT_SYMBOL(tegra_dc_config_pwm);
1020
1021 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1022                                 const struct tegra_dc_out_pin *pins,
1023                                 const unsigned int n_pins)
1024 {
1025         unsigned int i;
1026
1027         int name;
1028         int pol;
1029
1030         u32 pol1, pol3;
1031
1032         u32 set1, unset1;
1033         u32 set3, unset3;
1034
1035         set1 = set3 = unset1 = unset3 = 0;
1036
1037         for (i = 0; i < n_pins; i++) {
1038                 name = (pins + i)->name;
1039                 pol  = (pins + i)->pol;
1040
1041                 /* set polarity by name */
1042                 switch (name) {
1043                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1044                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1045                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1046                         else
1047                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1048                         break;
1049                 case TEGRA_DC_OUT_PIN_H_SYNC:
1050                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1051                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1052                         else
1053                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1054                         break;
1055                 case TEGRA_DC_OUT_PIN_V_SYNC:
1056                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1057                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1058                         else
1059                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1060                         break;
1061                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1062                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1063                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1064                         else
1065                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1066                         break;
1067                 default:
1068                         printk("Invalid argument in function %s\n",
1069                                __FUNCTION__);
1070                         break;
1071                 }
1072         }
1073
1074         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1075         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1076
1077         pol1 |= set1;
1078         pol1 &= ~unset1;
1079
1080         pol3 |= set3;
1081         pol3 &= ~unset3;
1082
1083         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1084         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1085 }
1086
1087 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1088 {
1089         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1090                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1091                 dc->out->type == TEGRA_DC_OUT_DSI)
1092                 return override_disp_mode[dc->out->type].pclk ?
1093                         &override_disp_mode[dc->out->type] : NULL;
1094         else
1095                 return NULL;
1096 }
1097
1098 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1099 {
1100         struct tegra_dc_mode *mode;
1101
1102         dc->out = out;
1103         mode = tegra_dc_get_override_mode(dc);
1104
1105         if (mode)
1106                 tegra_dc_set_mode(dc, mode);
1107         else if (out->n_modes > 0)
1108                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1109
1110         switch (out->type) {
1111         case TEGRA_DC_OUT_RGB:
1112                 dc->out_ops = &tegra_dc_rgb_ops;
1113                 break;
1114
1115         case TEGRA_DC_OUT_HDMI:
1116                 dc->out_ops = &tegra_dc_hdmi_ops;
1117                 break;
1118
1119         case TEGRA_DC_OUT_DSI:
1120                 dc->out_ops = &tegra_dc_dsi_ops;
1121                 break;
1122
1123         default:
1124                 dc->out_ops = NULL;
1125                 break;
1126         }
1127
1128         if (dc->out_ops && dc->out_ops->init)
1129                 dc->out_ops->init(dc);
1130 }
1131
1132 /* returns on error: -EINVAL
1133  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1134 int tegra_dc_get_out(const struct tegra_dc *dc)
1135 {
1136         if (dc && dc->out)
1137                 return dc->out->type;
1138         return -EINVAL;
1139 }
1140
1141 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1142 {
1143         if (dc->out)
1144                 return dc->out->height;
1145         else
1146                 return 0;
1147 }
1148 EXPORT_SYMBOL(tegra_dc_get_out_height);
1149
1150 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1151 {
1152         if (dc->out)
1153                 return dc->out->width;
1154         else
1155                 return 0;
1156 }
1157 EXPORT_SYMBOL(tegra_dc_get_out_width);
1158
1159 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1160 {
1161         if (dc->out && dc->out->max_pixclock)
1162                 return dc->out->max_pixclock;
1163         else
1164                 return 0;
1165 }
1166 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1167
1168 void tegra_dc_enable_crc(struct tegra_dc *dc)
1169 {
1170         u32 val;
1171
1172         mutex_lock(&dc->lock);
1173         tegra_dc_io_start(dc);
1174         tegra_dc_hold_dc_out(dc);
1175
1176         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1177                 CRC_ENABLE_ENABLE;
1178         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1179         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1180         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1181         tegra_dc_release_dc_out(dc);
1182         tegra_dc_io_end(dc);
1183         mutex_unlock(&dc->lock);
1184 }
1185
1186 void tegra_dc_disable_crc(struct tegra_dc *dc)
1187 {
1188         mutex_lock(&dc->lock);
1189         tegra_dc_io_start(dc);
1190         tegra_dc_hold_dc_out(dc);
1191         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1192         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1193         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1194
1195         tegra_dc_release_dc_out(dc);
1196         tegra_dc_io_end(dc);
1197         mutex_unlock(&dc->lock);
1198 }
1199
1200 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1201 {
1202         int crc = 0;
1203
1204         if (!dc) {
1205                 pr_err("Failed to get dc: NULL parameter.\n");
1206                 goto crc_error;
1207         }
1208
1209 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1210         /* TODO: Replace mdelay with code to sync VBlANK, since
1211          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1212         mdelay(TEGRA_CRC_LATCHED_DELAY);
1213 #endif
1214
1215         mutex_lock(&dc->lock);
1216         tegra_dc_io_start(dc);
1217         tegra_dc_hold_dc_out(dc);
1218         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1219         tegra_dc_release_dc_out(dc);
1220         tegra_dc_io_end(dc);
1221         mutex_unlock(&dc->lock);
1222 crc_error:
1223         return crc;
1224 }
1225
1226 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1227 {
1228 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1229         u32 val;
1230
1231         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1232         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1233             return true;
1234 #endif
1235         return false;
1236 }
1237
1238 static inline void enable_dc_irq(const struct tegra_dc *dc)
1239 {
1240 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1241         enable_irq(dc->irq);
1242 #else
1243         /* Always disable DC interrupts on FPGA. */
1244         disable_irq(dc->irq);
1245 #endif
1246 }
1247
1248 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1249 {
1250         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1251                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1252 }
1253
1254 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1255 {
1256         int ret = -ENOTTY;
1257
1258         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1259                 return ret;
1260
1261         /*
1262          * Logic is as follows
1263          * a) Indicate we need a vblank.
1264          * b) Wait for completion to be signalled from isr.
1265          * c) Initialize completion for next iteration.
1266          */
1267
1268         tegra_dc_hold_dc_out(dc);
1269         dc->out->user_needs_vblank = true;
1270
1271         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1272         init_completion(&dc->out->user_vblank_comp);
1273         tegra_dc_release_dc_out(dc);
1274
1275         return ret;
1276 }
1277
1278 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1279 {
1280         /* Do the actual brightness update outside of the mutex dc->lock */
1281         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1282                 dc->out->sd_settings->bl_device_name) {
1283                 char *bl_device_name =
1284                         dc->out->sd_settings->bl_device_name;
1285                 dc->out->sd_settings->bl_device =
1286                         get_backlight_device_by_name(bl_device_name);
1287         }
1288
1289         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1290                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1291                 backlight_update_status(bl);
1292         }
1293 }
1294
1295 static void tegra_dc_vblank(struct work_struct *work)
1296 {
1297         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1298         bool nvsd_updated = false;
1299
1300         mutex_lock(&dc->lock);
1301
1302         if (!dc->enabled) {
1303                 mutex_unlock(&dc->lock);
1304                 return;
1305         }
1306
1307         tegra_dc_io_start(dc);
1308         tegra_dc_hold_dc_out(dc);
1309         /* use the new frame's bandwidth setting instead of max(current, new),
1310          * skip this if we're using tegra_dc_one_shot_worker() */
1311         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1312                 tegra_dc_program_bandwidth(dc, true);
1313
1314         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1315         if (!tegra_dc_windows_are_dirty(dc))
1316                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1317
1318         /* Update the SD brightness */
1319         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1320                 nvsd_updated = nvsd_update_brightness(dc);
1321                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1322                  * V_BLANK_NVSD bit of vblank ref-count. */
1323                 if (nvsd_updated) {
1324                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1325                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1326                 } else {
1327                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1328                 }
1329         }
1330
1331         /* Mask vblank interrupt if ref-count is zero. */
1332         if (!dc->vblank_ref_count)
1333                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1334
1335         tegra_dc_release_dc_out(dc);
1336         tegra_dc_io_end(dc);
1337         mutex_unlock(&dc->lock);
1338
1339         /* Do the actual brightness update outside of the mutex dc->lock */
1340         if (nvsd_updated)
1341                 tegra_dc_prism_update_backlight(dc);
1342 }
1343
1344 static void tegra_dc_one_shot_worker(struct work_struct *work)
1345 {
1346         struct tegra_dc *dc = container_of(
1347                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1348         mutex_lock(&dc->lock);
1349
1350         /* memory client has gone idle */
1351         tegra_dc_clear_bandwidth(dc);
1352
1353         if (dc->out_ops->idle) {
1354                 tegra_dc_io_start(dc);
1355                 dc->out_ops->idle(dc);
1356                 tegra_dc_io_end(dc);
1357         }
1358
1359         mutex_unlock(&dc->lock);
1360 }
1361
1362 /* return an arbitrarily large number if count overflow occurs.
1363  * make it a nice base-10 number to show up in stats output */
1364 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1365 {
1366         unsigned count = tegra_dc_readl(dc, reg);
1367
1368         tegra_dc_writel(dc, 0, reg);
1369         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1370 }
1371
1372 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1373 {
1374         int i;
1375
1376         dc->stats.underflows++;
1377         if (dc->underflow_mask & WIN_A_UF_INT)
1378                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1379                         DC_WINBUF_AD_UFLOW_STATUS);
1380         if (dc->underflow_mask & WIN_B_UF_INT)
1381                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1382                         DC_WINBUF_BD_UFLOW_STATUS);
1383         if (dc->underflow_mask & WIN_C_UF_INT)
1384                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1385                         DC_WINBUF_CD_UFLOW_STATUS);
1386
1387         /* Check for any underflow reset conditions */
1388         for (i = 0; i < DC_N_WINDOWS; i++) {
1389                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1390                         dc->windows[i].underflows++;
1391
1392 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1393                         if (dc->windows[i].underflows > 4) {
1394                                 schedule_work(&dc->reset_work);
1395                                 /* reset counter */
1396                                 dc->windows[i].underflows = 0;
1397                                 trace_display_reset(dc);
1398                         }
1399 #endif
1400 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1401                         if (dc->windows[i].underflows > 4) {
1402                                 trace_display_reset(dc);
1403                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1404                                                 DC_DISP_DISP_MISC_CONTROL);
1405                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1406                                                 DC_CMD_STATE_CONTROL);
1407                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1408                                                 DC_CMD_STATE_CONTROL);
1409
1410                                 tegra_dc_writel(dc, 0,
1411                                                 DC_DISP_DISP_MISC_CONTROL);
1412                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1413                                                 DC_CMD_STATE_CONTROL);
1414                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1415                                                 DC_CMD_STATE_CONTROL);
1416                         }
1417 #endif
1418                 } else {
1419                         dc->windows[i].underflows = 0;
1420                 }
1421         }
1422
1423         /* Clear the underflow mask now that we've checked it. */
1424         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1425         dc->underflow_mask = 0;
1426         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1427         trace_underflow(dc);
1428 }
1429
1430 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1431 static void tegra_dc_vpulse2(struct work_struct *work)
1432 {
1433         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1434         bool nvsd_updated = false;
1435
1436         mutex_lock(&dc->lock);
1437
1438         if (!dc->enabled) {
1439                 mutex_unlock(&dc->lock);
1440                 return;
1441         }
1442
1443         tegra_dc_io_start(dc);
1444         tegra_dc_hold_dc_out(dc);
1445
1446         /* Clear the V_PULSE2_FLIP if no update */
1447         if (!tegra_dc_windows_are_dirty(dc))
1448                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1449
1450         /* Update the SD brightness */
1451         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1452                 nvsd_updated = nvsd_update_brightness(dc);
1453                 if (nvsd_updated) {
1454                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1455                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1456                 } else {
1457                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1458                 }
1459         }
1460
1461         /* Mask vpulse2 interrupt if ref-count is zero. */
1462         if (!dc->vpulse2_ref_count)
1463                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1464
1465         tegra_dc_release_dc_out(dc);
1466         tegra_dc_io_end(dc);
1467         mutex_unlock(&dc->lock);
1468
1469         /* Do the actual brightness update outside of the mutex dc->lock */
1470         if (nvsd_updated)
1471                 tegra_dc_prism_update_backlight(dc);
1472 }
1473 #endif
1474
1475 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1476 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1477 {
1478         /* pending user vblank, so wakeup */
1479         if ((status & (V_BLANK_INT | MSF_INT)) &&
1480             (dc->out->user_needs_vblank)) {
1481                 dc->out->user_needs_vblank = false;
1482                 complete(&dc->out->user_vblank_comp);
1483         }
1484
1485         if (status & V_BLANK_INT) {
1486                 /* Sync up windows. */
1487                 tegra_dc_trigger_windows(dc);
1488
1489                 /* Schedule any additional bottom-half vblank actvities. */
1490                 queue_work(system_freezable_wq, &dc->vblank_work);
1491         }
1492
1493         if (status & FRAME_END_INT) {
1494                 /* Mark the frame_end as complete. */
1495                 if (!completion_done(&dc->frame_end_complete))
1496                         complete(&dc->frame_end_complete);
1497         }
1498
1499 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1500         if (status & V_PULSE2_INT)
1501                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1502 #endif
1503 }
1504
1505 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1506 {
1507         /* Schedule any additional bottom-half vblank actvities. */
1508         if (status & V_BLANK_INT)
1509                 queue_work(system_freezable_wq, &dc->vblank_work);
1510
1511         if (status & FRAME_END_INT) {
1512                 struct timespec tm = CURRENT_TIME;
1513                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1514                 wake_up(&dc->timestamp_wq);
1515
1516                 /* Mark the frame_end as complete. */
1517                 if (!completion_done(&dc->frame_end_complete))
1518                         complete(&dc->frame_end_complete);
1519
1520                 tegra_dc_trigger_windows(dc);
1521         }
1522
1523 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1524         if (status & V_PULSE2_INT)
1525                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1526 #endif
1527 }
1528
1529 /* XXX: Not sure if we limit look ahead to 1 frame */
1530 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1531 {
1532         BUG_ON(!dc->frametime_ns);
1533         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1534 }
1535
1536 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1537 {
1538         BUG_ON(!dc->frametime_ns);
1539         return (((new_ts - old_ts) > dc->frametime_ns)
1540                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1541                         != div_s64((old_ts - dc->frame_end_timestamp),
1542                                 dc->frametime_ns)));
1543 }
1544 #endif
1545
1546 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1547 {
1548 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1549         struct tegra_dc *dc = ptr;
1550         unsigned long status;
1551         unsigned long underflow_mask;
1552         u32 val;
1553         int need_disable = 0;
1554
1555         mutex_lock(&dc->lock);
1556         if (!dc->enabled) {
1557                 mutex_unlock(&dc->lock);
1558                 return IRQ_HANDLED;
1559         }
1560
1561         clk_prepare_enable(dc->clk);
1562         tegra_dc_io_start(dc);
1563         tegra_dc_hold_dc_out(dc);
1564
1565         if (!nvhost_module_powered_ext(dc->ndev)) {
1566                 WARN(1, "IRQ when DC not powered!\n");
1567                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1568                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1569                 tegra_dc_release_dc_out(dc);
1570                 tegra_dc_io_end(dc);
1571                 clk_disable_unprepare(dc->clk);
1572                 mutex_unlock(&dc->lock);
1573                 return IRQ_HANDLED;
1574         }
1575
1576         /* clear all status flags except underflow, save those for the worker */
1577         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1578         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1579         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1580         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1581
1582         /*
1583          * Overlays can get thier internal state corrupted during and underflow
1584          * condition.  The only way to fix this state is to reset the DC.
1585          * if we get 4 consecutive frames with underflows, assume we're
1586          * hosed and reset.
1587          */
1588         underflow_mask = status & ALL_UF_INT;
1589
1590         /* Check underflow */
1591         if (underflow_mask) {
1592                 dc->underflow_mask |= underflow_mask;
1593                 schedule_delayed_work(&dc->underflow_work,
1594                         msecs_to_jiffies(1));
1595         }
1596
1597         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1598                 tegra_dc_one_shot_irq(dc, status);
1599         else
1600                 tegra_dc_continuous_irq(dc, status);
1601
1602         /* update video mode if it has changed since the last frame */
1603         if (status & (FRAME_END_INT | V_BLANK_INT))
1604                 if (tegra_dc_update_mode(dc))
1605                         need_disable = 1; /* force display off on error */
1606
1607         tegra_dc_release_dc_out(dc);
1608         tegra_dc_io_end(dc);
1609         clk_disable_unprepare(dc->clk);
1610         mutex_unlock(&dc->lock);
1611
1612         if (need_disable)
1613                 tegra_dc_disable(dc);
1614         return IRQ_HANDLED;
1615 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1616         return IRQ_NONE;
1617 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1618 }
1619
1620 void tegra_dc_set_color_control(struct tegra_dc *dc)
1621 {
1622         u32 color_control;
1623
1624         switch (dc->out->depth) {
1625         case 3:
1626                 color_control = BASE_COLOR_SIZE111;
1627                 break;
1628
1629         case 6:
1630                 color_control = BASE_COLOR_SIZE222;
1631                 break;
1632
1633         case 8:
1634                 color_control = BASE_COLOR_SIZE332;
1635                 break;
1636
1637         case 9:
1638                 color_control = BASE_COLOR_SIZE333;
1639                 break;
1640
1641         case 12:
1642                 color_control = BASE_COLOR_SIZE444;
1643                 break;
1644
1645         case 15:
1646                 color_control = BASE_COLOR_SIZE555;
1647                 break;
1648
1649         case 16:
1650                 color_control = BASE_COLOR_SIZE565;
1651                 break;
1652
1653         case 18:
1654                 color_control = BASE_COLOR_SIZE666;
1655                 break;
1656
1657         default:
1658                 color_control = BASE_COLOR_SIZE888;
1659                 break;
1660         }
1661
1662         switch (dc->out->dither) {
1663         case TEGRA_DC_DISABLE_DITHER:
1664                 color_control |= DITHER_CONTROL_DISABLE;
1665                 break;
1666         case TEGRA_DC_ORDERED_DITHER:
1667                 color_control |= DITHER_CONTROL_ORDERED;
1668                 break;
1669         case TEGRA_DC_ERRDIFF_DITHER:
1670                 /* The line buffer for error-diffusion dither is limited
1671                  * to 1280 pixels per line. This limits the maximum
1672                  * horizontal active area size to 1280 pixels when error
1673                  * diffusion is enabled.
1674                  */
1675                 BUG_ON(dc->mode.h_active > 1280);
1676                 color_control |= DITHER_CONTROL_ERRDIFF;
1677                 break;
1678         }
1679
1680 #ifdef CONFIG_TEGRA_DC_CMU
1681         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1682                 color_control |= CMU_ENABLE;
1683 #endif
1684
1685         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1686 }
1687
1688 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1689 {
1690         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
1691                 return dc->win_syncpt[idx];
1692         BUG();
1693 }
1694
1695 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
1696 {
1697 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1698         u32 start, end;
1699         unsigned long val;
1700
1701         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
1702         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
1703
1704         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
1705                 dc->mode.v_back_porch + dc->mode.v_active;
1706         end = start + 1;
1707         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
1708         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
1709
1710         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1711         val |= V_PULSE2_INT;
1712         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
1713
1714         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1715         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1716 #endif
1717 }
1718
1719 static int tegra_dc_init(struct tegra_dc *dc)
1720 {
1721         int i;
1722         int int_enable;
1723
1724         tegra_dc_io_start(dc);
1725         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1726         if (dc->ndev->id == 0) {
1727                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1728                                       TEGRA_MC_PRIO_MED);
1729                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1730                                       TEGRA_MC_PRIO_MED);
1731                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1732                                       TEGRA_MC_PRIO_MED);
1733 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1734                 /* only present on Tegra2 and 3 */
1735                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1736                                       TEGRA_MC_PRIO_MED);
1737 #endif
1738                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1739                                       TEGRA_MC_PRIO_HIGH);
1740         } else if (dc->ndev->id == 1) {
1741                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1742                                       TEGRA_MC_PRIO_MED);
1743                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1744                                       TEGRA_MC_PRIO_MED);
1745                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1746                                       TEGRA_MC_PRIO_MED);
1747 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1748                 /* only present on Tegra2 and 3 */
1749                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1750                                       TEGRA_MC_PRIO_MED);
1751 #endif
1752                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1753                                       TEGRA_MC_PRIO_HIGH);
1754         }
1755         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1756                         DC_CMD_CONT_SYNCPT_VSYNC);
1757
1758         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1759         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1760         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1761         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1762 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1763         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1764 #endif
1765         /* enable interrupts for vblank, frame_end and underflows */
1766         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1767         /* for panels with one-shot mode enable tearing effect interrupt */
1768         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1769                 int_enable |= MSF_INT;
1770
1771         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1772         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1773         tegra_dc_init_vpulse2_int(dc);
1774
1775         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1776
1777 #ifdef CONFIG_TEGRA_DC_CMU
1778         if (dc->pdata->cmu)
1779                 _tegra_dc_update_cmu(dc, dc->pdata->cmu);
1780         else
1781                 _tegra_dc_update_cmu(dc, &default_cmu);
1782 #endif
1783         tegra_dc_set_color_control(dc);
1784         for (i = 0; i < DC_N_WINDOWS; i++) {
1785                 struct tegra_dc_win *win = &dc->windows[i];
1786                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1787                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1788                 tegra_dc_set_csc(dc, &win->csc);
1789                 tegra_dc_set_lut(dc, win);
1790                 tegra_dc_set_scaling_filter(dc);
1791         }
1792
1793         /* Set window H to window mode by default for t14x. */
1794 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
1795         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
1796                         DC_DISP_BLEND_CURSOR_CONTROL);
1797 #endif
1798         for (i = 0; i < dc->n_windows; i++) {
1799                 u32 syncpt = get_syncpt(dc, i);
1800
1801                 dc->syncpt[i].id = syncpt;
1802
1803                 dc->syncpt[i].min = dc->syncpt[i].max =
1804                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1805         }
1806
1807         trace_display_mode(dc, &dc->mode);
1808
1809         if (dc->mode.pclk) {
1810                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1811                         tegra_dc_io_end(dc);
1812                         return -EINVAL;
1813                 }
1814         }
1815
1816         /* Initialize SD AFTER the modeset.
1817            nvsd_init handles the sd_settings = NULL case. */
1818         nvsd_init(dc, dc->out->sd_settings);
1819
1820         tegra_dc_io_end(dc);
1821
1822         return 0;
1823 }
1824
1825 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1826 {
1827         int failed_init = 0;
1828
1829         tegra_dc_unpowergate_locked(dc);
1830
1831         if (dc->out->enable)
1832                 dc->out->enable(&dc->ndev->dev);
1833
1834         tegra_dc_setup_clk(dc, dc->clk);
1835         tegra_dc_clk_enable(dc);
1836         tegra_dc_io_start(dc);
1837
1838         tegra_dc_power_on(dc);
1839
1840         /* do not accept interrupts during initialization */
1841         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1842
1843         enable_dc_irq(dc);
1844
1845         failed_init = tegra_dc_init(dc);
1846         if (failed_init) {
1847                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1848                 disable_irq_nosync(dc->irq);
1849                 tegra_dc_clear_bandwidth(dc);
1850                 tegra_dc_clk_disable(dc);
1851                 if (dc->out && dc->out->disable)
1852                         dc->out->disable();
1853                 tegra_dc_io_end(dc);
1854                 return false;
1855         }
1856
1857         if (dc->out_ops && dc->out_ops->enable)
1858                 dc->out_ops->enable(dc);
1859
1860         /* force a full blending update */
1861         dc->blend.z[0] = -1;
1862
1863         tegra_dc_ext_enable(dc->ext);
1864
1865         trace_display_enable(dc);
1866
1867         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1868         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1869
1870         if (dc->out->postpoweron)
1871                 dc->out->postpoweron();
1872
1873         tegra_dc_io_end(dc);
1874         return true;
1875 }
1876
1877 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1878 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1879 {
1880         bool ret = true;
1881
1882         if (dc->out->enable)
1883                 dc->out->enable(&dc->ndev->dev);
1884
1885         tegra_dc_setup_clk(dc, dc->clk);
1886         tegra_dc_clk_enable(dc);
1887
1888         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1889                 mutex_lock(&tegra_dcs[1]->lock);
1890                 disable_irq_nosync(tegra_dcs[1]->irq);
1891         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1892                 mutex_lock(&tegra_dcs[0]->lock);
1893                 disable_irq_nosync(tegra_dcs[0]->irq);
1894         }
1895
1896         msleep(5);
1897         tegra_periph_reset_assert(dc->clk);
1898         msleep(2);
1899 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1900         tegra_periph_reset_deassert(dc->clk);
1901         msleep(1);
1902 #endif
1903
1904         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1905                 enable_dc_irq(tegra_dcs[1]);
1906                 mutex_unlock(&tegra_dcs[1]->lock);
1907         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1908                 enable_dc_irq(tegra_dcs[0]);
1909                 mutex_unlock(&tegra_dcs[0]->lock);
1910         }
1911
1912         enable_dc_irq(dc);
1913
1914         if (tegra_dc_init(dc)) {
1915                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1916                 ret = false;
1917         }
1918
1919         if (dc->out_ops && dc->out_ops->enable)
1920                 dc->out_ops->enable(dc);
1921
1922         if (dc->out->postpoweron)
1923                 dc->out->postpoweron();
1924
1925         /* force a full blending update */
1926         dc->blend.z[0] = -1;
1927
1928         tegra_dc_ext_enable(dc->ext);
1929
1930         if (!ret) {
1931                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1932                 _tegra_dc_controller_disable(dc);
1933         }
1934
1935         trace_display_reset(dc);
1936         return ret;
1937 }
1938 #endif
1939
1940 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1941 {
1942         if (dc->mode.pclk == 0) {
1943                 switch (dc->out->type) {
1944                 case TEGRA_DC_OUT_HDMI:
1945                 /* DC enable called but no videomode is loaded.
1946                      Check if HDMI is connected, then set fallback mdoe */
1947                 if (tegra_dc_hpd(dc)) {
1948                         return tegra_dc_set_fb_mode(dc,
1949                                         &tegra_dc_hdmi_fallback_mode, 0);
1950                 } else
1951                         return false;
1952
1953                 break;
1954
1955                 /* Do nothing for other outputs for now */
1956                 case TEGRA_DC_OUT_RGB:
1957
1958                 case TEGRA_DC_OUT_DSI:
1959
1960                 default:
1961                         return false;
1962                 }
1963         }
1964
1965         return false;
1966 }
1967
1968 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1969 {
1970         return _tegra_dc_set_default_videomode(dc);
1971 }
1972
1973 static bool _tegra_dc_enable(struct tegra_dc *dc)
1974 {
1975         if (dc->mode.pclk == 0)
1976                 return false;
1977
1978         if (!dc->out)
1979                 return false;
1980
1981         if (dc->enabled)
1982                 return true;
1983
1984         pm_runtime_get_sync(&dc->ndev->dev);
1985
1986         if (!_tegra_dc_controller_enable(dc)) {
1987                 pm_runtime_put_sync(&dc->ndev->dev);
1988                 return false;
1989         }
1990
1991         return true;
1992 }
1993
1994 void tegra_dc_enable(struct tegra_dc *dc)
1995 {
1996         mutex_lock(&dc->lock);
1997
1998         if (!dc->enabled)
1999                 dc->enabled = _tegra_dc_enable(dc);
2000
2001         mutex_unlock(&dc->lock);
2002         trace_display_mode(dc, &dc->mode);
2003 }
2004
2005 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2006 {
2007         unsigned i;
2008
2009         tegra_dc_hold_dc_out(dc);
2010
2011         if (dc->out && dc->out->prepoweroff)
2012                 dc->out->prepoweroff();
2013
2014         if (dc->out_ops && dc->out_ops->disable)
2015                 dc->out_ops->disable(dc);
2016
2017         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2018
2019         disable_irq_nosync(dc->irq);
2020
2021         tegra_dc_clear_bandwidth(dc);
2022
2023         if (dc->out && dc->out->disable)
2024                 dc->out->disable();
2025
2026         for (i = 0; i < dc->n_windows; i++) {
2027                 struct tegra_dc_win *w = &dc->windows[i];
2028
2029                 /* reset window bandwidth */
2030                 w->bandwidth = 0;
2031                 w->new_bandwidth = 0;
2032
2033                 /* disable windows */
2034                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2035
2036                 /* flush any pending syncpt waits */
2037                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
2038                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
2039                                 dc->syncpt[i].min, dc->syncpt[i].max);
2040                         dc->syncpt[i].min++;
2041                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
2042                 }
2043         }
2044         trace_display_disable(dc);
2045
2046         tegra_dc_clk_disable(dc);
2047         tegra_dc_release_dc_out(dc);
2048 }
2049
2050 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2051 {
2052 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2053         u32 val;
2054         if (dc->enabled)  {
2055                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2056                 if (enable)
2057                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2058                 else
2059                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2060                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2061         }
2062 #endif
2063 }
2064
2065 bool tegra_dc_stats_get(struct tegra_dc *dc)
2066 {
2067 #if 0 /* right now it is always enabled */
2068         u32 val;
2069         bool res;
2070
2071         if (dc->enabled)  {
2072                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2073                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2074         } else {
2075                 res = false;
2076         }
2077
2078         return res;
2079 #endif
2080         return true;
2081 }
2082
2083 /* make the screen blank by disabling all windows */
2084 void tegra_dc_blank(struct tegra_dc *dc)
2085 {
2086         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2087         unsigned i;
2088
2089         for (i = 0; i < DC_N_WINDOWS; i++) {
2090                 dcwins[i] = tegra_dc_get_window(dc, i);
2091                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2092         }
2093
2094         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
2095         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
2096 }
2097
2098 static void _tegra_dc_disable(struct tegra_dc *dc)
2099 {
2100         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2101                 mutex_lock(&dc->one_shot_lock);
2102                 cancel_delayed_work_sync(&dc->one_shot_work);
2103         }
2104
2105         tegra_dc_io_start(dc);
2106         _tegra_dc_controller_disable(dc);
2107         tegra_dc_io_end(dc);
2108
2109         tegra_dc_powergate_locked(dc);
2110
2111         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2112                 mutex_unlock(&dc->one_shot_lock);
2113         pm_runtime_put(&dc->ndev->dev);
2114 }
2115
2116 void tegra_dc_disable(struct tegra_dc *dc)
2117 {
2118         tegra_dc_ext_disable(dc->ext);
2119
2120         /* it's important that new underflow work isn't scheduled before the
2121          * lock is acquired. */
2122         cancel_delayed_work_sync(&dc->underflow_work);
2123
2124         mutex_lock(&dc->lock);
2125
2126         if (dc->enabled) {
2127                 dc->enabled = false;
2128
2129                 if (!dc->suspended)
2130                         _tegra_dc_disable(dc);
2131         }
2132
2133 #ifdef CONFIG_SWITCH
2134         switch_set_state(&dc->modeset_switch, 0);
2135 #endif
2136
2137         mutex_unlock(&dc->lock);
2138         synchronize_irq(dc->irq);
2139         trace_display_mode(dc, &dc->mode);
2140 }
2141
2142 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2143 static void tegra_dc_reset_worker(struct work_struct *work)
2144 {
2145         struct tegra_dc *dc =
2146                 container_of(work, struct tegra_dc, reset_work);
2147
2148         unsigned long val = 0;
2149
2150         mutex_lock(&shared_lock);
2151
2152         dev_warn(&dc->ndev->dev,
2153                 "overlay stuck in underflow state.  resetting.\n");
2154
2155         tegra_dc_ext_disable(dc->ext);
2156
2157         mutex_lock(&dc->lock);
2158
2159         if (dc->enabled == false)
2160                 goto unlock;
2161
2162         dc->enabled = false;
2163
2164         /*
2165          * off host read bus
2166          */
2167         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2168         val &= ~(0x00000100);
2169         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2170
2171         /*
2172          * set DC to STOP mode
2173          */
2174         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2175
2176         msleep(10);
2177
2178         _tegra_dc_controller_disable(dc);
2179
2180         /* _tegra_dc_controller_reset_enable deasserts reset */
2181         _tegra_dc_controller_reset_enable(dc);
2182
2183         dc->enabled = true;
2184
2185         /* reopen host read bus */
2186         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2187         val &= ~(0x00000100);
2188         val |= 0x100;
2189         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2190
2191 unlock:
2192         mutex_unlock(&dc->lock);
2193         mutex_unlock(&shared_lock);
2194         trace_display_reset(dc);
2195 }
2196 #endif
2197
2198 static void tegra_dc_underflow_worker(struct work_struct *work)
2199 {
2200         struct tegra_dc *dc = container_of(
2201                 to_delayed_work(work), struct tegra_dc, underflow_work);
2202
2203         mutex_lock(&dc->lock);
2204         tegra_dc_io_start(dc);
2205         tegra_dc_hold_dc_out(dc);
2206
2207         if (dc->enabled) {
2208                 tegra_dc_underflow_handler(dc);
2209         }
2210         tegra_dc_release_dc_out(dc);
2211         tegra_dc_io_end(dc);
2212         mutex_unlock(&dc->lock);
2213 }
2214
2215 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2216 /* A mutex used to protect the critical section used by both DC heads. */
2217 static struct mutex tegra_dc_powergate_status_lock;
2218
2219 /* defer turning off DISA until DISB is turned off */
2220 void tegra_dc_powergate_locked(struct tegra_dc *dc)
2221 {
2222         struct tegra_dc *dc_partner;
2223
2224         mutex_lock(&tegra_dc_powergate_status_lock);
2225         /* Get the handler of the other display controller. */
2226         dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2227         if (!dc_partner)
2228                 _tegra_dc_powergate_locked(dc);
2229         else if (dc->powergate_id == TEGRA_POWERGATE_DISA) {
2230                 /* If DISB is powergated, then powergate DISA. */
2231                 if (!dc_partner->powered)
2232                         _tegra_dc_powergate_locked(dc);
2233         } else if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2234                 /* If DISA is enabled, only powergate DISB;
2235                  * otherwise, powergate DISA and DISB.
2236                  * */
2237                 if (dc_partner->enabled) {
2238                         _tegra_dc_powergate_locked(dc);
2239                 } else {
2240                         _tegra_dc_powergate_locked(dc);
2241                         _tegra_dc_powergate_locked(dc_partner);
2242                 }
2243         }
2244         mutex_unlock(&tegra_dc_powergate_status_lock);
2245 }
2246
2247
2248 /* to turn on DISB we must first power on DISA */
2249 void tegra_dc_unpowergate_locked(struct tegra_dc *dc)
2250 {
2251         mutex_lock(&tegra_dc_powergate_status_lock);
2252         if (dc->powergate_id == TEGRA_POWERGATE_DISB) {
2253                 struct tegra_dc *dc_partner;
2254
2255                 /* Get the handler of the other display controller. */
2256                 dc_partner = tegra_dc_get_dc(dc->ndev->id ^ 1);
2257                 if (dc_partner)
2258                         _tegra_dc_unpowergate_locked(dc_partner);
2259         }
2260         _tegra_dc_unpowergate_locked(dc);
2261         mutex_unlock(&tegra_dc_powergate_status_lock);
2262 }
2263 #endif
2264
2265 #ifdef CONFIG_SWITCH
2266 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2267 {
2268         struct tegra_dc *dc =
2269                 container_of(sdev, struct tegra_dc, modeset_switch);
2270
2271         if (!sdev->state)
2272                 return sprintf(buf, "offline\n");
2273
2274         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2275 }
2276 #endif
2277
2278 static void tegra_dc_add_modes(struct tegra_dc *dc)
2279 {
2280         struct fb_monspecs specs;
2281         int i;
2282
2283         memset(&specs, 0, sizeof(specs));
2284         specs.max_x = dc->mode.h_active * 1000;
2285         specs.max_y = dc->mode.v_active * 1000;
2286         specs.modedb_len = dc->out->n_modes;
2287         specs.modedb = kzalloc(specs.modedb_len *
2288                 sizeof(struct fb_videomode), GFP_KERNEL);
2289         for (i = 0; i < dc->out->n_modes; i++)
2290                 tegra_dc_to_fb_videomode(&specs.modedb[i],
2291                         &dc->out->modes[i]);
2292         tegra_fb_update_monspecs(dc->fb, &specs, NULL);
2293         kfree(specs.modedb);
2294 }
2295
2296 static int tegra_dc_probe(struct platform_device *ndev)
2297 {
2298         struct tegra_dc *dc;
2299         struct tegra_dc_mode *mode;
2300         struct clk *clk;
2301         struct clk *emc_clk;
2302         struct resource *res;
2303         struct resource *base_res;
2304         struct resource *fb_mem = NULL;
2305         int ret = 0;
2306         void __iomem *base;
2307         int irq;
2308         int i;
2309
2310         if (!ndev->dev.platform_data) {
2311                 dev_err(&ndev->dev, "no platform data\n");
2312                 return -ENOENT;
2313         }
2314
2315         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2316         if (!dc) {
2317                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2318                 return -ENOMEM;
2319         }
2320
2321         irq = platform_get_irq_byname(ndev, "irq");
2322         if (irq <= 0) {
2323                 dev_err(&ndev->dev, "no irq\n");
2324                 ret = -ENOENT;
2325                 goto err_free;
2326         }
2327
2328         res = platform_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2329         if (!res) {
2330                 dev_err(&ndev->dev, "no mem resource\n");
2331                 ret = -ENOENT;
2332                 goto err_free;
2333         }
2334
2335         base_res = request_mem_region(res->start, resource_size(res),
2336                 ndev->name);
2337         if (!base_res) {
2338                 dev_err(&ndev->dev, "request_mem_region failed\n");
2339                 ret = -EBUSY;
2340                 goto err_free;
2341         }
2342
2343         base = ioremap(res->start, resource_size(res));
2344         if (!base) {
2345                 dev_err(&ndev->dev, "registers can't be mapped\n");
2346                 ret = -EBUSY;
2347                 goto err_release_resource_reg;
2348         }
2349         if (TEGRA_DISPLAY_BASE == res->start) {
2350                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
2351                 dc->win_syncpt[0] = NVSYNCPT_DISP0_A;
2352                 dc->win_syncpt[1] = NVSYNCPT_DISP0_B;
2353                 dc->win_syncpt[2] = NVSYNCPT_DISP0_C;
2354 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2355                 dc->win_syncpt[3] = NVSYNCPT_DISP0_D;
2356                 dc->win_syncpt[4] = NVSYNCPT_DISP0_H;
2357 #endif
2358                 dc->powergate_id = TEGRA_POWERGATE_DISA;
2359         } else if (TEGRA_DISPLAY2_BASE == res->start) {
2360                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
2361                 dc->win_syncpt[0] = NVSYNCPT_DISP1_A;
2362                 dc->win_syncpt[1] = NVSYNCPT_DISP1_B;
2363                 dc->win_syncpt[2] = NVSYNCPT_DISP1_C;
2364 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
2365                 dc->win_syncpt[4] = NVSYNCPT_DISP1_H;
2366 #endif
2367                 dc->powergate_id = TEGRA_POWERGATE_DISB;
2368         } else {
2369                 dev_err(&ndev->dev,
2370                         "Unknown base address %#08x: unable to assign syncpt\n",
2371                         res->start);
2372         }
2373
2374
2375         fb_mem = platform_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2376
2377         clk = clk_get(&ndev->dev, NULL);
2378         if (IS_ERR_OR_NULL(clk)) {
2379                 dev_err(&ndev->dev, "can't get clock\n");
2380                 ret = -ENOENT;
2381                 goto err_iounmap_reg;
2382         }
2383
2384         emc_clk = clk_get(&ndev->dev, "emc");
2385         if (IS_ERR_OR_NULL(emc_clk)) {
2386                 dev_err(&ndev->dev, "can't get emc clock\n");
2387                 ret = -ENOENT;
2388                 goto err_put_clk;
2389         }
2390
2391         dc->clk = clk;
2392         dc->emc_clk = emc_clk;
2393         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2394         /* Initialize one shot work delay, it will be assigned by dsi
2395          * according to refresh rate later. */
2396         dc->one_shot_delay_ms = 40;
2397
2398         dc->base_res = base_res;
2399         dc->base = base;
2400         dc->irq = irq;
2401         dc->ndev = ndev;
2402         dc->pdata = ndev->dev.platform_data;
2403
2404         /*
2405          * The emc is a shared clock, it will be set based on
2406          * the requirements for each user on the bus.
2407          */
2408         dc->emc_clk_rate = 0;
2409
2410         mutex_init(&dc->lock);
2411         mutex_init(&dc->one_shot_lock);
2412 #ifdef CONFIG_ARCH_TEGRA_11x_SOC
2413         mutex_init(&tegra_dc_powergate_status_lock);
2414 #endif
2415         init_completion(&dc->frame_end_complete);
2416         init_waitqueue_head(&dc->wq);
2417         init_waitqueue_head(&dc->timestamp_wq);
2418 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2419         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2420 #endif
2421         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2422         dc->vblank_ref_count = 0;
2423 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2424         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
2425 #endif
2426         dc->vpulse2_ref_count = 0;
2427         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2428         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2429
2430         tegra_dc_init_lut_defaults(&dc->fb_lut);
2431
2432         dc->n_windows = DC_N_WINDOWS;
2433         for (i = 0; i < dc->n_windows; i++) {
2434                 struct tegra_dc_win *win = &dc->windows[i];
2435                 win->idx = i;
2436                 win->dc = dc;
2437                 tegra_dc_init_csc_defaults(&win->csc);
2438                 tegra_dc_init_lut_defaults(&win->lut);
2439         }
2440
2441         ret = tegra_dc_set(dc, ndev->id);
2442         if (ret < 0) {
2443                 dev_err(&ndev->dev, "can't add dc\n");
2444                 goto err_put_emc_clk;
2445         }
2446
2447         platform_set_drvdata(ndev, dc);
2448
2449 #ifdef CONFIG_SWITCH
2450         dc->modeset_switch.name = dev_name(&ndev->dev);
2451         dc->modeset_switch.state = 0;
2452         dc->modeset_switch.print_state = switch_modeset_print_mode;
2453         ret = switch_dev_register(&dc->modeset_switch);
2454         if (ret < 0)
2455                 dev_err(&ndev->dev, "failed to register switch driver\n");
2456 #endif
2457
2458         tegra_dc_feature_register(dc);
2459
2460         if (dc->pdata->default_out)
2461                 tegra_dc_set_out(dc, dc->pdata->default_out);
2462         else
2463                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2464         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
2465
2466         dc->ext = tegra_dc_ext_register(ndev, dc);
2467         if (IS_ERR_OR_NULL(dc->ext)) {
2468                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2469                 dc->ext = NULL;
2470         }
2471
2472         /* interrupt handler must be registered before tegra_fb_register() */
2473         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2474                         dev_name(&ndev->dev), dc)) {
2475                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2476                 ret = -EBUSY;
2477                 goto err_disable_dc;
2478         }
2479         disable_dc_irq(dc);
2480
2481         pm_runtime_use_autosuspend(&ndev->dev);
2482         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
2483         pm_runtime_enable(&ndev->dev);
2484
2485         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2486                 _tegra_dc_set_default_videomode(dc);
2487                 dc->enabled = _tegra_dc_enable(dc);
2488         }
2489
2490         tegra_dc_create_debugfs(dc);
2491
2492         dev_info(&ndev->dev, "probed\n");
2493
2494         if (dc->pdata->fb) {
2495                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2496                         unsigned long fmt;
2497                         tegra_dc_writel(dc,
2498                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2499                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2500
2501                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2502                         dc->pdata->fb->bits_per_pixel =
2503                                 tegra_dc_fmt_bpp(fmt);
2504                 }
2505
2506                 mode = tegra_dc_get_override_mode(dc);
2507                 if (mode) {
2508                         dc->pdata->fb->xres = mode->h_active;
2509                         dc->pdata->fb->yres = mode->v_active;
2510                 }
2511
2512                 tegra_dc_io_start(dc);
2513                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2514                 tegra_dc_io_end(dc);
2515                 if (IS_ERR_OR_NULL(dc->fb)) {
2516                         dc->fb = NULL;
2517                         dev_err(&ndev->dev, "failed to register fb\n");
2518                         goto err_remove_debugfs;
2519                 }
2520         }
2521
2522         if (dc->out && dc->out->n_modes)
2523                 tegra_dc_add_modes(dc);
2524
2525         if (dc->out && dc->out->hotplug_init)
2526                 dc->out->hotplug_init(&ndev->dev);
2527
2528         if (dc->out_ops && dc->out_ops->detect)
2529                 dc->out_ops->detect(dc);
2530         else
2531                 dc->connected = true;
2532
2533         /* Powergate display module when it's unconnected. */
2534         if (!tegra_dc_get_connected(dc))
2535                 tegra_dc_powergate_locked(dc);
2536
2537         tegra_dc_create_sysfs(&dc->ndev->dev);
2538
2539         return 0;
2540
2541 err_remove_debugfs:
2542         tegra_dc_remove_debugfs(dc);
2543         free_irq(irq, dc);
2544 err_disable_dc:
2545         if (dc->ext) {
2546                 tegra_dc_ext_disable(dc->ext);
2547                 tegra_dc_ext_unregister(dc->ext);
2548         }
2549         mutex_lock(&dc->lock);
2550         if (dc->enabled)
2551                 _tegra_dc_disable(dc);
2552         dc->enabled = false;
2553         mutex_unlock(&dc->lock);
2554 #ifdef CONFIG_SWITCH
2555         switch_dev_unregister(&dc->modeset_switch);
2556 #endif
2557 err_put_emc_clk:
2558         clk_put(emc_clk);
2559 err_put_clk:
2560         clk_put(clk);
2561 err_iounmap_reg:
2562         iounmap(base);
2563         if (fb_mem)
2564                 release_resource(fb_mem);
2565 err_release_resource_reg:
2566         release_resource(base_res);
2567 err_free:
2568         kfree(dc);
2569
2570         return ret;
2571 }
2572
2573 static int tegra_dc_remove(struct platform_device *ndev)
2574 {
2575         struct tegra_dc *dc = platform_get_drvdata(ndev);
2576
2577         tegra_dc_remove_sysfs(&dc->ndev->dev);
2578         tegra_dc_remove_debugfs(dc);
2579
2580         if (dc->fb) {
2581                 tegra_fb_unregister(dc->fb);
2582                 if (dc->fb_mem)
2583                         release_resource(dc->fb_mem);
2584         }
2585
2586         tegra_dc_ext_disable(dc->ext);
2587
2588         if (dc->ext)
2589                 tegra_dc_ext_unregister(dc->ext);
2590
2591         mutex_lock(&dc->lock);
2592         if (dc->enabled)
2593                 _tegra_dc_disable(dc);
2594         dc->enabled = false;
2595         mutex_unlock(&dc->lock);
2596         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2597
2598 #ifdef CONFIG_SWITCH
2599         switch_dev_unregister(&dc->modeset_switch);
2600 #endif
2601         free_irq(dc->irq, dc);
2602         clk_put(dc->emc_clk);
2603         clk_put(dc->clk);
2604         iounmap(dc->base);
2605         if (dc->fb_mem)
2606                 release_resource(dc->base_res);
2607         kfree(dc);
2608         tegra_dc_set(NULL, ndev->id);
2609
2610         return 0;
2611 }
2612
2613 #ifdef CONFIG_PM
2614 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
2615 {
2616         struct tegra_dc *dc = platform_get_drvdata(ndev);
2617
2618         trace_display_suspend(dc);
2619         dev_info(&ndev->dev, "suspend\n");
2620
2621         tegra_dc_ext_disable(dc->ext);
2622
2623         mutex_lock(&dc->lock);
2624         tegra_dc_io_start(dc);
2625
2626         if (dc->out_ops && dc->out_ops->suspend)
2627                 dc->out_ops->suspend(dc);
2628
2629         if (dc->enabled) {
2630                 _tegra_dc_disable(dc);
2631
2632                 dc->suspended = true;
2633         }
2634
2635         if (dc->out && dc->out->postsuspend) {
2636                 dc->out->postsuspend();
2637                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2638                         /*
2639                          * avoid resume event due to voltage falling
2640                          */
2641                         msleep(100);
2642         }
2643
2644         tegra_dc_io_end(dc);
2645         mutex_unlock(&dc->lock);
2646         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2647
2648         return 0;
2649 }
2650
2651 static int tegra_dc_resume(struct platform_device *ndev)
2652 {
2653         struct tegra_dc *dc = platform_get_drvdata(ndev);
2654
2655         trace_display_resume(dc);
2656         dev_info(&ndev->dev, "resume\n");
2657
2658         mutex_lock(&dc->lock);
2659         dc->suspended = false;
2660
2661         if (dc->enabled) {
2662                 dc->enabled = false;
2663                 _tegra_dc_set_default_videomode(dc);
2664                 dc->enabled = _tegra_dc_enable(dc);
2665         }
2666
2667         if (dc->out && dc->out->hotplug_init)
2668                 dc->out->hotplug_init(&ndev->dev);
2669
2670         if (dc->out_ops && dc->out_ops->resume)
2671                 dc->out_ops->resume(dc);
2672         mutex_unlock(&dc->lock);
2673
2674         return 0;
2675 }
2676
2677 #endif /* CONFIG_PM */
2678
2679 static void tegra_dc_shutdown(struct platform_device *ndev)
2680 {
2681         struct tegra_dc *dc = platform_get_drvdata(ndev);
2682
2683         if (!dc || !dc->enabled)
2684                 return;
2685
2686 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
2687         /* Hack: no windows blanking for simulation to save shutdown time */
2688         tegra_dc_blank(dc);
2689 #endif
2690         tegra_dc_disable(dc);
2691 }
2692
2693 extern int suspend_set(const char *val, struct kernel_param *kp)
2694 {
2695         if (!strcmp(val, "dump"))
2696                 dump_regs(tegra_dcs[0]);
2697 #ifdef CONFIG_PM
2698         else if (!strcmp(val, "suspend"))
2699                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2700         else if (!strcmp(val, "resume"))
2701                 tegra_dc_resume(tegra_dcs[0]->ndev);
2702 #endif
2703
2704         return 0;
2705 }
2706
2707 extern int suspend_get(char *buffer, struct kernel_param *kp)
2708 {
2709         return 0;
2710 }
2711
2712 int suspend;
2713
2714 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2715
2716 struct platform_driver tegra_dc_driver = {
2717         .driver = {
2718                 .name = "tegradc",
2719                 .owner = THIS_MODULE,
2720         },
2721         .probe = tegra_dc_probe,
2722         .remove = tegra_dc_remove,
2723 #ifdef CONFIG_PM
2724         .suspend = tegra_dc_suspend,
2725         .resume = tegra_dc_resume,
2726 #endif
2727         .shutdown = tegra_dc_shutdown,
2728 };
2729
2730 #ifndef MODULE
2731 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2732 {
2733         int i, params[11];
2734         char *p;
2735
2736         for (i = 0; i < ARRAY_SIZE(params); i++) {
2737                 if ((p = strsep(&options, ",")) != NULL) {
2738                         if (*p)
2739                                 params[i] = simple_strtoul(p, &p, 10);
2740                 } else
2741                         return -EINVAL;
2742         }
2743
2744         if ((mode->pclk = params[0]) == 0)
2745                 return -EINVAL;
2746
2747         mode->h_active      = params[1];
2748         mode->v_active      = params[2];
2749         mode->h_ref_to_sync = params[3];
2750         mode->v_ref_to_sync = params[4];
2751         mode->h_sync_width  = params[5];
2752         mode->v_sync_width  = params[6];
2753         mode->h_back_porch  = params[7];
2754         mode->v_back_porch  = params[8];
2755         mode->h_front_porch = params[9];
2756         mode->v_front_porch = params[10];
2757
2758         return 0;
2759 }
2760
2761 static int __init tegra_dc_mode_override(char *str)
2762 {
2763         char *p = str, *options;
2764
2765         if (!p || !*p)
2766                 return -EINVAL;
2767
2768         p = strstr(str, "hdmi:");
2769         if (p) {
2770                 p += 5;
2771                 options = strsep(&p, ";");
2772                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2773                         return -EINVAL;
2774         }
2775
2776         p = strstr(str, "rgb:");
2777         if (p) {
2778                 p += 4;
2779                 options = strsep(&p, ";");
2780                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2781                         return -EINVAL;
2782         }
2783
2784         p = strstr(str, "dsi:");
2785         if (p) {
2786                 p += 4;
2787                 options = strsep(&p, ";");
2788                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2789                         return -EINVAL;
2790         }
2791
2792         return 0;
2793 }
2794
2795 __setup("disp_params=", tegra_dc_mode_override);
2796 #endif
2797
2798 static int __init tegra_dc_module_init(void)
2799 {
2800         int ret = tegra_dc_ext_module_init();
2801         if (ret)
2802                 return ret;
2803         return platform_driver_register(&tegra_dc_driver);
2804 }
2805
2806 static void __exit tegra_dc_module_exit(void)
2807 {
2808         platform_driver_unregister(&tegra_dc_driver);
2809         tegra_dc_ext_module_exit();
2810 }
2811
2812 module_exit(tegra_dc_module_exit);
2813 module_init(tegra_dc_module_init);