video: tegra: dc: fix shift clk divider
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2012, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/clk.h>
28 #include <linux/mutex.h>
29 #include <linux/delay.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/workqueue.h>
32 #include <linux/ktime.h>
33 #include <linux/debugfs.h>
34 #include <linux/seq_file.h>
35 #include <linux/backlight.h>
36 #include <linux/gpio.h>
37 #include <linux/nvhost.h>
38 #include <video/tegrafb.h>
39 #include <drm/drm_fixed.h>
40 #ifdef CONFIG_SWITCH
41 #include <linux/switch.h>
42 #endif
43
44 #define CREATE_TRACE_POINTS
45 #include <trace/events/display.h>
46
47 #include <mach/clk.h>
48 #include <mach/dc.h>
49 #include <mach/fb.h>
50 #include <mach/mc.h>
51 #include <linux/nvhost.h>
52 #include <mach/latency_allowance.h>
53
54 #include "dc_reg.h"
55 #include "dc_config.h"
56 #include "dc_priv.h"
57 #include "dev.h"
58 #include "nvsd.h"
59
60 #define TEGRA_CRC_LATCHED_DELAY         34
61
62 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
63 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
64
65 static struct fb_videomode tegra_dc_hdmi_fallback_mode = {
66         .refresh = 60,
67         .xres = 640,
68         .yres = 480,
69         .pixclock = KHZ2PICOS(25200),
70         .hsync_len = 96,        /* h_sync_width */
71         .vsync_len = 2,         /* v_sync_width */
72         .left_margin = 48,      /* h_back_porch */
73         .upper_margin = 33,     /* v_back_porch */
74         .right_margin = 16,     /* h_front_porch */
75         .lower_margin = 10,     /* v_front_porch */
76         .vmode = 0,
77         .sync = 0,
78 };
79
80 static struct tegra_dc_mode override_disp_mode[3];
81
82 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
83
84 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
85
86 DEFINE_MUTEX(tegra_dc_lock);
87 DEFINE_MUTEX(shared_lock);
88
89 static const struct {
90         bool h;
91         bool v;
92 } can_filter[] = {
93         /* Window A has no filtering */
94         { false, false },
95         /* Window B has both H and V filtering */
96         { true,  true  },
97         /* Window C has only H filtering */
98         { false, true  },
99 };
100
101 #ifdef CONFIG_TEGRA_DC_CMU
102 static struct tegra_dc_cmu default_cmu = {
103         /* lut1 maps sRGB to linear space. */
104         {
105                 0,    1,    2,    4,    5,    6,    7,    9,
106                 10,   11,   12,   14,   15,   16,   18,   20,
107                 21,   23,   25,   27,   29,   31,   33,   35,
108                 37,   40,   42,   45,   48,   50,   53,   56,
109                 59,   62,   66,   69,   72,   76,   79,   83,
110                 87,   91,   95,   99,   103,  107,  112,  116,
111                 121,  126,  131,  136,  141,  146,  151,  156,
112                 162,  168,  173,  179,  185,  191,  197,  204,
113                 210,  216,  223,  230,  237,  244,  251,  258,
114                 265,  273,  280,  288,  296,  304,  312,  320,
115                 329,  337,  346,  354,  363,  372,  381,  390,
116                 400,  409,  419,  428,  438,  448,  458,  469,
117                 479,  490,  500,  511,  522,  533,  544,  555,
118                 567,  578,  590,  602,  614,  626,  639,  651,
119                 664,  676,  689,  702,  715,  728,  742,  755,
120                 769,  783,  797,  811,  825,  840,  854,  869,
121                 884,  899,  914,  929,  945,  960,  976,  992,
122                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
123                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
124                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
125                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
126                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
127                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
128                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
129                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
130                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
131                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
132                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
133                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
134                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
135                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
136                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
137         },
138         /* csc */
139         {
140                 0x100, 0x0,   0x0,
141                 0x0,   0x100, 0x0,
142                 0x0,   0x0,   0x100,
143         },
144         /* lut2 maps linear space to sRGB*/
145         {
146                 0,    1,    2,    2,    3,    4,    5,    6,
147                 6,    7,    8,    9,    10,   10,   11,   12,
148                 13,   13,   14,   15,   15,   16,   16,   17,
149                 18,   18,   19,   19,   20,   20,   21,   21,
150                 22,   22,   23,   23,   23,   24,   24,   25,
151                 25,   25,   26,   26,   27,   27,   27,   28,
152                 28,   29,   29,   29,   30,   30,   30,   31,
153                 31,   31,   32,   32,   32,   33,   33,   33,
154                 34,   34,   34,   34,   35,   35,   35,   36,
155                 36,   36,   37,   37,   37,   37,   38,   38,
156                 38,   38,   39,   39,   39,   40,   40,   40,
157                 40,   41,   41,   41,   41,   42,   42,   42,
158                 42,   43,   43,   43,   43,   43,   44,   44,
159                 44,   44,   45,   45,   45,   45,   46,   46,
160                 46,   46,   46,   47,   47,   47,   47,   48,
161                 48,   48,   48,   48,   49,   49,   49,   49,
162                 49,   50,   50,   50,   50,   50,   51,   51,
163                 51,   51,   51,   52,   52,   52,   52,   52,
164                 53,   53,   53,   53,   53,   54,   54,   54,
165                 54,   54,   55,   55,   55,   55,   55,   55,
166                 56,   56,   56,   56,   56,   57,   57,   57,
167                 57,   57,   57,   58,   58,   58,   58,   58,
168                 58,   59,   59,   59,   59,   59,   59,   60,
169                 60,   60,   60,   60,   60,   61,   61,   61,
170                 61,   61,   61,   62,   62,   62,   62,   62,
171                 62,   63,   63,   63,   63,   63,   63,   64,
172                 64,   64,   64,   64,   64,   64,   65,   65,
173                 65,   65,   65,   65,   66,   66,   66,   66,
174                 66,   66,   66,   67,   67,   67,   67,   67,
175                 67,   67,   68,   68,   68,   68,   68,   68,
176                 68,   69,   69,   69,   69,   69,   69,   69,
177                 70,   70,   70,   70,   70,   70,   70,   71,
178                 71,   71,   71,   71,   71,   71,   72,   72,
179                 72,   72,   72,   72,   72,   72,   73,   73,
180                 73,   73,   73,   73,   73,   74,   74,   74,
181                 74,   74,   74,   74,   74,   75,   75,   75,
182                 75,   75,   75,   75,   75,   76,   76,   76,
183                 76,   76,   76,   76,   77,   77,   77,   77,
184                 77,   77,   77,   77,   78,   78,   78,   78,
185                 78,   78,   78,   78,   78,   79,   79,   79,
186                 79,   79,   79,   79,   79,   80,   80,   80,
187                 80,   80,   80,   80,   80,   81,   81,   81,
188                 81,   81,   81,   81,   81,   81,   82,   82,
189                 82,   82,   82,   82,   82,   82,   83,   83,
190                 83,   83,   83,   83,   83,   83,   83,   84,
191                 84,   84,   84,   84,   84,   84,   84,   84,
192                 85,   85,   85,   85,   85,   85,   85,   85,
193                 85,   86,   86,   86,   86,   86,   86,   86,
194                 86,   86,   87,   87,   87,   87,   87,   87,
195                 87,   87,   87,   88,   88,   88,   88,   88,
196                 88,   88,   88,   88,   88,   89,   89,   89,
197                 89,   89,   89,   89,   89,   89,   90,   90,
198                 90,   90,   90,   90,   90,   90,   90,   90,
199                 91,   91,   91,   91,   91,   91,   91,   91,
200                 91,   91,   92,   92,   92,   92,   92,   92,
201                 92,   92,   92,   92,   93,   93,   93,   93,
202                 93,   93,   93,   93,   93,   93,   94,   94,
203                 94,   94,   94,   94,   94,   94,   94,   94,
204                 95,   95,   95,   95,   95,   95,   95,   95,
205                 95,   95,   96,   96,   96,   96,   96,   96,
206                 96,   96,   96,   96,   96,   97,   97,   97,
207                 97,   97,   97,   97,   97,   97,   97,   98,
208                 98,   98,   98,   98,   98,   98,   98,   98,
209                 98,   98,   99,   99,   99,   99,   99,   99,
210                 99,   100,  101,  101,  102,  103,  103,  104,
211                 105,  105,  106,  107,  107,  108,  109,  109,
212                 110,  111,  111,  112,  113,  113,  114,  115,
213                 115,  116,  116,  117,  118,  118,  119,  119,
214                 120,  120,  121,  122,  122,  123,  123,  124,
215                 124,  125,  126,  126,  127,  127,  128,  128,
216                 129,  129,  130,  130,  131,  131,  132,  132,
217                 133,  133,  134,  134,  135,  135,  136,  136,
218                 137,  137,  138,  138,  139,  139,  140,  140,
219                 141,  141,  142,  142,  143,  143,  144,  144,
220                 145,  145,  145,  146,  146,  147,  147,  148,
221                 148,  149,  149,  150,  150,  150,  151,  151,
222                 152,  152,  153,  153,  153,  154,  154,  155,
223                 155,  156,  156,  156,  157,  157,  158,  158,
224                 158,  159,  159,  160,  160,  160,  161,  161,
225                 162,  162,  162,  163,  163,  164,  164,  164,
226                 165,  165,  166,  166,  166,  167,  167,  167,
227                 168,  168,  169,  169,  169,  170,  170,  170,
228                 171,  171,  172,  172,  172,  173,  173,  173,
229                 174,  174,  174,  175,  175,  176,  176,  176,
230                 177,  177,  177,  178,  178,  178,  179,  179,
231                 179,  180,  180,  180,  181,  181,  182,  182,
232                 182,  183,  183,  183,  184,  184,  184,  185,
233                 185,  185,  186,  186,  186,  187,  187,  187,
234                 188,  188,  188,  189,  189,  189,  189,  190,
235                 190,  190,  191,  191,  191,  192,  192,  192,
236                 193,  193,  193,  194,  194,  194,  195,  195,
237                 195,  196,  196,  196,  196,  197,  197,  197,
238                 198,  198,  198,  199,  199,  199,  200,  200,
239                 200,  200,  201,  201,  201,  202,  202,  202,
240                 202,  203,  203,  203,  204,  204,  204,  205,
241                 205,  205,  205,  206,  206,  206,  207,  207,
242                 207,  207,  208,  208,  208,  209,  209,  209,
243                 209,  210,  210,  210,  211,  211,  211,  211,
244                 212,  212,  212,  213,  213,  213,  213,  214,
245                 214,  214,  214,  215,  215,  215,  216,  216,
246                 216,  216,  217,  217,  217,  217,  218,  218,
247                 218,  219,  219,  219,  219,  220,  220,  220,
248                 220,  221,  221,  221,  221,  222,  222,  222,
249                 223,  223,  223,  223,  224,  224,  224,  224,
250                 225,  225,  225,  225,  226,  226,  226,  226,
251                 227,  227,  227,  227,  228,  228,  228,  228,
252                 229,  229,  229,  229,  230,  230,  230,  230,
253                 231,  231,  231,  231,  232,  232,  232,  232,
254                 233,  233,  233,  233,  234,  234,  234,  234,
255                 235,  235,  235,  235,  236,  236,  236,  236,
256                 237,  237,  237,  237,  238,  238,  238,  238,
257                 239,  239,  239,  239,  240,  240,  240,  240,
258                 240,  241,  241,  241,  241,  242,  242,  242,
259                 242,  243,  243,  243,  243,  244,  244,  244,
260                 244,  244,  245,  245,  245,  245,  246,  246,
261                 246,  246,  247,  247,  247,  247,  247,  248,
262                 248,  248,  248,  249,  249,  249,  249,  249,
263                 250,  250,  250,  250,  251,  251,  251,  251,
264                 251,  252,  252,  252,  252,  253,  253,  253,
265                 253,  253,  254,  254,  254,  254,  255,  255,
266         },
267 };
268 #endif
269
270 void tegra_dc_clk_enable(struct tegra_dc *dc)
271 {
272         if (!tegra_is_clk_enabled(dc->clk)) {
273                 clk_prepare_enable(dc->clk);
274                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
275         }
276 }
277
278 void tegra_dc_clk_disable(struct tegra_dc *dc)
279 {
280         if (tegra_is_clk_enabled(dc->clk)) {
281                 clk_disable_unprepare(dc->clk);
282                 tegra_dvfs_set_rate(dc->clk, 0);
283         }
284 }
285
286 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
287 {
288         if (dc->out_ops->hold)
289                 dc->out_ops->hold(dc);
290 }
291
292 void tegra_dc_release_dc_out(struct tegra_dc *dc)
293 {
294         if (dc->out_ops->release)
295                 dc->out_ops->release(dc);
296 }
297
298 #define DUMP_REG(a) do {                        \
299         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
300                  #a, a, tegra_dc_readl(dc, a));               \
301         print(data, buff);                                    \
302         } while (0)
303
304 static void _dump_regs(struct tegra_dc *dc, void *data,
305                        void (* print)(void *data, const char *str))
306 {
307         int i;
308         char buff[256];
309
310         mutex_lock(&dc->lock);
311         tegra_dc_io_start(dc);
312         tegra_dc_hold_dc_out(dc);
313
314         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
315         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
316         DUMP_REG(DC_CMD_SIGNAL_RAISE);
317         DUMP_REG(DC_CMD_INT_STATUS);
318         DUMP_REG(DC_CMD_INT_MASK);
319         DUMP_REG(DC_CMD_INT_ENABLE);
320         DUMP_REG(DC_CMD_INT_TYPE);
321         DUMP_REG(DC_CMD_INT_POLARITY);
322         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
323         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
324         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
325         DUMP_REG(DC_CMD_STATE_ACCESS);
326         DUMP_REG(DC_CMD_STATE_CONTROL);
327         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
328         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
329
330         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
331         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
332         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
333         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
334         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
335         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
336         DUMP_REG(DC_DISP_REF_TO_SYNC);
337         DUMP_REG(DC_DISP_SYNC_WIDTH);
338         DUMP_REG(DC_DISP_BACK_PORCH);
339         DUMP_REG(DC_DISP_DISP_ACTIVE);
340         DUMP_REG(DC_DISP_FRONT_PORCH);
341         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
342         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
343         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
344         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
345         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
346         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
347         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
348         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
349         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
350         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
351         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
352         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
353         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
354         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
355         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
356         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
357         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
358         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
359         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
360         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
361         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
362         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
363         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
364         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
365         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
366         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
367         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
368         DUMP_REG(DC_DISP_M0_CONTROL);
369         DUMP_REG(DC_DISP_M1_CONTROL);
370         DUMP_REG(DC_DISP_DI_CONTROL);
371         DUMP_REG(DC_DISP_PP_CONTROL);
372         DUMP_REG(DC_DISP_PP_SELECT_A);
373         DUMP_REG(DC_DISP_PP_SELECT_B);
374         DUMP_REG(DC_DISP_PP_SELECT_C);
375         DUMP_REG(DC_DISP_PP_SELECT_D);
376         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
377         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
378         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
379         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
380         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
381         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
382         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
383         DUMP_REG(DC_DISP_BORDER_COLOR);
384         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
385         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
386         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
387         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
388         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
389         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
390         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
391         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
392         DUMP_REG(DC_DISP_CURSOR_POSITION);
393         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
394         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
395         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
396         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
397         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
398         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
399         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
400         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
401         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
402         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
403 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
404         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
405 #endif
406         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
407         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
408
409
410         for (i = 0; i < 3; i++) {
411                 print(data, "\n");
412                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", 'A' + i);
413                 print(data, buff);
414
415                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
416                                 DC_CMD_DISPLAY_WINDOW_HEADER);
417                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
418                 DUMP_REG(DC_WIN_WIN_OPTIONS);
419                 DUMP_REG(DC_WIN_BYTE_SWAP);
420                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
421                 DUMP_REG(DC_WIN_COLOR_DEPTH);
422                 DUMP_REG(DC_WIN_POSITION);
423                 DUMP_REG(DC_WIN_SIZE);
424                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
425                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
426                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
427                 DUMP_REG(DC_WIN_DDA_INCREMENT);
428                 DUMP_REG(DC_WIN_LINE_STRIDE);
429 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
430                 DUMP_REG(DC_WIN_BUF_STRIDE);
431                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
432 #endif
433                 DUMP_REG(DC_WIN_BLEND_NOKEY);
434                 DUMP_REG(DC_WIN_BLEND_1WIN);
435                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
436                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
437                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
438                 DUMP_REG(DC_WINBUF_START_ADDR);
439                 DUMP_REG(DC_WINBUF_START_ADDR_U);
440                 DUMP_REG(DC_WINBUF_START_ADDR_V);
441                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
442                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
443                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
444                 DUMP_REG(DC_WIN_CSC_YOF);
445                 DUMP_REG(DC_WIN_CSC_KYRGB);
446                 DUMP_REG(DC_WIN_CSC_KUR);
447                 DUMP_REG(DC_WIN_CSC_KVR);
448                 DUMP_REG(DC_WIN_CSC_KUG);
449                 DUMP_REG(DC_WIN_CSC_KVG);
450                 DUMP_REG(DC_WIN_CSC_KUB);
451                 DUMP_REG(DC_WIN_CSC_KVB);
452         }
453
454         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
455         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
456         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
457         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
458         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
459         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
460         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
461         DUMP_REG(DC_DISP_M1_CONTROL);
462         DUMP_REG(DC_COM_PM1_CONTROL);
463         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
464         DUMP_REG(DC_DISP_SD_CONTROL);
465
466         tegra_dc_release_dc_out(dc);
467         tegra_dc_io_end(dc);
468         mutex_unlock(&dc->lock);
469 }
470
471 #undef DUMP_REG
472
473 #ifdef DEBUG
474 static void dump_regs_print(void *data, const char *str)
475 {
476         struct tegra_dc *dc = data;
477         dev_dbg(&dc->ndev->dev, "%s", str);
478 }
479
480 static void dump_regs(struct tegra_dc *dc)
481 {
482         _dump_regs(dc, dc, dump_regs_print);
483 }
484 #else /* !DEBUG */
485
486 static void dump_regs(struct tegra_dc *dc) {}
487
488 #endif /* DEBUG */
489
490 #ifdef CONFIG_DEBUG_FS
491
492 static void dbg_regs_print(void *data, const char *str)
493 {
494         struct seq_file *s = data;
495
496         seq_printf(s, "%s", str);
497 }
498
499 #undef DUMP_REG
500
501 static int dbg_dc_show(struct seq_file *s, void *unused)
502 {
503         struct tegra_dc *dc = s->private;
504
505         _dump_regs(dc, s, dbg_regs_print);
506
507         return 0;
508 }
509
510
511 static int dbg_dc_open(struct inode *inode, struct file *file)
512 {
513         return single_open(file, dbg_dc_show, inode->i_private);
514 }
515
516 static const struct file_operations regs_fops = {
517         .open           = dbg_dc_open,
518         .read           = seq_read,
519         .llseek         = seq_lseek,
520         .release        = single_release,
521 };
522
523 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
524 {
525         struct tegra_dc *dc = s->private;
526         struct tegra_dc_mode *m;
527
528         mutex_lock(&dc->lock);
529         m = &dc->mode;
530         seq_printf(s,
531                 "pclk: %d\n"
532                 "h_ref_to_sync: %d\n"
533                 "v_ref_to_sync: %d\n"
534                 "h_sync_width: %d\n"
535                 "v_sync_width: %d\n"
536                 "h_back_porch: %d\n"
537                 "v_back_porch: %d\n"
538                 "h_active: %d\n"
539                 "v_active: %d\n"
540                 "h_front_porch: %d\n"
541                 "v_front_porch: %d\n"
542                 "stereo_mode: %d\n",
543                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
544                 m->h_sync_width, m->v_sync_width,
545                 m->h_back_porch, m->v_back_porch,
546                 m->h_active, m->v_active,
547                 m->h_front_porch, m->v_front_porch,
548                 m->stereo_mode);
549         mutex_unlock(&dc->lock);
550         return 0;
551 }
552
553 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
554 {
555         return single_open(file, dbg_dc_mode_show, inode->i_private);
556 }
557
558 static const struct file_operations mode_fops = {
559         .open           = dbg_dc_mode_open,
560         .read           = seq_read,
561         .llseek         = seq_lseek,
562         .release        = single_release,
563 };
564
565 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
566 {
567         struct tegra_dc *dc = s->private;
568
569         mutex_lock(&dc->lock);
570         seq_printf(s,
571                 "underflows: %llu\n"
572                 "underflows_a: %llu\n"
573                 "underflows_b: %llu\n"
574                 "underflows_c: %llu\n",
575                 dc->stats.underflows,
576                 dc->stats.underflows_a,
577                 dc->stats.underflows_b,
578                 dc->stats.underflows_c);
579         mutex_unlock(&dc->lock);
580
581         return 0;
582 }
583
584 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
585 {
586         return single_open(file, dbg_dc_stats_show, inode->i_private);
587 }
588
589 static const struct file_operations stats_fops = {
590         .open           = dbg_dc_stats_open,
591         .read           = seq_read,
592         .llseek         = seq_lseek,
593         .release        = single_release,
594 };
595
596 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
597 {
598         if (dc->debugdir)
599                 debugfs_remove_recursive(dc->debugdir);
600         dc->debugdir = NULL;
601 }
602
603 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
604 {
605         struct dentry *retval;
606
607         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
608         if (!dc->debugdir)
609                 goto remove_out;
610
611         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
612                 &regs_fops);
613         if (!retval)
614                 goto remove_out;
615
616         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
617                 &mode_fops);
618         if (!retval)
619                 goto remove_out;
620
621         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
622                 &stats_fops);
623         if (!retval)
624                 goto remove_out;
625
626         return;
627 remove_out:
628         dev_err(&dc->ndev->dev, "could not create debugfs\n");
629         tegra_dc_remove_debugfs(dc);
630 }
631
632 #else /* !CONFIG_DEBUGFS */
633 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
634 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
635 #endif /* CONFIG_DEBUGFS */
636
637 static int tegra_dc_set(struct tegra_dc *dc, int index)
638 {
639         int ret = 0;
640
641         mutex_lock(&tegra_dc_lock);
642         if (index >= TEGRA_MAX_DC) {
643                 ret = -EINVAL;
644                 goto out;
645         }
646
647         if (dc != NULL && tegra_dcs[index] != NULL) {
648                 ret = -EBUSY;
649                 goto out;
650         }
651
652         tegra_dcs[index] = dc;
653
654 out:
655         mutex_unlock(&tegra_dc_lock);
656
657         return ret;
658 }
659
660 unsigned int tegra_dc_has_multiple_dc(void)
661 {
662         unsigned int idx;
663         unsigned int cnt = 0;
664         struct tegra_dc *dc;
665
666         mutex_lock(&tegra_dc_lock);
667         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
668                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
669         mutex_unlock(&tegra_dc_lock);
670
671         return (cnt > 1);
672 }
673
674 /* get the stride size of a window.
675  * return: stride size in bytes for window win. or 0 if unavailble. */
676 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
677 {
678         u32 stride;
679
680         if (!dc->enabled)
681                 return 0;
682         BUG_ON(win > DC_N_WINDOWS);
683         mutex_lock(&dc->lock);
684         tegra_dc_io_start(dc);
685         tegra_dc_hold_dc_out(dc);
686         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
687                 DC_CMD_DISPLAY_WINDOW_HEADER);
688         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
689         tegra_dc_release_dc_out(dc);
690         tegra_dc_io_end(dc);
691         mutex_unlock(&dc->lock);
692         return GET_LINE_STRIDE(stride);
693 }
694 EXPORT_SYMBOL(tegra_dc_get_stride);
695
696 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
697 {
698         if (idx < TEGRA_MAX_DC)
699                 return tegra_dcs[idx];
700         else
701                 return NULL;
702 }
703 EXPORT_SYMBOL(tegra_dc_get_dc);
704
705 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
706 {
707         if (win >= dc->n_windows)
708                 return NULL;
709
710         return &dc->windows[win];
711 }
712 EXPORT_SYMBOL(tegra_dc_get_window);
713
714 bool tegra_dc_get_connected(struct tegra_dc *dc)
715 {
716         return dc->connected;
717 }
718 EXPORT_SYMBOL(tegra_dc_get_connected);
719
720 bool tegra_dc_hpd(struct tegra_dc *dc)
721 {
722         int sense;
723         int level;
724
725         level = gpio_get_value(dc->out->hotplug_gpio);
726
727         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
728
729         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
730                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
731 }
732 EXPORT_SYMBOL(tegra_dc_hpd);
733
734 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
735 {
736         unsigned i;
737         unsigned v0 = 128;
738         unsigned v1 = 0;
739
740         /* linear horizontal and vertical filters */
741         for (i = 0; i < 16; i++) {
742                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
743                                 DC_WIN_H_FILTER_P(i));
744
745                 tegra_dc_writel(dc, v0,
746                                 DC_WIN_V_FILTER_P(i));
747                 v0 -= 8;
748                 v1 += 8;
749         }
750 }
751
752 #ifdef CONFIG_TEGRA_DC_CMU
753 static void tegra_dc_cache_cmu(struct tegra_dc_cmu *dst_cmu,
754                                         struct tegra_dc_cmu *src_cmu)
755 {
756         memcpy(dst_cmu, src_cmu, sizeof(struct tegra_dc_cmu));
757 }
758
759 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
760 {
761         u32 val;
762         u32 i;
763
764         for (i = 0; i < 256; i++) {
765                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
766                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
767         }
768
769         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
770         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
771         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
772         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
773         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
774         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
775         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
776         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
777         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
778
779         for (i = 0; i < 960; i++) {
780                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
781                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
782         }
783 }
784
785 void tegra_dc_get_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
786 {
787         u32 val;
788         u32 i;
789         bool flags;
790
791         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
792         if (val & CMU_ENABLE)
793                 flags = true;
794
795         val &= ~CMU_ENABLE;
796         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
797         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
798         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
799
800         /*TODO: Sync up with frame end */
801         mdelay(20);
802
803         for (i = 0; i < 256; i++) {
804                 val = LUT1_READ_EN | LUT1_READ_ADDR(i);
805                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1_READ);
806                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT1);
807                 cmu->lut1[i] = LUT1_READ_DATA(val);
808         }
809
810         cmu->csc.krr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRR);
811         cmu->csc.kgr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGR);
812         cmu->csc.kbr = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBR);
813         cmu->csc.krg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRG);
814         cmu->csc.kgg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGG);
815         cmu->csc.kbg = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBG);
816         cmu->csc.krb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KRB);
817         cmu->csc.kgb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KGB);
818         cmu->csc.kbb = tegra_dc_readl(dc, DC_COM_CMU_CSC_KBB);
819
820         for (i = 0; i < 960; i++) {
821                 val = LUT2_READ_EN | LUT2_READ_ADDR(i);
822                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2_READ);
823                 val = tegra_dc_readl(dc, DC_COM_CMU_LUT2);
824                 cmu->lut2[i] = LUT2_READ_DATA(val);
825         }
826 }
827 EXPORT_SYMBOL(tegra_dc_get_cmu);
828
829 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
830 {
831         u32 val;
832
833         if (dc->pdata->cmu_enable) {
834                 dc->pdata->flags |= TEGRA_DC_FLAG_CMU_ENABLE;
835         } else {
836                 dc->pdata->flags &= ~TEGRA_DC_FLAG_CMU_ENABLE;
837                 return 0;
838         }
839
840         if (cmu != &dc->cmu) {
841                 tegra_dc_cache_cmu(&dc->cmu, cmu);
842
843                 /* Disable CMU */
844                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
845                 if (val & CMU_ENABLE) {
846                         val &= ~CMU_ENABLE;
847                         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
848                         val = GENERAL_UPDATE;
849                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
850                         val = GENERAL_ACT_REQ;
851                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
852                         /*TODO: Sync up with vsync */
853                         mdelay(20);
854                 }
855
856                 tegra_dc_set_cmu(dc, &dc->cmu);
857         }
858
859         return 0;
860 }
861 EXPORT_SYMBOL(tegra_dc_update_cmu);
862
863 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
864 {
865         dc->pdata->cmu_enable = cmu_enable;
866         tegra_dc_update_cmu(dc, &dc->cmu);
867         tegra_dc_set_color_control(dc);
868 }
869 #else
870 #define tegra_dc_cache_cmu(dst_cmu, src_cmu)
871 #define tegra_dc_set_cmu(dc, cmu)
872 #define tegra_dc_update_cmu(dc, cmu)
873 #endif
874
875 /* disable_irq() blocks until handler completes, calling this function while
876  * holding dc->lock can deadlock. */
877 static inline void disable_dc_irq(const struct tegra_dc *dc)
878 {
879         disable_irq(dc->irq);
880 }
881
882 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
883 {
884         return dc->syncpt[i].id;
885 }
886 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
887
888 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
889 {
890         u32 max;
891
892         mutex_lock(&dc->lock);
893         tegra_dc_io_start(dc);
894         tegra_dc_hold_dc_out(dc);
895         max = nvhost_syncpt_incr_max_ext(dc->ndev,
896                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
897         dc->syncpt[i].max = max;
898         tegra_dc_release_dc_out(dc);
899         tegra_dc_io_end(dc);
900         mutex_unlock(&dc->lock);
901
902         return max;
903 }
904
905 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
906 {
907         mutex_lock(&dc->lock);
908         if (dc->enabled) {
909                 tegra_dc_io_start(dc);
910                 tegra_dc_hold_dc_out(dc);
911                 while (dc->syncpt[i].min < val) {
912                         dc->syncpt[i].min++;
913                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
914                 }
915                 tegra_dc_release_dc_out(dc);
916                 tegra_dc_io_end(dc);
917         }
918         mutex_unlock(&dc->lock);
919 }
920
921 void
922 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
923 {
924         unsigned int ctrl;
925         unsigned long out_sel;
926         unsigned long cmd_state;
927
928         mutex_lock(&dc->lock);
929         if (!dc->enabled) {
930                 mutex_unlock(&dc->lock);
931                 return;
932         }
933
934         tegra_dc_io_start(dc);
935         tegra_dc_hold_dc_out(dc);
936
937         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
938                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
939                 cfg->clk_select);
940
941         /* The new value should be effected immediately */
942         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
943         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
944
945         switch (cfg->which_pwm) {
946         case TEGRA_PWM_PM0:
947                 /* Select the LM0 on PM0 */
948                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
949                 out_sel &= ~(7 << 0);
950                 out_sel |= (3 << 0);
951                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
952                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
953                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
954                 break;
955         case TEGRA_PWM_PM1:
956                 /* Select the LM1 on PM1 */
957                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
958                 out_sel &= ~(7 << 4);
959                 out_sel |= (3 << 4);
960                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
961                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
962                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
963                 break;
964         default:
965                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
966                 break;
967         }
968         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
969         tegra_dc_release_dc_out(dc);
970         tegra_dc_io_end(dc);
971         mutex_unlock(&dc->lock);
972 }
973 EXPORT_SYMBOL(tegra_dc_config_pwm);
974
975 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
976                                 const struct tegra_dc_out_pin *pins,
977                                 const unsigned int n_pins)
978 {
979         unsigned int i;
980
981         int name;
982         int pol;
983
984         u32 pol1, pol3;
985
986         u32 set1, unset1;
987         u32 set3, unset3;
988
989         set1 = set3 = unset1 = unset3 = 0;
990
991         for (i = 0; i < n_pins; i++) {
992                 name = (pins + i)->name;
993                 pol  = (pins + i)->pol;
994
995                 /* set polarity by name */
996                 switch (name) {
997                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
998                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
999                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1000                         else
1001                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1002                         break;
1003                 case TEGRA_DC_OUT_PIN_H_SYNC:
1004                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1005                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1006                         else
1007                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1008                         break;
1009                 case TEGRA_DC_OUT_PIN_V_SYNC:
1010                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1011                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1012                         else
1013                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1014                         break;
1015                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1016                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1017                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1018                         else
1019                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1020                         break;
1021                 default:
1022                         printk("Invalid argument in function %s\n",
1023                                __FUNCTION__);
1024                         break;
1025                 }
1026         }
1027
1028         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1029         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1030
1031         pol1 |= set1;
1032         pol1 &= ~unset1;
1033
1034         pol3 |= set3;
1035         pol3 &= ~unset3;
1036
1037         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1038         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1039 }
1040
1041 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1042 {
1043         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1044                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1045                 dc->out->type == TEGRA_DC_OUT_DSI)
1046                 return override_disp_mode[dc->out->type].pclk ?
1047                         &override_disp_mode[dc->out->type] : NULL;
1048         else
1049                 return NULL;
1050 }
1051
1052 static void tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1053 {
1054         struct tegra_dc_mode *mode;
1055
1056         dc->out = out;
1057         mode = tegra_dc_get_override_mode(dc);
1058
1059         if (mode)
1060                 tegra_dc_set_mode(dc, mode);
1061         else if (out->n_modes > 0)
1062                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1063
1064         switch (out->type) {
1065         case TEGRA_DC_OUT_RGB:
1066                 dc->out_ops = &tegra_dc_rgb_ops;
1067                 break;
1068
1069         case TEGRA_DC_OUT_HDMI:
1070                 dc->out_ops = &tegra_dc_hdmi_ops;
1071                 break;
1072
1073         case TEGRA_DC_OUT_DSI:
1074                 dc->out_ops = &tegra_dc_dsi_ops;
1075                 break;
1076
1077         default:
1078                 dc->out_ops = NULL;
1079                 break;
1080         }
1081
1082         if (dc->out_ops && dc->out_ops->init)
1083                 dc->out_ops->init(dc);
1084
1085 }
1086
1087 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1088 {
1089         if (dc->out)
1090                 return dc->out->height;
1091         else
1092                 return 0;
1093 }
1094 EXPORT_SYMBOL(tegra_dc_get_out_height);
1095
1096 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1097 {
1098         if (dc->out)
1099                 return dc->out->width;
1100         else
1101                 return 0;
1102 }
1103 EXPORT_SYMBOL(tegra_dc_get_out_width);
1104
1105 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1106 {
1107         if (dc->out && dc->out->max_pixclock)
1108                 return dc->out->max_pixclock;
1109         else
1110                 return 0;
1111 }
1112 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1113
1114 void tegra_dc_enable_crc(struct tegra_dc *dc)
1115 {
1116         u32 val;
1117
1118         mutex_lock(&dc->lock);
1119         tegra_dc_io_start(dc);
1120         tegra_dc_hold_dc_out(dc);
1121
1122         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1123                 CRC_ENABLE_ENABLE;
1124         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1125         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1126         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1127         tegra_dc_release_dc_out(dc);
1128         tegra_dc_io_end(dc);
1129         mutex_unlock(&dc->lock);
1130 }
1131
1132 void tegra_dc_disable_crc(struct tegra_dc *dc)
1133 {
1134         mutex_lock(&dc->lock);
1135         tegra_dc_io_start(dc);
1136         tegra_dc_hold_dc_out(dc);
1137         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1138         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1139         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1140
1141         tegra_dc_release_dc_out(dc);
1142         tegra_dc_io_end(dc);
1143         mutex_unlock(&dc->lock);
1144 }
1145
1146 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1147 {
1148         int crc = 0;
1149
1150         if (!dc) {
1151                 pr_err("Failed to get dc: NULL parameter.\n");
1152                 goto crc_error;
1153         }
1154
1155 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1156         /* TODO: Replace mdelay with code to sync VBlANK, since
1157          * DC_COM_CRC_CHECKSUM_LATCHED is available after VBLANK */
1158         mdelay(TEGRA_CRC_LATCHED_DELAY);
1159 #endif
1160
1161         mutex_lock(&dc->lock);
1162         tegra_dc_io_start(dc);
1163         tegra_dc_hold_dc_out(dc);
1164         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1165         tegra_dc_release_dc_out(dc);
1166         tegra_dc_io_end(dc);
1167         mutex_unlock(&dc->lock);
1168 crc_error:
1169         return crc;
1170 }
1171
1172 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1173 {
1174 #ifndef CONFIG_TEGRA_SIMULATION_PLATFORM
1175         u32 val;
1176
1177         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1178         if (val & (WIN_A_ACT_REQ | WIN_B_ACT_REQ | WIN_C_ACT_REQ))
1179             return true;
1180 #endif
1181         return false;
1182 }
1183
1184 static inline void enable_dc_irq(const struct tegra_dc *dc)
1185 {
1186 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1187         enable_irq(dc->irq);
1188 #else
1189         /* Always disable DC interrupts on FPGA. */
1190         disable_irq(dc->irq);
1191 #endif
1192 }
1193
1194 void tegra_dc_get_fbvblank(struct tegra_dc *dc, struct fb_vblank *vblank)
1195 {
1196         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1197                 vblank->flags = FB_VBLANK_HAVE_VSYNC;
1198 }
1199
1200 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1201 {
1202         int ret = -ENOTTY;
1203
1204         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled)
1205                 return ret;
1206
1207         /*
1208          * Logic is as follows
1209          * a) Indicate we need a vblank.
1210          * b) Wait for completion to be signalled from isr.
1211          * c) Initialize completion for next iteration.
1212          */
1213
1214         tegra_dc_hold_dc_out(dc);
1215         dc->out->user_needs_vblank = true;
1216
1217         ret = wait_for_completion_interruptible(&dc->out->user_vblank_comp);
1218         init_completion(&dc->out->user_vblank_comp);
1219         tegra_dc_release_dc_out(dc);
1220
1221         return ret;
1222 }
1223
1224 static void tegra_dc_vblank(struct work_struct *work)
1225 {
1226         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1227         bool nvsd_updated = false;
1228
1229         mutex_lock(&dc->lock);
1230
1231         if (!dc->enabled) {
1232                 mutex_unlock(&dc->lock);
1233                 return;
1234         }
1235
1236         tegra_dc_io_start(dc);
1237         tegra_dc_hold_dc_out(dc);
1238         /* use the new frame's bandwidth setting instead of max(current, new),
1239          * skip this if we're using tegra_dc_one_shot_worker() */
1240         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
1241                 tegra_dc_program_bandwidth(dc, true);
1242
1243         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1244         if (!tegra_dc_windows_are_dirty(dc))
1245                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1246
1247         /* Update the SD brightness */
1248         if (dc->enabled && dc->out->sd_settings) {
1249                 nvsd_updated = nvsd_update_brightness(dc);
1250                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1251                  * V_BLANK_NVSD bit of vblank ref-count. */
1252                 if (nvsd_updated) {
1253                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1254                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1255                 } else {
1256                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1257                 }
1258         }
1259
1260         /* Mask vblank interrupt if ref-count is zero. */
1261         if (!dc->vblank_ref_count)
1262                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1263
1264         tegra_dc_release_dc_out(dc);
1265         tegra_dc_io_end(dc);
1266         mutex_unlock(&dc->lock);
1267
1268         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1269                 dc->out->sd_settings->bl_device_name) {
1270                 char *bl_device_name =
1271                         dc->out->sd_settings->bl_device_name;
1272                 dc->out->sd_settings->bl_device =
1273                         get_backlight_device_by_name(bl_device_name);
1274         }
1275
1276         /* Do the actual brightness update outside of the mutex */
1277         if (nvsd_updated && dc->out->sd_settings &&
1278             dc->out->sd_settings->bl_device) {
1279
1280                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1281                 backlight_update_status(bl);
1282         }
1283 }
1284
1285 static void tegra_dc_one_shot_worker(struct work_struct *work)
1286 {
1287         struct tegra_dc *dc = container_of(
1288                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1289         mutex_lock(&dc->lock);
1290
1291         /* memory client has gone idle */
1292         tegra_dc_clear_bandwidth(dc);
1293
1294         if (dc->out_ops->idle) {
1295                 tegra_dc_io_start(dc);
1296                 dc->out_ops->idle(dc);
1297                 tegra_dc_io_end(dc);
1298         }
1299
1300         mutex_unlock(&dc->lock);
1301 }
1302
1303 /* return an arbitrarily large number if count overflow occurs.
1304  * make it a nice base-10 number to show up in stats output */
1305 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1306 {
1307         unsigned count = tegra_dc_readl(dc, reg);
1308
1309         tegra_dc_writel(dc, 0, reg);
1310         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1311 }
1312
1313 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1314 {
1315         int i;
1316
1317         dc->stats.underflows++;
1318         if (dc->underflow_mask & WIN_A_UF_INT)
1319                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1320                         DC_WINBUF_AD_UFLOW_STATUS);
1321         if (dc->underflow_mask & WIN_B_UF_INT)
1322                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1323                         DC_WINBUF_BD_UFLOW_STATUS);
1324         if (dc->underflow_mask & WIN_C_UF_INT)
1325                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1326                         DC_WINBUF_CD_UFLOW_STATUS);
1327
1328         /* Check for any underflow reset conditions */
1329         for (i = 0; i < DC_N_WINDOWS; i++) {
1330                 if (dc->underflow_mask & (WIN_A_UF_INT << i)) {
1331                         dc->windows[i].underflows++;
1332
1333 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1334                         if (dc->windows[i].underflows > 4) {
1335                                 schedule_work(&dc->reset_work);
1336                                 /* reset counter */
1337                                 dc->windows[i].underflows = 0;
1338                                 trace_display_reset(dc);
1339                         }
1340 #endif
1341 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1342                         if (dc->windows[i].underflows > 4) {
1343                                 trace_display_reset(dc);
1344                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1345                                                 DC_DISP_DISP_MISC_CONTROL);
1346                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1347                                                 DC_CMD_STATE_CONTROL);
1348                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1349                                                 DC_CMD_STATE_CONTROL);
1350
1351                                 tegra_dc_writel(dc, 0,
1352                                                 DC_DISP_DISP_MISC_CONTROL);
1353                                 tegra_dc_writel(dc, GENERAL_UPDATE,
1354                                                 DC_CMD_STATE_CONTROL);
1355                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1356                                                 DC_CMD_STATE_CONTROL);
1357                         }
1358 #endif
1359                 } else {
1360                         dc->windows[i].underflows = 0;
1361                 }
1362         }
1363
1364         /* Clear the underflow mask now that we've checked it. */
1365         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1366         dc->underflow_mask = 0;
1367         tegra_dc_unmask_interrupt(dc, ALL_UF_INT);
1368         trace_underflow(dc);
1369 }
1370
1371 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1372 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status)
1373 {
1374         /* pending user vblank, so wakeup */
1375         if ((status & (V_BLANK_INT | MSF_INT)) &&
1376             (dc->out->user_needs_vblank)) {
1377                 dc->out->user_needs_vblank = false;
1378                 complete(&dc->out->user_vblank_comp);
1379         }
1380
1381         if (status & V_BLANK_INT) {
1382                 /* Sync up windows. */
1383                 tegra_dc_trigger_windows(dc);
1384
1385                 /* Schedule any additional bottom-half vblank actvities. */
1386                 queue_work(system_freezable_wq, &dc->vblank_work);
1387         }
1388
1389         if (status & FRAME_END_INT) {
1390                 /* Mark the frame_end as complete. */
1391                 if (!completion_done(&dc->frame_end_complete))
1392                         complete(&dc->frame_end_complete);
1393         }
1394 }
1395
1396 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status)
1397 {
1398         /* Schedule any additional bottom-half vblank actvities. */
1399         if (status & V_BLANK_INT)
1400                 queue_work(system_freezable_wq, &dc->vblank_work);
1401
1402         if (status & FRAME_END_INT) {
1403                 struct timespec tm = CURRENT_TIME;
1404                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1405                 wake_up(&dc->timestamp_wq);
1406
1407                 /* Mark the frame_end as complete. */
1408                 if (!completion_done(&dc->frame_end_complete))
1409                         complete(&dc->frame_end_complete);
1410
1411                 tegra_dc_trigger_windows(dc);
1412         }
1413 }
1414
1415 /* XXX: Not sure if we limit look ahead to 1 frame */
1416 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1417 {
1418         BUG_ON(!dc->frametime_ns);
1419         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1420 }
1421
1422 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
1423 {
1424         BUG_ON(!dc->frametime_ns);
1425         return (((new_ts - old_ts) > dc->frametime_ns)
1426                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
1427                         != div_s64((old_ts - dc->frame_end_timestamp),
1428                                 dc->frametime_ns)));
1429 }
1430 #endif
1431
1432 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
1433 {
1434 #ifndef CONFIG_TEGRA_FPGA_PLATFORM
1435         struct tegra_dc *dc = ptr;
1436         unsigned long status;
1437         unsigned long underflow_mask;
1438         u32 val;
1439
1440         mutex_lock(&dc->lock);
1441         clk_enable(dc->clk);
1442         tegra_dc_io_start(dc);
1443         tegra_dc_hold_dc_out(dc);
1444
1445         if (!nvhost_module_powered_ext(nvhost_get_parent(dc->ndev))) {
1446                 WARN(1, "IRQ when DC not powered!\n");
1447                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1448                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
1449                 tegra_dc_release_dc_out(dc);
1450                 tegra_dc_io_end(dc);
1451                 clk_disable(dc->clk);
1452                 mutex_unlock(&dc->lock);
1453                 return IRQ_HANDLED;
1454         }
1455
1456         /* clear all status flags except underflow, save those for the worker */
1457         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
1458         tegra_dc_writel(dc, status & ~ALL_UF_INT, DC_CMD_INT_STATUS);
1459         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
1460         tegra_dc_writel(dc, val & ~ALL_UF_INT, DC_CMD_INT_MASK);
1461
1462         /*
1463          * Overlays can get thier internal state corrupted during and underflow
1464          * condition.  The only way to fix this state is to reset the DC.
1465          * if we get 4 consecutive frames with underflows, assume we're
1466          * hosed and reset.
1467          */
1468         underflow_mask = status & ALL_UF_INT;
1469
1470         /* Check underflow */
1471         if (underflow_mask) {
1472                 dc->underflow_mask |= underflow_mask;
1473                 schedule_delayed_work(&dc->underflow_work,
1474                         msecs_to_jiffies(1));
1475         }
1476
1477         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1478                 tegra_dc_one_shot_irq(dc, status);
1479         else
1480                 tegra_dc_continuous_irq(dc, status);
1481
1482         tegra_dc_release_dc_out(dc);
1483         tegra_dc_io_end(dc);
1484         clk_disable(dc->clk);
1485         mutex_unlock(&dc->lock);
1486
1487         return IRQ_HANDLED;
1488 #else /* CONFIG_TEGRA_FPGA_PLATFORM */
1489         return IRQ_NONE;
1490 #endif /* !CONFIG_TEGRA_FPGA_PLATFORM */
1491 }
1492
1493 void tegra_dc_set_color_control(struct tegra_dc *dc)
1494 {
1495         u32 color_control;
1496
1497         switch (dc->out->depth) {
1498         case 3:
1499                 color_control = BASE_COLOR_SIZE111;
1500                 break;
1501
1502         case 6:
1503                 color_control = BASE_COLOR_SIZE222;
1504                 break;
1505
1506         case 8:
1507                 color_control = BASE_COLOR_SIZE332;
1508                 break;
1509
1510         case 9:
1511                 color_control = BASE_COLOR_SIZE333;
1512                 break;
1513
1514         case 12:
1515                 color_control = BASE_COLOR_SIZE444;
1516                 break;
1517
1518         case 15:
1519                 color_control = BASE_COLOR_SIZE555;
1520                 break;
1521
1522         case 16:
1523                 color_control = BASE_COLOR_SIZE565;
1524                 break;
1525
1526         case 18:
1527                 color_control = BASE_COLOR_SIZE666;
1528                 break;
1529
1530         default:
1531                 color_control = BASE_COLOR_SIZE888;
1532                 break;
1533         }
1534
1535         switch (dc->out->dither) {
1536         case TEGRA_DC_DISABLE_DITHER:
1537                 color_control |= DITHER_CONTROL_DISABLE;
1538                 break;
1539         case TEGRA_DC_ORDERED_DITHER:
1540                 color_control |= DITHER_CONTROL_ORDERED;
1541                 break;
1542         case TEGRA_DC_ERRDIFF_DITHER:
1543                 /* The line buffer for error-diffusion dither is limited
1544                  * to 1280 pixels per line. This limits the maximum
1545                  * horizontal active area size to 1280 pixels when error
1546                  * diffusion is enabled.
1547                  */
1548                 BUG_ON(dc->mode.h_active > 1280);
1549                 color_control |= DITHER_CONTROL_ERRDIFF;
1550                 break;
1551         }
1552
1553 #ifdef CONFIG_TEGRA_DC_CMU
1554         if (dc->pdata->flags & TEGRA_DC_FLAG_CMU_ENABLE)
1555                 color_control |= CMU_ENABLE;
1556 #endif
1557
1558         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
1559 }
1560
1561 static u32 get_syncpt(struct tegra_dc *dc, int idx)
1562 {
1563         u32 syncpt_id;
1564
1565         switch (dc->ndev->id) {
1566         case 0:
1567                 switch (idx) {
1568                 case 0:
1569                         syncpt_id = NVSYNCPT_DISP0_A;
1570                         break;
1571                 case 1:
1572                         syncpt_id = NVSYNCPT_DISP0_B;
1573                         break;
1574                 case 2:
1575                         syncpt_id = NVSYNCPT_DISP0_C;
1576                         break;
1577                 default:
1578                         BUG();
1579                         break;
1580                 }
1581                 break;
1582         case 1:
1583                 switch (idx) {
1584                 case 0:
1585                         syncpt_id = NVSYNCPT_DISP1_A;
1586                         break;
1587                 case 1:
1588                         syncpt_id = NVSYNCPT_DISP1_B;
1589                         break;
1590                 case 2:
1591                         syncpt_id = NVSYNCPT_DISP1_C;
1592                         break;
1593                 default:
1594                         BUG();
1595                         break;
1596                 }
1597                 break;
1598         default:
1599                 BUG();
1600                 break;
1601         }
1602
1603         return syncpt_id;
1604 }
1605
1606 static int tegra_dc_init(struct tegra_dc *dc)
1607 {
1608         int i;
1609         int int_enable;
1610
1611         tegra_dc_io_start(dc);
1612         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1613         if (dc->ndev->id == 0) {
1614                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
1615                                       TEGRA_MC_PRIO_MED);
1616                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
1617                                       TEGRA_MC_PRIO_MED);
1618                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
1619                                       TEGRA_MC_PRIO_MED);
1620 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1621                 /* only present on Tegra2 and 3 */
1622                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
1623                                       TEGRA_MC_PRIO_MED);
1624 #endif
1625                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
1626                                       TEGRA_MC_PRIO_HIGH);
1627         } else if (dc->ndev->id == 1) {
1628                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
1629                                       TEGRA_MC_PRIO_MED);
1630                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
1631                                       TEGRA_MC_PRIO_MED);
1632                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
1633                                       TEGRA_MC_PRIO_MED);
1634 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
1635                 /* only present on Tegra2 and 3 */
1636                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
1637                                       TEGRA_MC_PRIO_MED);
1638 #endif
1639                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
1640                                       TEGRA_MC_PRIO_HIGH);
1641         }
1642         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
1643                         DC_CMD_CONT_SYNCPT_VSYNC);
1644         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
1645         tegra_dc_writel(dc, 0x0001c700, DC_CMD_INT_POLARITY);
1646         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
1647         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
1648 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1649         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
1650 #endif
1651         /* enable interrupts for vblank, frame_end and underflows */
1652         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT);
1653         /* for panels with one-shot mode enable tearing effect interrupt */
1654         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1655                 int_enable |= MSF_INT;
1656
1657         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
1658         tegra_dc_writel(dc, ALL_UF_INT, DC_CMD_INT_MASK);
1659
1660         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
1661
1662 #ifdef CONFIG_TEGRA_DC_CMU
1663         if (dc->pdata->cmu)
1664                 tegra_dc_update_cmu(dc, dc->pdata->cmu);
1665         else
1666                 tegra_dc_update_cmu(dc, &default_cmu);
1667 #endif
1668
1669         tegra_dc_set_color_control(dc);
1670         for (i = 0; i < DC_N_WINDOWS; i++) {
1671                 struct tegra_dc_win *win = &dc->windows[i];
1672                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
1673                                 DC_CMD_DISPLAY_WINDOW_HEADER);
1674                 tegra_dc_set_csc(dc, &win->csc);
1675                 tegra_dc_set_lut(dc, win);
1676                 tegra_dc_set_scaling_filter(dc);
1677         }
1678
1679         for (i = 0; i < dc->n_windows; i++) {
1680                 u32 syncpt = get_syncpt(dc, i);
1681
1682                 dc->syncpt[i].id = syncpt;
1683
1684                 dc->syncpt[i].min = dc->syncpt[i].max =
1685                         nvhost_syncpt_read_ext(dc->ndev, syncpt);
1686         }
1687
1688         trace_display_mode(dc, &dc->mode);
1689
1690         if (dc->mode.pclk) {
1691                 if (tegra_dc_program_mode(dc, &dc->mode)) {
1692                         tegra_dc_io_end(dc);
1693                         return -EINVAL;
1694                 }
1695         }
1696
1697         /* Initialize SD AFTER the modeset.
1698            nvsd_init handles the sd_settings = NULL case. */
1699         nvsd_init(dc, dc->out->sd_settings);
1700
1701         tegra_dc_io_end(dc);
1702
1703         return 0;
1704 }
1705
1706 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
1707 {
1708         int failed_init = 0;
1709
1710         if (dc->out->enable)
1711                 dc->out->enable(&dc->ndev->dev);
1712
1713         tegra_dc_setup_clk(dc, dc->clk);
1714         tegra_dc_clk_enable(dc);
1715         tegra_dc_io_start(dc);
1716
1717         tegra_dc_power_on(dc);
1718
1719         /* do not accept interrupts during initialization */
1720         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1721
1722         enable_dc_irq(dc);
1723
1724         failed_init = tegra_dc_init(dc);
1725         if (failed_init) {
1726                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1727                 disable_irq_nosync(dc->irq);
1728                 tegra_dc_clear_bandwidth(dc);
1729                 tegra_dc_clk_disable(dc);
1730                 if (dc->out && dc->out->disable)
1731                         dc->out->disable();
1732                 tegra_dc_io_end(dc);
1733                 return false;
1734         }
1735
1736         if (dc->out_ops && dc->out_ops->enable)
1737                 dc->out_ops->enable(dc);
1738
1739         /* force a full blending update */
1740         dc->blend.z[0] = -1;
1741
1742         tegra_dc_ext_enable(dc->ext);
1743
1744         trace_display_enable(dc);
1745
1746         tegra_dc_writel(dc, GENERAL_UPDATE, DC_CMD_STATE_CONTROL);
1747         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1748
1749         if (dc->out->postpoweron)
1750                 dc->out->postpoweron();
1751
1752         tegra_dc_io_end(dc);
1753         return true;
1754 }
1755
1756 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1757 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
1758 {
1759         bool ret = true;
1760
1761         if (dc->out->enable)
1762                 dc->out->enable(&dc->ndev->dev);
1763
1764         tegra_dc_setup_clk(dc, dc->clk);
1765         tegra_dc_clk_enable(dc);
1766
1767         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1768                 mutex_lock(&tegra_dcs[1]->lock);
1769                 disable_irq_nosync(tegra_dcs[1]->irq);
1770         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1771                 mutex_lock(&tegra_dcs[0]->lock);
1772                 disable_irq_nosync(tegra_dcs[0]->irq);
1773         }
1774
1775         msleep(5);
1776         tegra_periph_reset_assert(dc->clk);
1777         msleep(2);
1778 #ifdef CONFIG_TEGRA_SILICON_PLATFORM
1779         tegra_periph_reset_deassert(dc->clk);
1780         msleep(1);
1781 #endif
1782
1783         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
1784                 enable_dc_irq(tegra_dcs[1]);
1785                 mutex_unlock(&tegra_dcs[1]->lock);
1786         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
1787                 enable_dc_irq(tegra_dcs[0]);
1788                 mutex_unlock(&tegra_dcs[0]->lock);
1789         }
1790
1791         enable_dc_irq(dc);
1792
1793         if (tegra_dc_init(dc)) {
1794                 dev_err(&dc->ndev->dev, "cannot initialize\n");
1795                 ret = false;
1796         }
1797
1798         if (dc->out_ops && dc->out_ops->enable)
1799                 dc->out_ops->enable(dc);
1800
1801         if (dc->out->postpoweron)
1802                 dc->out->postpoweron();
1803
1804         /* force a full blending update */
1805         dc->blend.z[0] = -1;
1806
1807         tegra_dc_ext_enable(dc->ext);
1808
1809         if (!ret) {
1810                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
1811                 _tegra_dc_controller_disable(dc);
1812         }
1813
1814         trace_display_reset(dc);
1815         return ret;
1816 }
1817 #endif
1818
1819 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
1820 {
1821         if (dc->mode.pclk == 0) {
1822                 switch (dc->out->type) {
1823                 case TEGRA_DC_OUT_HDMI:
1824                 /* DC enable called but no videomode is loaded.
1825                      Check if HDMI is connected, then set fallback mdoe */
1826                 if (tegra_dc_hpd(dc)) {
1827                         return tegra_dc_set_fb_mode(dc,
1828                                         &tegra_dc_hdmi_fallback_mode, 0);
1829                 } else
1830                         return false;
1831
1832                 break;
1833
1834                 /* Do nothing for other outputs for now */
1835                 case TEGRA_DC_OUT_RGB:
1836
1837                 case TEGRA_DC_OUT_DSI:
1838
1839                 default:
1840                         return false;
1841                 }
1842         }
1843
1844         return false;
1845 }
1846
1847 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
1848 {
1849         return _tegra_dc_set_default_videomode(dc);
1850 }
1851
1852 static bool _tegra_dc_enable(struct tegra_dc *dc)
1853 {
1854         if (dc->mode.pclk == 0)
1855                 return false;
1856
1857         if (!dc->out)
1858                 return false;
1859
1860         if (dc->enabled)
1861                 return true;
1862
1863         if (!_tegra_dc_controller_enable(dc))
1864                 return false;
1865
1866         return true;
1867 }
1868
1869 void tegra_dc_enable(struct tegra_dc *dc)
1870 {
1871         mutex_lock(&dc->lock);
1872
1873         if (!dc->enabled)
1874                 dc->enabled = _tegra_dc_enable(dc);
1875
1876         mutex_unlock(&dc->lock);
1877         trace_display_mode(dc, &dc->mode);
1878 }
1879
1880 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
1881 {
1882         unsigned i;
1883
1884         tegra_dc_hold_dc_out(dc);
1885
1886         if (dc->out && dc->out->prepoweroff)
1887                 dc->out->prepoweroff();
1888
1889         if (dc->out_ops && dc->out_ops->disable)
1890                 dc->out_ops->disable(dc);
1891
1892         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
1893
1894         disable_irq_nosync(dc->irq);
1895
1896         tegra_dc_clear_bandwidth(dc);
1897         if (dc->out_ops->release) /* ugly hack */
1898                 tegra_dc_release_dc_out(dc);
1899         else
1900                 tegra_dc_clk_disable(dc);
1901
1902         if (dc->out && dc->out->disable)
1903                 dc->out->disable();
1904
1905         for (i = 0; i < dc->n_windows; i++) {
1906                 struct tegra_dc_win *w = &dc->windows[i];
1907
1908                 /* reset window bandwidth */
1909                 w->bandwidth = 0;
1910                 w->new_bandwidth = 0;
1911
1912                 /* disable windows */
1913                 w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1914
1915                 /* flush any pending syncpt waits */
1916                 while (dc->syncpt[i].min < dc->syncpt[i].max) {
1917                         trace_display_syncpt_flush(dc, dc->syncpt[i].id,
1918                                 dc->syncpt[i].min, dc->syncpt[i].max);
1919                         dc->syncpt[i].min++;
1920                         nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1921                 }
1922         }
1923         trace_display_disable(dc);
1924 }
1925
1926 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
1927 {
1928 #if 0 /* underflow interrupt is already enabled by dc reset worker */
1929         u32 val;
1930         if (dc->enabled)  {
1931                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1932                 if (enable)
1933                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1934                 else
1935                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
1936                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
1937         }
1938 #endif
1939 }
1940
1941 bool tegra_dc_stats_get(struct tegra_dc *dc)
1942 {
1943 #if 0 /* right now it is always enabled */
1944         u32 val;
1945         bool res;
1946
1947         if (dc->enabled)  {
1948                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
1949                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
1950         } else {
1951                 res = false;
1952         }
1953
1954         return res;
1955 #endif
1956         return true;
1957 }
1958
1959 /* make the screen blank by disabling all windows */
1960 void tegra_dc_blank(struct tegra_dc *dc)
1961 {
1962         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
1963         unsigned i;
1964
1965         for (i = 0; i < DC_N_WINDOWS; i++) {
1966                 dcwins[i] = tegra_dc_get_window(dc, i);
1967                 dcwins[i]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
1968         }
1969
1970         tegra_dc_update_windows(dcwins, DC_N_WINDOWS);
1971         tegra_dc_sync_windows(dcwins, DC_N_WINDOWS);
1972 }
1973
1974 static void _tegra_dc_disable(struct tegra_dc *dc)
1975 {
1976         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
1977                 mutex_lock(&dc->one_shot_lock);
1978                 cancel_delayed_work_sync(&dc->one_shot_work);
1979         }
1980
1981         tegra_dc_io_start(dc);
1982         _tegra_dc_controller_disable(dc);
1983         tegra_dc_io_end(dc);
1984
1985         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
1986                 mutex_unlock(&dc->one_shot_lock);
1987 }
1988
1989 void tegra_dc_disable(struct tegra_dc *dc)
1990 {
1991         tegra_dc_ext_disable(dc->ext);
1992
1993         /* it's important that new underflow work isn't scheduled before the
1994          * lock is acquired. */
1995         cancel_delayed_work_sync(&dc->underflow_work);
1996
1997         mutex_lock(&dc->lock);
1998
1999         if (dc->enabled) {
2000                 dc->enabled = false;
2001
2002                 if (!dc->suspended)
2003                         _tegra_dc_disable(dc);
2004         }
2005
2006 #ifdef CONFIG_SWITCH
2007         switch_set_state(&dc->modeset_switch, 0);
2008 #endif
2009
2010         mutex_unlock(&dc->lock);
2011         synchronize_irq(dc->irq);
2012         trace_display_mode(dc, &dc->mode);
2013 }
2014
2015 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2016 static void tegra_dc_reset_worker(struct work_struct *work)
2017 {
2018         struct tegra_dc *dc =
2019                 container_of(work, struct tegra_dc, reset_work);
2020
2021         unsigned long val = 0;
2022
2023         mutex_lock(&shared_lock);
2024
2025         dev_warn(&dc->ndev->dev,
2026                 "overlay stuck in underflow state.  resetting.\n");
2027
2028         tegra_dc_ext_disable(dc->ext);
2029
2030         mutex_lock(&dc->lock);
2031
2032         if (dc->enabled == false)
2033                 goto unlock;
2034
2035         dc->enabled = false;
2036
2037         /*
2038          * off host read bus
2039          */
2040         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2041         val &= ~(0x00000100);
2042         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2043
2044         /*
2045          * set DC to STOP mode
2046          */
2047         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2048
2049         msleep(10);
2050
2051         _tegra_dc_controller_disable(dc);
2052
2053         /* _tegra_dc_controller_reset_enable deasserts reset */
2054         _tegra_dc_controller_reset_enable(dc);
2055
2056         dc->enabled = true;
2057
2058         /* reopen host read bus */
2059         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2060         val &= ~(0x00000100);
2061         val |= 0x100;
2062         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2063
2064 unlock:
2065         mutex_unlock(&dc->lock);
2066         mutex_unlock(&shared_lock);
2067         trace_display_reset(dc);
2068 }
2069 #endif
2070
2071 static void tegra_dc_underflow_worker(struct work_struct *work)
2072 {
2073         struct tegra_dc *dc = container_of(
2074                 to_delayed_work(work), struct tegra_dc, underflow_work);
2075
2076         mutex_lock(&dc->lock);
2077         tegra_dc_io_start(dc);
2078         tegra_dc_hold_dc_out(dc);
2079
2080         if (dc->enabled) {
2081                 tegra_dc_underflow_handler(dc);
2082         }
2083         tegra_dc_release_dc_out(dc);
2084         tegra_dc_io_end(dc);
2085         mutex_unlock(&dc->lock);
2086 }
2087
2088 #ifdef CONFIG_SWITCH
2089 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2090 {
2091         struct tegra_dc *dc =
2092                 container_of(sdev, struct tegra_dc, modeset_switch);
2093
2094         if (!sdev->state)
2095                 return sprintf(buf, "offline\n");
2096
2097         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2098 }
2099 #endif
2100
2101 static int tegra_dc_probe(struct nvhost_device *ndev,
2102         struct nvhost_device_id *id_table)
2103 {
2104         struct tegra_dc *dc;
2105         struct tegra_dc_mode *mode;
2106         struct clk *clk;
2107         struct clk *emc_clk;
2108         struct resource *res;
2109         struct resource *base_res;
2110         struct resource *fb_mem = NULL;
2111         int ret = 0;
2112         void __iomem *base;
2113         int irq;
2114         int i;
2115
2116         if (!ndev->dev.platform_data) {
2117                 dev_err(&ndev->dev, "no platform data\n");
2118                 return -ENOENT;
2119         }
2120
2121         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2122         if (!dc) {
2123                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2124                 return -ENOMEM;
2125         }
2126
2127         irq = nvhost_get_irq_byname(ndev, "irq");
2128         if (irq <= 0) {
2129                 dev_err(&ndev->dev, "no irq\n");
2130                 ret = -ENOENT;
2131                 goto err_free;
2132         }
2133
2134         res = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "regs");
2135         if (!res) {
2136                 dev_err(&ndev->dev, "no mem resource\n");
2137                 ret = -ENOENT;
2138                 goto err_free;
2139         }
2140
2141         base_res = request_mem_region(res->start, resource_size(res),
2142                 ndev->name);
2143         if (!base_res) {
2144                 dev_err(&ndev->dev, "request_mem_region failed\n");
2145                 ret = -EBUSY;
2146                 goto err_free;
2147         }
2148
2149         base = ioremap(res->start, resource_size(res));
2150         if (!base) {
2151                 dev_err(&ndev->dev, "registers can't be mapped\n");
2152                 ret = -EBUSY;
2153                 goto err_release_resource_reg;
2154         }
2155
2156         fb_mem = nvhost_get_resource_byname(ndev, IORESOURCE_MEM, "fbmem");
2157
2158         clk = clk_get(&ndev->dev, NULL);
2159         if (IS_ERR_OR_NULL(clk)) {
2160                 dev_err(&ndev->dev, "can't get clock\n");
2161                 ret = -ENOENT;
2162                 goto err_iounmap_reg;
2163         }
2164
2165         emc_clk = clk_get(&ndev->dev, "emc");
2166         if (IS_ERR_OR_NULL(emc_clk)) {
2167                 dev_err(&ndev->dev, "can't get emc clock\n");
2168                 ret = -ENOENT;
2169                 goto err_put_clk;
2170         }
2171
2172         dc->clk = clk;
2173         dc->emc_clk = emc_clk;
2174         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
2175         /* Initialize one shot work delay, it will be assigned by dsi
2176          * according to refresh rate later. */
2177         dc->one_shot_delay_ms = 40;
2178
2179         dc->base_res = base_res;
2180         dc->base = base;
2181         dc->irq = irq;
2182         dc->ndev = ndev;
2183         dc->pdata = ndev->dev.platform_data;
2184
2185         /*
2186          * The emc is a shared clock, it will be set based on
2187          * the requirements for each user on the bus.
2188          */
2189         dc->emc_clk_rate = 0;
2190
2191         mutex_init(&dc->lock);
2192         mutex_init(&dc->one_shot_lock);
2193         init_completion(&dc->frame_end_complete);
2194         init_waitqueue_head(&dc->wq);
2195         init_waitqueue_head(&dc->timestamp_wq);
2196 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2197         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
2198 #endif
2199         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
2200         dc->vblank_ref_count = 0;
2201         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
2202         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
2203
2204         tegra_dc_init_lut_defaults(&dc->fb_lut);
2205
2206         dc->n_windows = DC_N_WINDOWS;
2207         for (i = 0; i < dc->n_windows; i++) {
2208                 struct tegra_dc_win *win = &dc->windows[i];
2209                 win->idx = i;
2210                 win->dc = dc;
2211                 tegra_dc_init_csc_defaults(&win->csc);
2212                 tegra_dc_init_lut_defaults(&win->lut);
2213         }
2214
2215         ret = tegra_dc_set(dc, ndev->id);
2216         if (ret < 0) {
2217                 dev_err(&ndev->dev, "can't add dc\n");
2218                 goto err_free_irq;
2219         }
2220
2221         nvhost_set_drvdata(ndev, dc);
2222
2223 #ifdef CONFIG_SWITCH
2224         dc->modeset_switch.name = dev_name(&ndev->dev);
2225         dc->modeset_switch.state = 0;
2226         dc->modeset_switch.print_state = switch_modeset_print_mode;
2227         ret = switch_dev_register(&dc->modeset_switch);
2228         if (ret < 0)
2229                 dev_err(&ndev->dev, "failed to register switch driver\n");
2230 #endif
2231
2232         tegra_dc_feature_register(dc);
2233
2234         if (dc->pdata->default_out)
2235                 tegra_dc_set_out(dc, dc->pdata->default_out);
2236         else
2237                 dev_err(&ndev->dev, "No default output specified.  Leaving output disabled.\n");
2238
2239         dc->vblank_syncpt = (dc->ndev->id == 0) ?
2240                 NVSYNCPT_VBLANK0 : NVSYNCPT_VBLANK1;
2241
2242         dc->ext = tegra_dc_ext_register(ndev, dc);
2243         if (IS_ERR_OR_NULL(dc->ext)) {
2244                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
2245                 dc->ext = NULL;
2246         }
2247
2248         /* interrupt handler must be registered before tegra_fb_register() */
2249         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
2250                         dev_name(&ndev->dev), dc)) {
2251                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
2252                 ret = -EBUSY;
2253                 goto err_put_emc_clk;
2254         }
2255         disable_dc_irq(dc);
2256
2257         mutex_lock(&dc->lock);
2258         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2259                 _tegra_dc_set_default_videomode(dc);
2260                 dc->enabled = _tegra_dc_enable(dc);
2261         }
2262         mutex_unlock(&dc->lock);
2263
2264         mutex_lock(&dc->lock);
2265         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
2266                 _tegra_dc_set_default_videomode(dc);
2267                 dc->enabled = _tegra_dc_enable(dc);
2268         }
2269         mutex_unlock(&dc->lock);
2270
2271         tegra_dc_create_debugfs(dc);
2272
2273         dev_info(&ndev->dev, "probed\n");
2274
2275         if (dc->pdata->fb) {
2276                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
2277                         unsigned long fmt;
2278                         tegra_dc_writel(dc,
2279                                         WINDOW_A_SELECT << dc->pdata->fb->win,
2280                                         DC_CMD_DISPLAY_WINDOW_HEADER);
2281
2282                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
2283                         dc->pdata->fb->bits_per_pixel =
2284                                 tegra_dc_fmt_bpp(fmt);
2285                 }
2286
2287                 mode = tegra_dc_get_override_mode(dc);
2288                 if (mode) {
2289                         dc->pdata->fb->xres = mode->h_active;
2290                         dc->pdata->fb->yres = mode->v_active;
2291                 }
2292
2293                 tegra_dc_io_start(dc);
2294                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
2295                 if (IS_ERR_OR_NULL(dc->fb))
2296                         dc->fb = NULL;
2297                 tegra_dc_io_end(dc);
2298         }
2299
2300         if (dc->out && dc->out->hotplug_init)
2301                 dc->out->hotplug_init(&ndev->dev);
2302
2303         if (dc->out_ops && dc->out_ops->detect)
2304                 dc->out_ops->detect(dc);
2305         else
2306                 dc->connected = true;
2307
2308         tegra_dc_create_sysfs(&dc->ndev->dev);
2309
2310         return 0;
2311
2312 err_free_irq:
2313         free_irq(irq, dc);
2314 err_put_emc_clk:
2315         clk_put(emc_clk);
2316 err_put_clk:
2317         clk_put(clk);
2318 err_iounmap_reg:
2319         iounmap(base);
2320         if (fb_mem)
2321                 release_resource(fb_mem);
2322 err_release_resource_reg:
2323         release_resource(base_res);
2324 err_free:
2325         kfree(dc);
2326
2327         return ret;
2328 }
2329
2330 static int tegra_dc_remove(struct nvhost_device *ndev)
2331 {
2332         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2333
2334         tegra_dc_remove_sysfs(&dc->ndev->dev);
2335         tegra_dc_remove_debugfs(dc);
2336
2337         if (dc->fb) {
2338                 tegra_fb_unregister(dc->fb);
2339                 if (dc->fb_mem)
2340                         release_resource(dc->fb_mem);
2341         }
2342
2343         tegra_dc_ext_disable(dc->ext);
2344
2345         if (dc->ext)
2346                 tegra_dc_ext_unregister(dc->ext);
2347
2348         mutex_lock(&dc->lock);
2349         if (dc->enabled)
2350                 _tegra_dc_disable(dc);
2351         dc->enabled = false;
2352         mutex_unlock(&dc->lock);
2353         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2354
2355 #ifdef CONFIG_SWITCH
2356         switch_dev_unregister(&dc->modeset_switch);
2357 #endif
2358         free_irq(dc->irq, dc);
2359         clk_put(dc->emc_clk);
2360         clk_put(dc->clk);
2361         iounmap(dc->base);
2362         if (dc->fb_mem)
2363                 release_resource(dc->base_res);
2364         kfree(dc);
2365         tegra_dc_set(NULL, ndev->id);
2366         return 0;
2367 }
2368
2369 #ifdef CONFIG_PM
2370 static int tegra_dc_suspend(struct nvhost_device *ndev, pm_message_t state)
2371 {
2372         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2373
2374         trace_display_suspend(dc);
2375         dev_info(&ndev->dev, "suspend\n");
2376
2377         tegra_dc_ext_disable(dc->ext);
2378
2379         mutex_lock(&dc->lock);
2380         tegra_dc_io_start(dc);
2381
2382         if (dc->out_ops && dc->out_ops->suspend)
2383                 dc->out_ops->suspend(dc);
2384
2385         if (dc->enabled) {
2386                 _tegra_dc_disable(dc);
2387
2388                 dc->suspended = true;
2389         }
2390
2391         if (dc->out && dc->out->postsuspend) {
2392                 dc->out->postsuspend();
2393                 if (dc->out->type && dc->out->type == TEGRA_DC_OUT_HDMI)
2394                         /*
2395                          * avoid resume event due to voltage falling
2396                          */
2397                         msleep(100);
2398         }
2399
2400         tegra_dc_io_end(dc);
2401         mutex_unlock(&dc->lock);
2402         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
2403
2404         return 0;
2405 }
2406
2407 static int tegra_dc_resume(struct nvhost_device *ndev)
2408 {
2409         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2410
2411         trace_display_resume(dc);
2412         dev_info(&ndev->dev, "resume\n");
2413
2414         mutex_lock(&dc->lock);
2415         dc->suspended = false;
2416
2417         if (dc->enabled) {
2418                 dc->enabled = false;
2419                 _tegra_dc_set_default_videomode(dc);
2420                 dc->enabled = _tegra_dc_enable(dc);
2421         }
2422
2423         if (dc->out && dc->out->hotplug_init)
2424                 dc->out->hotplug_init(&ndev->dev);
2425
2426         if (dc->out_ops && dc->out_ops->resume)
2427                 dc->out_ops->resume(dc);
2428         mutex_unlock(&dc->lock);
2429
2430         return 0;
2431 }
2432
2433 #endif /* CONFIG_PM */
2434
2435 static void tegra_dc_shutdown(struct nvhost_device *ndev)
2436 {
2437         struct tegra_dc *dc = nvhost_get_drvdata(ndev);
2438
2439         if (!dc || !dc->enabled)
2440                 return;
2441
2442         tegra_dc_blank(dc);
2443         tegra_dc_disable(dc);
2444 }
2445
2446 extern int suspend_set(const char *val, struct kernel_param *kp)
2447 {
2448         if (!strcmp(val, "dump"))
2449                 dump_regs(tegra_dcs[0]);
2450 #ifdef CONFIG_PM
2451         else if (!strcmp(val, "suspend"))
2452                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
2453         else if (!strcmp(val, "resume"))
2454                 tegra_dc_resume(tegra_dcs[0]->ndev);
2455 #endif
2456
2457         return 0;
2458 }
2459
2460 extern int suspend_get(char *buffer, struct kernel_param *kp)
2461 {
2462         return 0;
2463 }
2464
2465 int suspend;
2466
2467 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
2468
2469 struct nvhost_driver tegra_dc_driver = {
2470         .driver = {
2471                 .name = "tegradc",
2472                 .owner = THIS_MODULE,
2473         },
2474         .probe = tegra_dc_probe,
2475         .remove = tegra_dc_remove,
2476 #ifdef CONFIG_PM
2477         .suspend = tegra_dc_suspend,
2478         .resume = tegra_dc_resume,
2479 #endif
2480         .shutdown = tegra_dc_shutdown,
2481 };
2482
2483 #ifndef MODULE
2484 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
2485 {
2486         int i, params[11];
2487         char *p;
2488
2489         for (i = 0; i < ARRAY_SIZE(params); i++) {
2490                 if ((p = strsep(&options, ",")) != NULL) {
2491                         if (*p)
2492                                 params[i] = simple_strtoul(p, &p, 10);
2493                 } else
2494                         return -EINVAL;
2495         }
2496
2497         if ((mode->pclk = params[0]) == 0)
2498                 return -EINVAL;
2499
2500         mode->h_active      = params[1];
2501         mode->v_active      = params[2];
2502         mode->h_ref_to_sync = params[3];
2503         mode->v_ref_to_sync = params[4];
2504         mode->h_sync_width  = params[5];
2505         mode->v_sync_width  = params[6];
2506         mode->h_back_porch  = params[7];
2507         mode->v_back_porch  = params[8];
2508         mode->h_front_porch = params[9];
2509         mode->v_front_porch = params[10];
2510
2511         return 0;
2512 }
2513
2514 static int __init tegra_dc_mode_override(char *str)
2515 {
2516         char *p = str, *options;
2517
2518         if (!p || !*p)
2519                 return -EINVAL;
2520
2521         p = strstr(str, "hdmi:");
2522         if (p) {
2523                 p += 5;
2524                 options = strsep(&p, ";");
2525                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
2526                         return -EINVAL;
2527         }
2528
2529         p = strstr(str, "rgb:");
2530         if (p) {
2531                 p += 4;
2532                 options = strsep(&p, ";");
2533                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
2534                         return -EINVAL;
2535         }
2536
2537         p = strstr(str, "dsi:");
2538         if (p) {
2539                 p += 4;
2540                 options = strsep(&p, ";");
2541                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
2542                         return -EINVAL;
2543         }
2544
2545         return 0;
2546 }
2547
2548 __setup("disp_params=", tegra_dc_mode_override);
2549 #endif
2550
2551 static int __init tegra_dc_module_init(void)
2552 {
2553         int ret = tegra_dc_ext_module_init();
2554         if (ret)
2555                 return ret;
2556         return nvhost_driver_register(&tegra_dc_driver);
2557 }
2558
2559 static void __exit tegra_dc_module_exit(void)
2560 {
2561         nvhost_driver_unregister(&tegra_dc_driver);
2562         tegra_dc_ext_module_exit();
2563 }
2564
2565 module_exit(tegra_dc_module_exit);
2566 module_init(tegra_dc_module_init);