video: tegra: dc: rename tegra_dc_blank
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2017, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <linux/clk/tegra.h>
41 #include <video/tegrafb.h>
42 #include <drm/drm_fixed.h>
43 #ifdef CONFIG_SWITCH
44 #include <linux/switch.h>
45 #endif
46 #include <linux/of_irq.h>
47 #include <linux/of_address.h>
48 #include <linux/tegra_pm_domains.h>
49 #include <linux/uaccess.h>
50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
51 #include <linux/ote_protocol.h>
52 #endif
53 #include <linux/tegra-timer.h>
54
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/display.h>
57 EXPORT_TRACEPOINT_SYMBOL(display_writel);
58 EXPORT_TRACEPOINT_SYMBOL(display_readl);
59
60 #include <mach/dc.h>
61 #include <mach/fb.h>
62 #include <linux/nvhost.h>
63 #include <linux/nvhost_ioctl.h>
64
65 #include <linux/platform/tegra/latency_allowance.h>
66 #include <linux/platform/tegra/mc.h>
67 #include <soc/tegra/tegra_bpmp.h>
68
69 #include "dc_reg.h"
70 #include "dc_config.h"
71 #include "dc_priv.h"
72 #include "dev.h"
73 #include "nvhost_sync.h"
74 #include "nvsd.h"
75 #include "nvsd2.h"
76 #include "dpaux.h"
77 #include "nvsr.h"
78
79 #ifdef CONFIG_ADF_TEGRA
80 #include "tegra_adf.h"
81 #endif
82
83 #include "edid.h"
84
85 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
86 #include "fake_panel.h"
87 #include "null_or.h"
88 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
89
90
91 /* HACK! This needs to come from DT */
92 #include "../../../../arch/arm/mach-tegra/iomap.h"
93
94 #define TEGRA_CRC_LATCHED_DELAY         34
95
96 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
97 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
98
99 #define MAX_VRR_V_FRONT_PORCH                   0x1000
100
101 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
102 static struct of_device_id tegra_disa_pd[] = {
103         { .compatible = "nvidia, tegra210-disa-pd", },
104         { .compatible = "nvidia, tegra132-disa-pd", },
105         { .compatible = "nvidia, tegra124-disa-pd", },
106         {},
107 };
108
109 static struct of_device_id tegra_disb_pd[] = {
110         { .compatible = "nvidia, tegra210-disb-pd", },
111         { .compatible = "nvidia, tegra132-disb-pd", },
112         { .compatible = "nvidia, tegra124-disb-pd", },
113         {},
114 };
115 #endif
116
117 struct fb_videomode tegra_dc_vga_mode = {
118         .refresh = 60,
119         .xres = 640,
120         .yres = 480,
121         .pixclock = KHZ2PICOS(25200),
122         .hsync_len = 96,        /* h_sync_width */
123         .vsync_len = 2,         /* v_sync_width */
124         .left_margin = 48,      /* h_back_porch */
125         .upper_margin = 33,     /* v_back_porch */
126         .right_margin = 16,     /* h_front_porch */
127         .lower_margin = 10,     /* v_front_porch */
128         .vmode = 0,
129         .sync = 0,
130 };
131
132 /* needs to be big enough to be index by largest supported out->type */
133 static struct tegra_dc_mode override_disp_mode[TEGRA_DC_OUT_NULL + 1];
134
135 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
136 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq);
137 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable);
138
139 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out);
140 #ifdef PM
141 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state);
142 static int tegra_dc_resume(struct platform_device *ndev);
143 #endif
144
145 static struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
146
147 #ifdef CONFIG_TEGRA_NVDISPLAY
148 static struct tegra_dc_win      tegra_dc_windows[DC_N_WINDOWS];
149 #endif
150
151
152 static DEFINE_MUTEX(tegra_dc_lock);
153 static DEFINE_MUTEX(shared_lock);
154
155 static struct device_dma_parameters tegra_dc_dma_parameters = {
156         .max_segment_size = UINT_MAX,
157 };
158
159 static const struct {
160         bool h;
161         bool v;
162 } can_filter[] = {
163         /* Window A has no filtering */
164         { false, false },
165         /* Window B has both H and V filtering */
166         { true,  true  },
167         /* Window C has only H filtering */
168         { false, true  },
169 };
170
171 #ifdef CONFIG_TEGRA_DC_CMU
172 static struct tegra_dc_cmu default_cmu = {
173         /* lut1 maps sRGB to linear space. */
174         {
175                 0,    1,    2,    4,    5,    6,    7,    9,
176                 10,   11,   12,   14,   15,   16,   18,   20,
177                 21,   23,   25,   27,   29,   31,   33,   35,
178                 37,   40,   42,   45,   48,   50,   53,   56,
179                 59,   62,   66,   69,   72,   76,   79,   83,
180                 87,   91,   95,   99,   103,  107,  112,  116,
181                 121,  126,  131,  136,  141,  146,  151,  156,
182                 162,  168,  173,  179,  185,  191,  197,  204,
183                 210,  216,  223,  230,  237,  244,  251,  258,
184                 265,  273,  280,  288,  296,  304,  312,  320,
185                 329,  337,  346,  354,  363,  372,  381,  390,
186                 400,  409,  419,  428,  438,  448,  458,  469,
187                 479,  490,  500,  511,  522,  533,  544,  555,
188                 567,  578,  590,  602,  614,  626,  639,  651,
189                 664,  676,  689,  702,  715,  728,  742,  755,
190                 769,  783,  797,  811,  825,  840,  854,  869,
191                 884,  899,  914,  929,  945,  960,  976,  992,
192                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
193                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
194                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
195                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
196                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
197                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
198                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
199                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
200                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
201                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
202                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
203                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
204                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
205                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
206                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
207         },
208         /* csc */
209         {
210                 0x100, 0x0,   0x0,
211                 0x0,   0x100, 0x0,
212                 0x0,   0x0,   0x100,
213         },
214         /* lut2 maps linear space to sRGB*/
215         {
216                 0,    1,    2,    2,    3,    4,    5,    6,
217                 6,    7,    8,    9,    10,   10,   11,   12,
218                 13,   13,   14,   15,   15,   16,   16,   17,
219                 18,   18,   19,   19,   20,   20,   21,   21,
220                 22,   22,   23,   23,   23,   24,   24,   25,
221                 25,   25,   26,   26,   27,   27,   27,   28,
222                 28,   29,   29,   29,   30,   30,   30,   31,
223                 31,   31,   32,   32,   32,   33,   33,   33,
224                 34,   34,   34,   34,   35,   35,   35,   36,
225                 36,   36,   37,   37,   37,   37,   38,   38,
226                 38,   38,   39,   39,   39,   40,   40,   40,
227                 40,   41,   41,   41,   41,   42,   42,   42,
228                 42,   43,   43,   43,   43,   43,   44,   44,
229                 44,   44,   45,   45,   45,   45,   46,   46,
230                 46,   46,   46,   47,   47,   47,   47,   48,
231                 48,   48,   48,   48,   49,   49,   49,   49,
232                 49,   50,   50,   50,   50,   50,   51,   51,
233                 51,   51,   51,   52,   52,   52,   52,   52,
234                 53,   53,   53,   53,   53,   54,   54,   54,
235                 54,   54,   55,   55,   55,   55,   55,   55,
236                 56,   56,   56,   56,   56,   57,   57,   57,
237                 57,   57,   57,   58,   58,   58,   58,   58,
238                 58,   59,   59,   59,   59,   59,   59,   60,
239                 60,   60,   60,   60,   60,   61,   61,   61,
240                 61,   61,   61,   62,   62,   62,   62,   62,
241                 62,   63,   63,   63,   63,   63,   63,   64,
242                 64,   64,   64,   64,   64,   64,   65,   65,
243                 65,   65,   65,   65,   66,   66,   66,   66,
244                 66,   66,   66,   67,   67,   67,   67,   67,
245                 67,   67,   68,   68,   68,   68,   68,   68,
246                 68,   69,   69,   69,   69,   69,   69,   69,
247                 70,   70,   70,   70,   70,   70,   70,   71,
248                 71,   71,   71,   71,   71,   71,   72,   72,
249                 72,   72,   72,   72,   72,   72,   73,   73,
250                 73,   73,   73,   73,   73,   74,   74,   74,
251                 74,   74,   74,   74,   74,   75,   75,   75,
252                 75,   75,   75,   75,   75,   76,   76,   76,
253                 76,   76,   76,   76,   77,   77,   77,   77,
254                 77,   77,   77,   77,   78,   78,   78,   78,
255                 78,   78,   78,   78,   78,   79,   79,   79,
256                 79,   79,   79,   79,   79,   80,   80,   80,
257                 80,   80,   80,   80,   80,   81,   81,   81,
258                 81,   81,   81,   81,   81,   81,   82,   82,
259                 82,   82,   82,   82,   82,   82,   83,   83,
260                 83,   83,   83,   83,   83,   83,   83,   84,
261                 84,   84,   84,   84,   84,   84,   84,   84,
262                 85,   85,   85,   85,   85,   85,   85,   85,
263                 85,   86,   86,   86,   86,   86,   86,   86,
264                 86,   86,   87,   87,   87,   87,   87,   87,
265                 87,   87,   87,   88,   88,   88,   88,   88,
266                 88,   88,   88,   88,   88,   89,   89,   89,
267                 89,   89,   89,   89,   89,   89,   90,   90,
268                 90,   90,   90,   90,   90,   90,   90,   90,
269                 91,   91,   91,   91,   91,   91,   91,   91,
270                 91,   91,   92,   92,   92,   92,   92,   92,
271                 92,   92,   92,   92,   93,   93,   93,   93,
272                 93,   93,   93,   93,   93,   93,   94,   94,
273                 94,   94,   94,   94,   94,   94,   94,   94,
274                 95,   95,   95,   95,   95,   95,   95,   95,
275                 95,   95,   96,   96,   96,   96,   96,   96,
276                 96,   96,   96,   96,   96,   97,   97,   97,
277                 97,   97,   97,   97,   97,   97,   97,   98,
278                 98,   98,   98,   98,   98,   98,   98,   98,
279                 98,   98,   99,   99,   99,   99,   99,   99,
280                 99,   100,  101,  101,  102,  103,  103,  104,
281                 105,  105,  106,  107,  107,  108,  109,  109,
282                 110,  111,  111,  112,  113,  113,  114,  115,
283                 115,  116,  116,  117,  118,  118,  119,  119,
284                 120,  120,  121,  122,  122,  123,  123,  124,
285                 124,  125,  126,  126,  127,  127,  128,  128,
286                 129,  129,  130,  130,  131,  131,  132,  132,
287                 133,  133,  134,  134,  135,  135,  136,  136,
288                 137,  137,  138,  138,  139,  139,  140,  140,
289                 141,  141,  142,  142,  143,  143,  144,  144,
290                 145,  145,  145,  146,  146,  147,  147,  148,
291                 148,  149,  149,  150,  150,  150,  151,  151,
292                 152,  152,  153,  153,  153,  154,  154,  155,
293                 155,  156,  156,  156,  157,  157,  158,  158,
294                 158,  159,  159,  160,  160,  160,  161,  161,
295                 162,  162,  162,  163,  163,  164,  164,  164,
296                 165,  165,  166,  166,  166,  167,  167,  167,
297                 168,  168,  169,  169,  169,  170,  170,  170,
298                 171,  171,  172,  172,  172,  173,  173,  173,
299                 174,  174,  174,  175,  175,  176,  176,  176,
300                 177,  177,  177,  178,  178,  178,  179,  179,
301                 179,  180,  180,  180,  181,  181,  182,  182,
302                 182,  183,  183,  183,  184,  184,  184,  185,
303                 185,  185,  186,  186,  186,  187,  187,  187,
304                 188,  188,  188,  189,  189,  189,  189,  190,
305                 190,  190,  191,  191,  191,  192,  192,  192,
306                 193,  193,  193,  194,  194,  194,  195,  195,
307                 195,  196,  196,  196,  196,  197,  197,  197,
308                 198,  198,  198,  199,  199,  199,  200,  200,
309                 200,  200,  201,  201,  201,  202,  202,  202,
310                 202,  203,  203,  203,  204,  204,  204,  205,
311                 205,  205,  205,  206,  206,  206,  207,  207,
312                 207,  207,  208,  208,  208,  209,  209,  209,
313                 209,  210,  210,  210,  211,  211,  211,  211,
314                 212,  212,  212,  213,  213,  213,  213,  214,
315                 214,  214,  214,  215,  215,  215,  216,  216,
316                 216,  216,  217,  217,  217,  217,  218,  218,
317                 218,  219,  219,  219,  219,  220,  220,  220,
318                 220,  221,  221,  221,  221,  222,  222,  222,
319                 223,  223,  223,  223,  224,  224,  224,  224,
320                 225,  225,  225,  225,  226,  226,  226,  226,
321                 227,  227,  227,  227,  228,  228,  228,  228,
322                 229,  229,  229,  229,  230,  230,  230,  230,
323                 231,  231,  231,  231,  232,  232,  232,  232,
324                 233,  233,  233,  233,  234,  234,  234,  234,
325                 235,  235,  235,  235,  236,  236,  236,  236,
326                 237,  237,  237,  237,  238,  238,  238,  238,
327                 239,  239,  239,  239,  240,  240,  240,  240,
328                 240,  241,  241,  241,  241,  242,  242,  242,
329                 242,  243,  243,  243,  243,  244,  244,  244,
330                 244,  244,  245,  245,  245,  245,  246,  246,
331                 246,  246,  247,  247,  247,  247,  247,  248,
332                 248,  248,  248,  249,  249,  249,  249,  249,
333                 250,  250,  250,  250,  251,  251,  251,  251,
334                 251,  252,  252,  252,  252,  253,  253,  253,
335                 253,  253,  254,  254,  254,  254,  255,  255,
336         },
337 };
338
339 static struct tegra_dc_cmu default_limited_cmu = {
340         /* lut1 maps sRGB to linear space. */
341         {
342                 0,    1,    2,    4,    5,    6,    7,    9,
343                 10,   11,   12,   14,   15,   16,   18,   20,
344                 21,   23,   25,   27,   29,   31,   33,   35,
345                 37,   40,   42,   45,   48,   50,   53,   56,
346                 59,   62,   66,   69,   72,   76,   79,   83,
347                 87,   91,   95,   99,   103,  107,  112,  116,
348                 121,  126,  131,  136,  141,  146,  151,  156,
349                 162,  168,  173,  179,  185,  191,  197,  204,
350                 210,  216,  223,  230,  237,  244,  251,  258,
351                 265,  273,  280,  288,  296,  304,  312,  320,
352                 329,  337,  346,  354,  363,  372,  381,  390,
353                 400,  409,  419,  428,  438,  448,  458,  469,
354                 479,  490,  500,  511,  522,  533,  544,  555,
355                 567,  578,  590,  602,  614,  626,  639,  651,
356                 664,  676,  689,  702,  715,  728,  742,  755,
357                 769,  783,  797,  811,  825,  840,  854,  869,
358                 884,  899,  914,  929,  945,  960,  976,  992,
359                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
360                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
361                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
362                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
363                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
364                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
365                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
366                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
367                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
368                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
369                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
370                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
371                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
372                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
373                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
374         },
375         /* csc */
376         {
377                 0x100, 0x000, 0x000,
378                 0x000, 0x100, 0x000,
379                 0x000, 0x000, 0x100,
380         },
381         /*
382          * lut2 maps linear space back to sRGB, where
383          * the output range is [16...235] (limited).
384          */
385         {
386                 16,  17,  18,  18,  19,  19,  20,  21,
387                 21,  22,  23,  24,  25,  25,  25,  26,
388                 27,  27,  28,  28,  29,  30,  30,  31,
389                 31,  31,  31,  32,  32,  33,  33,  34,
390                 34,  35,  35,  36,  36,  37,  37,  37,
391                 37,  37,  38,  38,  38,  39,  39,  39,
392                 40,  40,  41,  41,  41,  42,  42,  42,
393                 43,  43,  43,  43,  43,  43,  44,  44,
394                 44,  44,  45,  45,  45,  46,  46,  46,
395                 47,  47,  47,  47,  48,  48,  48,  49,
396                 49,  49,  49,  49,  49,  49,  49,  50,
397                 50,  50,  50,  51,  51,  51,  51,  52,
398                 52,  52,  52,  53,  53,  53,  53,  54,
399                 54,  54,  54,  55,  55,  55,  55,  55,
400                 56,  56,  56,  56,  56,  56,  56,  56,
401                 56,  57,  57,  57,  57,  57,  58,  58,
402                 58,  58,  58,  59,  59,  59,  59,  59,
403                 60,  60,  60,  60,  60,  61,  61,  61,
404                 61,  61,  62,  62,  62,  62,  62,  62,
405                 62,  62,  62,  62,  63,  63,  63,  63,
406                 63,  63,  64,  64,  64,  64,  64,  64,
407                 65,  65,  65,  65,  65,  66,  66,  66,
408                 66,  66,  66,  67,  67,  67,  67,  67,
409                 67,  68,  68,  68,  68,  68,  68,  68,
410                 68,  68,  68,  68,  68,  69,  69,  69,
411                 69,  69,  69,  69,  70,  70,  70,  70,
412                 70,  70,  71,  71,  71,  71,  71,  71,
413                 72,  72,  72,  72,  72,  72,  72,  73,
414                 73,  73,  73,  73,  73,  73,  74,  74,
415                 74,  74,  74,  74,  74,  74,  74,  74,
416                 74,  74,  74,  74,  75,  75,  75,  75,
417                 75,  75,  75,  76,  76,  76,  76,  76,
418                 76,  76,  77,  77,  77,  77,  77,  77,
419                 77,  78,  78,  78,  78,  78,  78,  78,
420                 78,  79,  79,  79,  79,  79,  79,  79,
421                 80,  80,  80,  80,  80,  80,  80,  80,
422                 80,  80,  80,  80,  80,  80,  80,  80,
423                 81,  81,  81,  81,  81,  81,  81,  81,
424                 82,  82,  82,  82,  82,  82,  82,  82,
425                 83,  83,  83,  83,  83,  83,  83,  83,
426                 84,  84,  84,  84,  84,  84,  84,  84,
427                 84,  85,  85,  85,  85,  85,  85,  85,
428                 85,  86,  86,  86,  86,  86,  86,  86,
429                 86,  86,  86,  86,  86,  86,  86,  86,
430                 86,  86,  87,  87,  87,  87,  87,  87,
431                 87,  87,  87,  88,  88,  88,  88,  88,
432                 88,  88,  88,  88,  89,  89,  89,  89,
433                 89,  89,  89,  89,  89,  90,  90,  90,
434                 90,  90,  90,  90,  90,  90,  91,  91,
435                 91,  91,  91,  91,  91,  91,  91,  91,
436                 92,  92,  92,  92,  92,  92,  92,  92,
437                 92,  92,  92,  92,  92,  92,  92,  92,
438                 92,  92,  92,  93,  93,  93,  93,  93,
439                 93,  93,  93,  93,  94,  94,  94,  94,
440                 94,  94,  94,  94,  94,  94,  95,  95,
441                 95,  95,  95,  95,  95,  95,  95,  95,
442                 96,  96,  96,  96,  96,  96,  96,  96,
443                 96,  96,  97,  97,  97,  97,  97,  97,
444                 97,  97,  97,  97,  97,  98,  98,  98,
445                 98,  98,  98,  98,  98,  98,  98,  98,
446                 98,  98,  98,  98,  98,  98,  98,  98,
447                 98,  98,  99,  99,  99,  99,  99,  99,
448                 99,  99,  99,  99, 100, 100, 100, 100,
449                 100, 100, 100, 100, 100, 100, 100, 101,
450                 101, 102, 103, 103, 104, 104, 105, 105,
451                 106, 107, 107, 108, 109, 109, 110, 110,
452                 110, 111, 111, 112, 113, 113, 114, 115,
453                 115, 116, 116, 116, 117, 117, 118, 118,
454                 119, 120, 120, 121, 121, 122, 122, 122,
455                 122, 123, 124, 124, 125, 125, 126, 126,
456                 127, 127, 128, 128, 129, 129, 129, 129,
457                 130, 130, 131, 131, 132, 132, 133, 133,
458                 134, 134, 135, 135, 135, 135, 136, 136,
459                 137, 137, 138, 138, 139, 139, 140, 140,
460                 141, 141, 141, 141, 141, 142, 142, 143,
461                 143, 144, 144, 144, 145, 145, 146, 146,
462                 147, 147, 147, 147, 147, 148, 148, 149,
463                 149, 149, 150, 150, 151, 151, 151, 152,
464                 152, 153, 153, 153, 153, 153, 154, 154,
465                 154, 155, 155, 156, 156, 156, 157, 157,
466                 158, 158, 158, 159, 159, 159, 159, 159,
467                 160, 160, 160, 161, 161, 162, 162, 162,
468                 163, 163, 163, 164, 164, 165, 165, 165,
469                 165, 165, 165, 166, 166, 166, 167, 167,
470                 167, 168, 168, 169, 169, 169, 170, 170,
471                 170, 171, 171, 171, 171, 171, 171, 172,
472                 172, 172, 173, 173, 173, 174, 174, 174,
473                 175, 175, 175, 176, 176, 176, 177, 177,
474                 177, 177, 177, 177, 178, 178, 178, 179,
475                 179, 179, 180, 180, 180, 181, 181, 181,
476                 181, 182, 182, 182, 183, 183, 183, 183,
477                 183, 183, 184, 184, 184, 185, 185, 185,
478                 185, 186, 186, 186, 187, 187, 187, 188,
479                 188, 188, 188, 189, 189, 189, 189, 189,
480                 189, 190, 190, 190, 190, 191, 191, 191,
481                 192, 192, 192, 193, 193, 193, 193, 194,
482                 194, 194, 195, 195, 195, 195, 195, 195,
483                 195, 196, 196, 196, 196, 197, 197, 197,
484                 197, 198, 198, 198, 199, 199, 199, 199,
485                 200, 200, 200, 201, 201, 201, 201, 202,
486                 202, 202, 202, 202, 202, 202, 203, 203,
487                 203, 203, 204, 204, 204, 204, 205, 205,
488                 205, 205, 206, 206, 206, 207, 207, 207,
489                 207, 208, 208, 208, 208, 208, 208, 208,
490                 208, 209, 209, 209, 209, 210, 210, 210,
491                 210, 211, 211, 211, 211, 212, 212, 212,
492                 212, 213, 213, 213, 213, 214, 214, 214,
493                 214, 214, 214, 214, 214, 215, 215, 215,
494                 215, 216, 216, 216, 216, 217, 217, 217,
495                 217, 218, 218, 218, 218, 219, 219, 219,
496                 219, 220, 220, 220, 220, 220, 220, 220,
497                 220, 221, 221, 221, 221, 221, 222, 222,
498                 222, 222, 223, 223, 223, 223, 224, 224,
499                 224, 224, 225, 225, 225, 225, 225, 226,
500                 226, 226, 226, 226, 226, 226, 226, 227,
501                 227, 227, 227, 227, 228, 228, 228, 228,
502                 229, 229, 229, 229, 230, 230, 230, 230,
503                 230, 231, 231, 231, 231, 232, 232, 232,
504                 232, 232, 232, 232, 232, 232, 233, 233,
505                 233, 233, 233, 234, 234, 234, 234, 235
506         },
507 };
508 #elif defined(CONFIG_TEGRA_DC_CMU_V2)
509 static struct tegra_dc_cmu default_cmu = {
510         {},
511 };
512 static struct tegra_dc_cmu default_limited_cmu = {
513         {},
514 };
515 #endif
516
517 void tegra_dc_clk_enable(struct tegra_dc *dc)
518 {
519         tegra_disp_clk_prepare_enable(dc->clk);
520         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
521 }
522
523 void tegra_dc_clk_disable(struct tegra_dc *dc)
524 {
525         tegra_disp_clk_disable_unprepare(dc->clk);
526         tegra_dvfs_set_rate(dc->clk, 0);
527 }
528
529 static void tegra_dc_set_sor_instance(struct tegra_dc *dc, int out_type)
530 {
531         /* Fake DP should always be on SOR0. */
532         if (!strcmp(dc_or_node_names[dc->ndev->id], "/host1x/sor") ||
533                 out_type == TEGRA_DC_OUT_FAKE_DP)
534                 dc->sor_instance = 0;
535         else
536                 dc->sor_instance = 1;
537 }
538
539 void tegra_dc_get(struct tegra_dc *dc)
540 {
541         tegra_dc_io_start(dc);
542
543         /* extra reference to dc clk */
544         tegra_disp_clk_prepare_enable(dc->clk);
545 }
546 EXPORT_SYMBOL(tegra_dc_get);
547
548 void tegra_dc_put(struct tegra_dc *dc)
549 {
550         /* balance extra dc clk reference */
551         tegra_disp_clk_disable_unprepare(dc->clk);
552
553         tegra_dc_io_end(dc);
554 }
555 EXPORT_SYMBOL(tegra_dc_put);
556
557 unsigned tegra_dc_out_flags_from_dev(struct device *dev)
558 {
559         struct platform_device *ndev = NULL;
560         struct tegra_dc *dc = NULL;
561
562         if (dev)
563                 ndev = to_platform_device(dev);
564         if (ndev)
565                 dc = platform_get_drvdata(ndev);
566         if (dc)
567                 return dc->out->flags;
568         else
569                 return 0;
570 }
571 EXPORT_SYMBOL(tegra_dc_out_flags_from_dev);
572
573 bool tegra_dc_initialized(struct device *dev)
574 {
575         struct platform_device *ndev = NULL;
576         struct tegra_dc *dc = NULL;
577
578         if (dev)
579                 ndev = to_platform_device(dev);
580         if (ndev)
581                 dc = platform_get_drvdata(ndev);
582         if (dc)
583                 return dc->initialized;
584         else
585                 return false;
586 }
587 EXPORT_SYMBOL(tegra_dc_initialized);
588
589 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
590 {
591         if (1 == atomic_inc_return(&dc->holding)) {
592                 tegra_dc_get(dc);
593                 if (dc->out_ops && dc->out_ops->hold)
594                         dc->out_ops->hold(dc);
595         }
596 }
597
598 void tegra_dc_release_dc_out(struct tegra_dc *dc)
599 {
600         if (0 == atomic_dec_return(&dc->holding)) {
601                 if (dc->out_ops && dc->out_ops->release)
602                         dc->out_ops->release(dc);
603                 tegra_dc_put(dc);
604         }
605 }
606
607 #define DUMP_REG(a) do {                        \
608         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
609                  #a, a, tegra_dc_readl(dc, a));               \
610         print(data, buff);                                    \
611         } while (0)
612
613 static void _dump_regs(struct tegra_dc *dc, void *data,
614                        void (* print)(void *data, const char *str))
615 {
616         int i;
617         char buff[256];
618         const char winname[] = "ABCDHT";
619         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
620         unsigned long cmd_state;
621
622         /* If gated, quietly return. */
623         if (!tegra_powergate_is_powered(dc->powergate_id))
624                 return;
625
626         mutex_lock(&dc->lock);
627         tegra_dc_get(dc);
628         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
629         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
630                 DC_CMD_STATE_ACCESS);
631
632         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
633         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
634         DUMP_REG(DC_CMD_SIGNAL_RAISE);
635         DUMP_REG(DC_CMD_INT_STATUS);
636         DUMP_REG(DC_CMD_INT_MASK);
637         DUMP_REG(DC_CMD_INT_ENABLE);
638         DUMP_REG(DC_CMD_INT_TYPE);
639         DUMP_REG(DC_CMD_INT_POLARITY);
640         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
641         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
642         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
643         DUMP_REG(DC_CMD_STATE_ACCESS);
644         DUMP_REG(DC_CMD_STATE_CONTROL);
645         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
646         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
647
648         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
649         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
650         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
651         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
652         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
653         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
654         DUMP_REG(DC_DISP_REF_TO_SYNC);
655         DUMP_REG(DC_DISP_SYNC_WIDTH);
656         DUMP_REG(DC_DISP_BACK_PORCH);
657         DUMP_REG(DC_DISP_DISP_ACTIVE);
658         DUMP_REG(DC_DISP_FRONT_PORCH);
659         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
660         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
661         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
662         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
663         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
664         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
665         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
666         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
667         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
668         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
669         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
670         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
671         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
672         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
673         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
674         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
675         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
676         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
677         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
678         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
679         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
680         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
681         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
682         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
683         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
684         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
685         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
686         DUMP_REG(DC_DISP_M0_CONTROL);
687         DUMP_REG(DC_DISP_M1_CONTROL);
688         DUMP_REG(DC_DISP_DI_CONTROL);
689         DUMP_REG(DC_DISP_PP_CONTROL);
690         DUMP_REG(DC_DISP_PP_SELECT_A);
691         DUMP_REG(DC_DISP_PP_SELECT_B);
692         DUMP_REG(DC_DISP_PP_SELECT_C);
693         DUMP_REG(DC_DISP_PP_SELECT_D);
694         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
695         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
696         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
697         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
698         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
699         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
700         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
701 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
702         DUMP_REG(DC_DISP_BORDER_COLOR);
703 #endif
704         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
705         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
706         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
707         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
708         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
709         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
710         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
711         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
712 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
713         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
714         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
715 #endif
716         DUMP_REG(DC_DISP_CURSOR_POSITION);
717         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
718         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
719         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
720         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
721         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
722         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
723         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
724         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
725         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
726         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
727 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
728         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
729 #endif
730         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
731         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
732 #if defined(CONFIG_TEGRA_DC_INTERLACE)
733         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
734         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
735         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
736         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
737         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
738         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
739 #endif
740
741         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
742         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
743         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
744         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
745         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
746         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
747         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
748         DUMP_REG(DC_DISP_M1_CONTROL);
749         DUMP_REG(DC_COM_PM1_CONTROL);
750         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
751         DUMP_REG(DC_DISP_SD_CONTROL);
752
753 #ifdef CONFIG_TEGRA_DC_CMU
754         DUMP_REG(DC_COM_CMU_CSC_KRR);
755         DUMP_REG(DC_COM_CMU_CSC_KGR);
756         DUMP_REG(DC_COM_CMU_CSC_KBR);
757         DUMP_REG(DC_COM_CMU_CSC_KRG);
758         DUMP_REG(DC_COM_CMU_CSC_KGG);
759         DUMP_REG(DC_COM_CMU_CSC_KBG);
760         DUMP_REG(DC_COM_CMU_CSC_KRB);
761         DUMP_REG(DC_COM_CMU_CSC_KGB);
762         DUMP_REG(DC_COM_CMU_CSC_KBB);
763 #endif
764
765         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
766                 print(data, "\n");
767                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
768                 print(data, buff);
769
770                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
771                                 DC_CMD_DISPLAY_WINDOW_HEADER);
772                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
773                 DUMP_REG(DC_WIN_WIN_OPTIONS);
774                 DUMP_REG(DC_WIN_BYTE_SWAP);
775                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
776                 DUMP_REG(DC_WIN_COLOR_DEPTH);
777                 DUMP_REG(DC_WIN_POSITION);
778                 DUMP_REG(DC_WIN_SIZE);
779                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
780                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
781                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
782                 DUMP_REG(DC_WIN_DDA_INCREMENT);
783                 DUMP_REG(DC_WIN_LINE_STRIDE);
784 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
785                 DUMP_REG(DC_WIN_BUF_STRIDE);
786                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
787 #endif
788                 DUMP_REG(DC_WIN_BLEND_NOKEY);
789                 DUMP_REG(DC_WIN_BLEND_1WIN);
790                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
791                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
792                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
793                 DUMP_REG(DC_WIN_GLOBAL_ALPHA);
794 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
795         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
796         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
797         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
798                 DUMP_REG(DC_WINBUF_BLEND_LAYER_CONTROL);
799 #endif
800                 DUMP_REG(DC_WINBUF_START_ADDR);
801                 DUMP_REG(DC_WINBUF_START_ADDR_U);
802                 DUMP_REG(DC_WINBUF_START_ADDR_V);
803                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
804                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
805 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
806         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
807         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
808         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
809                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
810                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
811                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
812                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
813                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
814                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
815                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
816                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
817                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
818                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
819                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
820 #endif
821                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
822                 DUMP_REG(DC_WIN_CSC_YOF);
823                 DUMP_REG(DC_WIN_CSC_KYRGB);
824                 DUMP_REG(DC_WIN_CSC_KUR);
825                 DUMP_REG(DC_WIN_CSC_KVR);
826                 DUMP_REG(DC_WIN_CSC_KUG);
827                 DUMP_REG(DC_WIN_CSC_KVG);
828                 DUMP_REG(DC_WIN_CSC_KUB);
829                 DUMP_REG(DC_WIN_CSC_KVB);
830
831 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
832                 DUMP_REG(DC_WINBUF_CDE_CONTROL);
833                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASE_0);
834                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASEHI_0);
835                 DUMP_REG(DC_WINBUF_CDE_ZBC_COLOR_0);
836                 DUMP_REG(DC_WINBUF_CDE_SURFACE_OFFSET_0);
837                 DUMP_REG(DC_WINBUF_CDE_CTB_ENTRY_0);
838                 DUMP_REG(DC_WINBUF_CDE_CG_SW_OVR);
839                 DUMP_REG(DC_WINBUF_CDE_PM_CONTROL);
840                 DUMP_REG(DC_WINBUF_CDE_PM_COUNTER);
841 #endif
842         }
843
844         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
845         tegra_dc_put(dc);
846         mutex_unlock(&dc->lock);
847 }
848
849 #undef DUMP_REG
850
851 #ifdef DEBUG
852 static void dump_regs_print(void *data, const char *str)
853 {
854         struct tegra_dc *dc = data;
855         dev_dbg(&dc->ndev->dev, "%s", str);
856 }
857
858 static void dump_regs(struct tegra_dc *dc)
859 {
860         _dump_regs(dc, dc, dump_regs_print);
861 }
862 #else /* !DEBUG */
863
864 static void dump_regs(struct tegra_dc *dc) {}
865
866 #endif /* DEBUG */
867
868 #ifdef CONFIG_DEBUG_FS
869
870 static void dbg_regs_print(void *data, const char *str)
871 {
872         struct seq_file *s = data;
873
874         seq_printf(s, "%s", str);
875 }
876
877 #undef DUMP_REG
878
879 static int dbg_dc_show(struct seq_file *s, void *unused)
880 {
881         struct tegra_dc *dc = s->private;
882
883         _dump_regs(dc, s, dbg_regs_print);
884
885         return 0;
886 }
887
888
889 static int dbg_dc_open(struct inode *inode, struct file *file)
890 {
891         return single_open(file, dbg_dc_show, inode->i_private);
892 }
893
894 static const struct file_operations regs_fops = {
895         .open           = dbg_dc_open,
896         .read           = seq_read,
897         .llseek         = seq_lseek,
898         .release        = single_release,
899 };
900
901 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
902 {
903         struct tegra_dc *dc = s->private;
904         struct tegra_dc_mode *m;
905
906         mutex_lock(&dc->lock);
907         m = &dc->mode;
908         seq_printf(s,
909                 "pclk: %d\n"
910                 "h_ref_to_sync: %d\n"
911                 "v_ref_to_sync: %d\n"
912                 "h_sync_width: %d\n"
913                 "v_sync_width: %d\n"
914                 "h_back_porch: %d\n"
915                 "v_back_porch: %d\n"
916                 "h_active: %d\n"
917                 "v_active: %d\n"
918                 "h_front_porch: %d\n"
919                 "v_front_porch: %d\n"
920                 "flags: 0x%x\n"
921                 "stereo_mode: %d\n"
922                 "avi_m: 0x%x\n"
923                 "vmode: 0x%x\n",
924                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
925                 m->h_sync_width, m->v_sync_width,
926                 m->h_back_porch, m->v_back_porch,
927                 m->h_active, m->v_active,
928                 m->h_front_porch, m->v_front_porch,
929                 m->flags, m->stereo_mode, m->avi_m, m->vmode);
930         mutex_unlock(&dc->lock);
931         return 0;
932 }
933
934 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
935 {
936         return single_open(file, dbg_dc_mode_show, inode->i_private);
937 }
938
939 static const struct file_operations mode_fops = {
940         .open           = dbg_dc_mode_open,
941         .read           = seq_read,
942         .llseek         = seq_lseek,
943         .release        = single_release,
944 };
945
946 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
947 {
948         struct tegra_dc *dc = s->private;
949
950         mutex_lock(&dc->lock);
951         seq_printf(s,
952                 "underflows: %llu\n"
953                 "underflows_a: %llu\n"
954                 "underflows_b: %llu\n"
955                 "underflows_c: %llu\n",
956                 dc->stats.underflows,
957                 dc->stats.underflows_a,
958                 dc->stats.underflows_b,
959                 dc->stats.underflows_c);
960 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
961         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
962         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
963         seq_printf(s,
964                 "underflows_d: %llu\n"
965                 "underflows_h: %llu\n"
966                 "underflows_t: %llu\n",
967                 dc->stats.underflows_d,
968                 dc->stats.underflows_h,
969                 dc->stats.underflows_t);
970 #endif
971 #if defined(CONFIG_TEGRA_NVDISPLAY)
972         seq_printf(s,
973                 "underflow_frames: %llu\n",
974                 dc->stats.underflow_frames);
975 #endif
976         mutex_unlock(&dc->lock);
977
978         return 0;
979 }
980
981 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
982 {
983         return single_open(file, dbg_dc_stats_show, inode->i_private);
984 }
985
986 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
987 {
988         return 0;
989 }
990
991 static ssize_t dbg_dc_event_inject_write(struct file *file,
992         const char __user *addr, size_t len, loff_t *pos)
993 {
994         struct seq_file *m = file->private_data; /* single_open() initialized */
995         struct tegra_dc *dc = m ? m->private : NULL;
996         long event;
997         int ret;
998
999         if (!dc)
1000                 return -EINVAL;
1001
1002         ret = kstrtol_from_user(addr, len, 10, &event);
1003         if (ret < 0)
1004                 return ret;
1005
1006         /*
1007          * ADF has two seperate events for hotplug connect and disconnect.
1008          * We map event 0x0, and 0x1 for them accordingly.  For DC_EXT,
1009          * both events map to HOTPLUG.
1010          */
1011 #ifdef CONFIG_ADF_TEGRA
1012         if (event == 0x0)
1013                 tegra_adf_process_hotplug_connected(dc->adf, NULL);
1014         else if (event == 0x1)
1015                 tegra_adf_process_hotplug_disconnected(dc->adf);
1016         else if (event == 0x2)
1017                 tegra_adf_process_bandwidth_renegotiate(dc->adf, 0);
1018         else {
1019                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
1020                 return -EINVAL; /* unknown event number */
1021         }
1022 #endif
1023 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
1024         if (event == 0x0) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Connected) */
1025                 tegra_dc_ext_process_hotplug(dc->ndev->id, true);
1026         else if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Disconnected) */
1027                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
1028         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
1029                 tegra_dc_ext_process_bandwidth_renegotiate(
1030                                 dc->ndev->id, NULL);
1031         else {
1032                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
1033                 return -EINVAL; /* unknown event number */
1034         }
1035 #endif
1036         return len;
1037 }
1038
1039 /* Update the strings as dc.h get updated for new output types*/
1040 static const char * const dc_outtype_strings[] = {
1041         "TEGRA_DC_OUT_RGB",
1042         "TEGRA_DC_OUT_HDMI",
1043         "TEGRA_DC_OUT_DSI",
1044         "TEGRA_DC_OUT_DP",
1045         "TEGRA_DC_OUT_LVDS",
1046         "TEGRA_DC_OUT_NVSR_DP",
1047         "TEGRA_DC_OUT_FAKE_DP",
1048         "TEGRA_DC_OUT_FAKE_DSIA",
1049         "TEGRA_DC_OUT_FAKE_DSIB",
1050         "TEGRA_DC_OUT_FAKE_DSI_GANGED",
1051         "TEGRA_DC_OUT_NULL",
1052         "TEGRA_DC_OUT_UNKNOWN"
1053 };
1054
1055 static int dbg_dc_outtype_show(struct seq_file *s, void *unused)
1056 {
1057         struct tegra_dc *dc = s->private;
1058
1059         mutex_lock(&dc->lock);
1060         seq_puts(s, "\n");
1061         seq_printf(s,
1062                 "\tDC OUTPUT: \t%s (%d)\n",
1063                 dc_outtype_strings[dc->out->type], dc->out->type);
1064         seq_puts(s, "\n");
1065         mutex_unlock(&dc->lock);
1066         return 0;
1067 }
1068
1069 /* Add specific variable related to each output type.
1070  * Save and reuse on changing the output type
1071  */
1072 #if defined(CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT)
1073 struct tegra_dc_out_info {
1074         struct tegra_dc_out_ops *out_ops;
1075         void *out_data;
1076         struct tegra_dc_out out;
1077         struct tegra_dc_mode mode;
1078         int fblistindex;
1079 };
1080
1081 static struct tegra_dc_out_info dbg_dc_out_info[TEGRA_DC_OUT_MAX];
1082 /* array for saving the out_type for each head */
1083 static int  boot_out_type[] = {-1, -1};
1084
1085 static int is_invalid_dc_out(struct tegra_dc *dc, long dc_outtype)
1086 {
1087         if ((dc_outtype != boot_out_type[dc->ndev->id]) &&
1088                 (dc_outtype != TEGRA_DC_OUT_FAKE_DP) &&
1089                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIA) &&
1090                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIB) &&
1091                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSI_GANGED) &&
1092                 (dc_outtype != TEGRA_DC_OUT_NULL)) {
1093                 dev_err(&dc->ndev->dev,
1094                         "Request 0x%lx is unsupported target out_type\n",
1095                          dc_outtype);
1096                 dev_err(&dc->ndev->dev,
1097                         "boot_out_type[%d] is 0x%x\n",
1098                          dc->ndev->id, boot_out_type[dc->ndev->id]);
1099                 return -EINVAL;
1100         }
1101
1102         return 0;
1103 }
1104
1105 static int is_valid_dsi_out(struct tegra_dc *dc, long dc_outtype)
1106 {
1107         if (((dc_outtype >= TEGRA_DC_OUT_FAKE_DSIA) &&
1108                 (dc_outtype <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) ||
1109                 (dc_outtype == TEGRA_DC_OUT_DSI))
1110                         return 1;
1111
1112         return 0;
1113 }
1114
1115
1116 static int is_valid_fake_support(struct tegra_dc *dc, long dc_outtype)
1117 {
1118         if ((dc_outtype == TEGRA_DC_OUT_FAKE_DP) ||
1119                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIA) ||
1120                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) ||
1121                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) ||
1122                 (dc_outtype == TEGRA_DC_OUT_NULL))
1123                 return 1;
1124
1125         return 0;
1126 }
1127
1128 static int set_avdd(struct tegra_dc *dc, long cur_out, long new_out)
1129 {
1130 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1131         /* T210 macro_clk is failing SOR access
1132          * if avdd_lcd is not enabled
1133          */
1134         bool is_enable = false;
1135         struct tegra_dc_out *dc_out =
1136                 &dbg_dc_out_info[boot_out_type[dc->ndev->id]].out;
1137
1138         /* cur is fake and new is fake - skip */
1139         if (is_valid_fake_support(dc, cur_out) &&
1140                 is_valid_fake_support(dc, new_out))
1141                 return 0;
1142
1143         /* cur is valid and new is fake - enable */
1144         if (!is_valid_fake_support(dc, cur_out) &&
1145                 is_valid_fake_support(dc, new_out))
1146                 is_enable = true;
1147
1148         if (is_enable) {
1149                 if (dc_out && dc_out->enable)
1150                         dc_out->enable(&dc->ndev->dev);
1151         } else {
1152                 if (dc_out && dc_out->disable)
1153                         dc_out->disable(&dc->ndev->dev);
1154         }
1155 #endif
1156         return 0;
1157 }
1158 static ssize_t dbg_dc_out_type_set(struct file *file,
1159         const char __user *addr, size_t len, loff_t *pos)
1160 {
1161         struct seq_file *m = file->private_data; /* single_open() initialized */
1162         struct tegra_dc *dc = m ? m->private : NULL;
1163         long cur_dc_out;
1164         long out_type;
1165         int ret = 0;
1166         bool  allocate = false;
1167
1168         if (!dc)
1169                 return -EINVAL;
1170
1171         ret = kstrtol_from_user(addr, len, 10, &out_type);
1172         if (ret < 0)
1173                 return ret;
1174
1175         if (!dc->pdata->default_out)
1176                 return -EINVAL;
1177
1178         /* check out type is out of range then skip */
1179         if (out_type < TEGRA_DC_OUT_RGB ||
1180                 out_type >= TEGRA_DC_OUT_MAX) {
1181                 dev_err(&dc->ndev->dev, "Unknown out_type 0x%lx\n", out_type);
1182                 return -EINVAL;
1183         }
1184
1185         if (boot_out_type[dc->ndev->id] == -1)
1186                 boot_out_type[dc->ndev->id] = dc->pdata->default_out->type;
1187
1188         cur_dc_out = dc->pdata->default_out->type;
1189
1190         /* Nothing to do if new outtype is same as old
1191          * Allow to switch between booted out type and fake panel out
1192          */
1193         if ((cur_dc_out == out_type) || is_invalid_dc_out(dc, out_type))
1194                 return -EINVAL;
1195
1196         /* disable the dc and output controllers */
1197         if (dc->enabled)
1198                 tegra_dc_disable(dc);
1199
1200         /* If output is already created - save it */
1201         if (dc->out_data) {
1202                 dbg_dc_out_info[cur_dc_out].out_data = dc->out_data;
1203                 dbg_dc_out_info[cur_dc_out].out_ops  = dc->out_ops;
1204                 memcpy(&dbg_dc_out_info[cur_dc_out].out, dc->out,
1205                                         sizeof(struct tegra_dc_out));
1206                 dbg_dc_out_info[cur_dc_out].mode = dc->mode;
1207
1208                 if (is_valid_dsi_out(dc, cur_dc_out) &&
1209                         dbg_dc_out_info[cur_dc_out].out_data)
1210                         tegra_dc_destroy_dsi_resources(dc, cur_dc_out);
1211
1212                 if (!is_valid_fake_support(dc, cur_dc_out))
1213                         dbg_dc_out_info[cur_dc_out].fblistindex =
1214                                                 tegra_fb_update_modelist(dc, 0);
1215
1216                 set_avdd(dc, cur_dc_out, out_type);
1217         }
1218
1219         /* If output already created - reuse it */
1220         if (dbg_dc_out_info[out_type].out_data) {
1221                 mutex_lock(&dc->lp_lock);
1222                 mutex_lock(&dc->lock);
1223
1224                 /* Change the out type */
1225                 dc->pdata->default_out->type = out_type;
1226                 dc->out_ops = dbg_dc_out_info[out_type].out_ops;
1227                 dc->out_data = dbg_dc_out_info[out_type].out_data;
1228                 memcpy(dc->out, &dbg_dc_out_info[out_type].out,
1229                                                 sizeof(struct tegra_dc_out));
1230                 dc->mode = dbg_dc_out_info[out_type].mode;
1231
1232                 /* Re-init the resources that are destroyed for dsi */
1233                 if (is_valid_dsi_out(dc, out_type))
1234                         ret = tegra_dc_reinit_dsi_resources(dc, out_type);
1235
1236                 if (!is_valid_fake_support(dc, out_type))
1237                         tegra_fb_update_modelist(dc,
1238                                         dbg_dc_out_info[out_type].fblistindex);
1239
1240                 mutex_unlock(&dc->lock);
1241                 mutex_unlock(&dc->lp_lock);
1242
1243                 if (ret) {
1244                         dev_err(&dc->ndev->dev, "Failed to reinit!!!\n");
1245                         return -EINVAL;
1246                 }
1247
1248         } else {
1249                 /* Change the out type */
1250                 dc->pdata->default_out->type = out_type;
1251
1252                 /* create new - now restricted to fake_dp only */
1253                 if (out_type == TEGRA_DC_OUT_FAKE_DP) {
1254
1255                         /* set to default bpp */
1256                         if (!dc->pdata->default_out->depth)
1257                                 dc->pdata->default_out->depth = 24;
1258
1259                         /* DP and Fake_Dp use same data
1260                         *  Reuse if already created */
1261                         if (!dbg_dc_out_info[TEGRA_DC_OUT_DP].out_data) {
1262                                 allocate = true;
1263                                 tegra_dc_init_fakedp_panel(dc);
1264                         }
1265                 } else if ((out_type >= TEGRA_DC_OUT_FAKE_DSIA) &&
1266                                 (out_type <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) {
1267                         /* DSI and fake DSI use same data
1268                          * create new if not created yet
1269                          */
1270                         if (!dc->pdata->default_out->depth)
1271                                 dc->pdata->default_out->depth = 18;
1272
1273                         allocate = true;
1274                         tegra_dc_init_fakedsi_panel(dc, out_type);
1275
1276                 } else if (out_type == TEGRA_DC_OUT_NULL) {
1277                         if (!dbg_dc_out_info[TEGRA_DC_OUT_NULL].out_data) {
1278                                 allocate = true;
1279                                 tegra_dc_init_null_or(dc);
1280                         }
1281                 } else {
1282                         /* set  back to existing one */
1283                         dc->pdata->default_out->type = cur_dc_out;
1284                         dev_err(&dc->ndev->dev, "Unknown type is asked\n");
1285                         goto by_pass;
1286                 }
1287
1288                 if (allocate) {
1289                         ret = tegra_dc_set_out(dc, dc->pdata->default_out);
1290                                 if (ret < 0) {
1291                                         dev_err(&dc->ndev->dev,
1292                                         "Failed to initialize DC out ops\n");
1293                                         return -EINVAL;
1294                                 }
1295                 }
1296
1297                 dbg_dc_out_info[out_type].out_ops = dc->out_ops;
1298                 dbg_dc_out_info[out_type].out_data = dc->out_data;
1299                 memcpy(&dbg_dc_out_info[out_type].out, dc->out,
1300                                                 sizeof(struct tegra_dc_out));
1301
1302         }
1303
1304 by_pass:
1305         /*enable the dc and output controllers */
1306         if (!dc->enabled)
1307                 tegra_dc_enable(dc);
1308
1309         return len;
1310 }
1311 #else
1312 static ssize_t dbg_dc_out_type_set(struct file *file,
1313         const char __user *addr, size_t len, loff_t *pos)
1314 {
1315         return -EINVAL;
1316 }
1317 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1318
1319 static const struct file_operations stats_fops = {
1320         .open           = dbg_dc_stats_open,
1321         .read           = seq_read,
1322         .llseek         = seq_lseek,
1323         .release        = single_release,
1324 };
1325
1326 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
1327 {
1328         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
1329 }
1330
1331 static const struct file_operations event_inject_fops = {
1332         .open           = dbg_dc_event_inject_open,
1333         .read           = seq_read,
1334         .write          = dbg_dc_event_inject_write,
1335         .llseek         = seq_lseek,
1336         .release        = single_release,
1337 };
1338
1339 static int dbg_dc_outtype_open(struct inode *inode, struct file *file)
1340 {
1341         return single_open(file, dbg_dc_outtype_show, inode->i_private);
1342 }
1343
1344 static const struct file_operations outtype_fops = {
1345         .open           = dbg_dc_outtype_open,
1346         .read           = seq_read,
1347         .write          = dbg_dc_out_type_set,
1348         .llseek         = seq_lseek,
1349         .release        = single_release,
1350 };
1351
1352 static int dbg_edid_show(struct seq_file *s, void *unused)
1353 {
1354         struct tegra_dc *dc = s->private;
1355         struct tegra_edid *edid = dc->edid;
1356         struct tegra_dc_edid *data;
1357         u8 *buf;
1358         int i;
1359
1360         if (WARN_ON(!dc || !dc->out))
1361                 return -EINVAL;
1362
1363         if (dc->out->type == TEGRA_DC_OUT_DSI ||
1364                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIA ||
1365                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIB ||
1366                 dc->out->type == TEGRA_DC_OUT_FAKE_DSI_GANGED) {
1367                 seq_puts(s, "No EDID\n");
1368                 return 0;
1369         }
1370
1371         if (WARN_ON(!dc->edid))
1372                 return -EINVAL;
1373
1374         data = tegra_edid_get_data(edid);
1375         if (!data) {
1376                 seq_puts(s, "No EDID\n");
1377                 return 0;
1378         }
1379
1380         buf = data->buf;
1381
1382         for (i = 0; i < data->len; i++) {
1383 #ifdef DEBUG
1384                 if (i % 16 == 0)
1385                         seq_printf(s, "edid[%03x] =", i);
1386 #endif
1387
1388                 seq_printf(s, " %02x", buf[i]);
1389
1390                 if (i % 16 == 15)
1391                         seq_puts(s, "\n");
1392
1393         }
1394
1395         tegra_edid_put_data(data);
1396
1397         return 0;
1398 }
1399
1400 static int dbg_edid_open(struct inode *inode, struct file *file)
1401 {
1402         return single_open(file, dbg_edid_show, inode->i_private);
1403 }
1404
1405 static ssize_t dbg_edid_write(struct file *file,
1406 const char __user *addr, size_t len, loff_t *pos)
1407 {
1408         struct seq_file *m = file->private_data;
1409         struct tegra_dc *dc = m ? m->private : NULL;
1410         int ret;
1411
1412         if (WARN_ON(!dc || !dc->out))
1413                 return -EINVAL;
1414
1415         dc->vedid = false;
1416
1417         kfree(dc->vedid_data);
1418         dc->vedid_data = NULL;
1419
1420         if (len < 128) /* invalid edid, turn off vedid */
1421                 return 1;
1422
1423         dc->vedid_data = kmalloc(sizeof(char) * len, GFP_KERNEL);
1424         if (!dc->vedid_data) {
1425                 dev_err(&dc->ndev->dev, "no memory for edid\n");
1426                 return 0; /* dc->vedid is false */
1427         }
1428
1429         ret = copy_from_user(dc->vedid_data, addr, len);
1430         if (ret < 0) {
1431                 dev_err(&dc->ndev->dev, "error copying edid\n");
1432                 kfree(dc->vedid_data);
1433                 dc->vedid_data = NULL;
1434                 return ret; /* dc->vedid is false */
1435         }
1436
1437         dc->vedid = true;
1438
1439         return len;
1440 }
1441
1442 static const struct file_operations edid_fops = {
1443         .open           = dbg_edid_open,
1444         .read           = seq_read,
1445         .llseek         = seq_lseek,
1446         .write          = dbg_edid_write,
1447         .release        = single_release,
1448 };
1449
1450 static int dbg_hotplug_show(struct seq_file *s, void *unused)
1451 {
1452         struct tegra_dc *dc = s->private;
1453
1454         if (WARN_ON(!dc || !dc->out))
1455                 return -EINVAL;
1456
1457         rmb();
1458         seq_put_decimal_ll(s, '\0', dc->out->hotplug_state);
1459         seq_putc(s, '\n');
1460         return 0;
1461 }
1462
1463 static int dbg_hotplug_open(struct inode *inode, struct file *file)
1464 {
1465         return single_open(file, dbg_hotplug_show, inode->i_private);
1466 }
1467
1468 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
1469         size_t len, loff_t *pos)
1470 {
1471         struct seq_file *m = file->private_data; /* single_open() initialized */
1472         struct tegra_dc *dc = m ? m->private : NULL;
1473         int ret;
1474         long new_state;
1475         int hotplug_state;
1476
1477         if (WARN_ON(!dc || !dc->out))
1478                 return -EINVAL;
1479
1480         ret = kstrtol_from_user(addr, len, 10, &new_state);
1481         if (ret < 0)
1482                 return ret;
1483
1484         mutex_lock(&dc->lock);
1485         rmb();
1486         hotplug_state = dc->out->hotplug_state;
1487         if (hotplug_state == 0 && new_state != 0
1488                         && tegra_dc_hotplug_supported(dc)) {
1489                 /* was 0, now -1 or 1.
1490                  * we are overriding the hpd GPIO, so ignore the interrupt. */
1491                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1492
1493                 disable_irq(gpio_irq);
1494         } else if (hotplug_state != 0 && new_state == 0
1495                         && tegra_dc_hotplug_supported(dc)) {
1496                 /* was -1 or 1, and now 0
1497                  * restore the interrupt for hpd GPIO. */
1498                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1499
1500                 enable_irq(gpio_irq);
1501         }
1502
1503         dc->out->hotplug_state = new_state;
1504         wmb();
1505
1506         /* retrigger the hotplug */
1507         if (dc->out_ops->detect)
1508                 dc->connected = dc->out_ops->detect(dc);
1509         mutex_unlock(&dc->lock);
1510
1511         return len;
1512 }
1513
1514 static const struct file_operations dbg_hotplug_fops = {
1515         .open           = dbg_hotplug_open,
1516         .read           = seq_read,
1517         .write          = dbg_hotplug_write,
1518         .llseek         = seq_lseek,
1519         .release        = single_release,
1520 };
1521
1522 static int dbg_vrr_enable_show(struct seq_file *m, void *unused)
1523 {
1524         struct tegra_vrr *vrr = m->private;
1525
1526         if (!vrr) return -EINVAL;
1527
1528         seq_printf(m, "vrr enable state: %d\n", vrr->enable);
1529
1530         return 0;
1531 }
1532
1533 static int dbg_vrr_enable_open(struct inode *inode, struct file *file)
1534 {
1535         return single_open(file, dbg_vrr_enable_show, inode->i_private);
1536 }
1537
1538 static const struct file_operations dbg_vrr_enable_ops = {
1539         .open = dbg_vrr_enable_open,
1540         .read = seq_read,
1541         .llseek = seq_lseek,
1542         .release = single_release,
1543 };
1544
1545 static int dbg_vrr_dcb_show(struct seq_file *m, void *unused)
1546 {
1547         struct tegra_vrr *vrr = m->private;
1548
1549         if (!vrr)
1550                 return -EINVAL;
1551
1552         seq_printf(m, "vrr dc balance: %d\n", vrr->dcb);
1553
1554         return 0;
1555 }
1556
1557 static int dbg_vrr_dcb_open(struct inode *inode, struct file *file)
1558 {
1559         return single_open(file, dbg_vrr_dcb_show, inode->i_private);
1560 }
1561
1562 static const struct file_operations dbg_vrr_dcb_ops = {
1563         .open = dbg_vrr_dcb_open,
1564         .read = seq_read,
1565         .llseek = seq_lseek,
1566         .release = single_release,
1567 };
1568
1569 static int dbg_vrr_db_tolerance_show(struct seq_file *m, void *unused)
1570 {
1571         struct tegra_vrr *vrr = m->private;
1572
1573         if (!vrr)
1574                 return -EINVAL;
1575
1576         seq_printf(m, "vrr db tolerance: %d\n", vrr->db_tolerance);
1577
1578         return 0;
1579 }
1580
1581 static ssize_t dbg_vrr_db_tolerance_write(struct file *file,
1582                 const char __user *addr, size_t len, loff_t *pos)
1583 {
1584         struct seq_file *m = file->private_data;
1585         struct tegra_vrr *vrr = m->private;
1586         long   new_value;
1587         int    ret;
1588
1589         if (!vrr)
1590                 return -EINVAL;
1591
1592         ret = kstrtol_from_user(addr, len, 10, &new_value);
1593         if (ret < 0)
1594                 return ret;
1595
1596         vrr->db_tolerance = new_value;
1597
1598         return len;
1599 }
1600
1601 static int dbg_vrr_db_tolerance_open(struct inode *inode, struct file *file)
1602 {
1603         return single_open(file, dbg_vrr_db_tolerance_show, inode->i_private);
1604 }
1605
1606 static const struct file_operations dbg_vrr_db_tolerance_ops = {
1607         .open = dbg_vrr_db_tolerance_open,
1608         .read = seq_read,
1609         .write = dbg_vrr_db_tolerance_write,
1610         .llseek = seq_lseek,
1611         .release = single_release,
1612 };
1613
1614 static int dbg_vrr_frame_avg_pct_show(struct seq_file *m, void *unused)
1615 {
1616         struct tegra_vrr *vrr = m->private;
1617
1618         if (!vrr)
1619                 return -EINVAL;
1620
1621         seq_printf(m, "vrr frame average percent: %d\n", vrr->frame_avg_pct);
1622
1623         return 0;
1624 }
1625
1626 static ssize_t dbg_vrr_frame_avg_pct_write(struct file *file,
1627                 const char __user *addr, size_t len, loff_t *pos)
1628 {
1629         struct seq_file *m = file->private_data;
1630         struct tegra_vrr *vrr = m->private;
1631         long   new_pct;
1632         int    ret;
1633
1634         if (!vrr)
1635                 return -EINVAL;
1636
1637         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1638         if (ret < 0)
1639                 return ret;
1640
1641         vrr->frame_avg_pct = new_pct;
1642
1643         return len;
1644 }
1645
1646 static int dbg_vrr_frame_avg_pct_open(struct inode *inode, struct file *file)
1647 {
1648         return single_open(file, dbg_vrr_frame_avg_pct_show, inode->i_private);
1649 }
1650
1651 static const struct file_operations dbg_vrr_frame_avg_pct_ops = {
1652         .open = dbg_vrr_frame_avg_pct_open,
1653         .read = seq_read,
1654         .write = dbg_vrr_frame_avg_pct_write,
1655         .llseek = seq_lseek,
1656         .release = single_release,
1657 };
1658
1659 static int dbg_vrr_fluct_avg_pct_show(struct seq_file *m, void *unused)
1660 {
1661         struct tegra_vrr *vrr = m->private;
1662
1663         if (!vrr)
1664                 return -EINVAL;
1665
1666         seq_printf(m, "vrr fluct average percent: %d\n", vrr->fluct_avg_pct);
1667
1668         return 0;
1669 }
1670
1671 static ssize_t dbg_vrr_fluct_avg_pct_write(struct file *file,
1672                 const char __user *addr, size_t len, loff_t *pos)
1673 {
1674         struct seq_file *m = file->private_data;
1675         struct tegra_vrr *vrr = m->private;
1676         long   new_pct;
1677         int    ret;
1678
1679         if (!vrr)
1680                 return -EINVAL;
1681
1682         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1683         if (ret < 0)
1684                 return ret;
1685
1686         vrr->fluct_avg_pct = new_pct;
1687
1688         return len;
1689 }
1690
1691 static int dbg_vrr_fluct_avg_pct_open(struct inode *inode, struct file *file)
1692 {
1693         return single_open(file, dbg_vrr_fluct_avg_pct_show, inode->i_private);
1694 }
1695
1696 static const struct file_operations dbg_vrr_fluct_avg_pct_ops = {
1697         .open = dbg_vrr_fluct_avg_pct_open,
1698         .read = seq_read,
1699         .write = dbg_vrr_fluct_avg_pct_write,
1700         .llseek = seq_lseek,
1701         .release = single_release,
1702 };
1703
1704 static int dbg_tegrahw_type_show(struct seq_file *m, void *unused)
1705 {
1706         struct tegra_dc *dc = m->private;
1707
1708         if (WARN_ON(!dc || !dc->out))
1709                 return -EINVAL;
1710
1711         /* All platforms other than real silicon are taken
1712                 as simulation */
1713         seq_printf(m,
1714                 "real_silicon: %d\n",
1715                 tegra_platform_is_silicon());
1716
1717         return 0;
1718 }
1719
1720 static int dbg_tegrahw_type_open(struct inode *inode, struct file *file)
1721 {
1722         return single_open(file, dbg_tegrahw_type_show, inode->i_private);
1723 }
1724
1725 static const struct file_operations dbg_tegrahw_type_ops = {
1726         .open = dbg_tegrahw_type_open,
1727         .read = seq_read,
1728         .llseek = seq_lseek,
1729         .release = single_release,
1730 };
1731
1732 static int dbg_measure_refresh_show(struct seq_file *m, void *unused)
1733 {
1734         struct tegra_dc *dc = m->private;
1735
1736         if (WARN_ON(!dc || !dc->out))
1737                 return -EINVAL;
1738
1739         seq_puts(m, "Write capture time in seconds to this node.\n");
1740         seq_puts(m, "Results will show up in dmesg.\n");
1741
1742         return 0;
1743 }
1744
1745 static ssize_t dbg_measure_refresh_write(struct file *file,
1746                 const char __user *addr, size_t len, loff_t *pos)
1747 {
1748         struct seq_file *m = file->private_data;
1749         struct tegra_dc *dc = m->private;
1750         s32 seconds;
1751         u32 fe_count;
1752         int ret;
1753         fixed20_12 refresh_rate;
1754         fixed20_12 seconds_fixed;
1755
1756         if (WARN_ON(!dc || !dc->out))
1757                 return -EINVAL;
1758
1759         ret = kstrtoint_from_user(addr, len, 10, &seconds);
1760         if (ret < 0 || seconds < 1) {
1761                 dev_info(&dc->ndev->dev,
1762                         "specify integer number of seconds greater than 0\n");
1763                 return -EINVAL;
1764         }
1765
1766         dev_info(&dc->ndev->dev, "measuring for %d seconds\n", seconds);
1767
1768         mutex_lock(&dc->lock);
1769         _tegra_dc_config_frame_end_intr(dc, true);
1770         dc->dbg_fe_count = 0;
1771         mutex_unlock(&dc->lock);
1772
1773         msleep(1000 * seconds);
1774
1775         mutex_lock(&dc->lock);
1776         _tegra_dc_config_frame_end_intr(dc, false);
1777         fe_count = dc->dbg_fe_count;
1778         mutex_unlock(&dc->lock);
1779
1780         refresh_rate.full = dfixed_const(fe_count);
1781         seconds_fixed.full = dfixed_const(seconds);
1782         refresh_rate.full = dfixed_div(refresh_rate, seconds_fixed);
1783
1784         /* Print fixed point 20.12 in decimal, truncating the 12-bit fractional
1785            part to 2 decimal points */
1786         dev_info(&dc->ndev->dev, "refresh rate: %d.%dHz\n",
1787                 dfixed_trunc(refresh_rate),
1788                 dfixed_frac(refresh_rate) * 100 / 4096);
1789
1790         return len;
1791 }
1792
1793 static int dbg_measure_refresh_open(struct inode *inode, struct file *file)
1794 {
1795         return single_open(file, dbg_measure_refresh_show, inode->i_private);
1796 }
1797
1798 static const struct file_operations dbg_measure_refresh_ops = {
1799         .open = dbg_measure_refresh_open,
1800         .read = seq_read,
1801         .write = dbg_measure_refresh_write,
1802         .llseek = seq_lseek,
1803         .release = single_release,
1804 };
1805
1806 static int dbg_dc_cmu_lut1_show(struct seq_file *s, void *unused)
1807 {
1808         struct tegra_dc *dc = s->private;
1809         u32 val;
1810         int i;
1811
1812         mutex_lock(&dc->lock);
1813         tegra_dc_get(dc);
1814
1815         /* Disable CMU while reading LUTs */
1816         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1817         tegra_dc_writel(dc, val & ~CMU_ENABLE, DC_DISP_DISP_COLOR_CONTROL);
1818         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1819         _tegra_dc_wait_for_frame_end(dc,
1820                 div_s64(dc->frametime_ns, 1000000ll) * 2);
1821
1822         for (i = 0; i < 256; i++) {
1823                 tegra_dc_writel(dc, LUT1_READ_EN | LUT1_READ_ADDR(i),
1824                         DC_COM_CMU_LUT1_READ);
1825
1826                 seq_printf(s, "%lu\n",
1827                         LUT1_READ_DATA(tegra_dc_readl(dc, DC_COM_CMU_LUT1)));
1828         }
1829         tegra_dc_writel(dc, 0, DC_COM_CMU_LUT1_READ);
1830
1831         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1832         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1833
1834         tegra_dc_put(dc);
1835         mutex_unlock(&dc->lock);
1836         return 0;
1837 }
1838
1839 static int dbg_dc_cmu_lut1_open(struct inode *inode, struct file *file)
1840 {
1841         return single_open(file, dbg_dc_cmu_lut1_show, inode->i_private);
1842 }
1843
1844 static const struct file_operations cmu_lut1_fops = {
1845         .open           = dbg_dc_cmu_lut1_open,
1846         .read           = seq_read,
1847         .llseek         = seq_lseek,
1848         .release        = single_release,
1849 };
1850
1851 static int dbg_dc_cmu_lut2_show(struct seq_file *s, void *unused)
1852 {
1853         struct tegra_dc *dc = s->private;
1854         u32 val;
1855         int i;
1856
1857         mutex_lock(&dc->lock);
1858         tegra_dc_get(dc);
1859
1860         /* Disable CMU while reading LUTs */
1861         val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1862         tegra_dc_writel(dc, val & ~CMU_ENABLE, DC_DISP_DISP_COLOR_CONTROL);
1863         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1864         _tegra_dc_wait_for_frame_end(dc,
1865                 div_s64(dc->frametime_ns, 1000000ll) * 2);
1866
1867         for (i = 0; i < 960; i++) {
1868                 tegra_dc_writel(dc, LUT2_READ_EN | LUT2_READ_ADDR(i),
1869                         DC_COM_CMU_LUT2_READ);
1870
1871                 seq_printf(s, "%lu\n",
1872                         LUT2_READ_DATA(tegra_dc_readl(dc, DC_COM_CMU_LUT2)));
1873         }
1874         tegra_dc_writel(dc, 0, DC_COM_CMU_LUT2_READ);
1875
1876         tegra_dc_writel(dc, val, DC_DISP_DISP_COLOR_CONTROL);
1877         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1878
1879         tegra_dc_put(dc);
1880         mutex_unlock(&dc->lock);
1881         return 0;
1882 }
1883
1884 static int dbg_dc_cmu_lut2_open(struct inode *inode, struct file *file)
1885 {
1886         return single_open(file, dbg_dc_cmu_lut2_show, inode->i_private);
1887 }
1888
1889 static const struct file_operations cmu_lut2_fops = {
1890         .open           = dbg_dc_cmu_lut2_open,
1891         .read           = seq_read,
1892         .llseek         = seq_lseek,
1893         .release        = single_release,
1894 };
1895
1896 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
1897 {
1898         if (dc->debugdir)
1899                 debugfs_remove_recursive(dc->debugdir);
1900         dc->debugdir = NULL;
1901 }
1902
1903 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
1904 {
1905         struct dentry *retval, *vrrdir;
1906         char   devname[50];
1907
1908         snprintf(devname, sizeof(devname), "tegradc.%d", dc->ctrl_num);
1909         dc->debugdir = debugfs_create_dir(devname, NULL);
1910         if (!dc->debugdir)
1911                 goto remove_out;
1912
1913         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
1914                 &regs_fops);
1915         if (!retval)
1916                 goto remove_out;
1917
1918         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
1919                 &mode_fops);
1920         if (!retval)
1921                 goto remove_out;
1922
1923         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
1924                 &stats_fops);
1925         if (!retval)
1926                 goto remove_out;
1927
1928         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
1929                 &event_inject_fops);
1930         if (!retval)
1931                 goto remove_out;
1932
1933         retval = debugfs_create_file("out_type", S_IRUGO, dc->debugdir, dc,
1934                 &outtype_fops);
1935         if (!retval)
1936                 goto remove_out;
1937
1938         retval = debugfs_create_file("edid", S_IRUGO, dc->debugdir, dc,
1939                 &edid_fops);
1940         if (!retval)
1941                 goto remove_out;
1942
1943         if (dc->out_ops->detect) {
1944                 /* only create the file if hotplug is supported */
1945                 retval = debugfs_create_file("hotplug", S_IRUGO, dc->debugdir,
1946                         dc, &dbg_hotplug_fops);
1947                 if (!retval)
1948                         goto remove_out;
1949         }
1950
1951         vrrdir = debugfs_create_dir("vrr",  dc->debugdir);
1952         if (!vrrdir)
1953                 goto remove_out;
1954
1955         retval = debugfs_create_file("enable", S_IRUGO, vrrdir,
1956                                 dc->out->vrr, &dbg_vrr_enable_ops);
1957         if (!retval)
1958                 goto remove_out;
1959
1960         retval = debugfs_create_file("dcb", S_IRUGO, vrrdir,
1961                                 dc->out->vrr, &dbg_vrr_dcb_ops);
1962         if (!retval)
1963                 goto remove_out;
1964
1965         retval = debugfs_create_file("frame_avg_pct", S_IRUGO, vrrdir,
1966                                 dc->out->vrr, &dbg_vrr_frame_avg_pct_ops);
1967         if (!retval)
1968                 goto remove_out;
1969
1970         retval = debugfs_create_file("fluct_avg_pct", S_IRUGO, vrrdir,
1971                                 dc->out->vrr, &dbg_vrr_fluct_avg_pct_ops);
1972         if (!retval)
1973                 goto remove_out;
1974
1975         retval = debugfs_create_file("tegrahw_type", S_IRUGO, dc->debugdir,
1976                                 dc, &dbg_tegrahw_type_ops);
1977         if (!retval)
1978                 goto remove_out;
1979
1980         retval = debugfs_create_file("measure_refresh", S_IRUGO, dc->debugdir,
1981                                 dc, &dbg_measure_refresh_ops);
1982         if (!retval)
1983                 goto remove_out;
1984
1985         retval = debugfs_create_file("cmu_lut1", S_IRUGO, dc->debugdir, dc,
1986                 &cmu_lut1_fops);
1987         if (!retval)
1988                 goto remove_out;
1989
1990         retval = debugfs_create_file("cmu_lut2", S_IRUGO, dc->debugdir, dc,
1991                 &cmu_lut2_fops);
1992         if (!retval)
1993                 goto remove_out;
1994
1995         return;
1996 remove_out:
1997         dev_err(&dc->ndev->dev, "could not create debugfs\n");
1998         tegra_dc_remove_debugfs(dc);
1999 }
2000
2001 #else /* !CONFIG_DEBUGFS */
2002 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
2003 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
2004 #endif /* CONFIG_DEBUGFS */
2005
2006 s32 tegra_dc_calc_v_front_porch(struct tegra_dc_mode *mode,
2007                                 int desired_fps)
2008 {
2009         int vfp = 0;
2010
2011         if (desired_fps > 0) {
2012                 int line = mode->h_sync_width + mode->h_back_porch +
2013                         mode->h_active + mode->h_front_porch;
2014                 int lines_per_frame = mode->pclk / line / desired_fps;
2015                 vfp = lines_per_frame - mode->v_sync_width -
2016                         mode->v_active - mode->v_back_porch;
2017         }
2018
2019         return vfp;
2020 }
2021
2022 static void tegra_dc_setup_vrr(struct tegra_dc *dc)
2023 {
2024         int lines_per_frame_max, lines_per_frame_min;
2025
2026         struct tegra_dc_mode *m;
2027         struct tegra_vrr *vrr  = dc->out->vrr;
2028
2029         if (!vrr) return;
2030
2031         m = &dc->out->modes[dc->out->n_modes-1];
2032         vrr->v_front_porch = m->v_front_porch;
2033         vrr->v_back_porch = m->v_back_porch;
2034         vrr->pclk = m->pclk;
2035
2036         if (vrr->vrr_min_fps > 0)
2037                 vrr->v_front_porch_max = tegra_dc_calc_v_front_porch(m,
2038                                 vrr->vrr_min_fps);
2039
2040         vrr->vrr_max_fps =
2041                 (s32)div_s64(NSEC_PER_SEC, dc->frametime_ns);
2042
2043         vrr->v_front_porch_min = m->v_front_porch;
2044
2045         vrr->line_width = m->h_sync_width + m->h_back_porch +
2046                         m->h_active + m->h_front_porch;
2047         vrr->lines_per_frame_common = m->v_sync_width +
2048                         m->v_back_porch + m->v_active;
2049         lines_per_frame_max = vrr->lines_per_frame_common +
2050                         vrr->v_front_porch_max;
2051         lines_per_frame_min = vrr->lines_per_frame_common +
2052                         vrr->v_front_porch_min;
2053
2054         if (lines_per_frame_max < 2*lines_per_frame_min) {
2055                 pr_err("max fps is less than 2 times min fps.\n");
2056                 return;
2057         }
2058
2059         vrr->frame_len_max = vrr->line_width * lines_per_frame_max /
2060                                         (m->pclk / 1000000);
2061         vrr->frame_len_min = vrr->line_width * lines_per_frame_min /
2062                                         (m->pclk / 1000000);
2063         vrr->vfp_extend = vrr->v_front_porch_max;
2064         vrr->vfp_shrink = vrr->v_front_porch_min;
2065
2066         vrr->frame_type = 0;
2067         vrr->frame_delta_us = 0;
2068
2069         vrr->max_adj_pct = 50;
2070         vrr->max_flip_pct = 20;
2071         vrr->max_dcb = 20000;
2072         vrr->max_inc_pct = 5;
2073
2074         vrr->dcb = 0;
2075         vrr->frame_avg_pct = 75;
2076         vrr->fluct_avg_pct = 75;
2077         vrr->db_tolerance = 5000;
2078 }
2079
2080 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
2081                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
2082 {
2083         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
2084         u32 reg_val = 0;
2085
2086         if (tegra_platform_is_linsim())
2087                 return 0;
2088
2089         do {
2090                 usleep_range(poll_interval_us, poll_interval_us << 1);
2091                 reg_val = tegra_dc_readl(dc, reg);
2092         } while (((reg_val & mask) != exp_val) &&
2093                 time_after(timeout_jf, jiffies));
2094
2095         if ((reg_val & mask) == exp_val)
2096                 return 0;       /* success */
2097         dev_err(&dc->ndev->dev,
2098                 "dc_poll_register 0x%x: timeout\n", reg);
2099         return jiffies - timeout_jf + 1;
2100 }
2101
2102
2103 void tegra_dc_enable_general_act(struct tegra_dc *dc)
2104 {
2105         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2106
2107         if (tegra_dc_poll_register(dc, DC_CMD_STATE_CONTROL,
2108                 GENERAL_ACT_REQ, 0, 1,
2109                 TEGRA_DC_POLL_TIMEOUT_MS))
2110                 dev_err(&dc->ndev->dev,
2111                         "dc timeout waiting for DC to stop\n");
2112 }
2113
2114
2115 static int tegra_dc_set_next(struct tegra_dc *dc)
2116 {
2117         int i;
2118         int ret = -EBUSY;
2119
2120         mutex_lock(&tegra_dc_lock);
2121
2122         for (i = 0; i < TEGRA_MAX_DC; i++) {
2123                 if (tegra_dcs[i] == NULL) {
2124                         tegra_dcs[i] = dc;
2125                         ret = i;
2126                         break;
2127                 }
2128         }
2129
2130         mutex_unlock(&tegra_dc_lock);
2131
2132         return ret;
2133 }
2134
2135 static int tegra_dc_set_idx(struct tegra_dc *dc, int index)
2136 {
2137         int ret = 0;
2138
2139         mutex_lock(&tegra_dc_lock);
2140         if (index >= TEGRA_MAX_DC) {
2141                 ret = -EINVAL;
2142                 goto out;
2143         }
2144
2145         if (dc != NULL && tegra_dcs[index] != NULL) {
2146                 ret = -EBUSY;
2147                 goto out;
2148         }
2149
2150         tegra_dcs[index] = dc;
2151
2152 out:
2153         mutex_unlock(&tegra_dc_lock);
2154
2155         return ret;
2156 }
2157
2158 /*
2159  * If index == -1, set dc at next available index. This is to be called only
2160  * when registering dc in DT case. For non DT case & when removing the device
2161  * (dc == NULL), index should be accordingly.
2162  */
2163 static int tegra_dc_set(struct tegra_dc *dc, int index)
2164 {
2165         if ((index == -1) && (dc != NULL)) /* DT register case */
2166                 return tegra_dc_set_next(dc);
2167         else /* non DT, unregister case */
2168                 return tegra_dc_set_idx(dc, index);
2169 }
2170
2171 unsigned int tegra_dc_has_multiple_dc(void)
2172 {
2173         unsigned int idx;
2174         unsigned int cnt = 0;
2175         struct tegra_dc *dc;
2176
2177         mutex_lock(&tegra_dc_lock);
2178         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
2179                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
2180         mutex_unlock(&tegra_dc_lock);
2181
2182         return (cnt > 1);
2183 }
2184
2185 /* get the stride size of a window.
2186  * return: stride size in bytes for window win. or 0 if unavailble. */
2187 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
2188 {
2189         u32 stride;
2190
2191         if (!dc->enabled)
2192                 return 0;
2193         BUG_ON(win > DC_N_WINDOWS);
2194         mutex_lock(&dc->lock);
2195         tegra_dc_get(dc);
2196         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
2197                 DC_CMD_DISPLAY_WINDOW_HEADER);
2198 #ifdef CONFIG_TEGRA_NVDISPLAY
2199         stride = tegra_nvdisp_get_linestride(dc, win);
2200 #else
2201         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
2202 #endif
2203         tegra_dc_put(dc);
2204         mutex_unlock(&dc->lock);
2205         return GET_LINE_STRIDE(stride);
2206 }
2207 EXPORT_SYMBOL(tegra_dc_get_stride);
2208
2209 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
2210 {
2211         if (idx < TEGRA_MAX_DC)
2212                 return tegra_dcs[idx];
2213         else
2214                 return NULL;
2215 }
2216 EXPORT_SYMBOL(tegra_dc_get_dc);
2217
2218 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
2219 {
2220         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
2221                 return NULL;
2222
2223 #ifdef CONFIG_TEGRA_NVDISPLAY
2224         return &tegra_dc_windows[win];
2225 #else
2226         return &dc->windows[win];
2227 #endif
2228 }
2229 EXPORT_SYMBOL(tegra_dc_get_window);
2230
2231 bool tegra_dc_get_connected(struct tegra_dc *dc)
2232 {
2233         return dc->connected;
2234 }
2235 EXPORT_SYMBOL(tegra_dc_get_connected);
2236
2237 bool tegra_dc_hpd(struct tegra_dc *dc)
2238 {
2239         int hpd = false;
2240         int hotplug_state;
2241
2242         if (WARN_ON(!dc || !dc->out))
2243                 return false;
2244
2245         rmb();
2246         hotplug_state = dc->out->hotplug_state;
2247
2248         if (hotplug_state != TEGRA_HPD_STATE_NORMAL) {
2249                 if (hotplug_state == TEGRA_HPD_STATE_FORCE_ASSERT)
2250                         return true;
2251                 if (hotplug_state == TEGRA_HPD_STATE_FORCE_DEASSERT)
2252                         return false;
2253         }
2254
2255         if (!tegra_dc_hotplug_supported(dc))
2256                 return true;
2257
2258         if (dc->out_ops && dc->out_ops->hpd_state)
2259                 hpd = dc->out_ops->hpd_state(dc);
2260
2261         if (dc->out->hotplug_report)
2262                 dc->out->hotplug_report(hpd);
2263
2264         return hpd;
2265 }
2266 EXPORT_SYMBOL(tegra_dc_hpd);
2267
2268 #ifndef CONFIG_TEGRA_NVDISPLAY
2269 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
2270 {
2271         unsigned i;
2272         unsigned v0 = 128;
2273         unsigned v1 = 0;
2274
2275         /* linear horizontal and vertical filters */
2276         for (i = 0; i < 16; i++) {
2277                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
2278                                 DC_WIN_H_FILTER_P(i));
2279
2280                 tegra_dc_writel(dc, v0,
2281                                 DC_WIN_V_FILTER_P(i));
2282                 v0 -= 8;
2283                 v1 += 8;
2284         }
2285 }
2286 #endif
2287
2288 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
2289 {
2290         tegra_dc_io_start(dc);
2291         if (enable) {
2292                 atomic_inc(&dc->frame_end_ref);
2293                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
2294         } else if (!atomic_dec_return(&dc->frame_end_ref))
2295                 tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2296         tegra_dc_io_end(dc);
2297
2298         return 0;
2299 }
2300
2301 #if defined(CONFIG_TEGRA_DC_CMU) || defined(CONFIG_TEGRA_DC_CMU_V2)
2302 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
2303 {
2304         if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
2305                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIA ||
2306                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIB ||
2307                 dc->out->type == TEGRA_DC_OUT_FAKE_DSI_GANGED ||
2308                 dc->out->type == TEGRA_DC_OUT_NULL)
2309                 return &default_cmu;
2310         if (dc->pdata->cmu && !dc->pdata->default_clr_space)
2311                 return dc->pdata->cmu;
2312         else if (dc->pdata->cmu_adbRGB && dc->pdata->default_clr_space)
2313                 return dc->pdata->cmu_adbRGB;
2314         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
2315                 return &default_limited_cmu;
2316         else
2317                 return &default_cmu;
2318 }
2319
2320 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
2321 {
2322         dc->cmu_enabled = cmu_enable;
2323 #if defined(CONFIG_TEGRA_NVDISPLAY)
2324         tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
2325         tegra_nvdisp_update_cmu(dc, &dc->cmu);
2326 #else
2327         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2328 #endif
2329 }
2330 EXPORT_SYMBOL(tegra_dc_cmu_enable);
2331 #else
2332 #define tegra_dc_cmu_enable(dc, cmu_enable)
2333 #endif
2334
2335 #ifdef CONFIG_TEGRA_DC_CMU
2336 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
2337                                 struct tegra_dc_cmu *src_cmu)
2338 {
2339         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
2340                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
2341         dc->cmu_dirty = true;
2342 }
2343
2344 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2345 {
2346         u32 val;
2347         u32 i;
2348
2349         for (i = 0; i < 256; i++) {
2350                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
2351                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
2352         }
2353
2354         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
2355         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
2356         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
2357         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
2358         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
2359         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
2360         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
2361         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
2362         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
2363
2364         for (i = 0; i < 960; i++) {
2365                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
2366                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
2367         }
2368
2369         dc->cmu_dirty = false;
2370 }
2371
2372 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2373 {
2374         u32 val;
2375
2376         if (!dc->cmu_enabled)
2377                 return;
2378
2379         tegra_dc_cache_cmu(dc, cmu);
2380
2381         if (dc->cmu_dirty) {
2382                 /* Disable CMU to avoid programming it while it is in use */
2383                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2384                 if (val & CMU_ENABLE) {
2385                         val &= ~CMU_ENABLE;
2386                         tegra_dc_writel(dc, val,
2387                                         DC_DISP_DISP_COLOR_CONTROL);
2388                         val = GENERAL_ACT_REQ;
2389                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
2390                         /*TODO: Sync up with vsync */
2391                         mdelay(20);
2392                 }
2393                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
2394                         dc->cmu_dirty);
2395
2396                 tegra_dc_set_cmu(dc, &dc->cmu);
2397         }
2398 }
2399
2400 void _tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
2401 {
2402         /* If cmu_enable matches with the existing cmu state,
2403          * do not perform an update else it breaks seamless
2404          */
2405         if (dc->cmu_enabled == cmu_enable)
2406                 return;
2407         dc->cmu_enabled = cmu_enable;
2408         _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2409         tegra_dc_set_color_control(dc);
2410         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2411 }
2412
2413 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2414 {
2415         mutex_lock(&dc->lock);
2416         if (!dc->enabled) {
2417                 mutex_unlock(&dc->lock);
2418                 return 0;
2419         }
2420
2421         tegra_dc_get(dc);
2422
2423         _tegra_dc_update_cmu(dc, cmu);
2424         tegra_dc_set_color_control(dc);
2425         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2426
2427         tegra_dc_put(dc);
2428         mutex_unlock(&dc->lock);
2429
2430         return 0;
2431 }
2432 EXPORT_SYMBOL(tegra_dc_update_cmu);
2433
2434 static int _tegra_dc_update_cmu_aligned(struct tegra_dc *dc,
2435                                 struct tegra_dc_cmu *cmu,
2436                                 bool force)
2437 {
2438         memcpy(&dc->cmu_shadow, cmu, sizeof(dc->cmu));
2439         dc->cmu_shadow_dirty = true;
2440         dc->cmu_shadow_force_update = dc->cmu_shadow_force_update || force;
2441         _tegra_dc_config_frame_end_intr(dc, true);
2442
2443         return 0;
2444 }
2445
2446 int tegra_dc_update_cmu_aligned(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2447 {
2448         int ret;
2449
2450         mutex_lock(&dc->lock);
2451         if (!dc->enabled) {
2452                 mutex_unlock(&dc->lock);
2453                 return 0;
2454         }
2455         ret = _tegra_dc_update_cmu_aligned(dc, cmu, false);
2456         mutex_unlock(&dc->lock);
2457
2458         return ret;
2459 }
2460
2461 EXPORT_SYMBOL(tegra_dc_update_cmu_aligned);
2462 #else
2463 #define tegra_dc_cache_cmu(dc, src_cmu)
2464 #define tegra_dc_set_cmu(dc, cmu)
2465 #define tegra_dc_update_cmu(dc, cmu)
2466 #define _tegra_dc_enable_cmu(dc, cmu)
2467 #define tegra_dc_update_cmu_aligned(dc, cmu)
2468 #endif
2469
2470 int tegra_dc_set_hdr(struct tegra_dc *dc, struct tegra_dc_hdr *hdr,
2471                                                 bool cache_dirty)
2472 {
2473         int ret;
2474
2475         mutex_lock(&dc->lock);
2476
2477         if (!dc->enabled) {
2478                 mutex_unlock(&dc->lock);
2479                 return 0;
2480         }
2481         trace_hdr_data_update(dc, hdr);
2482         if (cache_dirty) {
2483                 dc->hdr.eotf = hdr->eotf;
2484                 dc->hdr.static_metadata_id = hdr->static_metadata_id;
2485                 memcpy(dc->hdr.static_metadata, hdr->static_metadata,
2486                                         sizeof(dc->hdr.static_metadata));
2487         } else if (dc->hdr.enabled == hdr->enabled) {
2488                 mutex_unlock(&dc->lock);
2489                 return 0;
2490         }
2491         dc->hdr.enabled = hdr->enabled;
2492         dc->hdr_cache_dirty = true;
2493         if (!dc->hdr.enabled)
2494                 memset(&dc->hdr, 0, sizeof(dc->hdr));
2495         ret = _tegra_dc_config_frame_end_intr(dc, true);
2496
2497         mutex_unlock(&dc->lock);
2498         return ret;
2499 }
2500 EXPORT_SYMBOL(tegra_dc_set_hdr);
2501
2502 /* disable_irq() blocks until handler completes, calling this function while
2503  * holding dc->lock can deadlock. */
2504 static inline void disable_dc_irq(const struct tegra_dc *dc)
2505 {
2506         disable_irq(dc->irq);
2507 }
2508
2509 u32 tegra_dc_get_syncpt_id(struct tegra_dc *dc, int i)
2510 {
2511         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2512         BUG_ON(!win);
2513         return win->syncpt.id;
2514 }
2515 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
2516
2517 static u32 tegra_dc_incr_syncpt_max_locked(struct tegra_dc *dc, int i)
2518 {
2519         u32 max;
2520         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2521
2522         BUG_ON(!win);
2523         max = nvhost_syncpt_incr_max_ext(dc->ndev,
2524                 win->syncpt.id, ((dc->enabled) ? 1 : 0));
2525         win->syncpt.max = max;
2526
2527         return max;
2528 }
2529
2530 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
2531 {
2532         u32 max;
2533
2534         mutex_lock(&dc->lock);
2535         tegra_dc_get(dc);
2536         max = tegra_dc_incr_syncpt_max_locked(dc, i);
2537         tegra_dc_put(dc);
2538         mutex_unlock(&dc->lock);
2539
2540         return max;
2541 }
2542
2543 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
2544 {
2545         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2546
2547         BUG_ON(!win);
2548         mutex_lock(&dc->lock);
2549
2550         tegra_dc_get(dc);
2551         while (win->syncpt.min < val) {
2552                 win->syncpt.min++;
2553                 nvhost_syncpt_cpu_incr_ext(dc->ndev, win->syncpt.id);
2554                 }
2555         tegra_dc_put(dc);
2556         mutex_unlock(&dc->lock);
2557 }
2558
2559 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
2560 {
2561         struct nvhost_ctrl_sync_fence_info syncpt;
2562         u32 id = tegra_dc_get_syncpt_id(dc, i);
2563
2564         syncpt.id = id;
2565         syncpt.thresh = val;
2566         return nvhost_sync_create_fence(
2567                         to_platform_device(dc->ndev->dev.parent),
2568                         &syncpt, 1, dev_name(&dc->ndev->dev));
2569 }
2570
2571 void
2572 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
2573 {
2574         unsigned int ctrl;
2575         unsigned long out_sel;
2576         unsigned long cmd_state;
2577
2578         mutex_lock(&dc->lock);
2579         if (!dc->enabled) {
2580                 mutex_unlock(&dc->lock);
2581                 return;
2582         }
2583
2584         tegra_dc_get(dc);
2585
2586         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
2587                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
2588                 cfg->clk_select);
2589
2590         /* The new value should be effected immediately */
2591         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
2592         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
2593
2594         switch (cfg->which_pwm) {
2595         case TEGRA_PWM_PM0:
2596                 /* Select the LM0 on PM0 */
2597                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2598                 out_sel &= ~(7 << 0);
2599                 out_sel |= (3 << 0);
2600                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2601                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2602                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2603                 break;
2604         case TEGRA_PWM_PM1:
2605                 /* Select the LM1 on PM1 */
2606                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2607                 out_sel &= ~(7 << 4);
2608                 out_sel |= (3 << 4);
2609                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2610                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2611                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2612                 break;
2613         default:
2614                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2615                 break;
2616         }
2617         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2618         tegra_dc_put(dc);
2619         mutex_unlock(&dc->lock);
2620 }
2621 EXPORT_SYMBOL(tegra_dc_config_pwm);
2622
2623 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2624                                 const struct tegra_dc_out_pin *pins,
2625                                 const unsigned int n_pins)
2626 {
2627         unsigned int i;
2628
2629         int name;
2630         int pol;
2631
2632         u32 pol1, pol3;
2633
2634         u32 set1, unset1;
2635         u32 set3, unset3;
2636
2637         set1 = set3 = unset1 = unset3 = 0;
2638
2639         for (i = 0; i < n_pins; i++) {
2640                 name = (pins + i)->name;
2641                 pol  = (pins + i)->pol;
2642
2643                 /* set polarity by name */
2644                 switch (name) {
2645                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2646                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2647                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2648                         else
2649                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2650                         break;
2651                 case TEGRA_DC_OUT_PIN_H_SYNC:
2652                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2653                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2654                         else
2655                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2656                         break;
2657                 case TEGRA_DC_OUT_PIN_V_SYNC:
2658                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2659                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2660                         else
2661                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2662                         break;
2663                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2664                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2665                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2666                         else
2667                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2668                         break;
2669                 default:
2670                         printk("Invalid argument in function %s\n",
2671                                __FUNCTION__);
2672                         break;
2673                 }
2674         }
2675
2676         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2677         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2678
2679         pol1 |= set1;
2680         pol1 &= ~unset1;
2681
2682         pol3 |= set3;
2683         pol3 &= ~unset3;
2684
2685         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2686         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2687 }
2688
2689 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
2690 {
2691         unsigned long refresh;
2692
2693         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2694                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2695
2696                 /* For seamless HDMI, read mode parameters from bootloader
2697                  * set DC configuration
2698                  */
2699                 u32 val = 0;
2700                 struct tegra_dc_mode *mode = &override_disp_mode[dc->out->type];
2701 #ifdef CONFIG_TEGRA_NVDISPLAY
2702                 struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
2703                                 dc->out->parent_clk ? : "plld2");
2704 #else
2705                 struct clk *parent_clk = clk_get_sys(NULL,
2706                                 dc->out->parent_clk ? : "pll_d2");
2707 #endif
2708                 memset(mode, 0, sizeof(struct tegra_dc_mode));
2709                 mode->pclk = clk_get_rate(parent_clk);
2710                 mode->rated_pclk = 0;
2711
2712                 tegra_dc_get(dc);
2713                 val = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
2714                 mode->h_ref_to_sync = val & 0xffff;
2715                 mode->v_ref_to_sync = (val >> 16) & 0xffff;
2716
2717                 val = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
2718                 mode->h_sync_width = val & 0xffff;
2719                 mode->v_sync_width = (val >> 16) & 0xffff;
2720
2721                 val = tegra_dc_readl(dc, DC_DISP_BACK_PORCH);
2722                 mode->h_back_porch = val & 0xffff;
2723                 mode->v_back_porch = (val >> 16) & 0xffff;
2724
2725                 val = tegra_dc_readl(dc, DC_DISP_FRONT_PORCH);
2726                 mode->h_front_porch = val & 0xffff;
2727                 mode->v_front_porch = (val >> 16) & 0xffff;
2728
2729                 val = tegra_dc_readl(dc, DC_DISP_DISP_ACTIVE);
2730                 mode->h_active = val & 0xffff;
2731                 mode->v_active = (val >> 16) & 0xffff;
2732
2733                 /*
2734                  * Implicit contract between BL and us. If CMU is enabled,
2735                  * assume limited range. This sort of works because we know
2736                  * BL doesn't support YUV
2737                  */
2738                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2739                 if (val & CMU_ENABLE)
2740                         mode->vmode |= FB_VMODE_LIMITED_RANGE;
2741
2742                 /* Check the freq setup by the BL, 59.94 or 60Hz
2743                  * If 59.94, vmode needs to be FB_VMODE_1000DIV1001
2744                  * for seamless
2745                  */
2746                 refresh = tegra_dc_calc_refresh(mode);
2747                 if (refresh % 1000)
2748                         mode->vmode |= FB_VMODE_1000DIV1001;
2749
2750                 tegra_dc_put(dc);
2751         }
2752
2753         if (dc->out->type == TEGRA_DC_OUT_RGB  ||
2754                 dc->out->type == TEGRA_DC_OUT_HDMI ||
2755                 dc->out->type == TEGRA_DC_OUT_DSI  ||
2756                 dc->out->type == TEGRA_DC_OUT_NULL)
2757                 return override_disp_mode[dc->out->type].pclk ?
2758                         &override_disp_mode[dc->out->type] : NULL;
2759         else
2760                 return NULL;
2761 }
2762
2763 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2764 {
2765         struct tegra_dc_mode *mode;
2766         int err = 0;
2767
2768         dc->out = out;
2769
2770         tegra_dc_set_sor_instance(dc, dc->out->type);
2771
2772         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2773                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2774                 /*
2775                  * Bootloader enables clk and host1x in seamless
2776                  * usecase. Below extra reference accounts for it
2777                  */
2778                 tegra_dc_get(dc);
2779         }
2780 /*
2781  * This config enables seamless feature only for
2782  * android usecase as a WAR for improper DSI initialization
2783  * in bootloader for L4T usecase.
2784  * Bug 200122858
2785  */
2786 #ifdef CONFIG_ANDROID
2787         /*
2788          * Seamless supporting panels can work in seamless mode
2789          * only if BL initializes DC/DSI. If not, panel should
2790          * go with complete initialization.
2791          */
2792         if (dc->out->type == TEGRA_DC_OUT_DSI &&
2793                         !tegra_is_bl_display_initialized(dc->ndev->id)) {
2794                 dc->initialized = false;
2795         } else if (dc->out->type == TEGRA_DC_OUT_DSI &&
2796                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2797                 dc->initialized = true;
2798         }
2799 #endif
2800         mode = tegra_dc_get_override_mode(dc);
2801
2802         if (mode) {
2803                 tegra_dc_set_mode(dc, mode);
2804
2805                 /*
2806                  * Bootloader should and should only pass disp_params if
2807                  * it has initialized display controller.  Whenever we see
2808                  * override modes, we should skip things cause display resets.
2809                  */
2810                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
2811                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
2812                                 dc->mode.h_active, dc->mode.v_active,
2813                                 dc->out->h_size, dc->out->v_size,
2814                                 dc->mode.pclk);
2815                 dc->initialized = true;
2816         } else if (out->n_modes > 0) {
2817                 /* For VRR panels, default mode is first in the list,
2818                  * and native panel mode is the last.
2819                  * Initialization must occur using the native panel mode. */
2820                 if (dc->out->vrr) {
2821                         tegra_dc_set_mode(dc,
2822                                 &dc->out->modes[dc->out->n_modes-1]);
2823                         tegra_dc_setup_vrr(dc);
2824                 } else
2825                         tegra_dc_set_mode(dc, &dc->out->modes[0]);
2826         }
2827
2828         switch (out->type) {
2829         case TEGRA_DC_OUT_RGB:
2830                 dc->out_ops = &tegra_dc_rgb_ops;
2831                 break;
2832
2833         case TEGRA_DC_OUT_HDMI:
2834 #if     defined(CONFIG_TEGRA_HDMI2_0)
2835                 dc->out_ops = &tegra_dc_hdmi2_0_ops;
2836 #elif defined(CONFIG_TEGRA_HDMI)
2837                 dc->out_ops = &tegra_dc_hdmi_ops;
2838 #endif
2839 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2840                 if (tegra_bonded_out_dev(BOND_OUT_SOR1)) {
2841                         dev_info(&dc->ndev->dev,
2842                                 "SOR1 instance is bonded out\n");
2843                         dc->out_ops = NULL;
2844                         err = -ENODEV;
2845                 }
2846 #endif
2847                 break;
2848
2849         case TEGRA_DC_OUT_DSI:
2850         case TEGRA_DC_OUT_FAKE_DSIA:
2851         case TEGRA_DC_OUT_FAKE_DSIB:
2852         case TEGRA_DC_OUT_FAKE_DSI_GANGED:
2853                 dc->out_ops = &tegra_dc_dsi_ops;
2854 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2855                 if (tegra_bonded_out_dev(BOND_OUT_DSI) ||
2856                         tegra_bonded_out_dev(BOND_OUT_DSIB)) {
2857                         dev_info(&dc->ndev->dev,
2858                                 "DSI instance is bonded out\n");
2859                         dc->out_ops = NULL;
2860                         err = -ENODEV;
2861                 }
2862 #endif
2863                 break;
2864
2865 #ifdef CONFIG_TEGRA_DP
2866         case TEGRA_DC_OUT_FAKE_DP:
2867         case TEGRA_DC_OUT_DP:
2868                 dc->out_ops = &tegra_dc_dp_ops;
2869                 break;
2870 #ifdef CONFIG_TEGRA_NVSR
2871         case TEGRA_DC_OUT_NVSR_DP:
2872                 dc->out_ops = &tegra_dc_nvsr_ops;
2873                 break;
2874 #endif
2875 #endif
2876 #ifdef CONFIG_TEGRA_LVDS
2877         case TEGRA_DC_OUT_LVDS:
2878                 dc->out_ops = &tegra_dc_lvds_ops;
2879                 break;
2880 #endif
2881 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
2882         case TEGRA_DC_OUT_NULL:
2883                 dc->out_ops = &tegra_dc_null_ops;
2884                 break;
2885 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
2886
2887         default:
2888                 dc->out_ops = NULL;
2889                 break;
2890         }
2891
2892 #ifdef CONFIG_TEGRA_DC_CMU
2893         tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
2894 #endif
2895
2896         if (dc->out_ops && dc->out_ops->init) {
2897                 err = dc->out_ops->init(dc);
2898                 if (err < 0) {
2899                         dc->out = NULL;
2900                         dc->out_ops = NULL;
2901                         dev_err(&dc->ndev->dev,
2902                                 "Error: out->type:%d out_ops->init() failed\n",
2903                                 out->type);
2904                         return err;
2905                 }
2906         }
2907
2908         return err;
2909 }
2910
2911 int tegra_dc_get_head(const struct tegra_dc *dc)
2912 {
2913         if (dc)
2914                 return dc->ctrl_num;
2915         return -EINVAL;
2916 }
2917
2918 /* returns on error: -EINVAL
2919  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, ... */
2920 int tegra_dc_get_out(const struct tegra_dc *dc)
2921 {
2922         if (dc && dc->out)
2923                 return dc->out->type;
2924         return -EINVAL;
2925 }
2926
2927 bool tegra_dc_is_ext_dp_panel(const struct tegra_dc *dc)
2928 {
2929         if (dc && dc->out)
2930                 return dc->out->is_ext_dp_panel;
2931         return false;
2932 }
2933
2934 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2935 {
2936         unsigned height = 0;
2937
2938         if (dc->out) {
2939                 if (dc->out->height)
2940                         height = dc->out->height;
2941                 else if (dc->out->h_size && dc->out->v_size)
2942                         height = dc->out->v_size;
2943         }
2944
2945         return height;
2946 }
2947 EXPORT_SYMBOL(tegra_dc_get_out_height);
2948
2949 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2950 {
2951         unsigned width = 0;
2952
2953         if (dc->out) {
2954                 if (dc->out->width)
2955                         width = dc->out->width;
2956                 else if (dc->out->h_size && dc->out->v_size)
2957                         width = dc->out->h_size;
2958         }
2959
2960         return width;
2961 }
2962 EXPORT_SYMBOL(tegra_dc_get_out_width);
2963
2964 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2965 {
2966         if (dc && dc->out)
2967                 return dc->out->max_pixclock;
2968         else
2969                 return 0;
2970 }
2971 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2972
2973 void tegra_dc_enable_crc(struct tegra_dc *dc)
2974 {
2975         u32 val;
2976
2977         mutex_lock(&dc->lock);
2978         tegra_dc_get(dc);
2979
2980         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2981                 CRC_ENABLE_ENABLE;
2982         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2983         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2984         tegra_dc_put(dc);
2985         mutex_unlock(&dc->lock);
2986
2987         /* Register a client of frame_end interrupt */
2988         tegra_dc_config_frame_end_intr(dc, true);
2989 }
2990
2991 void tegra_dc_disable_crc(struct tegra_dc *dc)
2992 {
2993         /* Unregister a client of frame_end interrupt */
2994         tegra_dc_config_frame_end_intr(dc, false);
2995
2996         mutex_lock(&dc->lock);
2997         tegra_dc_get(dc);
2998         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2999         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3000
3001         tegra_dc_put(dc);
3002         mutex_unlock(&dc->lock);
3003 }
3004
3005 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
3006 {
3007         int crc = 0;
3008
3009         if (!dc) {
3010                 pr_err("Failed to get dc: NULL parameter.\n");
3011                 goto crc_error;
3012         }
3013
3014         /* If gated quitely return */
3015         if (!tegra_dc_is_powered(dc))
3016                 return 0;
3017
3018         INIT_COMPLETION(dc->crc_complete);
3019         if (dc->crc_pending &&
3020             wait_for_completion_interruptible(&dc->crc_complete)) {
3021                 pr_err("CRC read interrupted.\n");
3022                 goto crc_error;
3023         }
3024
3025         mutex_lock(&dc->lock);
3026         tegra_dc_get(dc);
3027         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
3028         tegra_dc_put(dc);
3029         mutex_unlock(&dc->lock);
3030 crc_error:
3031         return crc;
3032 }
3033 EXPORT_SYMBOL(tegra_dc_read_checksum_latched);
3034
3035 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
3036 {
3037         u32 val;
3038
3039         if (tegra_platform_is_linsim())
3040                 return false;
3041
3042         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
3043         if (val & (win_act_req_mask))
3044                 return true;
3045
3046         return false;
3047 }
3048
3049 static inline void enable_dc_irq(const struct tegra_dc *dc)
3050 {
3051         if (tegra_platform_is_fpga())
3052                 /* Always disable DC interrupts on FPGA. */
3053                 disable_irq(dc->irq);
3054         else
3055                 enable_irq(dc->irq);
3056 }
3057
3058 /* assumes dc->lock is already taken. */
3059 static void _tegra_dc_vsync_enable(struct tegra_dc *dc)
3060 {
3061         int vsync_irq;
3062
3063         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3064                 vsync_irq = MSF_INT;
3065         else
3066                 vsync_irq = V_BLANK_INT;
3067         tegra_dc_hold_dc_out(dc);
3068         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
3069         tegra_dc_unmask_interrupt(dc, vsync_irq);
3070 }
3071
3072 int tegra_dc_vsync_enable(struct tegra_dc *dc)
3073 {
3074         mutex_lock(&dc->lock);
3075         if (dc->enabled) {
3076                 _tegra_dc_vsync_enable(dc);
3077                 mutex_unlock(&dc->lock);
3078                 return 0;
3079         }
3080         mutex_unlock(&dc->lock);
3081         return 1;
3082 }
3083
3084 /* assumes dc->lock is already taken. */
3085 static void _tegra_dc_vsync_disable(struct tegra_dc *dc)
3086 {
3087         int vsync_irq;
3088
3089         if (dc->out->type == TEGRA_DC_OUT_DSI)
3090                 vsync_irq = MSF_INT;
3091         else
3092                 vsync_irq = V_BLANK_INT;
3093         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
3094         if (!dc->vblank_ref_count)
3095                 tegra_dc_mask_interrupt(dc, vsync_irq);
3096         tegra_dc_release_dc_out(dc);
3097 }
3098
3099 void tegra_dc_vsync_disable(struct tegra_dc *dc)
3100 {
3101         mutex_lock(&dc->lock);
3102         if (dc->enabled)
3103                 _tegra_dc_vsync_disable(dc);
3104         mutex_unlock(&dc->lock);
3105 }
3106
3107 bool tegra_dc_has_vsync(struct tegra_dc *dc)
3108 {
3109         return true;
3110 }
3111
3112 /* assumes dc->lock is already taken. */
3113 static void _tegra_dc_user_vsync_enable(struct tegra_dc *dc, bool enable)
3114 {
3115         if (enable) {
3116                 dc->out->user_needs_vblank++;
3117                 init_completion(&dc->out->user_vblank_comp);
3118                 _tegra_dc_vsync_enable(dc);
3119         } else {
3120                 _tegra_dc_vsync_disable(dc);
3121                 if (dc->out->user_needs_vblank > 0)
3122                         dc->out->user_needs_vblank--;
3123         }
3124 }
3125
3126 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
3127 {
3128         unsigned long timeout_ms;
3129         unsigned long refresh; /* in 1000th Hz */
3130         int ret;
3131
3132         mutex_lock(&dc->lp_lock);
3133         mutex_lock(&dc->lock);
3134         if (!dc->enabled) {
3135                 ret = -ENOTTY;
3136                 goto out;
3137         }
3138         refresh = tegra_dc_calc_refresh(&dc->mode);
3139         /* time out if waiting took more than 2 frames */
3140         timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
3141         _tegra_dc_user_vsync_enable(dc, true);
3142         mutex_unlock(&dc->lock);
3143         ret = wait_for_completion_interruptible_timeout(
3144                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
3145         mutex_lock(&dc->lock);
3146         _tegra_dc_user_vsync_enable(dc, false);
3147 out:
3148         mutex_unlock(&dc->lock);
3149         mutex_unlock(&dc->lp_lock);
3150         return ret;
3151 }
3152
3153 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
3154         u32 timeout_ms)
3155 {
3156         int ret;
3157
3158         INIT_COMPLETION(dc->frame_end_complete);
3159
3160         tegra_dc_get(dc);
3161
3162         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
3163         /* unmask frame end interrupt */
3164         _tegra_dc_config_frame_end_intr(dc, true);
3165
3166         ret = wait_for_completion_interruptible_timeout(
3167                         &dc->frame_end_complete,
3168                         msecs_to_jiffies(timeout_ms));
3169
3170         _tegra_dc_config_frame_end_intr(dc, false);
3171
3172         tegra_dc_put(dc);
3173
3174         return ret;
3175 }
3176
3177 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
3178 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
3179 {
3180         /* Do the actual brightness update outside of the mutex dc->lock */
3181         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
3182                 dc->out->sd_settings->bl_device_name) {
3183                 char *bl_device_name =
3184                         dc->out->sd_settings->bl_device_name;
3185                 dc->out->sd_settings->bl_device =
3186                         get_backlight_device_by_name(bl_device_name);
3187         }
3188
3189         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
3190                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
3191                 backlight_update_status(bl);
3192         }
3193 }
3194 #endif
3195
3196 void tegra_dc_set_act_vfp(struct tegra_dc *dc, int vfp)
3197 {
3198         WARN_ON(!mutex_is_locked(&dc->lock));
3199         WARN_ON(vfp < dc->mode.v_ref_to_sync + 1);
3200         /* It's very unlikely that active vfp will need to
3201          * be changed outside of vrr context */
3202         WARN_ON(!dc->out->vrr || !dc->out->vrr->capability);
3203
3204         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
3205                         DC_CMD_STATE_ACCESS);
3206         tegra_dc_writel(dc, dc->mode.h_front_porch |
3207                         (vfp << 16), DC_DISP_FRONT_PORCH);
3208         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
3209                         DC_CMD_STATE_ACCESS);
3210 }
3211
3212 static void tegra_dc_vrr_extend_vfp(struct tegra_dc *dc)
3213 {
3214         struct tegra_vrr *vrr  = dc->out->vrr;
3215
3216         if (!vrr || !vrr->capability)
3217                 return;
3218
3219         if (!vrr->enable)
3220                 return;
3221
3222         tegra_dc_set_act_vfp(dc, MAX_VRR_V_FRONT_PORCH);
3223 }
3224
3225 int tegra_dc_get_v_count(struct tegra_dc *dc)
3226 {
3227         u32     value;
3228
3229         value = tegra_dc_readl(dc, DC_DISP_DISPLAY_DBG_TIMING);
3230         return (value & DBG_V_COUNT_MASK) >> DBG_V_COUNT_SHIFT;
3231 }
3232
3233 static void tegra_dc_vrr_get_ts(struct tegra_dc *dc)
3234 {
3235         struct timespec time_now;
3236         struct tegra_vrr *vrr  = dc->out->vrr;
3237
3238         if (!vrr || !vrr->capability ||
3239                 (!vrr->enable && !vrr->lastenable))
3240                 return;
3241
3242         getnstimeofday(&time_now);
3243         vrr->fe_time_us = (s64)time_now.tv_sec * 1000000 +
3244                                 time_now.tv_nsec / 1000;
3245         vrr->v_count = tegra_dc_get_v_count(dc);
3246 }
3247
3248 static void tegra_dc_vrr_sec(struct tegra_dc *dc)
3249 {
3250         struct tegra_vrr *vrr  = dc->out->vrr;
3251
3252         if (!vrr || !vrr->capability)
3253                 return;
3254
3255         if (!vrr->enable && !vrr->fe_intr_req)
3256                 return;
3257
3258         /* Decrement frame end interrupt refcount previously
3259            requested by secure library */
3260         if (vrr->fe_intr_req) {
3261                 _tegra_dc_config_frame_end_intr(dc, false);
3262                 vrr->fe_intr_req = 0;
3263         }
3264
3265 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
3266         te_vrr_sec();
3267 #endif
3268         /* Increment frame end interrupt refcount requested
3269            by secure library */
3270         if (vrr->fe_intr_req)
3271                 _tegra_dc_config_frame_end_intr(dc, true);
3272 }
3273
3274 static void tegra_dc_vblank(struct work_struct *work)
3275 {
3276         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
3277 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
3278         bool nvsd_updated = false;
3279 #endif /* CONFIG_TEGRA_NVSD */
3280
3281         mutex_lock(&dc->lock);
3282
3283         if (!dc->enabled) {
3284                 mutex_unlock(&dc->lock);
3285                 return;
3286         }
3287
3288         tegra_dc_get(dc);
3289
3290         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
3291         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
3292                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
3293
3294 #ifdef CONFIG_TEGRA_NVDISPLAY
3295         if (dc->out->sd_settings) {
3296                 if (dc->out->sd_settings->enable) {
3297                         if ((dc->out->sd_settings->update_sd) ||
3298                                         (dc->out->sd_settings->phase_in_steps)) {
3299                                 tegra_dc_mask_interrupt(dc, SMARTDIM_INT);
3300                                 nvsd_updated = tegra_sd_update_brightness(dc);
3301                                 dc->out->sd_settings->update_sd = false;
3302                                 tegra_dc_unmask_interrupt(dc, SMARTDIM_INT);
3303                         }
3304                 }
3305         }
3306 #endif
3307 #ifdef CONFIG_TEGRA_NVSD
3308         /* Update the SD brightness */
3309         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
3310                 nvsd_updated = nvsd_update_brightness(dc);
3311                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
3312                  * V_BLANK_NVSD bit of vblank ref-count. */
3313                 if (nvsd_updated) {
3314                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
3315                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
3316                 } else {
3317                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
3318                 }
3319         }
3320
3321         /* Mask vblank interrupt if ref-count is zero. */
3322         if (!dc->vblank_ref_count)
3323                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
3324 #endif /* CONFIG_TEGRA_NVSD */
3325
3326         tegra_dc_put(dc);
3327         mutex_unlock(&dc->lock);
3328
3329 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
3330         /* Do the actual brightness update outside of the mutex dc->lock */
3331         if (nvsd_updated)
3332                 tegra_dc_prism_update_backlight(dc);
3333 #endif /* CONFIG_TEGRA_NVSD */
3334 }
3335
3336 #define CSC_UPDATE_IF_CHANGED(entry, ENTRY) do { \
3337                 if (cmu_active->csc.entry != cmu_shadow->csc.entry || \
3338                         dc->cmu_shadow_force_update) { \
3339                         cmu_active->csc.entry = cmu_shadow->csc.entry; \
3340                         tegra_dc_writel(dc, \
3341                                 cmu_active->csc.entry, \
3342                                 DC_COM_CMU_CSC_##ENTRY); \
3343                 } \
3344         } while (0)
3345
3346 static void _tegra_dc_handle_hdr(struct tegra_dc *dc)
3347 {
3348         mutex_lock(&dc->lock);
3349         if (!dc->enabled) {
3350                 mutex_unlock(&dc->lock);
3351                 return;
3352         }
3353
3354         tegra_dc_get(dc);
3355
3356         if (dc->out_ops->set_hdr)
3357                 dc->out_ops->set_hdr(dc);
3358
3359         tegra_dc_put(dc);
3360         mutex_unlock(&dc->lock);
3361
3362         return;
3363 }
3364
3365 static void tegra_dc_frame_end(struct work_struct *work)
3366 {
3367         struct tegra_dc *dc = container_of(work,
3368                 struct tegra_dc, frame_end_work);
3369 #ifdef CONFIG_TEGRA_DC_CMU
3370         u32 val;
3371         u32 i;
3372
3373         mutex_lock(&dc->lock);
3374
3375         if (!dc->enabled) {
3376                 mutex_unlock(&dc->lock);
3377                 return;
3378         }
3379
3380         tegra_dc_get(dc);
3381
3382         if (dc->cmu_shadow_dirty) {
3383                 struct tegra_dc_cmu *cmu_active = &dc->cmu;
3384                 struct tegra_dc_cmu *cmu_shadow = &dc->cmu_shadow;
3385
3386                 for (i = 0; i < 256; i++) {
3387                         if (cmu_active->lut1[i] != cmu_shadow->lut1[i] ||
3388                                 dc->cmu_shadow_force_update) {
3389                                 cmu_active->lut1[i] = cmu_shadow->lut1[i];
3390                                 val = LUT1_ADDR(i) |
3391                                         LUT1_DATA(cmu_shadow->lut1[i]);
3392                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
3393                         }
3394                 }
3395
3396                 CSC_UPDATE_IF_CHANGED(krr, KRR);
3397                 CSC_UPDATE_IF_CHANGED(kgr, KGR);
3398                 CSC_UPDATE_IF_CHANGED(kbr, KBR);
3399                 CSC_UPDATE_IF_CHANGED(krg, KRG);
3400                 CSC_UPDATE_IF_CHANGED(kgg, KGG);
3401                 CSC_UPDATE_IF_CHANGED(kbg, KBG);
3402                 CSC_UPDATE_IF_CHANGED(krb, KRB);
3403                 CSC_UPDATE_IF_CHANGED(kgb, KGB);
3404                 CSC_UPDATE_IF_CHANGED(kbb, KBB);
3405
3406                 for (i = 0; i < 960; i++)
3407                         if (cmu_active->lut2[i] != cmu_shadow->lut2[i] ||
3408                                 dc->cmu_shadow_force_update) {
3409                                 cmu_active->lut2[i] = cmu_shadow->lut2[i];
3410                                 val = LUT2_ADDR(i) |
3411                                         LUT2_DATA(cmu_active->lut2[i]);
3412                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
3413                         }
3414
3415                 dc->cmu_shadow_dirty = false;
3416                 dc->cmu_shadow_force_update = false;
3417                 _tegra_dc_config_frame_end_intr(dc, false);
3418         }
3419
3420         tegra_dc_put(dc);
3421         mutex_unlock(&dc->lock);
3422 #endif
3423         if (dc->hdr_cache_dirty) {
3424                 _tegra_dc_handle_hdr(dc);
3425                 _tegra_dc_config_frame_end_intr(dc, false);
3426                 dc->hdr_cache_dirty = false;
3427         }
3428         return;
3429 }
3430
3431 static void tegra_dc_one_shot_worker(struct work_struct *work)
3432 {
3433         struct tegra_dc *dc = container_of(
3434                 to_delayed_work(work), struct tegra_dc, one_shot_work);
3435         mutex_lock(&dc->lock);
3436
3437         /* memory client has gone idle */
3438         tegra_dc_clear_bandwidth(dc);
3439
3440         if (dc->out_ops && dc->out_ops->idle) {
3441                 tegra_dc_io_start(dc);
3442                 dc->out_ops->idle(dc);
3443                 tegra_dc_io_end(dc);
3444         }
3445
3446         mutex_unlock(&dc->lock);
3447 }
3448
3449 #if !defined(CONFIG_TEGRA_NVDISPLAY)
3450 /* return an arbitrarily large number if count overflow occurs.
3451  * make it a nice base-10 number to show up in stats output */
3452 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
3453 {
3454         unsigned count = tegra_dc_readl(dc, reg);
3455
3456         tegra_dc_writel(dc, 0, reg);
3457         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
3458 }
3459 #endif
3460
3461 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
3462 {
3463 #if !defined(CONFIG_TEGRA_NVDISPLAY)
3464
3465         const u32 masks[] = {
3466                 WIN_A_UF_INT,
3467                 WIN_B_UF_INT,
3468                 WIN_C_UF_INT,
3469 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3470         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3471         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3472                 WIN_D_UF_INT,
3473                 HC_UF_INT,
3474                 WIN_T_UF_INT,
3475 #endif
3476         };
3477         int i;
3478
3479         dc->stats.underflows++;
3480         if (dc->underflow_mask & WIN_A_UF_INT)
3481                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
3482                         DC_WINBUF_AD_UFLOW_STATUS);
3483         if (dc->underflow_mask & WIN_B_UF_INT)
3484                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
3485                         DC_WINBUF_BD_UFLOW_STATUS);
3486         if (dc->underflow_mask & WIN_C_UF_INT)
3487                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
3488                         DC_WINBUF_CD_UFLOW_STATUS);
3489 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3490         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3491         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3492         if (dc->underflow_mask & HC_UF_INT)
3493                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
3494                         DC_WINBUF_HD_UFLOW_STATUS);
3495         if (dc->underflow_mask & WIN_D_UF_INT)
3496                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
3497                         DC_WINBUF_DD_UFLOW_STATUS);
3498         if (dc->underflow_mask & WIN_T_UF_INT)
3499                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
3500                         DC_WINBUF_TD_UFLOW_STATUS);
3501 #endif
3502
3503         /* Check for any underflow reset conditions */
3504         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3505                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3506                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
3507                         "underflow stats unsupported"))
3508                         break; /* bail if the table above is missing entries */
3509                 if (!masks[i])
3510                         continue; /* skip empty entries */
3511
3512                 if (dc->underflow_mask & masks[i]) {
3513                         win->underflows++;
3514
3515 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3516                         if (i < 3 && win->underflows > 4) {
3517                                 schedule_work(&dc->reset_work);
3518                                 /* reset counter */
3519                                 win->underflows = 0;
3520                                 trace_display_reset(dc);
3521                         }
3522 #endif
3523 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3524                         if (i < 3 && win->underflows > 4) {
3525                                 trace_display_reset(dc);
3526                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
3527                                                 DC_DISP_DISP_MISC_CONTROL);
3528                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3529                                                 DC_CMD_STATE_CONTROL);
3530
3531                                 tegra_dc_writel(dc, 0,
3532                                                 DC_DISP_DISP_MISC_CONTROL);
3533                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3534                                                 DC_CMD_STATE_CONTROL);
3535                         }
3536 #endif
3537                 } else {
3538                         win->underflows = 0;
3539                 }
3540         }
3541
3542 #else
3543         tegra_nvdisp_underflow_handler(dc);
3544 #endif /* CONFIG_TEGRA_NVDISPLAY */
3545
3546         /* Clear the underflow mask now that we've checked it. */
3547         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
3548         dc->underflow_mask = 0;
3549         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
3550         trace_underflow(dc);
3551 }
3552
3553 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3554 static void tegra_dc_vpulse2(struct work_struct *work)
3555 {
3556         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
3557 #ifdef CONFIG_TEGRA_NVSD
3558         bool nvsd_updated = false;
3559 #endif /* CONFIG_TEGRA_NVSD */
3560
3561         mutex_lock(&dc->lock);
3562
3563         if (!dc->enabled) {
3564                 mutex_unlock(&dc->lock);
3565                 return;
3566         }
3567
3568         tegra_dc_get(dc);
3569
3570         /* Clear the V_PULSE2_FLIP if no update */
3571         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
3572                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
3573
3574 #ifdef CONFIG_TEGRA_NVSD
3575         /* Update the SD brightness */
3576         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
3577                 nvsd_updated = nvsd_update_brightness(dc);
3578
3579                 if (nvsd_updated) {
3580                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3581                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
3582                 } else {
3583                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3584                 }
3585         }
3586
3587         /* Mask vpulse2 interrupt if ref-count is zero. */
3588         if (!dc->vpulse2_ref_count)
3589                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3590 #endif /* CONFIG_TEGRA_NVSD */
3591
3592         tegra_dc_put(dc);
3593         mutex_unlock(&dc->lock);
3594
3595 #ifdef CONFIG_TEGRA_NVSD
3596         /* Do the actual brightness update outside of the mutex dc->lock */
3597         if (nvsd_updated)
3598                 tegra_dc_prism_update_backlight(dc);
3599 #endif /* CONFIG_TEGRA_NVSD */
3600 }
3601 #endif
3602
3603 static void tegra_dc_process_vblank(struct tegra_dc *dc, ktime_t timestamp)
3604 {
3605         /* pending user vblank, so wakeup */
3606         if (dc->out->user_needs_vblank) {
3607                 dc->out->user_needs_vblank = false;
3608                 complete(&dc->out->user_vblank_comp);
3609         }
3610         if (test_bit(V_BLANK_USER, &dc->vblank_ref_count)) {
3611 #ifdef CONFIG_ADF_TEGRA
3612                 tegra_adf_process_vblank(dc->adf, timestamp);
3613 #endif
3614 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3615                 tegra_dc_ext_process_vblank(dc->ndev->id, timestamp);
3616 #endif
3617         }
3618 }
3619
3620 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
3621 {
3622         int ret;
3623
3624         mutex_lock(&dc->lock);
3625         ret = _tegra_dc_config_frame_end_intr(dc, enable);
3626         mutex_unlock(&dc->lock);
3627
3628         return ret;
3629 }
3630
3631 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
3632                 ktime_t timestamp)
3633 {
3634         if (status & MSF_INT)
3635                 tegra_dc_process_vblank(dc, timestamp);
3636
3637         if (status & V_BLANK_INT) {
3638                 /* Sync up windows. */
3639                 tegra_dc_trigger_windows(dc);
3640
3641                 /* Schedule any additional bottom-half vblank actvities. */
3642                 queue_work(system_freezable_wq, &dc->vblank_work);
3643         }
3644
3645         if (status & FRAME_END_INT) {
3646                 /* Mark the frame_end as complete. */
3647                 dc->crc_pending = false;
3648                 if (!completion_done(&dc->frame_end_complete))
3649                         complete(&dc->frame_end_complete);
3650                 if (!completion_done(&dc->crc_complete))
3651                         complete(&dc->crc_complete);
3652
3653                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3654                         tegra_dc_put(dc);
3655
3656                 queue_work(system_freezable_wq, &dc->frame_end_work);
3657         }
3658
3659 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3660         if (status & V_PULSE2_INT)
3661                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3662 #endif
3663 }
3664
3665 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
3666                 ktime_t timestamp)
3667 {
3668         /* Schedule any additional bottom-half vblank actvities. */
3669         if (status & V_BLANK_INT) {
3670 #ifdef CONFIG_TEGRA_NVDISPLAY
3671                 if (status & SMARTDIM_INT) {
3672                         if (dc->out->sd_settings) {
3673                                 dc->out->sd_settings->update_sd = true;
3674                         }
3675                 }
3676 #endif
3677                 queue_work(system_freezable_wq, &dc->vblank_work);
3678         }
3679         if (status & (V_BLANK_INT | MSF_INT)) {
3680                 if (dc->out->user_needs_vblank) {
3681                         dc->out->user_needs_vblank = false;
3682                         complete(&dc->out->user_vblank_comp);
3683                 }
3684                 tegra_dc_process_vblank(dc, timestamp);
3685         }
3686
3687         if (status & FRAME_END_INT) {
3688                 struct timespec tm;
3689                 ktime_get_ts(&tm);
3690                 dc->frame_end_timestamp = timespec_to_ns(&tm);
3691                 wake_up(&dc->timestamp_wq);
3692
3693                 if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ)) {
3694                         if (dc->out->type == TEGRA_DC_OUT_DSI) {
3695                                 tegra_dc_vrr_get_ts(dc);
3696                                 tegra_dc_vrr_sec(dc);
3697                         } else
3698                                 tegra_dc_vrr_extend_vfp(dc);
3699                 }
3700
3701                 /* Mark the frame_end as complete. */
3702                 if (!completion_done(&dc->frame_end_complete))
3703                         complete(&dc->frame_end_complete);
3704                 if (!completion_done(&dc->crc_complete))
3705                         complete(&dc->crc_complete);
3706
3707                 tegra_dc_trigger_windows(dc);
3708
3709                 queue_work(system_freezable_wq, &dc->frame_end_work);
3710         }
3711
3712 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3713         if (status & V_PULSE2_INT)
3714                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3715 #endif
3716 }
3717
3718 /* XXX: Not sure if we limit look ahead to 1 frame */
3719 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
3720 {
3721         BUG_ON(!dc->frametime_ns);
3722         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
3723 }
3724
3725 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
3726 {
3727         BUG_ON(!dc->frametime_ns);
3728         return (((new_ts - old_ts) > dc->frametime_ns)
3729                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
3730                         != div_s64((old_ts - dc->frame_end_timestamp),
3731                                 dc->frametime_ns)));
3732 }
3733
3734 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
3735 {
3736         ktime_t timestamp = ktime_get();
3737         struct tegra_dc *dc = ptr;
3738         unsigned long status;
3739         unsigned long underflow_mask;
3740         u32 val;
3741         int need_disable = 0;
3742
3743         if (tegra_platform_is_fpga())
3744                 return IRQ_NONE;
3745
3746         mutex_lock(&dc->lock);
3747         if (!tegra_dc_is_powered(dc)) {
3748                 mutex_unlock(&dc->lock);
3749                 return IRQ_HANDLED;
3750         }
3751
3752         tegra_dc_get(dc);
3753
3754         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
3755                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
3756                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3757                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
3758                 tegra_dc_put(dc);
3759                 mutex_unlock(&dc->lock);
3760                 return IRQ_HANDLED;
3761         }
3762
3763         /* clear all status flags except underflow, save those for the worker */
3764         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3765         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
3766         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
3767         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
3768
3769         /*
3770          * Overlays can get thier internal state corrupted during and underflow
3771          * condition.  The only way to fix this state is to reset the DC.
3772          * if we get 4 consecutive frames with underflows, assume we're
3773          * hosed and reset.
3774          */
3775         underflow_mask = status & ALL_UF_INT();
3776
3777         /* Check underflow */
3778         if (underflow_mask) {
3779                 dc->underflow_mask |= underflow_mask;
3780                 schedule_delayed_work(&dc->underflow_work,
3781                         msecs_to_jiffies(1));
3782         }
3783
3784         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE ||
3785                 dc->out->flags & TEGRA_DC_OUT_NVSR_MODE)
3786                 tegra_dc_one_shot_irq(dc, status, timestamp);
3787         else
3788                 tegra_dc_continuous_irq(dc, status, timestamp);
3789
3790         if (dc->nvsr)
3791                 tegra_dc_nvsr_irq(dc->nvsr, status);
3792
3793         /* update video mode if it has changed since the last frame */
3794         if (status & (FRAME_END_INT | V_BLANK_INT))
3795                 if (tegra_dc_update_mode(dc))
3796                         need_disable = 1; /* force display off on error */
3797
3798         if (status & FRAME_END_INT)
3799                 dc->dbg_fe_count++;
3800         if (dc->disp_active_dirty) {
3801                 tegra_dc_writel(dc, dc->mode.h_active |
3802                         (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
3803                 tegra_dc_writel(dc,
3804                         GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3805                 dc->disp_active_dirty = false;
3806         }
3807
3808         tegra_dc_put(dc);
3809         mutex_unlock(&dc->lock);
3810
3811         if (need_disable)
3812                 tegra_dc_disable_irq_ops(dc, true);
3813         return IRQ_HANDLED;
3814 }
3815
3816 void tegra_dc_set_color_control(struct tegra_dc *dc)
3817 {
3818         u32 color_control;
3819
3820         switch (dc->out->depth) {
3821         case 3:
3822                 color_control = BASE_COLOR_SIZE111;
3823                 break;
3824
3825         case 6:
3826                 color_control = BASE_COLOR_SIZE222;
3827                 break;
3828
3829         case 8:
3830                 color_control = BASE_COLOR_SIZE332;
3831                 break;
3832
3833         case 9:
3834                 color_control = BASE_COLOR_SIZE333;
3835                 break;
3836
3837         case 12:
3838                 color_control = BASE_COLOR_SIZE444;
3839                 break;
3840
3841         case 15:
3842                 color_control = BASE_COLOR_SIZE555;
3843                 break;
3844
3845         case 16:
3846                 color_control = BASE_COLOR_SIZE565;
3847                 break;
3848
3849         case 18:
3850                 color_control = BASE_COLOR_SIZE666;
3851                 break;
3852
3853         default:
3854                 color_control = BASE_COLOR_SIZE888;
3855                 break;
3856         }
3857
3858         switch (dc->out->dither) {
3859         case TEGRA_DC_UNDEFINED_DITHER:
3860         case TEGRA_DC_DISABLE_DITHER:
3861                 color_control |= DITHER_CONTROL_DISABLE;
3862                 break;
3863         case TEGRA_DC_ORDERED_DITHER:
3864                 color_control |= DITHER_CONTROL_ORDERED;
3865                 break;
3866 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
3867         case TEGRA_DC_TEMPORAL_DITHER:
3868                 color_control |= DITHER_CONTROL_TEMPORAL;
3869                 break;
3870 #else
3871         case TEGRA_DC_ERRDIFF_DITHER:
3872                 /* The line buffer for error-diffusion dither is limited
3873                  * to 1280 pixels per line. This limits the maximum
3874                  * horizontal active area size to 1280 pixels when error
3875                  * diffusion is enabled.
3876                  */
3877                 BUG_ON(dc->mode.h_active > 1280);
3878                 color_control |= DITHER_CONTROL_ERRDIFF;
3879                 break;
3880 #endif
3881         default:
3882                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
3883         }
3884
3885 #ifdef CONFIG_TEGRA_DC_CMU
3886         if (dc->cmu_enabled)
3887                 color_control |= CMU_ENABLE;
3888 #endif
3889
3890         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
3891 }
3892
3893 #ifndef CONFIG_TEGRA_NVDISPLAY
3894 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
3895 {
3896 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3897         u32 start, end;
3898         unsigned long val;
3899
3900         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
3901         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
3902
3903         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
3904                 dc->mode.v_back_porch + dc->mode.v_active;
3905         end = start + 1;
3906         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
3907         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
3908
3909         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3910         val |= V_PULSE2_INT;
3911         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
3912
3913         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3914         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
3915         val |= V_PULSE_2_ENABLE;
3916         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
3917 #endif
3918 }
3919
3920 static int tegra_dc_init(struct tegra_dc *dc)
3921 {
3922         int i;
3923         int int_enable;
3924         u32 val;
3925
3926         tegra_dc_io_start(dc);
3927         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
3928         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
3929                         DC_CMD_CONT_SYNCPT_VSYNC);
3930
3931         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
3932 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3933         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3934         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3935         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3936                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
3937                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3938                 DC_CMD_INT_POLARITY);
3939 #else
3940         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3941                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3942                 DC_CMD_INT_POLARITY);
3943 #endif
3944         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
3945         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
3946 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3947         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
3948 #endif
3949         /* enable interrupts for vblank, frame_end and underflows */
3950         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
3951         /* for panels with one-shot mode enable tearing effect interrupt */
3952         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3953                 int_enable |= MSF_INT;
3954
3955         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
3956         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
3957         tegra_dc_init_vpulse2_int(dc);
3958
3959         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
3960                 DC_CMD_STATE_ACCESS);
3961
3962 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
3963         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
3964 #else
3965         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
3966 #endif
3967
3968 #ifdef CONFIG_TEGRA_DC_CMU
3969         if (dc->is_cmu_set_bl)
3970                 _tegra_dc_update_cmu_aligned(dc, &dc->cmu, true);
3971         else
3972                 _tegra_dc_update_cmu(dc, &dc->cmu);
3973         dc->is_cmu_set_bl = false;
3974 #endif
3975         tegra_dc_set_color_control(dc);
3976         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3977                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3978                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
3979                                 DC_CMD_DISPLAY_WINDOW_HEADER);
3980                 tegra_dc_set_csc(dc, &win->csc);
3981                 tegra_dc_set_lut(dc, win);
3982                 tegra_dc_set_scaling_filter(dc);
3983         }
3984
3985 #ifdef CONFIG_TEGRA_DC_WIN_H
3986         /* Window H is set to window mode by default for t14x. */
3987         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
3988                         DC_DISP_BLEND_CURSOR_CONTROL);
3989 #endif
3990
3991         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3992                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3993
3994                 BUG_ON(!win);
3995
3996                 /* refuse to operate on invalid syncpts */
3997                 if (WARN_ON(win->syncpt.id == NVSYNCPT_INVALID))
3998                         continue;
3999
4000                 if (!nvhost_syncpt_read_ext_check(dc->ndev, win->syncpt.id, &val))
4001                         win->syncpt.min = win->syncpt.max = val;
4002         }
4003
4004         dc->crc_pending = false;
4005
4006         trace_display_mode(dc, &dc->mode);
4007
4008         if (dc->mode.pclk) {
4009                 if (!dc->initialized) {
4010                         if (tegra_dc_program_mode(dc, &dc->mode)) {
4011                                 tegra_dc_io_end(dc);
4012                                 dev_warn(&dc->ndev->dev,
4013                                         "%s: tegra_dc_program_mode failed\n",
4014                                         __func__);
4015                                 return -EINVAL;
4016                         }
4017                 } else {
4018                         dev_info(&dc->ndev->dev, "DC initialized, "
4019                                         "skipping tegra_dc_program_mode.\n");
4020                 }
4021         }
4022
4023         /* Initialize SD AFTER the modeset.
4024            nvsd_init handles the sd_settings = NULL case. */
4025         nvsd_init(dc, dc->out->sd_settings);
4026
4027         tegra_dc_io_end(dc);
4028
4029         return 0;
4030 }
4031
4032 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
4033 {
4034         int failed_init = 0;
4035         int i;
4036
4037 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
4038         struct device_node *np_dpaux;
4039 #endif
4040
4041         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4042                 return false;
4043
4044         tegra_dc_unpowergate_locked(dc);
4045
4046         if (dc->out->enable)
4047                 dc->out->enable(&dc->ndev->dev);
4048
4049         tegra_dc_setup_clk(dc, dc->clk);
4050
4051         /* dc clk always on for continuous mode */
4052         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
4053                 tegra_dc_clk_enable(dc);
4054         else
4055                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
4056
4057         tegra_dc_get(dc);
4058
4059         tegra_dc_power_on(dc);
4060
4061         /* do not accept interrupts during initialization */
4062         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
4063
4064         enable_dc_irq(dc);
4065
4066         failed_init = tegra_dc_init(dc);
4067         if (failed_init) {
4068                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
4069                 disable_irq_nosync(dc->irq);
4070                 tegra_dc_clear_bandwidth(dc);
4071                 if (dc->out && dc->out->disable)
4072                         dc->out->disable(&dc->ndev->dev);
4073                 tegra_dc_put(dc);
4074                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
4075                         tegra_dc_clk_disable(dc);
4076                 else
4077                         tegra_dvfs_set_rate(dc->clk, 0);
4078                 dev_warn(&dc->ndev->dev,
4079                         "%s: tegra_dc_init failed\n", __func__);
4080                 return false;
4081         }
4082
4083         if (dc->out->type != TEGRA_DC_OUT_DP) {
4084 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
4085                 int sor_num = tegra_dc_which_sor(dc);
4086                 np_dpaux = of_find_node_by_path(
4087                                 sor_num ? DPAUX1_NODE : DPAUX_NODE);
4088                 if (np_dpaux || !dc->ndev->dev.of_node)
4089                         tegra_dpaux_pad_power(dc,
4090                         sor_num ? TEGRA_DPAUX_INSTANCE_1 :
4091                         TEGRA_DPAUX_INSTANCE_0, false);
4092                 of_node_put(np_dpaux);
4093 #endif
4094         }
4095
4096         if (dc->out_ops && dc->out_ops->enable)
4097                 dc->out_ops->enable(dc);
4098
4099         /* force a full blending update */
4100         for (i = 0; i < DC_N_WINDOWS; i++)
4101                 dc->blend.z[i] = -1;
4102
4103 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4104         tegra_dc_ext_enable(dc->ext);
4105 #endif
4106
4107         /* initialize cursor to defaults, as driver depends on HW state */
4108         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
4109         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
4110 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
4111         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
4112         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
4113 #endif
4114         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
4115         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
4116         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
4117         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
4118         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
4119
4120         trace_display_enable(dc);
4121
4122 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
4123 !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
4124 !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
4125 !defined(CONFIG_ARCH_TEGRA_14x_SOC)
4126         tegra_dc_writel(dc, CURSOR_UPDATE, DC_CMD_STATE_CONTROL);
4127         tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
4128 #endif
4129         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
4130
4131         if (dc->out->postpoweron)
4132                 dc->out->postpoweron(&dc->ndev->dev);
4133
4134         if (dc->out_ops && dc->out_ops->postpoweron)
4135                 dc->out_ops->postpoweron(dc);
4136
4137         tegra_log_resume_time();
4138
4139         tegra_dc_put(dc);
4140
4141         tegra_disp_clk_prepare_enable(dc->emc_la_clk);
4142
4143         return true;
4144 }
4145 #endif
4146
4147 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4148 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
4149 {
4150         bool ret = true;
4151
4152         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4153                 return false;
4154
4155         if (dc->out->enable)
4156                 dc->out->enable(&dc->ndev->dev);
4157
4158         tegra_dc_setup_clk(dc, dc->clk);
4159         tegra_dc_clk_enable(dc);
4160
4161         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
4162                 mutex_lock(&tegra_dcs[1]->lock);
4163                 disable_irq_nosync(tegra_dcs[1]->irq);
4164         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
4165                 mutex_lock(&tegra_dcs[0]->lock);
4166                 disable_irq_nosync(tegra_dcs[0]->irq);
4167         }
4168
4169         msleep(5);
4170         tegra_periph_reset_assert(dc->clk);
4171         msleep(2);
4172         if (tegra_platform_is_silicon()) {
4173                 tegra_periph_reset_deassert(dc->clk);
4174                 msleep(1);
4175         }
4176
4177         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
4178                 enable_dc_irq(tegra_dcs[1]);
4179                 mutex_unlock(&tegra_dcs[1]->lock);
4180         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
4181                 enable_dc_irq(tegra_dcs[0]);
4182                 mutex_unlock(&tegra_dcs[0]->lock);
4183         }
4184
4185         enable_dc_irq(dc);
4186
4187         if (tegra_dc_init(dc)) {
4188                 dev_err(&dc->ndev->dev, "cannot initialize\n");
4189                 ret = false;
4190         }
4191
4192         if (dc->out_ops && dc->out_ops->enable)
4193                 dc->out_ops->enable(dc);
4194
4195         if (dc->out->postpoweron)
4196                 dc->out->postpoweron(&dc->ndev->dev);
4197
4198         /* force a full blending update */
4199         dc->blend.z[0] = -1;
4200
4201 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4202         tegra_dc_ext_enable(dc->ext);
4203 #endif
4204
4205         if (!ret) {
4206                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
4207                 _tegra_dc_controller_disable(dc);
4208         }
4209
4210         trace_display_reset(dc);
4211         return ret;
4212 }
4213 #endif
4214
4215 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
4216 {
4217         if (dc->mode.pclk == 0) {
4218                 switch (dc->out->type) {
4219                 case TEGRA_DC_OUT_HDMI:
4220                         /* No fallback mode. If no mode info available
4221                          * from bootloader or device tree,
4222                          * mode will be set by userspace during unblank.
4223                          */
4224                         break;
4225                 case TEGRA_DC_OUT_DP:
4226                 case TEGRA_DC_OUT_NVSR_DP:
4227                 case TEGRA_DC_OUT_FAKE_DP:
4228                 case TEGRA_DC_OUT_NULL:
4229                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
4230
4231                 /* Do nothing for other outputs for now */
4232                 case TEGRA_DC_OUT_RGB:
4233
4234                 case TEGRA_DC_OUT_DSI:
4235
4236                 default:
4237                         return false;
4238                 }
4239         }
4240
4241         return false;
4242 }
4243
4244 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
4245 {
4246         return _tegra_dc_set_default_videomode(dc);
4247 }
4248
4249 static bool _tegra_dc_enable(struct tegra_dc *dc)
4250 {
4251         if (dc->mode.pclk == 0)
4252                 return false;
4253
4254         if (!dc->out)
4255                 return false;
4256
4257         if (dc->enabled)
4258                 return true;
4259
4260         dc->shutdown = false;
4261
4262         pm_runtime_get_sync(&dc->ndev->dev);
4263
4264         if ((dc->out->type == TEGRA_DC_OUT_HDMI ||
4265                 dc->out->type == TEGRA_DC_OUT_DP) &&
4266                 !tegra_dc_hpd(dc))
4267                 return false;
4268
4269 #ifdef CONFIG_TEGRA_NVDISPLAY
4270         if (tegra_nvdisp_head_enable(dc)) {
4271 #else
4272         if (!_tegra_dc_controller_enable(dc)) {
4273 #endif
4274                 pm_runtime_put_sync(&dc->ndev->dev);
4275                 return false;
4276         }
4277
4278         return true;
4279 }
4280
4281 void tegra_dc_enable(struct tegra_dc *dc)
4282 {
4283         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4284                 return;
4285
4286         mutex_lock(&dc->lock);
4287
4288         if (!dc->enabled)
4289                 dc->enabled = _tegra_dc_enable(dc);
4290
4291         mutex_unlock(&dc->lock);
4292         trace_display_mode(dc, &dc->mode);
4293 }
4294
4295 static void tegra_dc_flush_syncpts_window(struct tegra_dc *dc, unsigned win)
4296 {
4297         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
4298         u32 max;
4299
4300         /* refuse to operate on invalid syncpts */
4301         if (WARN_ON(w->syncpt.id == NVSYNCPT_INVALID))
4302                 return;
4303
4304         /* flush any pending syncpt waits */
4305         max = tegra_dc_incr_syncpt_max_locked(dc, win);
4306         while (w->syncpt.min < w->syncpt.max) {
4307                 trace_display_syncpt_flush(dc, w->syncpt.id,
4308                         w->syncpt.min, w->syncpt.max);
4309                 w->syncpt.min++;
4310                 nvhost_syncpt_cpu_incr_ext(dc->ndev, w->syncpt.id);
4311         }
4312 }
4313
4314 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
4315 {
4316         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
4317
4318         /* reset window bandwidth */
4319         w->bandwidth = 0;
4320         w->new_bandwidth = 0;
4321
4322         /* disable windows */
4323         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
4324
4325         /* flush pending syncpts */
4326         tegra_dc_flush_syncpts_window(dc, win);
4327 }
4328
4329 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
4330 {
4331         unsigned i;
4332
4333         tegra_dc_get(dc);
4334
4335         if (atomic_read(&dc->holding)) {
4336                 /* Force release all refs but the last one */
4337                 atomic_set(&dc->holding, 1);
4338                 tegra_dc_release_dc_out(dc);
4339         }
4340
4341         if (dc->out && dc->out->prepoweroff)
4342                 dc->out->prepoweroff();
4343
4344         if (dc->out_ops && dc->out_ops->vrr_enable &&
4345                 dc->out->vrr && dc->out->vrr->capability) {
4346                 dc->out_ops->vrr_enable(dc, 0);
4347                 /* TODO: Fix properly. Bug 1644102. */
4348                 tegra_dc_set_act_vfp(dc, dc->mode.v_front_porch);
4349         }
4350
4351         if (dc->out_ops && dc->out_ops->disable)
4352                 dc->out_ops->disable(dc);
4353
4354         if (tegra_powergate_is_powered(dc->powergate_id))
4355                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
4356
4357         disable_irq_nosync(dc->irq);
4358
4359         tegra_dc_clear_bandwidth(dc);
4360
4361         if (dc->out && dc->out->disable)
4362                 dc->out->disable(&dc->ndev->dev);
4363
4364         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
4365                 tegra_dc_disable_window(dc, i);
4366         }
4367         trace_display_disable(dc);
4368
4369         if (dc->out_ops && dc->out_ops->postpoweroff)
4370                 dc->out_ops->postpoweroff(dc);
4371
4372         tegra_dc_put(dc);
4373
4374         /* disable always on dc clk in continuous mode */
4375         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
4376                 tegra_dc_clk_disable(dc);
4377         else
4378                 tegra_dvfs_set_rate(dc->clk, 0);
4379
4380         tegra_disp_clk_disable_unprepare(dc->emc_la_clk);
4381 }
4382
4383 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
4384 {
4385 #if 0 /* underflow interrupt is already enabled by dc reset worker */
4386         u32 val;
4387         if (dc->enabled)  {
4388                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
4389                 if (enable)
4390                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
4391                 else
4392                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
4393                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
4394         }
4395 #endif
4396 }
4397
4398 bool tegra_dc_stats_get(struct tegra_dc *dc)
4399 {
4400 #if 0 /* right now it is always enabled */
4401         u32 val;
4402         bool res;
4403
4404         if (dc->enabled)  {
4405                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
4406                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
4407         } else {
4408                 res = false;
4409         }
4410
4411         return res;
4412 #endif
4413         return true;
4414 }
4415
4416 /* blank selected windows by disabling them */
4417 int tegra_dc_blank_wins(struct tegra_dc *dc, unsigned windows)
4418 {
4419         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
4420         struct tegra_dc_win blank_win;
4421         unsigned i;
4422         unsigned long int blank_windows;
4423         int nr_win = 0;
4424         int ret = 0;
4425
4426         /* YUV420 10bpc variables */
4427         int yuv_flag = dc->mode.vmode & FB_VMODE_YUV_MASK;
4428         bool yuv_420_10b_path = false;
4429         int fb_win_idx = -1;
4430         int fb_win_pos = -1;
4431
4432         if (dc->yuv_bypass && yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
4433                 yuv_420_10b_path = true;
4434
4435         if (yuv_420_10b_path) {
4436                 u32 active_width = dc->mode.h_active;
4437                 u32 active_height = dc->mode.v_active;
4438
4439                 blank_win = *tegra_fb_get_blank_win(dc->fb);
4440
4441                 /*
4442                  * 420 10bpc blank frame statically
4443                  * created for this pixel format
4444                  */
4445                 blank_win.h.full = dfixed_const(1);
4446                 blank_win.w.full = dfixed_const(active_width);
4447                 blank_win.fmt = TEGRA_WIN_FMT_B8G8R8A8;
4448                 blank_win.out_w = active_width;
4449                 blank_win.out_h = active_height;
4450
4451                 dcwins[0] = &blank_win;
4452                 fb_win_idx = dcwins[0]->idx;
4453                 nr_win++;
4454         }
4455
4456         blank_windows = windows & dc->valid_windows;
4457
4458         if (!blank_windows)
4459                 return ret;
4460
4461         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4462                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
4463                 if (!dcwins[nr_win])
4464                         continue;
4465                 /*
4466                  * Prevent disabling the YUV410 10bpc window in case
4467                  * it is also in blank_windows, additionally, prevent
4468                  * adding it to the list twice.
4469                  */
4470                 if (fb_win_idx == dcwins[nr_win]->idx) {
4471                         fb_win_pos = i;
4472                         continue;
4473                 }
4474                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
4475         }
4476
4477         if (dc->shutdown) {
4478                 if ((dc->out->type == TEGRA_DC_OUT_HDMI) ||
4479                         (dc->out->type == TEGRA_DC_OUT_DP))
4480                         if (dc->out_ops && dc->out_ops->shutdown_interface)
4481                                 dc->out_ops->shutdown_interface(dc);
4482         }
4483
4484         /* Skip update for linsim */
4485         if (!tegra_platform_is_linsim()) {
4486                 tegra_dc_update_windows(dcwins, nr_win, NULL, true);
4487                 ret = tegra_dc_sync_windows(dcwins, nr_win);
4488         }
4489         tegra_dc_program_bandwidth(dc, true);
4490
4491         /*
4492          * Disable, reset bandwidth and advance pending syncpoints
4493          * of all windows. In case the statically created 420 10bpc
4494          * is also present in blank_windows, only advance syncpoints.
4495          */
4496         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4497                 if (fb_win_pos == i) {
4498                         tegra_dc_flush_syncpts_window(dc, i);
4499                         continue;
4500                 }
4501                 tegra_dc_disable_window(dc, i);
4502         }
4503
4504         return ret;
4505 }
4506
4507 int tegra_dc_restore(struct tegra_dc *dc)
4508 {
4509 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4510         return tegra_dc_ext_restore(dc->ext);
4511 #else
4512         return 0;
4513 #endif
4514 }
4515
4516 static void _tegra_dc_disable(struct tegra_dc *dc)
4517 {
4518 #ifdef CONFIG_TEGRA_DC_CMU
4519         /* power down resets the registers, setting to true
4520          * causes CMU to be restored in tegra_dc_init(). */
4521         dc->cmu_dirty = true;
4522 #endif
4523         tegra_dc_io_start(dc);
4524         _tegra_dc_controller_disable(dc);
4525         tegra_dc_io_end(dc);
4526
4527         tegra_dc_powergate_locked(dc);
4528
4529         pm_runtime_put(&dc->ndev->dev);
4530
4531         tegra_log_suspend_time();
4532 }
4533
4534 void tegra_dc_disable(struct tegra_dc *dc)
4535 {
4536         dc->shutdown = true;
4537         tegra_dc_disable_irq_ops(dc, false);
4538 }
4539
4540 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq)
4541 {
4542         bool blank_windows = true;
4543
4544         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4545                 return;
4546
4547         if (dc->shutdown) {
4548                 if ((dc->out->type == TEGRA_DC_OUT_HDMI) ||
4549                     (dc->out->type == TEGRA_DC_OUT_DP))
4550                         if (dc->out_ops && dc->out_ops->shutdown_interface)
4551                                 dc->out_ops->shutdown_interface(dc);
4552         }
4553
4554 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4555         blank_windows = !tegra_dc_ext_disable(dc->ext);
4556 #endif
4557
4558         if (blank_windows)
4559                 tegra_dc_blank_wins(dc, BLANK_ALL);
4560
4561         /* it's important that new underflow work isn't scheduled before the
4562          * lock is acquired. */
4563         cancel_delayed_work_sync(&dc->underflow_work);
4564
4565
4566         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4567                 mutex_lock(&dc->one_shot_lock);
4568                 cancel_delayed_work_sync(&dc->one_shot_work);
4569         }
4570
4571         mutex_lock(&dc->lp_lock);
4572         mutex_lock(&dc->lock);
4573
4574         if (dc->enabled) {
4575                 dc->enabled = false;
4576                 dc->blanked = false;
4577
4578                 if (!dc->suspended)
4579                         _tegra_dc_disable(dc);
4580         }
4581
4582 #ifdef CONFIG_SWITCH
4583         if (dc->switchdev_registered)
4584                 switch_set_state(&dc->modeset_switch, 0);
4585 #endif
4586         mutex_unlock(&dc->lock);
4587         mutex_unlock(&dc->lp_lock);
4588         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4589                 mutex_unlock(&dc->one_shot_lock);
4590         if (!from_irq)
4591                 synchronize_irq(dc->irq);
4592         trace_display_mode(dc, &dc->mode);
4593
4594         /* disable pending clks due to uncompleted frames */
4595         while (!tegra_platform_is_linsim() && tegra_is_clk_enabled(dc->clk))
4596                 tegra_dc_put(dc);
4597 }
4598
4599 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4600 static void tegra_dc_reset_worker(struct work_struct *work)
4601 {
4602         struct tegra_dc *dc =
4603                 container_of(work, struct tegra_dc, reset_work);
4604
4605         unsigned long val = 0;
4606
4607         mutex_lock(&shared_lock);
4608
4609         dev_warn(&dc->ndev->dev,
4610                 "overlay stuck in underflow state.  resetting.\n");
4611
4612 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4613         tegra_dc_ext_disable(dc->ext);
4614 #endif
4615
4616         mutex_lock(&dc->lock);
4617
4618         if (dc->enabled == false)
4619                 goto unlock;
4620
4621         dc->enabled = false;
4622
4623         /*
4624          * off host read bus
4625          */
4626         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4627         val &= ~(0x00000100);
4628         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4629
4630         /*
4631          * set DC to STOP mode
4632          */
4633         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
4634
4635         msleep(10);
4636
4637         _tegra_dc_controller_disable(dc);
4638
4639         /* _tegra_dc_controller_reset_enable deasserts reset */
4640         _tegra_dc_controller_reset_enable(dc);
4641
4642         dc->enabled = true;
4643
4644         /* reopen host read bus */
4645         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4646         val &= ~(0x00000100);
4647         val |= 0x100;
4648         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4649
4650 unlock:
4651         mutex_unlock(&dc->lock);
4652         mutex_unlock(&shared_lock);
4653         trace_display_reset(dc);
4654 }
4655 #endif
4656
4657 static void tegra_dc_underflow_worker(struct work_struct *work)
4658 {
4659         struct tegra_dc *dc = container_of(
4660                 to_delayed_work(work), struct tegra_dc, underflow_work);
4661
4662         mutex_lock(&dc->lock);
4663         tegra_dc_get(dc);
4664
4665         if (dc->enabled)
4666                 tegra_dc_underflow_handler(dc);
4667
4668         tegra_dc_put(dc);
4669         mutex_unlock(&dc->lock);
4670 }
4671
4672 static void (*flip_callback)(void);
4673 static spinlock_t flip_callback_lock;
4674 static bool init_tegra_dc_flip_callback_called;
4675
4676 static int __init init_tegra_dc_flip_callback(void)
4677 {
4678         spin_lock_init(&flip_callback_lock);
4679         init_tegra_dc_flip_callback_called = true;
4680         return 0;
4681 }
4682
4683 pure_initcall(init_tegra_dc_flip_callback);
4684
4685 int tegra_dc_set_flip_callback(void (*callback)(void))
4686 {
4687         WARN_ON(!init_tegra_dc_flip_callback_called);
4688
4689         spin_lock(&flip_callback_lock);
4690         flip_callback = callback;
4691         spin_unlock(&flip_callback_lock);
4692
4693         return 0;
4694 }
4695 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
4696
4697 int tegra_dc_unset_flip_callback(void)
4698 {
4699         spin_lock(&flip_callback_lock);
4700         flip_callback = NULL;
4701         spin_unlock(&flip_callback_lock);
4702
4703         return 0;
4704 }
4705 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
4706
4707 void tegra_dc_call_flip_callback(void)
4708 {
4709         spin_lock(&flip_callback_lock);
4710         if (flip_callback)
4711                 flip_callback();
4712         spin_unlock(&flip_callback_lock);
4713 }
4714 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
4715
4716 #ifdef CONFIG_SWITCH
4717 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
4718 {
4719         struct tegra_dc *dc =
4720                 container_of(sdev, struct tegra_dc, modeset_switch);
4721
4722         if (!sdev->state)
4723                 return sprintf(buf, "offline\n");
4724
4725         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
4726 }
4727 #endif
4728
4729 /* enables pads and clocks to perform DDC/I2C */
4730 int tegra_dc_ddc_enable(struct tegra_dc *dc, bool enabled)
4731 {
4732         int ret = -ENOSYS;
4733         if (dc->out_ops) {
4734                 if (enabled && dc->out_ops->ddc_enable)
4735                         ret = dc->out_ops->ddc_enable(dc);
4736                 else if (!enabled && dc->out_ops->ddc_disable)
4737                         ret = dc->out_ops->ddc_disable(dc);
4738         }
4739         return ret;
4740 }
4741
4742 int tegra_dc_slgc_disp0(struct notifier_block *nb,
4743         unsigned long unused0, void *unused1)
4744 {
4745 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4746         struct tegra_dc *dc = container_of(nb, struct tegra_dc, slgc_notifier);
4747         u32 val;
4748
4749         tegra_dc_get(dc);
4750
4751         val = tegra_dc_readl(dc, DC_COM_DSC_TOP_CTL);
4752         val |= DSC_SLCG_OVERRIDE;
4753         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* set */
4754         /* flush the previous write */
4755         (void)tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
4756         val &= ~DSC_SLCG_OVERRIDE;
4757         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* restore */
4758
4759         tegra_dc_put(dc);
4760 #endif
4761         return NOTIFY_OK;
4762 }
4763
4764 struct clk *tegra_disp_of_clk_get_by_name(struct device_node *np,
4765                                                 const char *name)
4766 {
4767 #ifdef CONFIG_TEGRA_NVDISPLAY
4768         if (!tegra_platform_is_silicon() && !tegra_bpmp_running())
4769                 return of_clk_get_by_name(np, "clk32k_in");
4770 #endif
4771         return of_clk_get_by_name(np, name);
4772 }
4773
4774 struct clk *tegra_disp_clk_get(struct device *dev, const char *id)
4775 {
4776 #ifdef CONFIG_TEGRA_NVDISPLAY
4777         if (!tegra_platform_is_silicon() && !tegra_bpmp_running())
4778                 return of_clk_get_by_name(dev->of_node, "clk32k_in");
4779         else
4780                 return devm_clk_get(dev, id);
4781
4782 #else
4783         return clk_get(dev, id);
4784 #endif
4785 }
4786
4787 void tegra_disp_clk_put(struct device *dev, struct clk *clk)
4788 {
4789 #ifdef CONFIG_TEGRA_NVDISPLAY
4790         if (tegra_platform_is_silicon() || tegra_bpmp_running())
4791                 devm_clk_put(dev, clk);
4792 #else
4793         return clk_put(clk);
4794 #endif
4795 }
4796
4797 static int tegra_dc_probe(struct platform_device *ndev)
4798 {
4799         struct tegra_dc *dc;
4800         struct tegra_dc_mode *mode;
4801         struct tegra_dc_platform_data *dt_pdata = NULL;
4802         struct clk *clk;
4803 #ifndef CONFIG_TEGRA_ISOMGR
4804         struct clk *emc_clk;
4805 #else
4806         int isomgr_client_id = -1;
4807 #endif
4808         struct clk *emc_la_clk;
4809         struct device_node *np = ndev->dev.of_node;
4810         struct resource *res;
4811         struct resource dt_res;
4812         struct resource *base_res;
4813         struct resource *fb_mem = NULL;
4814         char clk_name[16];
4815         int ret = 0;
4816         void __iomem *base;
4817         int irq;
4818         int i;
4819 #ifndef CONFIG_TEGRA_NVDISPLAY
4820
4821 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4822         int partition_id_disa, partition_id_disb;
4823 #endif
4824 #endif
4825
4826 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4827         if (tegra_platform_is_linsim()) {
4828                 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
4829                 return -ENODEV;
4830         }
4831 #endif
4832
4833         if (!np && !ndev->dev.platform_data) {
4834                 dev_err(&ndev->dev, "no platform data\n");
4835                 return -ENOENT;
4836         }
4837
4838         /* Specify parameters for the maximum physical segment size. */
4839         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
4840
4841         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
4842         if (!dc) {
4843                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
4844                 return -ENOMEM;
4845         }
4846
4847         if (np) {
4848 #ifdef CONFIG_OF
4849                 irq = of_irq_to_resource(np, 0, NULL);
4850                 if (!irq)
4851                         goto err_free;
4852 #endif
4853
4854                 ret = of_address_to_resource(np, 0, &dt_res);
4855                 if (ret)
4856                         goto err_free;
4857
4858                 ndev->id = tegra_dc_set(dc, -1);
4859                 if (ndev->id < 0) {
4860                         dev_err(&ndev->dev, "can't add dc\n");
4861                         goto err_free;
4862                 }
4863
4864                 dev_info(&ndev->dev, "Display dc.%08x registered with id=%d\n",
4865                                 (unsigned int)dt_res.start, ndev->id);
4866
4867                 res = &dt_res;
4868
4869                 dt_pdata = of_dc_parse_platform_data(ndev);
4870                 if (dt_pdata == NULL)
4871                         goto err_free;
4872
4873 #ifdef CONFIG_TEGRA_NVDISPLAY
4874                 dc->ctrl_num = dt_pdata->ctrl_num;
4875 #else
4876                 if (dt_res.start == TEGRA_DISPLAY_BASE)
4877                         dc->ctrl_num = 0;
4878                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
4879                         dc->ctrl_num = 1;
4880                 else
4881                         goto err_free;
4882 #endif
4883
4884         } else {
4885
4886                 dc->ctrl_num = ndev->id;
4887
4888                 irq = platform_get_irq_byname(ndev, "irq");
4889                 if (irq <= 0) {
4890                         dev_err(&ndev->dev, "no irq\n");
4891                         ret = -ENOENT;
4892                         goto err_free;
4893                 }
4894
4895                 res = platform_get_resource_byname(ndev,
4896                         IORESOURCE_MEM, "regs");
4897                 if (!res) {
4898                         dev_err(&ndev->dev, "no mem resource\n");
4899                         ret = -ENOENT;
4900                         goto err_free;
4901                 }
4902
4903                 if (tegra_dc_set(dc, ndev->id) < 0) {
4904                         dev_err(&ndev->dev, "can't add dc\n");
4905                         goto err_free;
4906                 }
4907
4908         }
4909
4910         base_res = request_mem_region(res->start, resource_size(res),
4911                 ndev->name);
4912         if (!base_res) {
4913                 dev_err(&ndev->dev, "request_mem_region failed\n");
4914                 ret = -EBUSY;
4915                 goto err_free;
4916         }
4917
4918         base = ioremap(res->start, resource_size(res));
4919         if (!base) {
4920                 dev_err(&ndev->dev, "registers can't be mapped\n");
4921                 ret = -EBUSY;
4922                 goto err_release_resource_reg;
4923         }
4924
4925 #ifndef CONFIG_TEGRA_NVDISPLAY
4926         for (i = 0; i < DC_N_WINDOWS; i++)
4927                 dc->windows[i].syncpt.id = NVSYNCPT_INVALID;
4928
4929         if (TEGRA_DISPLAY_BASE == res->start) {
4930                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
4931                 dc->windows[0].syncpt.id =
4932                         nvhost_get_syncpt_client_managed(ndev, "disp0_a");
4933                 dc->windows[1].syncpt.id =
4934                         nvhost_get_syncpt_client_managed(ndev, "disp0_b");
4935                 dc->windows[2].syncpt.id =
4936                         nvhost_get_syncpt_client_managed(ndev, "disp0_c");
4937                 dc->valid_windows = 0x07;
4938 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
4939                 dc->windows[3].syncpt.id =
4940                         nvhost_get_syncpt_client_managed(ndev, "disp0_d");
4941                 dc->windows[4].syncpt.id =
4942                         nvhost_get_syncpt_client_managed(ndev, "disp0_h");
4943                 dc->valid_windows |= 0x18;
4944 #elif !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
4945         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
4946         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
4947                 dc->windows[3].syncpt.id =
4948                         nvhost_get_syncpt_client_managed(ndev, "disp0_d");
4949                 dc->valid_windows |= 0x08;
4950 #endif
4951 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4952                 partition_id_disa = tegra_pd_get_powergate_id(tegra_disa_pd);
4953                 if (partition_id_disa < 0)
4954                         return -EINVAL;
4955
4956                 dc->powergate_id = partition_id_disa;
4957 #else
4958                 dc->powergate_id = TEGRA_POWERGATE_DISA;
4959 #endif
4960 #ifdef CONFIG_TEGRA_ISOMGR
4961                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
4962 #endif
4963                 dc->slgc_notifier.notifier_call = tegra_dc_slgc_disp0;
4964                 slcg_register_notifier(dc->powergate_id,
4965                         &dc->slgc_notifier);
4966         } else if (TEGRA_DISPLAY2_BASE == res->start) {
4967                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
4968                 dc->windows[0].syncpt.id =
4969                         nvhost_get_syncpt_client_managed(ndev, "disp1_a");
4970                 dc->windows[1].syncpt.id =
4971                         nvhost_get_syncpt_client_managed(ndev, "disp1_b");
4972                 dc->windows[2].syncpt.id =
4973                         nvhost_get_syncpt_client_managed(ndev, "disp1_c");
4974                 dc->valid_windows = 0x07;
4975 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
4976                 dc->windows[4].syncpt.id =
4977                         nvhost_get_syncpt_client_managed(ndev, "disp1_h");
4978                 dc->valid_windows |= 0x10;
4979 #endif
4980 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4981                 partition_id_disb = tegra_pd_get_powergate_id(tegra_disb_pd);
4982                 if (partition_id_disb < 0)
4983                         return -EINVAL;
4984
4985                 dc->powergate_id = partition_id_disb;
4986 #else
4987                 dc->powergate_id = TEGRA_POWERGATE_DISB;
4988 #endif
4989 #ifdef CONFIG_TEGRA_ISOMGR
4990                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
4991 #endif
4992         } else {
4993                 dev_err(&ndev->dev,
4994                         "Unknown base address %llx: unable to assign syncpt\n",
4995                         (u64)res->start);
4996         }
4997 #endif  /* !CONFIG_TEGRA_NVDISPLAY */
4998
4999         if (np) {
5000                 struct resource of_fb_res;
5001 #ifdef CONFIG_TEGRA_NVDISPLAY
5002                 tegra_get_fb_resource(&of_fb_res);
5003 #else
5004                 if (dc->ctrl_num == 0)
5005                         tegra_get_fb_resource(&of_fb_res);
5006                 else /* dc->ctrl_num == 1*/
5007                         tegra_get_fb2_resource(&of_fb_res);
5008 #endif
5009
5010                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
5011                 if (fb_mem == NULL) {
5012                         ret = -ENOMEM;
5013                         goto err_iounmap_reg;
5014                 }
5015                 fb_mem->name = "fbmem";
5016                 fb_mem->flags = IORESOURCE_MEM;
5017                 fb_mem->start = (resource_size_t)of_fb_res.start;
5018                 fb_mem->end = (resource_size_t)of_fb_res.end;
5019         } else {
5020                 fb_mem = platform_get_resource_byname(ndev,
5021                         IORESOURCE_MEM, "fbmem");
5022                 if (fb_mem == NULL) {
5023                         ret = -ENOMEM;
5024                         goto err_iounmap_reg;
5025                 }
5026         }
5027
5028 #ifdef CONFIG_TEGRA_NVDISPLAY
5029         snprintf(clk_name, sizeof(clk_name), "nvdisplay_p%u", dc->ctrl_num);
5030 #else
5031         memset(clk_name, 0, sizeof(clk_name));
5032 #endif
5033         clk = tegra_disp_clk_get(&ndev->dev, clk_name);
5034         if (IS_ERR_OR_NULL(clk)) {
5035                 dev_err(&ndev->dev, "can't get clock\n");
5036                 ret = -ENOENT;
5037                 goto err_iounmap_reg;
5038         }
5039
5040         dc->clk = clk;
5041         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
5042         /* Initialize one shot work delay, it will be assigned by dsi
5043          * according to refresh rate later. */
5044         dc->one_shot_delay_ms = 40;
5045
5046         dc->base_res = base_res;
5047         dc->base = base;
5048         dc->irq = irq;
5049         dc->ndev = ndev;
5050         dc->fb_mem = fb_mem;
5051
5052         if (!np)
5053                 dc->pdata = ndev->dev.platform_data;
5054         else
5055                 dc->pdata = dt_pdata;
5056
5057         dc->bw_kbps = 0;
5058
5059 #ifdef CONFIG_TEGRA_NVDISPLAY
5060         /* dc variables need to initialized before nvdisp init */
5061         ret = tegra_nvdisp_init(dc);
5062         if (ret)
5063                 goto err_iounmap_reg;
5064 #endif
5065
5066         mutex_init(&dc->lock);
5067         mutex_init(&dc->one_shot_lock);
5068         mutex_init(&dc->lp_lock);
5069         init_completion(&dc->frame_end_complete);
5070         init_completion(&dc->crc_complete);
5071         init_waitqueue_head(&dc->wq);
5072         init_waitqueue_head(&dc->timestamp_wq);
5073 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
5074         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
5075 #endif
5076         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
5077         dc->vblank_ref_count = 0;
5078         INIT_WORK(&dc->frame_end_work, tegra_dc_frame_end);
5079 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
5080         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
5081 #endif
5082         dc->vpulse2_ref_count = 0;
5083         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
5084         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
5085
5086         tegra_dc_init_lut_defaults(&dc->fb_lut);
5087
5088         dc->n_windows = DC_N_WINDOWS;
5089         for (i = 0; i < DC_N_WINDOWS; i++) {
5090                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
5091 #ifdef CONFIG_TEGRA_NVDISPLAY
5092                 struct tegra_dc_win *win = &tegra_dc_windows[i];
5093 #else
5094                 struct tegra_dc_win *win = &dc->windows[i];
5095                 win->dc = dc;
5096 #endif
5097                 if (!test_bit(i, &dc->valid_windows))
5098                         win->flags |= TEGRA_WIN_FLAG_INVALID;
5099                 win->idx = i;
5100                 tmp_win->idx = i;
5101                 tmp_win->dc = dc;
5102 #if defined(CONFIG_TEGRA_CSC)
5103                 tegra_dc_init_csc_defaults(&win->csc);
5104 #endif
5105                 tegra_dc_init_lut_defaults(&win->lut);
5106         }
5107
5108         platform_set_drvdata(ndev, dc);
5109
5110 #ifdef CONFIG_SWITCH
5111         dc->modeset_switch.name = dev_name(&ndev->dev);
5112         dc->modeset_switch.state = 0;
5113         dc->modeset_switch.print_state = switch_modeset_print_mode;
5114         ret = switch_dev_register(&dc->modeset_switch);
5115         if (ret < 0) {
5116                 dev_err(&ndev->dev,
5117                         "failed to register switch driver ret(%d)\n", ret);
5118                 dc->switchdev_registered = false;
5119         } else
5120                 dc->switchdev_registered = true;
5121 #endif
5122
5123         tegra_dc_feature_register(dc);
5124
5125         if (dc->pdata->default_out) {
5126                 if (dc->pdata->default_out->hotplug_init)
5127                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
5128                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
5129                 if (ret < 0) {
5130                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
5131                         goto err_put_clk;
5132                 }
5133         } else {
5134                 dev_err(&ndev->dev,
5135                         "No default output specified.  Leaving output disabled.\n");
5136         }
5137         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
5138
5139         if ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
5140                         dc->out && dc->out->type == TEGRA_DC_OUT_LVDS) {
5141                 struct fb_monspecs specs;
5142                 struct tegra_dc_lvds_data *lvds = tegra_dc_get_outdata(dc);
5143                 if (!tegra_edid_get_monspecs(lvds->edid, &specs))
5144                         tegra_dc_set_fb_mode(dc, specs.modedb, false);
5145         }
5146
5147 #ifndef CONFIG_TEGRA_ISOMGR
5148                 /*
5149                  * The emc is a shared clock, it will be set based on
5150                  * the requirements for each user on the bus.
5151                  */
5152                 emc_clk = tegra_disp_clk_get(&ndev->dev, "emc");
5153                 if (IS_ERR_OR_NULL(emc_clk)) {
5154                         dev_err(&ndev->dev, "can't get emc clock\n");
5155                         ret = -ENOENT;
5156                         goto err_put_clk;
5157                 }
5158                 dc->emc_clk = emc_clk;
5159 #endif
5160                 /*
5161                  * The emc_la clock is being added to set the floor value
5162                  * for emc depending on the LA calculaions for each window
5163                  */
5164 #ifdef CONFIG_TEGRA_NVDISPLAY
5165                 emc_la_clk = tegra_disp_clk_get(&ndev->dev, "emc_latency");
5166 #else
5167                 emc_la_clk = tegra_disp_clk_get(&ndev->dev, "emc.la");
5168 #endif
5169                 if (IS_ERR_OR_NULL(emc_la_clk)) {
5170                         dev_err(&ndev->dev, "can't get emc.la clock\n");
5171                         ret = -ENOENT;
5172                         goto err_put_clk;
5173                 }
5174                 dc->emc_la_clk = emc_la_clk;
5175                 clk_set_rate(dc->emc_la_clk, 0);
5176
5177 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5178         dc->ext = tegra_dc_ext_register(ndev, dc);
5179         if (IS_ERR_OR_NULL(dc->ext)) {
5180                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
5181                 dc->ext = NULL;
5182         }
5183 #endif
5184
5185         /* interrupt handler must be registered before tegra_fb_register() */
5186         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
5187                         dev_name(&ndev->dev), dc)) {
5188                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
5189                 ret = -EBUSY;
5190                 goto err_disable_dc;
5191         }
5192         disable_dc_irq(dc);
5193
5194         tegra_pd_add_device(&ndev->dev);
5195         pm_runtime_use_autosuspend(&ndev->dev);
5196         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
5197         pm_runtime_enable(&ndev->dev);
5198
5199 #if defined(CONFIG_TEGRA_DC_CMU) || defined(CONFIG_TEGRA_DC_CMU_V2)
5200         /* if bootloader leaves this head enabled, then skip CMU programming. */
5201         dc->is_cmu_set_bl = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) != 0;
5202         dc->cmu_enabled = dc->pdata->cmu_enable;
5203 #endif
5204
5205         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
5206                 /* WAR: BL is putting DC in bad state for EDP configuration */
5207                 if (!tegra_platform_is_linsim() &&
5208                         (dc->out->type == TEGRA_DC_OUT_DP ||
5209                                 dc->out->type == TEGRA_DC_OUT_NVSR_DP)) {
5210                         tegra_disp_clk_prepare_enable(dc->clk);
5211                         tegra_periph_reset_assert(dc->clk);
5212                         udelay(10);
5213                         tegra_periph_reset_deassert(dc->clk);
5214                         udelay(10);
5215                         tegra_disp_clk_disable_unprepare(dc->clk);
5216                 }
5217
5218                 if (dc->out_ops && dc->out_ops->hotplug_init)
5219                         dc->out_ops->hotplug_init(dc);
5220
5221                 _tegra_dc_set_default_videomode(dc);
5222                 dc->enabled = _tegra_dc_enable(dc);
5223
5224 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
5225                 /* BL or PG init will keep DISA unpowergated after booting.
5226                  * Adding an extra powergate to balance the refcount
5227                  * since _tegra_dc_enable() increases the refcount.
5228                  */
5229                 if (!tegra_platform_is_fpga())
5230                         if (dc->powergate_id == TEGRA_POWERGATE_DISA)
5231                                 tegra_dc_powergate_locked(dc);
5232 #endif
5233         }
5234
5235 #ifdef CONFIG_TEGRA_ISOMGR
5236         if (isomgr_client_id == -1) {
5237                 dc->isomgr_handle = NULL;
5238         } else {
5239                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
5240                         tegra_dc_calc_min_bandwidth(dc),
5241                         tegra_dc_bandwidth_renegotiate, dc);
5242                 if (IS_ERR(dc->isomgr_handle)) {
5243                         dev_err(&dc->ndev->dev,
5244                                 "could not register isomgr. err=%ld\n",
5245                                 PTR_ERR(dc->isomgr_handle));
5246                         ret = -ENOENT;
5247                         goto err_put_clk;
5248                 }
5249                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
5250                 /*
5251                  * Use maximum value so we can try to reserve as much as
5252                  * needed until we are told by isomgr to backoff.
5253                  */
5254                 dc->available_bw = UINT_MAX;
5255         }
5256 #endif
5257
5258         tegra_dc_create_debugfs(dc);
5259
5260         dev_info(&ndev->dev, "probed\n");
5261
5262         if (dc->pdata->fb) {
5263                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
5264                         unsigned long fmt;
5265                         tegra_dc_writel(dc,
5266                                         WINDOW_A_SELECT << dc->pdata->fb->win,
5267                                         DC_CMD_DISPLAY_WINDOW_HEADER);
5268
5269                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
5270                         dc->pdata->fb->bits_per_pixel =
5271                                 tegra_dc_fmt_bpp(fmt);
5272                 }
5273
5274                 mode = tegra_dc_get_override_mode(dc);
5275                 if (mode) {
5276                         dc->pdata->fb->xres = mode->h_active;
5277                         dc->pdata->fb->yres = mode->v_active;
5278                 }
5279
5280 #ifdef CONFIG_ADF_TEGRA
5281                 tegra_dc_io_start(dc);
5282                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb, fb_mem);
5283                 tegra_dc_io_end(dc);
5284
5285                 if (IS_ERR(dc->adf)) {
5286                         tegra_dc_io_start(dc);
5287                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
5288                                 fb_mem);
5289                         tegra_dc_io_end(dc);
5290                         if (IS_ERR_OR_NULL(dc->fb)) {
5291                                 dc->fb = NULL;
5292                                 dev_err(&ndev->dev, "failed to register fb\n");
5293                                 goto err_remove_debugfs;
5294                         }
5295                 }
5296 #endif
5297 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5298                 tegra_dc_io_start(dc);
5299 #ifdef CONFIG_TEGRA_NVDISPLAY
5300                 dc->fb = tegra_nvdisp_fb_register(ndev, dc, dc->pdata->fb,
5301                         fb_mem);
5302 #else
5303                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem,
5304                         NULL);
5305 #endif
5306                 tegra_dc_io_end(dc);
5307                 if (IS_ERR_OR_NULL(dc->fb)) {
5308                         dc->fb = NULL;
5309                         dev_err(&ndev->dev, "failed to register fb\n");
5310                         goto err_remove_debugfs;
5311                 }
5312 #endif
5313         }
5314
5315         if (dc->out_ops) {
5316                 if (dc->out_ops->detect)
5317                         dc->connected = dc->out_ops->detect(dc);
5318                 else
5319                         dc->connected = true;
5320         } else
5321                 dc->connected = false;
5322
5323         /* Powergate display module when it's unconnected. */
5324         /* detect() function, if presetns, responsible for the powergate */
5325         if (!tegra_dc_get_connected(dc) &&
5326                         !(dc->out_ops && dc->out_ops->detect))
5327                 tegra_dc_powergate_locked(dc);
5328
5329         tegra_dc_create_sysfs(&dc->ndev->dev);
5330
5331         /*
5332          * Overriding the display mode only applies for modes set up during
5333          * boot. It should not apply for e.g. HDMI hotplug.
5334          */
5335         dc->initialized = false;
5336
5337         /*
5338          * Initialize vedid state. This is placed here
5339          * to allow persistence across sw HDMI hotplugs.
5340          */
5341         dc->vedid = false;
5342         dc->vedid_data = NULL;
5343
5344         return 0;
5345
5346 err_remove_debugfs:
5347         tegra_dc_remove_debugfs(dc);
5348         free_irq(irq, dc);
5349 err_disable_dc:
5350 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5351         if (dc->ext) {
5352                 tegra_dc_ext_disable(dc->ext);
5353                 tegra_dc_ext_unregister(dc->ext);
5354         }
5355 #endif
5356         mutex_lock(&dc->lock);
5357         if (dc->enabled)
5358                 _tegra_dc_disable(dc);
5359         dc->enabled = false;
5360         mutex_unlock(&dc->lock);
5361 #ifdef CONFIG_TEGRA_ISOMGR
5362         tegra_isomgr_unregister(dc->isomgr_handle);
5363 #else
5364         tegra_disp_clk_put(&ndev->dev, emc_clk);
5365 #endif
5366         tegra_disp_clk_put(&ndev->dev, dc->emc_la_clk);
5367 err_put_clk:
5368 #ifdef CONFIG_SWITCH
5369         if (dc->switchdev_registered)
5370                 switch_dev_unregister(&dc->modeset_switch);
5371 #endif
5372         tegra_disp_clk_put(&ndev->dev, clk);
5373 err_iounmap_reg:
5374         iounmap(base);
5375         if (fb_mem) {
5376                 if (!np)
5377                         release_resource(fb_mem);
5378                 else
5379                         kfree(fb_mem);
5380         }
5381 err_release_resource_reg:
5382         release_resource(base_res);
5383 err_free:
5384         kfree(dc);
5385         tegra_dc_set(NULL, ndev->id);
5386
5387         return ret;
5388 }
5389
5390 static int tegra_dc_remove(struct platform_device *ndev)
5391 {
5392         struct tegra_dc *dc = platform_get_drvdata(ndev);
5393         struct device_node *np = ndev->dev.of_node;
5394
5395         tegra_dc_remove_sysfs(&dc->ndev->dev);
5396         tegra_dc_remove_debugfs(dc);
5397
5398         if (dc->fb) {
5399                 tegra_fb_unregister(dc->fb);
5400                 if (dc->fb_mem) {
5401                         if (!np)
5402                                 release_resource(dc->fb_mem);
5403                         else
5404                                 kfree(dc->fb_mem);
5405                 }
5406         }
5407
5408 #ifdef CONFIG_ADF_TEGRA
5409         if (dc->adf)
5410                 tegra_adf_unregister(dc->adf);
5411 #endif
5412 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5413         if (dc->ext) {
5414                 tegra_dc_ext_disable(dc->ext);
5415                 tegra_dc_ext_unregister(dc->ext);
5416         }
5417 #endif
5418
5419         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
5420                 mutex_lock(&dc->one_shot_lock);
5421                 cancel_delayed_work_sync(&dc->one_shot_work);
5422         }
5423         mutex_lock(&dc->lock);
5424         if (dc->enabled)
5425                 _tegra_dc_disable(dc);
5426         dc->enabled = false;
5427         mutex_unlock(&dc->lock);
5428         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5429                 mutex_unlock(&dc->one_shot_lock);
5430         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
5431
5432 #ifdef CONFIG_SWITCH
5433         if (dc->switchdev_registered)
5434                 switch_dev_unregister(&dc->modeset_switch);
5435 #endif
5436         free_irq(dc->irq, dc);
5437 #ifdef CONFIG_TEGRA_ISOMGR
5438         if (dc->isomgr_handle) {
5439                 tegra_isomgr_unregister(dc->isomgr_handle);
5440                 dc->isomgr_handle = NULL;
5441         }
5442 #else
5443         tegra_disp_clk_put(&ndev->dev, dc->emc_clk);
5444 #endif
5445         tegra_disp_clk_put(&ndev->dev, dc->emc_la_clk);
5446
5447         tegra_disp_clk_put(&ndev->dev, dc->clk);
5448         iounmap(dc->base);
5449         if (dc->fb_mem)
5450                 release_resource(dc->base_res);
5451         kfree(dc);
5452         tegra_dc_set(NULL, ndev->id);
5453
5454         return 0;
5455 }
5456
5457 #ifdef CONFIG_PM
5458 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
5459 {
5460         struct tegra_dc *dc = platform_get_drvdata(ndev);
5461         int ret = 0;
5462
5463         trace_display_suspend(dc);
5464         dev_info(&ndev->dev, "suspend\n");
5465
5466 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5467         tegra_dc_ext_disable(dc->ext);
5468 #endif
5469
5470         tegra_dc_cursor_suspend(dc);
5471
5472         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
5473                 mutex_lock(&dc->one_shot_lock);
5474                 cancel_delayed_work_sync(&dc->one_shot_work);
5475         }
5476         mutex_lock(&dc->lock);
5477         ret = tegra_dc_io_start(dc);
5478
5479         if (dc->out_ops && dc->out_ops->suspend)
5480                 dc->out_ops->suspend(dc);
5481
5482         if (dc->enabled) {
5483                 _tegra_dc_disable(dc);
5484
5485                 dc->suspended = true;
5486         }
5487
5488         if (dc->out && dc->out->postsuspend) {
5489                 dc->out->postsuspend();
5490                 /* avoid resume event due to voltage falling on interfaces that
5491                  * support hotplug wake. And only do this if a panel is
5492                  * connected, if we are already disconnected, then no phantom
5493                  * hotplug can occur by disabling the voltage.
5494                  */
5495                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
5496                         && tegra_dc_get_connected(dc))
5497                         msleep(100);
5498         }
5499
5500         if (!ret)
5501                 tegra_dc_io_end(dc);
5502
5503         mutex_unlock(&dc->lock);
5504         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5505                 mutex_unlock(&dc->one_shot_lock);
5506         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
5507
5508         return 0;
5509 }
5510
5511 static int tegra_dc_resume(struct platform_device *ndev)
5512 {
5513         struct tegra_dc *dc = platform_get_drvdata(ndev);
5514
5515         trace_display_resume(dc);
5516         dev_info(&ndev->dev, "resume\n");
5517
5518         mutex_lock(&dc->lock);
5519         dc->suspended = false;
5520
5521         /* To pan the fb on resume */
5522         tegra_fb_pan_display_reset(dc->fb);
5523
5524         if (dc->enabled) {
5525                 dc->enabled = false;
5526                 _tegra_dc_set_default_videomode(dc);
5527                 dc->enabled = _tegra_dc_enable(dc);
5528         }
5529
5530         if (dc->out && dc->out->hotplug_init)
5531                 dc->out->hotplug_init(&ndev->dev);
5532
5533         if (dc->out_ops && dc->out_ops->resume)
5534                 dc->out_ops->resume(dc);
5535
5536         mutex_unlock(&dc->lock);
5537         tegra_dc_cursor_resume(dc);
5538
5539         return 0;
5540 }
5541
5542 #endif /* CONFIG_PM */
5543
5544 static void tegra_dc_shutdown(struct platform_device *ndev)
5545 {
5546         struct tegra_dc *dc = platform_get_drvdata(ndev);
5547
5548         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
5549                 return;
5550
5551         if (!dc->enabled)
5552                 return;
5553
5554         kfree(dc->vedid_data);
5555         dc->vedid_data = NULL;
5556         dc->vedid = false;
5557
5558
5559         /* Let dc clients know about shutdown event before calling disable */
5560         if (dc->out_ops && dc->out_ops->shutdown)
5561                 dc->out_ops->shutdown(dc);
5562
5563         tegra_dc_disable(dc);
5564 }
5565
5566 static int suspend_set(const char *val, struct kernel_param *kp)
5567 {
5568         if (!strcmp(val, "dump"))
5569                 dump_regs(tegra_dcs[0]);
5570 #ifdef CONFIG_PM
5571         else if (!strcmp(val, "suspend"))
5572                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
5573         else if (!strcmp(val, "resume"))
5574                 tegra_dc_resume(tegra_dcs[0]->ndev);
5575 #endif
5576
5577         return 0;
5578 }
5579
5580 static int suspend_get(char *buffer, struct kernel_param *kp)
5581 {
5582         return 0;
5583 }
5584
5585 static int suspend;
5586
5587 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
5588
5589
5590 #ifdef CONFIG_OF
5591 static struct of_device_id tegra_display_of_match[] = {
5592         {.compatible = "nvidia,tegra114-dc", },
5593         {.compatible = "nvidia,tegra124-dc", },
5594         {.compatible = "nvidia,tegra210-dc", },
5595         {.compatible = "nvidia,tegra186-dc", },
5596         { },
5597 };
5598 #endif
5599
5600 static struct platform_driver tegra_dc_driver = {
5601         .driver = {
5602                 .name = "tegradc",
5603                 .owner = THIS_MODULE,
5604 #ifdef CONFIG_OF
5605                 .of_match_table =
5606                         of_match_ptr(tegra_display_of_match),
5607 #endif
5608         },
5609         .probe = tegra_dc_probe,
5610         .remove = tegra_dc_remove,
5611 #ifdef CONFIG_PM
5612         .suspend = tegra_dc_suspend,
5613         .resume = tegra_dc_resume,
5614 #endif
5615         .shutdown = tegra_dc_shutdown,
5616 };
5617
5618 #ifndef MODULE
5619 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
5620 {
5621         int i, params[11];
5622         char *p;
5623
5624         for (i = 0; i < ARRAY_SIZE(params); i++) {
5625                 if ((p = strsep(&options, ",")) != NULL) {
5626                         if (*p)
5627                                 params[i] = simple_strtoul(p, &p, 10);
5628                 } else
5629                         return -EINVAL;
5630         }
5631
5632         if ((mode->pclk = params[0]) == 0)
5633                 return -EINVAL;
5634
5635         mode->h_active      = params[1];
5636         mode->v_active      = params[2];
5637         mode->h_ref_to_sync = params[3];
5638         mode->v_ref_to_sync = params[4];
5639         mode->h_sync_width  = params[5];
5640         mode->v_sync_width  = params[6];
5641         mode->h_back_porch  = params[7];
5642         mode->v_back_porch  = params[8];
5643         mode->h_front_porch = params[9];
5644         mode->v_front_porch = params[10];
5645
5646         return 0;
5647 }
5648
5649 static int __init tegra_dc_mode_override(char *str)
5650 {
5651         char *p = str, *options;
5652
5653         if (!p || !*p)
5654                 return -EINVAL;
5655
5656         p = strstr(str, "hdmi:");
5657         if (p) {
5658                 p += 5;
5659                 options = strsep(&p, ";");
5660                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
5661                         return -EINVAL;
5662         }
5663
5664         p = strstr(str, "rgb:");
5665         if (p) {
5666                 p += 4;
5667                 options = strsep(&p, ";");
5668                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
5669                         return -EINVAL;
5670         }
5671
5672         p = strstr(str, "dsi:");
5673         if (p) {
5674                 p += 4;
5675                 options = strsep(&p, ";");
5676                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
5677                         return -EINVAL;
5678         }
5679
5680         p = strstr(str, "null:");
5681         if (p) {
5682                 p += 5;
5683                 options = strsep(&p, ";");
5684                 if (parse_disp_params(options,
5685                                 &override_disp_mode[TEGRA_DC_OUT_NULL]))
5686                         return -EINVAL;
5687         }
5688
5689         return 0;
5690 }
5691
5692 __setup("disp_params=", tegra_dc_mode_override);
5693 #endif
5694
5695 static int __init tegra_dc_module_init(void)
5696 {
5697 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5698         int ret = tegra_dc_ext_module_init();
5699         if (ret)
5700                 return ret;
5701 #endif
5702         return platform_driver_register(&tegra_dc_driver);
5703 }
5704
5705 static void __exit tegra_dc_module_exit(void)
5706 {
5707         platform_driver_unregister(&tegra_dc_driver);
5708 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5709         tegra_dc_ext_module_exit();
5710 #endif
5711 }
5712
5713 module_exit(tegra_dc_module_exit);
5714 module_init(tegra_dc_module_init);