tegra: dc: Unsetting DC to default mode in probe
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <linux/clk/tegra.h>
41 #include <video/tegrafb.h>
42 #include <drm/drm_fixed.h>
43 #ifdef CONFIG_SWITCH
44 #include <linux/switch.h>
45 #endif
46 #include <linux/of_irq.h>
47 #include <linux/of_address.h>
48 #include <linux/tegra_pm_domains.h>
49
50 #define CREATE_TRACE_POINTS
51 #include <trace/events/display.h>
52
53 #include <mach/dc.h>
54 #include <mach/fb.h>
55 #include <mach/mc.h>
56 #include <linux/nvhost.h>
57 #include <linux/nvhost_ioctl.h>
58 #include <mach/latency_allowance.h>
59
60 #include "dc_reg.h"
61 #include "dc_config.h"
62 #include "dc_priv.h"
63 #include "dev.h"
64 #include "nvhost_sync.h"
65 #include "nvsd.h"
66 #include "dp.h"
67 #include "nvsr.h"
68
69 #ifdef CONFIG_ADF_TEGRA
70 #include "tegra_adf.h"
71 #endif
72
73 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
74 #include "hdmi.h"
75 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
76
77 /* HACK! This needs to come from DT */
78 #include "../../../../arch/arm/mach-tegra/iomap.h"
79
80 #define TEGRA_CRC_LATCHED_DELAY         34
81
82 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
83 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
84
85 static struct fb_videomode tegra_dc_vga_mode = {
86         .refresh = 60,
87         .xres = 640,
88         .yres = 480,
89         .pixclock = KHZ2PICOS(25200),
90         .hsync_len = 96,        /* h_sync_width */
91         .vsync_len = 2,         /* v_sync_width */
92         .left_margin = 48,      /* h_back_porch */
93         .upper_margin = 33,     /* v_back_porch */
94         .right_margin = 16,     /* h_front_porch */
95         .lower_margin = 10,     /* v_front_porch */
96         .vmode = 0,
97         .sync = 0,
98 };
99
100 static struct tegra_dc_mode override_disp_mode[3];
101
102 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
103 static void tegra_dc_disable_nosync(struct tegra_dc *dc);
104 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
105
106 DEFINE_MUTEX(tegra_dc_lock);
107 DEFINE_MUTEX(shared_lock);
108
109 static struct device_dma_parameters tegra_dc_dma_parameters = {
110         .max_segment_size = UINT_MAX,
111 };
112
113 static const struct {
114         bool h;
115         bool v;
116 } can_filter[] = {
117         /* Window A has no filtering */
118         { false, false },
119         /* Window B has both H and V filtering */
120         { true,  true  },
121         /* Window C has only H filtering */
122         { false, true  },
123 };
124
125 #ifdef CONFIG_TEGRA_DC_CMU
126 static struct tegra_dc_cmu default_cmu = {
127         /* lut1 maps sRGB to linear space. */
128         {
129                 0,    1,    2,    4,    5,    6,    7,    9,
130                 10,   11,   12,   14,   15,   16,   18,   20,
131                 21,   23,   25,   27,   29,   31,   33,   35,
132                 37,   40,   42,   45,   48,   50,   53,   56,
133                 59,   62,   66,   69,   72,   76,   79,   83,
134                 87,   91,   95,   99,   103,  107,  112,  116,
135                 121,  126,  131,  136,  141,  146,  151,  156,
136                 162,  168,  173,  179,  185,  191,  197,  204,
137                 210,  216,  223,  230,  237,  244,  251,  258,
138                 265,  273,  280,  288,  296,  304,  312,  320,
139                 329,  337,  346,  354,  363,  372,  381,  390,
140                 400,  409,  419,  428,  438,  448,  458,  469,
141                 479,  490,  500,  511,  522,  533,  544,  555,
142                 567,  578,  590,  602,  614,  626,  639,  651,
143                 664,  676,  689,  702,  715,  728,  742,  755,
144                 769,  783,  797,  811,  825,  840,  854,  869,
145                 884,  899,  914,  929,  945,  960,  976,  992,
146                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
147                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
148                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
149                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
150                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
151                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
152                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
153                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
154                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
155                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
156                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
157                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
158                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
159                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
160                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
161         },
162         /* csc */
163         {
164                 0x100, 0x0,   0x0,
165                 0x0,   0x100, 0x0,
166                 0x0,   0x0,   0x100,
167         },
168         /* lut2 maps linear space to sRGB*/
169         {
170                 0,    1,    2,    2,    3,    4,    5,    6,
171                 6,    7,    8,    9,    10,   10,   11,   12,
172                 13,   13,   14,   15,   15,   16,   16,   17,
173                 18,   18,   19,   19,   20,   20,   21,   21,
174                 22,   22,   23,   23,   23,   24,   24,   25,
175                 25,   25,   26,   26,   27,   27,   27,   28,
176                 28,   29,   29,   29,   30,   30,   30,   31,
177                 31,   31,   32,   32,   32,   33,   33,   33,
178                 34,   34,   34,   34,   35,   35,   35,   36,
179                 36,   36,   37,   37,   37,   37,   38,   38,
180                 38,   38,   39,   39,   39,   40,   40,   40,
181                 40,   41,   41,   41,   41,   42,   42,   42,
182                 42,   43,   43,   43,   43,   43,   44,   44,
183                 44,   44,   45,   45,   45,   45,   46,   46,
184                 46,   46,   46,   47,   47,   47,   47,   48,
185                 48,   48,   48,   48,   49,   49,   49,   49,
186                 49,   50,   50,   50,   50,   50,   51,   51,
187                 51,   51,   51,   52,   52,   52,   52,   52,
188                 53,   53,   53,   53,   53,   54,   54,   54,
189                 54,   54,   55,   55,   55,   55,   55,   55,
190                 56,   56,   56,   56,   56,   57,   57,   57,
191                 57,   57,   57,   58,   58,   58,   58,   58,
192                 58,   59,   59,   59,   59,   59,   59,   60,
193                 60,   60,   60,   60,   60,   61,   61,   61,
194                 61,   61,   61,   62,   62,   62,   62,   62,
195                 62,   63,   63,   63,   63,   63,   63,   64,
196                 64,   64,   64,   64,   64,   64,   65,   65,
197                 65,   65,   65,   65,   66,   66,   66,   66,
198                 66,   66,   66,   67,   67,   67,   67,   67,
199                 67,   67,   68,   68,   68,   68,   68,   68,
200                 68,   69,   69,   69,   69,   69,   69,   69,
201                 70,   70,   70,   70,   70,   70,   70,   71,
202                 71,   71,   71,   71,   71,   71,   72,   72,
203                 72,   72,   72,   72,   72,   72,   73,   73,
204                 73,   73,   73,   73,   73,   74,   74,   74,
205                 74,   74,   74,   74,   74,   75,   75,   75,
206                 75,   75,   75,   75,   75,   76,   76,   76,
207                 76,   76,   76,   76,   77,   77,   77,   77,
208                 77,   77,   77,   77,   78,   78,   78,   78,
209                 78,   78,   78,   78,   78,   79,   79,   79,
210                 79,   79,   79,   79,   79,   80,   80,   80,
211                 80,   80,   80,   80,   80,   81,   81,   81,
212                 81,   81,   81,   81,   81,   81,   82,   82,
213                 82,   82,   82,   82,   82,   82,   83,   83,
214                 83,   83,   83,   83,   83,   83,   83,   84,
215                 84,   84,   84,   84,   84,   84,   84,   84,
216                 85,   85,   85,   85,   85,   85,   85,   85,
217                 85,   86,   86,   86,   86,   86,   86,   86,
218                 86,   86,   87,   87,   87,   87,   87,   87,
219                 87,   87,   87,   88,   88,   88,   88,   88,
220                 88,   88,   88,   88,   88,   89,   89,   89,
221                 89,   89,   89,   89,   89,   89,   90,   90,
222                 90,   90,   90,   90,   90,   90,   90,   90,
223                 91,   91,   91,   91,   91,   91,   91,   91,
224                 91,   91,   92,   92,   92,   92,   92,   92,
225                 92,   92,   92,   92,   93,   93,   93,   93,
226                 93,   93,   93,   93,   93,   93,   94,   94,
227                 94,   94,   94,   94,   94,   94,   94,   94,
228                 95,   95,   95,   95,   95,   95,   95,   95,
229                 95,   95,   96,   96,   96,   96,   96,   96,
230                 96,   96,   96,   96,   96,   97,   97,   97,
231                 97,   97,   97,   97,   97,   97,   97,   98,
232                 98,   98,   98,   98,   98,   98,   98,   98,
233                 98,   98,   99,   99,   99,   99,   99,   99,
234                 99,   100,  101,  101,  102,  103,  103,  104,
235                 105,  105,  106,  107,  107,  108,  109,  109,
236                 110,  111,  111,  112,  113,  113,  114,  115,
237                 115,  116,  116,  117,  118,  118,  119,  119,
238                 120,  120,  121,  122,  122,  123,  123,  124,
239                 124,  125,  126,  126,  127,  127,  128,  128,
240                 129,  129,  130,  130,  131,  131,  132,  132,
241                 133,  133,  134,  134,  135,  135,  136,  136,
242                 137,  137,  138,  138,  139,  139,  140,  140,
243                 141,  141,  142,  142,  143,  143,  144,  144,
244                 145,  145,  145,  146,  146,  147,  147,  148,
245                 148,  149,  149,  150,  150,  150,  151,  151,
246                 152,  152,  153,  153,  153,  154,  154,  155,
247                 155,  156,  156,  156,  157,  157,  158,  158,
248                 158,  159,  159,  160,  160,  160,  161,  161,
249                 162,  162,  162,  163,  163,  164,  164,  164,
250                 165,  165,  166,  166,  166,  167,  167,  167,
251                 168,  168,  169,  169,  169,  170,  170,  170,
252                 171,  171,  172,  172,  172,  173,  173,  173,
253                 174,  174,  174,  175,  175,  176,  176,  176,
254                 177,  177,  177,  178,  178,  178,  179,  179,
255                 179,  180,  180,  180,  181,  181,  182,  182,
256                 182,  183,  183,  183,  184,  184,  184,  185,
257                 185,  185,  186,  186,  186,  187,  187,  187,
258                 188,  188,  188,  189,  189,  189,  189,  190,
259                 190,  190,  191,  191,  191,  192,  192,  192,
260                 193,  193,  193,  194,  194,  194,  195,  195,
261                 195,  196,  196,  196,  196,  197,  197,  197,
262                 198,  198,  198,  199,  199,  199,  200,  200,
263                 200,  200,  201,  201,  201,  202,  202,  202,
264                 202,  203,  203,  203,  204,  204,  204,  205,
265                 205,  205,  205,  206,  206,  206,  207,  207,
266                 207,  207,  208,  208,  208,  209,  209,  209,
267                 209,  210,  210,  210,  211,  211,  211,  211,
268                 212,  212,  212,  213,  213,  213,  213,  214,
269                 214,  214,  214,  215,  215,  215,  216,  216,
270                 216,  216,  217,  217,  217,  217,  218,  218,
271                 218,  219,  219,  219,  219,  220,  220,  220,
272                 220,  221,  221,  221,  221,  222,  222,  222,
273                 223,  223,  223,  223,  224,  224,  224,  224,
274                 225,  225,  225,  225,  226,  226,  226,  226,
275                 227,  227,  227,  227,  228,  228,  228,  228,
276                 229,  229,  229,  229,  230,  230,  230,  230,
277                 231,  231,  231,  231,  232,  232,  232,  232,
278                 233,  233,  233,  233,  234,  234,  234,  234,
279                 235,  235,  235,  235,  236,  236,  236,  236,
280                 237,  237,  237,  237,  238,  238,  238,  238,
281                 239,  239,  239,  239,  240,  240,  240,  240,
282                 240,  241,  241,  241,  241,  242,  242,  242,
283                 242,  243,  243,  243,  243,  244,  244,  244,
284                 244,  244,  245,  245,  245,  245,  246,  246,
285                 246,  246,  247,  247,  247,  247,  247,  248,
286                 248,  248,  248,  249,  249,  249,  249,  249,
287                 250,  250,  250,  250,  251,  251,  251,  251,
288                 251,  252,  252,  252,  252,  253,  253,  253,
289                 253,  253,  254,  254,  254,  254,  255,  255,
290         },
291 };
292
293 static struct tegra_dc_cmu default_limited_cmu = {
294         /* lut1 maps sRGB to linear space. */
295         {
296                 0,    1,    2,    4,    5,    6,    7,    9,
297                 10,   11,   12,   14,   15,   16,   18,   20,
298                 21,   23,   25,   27,   29,   31,   33,   35,
299                 37,   40,   42,   45,   48,   50,   53,   56,
300                 59,   62,   66,   69,   72,   76,   79,   83,
301                 87,   91,   95,   99,   103,  107,  112,  116,
302                 121,  126,  131,  136,  141,  146,  151,  156,
303                 162,  168,  173,  179,  185,  191,  197,  204,
304                 210,  216,  223,  230,  237,  244,  251,  258,
305                 265,  273,  280,  288,  296,  304,  312,  320,
306                 329,  337,  346,  354,  363,  372,  381,  390,
307                 400,  409,  419,  428,  438,  448,  458,  469,
308                 479,  490,  500,  511,  522,  533,  544,  555,
309                 567,  578,  590,  602,  614,  626,  639,  651,
310                 664,  676,  689,  702,  715,  728,  742,  755,
311                 769,  783,  797,  811,  825,  840,  854,  869,
312                 884,  899,  914,  929,  945,  960,  976,  992,
313                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
314                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
315                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
316                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
317                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
318                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
319                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
320                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
321                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
322                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
323                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
324                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
325                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
326                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
327                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
328         },
329         /* csc */
330         {
331                 0x100, 0x000, 0x000,
332                 0x000, 0x100, 0x000,
333                 0x000, 0x000, 0x100,
334         },
335         /*
336          * lut2 maps linear space back to sRGB, where
337          * the output range is [16...235] (limited).
338          */
339         {
340                 16,  17,  17,  18,  19,  19,  20,  21,
341                 22,  22,  23,  24,  24,  25,  26,  26,
342                 27,  27,  28,  29,  29,  30,  30,  31,
343                 31,  32,  32,  32,  33,  33,  34,  34,
344                 35,  35,  35,  36,  36,  36,  37,  37,
345                 38,  38,  38,  39,  39,  39,  40,  40,
346                 40,  41,  41,  41,  41,  42,  42,  42,
347                 43,  43,  43,  43,  44,  44,  44,  45,
348                 45,  45,  45,  46,  46,  46,  46,  47,
349                 47,  47,  47,  48,  48,  48,  48,  49,
350                 49,  49,  49,  49,  50,  50,  50,  50,
351                 51,  51,  51,  51,  51,  52,  52,  52,
352                 52,  53,  53,  53,  53,  53,  54,  54,
353                 54,  54,  54,  55,  55,  55,  55,  55,
354                 56,  56,  56,  56,  56,  56,  57,  57,
355                 57,  57,  57,  58,  58,  58,  58,  58,
356                 58,  59,  59,  59,  59,  59,  60,  60,
357                 60,  60,  60,  60,  61,  61,  61,  61,
358                 61,  61,  62,  62,  62,  62,  62,  62,
359                 63,  63,  63,  63,  63,  63,  63,  64,
360                 64,  64,  64,  64,  64,  65,  65,  65,
361                 65,  65,  65,  65,  66,  66,  66,  66,
362                 66,  66,  67,  67,  67,  67,  67,  67,
363                 67,  68,  68,  68,  68,  68,  68,  68,
364                 69,  69,  69,  69,  69,  69,  69,  69,
365                 70,  70,  70,  70,  70,  70,  70,  71,
366                 71,  71,  71,  71,  71,  71,  72,  72,
367                 72,  72,  72,  72,  72,  72,  73,  73,
368                 73,  73,  73,  73,  73,  73,  74,  74,
369                 74,  74,  74,  74,  74,  74,  75,  75,
370                 75,  75,  75,  75,  75,  75,  76,  76,
371                 76,  76,  76,  76,  76,  76,  76,  77,
372                 77,  77,  77,  77,  77,  77,  77,  78,
373                 78,  78,  78,  78,  78,  78,  78,  78,
374                 79,  79,  79,  79,  79,  79,  79,  79,
375                 80,  80,  80,  80,  80,  80,  80,  80,
376                 80,  81,  81,  81,  81,  81,  81,  81,
377                 81,  81,  81,  82,  82,  82,  82,  82,
378                 82,  82,  82,  82,  83,  83,  83,  83,
379                 83,  83,  83,  83,  83,  84,  84,  84,
380                 84,  84,  84,  84,  84,  84,  84,  85,
381                 85,  85,  85,  85,  85,  85,  85,  85,
382                 85,  86,  86,  86,  86,  86,  86,  86,
383                 86,  86,  86,  87,  87,  87,  87,  87,
384                 87,  87,  87,  87,  87,  88,  88,  88,
385                 88,  88,  88,  88,  88,  88,  88,  89,
386                 89,  89,  89,  89,  89,  89,  89,  89,
387                 89,  89,  90,  90,  90,  90,  90,  90,
388                 90,  90,  90,  90,  91,  91,  91,  91,
389                 91,  91,  91,  91,  91,  91,  91,  92,
390                 92,  92,  92,  92,  92,  92,  92,  92,
391                 92,  92,  93,  93,  93,  93,  93,  93,
392                 93,  93,  93,  93,  93,  94,  94,  94,
393                 94,  94,  94,  94,  94,  94,  94,  94,
394                 94,  95,  95,  95,  95,  95,  95,  95,
395                 95,  95,  95,  95,  96,  96,  96,  96,
396                 96,  96,  96,  96,  96,  96,  96,  96,
397                 97,  97,  97,  97,  97,  97,  97,  97,
398                 97,  97,  97,  97,  98,  98,  98,  98,
399                 98,  98,  98,  98,  98,  98,  98,  98,
400                 99,  99,  99,  99,  99,  99,  99,  99,
401                 99,  99,  99,  99, 100, 100, 100, 100,
402                 100, 100, 100, 100, 100, 100, 100, 100,
403                 100, 101, 101, 101, 101, 101, 101, 101,
404                 102, 102, 103, 104, 104, 105, 105, 106,
405                 107, 107, 108, 108, 109, 109, 110, 111,
406                 111, 112, 112, 113, 113, 114, 114, 115,
407                 115, 116, 116, 117, 117, 118, 118, 119,
408                 119, 120, 120, 121, 121, 122, 122, 123,
409                 123, 124, 124, 125, 125, 126, 126, 127,
410                 127, 127, 128, 128, 129, 129, 130, 130,
411                 131, 131, 131, 132, 132, 133, 133, 134,
412                 134, 134, 135, 135, 136, 136, 136, 137,
413                 137, 138, 138, 139, 139, 139, 140, 140,
414                 141, 141, 141, 142, 142, 142, 143, 143,
415                 144, 144, 144, 145, 145, 145, 146, 146,
416                 147, 147, 147, 148, 148, 148, 149, 149,
417                 150, 150, 150, 151, 151, 151, 152, 152,
418                 152, 153, 153, 153, 154, 154, 154, 155,
419                 155, 155, 156, 156, 156, 157, 157, 157,
420                 158, 158, 158, 159, 159, 159, 160, 160,
421                 160, 161, 161, 161, 162, 162, 162, 163,
422                 163, 163, 164, 164, 164, 165, 165, 165,
423                 166, 166, 166, 166, 167, 167, 167, 168,
424                 168, 168, 169, 169, 169, 169, 170, 170,
425                 170, 171, 171, 171, 172, 172, 172, 172,
426                 173, 173, 173, 174, 174, 174, 174, 175,
427                 175, 175, 176, 176, 176, 176, 177, 177,
428                 177, 178, 178, 178, 178, 179, 179, 179,
429                 180, 180, 180, 180, 181, 181, 181, 181,
430                 182, 182, 182, 183, 183, 183, 183, 184,
431                 184, 184, 184, 185, 185, 185, 185, 186,
432                 186, 186, 187, 187, 187, 187, 188, 188,
433                 188, 188, 189, 189, 189, 189, 190, 190,
434                 190, 190, 191, 191, 191, 191, 192, 192,
435                 192, 192, 193, 193, 193, 193, 194, 194,
436                 194, 194, 195, 195, 195, 195, 196, 196,
437                 196, 196, 197, 197, 197, 197, 198, 198,
438                 198, 198, 199, 199, 199, 199, 199, 200,
439                 200, 200, 200, 201, 201, 201, 201, 202,
440                 202, 202, 202, 203, 203, 203, 203, 203,
441                 204, 204, 204, 204, 205, 205, 205, 205,
442                 206, 206, 206, 206, 206, 207, 207, 207,
443                 207, 208, 208, 208, 208, 208, 209, 209,
444                 209, 209, 210, 210, 210, 210, 210, 211,
445                 211, 211, 211, 212, 212, 212, 212, 212,
446                 213, 213, 213, 213, 213, 214, 214, 214,
447                 214, 215, 215, 215, 215, 215, 216, 216,
448                 216, 216, 216, 217, 217, 217, 217, 218,
449                 218, 218, 218, 218, 219, 219, 219, 219,
450                 219, 220, 220, 220, 220, 220, 221, 221,
451                 221, 221, 221, 222, 222, 222, 222, 222,
452                 223, 223, 223, 223, 224, 224, 224, 224,
453                 224, 225, 225, 225, 225, 225, 226, 226,
454                 226, 226, 226, 227, 227, 227, 227, 227,
455                 227, 228, 228, 228, 228, 228, 229, 229,
456                 229, 229, 229, 230, 230, 230, 230, 230,
457                 231, 231, 231, 231, 231, 232, 232, 232,
458                 232, 232, 233, 233, 233, 233, 233, 233,
459                 234, 234, 234, 234, 234, 235, 235, 235,
460         },
461 };
462 #endif
463
464 void tegra_dc_clk_enable(struct tegra_dc *dc)
465 {
466         clk_prepare_enable(dc->clk);
467         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
468 }
469
470 void tegra_dc_clk_disable(struct tegra_dc *dc)
471 {
472         clk_disable_unprepare(dc->clk);
473         tegra_dvfs_set_rate(dc->clk, 0);
474 }
475
476 void tegra_dc_get(struct tegra_dc *dc)
477 {
478         tegra_dc_io_start(dc);
479
480         /* extra reference to dc clk */
481         clk_prepare_enable(dc->clk);
482 }
483
484 void tegra_dc_put(struct tegra_dc *dc)
485 {
486         /* balance extra dc clk reference */
487         clk_disable_unprepare(dc->clk);
488
489         tegra_dc_io_end(dc);
490 }
491
492 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
493 {
494         tegra_dc_get(dc);
495         if (dc->out_ops && dc->out_ops->hold)
496                 dc->out_ops->hold(dc);
497 }
498
499 void tegra_dc_release_dc_out(struct tegra_dc *dc)
500 {
501         if (dc->out_ops && dc->out_ops->release)
502                 dc->out_ops->release(dc);
503         tegra_dc_put(dc);
504 }
505
506 #define DUMP_REG(a) do {                        \
507         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
508                  #a, a, tegra_dc_readl(dc, a));               \
509         print(data, buff);                                    \
510         } while (0)
511
512 static void _dump_regs(struct tegra_dc *dc, void *data,
513                        void (* print)(void *data, const char *str))
514 {
515         int i;
516         char buff[256];
517         const char winname[] = "ABCDHT";
518         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
519
520         /* If gated, quietly return. */
521         if (!tegra_powergate_is_powered(dc->powergate_id))
522                 return;
523
524         mutex_lock(&dc->lock);
525         tegra_dc_get(dc);
526         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
527                 DC_CMD_STATE_ACCESS);
528
529         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
530         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
531         DUMP_REG(DC_CMD_SIGNAL_RAISE);
532         DUMP_REG(DC_CMD_INT_STATUS);
533         DUMP_REG(DC_CMD_INT_MASK);
534         DUMP_REG(DC_CMD_INT_ENABLE);
535         DUMP_REG(DC_CMD_INT_TYPE);
536         DUMP_REG(DC_CMD_INT_POLARITY);
537         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
538         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
539         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
540         DUMP_REG(DC_CMD_STATE_ACCESS);
541         DUMP_REG(DC_CMD_STATE_CONTROL);
542         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
543         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
544
545         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
546         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
547         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
548         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
549         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
550         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
551         DUMP_REG(DC_DISP_REF_TO_SYNC);
552         DUMP_REG(DC_DISP_SYNC_WIDTH);
553         DUMP_REG(DC_DISP_BACK_PORCH);
554         DUMP_REG(DC_DISP_DISP_ACTIVE);
555         DUMP_REG(DC_DISP_FRONT_PORCH);
556         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
557         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
558         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
559         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
560         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
561         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
562         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
563         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
564         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
565         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
566         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
567         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
568         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
569         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
570         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
571         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
572         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
573         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
574         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
575         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
576         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
577         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
578         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
579         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
580         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
581         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
582         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
583         DUMP_REG(DC_DISP_M0_CONTROL);
584         DUMP_REG(DC_DISP_M1_CONTROL);
585         DUMP_REG(DC_DISP_DI_CONTROL);
586         DUMP_REG(DC_DISP_PP_CONTROL);
587         DUMP_REG(DC_DISP_PP_SELECT_A);
588         DUMP_REG(DC_DISP_PP_SELECT_B);
589         DUMP_REG(DC_DISP_PP_SELECT_C);
590         DUMP_REG(DC_DISP_PP_SELECT_D);
591         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
592         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
593         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
594         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
595         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
596         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
597         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
598 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
599         DUMP_REG(DC_DISP_BORDER_COLOR);
600 #endif
601         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
602         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
603         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
604         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
605         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
606         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
607         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
608         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
609 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
610         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
611         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
612 #endif
613         DUMP_REG(DC_DISP_CURSOR_POSITION);
614         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
615         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
616         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
617         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
618         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
619         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
620         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
621         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
622         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
623         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
624 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
625         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
626 #endif
627         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
628         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
629 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) && defined(CONFIG_TEGRA_DC_INTERLACE)
630         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
631         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
632         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
633         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
634         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
635         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
636 #endif
637         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
638                 print(data, "\n");
639                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
640                 print(data, buff);
641
642                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
643                                 DC_CMD_DISPLAY_WINDOW_HEADER);
644                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
645                 DUMP_REG(DC_WIN_WIN_OPTIONS);
646                 DUMP_REG(DC_WIN_BYTE_SWAP);
647                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
648                 DUMP_REG(DC_WIN_COLOR_DEPTH);
649                 DUMP_REG(DC_WIN_POSITION);
650                 DUMP_REG(DC_WIN_SIZE);
651                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
652                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
653                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
654                 DUMP_REG(DC_WIN_DDA_INCREMENT);
655                 DUMP_REG(DC_WIN_LINE_STRIDE);
656 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
657                 DUMP_REG(DC_WIN_BUF_STRIDE);
658                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
659 #endif
660                 DUMP_REG(DC_WIN_BLEND_NOKEY);
661                 DUMP_REG(DC_WIN_BLEND_1WIN);
662                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
663                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
664                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
665                 DUMP_REG(DC_WINBUF_START_ADDR);
666                 DUMP_REG(DC_WINBUF_START_ADDR_U);
667                 DUMP_REG(DC_WINBUF_START_ADDR_V);
668                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
669                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
670 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
671                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
672                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
673                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
674                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
675                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
676                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
677                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
678                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
679                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
680                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
681                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
682 #endif
683                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
684                 DUMP_REG(DC_WIN_CSC_YOF);
685                 DUMP_REG(DC_WIN_CSC_KYRGB);
686                 DUMP_REG(DC_WIN_CSC_KUR);
687                 DUMP_REG(DC_WIN_CSC_KVR);
688                 DUMP_REG(DC_WIN_CSC_KUG);
689                 DUMP_REG(DC_WIN_CSC_KVG);
690                 DUMP_REG(DC_WIN_CSC_KUB);
691                 DUMP_REG(DC_WIN_CSC_KVB);
692         }
693
694         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
695         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
696         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
697         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
698         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
699         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
700         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
701         DUMP_REG(DC_DISP_M1_CONTROL);
702         DUMP_REG(DC_COM_PM1_CONTROL);
703         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
704         DUMP_REG(DC_DISP_SD_CONTROL);
705 #ifdef CONFIG_TEGRA_DC_CMU
706         DUMP_REG(DC_COM_CMU_CSC_KRR);
707         DUMP_REG(DC_COM_CMU_CSC_KGR);
708         DUMP_REG(DC_COM_CMU_CSC_KBR);
709         DUMP_REG(DC_COM_CMU_CSC_KRG);
710         DUMP_REG(DC_COM_CMU_CSC_KGG);
711         DUMP_REG(DC_COM_CMU_CSC_KBR);
712         DUMP_REG(DC_COM_CMU_CSC_KRB);
713         DUMP_REG(DC_COM_CMU_CSC_KGB);
714         DUMP_REG(DC_COM_CMU_CSC_KBB);
715 #endif
716
717         tegra_dc_put(dc);
718         mutex_unlock(&dc->lock);
719 }
720
721 #undef DUMP_REG
722
723 #ifdef DEBUG
724 static void dump_regs_print(void *data, const char *str)
725 {
726         struct tegra_dc *dc = data;
727         dev_dbg(&dc->ndev->dev, "%s", str);
728 }
729
730 static void dump_regs(struct tegra_dc *dc)
731 {
732         _dump_regs(dc, dc, dump_regs_print);
733 }
734 #else /* !DEBUG */
735
736 static void dump_regs(struct tegra_dc *dc) {}
737
738 #endif /* DEBUG */
739
740 #ifdef CONFIG_DEBUG_FS
741
742 static void dbg_regs_print(void *data, const char *str)
743 {
744         struct seq_file *s = data;
745
746         seq_printf(s, "%s", str);
747 }
748
749 #undef DUMP_REG
750
751 static int dbg_dc_show(struct seq_file *s, void *unused)
752 {
753         struct tegra_dc *dc = s->private;
754
755         _dump_regs(dc, s, dbg_regs_print);
756
757         return 0;
758 }
759
760
761 static int dbg_dc_open(struct inode *inode, struct file *file)
762 {
763         return single_open(file, dbg_dc_show, inode->i_private);
764 }
765
766 static const struct file_operations regs_fops = {
767         .open           = dbg_dc_open,
768         .read           = seq_read,
769         .llseek         = seq_lseek,
770         .release        = single_release,
771 };
772
773 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
774 {
775         struct tegra_dc *dc = s->private;
776         struct tegra_dc_mode *m;
777
778         mutex_lock(&dc->lock);
779         m = &dc->mode;
780         seq_printf(s,
781                 "pclk: %d\n"
782                 "h_ref_to_sync: %d\n"
783                 "v_ref_to_sync: %d\n"
784                 "h_sync_width: %d\n"
785                 "v_sync_width: %d\n"
786                 "h_back_porch: %d\n"
787                 "v_back_porch: %d\n"
788                 "h_active: %d\n"
789                 "v_active: %d\n"
790                 "h_front_porch: %d\n"
791                 "v_front_porch: %d\n"
792                 "stereo_mode: %d\n",
793                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
794                 m->h_sync_width, m->v_sync_width,
795                 m->h_back_porch, m->v_back_porch,
796                 m->h_active, m->v_active,
797                 m->h_front_porch, m->v_front_porch,
798                 m->stereo_mode);
799         mutex_unlock(&dc->lock);
800         return 0;
801 }
802
803 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
804 {
805         return single_open(file, dbg_dc_mode_show, inode->i_private);
806 }
807
808 static const struct file_operations mode_fops = {
809         .open           = dbg_dc_mode_open,
810         .read           = seq_read,
811         .llseek         = seq_lseek,
812         .release        = single_release,
813 };
814
815 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
816 {
817         struct tegra_dc *dc = s->private;
818
819         mutex_lock(&dc->lock);
820         seq_printf(s,
821                 "underflows: %llu\n"
822                 "underflows_a: %llu\n"
823                 "underflows_b: %llu\n"
824                 "underflows_c: %llu\n",
825                 dc->stats.underflows,
826                 dc->stats.underflows_a,
827                 dc->stats.underflows_b,
828                 dc->stats.underflows_c);
829 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
830         seq_printf(s,
831                 "underflows_d: %llu\n"
832                 "underflows_h: %llu\n"
833                 "underflows_t: %llu\n",
834                 dc->stats.underflows_d,
835                 dc->stats.underflows_h,
836                 dc->stats.underflows_t);
837 #endif
838         mutex_unlock(&dc->lock);
839
840         return 0;
841 }
842
843 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
844 {
845         return single_open(file, dbg_dc_stats_show, inode->i_private);
846 }
847
848 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
849 {
850         return 0;
851 }
852
853 static ssize_t dbg_dc_event_inject_write(struct file *file,
854         const char __user *addr, size_t len, loff_t *pos)
855 {
856         struct seq_file *m = file->private_data; /* single_open() initialized */
857         struct tegra_dc *dc = m ? m->private : NULL;
858         long event;
859         int ret;
860
861         if (!dc)
862                 return -EINVAL;
863
864         ret = kstrtol_from_user(addr, len, 10, &event);
865         if (ret < 0)
866                 return ret;
867
868         if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG */
869                 tegra_dc_ext_process_hotplug(dc->ndev->id);
870         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
871                 tegra_dc_ext_process_bandwidth_renegotiate(
872                                 dc->ndev->id, NULL);
873         else {
874                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
875                 return -EINVAL; /* unknown event number */
876         }
877         return len;
878 }
879
880 static const struct file_operations stats_fops = {
881         .open           = dbg_dc_stats_open,
882         .read           = seq_read,
883         .llseek         = seq_lseek,
884         .release        = single_release,
885 };
886
887 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
888 {
889         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
890 }
891
892 static const struct file_operations event_inject_fops = {
893         .open           = dbg_dc_event_inject_open,
894         .read           = seq_read,
895         .write          = dbg_dc_event_inject_write,
896         .llseek         = seq_lseek,
897         .release        = single_release,
898 };
899
900 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
901 {
902         if (dc->debugdir)
903                 debugfs_remove_recursive(dc->debugdir);
904         dc->debugdir = NULL;
905 }
906
907 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
908 {
909         struct dentry *retval;
910
911         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
912         if (!dc->debugdir)
913                 goto remove_out;
914
915         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
916                 &regs_fops);
917         if (!retval)
918                 goto remove_out;
919
920         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
921                 &mode_fops);
922         if (!retval)
923                 goto remove_out;
924
925         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
926                 &stats_fops);
927         if (!retval)
928                 goto remove_out;
929
930         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
931                 &event_inject_fops);
932         if (!retval)
933                 goto remove_out;
934
935         return;
936 remove_out:
937         dev_err(&dc->ndev->dev, "could not create debugfs\n");
938         tegra_dc_remove_debugfs(dc);
939 }
940
941 #else /* !CONFIG_DEBUGFS */
942 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
943 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
944 #endif /* CONFIG_DEBUGFS */
945
946 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
947                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
948 {
949         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
950         u32 reg_val = 0;
951
952         do {
953                 usleep_range(poll_interval_us, poll_interval_us << 1);
954                 reg_val = tegra_dc_readl(dc, reg);
955         } while (((reg_val & mask) != exp_val) &&
956                 time_after(timeout_jf, jiffies));
957
958         if ((reg_val & mask) == exp_val)
959                 return 0;       /* success */
960         dev_err(&dc->ndev->dev,
961                 "dc_poll_register 0x%x: timeout\n", reg);
962         return jiffies - timeout_jf + 1;
963 }
964
965 static int tegra_dc_set(struct tegra_dc *dc, int index)
966 {
967         int ret = 0;
968
969         mutex_lock(&tegra_dc_lock);
970         if (index >= TEGRA_MAX_DC) {
971                 ret = -EINVAL;
972                 goto out;
973         }
974
975         if (dc != NULL && tegra_dcs[index] != NULL) {
976                 ret = -EBUSY;
977                 goto out;
978         }
979
980         tegra_dcs[index] = dc;
981
982 out:
983         mutex_unlock(&tegra_dc_lock);
984
985         return ret;
986 }
987
988 unsigned int tegra_dc_has_multiple_dc(void)
989 {
990         unsigned int idx;
991         unsigned int cnt = 0;
992         struct tegra_dc *dc;
993
994         mutex_lock(&tegra_dc_lock);
995         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
996                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
997         mutex_unlock(&tegra_dc_lock);
998
999         return (cnt > 1);
1000 }
1001
1002 /* get the stride size of a window.
1003  * return: stride size in bytes for window win. or 0 if unavailble. */
1004 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1005 {
1006         u32 stride;
1007
1008         if (!dc->enabled)
1009                 return 0;
1010         BUG_ON(win > DC_N_WINDOWS);
1011         mutex_lock(&dc->lock);
1012         tegra_dc_get(dc);
1013         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1014                 DC_CMD_DISPLAY_WINDOW_HEADER);
1015         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1016         tegra_dc_put(dc);
1017         mutex_unlock(&dc->lock);
1018         return GET_LINE_STRIDE(stride);
1019 }
1020 EXPORT_SYMBOL(tegra_dc_get_stride);
1021
1022 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1023 {
1024         if (idx < TEGRA_MAX_DC)
1025                 return tegra_dcs[idx];
1026         else
1027                 return NULL;
1028 }
1029 EXPORT_SYMBOL(tegra_dc_get_dc);
1030
1031 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1032 {
1033         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1034                 return NULL;
1035
1036         return &dc->windows[win];
1037 }
1038 EXPORT_SYMBOL(tegra_dc_get_window);
1039
1040 bool tegra_dc_get_connected(struct tegra_dc *dc)
1041 {
1042         return dc->connected;
1043 }
1044 EXPORT_SYMBOL(tegra_dc_get_connected);
1045
1046 bool tegra_dc_hpd(struct tegra_dc *dc)
1047 {
1048         int sense;
1049         int level;
1050         int hpd;
1051
1052         if (WARN_ON(!dc || !dc->out))
1053                 return false;
1054
1055         if (dc->out->hotplug_state != 0) {
1056                 if (dc->out->hotplug_state == 1) /* force on */
1057                         return true;
1058                 if (dc->out->hotplug_state == -1) /* force off */
1059                         return false;
1060         }
1061         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
1062
1063         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1064
1065         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1066                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1067
1068         if (dc->out->hotplug_report)
1069                 dc->out->hotplug_report(hpd);
1070
1071         return hpd;
1072 }
1073 EXPORT_SYMBOL(tegra_dc_hpd);
1074
1075 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1076 {
1077         unsigned i;
1078         unsigned v0 = 128;
1079         unsigned v1 = 0;
1080
1081         /* linear horizontal and vertical filters */
1082         for (i = 0; i < 16; i++) {
1083                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1084                                 DC_WIN_H_FILTER_P(i));
1085
1086                 tegra_dc_writel(dc, v0,
1087                                 DC_WIN_V_FILTER_P(i));
1088                 v0 -= 8;
1089                 v1 += 8;
1090         }
1091 }
1092
1093 #ifdef CONFIG_TEGRA_DC_CMU
1094 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
1095                                         struct tegra_dc_cmu *src_cmu)
1096 {
1097         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
1098                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
1099         dc->cmu_dirty = true;
1100 }
1101
1102 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1103 {
1104         u32 val;
1105         u32 i;
1106
1107         for (i = 0; i < 256; i++) {
1108                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1109                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1110         }
1111
1112         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1113         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1114         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1115         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1116         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1117         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1118         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1119         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1120         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1121
1122         for (i = 0; i < 960; i++) {
1123                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1124                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1125         }
1126
1127         dc->cmu_dirty = false;
1128 }
1129
1130 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1131 {
1132         u32 val;
1133
1134         if (!dc->cmu_enabled)
1135                 return;
1136
1137         tegra_dc_cache_cmu(dc, cmu);
1138
1139         if (dc->cmu_dirty) {
1140                 /* Disable CMU to avoid programming it while it is in use */
1141                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1142                 if (val & CMU_ENABLE) {
1143                         val &= ~CMU_ENABLE;
1144                         tegra_dc_writel(dc, val,
1145                                         DC_DISP_DISP_COLOR_CONTROL);
1146                         val = GENERAL_ACT_REQ;
1147                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
1148                         /*TODO: Sync up with vsync */
1149                         mdelay(20);
1150                 }
1151                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
1152                         dc->cmu_dirty);
1153
1154                 tegra_dc_set_cmu(dc, &dc->cmu);
1155         }
1156 }
1157
1158 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1159 {
1160         mutex_lock(&dc->lock);
1161         if (!dc->enabled) {
1162                 mutex_unlock(&dc->lock);
1163                 return 0;
1164         }
1165
1166         tegra_dc_get(dc);
1167
1168         _tegra_dc_update_cmu(dc, cmu);
1169         tegra_dc_set_color_control(dc);
1170
1171         tegra_dc_put(dc);
1172         mutex_unlock(&dc->lock);
1173
1174         return 0;
1175 }
1176 EXPORT_SYMBOL(tegra_dc_update_cmu);
1177
1178 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
1179 {
1180         if (dc->pdata->cmu)
1181                 return dc->pdata->cmu;
1182         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
1183                 return &default_limited_cmu;
1184         else
1185                 return &default_cmu;
1186 }
1187
1188 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
1189 {
1190         dc->cmu_enabled = cmu_enable;
1191         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
1192 }
1193 #else
1194 #define tegra_dc_cache_cmu(dc, src_cmu)
1195 #define tegra_dc_set_cmu(dc, cmu)
1196 #define tegra_dc_update_cmu(dc, cmu)
1197 #endif
1198
1199 /* disable_irq() blocks until handler completes, calling this function while
1200  * holding dc->lock can deadlock. */
1201 static inline void disable_dc_irq(const struct tegra_dc *dc)
1202 {
1203         disable_irq(dc->irq);
1204 }
1205
1206 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1207 {
1208         return dc->syncpt[i].id;
1209 }
1210 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1211
1212 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1213 {
1214         u32 max;
1215
1216         mutex_lock(&dc->lock);
1217         tegra_dc_get(dc);
1218         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1219                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1220         dc->syncpt[i].max = max;
1221         tegra_dc_put(dc);
1222         mutex_unlock(&dc->lock);
1223
1224         return max;
1225 }
1226
1227 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1228 {
1229         mutex_lock(&dc->lock);
1230
1231         tegra_dc_get(dc);
1232         while (dc->syncpt[i].min < val) {
1233                 dc->syncpt[i].min++;
1234                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1235                 }
1236         tegra_dc_put(dc);
1237         mutex_unlock(&dc->lock);
1238 }
1239
1240 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
1241 {
1242         struct nvhost_ctrl_sync_fence_info syncpt;
1243         u32 id = tegra_dc_get_syncpt_id(dc, i);
1244
1245         syncpt.id = id;
1246         syncpt.thresh = val;
1247         return nvhost_sync_create_fence(
1248                         to_platform_device(dc->ndev->dev.parent),
1249                         &syncpt, 1, dev_name(&dc->ndev->dev));
1250 }
1251
1252 void
1253 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1254 {
1255         unsigned int ctrl;
1256         unsigned long out_sel;
1257         unsigned long cmd_state;
1258
1259         mutex_lock(&dc->lock);
1260         if (!dc->enabled) {
1261                 mutex_unlock(&dc->lock);
1262                 return;
1263         }
1264
1265         tegra_dc_get(dc);
1266
1267         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1268                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1269                 cfg->clk_select);
1270
1271         /* The new value should be effected immediately */
1272         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1273         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1274
1275         switch (cfg->which_pwm) {
1276         case TEGRA_PWM_PM0:
1277                 /* Select the LM0 on PM0 */
1278                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1279                 out_sel &= ~(7 << 0);
1280                 out_sel |= (3 << 0);
1281                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1282                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1283                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1284                 break;
1285         case TEGRA_PWM_PM1:
1286                 /* Select the LM1 on PM1 */
1287                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1288                 out_sel &= ~(7 << 4);
1289                 out_sel |= (3 << 4);
1290                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1291                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1292                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1293                 break;
1294         default:
1295                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1296                 break;
1297         }
1298         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1299         tegra_dc_put(dc);
1300         mutex_unlock(&dc->lock);
1301 }
1302 EXPORT_SYMBOL(tegra_dc_config_pwm);
1303
1304 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1305                                 const struct tegra_dc_out_pin *pins,
1306                                 const unsigned int n_pins)
1307 {
1308         unsigned int i;
1309
1310         int name;
1311         int pol;
1312
1313         u32 pol1, pol3;
1314
1315         u32 set1, unset1;
1316         u32 set3, unset3;
1317
1318         set1 = set3 = unset1 = unset3 = 0;
1319
1320         for (i = 0; i < n_pins; i++) {
1321                 name = (pins + i)->name;
1322                 pol  = (pins + i)->pol;
1323
1324                 /* set polarity by name */
1325                 switch (name) {
1326                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1327                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1328                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1329                         else
1330                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1331                         break;
1332                 case TEGRA_DC_OUT_PIN_H_SYNC:
1333                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1334                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1335                         else
1336                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1337                         break;
1338                 case TEGRA_DC_OUT_PIN_V_SYNC:
1339                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1340                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1341                         else
1342                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1343                         break;
1344                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1345                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1346                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1347                         else
1348                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1349                         break;
1350                 default:
1351                         printk("Invalid argument in function %s\n",
1352                                __FUNCTION__);
1353                         break;
1354                 }
1355         }
1356
1357         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1358         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1359
1360         pol1 |= set1;
1361         pol1 &= ~unset1;
1362
1363         pol3 |= set3;
1364         pol3 &= ~unset3;
1365
1366         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1367         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1368 }
1369
1370 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1371 {
1372         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1373                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1374                 dc->out->type == TEGRA_DC_OUT_DSI)
1375                 return override_disp_mode[dc->out->type].pclk ?
1376                         &override_disp_mode[dc->out->type] : NULL;
1377         else
1378                 return NULL;
1379 }
1380
1381 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1382 {
1383         struct tegra_dc_mode *mode;
1384         int err = 0;
1385
1386         dc->out = out;
1387         mode = tegra_dc_get_override_mode(dc);
1388
1389         if (mode) {
1390                 tegra_dc_set_mode(dc, mode);
1391
1392                 /*
1393                  * Bootloader should and should only pass disp_params if
1394                  * it has initialized display controller.  Whenever we see
1395                  * override modes, we should skip things cause display resets.
1396                  */
1397                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
1398                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
1399                                 dc->mode.h_active, dc->mode.v_active,
1400                                 dc->out->h_size, dc->out->v_size,
1401                                 dc->mode.pclk);
1402                 dc->initialized = true;
1403
1404 #ifdef CONFIG_TEGRA_DC_CMU
1405                 /*
1406                  * If the bootloader already set the mode, assume the CMU
1407                  * parameters are also correctly set. It would be better to
1408                  * read them, but unfortunately there is no reliable and
1409                  * flicker-free way to do this!
1410                  */
1411                 tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
1412 #endif
1413         } else if (out->n_modes > 0)
1414                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1415
1416         switch (out->type) {
1417         case TEGRA_DC_OUT_RGB:
1418                 dc->out_ops = &tegra_dc_rgb_ops;
1419                 break;
1420
1421         case TEGRA_DC_OUT_HDMI:
1422                 dc->out_ops = &tegra_dc_hdmi_ops;
1423                 break;
1424
1425         case TEGRA_DC_OUT_DSI:
1426                 dc->out_ops = &tegra_dc_dsi_ops;
1427                 break;
1428
1429 #ifdef CONFIG_TEGRA_DP
1430         case TEGRA_DC_OUT_DP:
1431                 dc->out_ops = &tegra_dc_dp_ops;
1432                 break;
1433 #ifdef CONFIG_TEGRA_NVSR
1434         case TEGRA_DC_OUT_NVSR_DP:
1435                 dc->out_ops = &tegra_dc_nvsr_ops;
1436                 break;
1437 #endif
1438 #endif
1439 #ifdef CONFIG_TEGRA_LVDS
1440         case TEGRA_DC_OUT_LVDS:
1441                 dc->out_ops = &tegra_dc_lvds_ops;
1442                 break;
1443 #endif
1444         default:
1445                 dc->out_ops = NULL;
1446                 break;
1447         }
1448
1449         if (dc->out_ops && dc->out_ops->init) {
1450                 err = dc->out_ops->init(dc);
1451                 if (err < 0) {
1452                         dc->out = NULL;
1453                         dc->out_ops = NULL;
1454                         dev_err(&dc->ndev->dev,
1455                                 "Error: out->type:%d out_ops->init() failed\n",
1456                                 out->type);
1457                         return err;
1458                 }
1459         }
1460
1461         return err;
1462 }
1463
1464 /* returns on error: -EINVAL
1465  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, or TEGRA_DC_OUT_DSI. */
1466 int tegra_dc_get_out(const struct tegra_dc *dc)
1467 {
1468         if (dc && dc->out)
1469                 return dc->out->type;
1470         return -EINVAL;
1471 }
1472
1473 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1474 {
1475         if (dc->out)
1476                 return dc->out->height;
1477         else
1478                 return 0;
1479 }
1480 EXPORT_SYMBOL(tegra_dc_get_out_height);
1481
1482 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1483 {
1484         if (dc->out)
1485                 return dc->out->width;
1486         else
1487                 return 0;
1488 }
1489 EXPORT_SYMBOL(tegra_dc_get_out_width);
1490
1491 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1492 {
1493         if (dc && dc->out)
1494                 return dc->out->max_pixclock;
1495         else
1496                 return 0;
1497 }
1498 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1499
1500 void tegra_dc_enable_crc(struct tegra_dc *dc)
1501 {
1502         u32 val;
1503
1504         mutex_lock(&dc->lock);
1505         tegra_dc_get(dc);
1506
1507         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1508                 CRC_ENABLE_ENABLE;
1509         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1510         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1511         tegra_dc_put(dc);
1512         mutex_unlock(&dc->lock);
1513
1514         /* Register a client of frame_end interrupt */
1515         tegra_dc_config_frame_end_intr(dc, true);
1516 }
1517
1518 void tegra_dc_disable_crc(struct tegra_dc *dc)
1519 {
1520         /* Unregister a client of frame_end interrupt */
1521         tegra_dc_config_frame_end_intr(dc, false);
1522
1523         mutex_lock(&dc->lock);
1524         tegra_dc_get(dc);
1525         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1526         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1527
1528         tegra_dc_put(dc);
1529         mutex_unlock(&dc->lock);
1530 }
1531
1532 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1533 {
1534         int crc = 0;
1535
1536         if (!dc) {
1537                 pr_err("Failed to get dc: NULL parameter.\n");
1538                 goto crc_error;
1539         }
1540
1541         /* If gated quitely return */
1542         if (!tegra_dc_is_powered(dc))
1543                 return 0;
1544
1545         INIT_COMPLETION(dc->crc_complete);
1546         if (dc->crc_pending &&
1547             wait_for_completion_interruptible(&dc->crc_complete)) {
1548                 pr_err("CRC read interrupted.\n");
1549                 goto crc_error;
1550         }
1551
1552         mutex_lock(&dc->lock);
1553         tegra_dc_get(dc);
1554         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1555         tegra_dc_put(dc);
1556         mutex_unlock(&dc->lock);
1557 crc_error:
1558         return crc;
1559 }
1560
1561 static bool tegra_dc_windows_are_dirty(struct tegra_dc *dc)
1562 {
1563         u32 val;
1564
1565         if (tegra_platform_is_linsim())
1566                 return false;
1567
1568         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1569         if (val & WIN_ALL_ACT_REQ)
1570                 return true;
1571
1572         return false;
1573 }
1574
1575 static inline void enable_dc_irq(const struct tegra_dc *dc)
1576 {
1577         if (tegra_platform_is_fpga())
1578                 /* Always disable DC interrupts on FPGA. */
1579                 disable_irq(dc->irq);
1580         else
1581                 enable_irq(dc->irq);
1582 }
1583
1584 bool tegra_dc_has_vsync(struct tegra_dc *dc)
1585 {
1586         return !!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE);
1587 }
1588
1589 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
1590 {
1591         int ret = -ENOTTY;
1592
1593         /* Generally vsync comes at 60Hz (~16.67ms per cycle).
1594          * 2 time periods should be good enough for the timeout.
1595          * We add some margin here for the default timeout value.
1596          */
1597         unsigned long timeout_ms = 40;
1598
1599         if (dc->out->type == TEGRA_DC_OUT_DSI &&
1600                 dc->out->dsi->rated_refresh_rate != 0)
1601                 timeout_ms = 2 * DIV_ROUND_UP(1000,
1602                          dc->out->dsi->rated_refresh_rate);
1603
1604         mutex_lock(&dc->one_shot_lp_lock);
1605
1606         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) || !dc->enabled) {
1607                 mutex_unlock(&dc->one_shot_lp_lock);
1608                 return ret;
1609         }
1610
1611         tegra_dc_get(dc);
1612         if (dc->out_ops && dc->out_ops->hold)
1613                 dc->out_ops->hold(dc);
1614
1615         /*
1616          * Logic is as follows
1617          * a) Indicate we need a vblank.
1618          * b) Wait for completion to be signalled from isr.
1619          * c) Initialize completion for next iteration.
1620          */
1621
1622         dc->out->user_needs_vblank = true;
1623
1624         mutex_lock(&dc->lock);
1625         tegra_dc_unmask_interrupt(dc, MSF_INT);
1626         mutex_unlock(&dc->lock);
1627
1628         ret = wait_for_completion_interruptible_timeout(
1629                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
1630         init_completion(&dc->out->user_vblank_comp);
1631
1632         mutex_lock(&dc->lock);
1633         tegra_dc_mask_interrupt(dc, MSF_INT);
1634         mutex_unlock(&dc->lock);
1635
1636         if (dc->out_ops && dc->out_ops->release)
1637                 dc->out_ops->release(dc);
1638         tegra_dc_put(dc);
1639
1640         mutex_unlock(&dc->one_shot_lp_lock);
1641         return ret;
1642 }
1643
1644 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
1645 {
1646         tegra_dc_io_start(dc);
1647         if (enable) {
1648                 atomic_inc(&dc->frame_end_ref);
1649                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
1650         } else if (!atomic_dec_return(&dc->frame_end_ref))
1651                 tegra_dc_mask_interrupt(dc, FRAME_END_INT);
1652         tegra_dc_io_end(dc);
1653
1654         return 0;
1655 }
1656
1657 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
1658         u32 timeout_ms)
1659 {
1660         int ret;
1661
1662         INIT_COMPLETION(dc->frame_end_complete);
1663
1664         tegra_dc_get(dc);
1665
1666         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
1667         /* unmask frame end interrupt */
1668         _tegra_dc_config_frame_end_intr(dc, true);
1669
1670         ret = wait_for_completion_interruptible_timeout(
1671                         &dc->frame_end_complete,
1672                         msecs_to_jiffies(timeout_ms));
1673
1674         _tegra_dc_config_frame_end_intr(dc, false);
1675
1676         tegra_dc_put(dc);
1677
1678         return ret;
1679 }
1680
1681 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
1682 {
1683         /* Do the actual brightness update outside of the mutex dc->lock */
1684         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
1685                 dc->out->sd_settings->bl_device_name) {
1686                 char *bl_device_name =
1687                         dc->out->sd_settings->bl_device_name;
1688                 dc->out->sd_settings->bl_device =
1689                         get_backlight_device_by_name(bl_device_name);
1690         }
1691
1692         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
1693                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
1694                 backlight_update_status(bl);
1695         }
1696 }
1697
1698 void tegra_dc_vsync_enable(struct tegra_dc *dc)
1699 {
1700         mutex_lock(&dc->lock);
1701         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
1702         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1703         mutex_unlock(&dc->lock);
1704 }
1705
1706 void tegra_dc_vsync_disable(struct tegra_dc *dc)
1707 {
1708         mutex_lock(&dc->lock);
1709         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
1710         if (!dc->vblank_ref_count)
1711                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1712         mutex_unlock(&dc->lock);
1713 }
1714
1715 static void tegra_dc_vblank(struct work_struct *work)
1716 {
1717         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
1718         bool nvsd_updated = false;
1719
1720         mutex_lock(&dc->lock);
1721
1722         if (!dc->enabled) {
1723                 mutex_unlock(&dc->lock);
1724                 return;
1725         }
1726
1727         tegra_dc_get(dc);
1728
1729         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
1730         if (!tegra_dc_windows_are_dirty(dc))
1731                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
1732
1733         /* Update the SD brightness */
1734         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
1735                 nvsd_updated = nvsd_update_brightness(dc);
1736                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
1737                  * V_BLANK_NVSD bit of vblank ref-count. */
1738                 if (nvsd_updated) {
1739                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1740                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
1741                 } else {
1742                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
1743                 }
1744         }
1745
1746         /* Mask vblank interrupt if ref-count is zero. */
1747         if (!dc->vblank_ref_count)
1748                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
1749
1750         tegra_dc_put(dc);
1751         mutex_unlock(&dc->lock);
1752
1753         /* Do the actual brightness update outside of the mutex dc->lock */
1754         if (nvsd_updated)
1755                 tegra_dc_prism_update_backlight(dc);
1756 }
1757
1758 static void tegra_dc_one_shot_worker(struct work_struct *work)
1759 {
1760         struct tegra_dc *dc = container_of(
1761                 to_delayed_work(work), struct tegra_dc, one_shot_work);
1762         mutex_lock(&dc->lock);
1763
1764         /* memory client has gone idle */
1765         tegra_dc_clear_bandwidth(dc);
1766
1767         if (dc->out_ops && dc->out_ops->idle) {
1768                 tegra_dc_io_start(dc);
1769                 dc->out_ops->idle(dc);
1770                 tegra_dc_io_end(dc);
1771         }
1772
1773         mutex_unlock(&dc->lock);
1774 }
1775
1776 /* return an arbitrarily large number if count overflow occurs.
1777  * make it a nice base-10 number to show up in stats output */
1778 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
1779 {
1780         unsigned count = tegra_dc_readl(dc, reg);
1781
1782         tegra_dc_writel(dc, 0, reg);
1783         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
1784 }
1785
1786 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
1787 {
1788         const u32 masks[] = {
1789                 WIN_A_UF_INT,
1790                 WIN_B_UF_INT,
1791                 WIN_C_UF_INT,
1792 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1793                 WIN_D_UF_INT,
1794                 HC_UF_INT,
1795                 WIN_T_UF_INT,
1796 #endif
1797         };
1798         int i;
1799
1800         dc->stats.underflows++;
1801         if (dc->underflow_mask & WIN_A_UF_INT)
1802                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
1803                         DC_WINBUF_AD_UFLOW_STATUS);
1804         if (dc->underflow_mask & WIN_B_UF_INT)
1805                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
1806                         DC_WINBUF_BD_UFLOW_STATUS);
1807         if (dc->underflow_mask & WIN_C_UF_INT)
1808                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
1809                         DC_WINBUF_CD_UFLOW_STATUS);
1810 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
1811         if (dc->underflow_mask & HC_UF_INT)
1812                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
1813                         DC_WINBUF_HD_UFLOW_STATUS);
1814         if (dc->underflow_mask & WIN_D_UF_INT)
1815                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
1816                         DC_WINBUF_DD_UFLOW_STATUS);
1817         if (dc->underflow_mask & WIN_T_UF_INT)
1818                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
1819                         DC_WINBUF_TD_UFLOW_STATUS);
1820 #endif
1821
1822         /* Check for any underflow reset conditions */
1823         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
1824                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
1825                         "underflow stats unsupported"))
1826                         break; /* bail if the table above is missing entries */
1827                 if (!masks[i])
1828                         continue; /* skip empty entries */
1829
1830                 if (dc->underflow_mask & masks[i]) {
1831                         dc->windows[i].underflows++;
1832
1833 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
1834                         if (i < 3 && dc->windows[i].underflows > 4) {
1835                                 schedule_work(&dc->reset_work);
1836                                 /* reset counter */
1837                                 dc->windows[i].underflows = 0;
1838                                 trace_display_reset(dc);
1839                         }
1840 #endif
1841 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
1842                         if (i < 3 && dc->windows[i].underflows > 4) {
1843                                 trace_display_reset(dc);
1844                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
1845                                                 DC_DISP_DISP_MISC_CONTROL);
1846                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1847                                                 DC_CMD_STATE_CONTROL);
1848
1849                                 tegra_dc_writel(dc, 0,
1850                                                 DC_DISP_DISP_MISC_CONTROL);
1851                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
1852                                                 DC_CMD_STATE_CONTROL);
1853                         }
1854 #endif
1855                 } else {
1856                         dc->windows[i].underflows = 0;
1857                 }
1858         }
1859
1860         /* Clear the underflow mask now that we've checked it. */
1861         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
1862         dc->underflow_mask = 0;
1863         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
1864         trace_underflow(dc);
1865 }
1866
1867 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1868 static void tegra_dc_vpulse2(struct work_struct *work)
1869 {
1870         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
1871         bool nvsd_updated = false;
1872
1873         mutex_lock(&dc->lock);
1874
1875         if (!dc->enabled) {
1876                 mutex_unlock(&dc->lock);
1877                 return;
1878         }
1879
1880         tegra_dc_get(dc);
1881
1882         /* Clear the V_PULSE2_FLIP if no update */
1883         if (!tegra_dc_windows_are_dirty(dc))
1884                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
1885
1886         /* Update the SD brightness */
1887         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
1888                 nvsd_updated = nvsd_update_brightness(dc);
1889                 if (nvsd_updated) {
1890                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1891                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
1892                 } else {
1893                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
1894                 }
1895         }
1896
1897         /* Mask vpulse2 interrupt if ref-count is zero. */
1898         if (!dc->vpulse2_ref_count)
1899                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
1900
1901         tegra_dc_put(dc);
1902         mutex_unlock(&dc->lock);
1903
1904         /* Do the actual brightness update outside of the mutex dc->lock */
1905         if (nvsd_updated)
1906                 tegra_dc_prism_update_backlight(dc);
1907 }
1908 #endif
1909
1910 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
1911 {
1912         int ret;
1913
1914         mutex_lock(&dc->lock);
1915         ret = _tegra_dc_config_frame_end_intr(dc, enable);
1916         mutex_unlock(&dc->lock);
1917
1918         return ret;
1919 }
1920
1921 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
1922                 ktime_t timestamp)
1923 {
1924         /* pending user vblank, so wakeup */
1925         if (status & (V_BLANK_INT | MSF_INT)) {
1926                 if (dc->out->user_needs_vblank) {
1927                         dc->out->user_needs_vblank = false;
1928                         complete(&dc->out->user_vblank_comp);
1929                 }
1930 #ifdef CONFIG_ADF_TEGRA
1931                 tegra_adf_process_vblank(dc->adf, timestamp);
1932 #endif
1933         }
1934
1935         if (status & V_BLANK_INT) {
1936                 /* Sync up windows. */
1937                 tegra_dc_trigger_windows(dc);
1938
1939                 /* Schedule any additional bottom-half vblank actvities. */
1940                 queue_work(system_freezable_wq, &dc->vblank_work);
1941         }
1942
1943         if (status & FRAME_END_INT) {
1944                 /* Mark the frame_end as complete. */
1945                 dc->crc_pending = false;
1946                 if (!completion_done(&dc->frame_end_complete))
1947                         complete(&dc->frame_end_complete);
1948                 if (!completion_done(&dc->crc_complete))
1949                         complete(&dc->crc_complete);
1950
1951                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
1952                         tegra_dc_put(dc);
1953         }
1954
1955 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1956         if (status & V_PULSE2_INT)
1957                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1958 #endif
1959 }
1960
1961 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
1962                 ktime_t timestamp)
1963 {
1964         /* Schedule any additional bottom-half vblank actvities. */
1965         if (status & V_BLANK_INT)
1966                 queue_work(system_freezable_wq, &dc->vblank_work);
1967
1968 #ifdef CONFIG_ADF_TEGRA
1969         if (status & (V_BLANK_INT | MSF_INT))
1970                 tegra_adf_process_vblank(dc->adf, timestamp);
1971 #endif
1972
1973         if (status & FRAME_END_INT) {
1974                 struct timespec tm = CURRENT_TIME;
1975                 dc->frame_end_timestamp = timespec_to_ns(&tm);
1976                 wake_up(&dc->timestamp_wq);
1977
1978                 /* Mark the frame_end as complete. */
1979                 if (!completion_done(&dc->frame_end_complete))
1980                         complete(&dc->frame_end_complete);
1981                 if (!completion_done(&dc->crc_complete))
1982                         complete(&dc->crc_complete);
1983
1984                 tegra_dc_trigger_windows(dc);
1985         }
1986
1987 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
1988         if (status & V_PULSE2_INT)
1989                 queue_work(system_freezable_wq, &dc->vpulse2_work);
1990 #endif
1991 }
1992
1993 /* XXX: Not sure if we limit look ahead to 1 frame */
1994 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
1995 {
1996         BUG_ON(!dc->frametime_ns);
1997         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
1998 }
1999
2000 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
2001 {
2002         BUG_ON(!dc->frametime_ns);
2003         return (((new_ts - old_ts) > dc->frametime_ns)
2004                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
2005                         != div_s64((old_ts - dc->frame_end_timestamp),
2006                                 dc->frametime_ns)));
2007 }
2008
2009 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2010 {
2011         ktime_t timestamp = ktime_get();
2012         struct tegra_dc *dc = ptr;
2013         unsigned long status;
2014         unsigned long underflow_mask;
2015         u32 val;
2016         int need_disable = 0;
2017
2018         if (tegra_platform_is_fpga())
2019                 return IRQ_NONE;
2020
2021         mutex_lock(&dc->lock);
2022         if (!tegra_dc_is_powered(dc)) {
2023                 mutex_unlock(&dc->lock);
2024                 return IRQ_HANDLED;
2025         }
2026
2027         tegra_dc_get(dc);
2028
2029         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
2030                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
2031                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2032                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2033                 tegra_dc_put(dc);
2034                 mutex_unlock(&dc->lock);
2035                 return IRQ_HANDLED;
2036         }
2037
2038         /* clear all status flags except underflow, save those for the worker */
2039         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2040         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
2041         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2042         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
2043
2044         /*
2045          * Overlays can get thier internal state corrupted during and underflow
2046          * condition.  The only way to fix this state is to reset the DC.
2047          * if we get 4 consecutive frames with underflows, assume we're
2048          * hosed and reset.
2049          */
2050         underflow_mask = status & ALL_UF_INT();
2051
2052         /* Check underflow */
2053         if (underflow_mask) {
2054                 dc->underflow_mask |= underflow_mask;
2055                 schedule_delayed_work(&dc->underflow_work,
2056                         msecs_to_jiffies(1));
2057         }
2058
2059         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2060                 tegra_dc_one_shot_irq(dc, status, timestamp);
2061         else
2062                 tegra_dc_continuous_irq(dc, status, timestamp);
2063
2064         if (dc->nvsr)
2065                 tegra_dc_nvsr_irq(dc->nvsr, status);
2066
2067         /* update video mode if it has changed since the last frame */
2068         if (status & (FRAME_END_INT | V_BLANK_INT))
2069                 if (tegra_dc_update_mode(dc))
2070                         need_disable = 1; /* force display off on error */
2071
2072         if (status & FRAME_END_INT)
2073                 if (dc->disp_active_dirty) {
2074                         tegra_dc_writel(dc, dc->mode.h_active |
2075                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
2076                         tegra_dc_writel(dc,
2077                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2078
2079                         dc->disp_active_dirty = false;
2080                 }
2081
2082         tegra_dc_put(dc);
2083         mutex_unlock(&dc->lock);
2084
2085         if (need_disable)
2086                 tegra_dc_disable_nosync(dc);
2087         return IRQ_HANDLED;
2088 }
2089
2090 void tegra_dc_set_color_control(struct tegra_dc *dc)
2091 {
2092         u32 color_control;
2093
2094         switch (dc->out->depth) {
2095         case 3:
2096                 color_control = BASE_COLOR_SIZE111;
2097                 break;
2098
2099         case 6:
2100                 color_control = BASE_COLOR_SIZE222;
2101                 break;
2102
2103         case 8:
2104                 color_control = BASE_COLOR_SIZE332;
2105                 break;
2106
2107         case 9:
2108                 color_control = BASE_COLOR_SIZE333;
2109                 break;
2110
2111         case 12:
2112                 color_control = BASE_COLOR_SIZE444;
2113                 break;
2114
2115         case 15:
2116                 color_control = BASE_COLOR_SIZE555;
2117                 break;
2118
2119         case 16:
2120                 color_control = BASE_COLOR_SIZE565;
2121                 break;
2122
2123         case 18:
2124                 color_control = BASE_COLOR_SIZE666;
2125                 break;
2126
2127         default:
2128                 color_control = BASE_COLOR_SIZE888;
2129                 break;
2130         }
2131
2132         switch (dc->out->dither) {
2133         case TEGRA_DC_UNDEFINED_DITHER:
2134         case TEGRA_DC_DISABLE_DITHER:
2135                 color_control |= DITHER_CONTROL_DISABLE;
2136                 break;
2137         case TEGRA_DC_ORDERED_DITHER:
2138                 color_control |= DITHER_CONTROL_ORDERED;
2139                 break;
2140 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
2141         case TEGRA_DC_TEMPORAL_DITHER:
2142                 color_control |= DITHER_CONTROL_TEMPORAL;
2143                 break;
2144 #else
2145         case TEGRA_DC_ERRDIFF_DITHER:
2146                 /* The line buffer for error-diffusion dither is limited
2147                  * to 1280 pixels per line. This limits the maximum
2148                  * horizontal active area size to 1280 pixels when error
2149                  * diffusion is enabled.
2150                  */
2151                 BUG_ON(dc->mode.h_active > 1280);
2152                 color_control |= DITHER_CONTROL_ERRDIFF;
2153                 break;
2154 #endif
2155         default:
2156                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
2157         }
2158
2159 #ifdef CONFIG_TEGRA_DC_CMU
2160         if (dc->cmu_enabled)
2161                 color_control |= CMU_ENABLE;
2162 #endif
2163
2164         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2165 }
2166
2167 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2168 {
2169         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
2170                 return dc->win_syncpt[idx];
2171         BUG();
2172 }
2173
2174 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
2175 {
2176 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2177         u32 start, end;
2178         unsigned long val;
2179
2180         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
2181         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
2182
2183         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
2184                 dc->mode.v_back_porch + dc->mode.v_active;
2185         end = start + 1;
2186         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
2187         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
2188
2189         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2190         val |= V_PULSE2_INT;
2191         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
2192
2193         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2194         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2195 #endif
2196 }
2197
2198 static int tegra_dc_init(struct tegra_dc *dc)
2199 {
2200         int i;
2201         int int_enable;
2202         u32 val;
2203
2204         tegra_dc_io_start(dc);
2205         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2206         if (dc->ndev->id == 0) {
2207                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2208                                       TEGRA_MC_PRIO_MED);
2209                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2210                                       TEGRA_MC_PRIO_MED);
2211                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2212                                       TEGRA_MC_PRIO_MED);
2213 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2214                 /* only present on Tegra2 and 3 */
2215                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2216                                       TEGRA_MC_PRIO_MED);
2217 #endif
2218                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2219                                       TEGRA_MC_PRIO_HIGH);
2220         } else if (dc->ndev->id == 1) {
2221                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2222                                       TEGRA_MC_PRIO_MED);
2223                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2224                                       TEGRA_MC_PRIO_MED);
2225                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2226                                       TEGRA_MC_PRIO_MED);
2227 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2228                 /* only present on Tegra2 and 3 */
2229                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2230                                       TEGRA_MC_PRIO_MED);
2231 #endif
2232                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2233                                       TEGRA_MC_PRIO_HIGH);
2234         }
2235         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2236                         DC_CMD_CONT_SYNCPT_VSYNC);
2237
2238         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2239 #if defined(CONFIG_ARCH_TEGRA_14x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
2240         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2241                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
2242                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2243                 DC_CMD_INT_POLARITY);
2244 #else
2245         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2246                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2247                 DC_CMD_INT_POLARITY);
2248 #endif
2249         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2250         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2251 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2252         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2253 #endif
2254         /* enable interrupts for vblank, frame_end and underflows */
2255         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
2256         /* for panels with one-shot mode enable tearing effect interrupt */
2257         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2258                 int_enable |= MSF_INT;
2259
2260         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
2261         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
2262         tegra_dc_init_vpulse2_int(dc);
2263
2264 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
2265         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2266 #else
2267         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
2268 #endif
2269
2270 #ifdef CONFIG_TEGRA_DC_CMU
2271         _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2272 #endif
2273         tegra_dc_set_color_control(dc);
2274         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2275                 struct tegra_dc_win *win = &dc->windows[i];
2276                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2277                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2278                 tegra_dc_set_csc(dc, &win->csc);
2279                 tegra_dc_set_lut(dc, win);
2280                 tegra_dc_set_scaling_filter(dc);
2281         }
2282
2283 #ifdef CONFIG_TEGRA_DC_WIN_H
2284         /* Window H is set to window mode by default for t14x. */
2285         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
2286                         DC_DISP_BLEND_CURSOR_CONTROL);
2287 #endif
2288
2289         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2290                 u32 syncpt = get_syncpt(dc, i);
2291
2292                 /* refuse to operate on invalid syncpts */
2293                 if (WARN_ON(syncpt == NVSYNCPT_INVALID))
2294                         continue;
2295
2296                 dc->syncpt[i].id = syncpt;
2297
2298                 if (!nvhost_syncpt_read_ext_check(dc->ndev, syncpt, &val))
2299                         dc->syncpt[i].min = dc->syncpt[i].max = val;
2300         }
2301
2302         dc->crc_pending = false;
2303
2304         trace_display_mode(dc, &dc->mode);
2305
2306         if (dc->mode.pclk) {
2307                 if (!dc->initialized) {
2308                         if (tegra_dc_program_mode(dc, &dc->mode)) {
2309                                 tegra_dc_io_end(dc);
2310                                 dev_warn(&dc->ndev->dev,
2311                                         "%s: tegra_dc_program_mode failed\n",
2312                                         __func__);
2313                                 return -EINVAL;
2314                         }
2315                 } else {
2316                         dev_info(&dc->ndev->dev, "DC initialized, "
2317                                         "skipping tegra_dc_program_mode.\n");
2318                 }
2319         }
2320
2321         /* Initialize SD AFTER the modeset.
2322            nvsd_init handles the sd_settings = NULL case. */
2323         nvsd_init(dc, dc->out->sd_settings);
2324
2325         tegra_dc_io_end(dc);
2326
2327         return 0;
2328 }
2329
2330 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2331 {
2332         int failed_init = 0;
2333         int i;
2334
2335         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2336                 return false;
2337
2338         tegra_dc_unpowergate_locked(dc);
2339
2340         if (dc->out->enable)
2341                 dc->out->enable(&dc->ndev->dev);
2342
2343         tegra_dc_setup_clk(dc, dc->clk);
2344
2345         /* dc clk always on for continuous mode */
2346         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2347                 tegra_dc_clk_enable(dc);
2348         else
2349                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
2350
2351         tegra_dc_get(dc);
2352
2353         tegra_dc_power_on(dc);
2354
2355         /* do not accept interrupts during initialization */
2356         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2357
2358         enable_dc_irq(dc);
2359
2360         failed_init = tegra_dc_init(dc);
2361         if (failed_init) {
2362                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2363                 disable_irq_nosync(dc->irq);
2364                 tegra_dc_clear_bandwidth(dc);
2365                 if (dc->out && dc->out->disable)
2366                         dc->out->disable();
2367                 tegra_dc_put(dc);
2368                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2369                         tegra_dc_clk_disable(dc);
2370                 else
2371                         tegra_dvfs_set_rate(dc->clk, 0);
2372                 dev_warn(&dc->ndev->dev,
2373                         "%s: tegra_dc_init failed\n", __func__);
2374                 return false;
2375         }
2376
2377         tegra_dpaux_pad_power(dc, false);
2378
2379         if (dc->out_ops && dc->out_ops->enable)
2380                 dc->out_ops->enable(dc);
2381
2382         /* force a full blending update */
2383         for (i = 0; i < DC_N_WINDOWS; i++)
2384                 dc->blend.z[i] = -1;
2385
2386         tegra_dc_ext_enable(dc->ext);
2387
2388         /* initialize cursor to defaults, as driver depends on HW state */
2389         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
2390         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
2391 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2392         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
2393         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
2394 #endif
2395         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
2396         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
2397         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
2398         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
2399         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
2400
2401         trace_display_enable(dc);
2402
2403         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2404
2405         if (dc->out->postpoweron)
2406                 dc->out->postpoweron(&dc->ndev->dev);
2407
2408         if (dc->out_ops && dc->out_ops->postpoweron)
2409                 dc->out_ops->postpoweron(dc);
2410
2411         tegra_log_resume_time();
2412         /*
2413          * We will need to reinitialize the display the next time panel
2414          * is enabled.
2415          */
2416         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2417
2418         tegra_dc_put(dc);
2419
2420         return true;
2421 }
2422
2423 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2424 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2425 {
2426         bool ret = true;
2427
2428         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2429                 return false;
2430
2431         if (dc->out->enable)
2432                 dc->out->enable(&dc->ndev->dev);
2433
2434         tegra_dc_setup_clk(dc, dc->clk);
2435         tegra_dc_clk_enable(dc);
2436
2437         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2438                 mutex_lock(&tegra_dcs[1]->lock);
2439                 disable_irq_nosync(tegra_dcs[1]->irq);
2440         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2441                 mutex_lock(&tegra_dcs[0]->lock);
2442                 disable_irq_nosync(tegra_dcs[0]->irq);
2443         }
2444
2445         msleep(5);
2446         tegra_periph_reset_assert(dc->clk);
2447         msleep(2);
2448         if (tegra_platform_is_silicon()) {
2449                 tegra_periph_reset_deassert(dc->clk);
2450                 msleep(1);
2451         }
2452
2453         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2454                 enable_dc_irq(tegra_dcs[1]);
2455                 mutex_unlock(&tegra_dcs[1]->lock);
2456         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2457                 enable_dc_irq(tegra_dcs[0]);
2458                 mutex_unlock(&tegra_dcs[0]->lock);
2459         }
2460
2461         enable_dc_irq(dc);
2462
2463         if (tegra_dc_init(dc)) {
2464                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2465                 ret = false;
2466         }
2467
2468         if (dc->out_ops && dc->out_ops->enable)
2469                 dc->out_ops->enable(dc);
2470
2471         if (dc->out->postpoweron)
2472                 dc->out->postpoweron(&dc->ndev->dev);
2473
2474         /* force a full blending update */
2475         dc->blend.z[0] = -1;
2476
2477         tegra_dc_ext_enable(dc->ext);
2478
2479         if (!ret) {
2480                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2481                 _tegra_dc_controller_disable(dc);
2482         }
2483
2484         trace_display_reset(dc);
2485         return ret;
2486 }
2487 #endif
2488
2489 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2490 {
2491         if (dc->mode.pclk == 0) {
2492                 switch (dc->out->type) {
2493                 case TEGRA_DC_OUT_HDMI:
2494                 /* If DC is enable called, and HDMI is connected,
2495                  * but DC is not initialized by bootloader and no
2496                  * mode is set up, then set a fallback mode.
2497                  */
2498                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
2499                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2500                 } else
2501                         return false;
2502
2503                 break;
2504
2505                 case TEGRA_DC_OUT_DP:
2506                 case TEGRA_DC_OUT_NVSR_DP:
2507                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2508
2509                 /* Do nothing for other outputs for now */
2510                 case TEGRA_DC_OUT_RGB:
2511
2512                 case TEGRA_DC_OUT_DSI:
2513
2514                 default:
2515                         return false;
2516                 }
2517         }
2518
2519         return false;
2520 }
2521
2522 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2523 {
2524         return _tegra_dc_set_default_videomode(dc);
2525 }
2526
2527 static bool _tegra_dc_enable(struct tegra_dc *dc)
2528 {
2529         if (dc->mode.pclk == 0)
2530                 return false;
2531
2532         if (!dc->out)
2533                 return false;
2534
2535         if (dc->enabled)
2536                 return true;
2537
2538         pm_runtime_get_sync(&dc->ndev->dev);
2539
2540         if (dc->out->type == TEGRA_DC_OUT_HDMI && !tegra_dc_hpd(dc))
2541                 return false;
2542
2543         if (!_tegra_dc_controller_enable(dc)) {
2544                 pm_runtime_put_sync(&dc->ndev->dev);
2545                 return false;
2546         }
2547
2548         return true;
2549 }
2550
2551 void tegra_dc_enable(struct tegra_dc *dc)
2552 {
2553         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2554                 return;
2555
2556         mutex_lock(&dc->lock);
2557
2558         if (!dc->enabled)
2559                 dc->enabled = _tegra_dc_enable(dc);
2560
2561         mutex_unlock(&dc->lock);
2562         trace_display_mode(dc, &dc->mode);
2563 }
2564
2565 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
2566 {
2567         struct tegra_dc_win *w = &dc->windows[win];
2568
2569         /* reset window bandwidth */
2570         w->bandwidth = 0;
2571         w->new_bandwidth = 0;
2572
2573         /* disable windows */
2574         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2575
2576         /* refuse to operate on invalid syncpts */
2577         if (WARN_ON(dc->syncpt[win].id == NVSYNCPT_INVALID))
2578                 return;
2579
2580         /* flush any pending syncpt waits */
2581         dc->syncpt[win].max += 1;
2582         while (dc->syncpt[win].min < dc->syncpt[win].max) {
2583                 trace_display_syncpt_flush(dc, dc->syncpt[win].id,
2584                         dc->syncpt[win].min, dc->syncpt[win].max);
2585                 dc->syncpt[win].min++;
2586                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[win].id);
2587         }
2588 }
2589
2590 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2591 {
2592         unsigned i;
2593
2594         tegra_dc_get(dc);
2595
2596         if (dc->out && dc->out->prepoweroff)
2597                 dc->out->prepoweroff();
2598
2599         if (dc->out_ops && dc->out_ops->disable)
2600                 dc->out_ops->disable(dc);
2601
2602         if (tegra_powergate_is_powered(dc->powergate_id))
2603                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2604
2605         disable_irq_nosync(dc->irq);
2606
2607         tegra_dc_clear_bandwidth(dc);
2608
2609         if (dc->out && dc->out->disable)
2610                 dc->out->disable();
2611
2612         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2613                 tegra_dc_disable_window(dc, i);
2614         }
2615         trace_display_disable(dc);
2616
2617         if (dc->out_ops && dc->out_ops->postpoweroff)
2618                 dc->out_ops->postpoweroff(dc);
2619
2620         tegra_dc_put(dc);
2621
2622         /* disable always on dc clk in continuous mode */
2623         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2624                 tegra_dc_clk_disable(dc);
2625         else
2626                 tegra_dvfs_set_rate(dc->clk, 0);
2627 }
2628
2629 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
2630 {
2631 #if 0 /* underflow interrupt is already enabled by dc reset worker */
2632         u32 val;
2633         if (dc->enabled)  {
2634                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2635                 if (enable)
2636                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2637                 else
2638                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
2639                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
2640         }
2641 #endif
2642 }
2643
2644 bool tegra_dc_stats_get(struct tegra_dc *dc)
2645 {
2646 #if 0 /* right now it is always enabled */
2647         u32 val;
2648         bool res;
2649
2650         if (dc->enabled)  {
2651                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2652                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
2653         } else {
2654                 res = false;
2655         }
2656
2657         return res;
2658 #endif
2659         return true;
2660 }
2661
2662 /* blank selected windows by disabling them */
2663 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
2664 {
2665         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
2666         unsigned i;
2667         unsigned long int blank_windows;
2668         int nr_win = 0;
2669
2670         blank_windows = windows & dc->valid_windows;
2671
2672         if (!blank_windows)
2673                 return;
2674
2675         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
2676                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
2677                 if (!dcwins[nr_win])
2678                         continue;
2679                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2680         }
2681
2682         tegra_dc_update_windows(dcwins, nr_win, NULL);
2683         tegra_dc_sync_windows(dcwins, nr_win);
2684         tegra_dc_program_bandwidth(dc, true);
2685 }
2686
2687 int tegra_dc_restore(struct tegra_dc *dc)
2688 {
2689         return tegra_dc_ext_restore(dc->ext);
2690 }
2691
2692 static void _tegra_dc_disable(struct tegra_dc *dc)
2693 {
2694 #ifdef CONFIG_TEGRA_DC_CMU
2695         /* power down resets the registers, setting to true
2696          * causes CMU to be restored in tegra_dc_init(). */
2697         dc->cmu_dirty = true;
2698 #endif
2699
2700         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
2701                 mutex_lock(&dc->one_shot_lock);
2702                 cancel_delayed_work_sync(&dc->one_shot_work);
2703         }
2704
2705         tegra_dc_io_start(dc);
2706         _tegra_dc_controller_disable(dc);
2707         tegra_dc_io_end(dc);
2708
2709         tegra_dc_powergate_locked(dc);
2710
2711         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2712                 mutex_unlock(&dc->one_shot_lock);
2713         pm_runtime_put(&dc->ndev->dev);
2714
2715         tegra_log_suspend_time();
2716 }
2717
2718 static void tegra_dc_disable_nosync(struct tegra_dc *dc)
2719 {
2720         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2721                 return;
2722
2723         tegra_dc_ext_disable(dc->ext);
2724
2725         /* it's important that new underflow work isn't scheduled before the
2726          * lock is acquired. */
2727         cancel_delayed_work_sync(&dc->underflow_work);
2728
2729         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2730                 mutex_lock(&dc->one_shot_lp_lock);
2731         mutex_lock(&dc->lock);
2732
2733         if (dc->enabled) {
2734                 dc->enabled = false;
2735                 dc->blanked = false;
2736
2737                 if (!dc->suspended)
2738                         _tegra_dc_disable(dc);
2739         }
2740
2741 #ifdef CONFIG_SWITCH
2742         switch_set_state(&dc->modeset_switch, 0);
2743 #endif
2744         mutex_unlock(&dc->lock);
2745         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2746                 mutex_unlock(&dc->one_shot_lp_lock);
2747         trace_display_mode(dc, &dc->mode);
2748
2749         /* disable pending clks due to uncompleted frames */
2750         while (tegra_is_clk_enabled(dc->clk))
2751                 tegra_dc_put(dc);
2752 }
2753
2754 void tegra_dc_disable(struct tegra_dc *dc)
2755 {
2756         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2757                 return;
2758
2759         tegra_dc_ext_disable(dc->ext);
2760
2761         /* it's important that new underflow work isn't scheduled before the
2762          * lock is acquired. */
2763         cancel_delayed_work_sync(&dc->underflow_work);
2764
2765         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2766                 mutex_lock(&dc->one_shot_lp_lock);
2767         mutex_lock(&dc->lock);
2768
2769         if (dc->enabled) {
2770                 dc->enabled = false;
2771                 dc->blanked = false;
2772
2773                 if (!dc->suspended)
2774                         _tegra_dc_disable(dc);
2775         }
2776
2777 #ifdef CONFIG_SWITCH
2778         switch_set_state(&dc->modeset_switch, 0);
2779 #endif
2780         mutex_unlock(&dc->lock);
2781         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2782                 mutex_unlock(&dc->one_shot_lp_lock);
2783         synchronize_irq(dc->irq);
2784         trace_display_mode(dc, &dc->mode);
2785
2786         /* disable pending clks due to uncompleted frames */
2787         while (tegra_is_clk_enabled(dc->clk))
2788                 tegra_dc_put(dc);
2789 }
2790
2791 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2792 static void tegra_dc_reset_worker(struct work_struct *work)
2793 {
2794         struct tegra_dc *dc =
2795                 container_of(work, struct tegra_dc, reset_work);
2796
2797         unsigned long val = 0;
2798
2799         mutex_lock(&shared_lock);
2800
2801         dev_warn(&dc->ndev->dev,
2802                 "overlay stuck in underflow state.  resetting.\n");
2803
2804         tegra_dc_ext_disable(dc->ext);
2805
2806         mutex_lock(&dc->lock);
2807
2808         if (dc->enabled == false)
2809                 goto unlock;
2810
2811         dc->enabled = false;
2812
2813         /*
2814          * off host read bus
2815          */
2816         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2817         val &= ~(0x00000100);
2818         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2819
2820         /*
2821          * set DC to STOP mode
2822          */
2823         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
2824
2825         msleep(10);
2826
2827         _tegra_dc_controller_disable(dc);
2828
2829         /* _tegra_dc_controller_reset_enable deasserts reset */
2830         _tegra_dc_controller_reset_enable(dc);
2831
2832         dc->enabled = true;
2833
2834         /* reopen host read bus */
2835         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
2836         val &= ~(0x00000100);
2837         val |= 0x100;
2838         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
2839
2840 unlock:
2841         mutex_unlock(&dc->lock);
2842         mutex_unlock(&shared_lock);
2843         trace_display_reset(dc);
2844 }
2845 #endif
2846
2847 static void tegra_dc_underflow_worker(struct work_struct *work)
2848 {
2849         struct tegra_dc *dc = container_of(
2850                 to_delayed_work(work), struct tegra_dc, underflow_work);
2851
2852         mutex_lock(&dc->lock);
2853         tegra_dc_get(dc);
2854
2855         if (dc->enabled) {
2856                 tegra_dc_underflow_handler(dc);
2857         }
2858         tegra_dc_put(dc);
2859         mutex_unlock(&dc->lock);
2860 }
2861
2862 static void (*flip_callback)(void);
2863 static spinlock_t flip_callback_lock;
2864 static bool init_tegra_dc_flip_callback_called;
2865
2866 static int __init init_tegra_dc_flip_callback(void)
2867 {
2868         spin_lock_init(&flip_callback_lock);
2869         init_tegra_dc_flip_callback_called = true;
2870         return 0;
2871 }
2872
2873 pure_initcall(init_tegra_dc_flip_callback);
2874
2875 int tegra_dc_set_flip_callback(void (*callback)(void))
2876 {
2877         WARN_ON(!init_tegra_dc_flip_callback_called);
2878
2879         spin_lock(&flip_callback_lock);
2880         flip_callback = callback;
2881         spin_unlock(&flip_callback_lock);
2882
2883         return 0;
2884 }
2885 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
2886
2887 int tegra_dc_unset_flip_callback()
2888 {
2889         spin_lock(&flip_callback_lock);
2890         flip_callback = NULL;
2891         spin_unlock(&flip_callback_lock);
2892
2893         return 0;
2894 }
2895 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
2896
2897 void tegra_dc_call_flip_callback()
2898 {
2899         spin_lock(&flip_callback_lock);
2900         if (flip_callback)
2901                 flip_callback();
2902         spin_unlock(&flip_callback_lock);
2903 }
2904 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
2905
2906 #ifdef CONFIG_SWITCH
2907 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
2908 {
2909         struct tegra_dc *dc =
2910                 container_of(sdev, struct tegra_dc, modeset_switch);
2911
2912         if (!sdev->state)
2913                 return sprintf(buf, "offline\n");
2914
2915         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
2916 }
2917 #endif
2918
2919 static int tegra_dc_probe(struct platform_device *ndev)
2920 {
2921         struct tegra_dc *dc;
2922         struct tegra_dc_mode *mode;
2923         struct tegra_dc_platform_data *dt_pdata = NULL;
2924         struct clk *clk;
2925 #ifndef CONFIG_TEGRA_ISOMGR
2926         struct clk *emc_clk;
2927 #else
2928         int isomgr_client_id = -1;
2929 #endif
2930         struct device_node *np = ndev->dev.of_node;
2931         struct resource *res;
2932         struct resource dt_res;
2933         struct resource *base_res;
2934         struct resource *fb_mem = NULL;
2935         int ret = 0;
2936         void __iomem *base;
2937         int irq;
2938         int i;
2939
2940         if (!np && !ndev->dev.platform_data) {
2941                 dev_err(&ndev->dev, "no platform data\n");
2942                 return -ENOENT;
2943         }
2944
2945         /* Specify parameters for the maximum physical segment size. */
2946         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
2947
2948         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
2949         if (!dc) {
2950                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
2951                 return -ENOMEM;
2952         }
2953
2954         if (np) {
2955                 dt_pdata = of_dc_parse_platform_data(ndev);
2956                 if (dt_pdata == NULL)
2957                         goto err_free;
2958
2959 #ifdef CONFIG_OF
2960                 irq = of_irq_to_resource(np, 0, NULL);
2961                 if (!irq)
2962                         goto err_free;
2963 #endif
2964
2965                 ret = of_address_to_resource(np, 0, &dt_res);
2966                 if (ret)
2967                         goto err_free;
2968
2969                 if (dt_res.start == TEGRA_DISPLAY_BASE)
2970                         ndev->id = 0;
2971                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
2972                         ndev->id = 1;
2973                 else
2974                         goto err_free;
2975
2976                 res = &dt_res;
2977         } else {
2978                 irq = platform_get_irq_byname(ndev, "irq");
2979                 if (irq <= 0) {
2980                         dev_err(&ndev->dev, "no irq\n");
2981                         ret = -ENOENT;
2982                         goto err_free;
2983                 }
2984
2985                 res = platform_get_resource_byname(ndev,
2986                         IORESOURCE_MEM, "regs");
2987                 if (!res) {
2988                         dev_err(&ndev->dev, "no mem resource\n");
2989                         ret = -ENOENT;
2990                         goto err_free;
2991                 }
2992         }
2993
2994         base_res = request_mem_region(res->start, resource_size(res),
2995                 ndev->name);
2996         if (!base_res) {
2997                 dev_err(&ndev->dev, "request_mem_region failed\n");
2998                 ret = -EBUSY;
2999                 goto err_free;
3000         }
3001
3002         base = ioremap(res->start, resource_size(res));
3003         if (!base) {
3004                 dev_err(&ndev->dev, "registers can't be mapped\n");
3005                 ret = -EBUSY;
3006                 goto err_release_resource_reg;
3007         }
3008
3009         for (i = 0; i < DC_N_WINDOWS; i++)
3010                 dc->win_syncpt[i] = NVSYNCPT_INVALID;
3011
3012         if (TEGRA_DISPLAY_BASE == res->start) {
3013                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
3014                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp0_a");
3015                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp0_b");
3016                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp0_c");
3017                 dc->valid_windows = 0x07;
3018 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
3019                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3020                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp0_h");
3021                 dc->valid_windows |= 0x18;
3022 #elif defined(CONFIG_ARCH_TEGRA_12x_SOC)
3023                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3024                 dc->valid_windows |= 0x08;
3025 #endif
3026                 dc->powergate_id = TEGRA_POWERGATE_DISA;
3027 #ifdef CONFIG_TEGRA_ISOMGR
3028                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
3029 #endif
3030         } else if (TEGRA_DISPLAY2_BASE == res->start) {
3031                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
3032                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp1_a");
3033                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp1_b");
3034                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp1_c");
3035                 dc->valid_windows = 0x07;
3036 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
3037                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp1_h");
3038                 dc->valid_windows |= 0x10;
3039 #endif
3040                 dc->powergate_id = TEGRA_POWERGATE_DISB;
3041 #ifdef CONFIG_TEGRA_ISOMGR
3042                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
3043 #endif
3044         } else {
3045                 dev_err(&ndev->dev,
3046                         "Unknown base address %llx: unable to assign syncpt\n",
3047                         (u64)res->start);
3048         }
3049
3050         if (np) {
3051                 struct resource of_fb_res;
3052                 if (ndev->id == 0)
3053                         tegra_get_fb_resource(&of_fb_res);
3054                 else /*ndev->id == 1*/
3055                         tegra_get_fb2_resource(&of_fb_res);
3056
3057                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
3058                 if (fb_mem == NULL) {
3059                         ret = -ENOMEM;
3060                         goto err_iounmap_reg;
3061                 }
3062                 fb_mem->name = "fbmem";
3063                 fb_mem->flags = IORESOURCE_MEM;
3064                 fb_mem->start = (resource_size_t)of_fb_res.start;
3065                 fb_mem->end = (resource_size_t)of_fb_res.end;
3066         } else {
3067                 fb_mem = platform_get_resource_byname(ndev,
3068                         IORESOURCE_MEM, "fbmem");
3069         }
3070
3071         clk = clk_get(&ndev->dev, NULL);
3072         if (IS_ERR_OR_NULL(clk)) {
3073                 dev_err(&ndev->dev, "can't get clock\n");
3074                 ret = -ENOENT;
3075                 goto err_iounmap_reg;
3076         }
3077
3078         dc->clk = clk;
3079         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
3080         /* Initialize one shot work delay, it will be assigned by dsi
3081          * according to refresh rate later. */
3082         dc->one_shot_delay_ms = 40;
3083
3084         dc->base_res = base_res;
3085         dc->base = base;
3086         dc->irq = irq;
3087         dc->ndev = ndev;
3088         dc->fb_mem = fb_mem;
3089
3090         if (!np)
3091                 dc->pdata = ndev->dev.platform_data;
3092         else
3093                 dc->pdata = dt_pdata;
3094
3095         dc->bw_kbps = 0;
3096
3097         mutex_init(&dc->lock);
3098         mutex_init(&dc->one_shot_lock);
3099         mutex_init(&dc->one_shot_lp_lock);
3100         init_completion(&dc->frame_end_complete);
3101         init_completion(&dc->crc_complete);
3102         init_waitqueue_head(&dc->wq);
3103         init_waitqueue_head(&dc->timestamp_wq);
3104 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3105         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3106 #endif
3107         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3108         dc->vblank_ref_count = 0;
3109 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3110         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
3111 #endif
3112         dc->vpulse2_ref_count = 0;
3113         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3114         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3115
3116         tegra_dc_init_lut_defaults(&dc->fb_lut);
3117
3118         dc->n_windows = DC_N_WINDOWS;
3119         for (i = 0; i < DC_N_WINDOWS; i++) {
3120                 struct tegra_dc_win *win = &dc->windows[i];
3121                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
3122                 if (!test_bit(i, &dc->valid_windows))
3123                         win->flags |= TEGRA_WIN_FLAG_INVALID;
3124                 win->idx = i;
3125                 win->dc = dc;
3126                 tmp_win->idx = i;
3127                 tmp_win->dc = dc;
3128                 tegra_dc_init_csc_defaults(&win->csc);
3129                 tegra_dc_init_lut_defaults(&win->lut);
3130         }
3131
3132         ret = tegra_dc_set(dc, ndev->id);
3133         if (ret < 0) {
3134                 dev_err(&ndev->dev, "can't add dc\n");
3135                 goto err_put_clk;
3136         }
3137
3138         platform_set_drvdata(ndev, dc);
3139
3140 #ifdef CONFIG_SWITCH
3141         dc->modeset_switch.name = dev_name(&ndev->dev);
3142         dc->modeset_switch.state = 0;
3143         dc->modeset_switch.print_state = switch_modeset_print_mode;
3144         ret = switch_dev_register(&dc->modeset_switch);
3145         if (ret < 0)
3146                 dev_err(&ndev->dev, "failed to register switch driver\n");
3147 #endif
3148
3149         tegra_dc_feature_register(dc);
3150
3151         if (dc->pdata->default_out) {
3152 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3153                 if (dc->pdata->default_out->hotplug_init)
3154                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
3155 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3156                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
3157                 if (ret < 0) {
3158                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
3159                         goto err_put_clk;
3160                 }
3161         } else {
3162                 dev_err(&ndev->dev,
3163                         "No default output specified.  Leaving output disabled.\n");
3164         }
3165         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
3166
3167 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3168         if (dc->out && dc->out->n_modes &&
3169             (dc->out->type == TEGRA_DC_OUT_HDMI)) {
3170                 struct fb_monspecs specs;
3171                 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
3172                 if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
3173                         struct tegra_dc_mode *dcmode = &dc->out->modes[0];
3174                         if (specs.modedb->pixclock >
3175                                         tegra_dc_get_out_max_pixclock(dc)) {
3176                                 dc->mode.pclk = 0;
3177                                 _tegra_dc_set_default_videomode(dc);
3178                         } else {
3179                                 dcmode->pclk          = specs.modedb->pixclock;
3180                                 dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
3181                                 dcmode->pclk         *= 1000;
3182                                 dcmode->h_ref_to_sync = 1;
3183                                 dcmode->v_ref_to_sync = 1;
3184                                 dcmode->h_sync_width  = specs.modedb->hsync_len;
3185                                 dcmode->v_sync_width  = specs.modedb->vsync_len;
3186                                 dcmode->h_back_porch  = specs.modedb->left_margin;
3187                                 dcmode->v_back_porch  = specs.modedb->upper_margin;
3188                                 dcmode->h_active      = specs.modedb->xres;
3189                                 dcmode->v_active      = specs.modedb->yres;
3190                                 dcmode->h_front_porch = specs.modedb->right_margin;
3191                                 dcmode->v_front_porch = specs.modedb->lower_margin;
3192                                 tegra_dc_set_mode(dc, dcmode);
3193                                 dc->pdata->fb->xres = dcmode->h_active;
3194                                 dc->pdata->fb->yres = dcmode->v_active;
3195                         }
3196                 }
3197         }
3198 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3199
3200 #ifndef CONFIG_TEGRA_ISOMGR
3201                 /*
3202                  * The emc is a shared clock, it will be set based on
3203                  * the requirements for each user on the bus.
3204                  */
3205                 emc_clk = clk_get(&ndev->dev, "emc");
3206                 if (IS_ERR_OR_NULL(emc_clk)) {
3207                         dev_err(&ndev->dev, "can't get emc clock\n");
3208                         ret = -ENOENT;
3209                         goto err_put_clk;
3210                 }
3211                 dc->emc_clk = emc_clk;
3212 #endif
3213
3214         dc->ext = tegra_dc_ext_register(ndev, dc);
3215         if (IS_ERR_OR_NULL(dc->ext)) {
3216                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3217                 dc->ext = NULL;
3218         }
3219
3220         /* interrupt handler must be registered before tegra_fb_register() */
3221         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
3222                         dev_name(&ndev->dev), dc)) {
3223                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3224                 ret = -EBUSY;
3225                 goto err_disable_dc;
3226         }
3227         disable_dc_irq(dc);
3228
3229         tegra_pd_add_device(&ndev->dev);
3230         pm_runtime_use_autosuspend(&ndev->dev);
3231         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
3232         pm_runtime_enable(&ndev->dev);
3233
3234 #ifdef CONFIG_TEGRA_DC_CMU
3235         /* if bootloader leaves this head enabled, then skip CMU programming. */
3236         dc->cmu_dirty = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) == 0;
3237         dc->cmu_enabled = dc->pdata->cmu_enable;
3238 #endif
3239
3240         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
3241                 /* WAR: BL is putting DC in bad state for EDP configuration */
3242                 if (dc->out->type == TEGRA_DC_OUT_DP ||
3243                         dc->out->type == TEGRA_DC_OUT_NVSR_DP) {
3244                         clk_prepare_enable(dc->clk);
3245                         tegra_periph_reset_assert(dc->clk);
3246                         udelay(10);
3247                         tegra_periph_reset_deassert(dc->clk);
3248                         udelay(10);
3249                         clk_disable_unprepare(dc->clk);
3250                 }
3251                 dc->enabled = _tegra_dc_enable(dc);
3252
3253 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3254                 /* BL or PG init will keep DISA unpowergated after booting.
3255                  * Adding an extra powergate to balance the refcount
3256                  * since _tegra_dc_enable() increases the refcount.
3257                  */
3258                 if (dc->powergate_id == TEGRA_POWERGATE_DISA)
3259                         tegra_dc_powergate_locked(dc);
3260 #endif
3261         }
3262
3263 #ifdef CONFIG_TEGRA_ISOMGR
3264         if (isomgr_client_id == -1) {
3265                 dc->isomgr_handle = NULL;
3266         } else {
3267                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
3268                         tegra_dc_calc_min_bandwidth(dc),
3269                         tegra_dc_bandwidth_renegotiate, dc);
3270                 if (IS_ERR(dc->isomgr_handle)) {
3271                         dev_err(&dc->ndev->dev,
3272                                 "could not register isomgr. err=%ld\n",
3273                                 PTR_ERR(dc->isomgr_handle));
3274                         ret = -ENOENT;
3275                         goto err_put_clk;
3276                 }
3277                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
3278                 /*
3279                  * Use maximum value so we can try to reserve as much as
3280                  * needed until we are told by isomgr to backoff.
3281                  */
3282                 dc->available_bw = UINT_MAX;
3283         }
3284 #endif
3285
3286         tegra_dc_create_debugfs(dc);
3287
3288         dev_info(&ndev->dev, "probed\n");
3289
3290         if (dc->pdata->fb) {
3291                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
3292                         unsigned long fmt;
3293                         tegra_dc_writel(dc,
3294                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3295                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3296
3297                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3298                         dc->pdata->fb->bits_per_pixel =
3299                                 tegra_dc_fmt_bpp(fmt);
3300                 }
3301
3302                 mode = tegra_dc_get_override_mode(dc);
3303                 if (mode) {
3304                         dc->pdata->fb->xres = mode->h_active;
3305                         dc->pdata->fb->yres = mode->v_active;
3306                 }
3307
3308 #ifdef CONFIG_ADF_TEGRA
3309                 tegra_dc_io_start(dc);
3310                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb);
3311                 tegra_dc_io_end(dc);
3312
3313                 if (IS_ERR(dc->adf)) {
3314                         tegra_dc_io_start(dc);
3315                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
3316                                         fb_mem);
3317                         tegra_dc_io_end(dc);
3318                         if (IS_ERR_OR_NULL(dc->fb)) {
3319                                 dc->fb = NULL;
3320                                 dev_err(&ndev->dev, "failed to register fb\n");
3321                                 goto err_remove_debugfs;
3322                         }
3323                 }
3324 #else
3325                 tegra_dc_io_start(dc);
3326                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3327                 tegra_dc_io_end(dc);
3328                 if (IS_ERR_OR_NULL(dc->fb)) {
3329                         dc->fb = NULL;
3330                         dev_err(&ndev->dev, "failed to register fb\n");
3331                         goto err_remove_debugfs;
3332                 }
3333 #endif
3334         }
3335
3336 #ifndef CONFIG_FRAMEBUFFER_CONSOLE
3337         if (dc->out && dc->out->hotplug_init)
3338                 dc->out->hotplug_init(&ndev->dev);
3339 #endif /* !CONFIG_FRAMEBUFFER_CONSOLE */
3340
3341         if (dc->out_ops) {
3342                 if (dc->out_ops->detect)
3343                         dc->connected = dc->out_ops->detect(dc);
3344                 else
3345                         dc->connected = true;
3346         }
3347         else
3348                 dc->connected = false;
3349
3350         /* Powergate display module when it's unconnected. */
3351         /* detect() function, if presetns, responsible for the powergate */
3352         if (!tegra_dc_get_connected(dc) &&
3353                         !(dc->out_ops && dc->out_ops->detect))
3354                 tegra_dc_powergate_locked(dc);
3355
3356         tegra_dc_create_sysfs(&dc->ndev->dev);
3357
3358         /*
3359          * Overriding the display mode only applies for modes set up during
3360          * boot. It should not apply for e.g. HDMI hotplug.
3361          */
3362         dc->initialized = false;
3363
3364         return 0;
3365
3366 err_remove_debugfs:
3367         tegra_dc_remove_debugfs(dc);
3368         free_irq(irq, dc);
3369 err_disable_dc:
3370         if (dc->ext) {
3371                 tegra_dc_ext_disable(dc->ext);
3372                 tegra_dc_ext_unregister(dc->ext);
3373         }
3374         mutex_lock(&dc->lock);
3375         if (dc->enabled)
3376                 _tegra_dc_disable(dc);
3377         dc->enabled = false;
3378         mutex_unlock(&dc->lock);
3379 #ifdef CONFIG_SWITCH
3380         switch_dev_unregister(&dc->modeset_switch);
3381 #endif
3382 #ifdef CONFIG_TEGRA_ISOMGR
3383         tegra_isomgr_unregister(dc->isomgr_handle);
3384 #else
3385         clk_put(emc_clk);
3386 #endif
3387 err_put_clk:
3388         clk_put(clk);
3389 err_iounmap_reg:
3390         iounmap(base);
3391         if (fb_mem) {
3392                 if (!np)
3393                         release_resource(fb_mem);
3394                 else
3395                         kfree(fb_mem);
3396         }
3397 err_release_resource_reg:
3398         release_resource(base_res);
3399 err_free:
3400         kfree(dc);
3401
3402         return ret;
3403 }
3404
3405 static int tegra_dc_remove(struct platform_device *ndev)
3406 {
3407         struct tegra_dc *dc = platform_get_drvdata(ndev);
3408         struct device_node *np = ndev->dev.of_node;
3409
3410         tegra_dc_remove_sysfs(&dc->ndev->dev);
3411         tegra_dc_remove_debugfs(dc);
3412
3413         if (dc->fb) {
3414                 tegra_fb_unregister(dc->fb);
3415                 if (dc->fb_mem) {
3416                         if (!np)
3417                                 release_resource(dc->fb_mem);
3418                         else
3419                                 kfree(dc->fb_mem);
3420                 }
3421         }
3422
3423 #ifdef CONFIG_ADF_TEGRA
3424         if (dc->adf)
3425                 tegra_adf_unregister(dc->adf);
3426 #endif
3427
3428         tegra_dc_ext_disable(dc->ext);
3429
3430         if (dc->ext)
3431                 tegra_dc_ext_unregister(dc->ext);
3432
3433         mutex_lock(&dc->lock);
3434         if (dc->enabled)
3435                 _tegra_dc_disable(dc);
3436         dc->enabled = false;
3437         mutex_unlock(&dc->lock);
3438         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3439
3440 #ifdef CONFIG_SWITCH
3441         switch_dev_unregister(&dc->modeset_switch);
3442 #endif
3443         free_irq(dc->irq, dc);
3444 #ifdef CONFIG_TEGRA_ISOMGR
3445         if (dc->isomgr_handle) {
3446                 tegra_isomgr_unregister(dc->isomgr_handle);
3447                 dc->isomgr_handle = NULL;
3448         }
3449 #else
3450         clk_put(dc->emc_clk);
3451 #endif
3452         clk_put(dc->clk);
3453         iounmap(dc->base);
3454         if (dc->fb_mem)
3455                 release_resource(dc->base_res);
3456         kfree(dc);
3457         tegra_dc_set(NULL, ndev->id);
3458
3459         return 0;
3460 }
3461
3462 #ifdef CONFIG_PM
3463 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
3464 {
3465         struct tegra_dc *dc = platform_get_drvdata(ndev);
3466         int ret = 0;
3467
3468         trace_display_suspend(dc);
3469         dev_info(&ndev->dev, "suspend\n");
3470
3471         tegra_dc_ext_disable(dc->ext);
3472
3473         tegra_dc_cursor_suspend(dc);
3474         mutex_lock(&dc->lock);
3475         ret = tegra_dc_io_start(dc);
3476
3477         if (dc->out_ops && dc->out_ops->suspend)
3478                 dc->out_ops->suspend(dc);
3479
3480         if (dc->enabled) {
3481                 _tegra_dc_disable(dc);
3482
3483                 dc->suspended = true;
3484         }
3485
3486         if (dc->out && dc->out->postsuspend) {
3487                 dc->out->postsuspend();
3488                 /* avoid resume event due to voltage falling on interfaces that
3489                  * support hotplug wake. And only do this if a panel is
3490                  * connected, if we are already disconnected, then no phantom
3491                  * hotplug can occur by disabling the voltage.
3492                  */
3493                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
3494                         && tegra_dc_get_connected(dc))
3495                         msleep(100);
3496         }
3497
3498         if (!ret)
3499                 tegra_dc_io_end(dc);
3500
3501 #ifdef CONFIG_TEGRA_DC_CMU
3502         /*
3503          * CMU settings are lost when the DC goes to sleep. User-space will
3504          * perform a blank ioctl upon resume which will call tegra_dc_init()
3505          * and apply CMU settings again, but only if the cached values are
3506          * different from those specified. Clearing the cache here ensures
3507          * that this will happen.
3508          *
3509          * It would be better to reapply the CMU settings in tegra_dc_resume(),
3510          * but color corruption sometimes happens if we do so and
3511          * tegra_dc_init() seems to be the only safe place for this.
3512          */
3513         memset(&dc->cmu, 0, sizeof(dc->cmu));
3514 #endif
3515
3516         mutex_unlock(&dc->lock);
3517         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3518
3519         return 0;
3520 }
3521
3522 static int tegra_dc_resume(struct platform_device *ndev)
3523 {
3524         struct tegra_dc *dc = platform_get_drvdata(ndev);
3525
3526         trace_display_resume(dc);
3527         dev_info(&ndev->dev, "resume\n");
3528
3529         mutex_lock(&dc->lock);
3530         dc->suspended = false;
3531
3532         /* To pan the fb on resume */
3533         tegra_fb_pan_display_reset(dc->fb);
3534
3535         if (dc->enabled) {
3536                 dc->enabled = false;
3537                 _tegra_dc_set_default_videomode(dc);
3538                 dc->enabled = _tegra_dc_enable(dc);
3539         }
3540
3541         if (dc->out && dc->out->hotplug_init)
3542                 dc->out->hotplug_init(&ndev->dev);
3543
3544         if (dc->out_ops && dc->out_ops->resume)
3545                 dc->out_ops->resume(dc);
3546
3547         mutex_unlock(&dc->lock);
3548         tegra_dc_cursor_resume(dc);
3549
3550         return 0;
3551 }
3552
3553 #endif /* CONFIG_PM */
3554
3555 static void tegra_dc_shutdown(struct platform_device *ndev)
3556 {
3557         struct tegra_dc *dc = platform_get_drvdata(ndev);
3558
3559         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3560                 return;
3561
3562         if (!dc->enabled)
3563                 return;
3564
3565         tegra_dc_disable(dc);
3566 }
3567
3568 extern int suspend_set(const char *val, struct kernel_param *kp)
3569 {
3570         if (!strcmp(val, "dump"))
3571                 dump_regs(tegra_dcs[0]);
3572 #ifdef CONFIG_PM
3573         else if (!strcmp(val, "suspend"))
3574                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3575         else if (!strcmp(val, "resume"))
3576                 tegra_dc_resume(tegra_dcs[0]->ndev);
3577 #endif
3578
3579         return 0;
3580 }
3581
3582 extern int suspend_get(char *buffer, struct kernel_param *kp)
3583 {
3584         return 0;
3585 }
3586
3587 int suspend;
3588
3589 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3590
3591
3592 #ifdef CONFIG_OF
3593 static struct of_device_id tegra_display_of_match[] = {
3594         {.compatible = "nvidia,tegra114-dc", },
3595         {.compatible = "nvidia,tegra124-dc", },
3596         { },
3597 };
3598 #endif
3599
3600 struct platform_driver tegra_dc_driver = {
3601         .driver = {
3602                 .name = "tegradc",
3603                 .owner = THIS_MODULE,
3604 #ifdef CONFIG_OF
3605                 .of_match_table =
3606                         of_match_ptr(tegra_display_of_match),
3607 #endif
3608         },
3609         .probe = tegra_dc_probe,
3610         .remove = tegra_dc_remove,
3611 #ifdef CONFIG_PM
3612         .suspend = tegra_dc_suspend,
3613         .resume = tegra_dc_resume,
3614 #endif
3615         .shutdown = tegra_dc_shutdown,
3616 };
3617
3618 #ifndef MODULE
3619 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
3620 {
3621         int i, params[11];
3622         char *p;
3623
3624         for (i = 0; i < ARRAY_SIZE(params); i++) {
3625                 if ((p = strsep(&options, ",")) != NULL) {
3626                         if (*p)
3627                                 params[i] = simple_strtoul(p, &p, 10);
3628                 } else
3629                         return -EINVAL;
3630         }
3631
3632         if ((mode->pclk = params[0]) == 0)
3633                 return -EINVAL;
3634
3635         mode->h_active      = params[1];
3636         mode->v_active      = params[2];
3637         mode->h_ref_to_sync = params[3];
3638         mode->v_ref_to_sync = params[4];
3639         mode->h_sync_width  = params[5];
3640         mode->v_sync_width  = params[6];
3641         mode->h_back_porch  = params[7];
3642         mode->v_back_porch  = params[8];
3643         mode->h_front_porch = params[9];
3644         mode->v_front_porch = params[10];
3645
3646         return 0;
3647 }
3648
3649 static int __init tegra_dc_mode_override(char *str)
3650 {
3651         char *p = str, *options;
3652
3653         if (!p || !*p)
3654                 return -EINVAL;
3655
3656         p = strstr(str, "hdmi:");
3657         if (p) {
3658                 p += 5;
3659                 options = strsep(&p, ";");
3660                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
3661                         return -EINVAL;
3662         }
3663
3664         p = strstr(str, "rgb:");
3665         if (p) {
3666                 p += 4;
3667                 options = strsep(&p, ";");
3668                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
3669                         return -EINVAL;
3670         }
3671
3672         p = strstr(str, "dsi:");
3673         if (p) {
3674                 p += 4;
3675                 options = strsep(&p, ";");
3676                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
3677                         return -EINVAL;
3678         }
3679
3680         return 0;
3681 }
3682
3683 __setup("disp_params=", tegra_dc_mode_override);
3684 #endif
3685
3686 static int __init tegra_dc_module_init(void)
3687 {
3688         int ret = tegra_dc_ext_module_init();
3689         if (ret)
3690                 return ret;
3691         return platform_driver_register(&tegra_dc_driver);
3692 }
3693
3694 static void __exit tegra_dc_module_exit(void)
3695 {
3696         platform_driver_unregister(&tegra_dc_driver);
3697         tegra_dc_ext_module_exit();
3698 }
3699
3700 module_exit(tegra_dc_module_exit);
3701 module_init(tegra_dc_module_init);