[DNI] video: tegra: dc: Fixes for seamless boot
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2015, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <linux/clk/tegra.h>
41 #include <video/tegrafb.h>
42 #include <drm/drm_fixed.h>
43 #ifdef CONFIG_SWITCH
44 #include <linux/switch.h>
45 #endif
46 #include <linux/of_irq.h>
47 #include <linux/of_address.h>
48 #include <linux/tegra_pm_domains.h>
49 #include <linux/uaccess.h>
50 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
51 #include <linux/ote_protocol.h>
52 #endif
53 #include <linux/tegra-timer.h>
54
55 #define CREATE_TRACE_POINTS
56 #include <trace/events/display.h>
57 EXPORT_TRACEPOINT_SYMBOL(display_writel);
58 EXPORT_TRACEPOINT_SYMBOL(display_readl);
59
60 #include <mach/dc.h>
61 #include <mach/fb.h>
62 #include <linux/nvhost.h>
63 #include <linux/nvhost_ioctl.h>
64
65 #include <linux/platform/tegra/latency_allowance.h>
66 #include <linux/platform/tegra/mc.h>
67 #include <soc/tegra/tegra_bpmp.h>
68
69 #include "dc_reg.h"
70 #include "dc_config.h"
71 #include "dc_priv.h"
72 #include "dev.h"
73 #include "nvhost_sync.h"
74 #include "nvsd.h"
75 #include "nvsd2.h"
76 #include "dpaux.h"
77 #include "nvsr.h"
78
79 #ifdef CONFIG_ADF_TEGRA
80 #include "tegra_adf.h"
81 #endif
82
83 #include "edid.h"
84
85 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
86 #include "fake_panel.h"
87 #include "null_or.h"
88 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
89
90
91 /* HACK! This needs to come from DT */
92 #include "../../../../arch/arm/mach-tegra/iomap.h"
93
94 #define TEGRA_CRC_LATCHED_DELAY         34
95
96 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
97 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
98
99 #define MAX_VRR_V_FRONT_PORCH                   0x1000
100
101 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
102 static struct of_device_id tegra_disa_pd[] = {
103         { .compatible = "nvidia, tegra210-disa-pd", },
104         { .compatible = "nvidia, tegra132-disa-pd", },
105         { .compatible = "nvidia, tegra124-disa-pd", },
106         {},
107 };
108
109 static struct of_device_id tegra_disb_pd[] = {
110         { .compatible = "nvidia, tegra210-disb-pd", },
111         { .compatible = "nvidia, tegra132-disb-pd", },
112         { .compatible = "nvidia, tegra124-disb-pd", },
113         {},
114 };
115 #endif
116
117 static struct fb_videomode tegra_dc_vga_mode = {
118         .refresh = 60,
119         .xres = 640,
120         .yres = 480,
121         .pixclock = KHZ2PICOS(25200),
122         .hsync_len = 96,        /* h_sync_width */
123         .vsync_len = 2,         /* v_sync_width */
124         .left_margin = 48,      /* h_back_porch */
125         .upper_margin = 33,     /* v_back_porch */
126         .right_margin = 16,     /* h_front_porch */
127         .lower_margin = 10,     /* v_front_porch */
128         .vmode = 0,
129         .sync = 0,
130 };
131
132 /* needs to be big enough to be index by largest supported out->type */
133 static struct tegra_dc_mode override_disp_mode[TEGRA_DC_OUT_NULL + 1];
134
135 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
136 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq);
137
138 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out);
139 #ifdef PM
140 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state);
141 static int tegra_dc_resume(struct platform_device *ndev);
142 #endif
143
144 static struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
145
146 #ifdef CONFIG_TEGRA_NVDISPLAY
147 static struct tegra_dc_win      tegra_dc_windows[DC_N_WINDOWS];
148 #endif
149
150
151 static DEFINE_MUTEX(tegra_dc_lock);
152 static DEFINE_MUTEX(shared_lock);
153
154 static struct device_dma_parameters tegra_dc_dma_parameters = {
155         .max_segment_size = UINT_MAX,
156 };
157
158 static const struct {
159         bool h;
160         bool v;
161 } can_filter[] = {
162         /* Window A has no filtering */
163         { false, false },
164         /* Window B has both H and V filtering */
165         { true,  true  },
166         /* Window C has only H filtering */
167         { false, true  },
168 };
169
170 #ifdef CONFIG_TEGRA_DC_CMU
171 static struct tegra_dc_cmu default_cmu = {
172         /* lut1 maps sRGB to linear space. */
173         {
174                 0,    1,    2,    4,    5,    6,    7,    9,
175                 10,   11,   12,   14,   15,   16,   18,   20,
176                 21,   23,   25,   27,   29,   31,   33,   35,
177                 37,   40,   42,   45,   48,   50,   53,   56,
178                 59,   62,   66,   69,   72,   76,   79,   83,
179                 87,   91,   95,   99,   103,  107,  112,  116,
180                 121,  126,  131,  136,  141,  146,  151,  156,
181                 162,  168,  173,  179,  185,  191,  197,  204,
182                 210,  216,  223,  230,  237,  244,  251,  258,
183                 265,  273,  280,  288,  296,  304,  312,  320,
184                 329,  337,  346,  354,  363,  372,  381,  390,
185                 400,  409,  419,  428,  438,  448,  458,  469,
186                 479,  490,  500,  511,  522,  533,  544,  555,
187                 567,  578,  590,  602,  614,  626,  639,  651,
188                 664,  676,  689,  702,  715,  728,  742,  755,
189                 769,  783,  797,  811,  825,  840,  854,  869,
190                 884,  899,  914,  929,  945,  960,  976,  992,
191                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
192                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
193                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
194                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
195                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
196                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
197                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
198                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
199                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
200                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
201                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
202                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
203                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
204                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
205                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
206         },
207         /* csc */
208         {
209                 0x100, 0x0,   0x0,
210                 0x0,   0x100, 0x0,
211                 0x0,   0x0,   0x100,
212         },
213         /* lut2 maps linear space to sRGB*/
214         {
215                 0,    1,    2,    2,    3,    4,    5,    6,
216                 6,    7,    8,    9,    10,   10,   11,   12,
217                 13,   13,   14,   15,   15,   16,   16,   17,
218                 18,   18,   19,   19,   20,   20,   21,   21,
219                 22,   22,   23,   23,   23,   24,   24,   25,
220                 25,   25,   26,   26,   27,   27,   27,   28,
221                 28,   29,   29,   29,   30,   30,   30,   31,
222                 31,   31,   32,   32,   32,   33,   33,   33,
223                 34,   34,   34,   34,   35,   35,   35,   36,
224                 36,   36,   37,   37,   37,   37,   38,   38,
225                 38,   38,   39,   39,   39,   40,   40,   40,
226                 40,   41,   41,   41,   41,   42,   42,   42,
227                 42,   43,   43,   43,   43,   43,   44,   44,
228                 44,   44,   45,   45,   45,   45,   46,   46,
229                 46,   46,   46,   47,   47,   47,   47,   48,
230                 48,   48,   48,   48,   49,   49,   49,   49,
231                 49,   50,   50,   50,   50,   50,   51,   51,
232                 51,   51,   51,   52,   52,   52,   52,   52,
233                 53,   53,   53,   53,   53,   54,   54,   54,
234                 54,   54,   55,   55,   55,   55,   55,   55,
235                 56,   56,   56,   56,   56,   57,   57,   57,
236                 57,   57,   57,   58,   58,   58,   58,   58,
237                 58,   59,   59,   59,   59,   59,   59,   60,
238                 60,   60,   60,   60,   60,   61,   61,   61,
239                 61,   61,   61,   62,   62,   62,   62,   62,
240                 62,   63,   63,   63,   63,   63,   63,   64,
241                 64,   64,   64,   64,   64,   64,   65,   65,
242                 65,   65,   65,   65,   66,   66,   66,   66,
243                 66,   66,   66,   67,   67,   67,   67,   67,
244                 67,   67,   68,   68,   68,   68,   68,   68,
245                 68,   69,   69,   69,   69,   69,   69,   69,
246                 70,   70,   70,   70,   70,   70,   70,   71,
247                 71,   71,   71,   71,   71,   71,   72,   72,
248                 72,   72,   72,   72,   72,   72,   73,   73,
249                 73,   73,   73,   73,   73,   74,   74,   74,
250                 74,   74,   74,   74,   74,   75,   75,   75,
251                 75,   75,   75,   75,   75,   76,   76,   76,
252                 76,   76,   76,   76,   77,   77,   77,   77,
253                 77,   77,   77,   77,   78,   78,   78,   78,
254                 78,   78,   78,   78,   78,   79,   79,   79,
255                 79,   79,   79,   79,   79,   80,   80,   80,
256                 80,   80,   80,   80,   80,   81,   81,   81,
257                 81,   81,   81,   81,   81,   81,   82,   82,
258                 82,   82,   82,   82,   82,   82,   83,   83,
259                 83,   83,   83,   83,   83,   83,   83,   84,
260                 84,   84,   84,   84,   84,   84,   84,   84,
261                 85,   85,   85,   85,   85,   85,   85,   85,
262                 85,   86,   86,   86,   86,   86,   86,   86,
263                 86,   86,   87,   87,   87,   87,   87,   87,
264                 87,   87,   87,   88,   88,   88,   88,   88,
265                 88,   88,   88,   88,   88,   89,   89,   89,
266                 89,   89,   89,   89,   89,   89,   90,   90,
267                 90,   90,   90,   90,   90,   90,   90,   90,
268                 91,   91,   91,   91,   91,   91,   91,   91,
269                 91,   91,   92,   92,   92,   92,   92,   92,
270                 92,   92,   92,   92,   93,   93,   93,   93,
271                 93,   93,   93,   93,   93,   93,   94,   94,
272                 94,   94,   94,   94,   94,   94,   94,   94,
273                 95,   95,   95,   95,   95,   95,   95,   95,
274                 95,   95,   96,   96,   96,   96,   96,   96,
275                 96,   96,   96,   96,   96,   97,   97,   97,
276                 97,   97,   97,   97,   97,   97,   97,   98,
277                 98,   98,   98,   98,   98,   98,   98,   98,
278                 98,   98,   99,   99,   99,   99,   99,   99,
279                 99,   100,  101,  101,  102,  103,  103,  104,
280                 105,  105,  106,  107,  107,  108,  109,  109,
281                 110,  111,  111,  112,  113,  113,  114,  115,
282                 115,  116,  116,  117,  118,  118,  119,  119,
283                 120,  120,  121,  122,  122,  123,  123,  124,
284                 124,  125,  126,  126,  127,  127,  128,  128,
285                 129,  129,  130,  130,  131,  131,  132,  132,
286                 133,  133,  134,  134,  135,  135,  136,  136,
287                 137,  137,  138,  138,  139,  139,  140,  140,
288                 141,  141,  142,  142,  143,  143,  144,  144,
289                 145,  145,  145,  146,  146,  147,  147,  148,
290                 148,  149,  149,  150,  150,  150,  151,  151,
291                 152,  152,  153,  153,  153,  154,  154,  155,
292                 155,  156,  156,  156,  157,  157,  158,  158,
293                 158,  159,  159,  160,  160,  160,  161,  161,
294                 162,  162,  162,  163,  163,  164,  164,  164,
295                 165,  165,  166,  166,  166,  167,  167,  167,
296                 168,  168,  169,  169,  169,  170,  170,  170,
297                 171,  171,  172,  172,  172,  173,  173,  173,
298                 174,  174,  174,  175,  175,  176,  176,  176,
299                 177,  177,  177,  178,  178,  178,  179,  179,
300                 179,  180,  180,  180,  181,  181,  182,  182,
301                 182,  183,  183,  183,  184,  184,  184,  185,
302                 185,  185,  186,  186,  186,  187,  187,  187,
303                 188,  188,  188,  189,  189,  189,  189,  190,
304                 190,  190,  191,  191,  191,  192,  192,  192,
305                 193,  193,  193,  194,  194,  194,  195,  195,
306                 195,  196,  196,  196,  196,  197,  197,  197,
307                 198,  198,  198,  199,  199,  199,  200,  200,
308                 200,  200,  201,  201,  201,  202,  202,  202,
309                 202,  203,  203,  203,  204,  204,  204,  205,
310                 205,  205,  205,  206,  206,  206,  207,  207,
311                 207,  207,  208,  208,  208,  209,  209,  209,
312                 209,  210,  210,  210,  211,  211,  211,  211,
313                 212,  212,  212,  213,  213,  213,  213,  214,
314                 214,  214,  214,  215,  215,  215,  216,  216,
315                 216,  216,  217,  217,  217,  217,  218,  218,
316                 218,  219,  219,  219,  219,  220,  220,  220,
317                 220,  221,  221,  221,  221,  222,  222,  222,
318                 223,  223,  223,  223,  224,  224,  224,  224,
319                 225,  225,  225,  225,  226,  226,  226,  226,
320                 227,  227,  227,  227,  228,  228,  228,  228,
321                 229,  229,  229,  229,  230,  230,  230,  230,
322                 231,  231,  231,  231,  232,  232,  232,  232,
323                 233,  233,  233,  233,  234,  234,  234,  234,
324                 235,  235,  235,  235,  236,  236,  236,  236,
325                 237,  237,  237,  237,  238,  238,  238,  238,
326                 239,  239,  239,  239,  240,  240,  240,  240,
327                 240,  241,  241,  241,  241,  242,  242,  242,
328                 242,  243,  243,  243,  243,  244,  244,  244,
329                 244,  244,  245,  245,  245,  245,  246,  246,
330                 246,  246,  247,  247,  247,  247,  247,  248,
331                 248,  248,  248,  249,  249,  249,  249,  249,
332                 250,  250,  250,  250,  251,  251,  251,  251,
333                 251,  252,  252,  252,  252,  253,  253,  253,
334                 253,  253,  254,  254,  254,  254,  255,  255,
335         },
336 };
337
338 static struct tegra_dc_cmu default_limited_cmu = {
339         /* lut1 maps sRGB to linear space. */
340         {
341                 0,    1,    2,    4,    5,    6,    7,    9,
342                 10,   11,   12,   14,   15,   16,   18,   20,
343                 21,   23,   25,   27,   29,   31,   33,   35,
344                 37,   40,   42,   45,   48,   50,   53,   56,
345                 59,   62,   66,   69,   72,   76,   79,   83,
346                 87,   91,   95,   99,   103,  107,  112,  116,
347                 121,  126,  131,  136,  141,  146,  151,  156,
348                 162,  168,  173,  179,  185,  191,  197,  204,
349                 210,  216,  223,  230,  237,  244,  251,  258,
350                 265,  273,  280,  288,  296,  304,  312,  320,
351                 329,  337,  346,  354,  363,  372,  381,  390,
352                 400,  409,  419,  428,  438,  448,  458,  469,
353                 479,  490,  500,  511,  522,  533,  544,  555,
354                 567,  578,  590,  602,  614,  626,  639,  651,
355                 664,  676,  689,  702,  715,  728,  742,  755,
356                 769,  783,  797,  811,  825,  840,  854,  869,
357                 884,  899,  914,  929,  945,  960,  976,  992,
358                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
359                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
360                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
361                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
362                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
363                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
364                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
365                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
366                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
367                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
368                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
369                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
370                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
371                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
372                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
373         },
374         /* csc */
375         {
376                 0x100, 0x000, 0x000,
377                 0x000, 0x100, 0x000,
378                 0x000, 0x000, 0x100,
379         },
380         /*
381          * lut2 maps linear space back to sRGB, where
382          * the output range is [16...235] (limited).
383          */
384         {
385                 16,  17,  17,  18,  19,  19,  20,  21,
386                 22,  22,  23,  24,  24,  25,  26,  26,
387                 27,  27,  28,  29,  29,  30,  30,  31,
388                 31,  32,  32,  32,  33,  33,  34,  34,
389                 35,  35,  35,  36,  36,  36,  37,  37,
390                 38,  38,  38,  39,  39,  39,  40,  40,
391                 40,  41,  41,  41,  41,  42,  42,  42,
392                 43,  43,  43,  43,  44,  44,  44,  45,
393                 45,  45,  45,  46,  46,  46,  46,  47,
394                 47,  47,  47,  48,  48,  48,  48,  49,
395                 49,  49,  49,  49,  50,  50,  50,  50,
396                 51,  51,  51,  51,  51,  52,  52,  52,
397                 52,  53,  53,  53,  53,  53,  54,  54,
398                 54,  54,  54,  55,  55,  55,  55,  55,
399                 56,  56,  56,  56,  56,  56,  57,  57,
400                 57,  57,  57,  58,  58,  58,  58,  58,
401                 58,  59,  59,  59,  59,  59,  60,  60,
402                 60,  60,  60,  60,  61,  61,  61,  61,
403                 61,  61,  62,  62,  62,  62,  62,  62,
404                 63,  63,  63,  63,  63,  63,  63,  64,
405                 64,  64,  64,  64,  64,  65,  65,  65,
406                 65,  65,  65,  65,  66,  66,  66,  66,
407                 66,  66,  67,  67,  67,  67,  67,  67,
408                 67,  68,  68,  68,  68,  68,  68,  68,
409                 69,  69,  69,  69,  69,  69,  69,  69,
410                 70,  70,  70,  70,  70,  70,  70,  71,
411                 71,  71,  71,  71,  71,  71,  72,  72,
412                 72,  72,  72,  72,  72,  72,  73,  73,
413                 73,  73,  73,  73,  73,  73,  74,  74,
414                 74,  74,  74,  74,  74,  74,  75,  75,
415                 75,  75,  75,  75,  75,  75,  76,  76,
416                 76,  76,  76,  76,  76,  76,  76,  77,
417                 77,  77,  77,  77,  77,  77,  77,  78,
418                 78,  78,  78,  78,  78,  78,  78,  78,
419                 79,  79,  79,  79,  79,  79,  79,  79,
420                 80,  80,  80,  80,  80,  80,  80,  80,
421                 80,  81,  81,  81,  81,  81,  81,  81,
422                 81,  81,  81,  82,  82,  82,  82,  82,
423                 82,  82,  82,  82,  83,  83,  83,  83,
424                 83,  83,  83,  83,  83,  84,  84,  84,
425                 84,  84,  84,  84,  84,  84,  84,  85,
426                 85,  85,  85,  85,  85,  85,  85,  85,
427                 85,  86,  86,  86,  86,  86,  86,  86,
428                 86,  86,  86,  87,  87,  87,  87,  87,
429                 87,  87,  87,  87,  87,  88,  88,  88,
430                 88,  88,  88,  88,  88,  88,  88,  89,
431                 89,  89,  89,  89,  89,  89,  89,  89,
432                 89,  89,  90,  90,  90,  90,  90,  90,
433                 90,  90,  90,  90,  91,  91,  91,  91,
434                 91,  91,  91,  91,  91,  91,  91,  92,
435                 92,  92,  92,  92,  92,  92,  92,  92,
436                 92,  92,  93,  93,  93,  93,  93,  93,
437                 93,  93,  93,  93,  93,  94,  94,  94,
438                 94,  94,  94,  94,  94,  94,  94,  94,
439                 94,  95,  95,  95,  95,  95,  95,  95,
440                 95,  95,  95,  95,  96,  96,  96,  96,
441                 96,  96,  96,  96,  96,  96,  96,  96,
442                 97,  97,  97,  97,  97,  97,  97,  97,
443                 97,  97,  97,  97,  98,  98,  98,  98,
444                 98,  98,  98,  98,  98,  98,  98,  98,
445                 99,  99,  99,  99,  99,  99,  99,  99,
446                 99,  99,  99,  99, 100, 100, 100, 100,
447                 100, 100, 100, 100, 100, 100, 100, 100,
448                 100, 101, 101, 101, 101, 101, 101, 101,
449                 102, 102, 103, 104, 104, 105, 105, 106,
450                 107, 107, 108, 108, 109, 109, 110, 111,
451                 111, 112, 112, 113, 113, 114, 114, 115,
452                 115, 116, 116, 117, 117, 118, 118, 119,
453                 119, 120, 120, 121, 121, 122, 122, 123,
454                 123, 124, 124, 125, 125, 126, 126, 127,
455                 127, 127, 128, 128, 129, 129, 130, 130,
456                 131, 131, 131, 132, 132, 133, 133, 134,
457                 134, 134, 135, 135, 136, 136, 136, 137,
458                 137, 138, 138, 139, 139, 139, 140, 140,
459                 141, 141, 141, 142, 142, 142, 143, 143,
460                 144, 144, 144, 145, 145, 145, 146, 146,
461                 147, 147, 147, 148, 148, 148, 149, 149,
462                 150, 150, 150, 151, 151, 151, 152, 152,
463                 152, 153, 153, 153, 154, 154, 154, 155,
464                 155, 155, 156, 156, 156, 157, 157, 157,
465                 158, 158, 158, 159, 159, 159, 160, 160,
466                 160, 161, 161, 161, 162, 162, 162, 163,
467                 163, 163, 164, 164, 164, 165, 165, 165,
468                 166, 166, 166, 166, 167, 167, 167, 168,
469                 168, 168, 169, 169, 169, 169, 170, 170,
470                 170, 171, 171, 171, 172, 172, 172, 172,
471                 173, 173, 173, 174, 174, 174, 174, 175,
472                 175, 175, 176, 176, 176, 176, 177, 177,
473                 177, 178, 178, 178, 178, 179, 179, 179,
474                 180, 180, 180, 180, 181, 181, 181, 181,
475                 182, 182, 182, 183, 183, 183, 183, 184,
476                 184, 184, 184, 185, 185, 185, 185, 186,
477                 186, 186, 187, 187, 187, 187, 188, 188,
478                 188, 188, 189, 189, 189, 189, 190, 190,
479                 190, 190, 191, 191, 191, 191, 192, 192,
480                 192, 192, 193, 193, 193, 193, 194, 194,
481                 194, 194, 195, 195, 195, 195, 196, 196,
482                 196, 196, 197, 197, 197, 197, 198, 198,
483                 198, 198, 199, 199, 199, 199, 199, 200,
484                 200, 200, 200, 201, 201, 201, 201, 202,
485                 202, 202, 202, 203, 203, 203, 203, 203,
486                 204, 204, 204, 204, 205, 205, 205, 205,
487                 206, 206, 206, 206, 206, 207, 207, 207,
488                 207, 208, 208, 208, 208, 208, 209, 209,
489                 209, 209, 210, 210, 210, 210, 210, 211,
490                 211, 211, 211, 212, 212, 212, 212, 212,
491                 213, 213, 213, 213, 213, 214, 214, 214,
492                 214, 215, 215, 215, 215, 215, 216, 216,
493                 216, 216, 216, 217, 217, 217, 217, 218,
494                 218, 218, 218, 218, 219, 219, 219, 219,
495                 219, 220, 220, 220, 220, 220, 221, 221,
496                 221, 221, 221, 222, 222, 222, 222, 222,
497                 223, 223, 223, 223, 224, 224, 224, 224,
498                 224, 225, 225, 225, 225, 225, 226, 226,
499                 226, 226, 226, 227, 227, 227, 227, 227,
500                 227, 228, 228, 228, 228, 228, 229, 229,
501                 229, 229, 229, 230, 230, 230, 230, 230,
502                 231, 231, 231, 231, 231, 232, 232, 232,
503                 232, 232, 233, 233, 233, 233, 233, 233,
504                 234, 234, 234, 234, 234, 235, 235, 235,
505         },
506 };
507 #elif defined(CONFIG_TEGRA_DC_CMU_V2)
508 static struct tegra_dc_cmu default_cmu = {
509         {},
510 };
511 static struct tegra_dc_cmu default_limited_cmu = {
512         {},
513 };
514 #endif
515
516 void tegra_dc_clk_enable(struct tegra_dc *dc)
517 {
518         tegra_disp_clk_prepare_enable(dc->clk);
519         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
520 }
521
522 void tegra_dc_clk_disable(struct tegra_dc *dc)
523 {
524         tegra_disp_clk_disable_unprepare(dc->clk);
525         tegra_dvfs_set_rate(dc->clk, 0);
526 }
527
528 void tegra_dc_get(struct tegra_dc *dc)
529 {
530         tegra_dc_io_start(dc);
531
532         /* extra reference to dc clk */
533         tegra_disp_clk_prepare_enable(dc->clk);
534 }
535 EXPORT_SYMBOL(tegra_dc_get);
536
537 void tegra_dc_put(struct tegra_dc *dc)
538 {
539         /* balance extra dc clk reference */
540         tegra_disp_clk_disable_unprepare(dc->clk);
541
542         tegra_dc_io_end(dc);
543 }
544 EXPORT_SYMBOL(tegra_dc_put);
545
546 unsigned tegra_dc_out_flags_from_dev(struct device *dev)
547 {
548         struct platform_device *ndev = NULL;
549         struct tegra_dc *dc = NULL;
550
551         if (dev)
552                 ndev = to_platform_device(dev);
553         if (ndev)
554                 dc = platform_get_drvdata(ndev);
555         if (dc)
556                 return dc->out->flags;
557         else
558                 return 0;
559 }
560 EXPORT_SYMBOL(tegra_dc_out_flags_from_dev);
561
562 bool tegra_dc_initialized(struct device *dev)
563 {
564         struct platform_device *ndev = NULL;
565         struct tegra_dc *dc = NULL;
566
567         if (dev)
568                 ndev = to_platform_device(dev);
569         if (ndev)
570                 dc = platform_get_drvdata(ndev);
571         if (dc)
572                 return dc->initialized;
573         else
574                 return false;
575 }
576 EXPORT_SYMBOL(tegra_dc_initialized);
577
578 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
579 {
580         if (1 == atomic_inc_return(&dc->holding)) {
581                 tegra_dc_get(dc);
582                 if (dc->out_ops && dc->out_ops->hold)
583                         dc->out_ops->hold(dc);
584         }
585 }
586
587 void tegra_dc_release_dc_out(struct tegra_dc *dc)
588 {
589         if (0 == atomic_dec_return(&dc->holding)) {
590                 if (dc->out_ops && dc->out_ops->release)
591                         dc->out_ops->release(dc);
592                 tegra_dc_put(dc);
593         }
594 }
595
596 #define DUMP_REG(a) do {                        \
597         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
598                  #a, a, tegra_dc_readl(dc, a));               \
599         print(data, buff);                                    \
600         } while (0)
601
602 static void _dump_regs(struct tegra_dc *dc, void *data,
603                        void (* print)(void *data, const char *str))
604 {
605         int i;
606         char buff[256];
607         const char winname[] = "ABCDHT";
608         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
609
610         /* If gated, quietly return. */
611         if (!tegra_powergate_is_powered(dc->powergate_id))
612                 return;
613
614         mutex_lock(&dc->lock);
615         tegra_dc_get(dc);
616         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
617                 DC_CMD_STATE_ACCESS);
618
619         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
620         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
621         DUMP_REG(DC_CMD_SIGNAL_RAISE);
622         DUMP_REG(DC_CMD_INT_STATUS);
623         DUMP_REG(DC_CMD_INT_MASK);
624         DUMP_REG(DC_CMD_INT_ENABLE);
625         DUMP_REG(DC_CMD_INT_TYPE);
626         DUMP_REG(DC_CMD_INT_POLARITY);
627         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
628         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
629         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
630         DUMP_REG(DC_CMD_STATE_ACCESS);
631         DUMP_REG(DC_CMD_STATE_CONTROL);
632         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
633         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
634
635         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
636         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
637         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
638         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
639         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
640         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
641         DUMP_REG(DC_DISP_REF_TO_SYNC);
642         DUMP_REG(DC_DISP_SYNC_WIDTH);
643         DUMP_REG(DC_DISP_BACK_PORCH);
644         DUMP_REG(DC_DISP_DISP_ACTIVE);
645         DUMP_REG(DC_DISP_FRONT_PORCH);
646         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
647         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
648         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
649         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
650         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
651         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
652         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
653         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
654         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
655         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
656         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
657         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
658         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
659         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
660         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
661         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
662         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
663         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
664         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
665         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
666         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
667         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
668         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
669         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
670         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
671         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
672         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
673         DUMP_REG(DC_DISP_M0_CONTROL);
674         DUMP_REG(DC_DISP_M1_CONTROL);
675         DUMP_REG(DC_DISP_DI_CONTROL);
676         DUMP_REG(DC_DISP_PP_CONTROL);
677         DUMP_REG(DC_DISP_PP_SELECT_A);
678         DUMP_REG(DC_DISP_PP_SELECT_B);
679         DUMP_REG(DC_DISP_PP_SELECT_C);
680         DUMP_REG(DC_DISP_PP_SELECT_D);
681         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
682         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
683         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
684         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
685         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
686         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
687         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
688 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
689         DUMP_REG(DC_DISP_BORDER_COLOR);
690 #endif
691         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
692         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
693         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
694         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
695         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
696         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
697         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
698         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
699 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
700         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
701         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
702 #endif
703         DUMP_REG(DC_DISP_CURSOR_POSITION);
704         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
705         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
706         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
707         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
708         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
709         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
710         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
711         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
712         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
713         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
714 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
715         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
716 #endif
717         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
718         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
719 #if defined(CONFIG_TEGRA_DC_INTERLACE)
720         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
721         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
722         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
723         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
724         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
725         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
726 #endif
727
728         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
729         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
730         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
731         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
732         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
733         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
734         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
735         DUMP_REG(DC_DISP_M1_CONTROL);
736         DUMP_REG(DC_COM_PM1_CONTROL);
737         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
738         DUMP_REG(DC_DISP_SD_CONTROL);
739
740 #ifdef CONFIG_TEGRA_DC_CMU
741         DUMP_REG(DC_COM_CMU_CSC_KRR);
742         DUMP_REG(DC_COM_CMU_CSC_KGR);
743         DUMP_REG(DC_COM_CMU_CSC_KBR);
744         DUMP_REG(DC_COM_CMU_CSC_KRG);
745         DUMP_REG(DC_COM_CMU_CSC_KGG);
746         DUMP_REG(DC_COM_CMU_CSC_KBG);
747         DUMP_REG(DC_COM_CMU_CSC_KRB);
748         DUMP_REG(DC_COM_CMU_CSC_KGB);
749         DUMP_REG(DC_COM_CMU_CSC_KBB);
750 #endif
751
752         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
753                 print(data, "\n");
754                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
755                 print(data, buff);
756
757                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
758                                 DC_CMD_DISPLAY_WINDOW_HEADER);
759                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
760                 DUMP_REG(DC_WIN_WIN_OPTIONS);
761                 DUMP_REG(DC_WIN_BYTE_SWAP);
762                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
763                 DUMP_REG(DC_WIN_COLOR_DEPTH);
764                 DUMP_REG(DC_WIN_POSITION);
765                 DUMP_REG(DC_WIN_SIZE);
766                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
767                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
768                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
769                 DUMP_REG(DC_WIN_DDA_INCREMENT);
770                 DUMP_REG(DC_WIN_LINE_STRIDE);
771 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
772                 DUMP_REG(DC_WIN_BUF_STRIDE);
773                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
774 #endif
775                 DUMP_REG(DC_WIN_BLEND_NOKEY);
776                 DUMP_REG(DC_WIN_BLEND_1WIN);
777                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
778                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
779                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
780                 DUMP_REG(DC_WIN_GLOBAL_ALPHA);
781 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
782         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
783         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
784         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
785                 DUMP_REG(DC_WINBUF_BLEND_LAYER_CONTROL);
786 #endif
787                 DUMP_REG(DC_WINBUF_START_ADDR);
788                 DUMP_REG(DC_WINBUF_START_ADDR_U);
789                 DUMP_REG(DC_WINBUF_START_ADDR_V);
790                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
791                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
792 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
793         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
794         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
795         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
796                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
797                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
798                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
799                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
800                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
801                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
802                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
803                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
804                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
805                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
806                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
807 #endif
808                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
809                 DUMP_REG(DC_WIN_CSC_YOF);
810                 DUMP_REG(DC_WIN_CSC_KYRGB);
811                 DUMP_REG(DC_WIN_CSC_KUR);
812                 DUMP_REG(DC_WIN_CSC_KVR);
813                 DUMP_REG(DC_WIN_CSC_KUG);
814                 DUMP_REG(DC_WIN_CSC_KVG);
815                 DUMP_REG(DC_WIN_CSC_KUB);
816                 DUMP_REG(DC_WIN_CSC_KVB);
817
818 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
819                 DUMP_REG(DC_WINBUF_CDE_CONTROL);
820                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASE_0);
821                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASEHI_0);
822                 DUMP_REG(DC_WINBUF_CDE_ZBC_COLOR_0);
823                 DUMP_REG(DC_WINBUF_CDE_SURFACE_OFFSET_0);
824                 DUMP_REG(DC_WINBUF_CDE_CTB_ENTRY_0);
825                 DUMP_REG(DC_WINBUF_CDE_CG_SW_OVR);
826                 DUMP_REG(DC_WINBUF_CDE_PM_CONTROL);
827                 DUMP_REG(DC_WINBUF_CDE_PM_COUNTER);
828 #endif
829         }
830
831         tegra_dc_put(dc);
832         mutex_unlock(&dc->lock);
833 }
834
835 #undef DUMP_REG
836
837 #ifdef DEBUG
838 static void dump_regs_print(void *data, const char *str)
839 {
840         struct tegra_dc *dc = data;
841         dev_dbg(&dc->ndev->dev, "%s", str);
842 }
843
844 static void dump_regs(struct tegra_dc *dc)
845 {
846         _dump_regs(dc, dc, dump_regs_print);
847 }
848 #else /* !DEBUG */
849
850 static void dump_regs(struct tegra_dc *dc) {}
851
852 #endif /* DEBUG */
853
854 #ifdef CONFIG_DEBUG_FS
855
856 static void dbg_regs_print(void *data, const char *str)
857 {
858         struct seq_file *s = data;
859
860         seq_printf(s, "%s", str);
861 }
862
863 #undef DUMP_REG
864
865 static int dbg_dc_show(struct seq_file *s, void *unused)
866 {
867         struct tegra_dc *dc = s->private;
868
869         _dump_regs(dc, s, dbg_regs_print);
870
871         return 0;
872 }
873
874
875 static int dbg_dc_open(struct inode *inode, struct file *file)
876 {
877         return single_open(file, dbg_dc_show, inode->i_private);
878 }
879
880 static const struct file_operations regs_fops = {
881         .open           = dbg_dc_open,
882         .read           = seq_read,
883         .llseek         = seq_lseek,
884         .release        = single_release,
885 };
886
887 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
888 {
889         struct tegra_dc *dc = s->private;
890         struct tegra_dc_mode *m;
891
892         mutex_lock(&dc->lock);
893         m = &dc->mode;
894         seq_printf(s,
895                 "pclk: %d\n"
896                 "h_ref_to_sync: %d\n"
897                 "v_ref_to_sync: %d\n"
898                 "h_sync_width: %d\n"
899                 "v_sync_width: %d\n"
900                 "h_back_porch: %d\n"
901                 "v_back_porch: %d\n"
902                 "h_active: %d\n"
903                 "v_active: %d\n"
904                 "h_front_porch: %d\n"
905                 "v_front_porch: %d\n"
906                 "flags: 0x%x\n"
907                 "stereo_mode: %d\n"
908                 "avi_m: 0x%x\n",
909                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
910                 m->h_sync_width, m->v_sync_width,
911                 m->h_back_porch, m->v_back_porch,
912                 m->h_active, m->v_active,
913                 m->h_front_porch, m->v_front_porch,
914                 m->flags, m->stereo_mode, m->avi_m);
915         mutex_unlock(&dc->lock);
916         return 0;
917 }
918
919 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
920 {
921         return single_open(file, dbg_dc_mode_show, inode->i_private);
922 }
923
924 static const struct file_operations mode_fops = {
925         .open           = dbg_dc_mode_open,
926         .read           = seq_read,
927         .llseek         = seq_lseek,
928         .release        = single_release,
929 };
930
931 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
932 {
933         struct tegra_dc *dc = s->private;
934
935         mutex_lock(&dc->lock);
936         seq_printf(s,
937                 "underflows: %llu\n"
938                 "underflows_a: %llu\n"
939                 "underflows_b: %llu\n"
940                 "underflows_c: %llu\n",
941                 dc->stats.underflows,
942                 dc->stats.underflows_a,
943                 dc->stats.underflows_b,
944                 dc->stats.underflows_c);
945 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
946         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
947         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
948         seq_printf(s,
949                 "underflows_d: %llu\n"
950                 "underflows_h: %llu\n"
951                 "underflows_t: %llu\n",
952                 dc->stats.underflows_d,
953                 dc->stats.underflows_h,
954                 dc->stats.underflows_t);
955 #endif
956 #if defined(CONFIG_TEGRA_NVDISPLAY)
957         seq_printf(s,
958                 "underflow_frames: %llu\n",
959                 dc->stats.underflow_frames);
960 #endif
961         mutex_unlock(&dc->lock);
962
963         return 0;
964 }
965
966 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
967 {
968         return single_open(file, dbg_dc_stats_show, inode->i_private);
969 }
970
971 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
972 {
973         return 0;
974 }
975
976 static ssize_t dbg_dc_event_inject_write(struct file *file,
977         const char __user *addr, size_t len, loff_t *pos)
978 {
979         struct seq_file *m = file->private_data; /* single_open() initialized */
980         struct tegra_dc *dc = m ? m->private : NULL;
981         long event;
982         int ret;
983
984         if (!dc)
985                 return -EINVAL;
986
987         ret = kstrtol_from_user(addr, len, 10, &event);
988         if (ret < 0)
989                 return ret;
990
991         /*
992          * ADF has two seperate events for hotplug connect and disconnect.
993          * We map event 0x0, and 0x1 for them accordingly.  For DC_EXT,
994          * both events map to HOTPLUG.
995          */
996 #ifdef CONFIG_ADF_TEGRA
997         if (event == 0x0)
998                 tegra_adf_process_hotplug_connected(dc->adf, NULL);
999         else if (event == 0x1)
1000                 tegra_adf_process_hotplug_disconnected(dc->adf);
1001         else if (event == 0x2)
1002                 tegra_adf_process_bandwidth_renegotiate(dc->adf, 0);
1003         else {
1004                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
1005                 return -EINVAL; /* unknown event number */
1006         }
1007 #endif
1008 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
1009         if (event == 0x0) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Connected) */
1010                 tegra_dc_ext_process_hotplug(dc->ndev->id, true);
1011         else if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG (Disconnected) */
1012                 tegra_dc_ext_process_hotplug(dc->ndev->id, false);
1013         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
1014                 tegra_dc_ext_process_bandwidth_renegotiate(
1015                                 dc->ndev->id, NULL);
1016         else {
1017                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
1018                 return -EINVAL; /* unknown event number */
1019         }
1020 #endif
1021         return len;
1022 }
1023
1024 /* Update the strings as dc.h get updated for new output types*/
1025 static const char * const dc_outtype_strings[] = {
1026         "TEGRA_DC_OUT_RGB",
1027         "TEGRA_DC_OUT_HDMI",
1028         "TEGRA_DC_OUT_DSI",
1029         "TEGRA_DC_OUT_DP",
1030         "TEGRA_DC_OUT_LVDS",
1031         "TEGRA_DC_OUT_NVSR_DP",
1032         "TEGRA_DC_OUT_FAKE_DP",
1033         "TEGRA_DC_OUT_FAKE_DSIA",
1034         "TEGRA_DC_OUT_FAKE_DSIB",
1035         "TEGRA_DC_OUT_FAKE_DSI_GANGED",
1036         "TEGRA_DC_OUT_NULL",
1037         "TEGRA_DC_OUT_UNKNOWN"
1038 };
1039
1040 static int dbg_dc_outtype_show(struct seq_file *s, void *unused)
1041 {
1042         struct tegra_dc *dc = s->private;
1043
1044         mutex_lock(&dc->lock);
1045         seq_puts(s, "\n");
1046         seq_printf(s,
1047                 "\tDC OUTPUT: \t%s (%d)\n",
1048                 dc_outtype_strings[dc->out->type], dc->out->type);
1049         seq_puts(s, "\n");
1050         mutex_unlock(&dc->lock);
1051         return 0;
1052 }
1053
1054 /* Add specific variable related to each output type.
1055  * Save and reuse on changing the output type
1056  */
1057 #if defined(CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT)
1058 struct tegra_dc_out_info {
1059         struct tegra_dc_out_ops *out_ops;
1060         void *out_data;
1061         struct tegra_dc_out out;
1062         struct tegra_dc_mode mode;
1063         int fblistindex;
1064 };
1065
1066 static struct tegra_dc_out_info dbg_dc_out_info[TEGRA_DC_OUT_MAX];
1067 /* array for saving the out_type for each head */
1068 static int  boot_out_type[] = {-1, -1};
1069
1070 static int is_invalid_dc_out(struct tegra_dc *dc, long dc_outtype)
1071 {
1072         if ((dc_outtype != boot_out_type[dc->ndev->id]) &&
1073                 (dc_outtype != TEGRA_DC_OUT_FAKE_DP) &&
1074                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIA) &&
1075                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIB) &&
1076                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSI_GANGED) &&
1077                 (dc_outtype != TEGRA_DC_OUT_NULL)) {
1078                 dev_err(&dc->ndev->dev,
1079                         "Request 0x%lx is unsupported target out_type\n",
1080                          dc_outtype);
1081                 dev_err(&dc->ndev->dev,
1082                         "boot_out_type[%d] is 0x%x\n",
1083                          dc->ndev->id, boot_out_type[dc->ndev->id]);
1084                 return -EINVAL;
1085         }
1086
1087         return 0;
1088 }
1089
1090 static int is_valid_dsi_out(struct tegra_dc *dc, long dc_outtype)
1091 {
1092         if (((dc_outtype >= TEGRA_DC_OUT_FAKE_DSIA) &&
1093                 (dc_outtype <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) ||
1094                 (dc_outtype == TEGRA_DC_OUT_DSI))
1095                         return 1;
1096
1097         return 0;
1098 }
1099
1100
1101 static int is_valid_fake_support(struct tegra_dc *dc, long dc_outtype)
1102 {
1103         if ((dc_outtype == TEGRA_DC_OUT_FAKE_DP) ||
1104                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIA) ||
1105                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) ||
1106                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) ||
1107                 (dc_outtype == TEGRA_DC_OUT_NULL))
1108                 return 1;
1109
1110         return 0;
1111 }
1112
1113 static int set_avdd(struct tegra_dc *dc, long cur_out, long new_out)
1114 {
1115 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1116         /* T210 macro_clk is failing SOR access
1117          * if avdd_lcd is not enabled
1118          */
1119         bool is_enable = false;
1120         struct tegra_dc_out *dc_out =
1121                 &dbg_dc_out_info[boot_out_type[dc->ndev->id]].out;
1122
1123         /* cur is fake and new is fake - skip */
1124         if (is_valid_fake_support(dc, cur_out) &&
1125                 is_valid_fake_support(dc, new_out))
1126                 return 0;
1127
1128         /* cur is valid and new is fake - enable */
1129         if (!is_valid_fake_support(dc, cur_out) &&
1130                 is_valid_fake_support(dc, new_out))
1131                 is_enable = true;
1132
1133         if (is_enable) {
1134                 if (dc_out && dc_out->enable)
1135                         dc_out->enable(&dc->ndev->dev);
1136         } else {
1137                 if (dc_out && dc_out->disable)
1138                         dc_out->disable(&dc->ndev->dev);
1139         }
1140 #endif
1141         return 0;
1142 }
1143 static ssize_t dbg_dc_out_type_set(struct file *file,
1144         const char __user *addr, size_t len, loff_t *pos)
1145 {
1146         struct seq_file *m = file->private_data; /* single_open() initialized */
1147         struct tegra_dc *dc = m ? m->private : NULL;
1148         long cur_dc_out;
1149         long out_type;
1150         int ret = 0;
1151         bool  allocate = false;
1152
1153         if (!dc)
1154                 return -EINVAL;
1155
1156         ret = kstrtol_from_user(addr, len, 10, &out_type);
1157         if (ret < 0)
1158                 return ret;
1159
1160         if (!dc->pdata->default_out)
1161                 return -EINVAL;
1162
1163         /* check out type is out of range then skip */
1164         if (out_type < TEGRA_DC_OUT_RGB ||
1165                 out_type >= TEGRA_DC_OUT_MAX) {
1166                 dev_err(&dc->ndev->dev, "Unknown out_type 0x%lx\n", out_type);
1167                 return -EINVAL;
1168         }
1169
1170         if (boot_out_type[dc->ndev->id] == -1)
1171                 boot_out_type[dc->ndev->id] = dc->pdata->default_out->type;
1172
1173         cur_dc_out = dc->pdata->default_out->type;
1174
1175         /* Nothing to do if new outtype is same as old
1176          * Allow to switch between booted out type and fake panel out
1177          */
1178         if ((cur_dc_out == out_type) || is_invalid_dc_out(dc, out_type))
1179                 return -EINVAL;
1180
1181         /* disable the dc and output controllers */
1182         if (dc->enabled)
1183                 tegra_dc_disable(dc);
1184
1185         /* If output is already created - save it */
1186         if (dc->out_data) {
1187                 dbg_dc_out_info[cur_dc_out].out_data = dc->out_data;
1188                 dbg_dc_out_info[cur_dc_out].out_ops  = dc->out_ops;
1189                 memcpy(&dbg_dc_out_info[cur_dc_out].out, dc->out,
1190                                         sizeof(struct tegra_dc_out));
1191                 dbg_dc_out_info[cur_dc_out].mode = dc->mode;
1192
1193                 if (is_valid_dsi_out(dc, cur_dc_out) &&
1194                         dbg_dc_out_info[cur_dc_out].out_data)
1195                         tegra_dc_destroy_dsi_resources(dc, cur_dc_out);
1196
1197                 if (!is_valid_fake_support(dc, cur_dc_out))
1198                         dbg_dc_out_info[cur_dc_out].fblistindex =
1199                                                 tegra_fb_update_modelist(dc, 0);
1200
1201                 set_avdd(dc, cur_dc_out, out_type);
1202         }
1203
1204         /* If output already created - reuse it */
1205         if (dbg_dc_out_info[out_type].out_data) {
1206                 mutex_lock(&dc->lp_lock);
1207                 mutex_lock(&dc->lock);
1208
1209                 /* Change the out type */
1210                 dc->pdata->default_out->type = out_type;
1211                 dc->out_ops = dbg_dc_out_info[out_type].out_ops;
1212                 dc->out_data = dbg_dc_out_info[out_type].out_data;
1213                 memcpy(dc->out, &dbg_dc_out_info[out_type].out,
1214                                                 sizeof(struct tegra_dc_out));
1215                 dc->mode = dbg_dc_out_info[out_type].mode;
1216
1217                 /* Re-init the resources that are destroyed for dsi */
1218                 if (is_valid_dsi_out(dc, out_type))
1219                         ret = tegra_dc_reinit_dsi_resources(dc, out_type);
1220
1221                 if (!is_valid_fake_support(dc, out_type))
1222                         tegra_fb_update_modelist(dc,
1223                                         dbg_dc_out_info[out_type].fblistindex);
1224
1225                 mutex_unlock(&dc->lock);
1226                 mutex_unlock(&dc->lp_lock);
1227
1228                 if (ret) {
1229                         dev_err(&dc->ndev->dev, "Failed to reinit!!!\n");
1230                         return -EINVAL;
1231                 }
1232
1233         } else {
1234                 /* Change the out type */
1235                 dc->pdata->default_out->type = out_type;
1236
1237                 /* create new - now restricted to fake_dp only */
1238                 if (out_type == TEGRA_DC_OUT_FAKE_DP) {
1239
1240                         /* set to default bpp */
1241                         if (!dc->pdata->default_out->depth)
1242                                 dc->pdata->default_out->depth = 24;
1243
1244                         /* DP and Fake_Dp use same data
1245                         *  Reuse if already created */
1246                         if (!dbg_dc_out_info[TEGRA_DC_OUT_DP].out_data) {
1247                                 allocate = true;
1248                                 tegra_dc_init_fakedp_panel(dc);
1249                         }
1250                 } else if ((out_type >= TEGRA_DC_OUT_FAKE_DSIA) &&
1251                                 (out_type <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) {
1252                         /* DSI and fake DSI use same data
1253                          * create new if not created yet
1254                          */
1255                         if (!dc->pdata->default_out->depth)
1256                                 dc->pdata->default_out->depth = 18;
1257
1258                         allocate = true;
1259                         tegra_dc_init_fakedsi_panel(dc, out_type);
1260
1261                 } else if (out_type == TEGRA_DC_OUT_NULL) {
1262                         if (!dbg_dc_out_info[TEGRA_DC_OUT_NULL].out_data) {
1263                                 allocate = true;
1264                                 tegra_dc_init_null_or(dc);
1265                         }
1266                 } else {
1267                         /* set  back to existing one */
1268                         dc->pdata->default_out->type = cur_dc_out;
1269                         dev_err(&dc->ndev->dev, "Unknown type is asked\n");
1270                         goto by_pass;
1271                 }
1272
1273                 if (allocate) {
1274                         ret = tegra_dc_set_out(dc, dc->pdata->default_out);
1275                                 if (ret < 0) {
1276                                         dev_err(&dc->ndev->dev,
1277                                         "Failed to initialize DC out ops\n");
1278                                         return -EINVAL;
1279                                 }
1280                 }
1281
1282                 dbg_dc_out_info[out_type].out_ops = dc->out_ops;
1283                 dbg_dc_out_info[out_type].out_data = dc->out_data;
1284                 memcpy(&dbg_dc_out_info[out_type].out, dc->out,
1285                                                 sizeof(struct tegra_dc_out));
1286
1287         }
1288
1289 by_pass:
1290         /*enable the dc and output controllers */
1291         if (!dc->enabled)
1292                 tegra_dc_enable(dc);
1293
1294         return len;
1295 }
1296 #else
1297 static ssize_t dbg_dc_out_type_set(struct file *file,
1298         const char __user *addr, size_t len, loff_t *pos)
1299 {
1300         return -EINVAL;
1301 }
1302 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1303
1304 static const struct file_operations stats_fops = {
1305         .open           = dbg_dc_stats_open,
1306         .read           = seq_read,
1307         .llseek         = seq_lseek,
1308         .release        = single_release,
1309 };
1310
1311 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
1312 {
1313         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
1314 }
1315
1316 static const struct file_operations event_inject_fops = {
1317         .open           = dbg_dc_event_inject_open,
1318         .read           = seq_read,
1319         .write          = dbg_dc_event_inject_write,
1320         .llseek         = seq_lseek,
1321         .release        = single_release,
1322 };
1323
1324 static int dbg_dc_outtype_open(struct inode *inode, struct file *file)
1325 {
1326         return single_open(file, dbg_dc_outtype_show, inode->i_private);
1327 }
1328
1329 static const struct file_operations outtype_fops = {
1330         .open           = dbg_dc_outtype_open,
1331         .read           = seq_read,
1332         .write          = dbg_dc_out_type_set,
1333         .llseek         = seq_lseek,
1334         .release        = single_release,
1335 };
1336
1337 static int dbg_edid_show(struct seq_file *s, void *unused)
1338 {
1339         struct tegra_dc *dc = s->private;
1340         struct tegra_edid *edid = dc->edid;
1341         struct tegra_dc_edid *data;
1342         u8 *buf;
1343         int i;
1344
1345         if (WARN_ON(!dc || !dc->out || !dc->edid))
1346                 return -EINVAL;
1347
1348         data = tegra_edid_get_data(edid);
1349         if (!data) {
1350                 seq_puts(s, "No EDID\n");
1351                 return 0;
1352         }
1353
1354         buf = data->buf;
1355
1356         for (i = 0; i < data->len; i++) {
1357 #ifdef DEBUG
1358                 if (i % 16 == 0)
1359                         seq_printf(s, "edid[%03x] =", i);
1360 #endif
1361
1362                 seq_printf(s, " %02x", buf[i]);
1363
1364                 if (i % 16 == 15)
1365                         seq_puts(s, "\n");
1366
1367         }
1368
1369         tegra_edid_put_data(data);
1370
1371         return 0;
1372 }
1373
1374 static int dbg_edid_open(struct inode *inode, struct file *file)
1375 {
1376         return single_open(file, dbg_edid_show, inode->i_private);
1377 }
1378
1379 static ssize_t dbg_edid_write(struct file *file,
1380 const char __user *addr, size_t len, loff_t *pos)
1381 {
1382         struct seq_file *m = file->private_data;
1383         struct tegra_dc *dc = m ? m->private : NULL;
1384         int ret;
1385
1386         if (WARN_ON(!dc || !dc->out))
1387                 return -EINVAL;
1388
1389         dc->vedid = false;
1390
1391         kfree(dc->vedid_data);
1392         dc->vedid_data = NULL;
1393
1394         if (len < 128) /* invalid edid, turn off vedid */
1395                 return 1;
1396
1397         dc->vedid_data = kmalloc(sizeof(char) * len, GFP_KERNEL);
1398         if (!dc->vedid_data) {
1399                 dev_err(&dc->ndev->dev, "no memory for edid\n");
1400                 return 0; /* dc->vedid is false */
1401         }
1402
1403         ret = copy_from_user(dc->vedid_data, addr, len);
1404         if (ret < 0) {
1405                 dev_err(&dc->ndev->dev, "error copying edid\n");
1406                 kfree(dc->vedid_data);
1407                 dc->vedid_data = NULL;
1408                 return ret; /* dc->vedid is false */
1409         }
1410
1411         dc->vedid = true;
1412
1413         return len;
1414 }
1415
1416 static const struct file_operations edid_fops = {
1417         .open           = dbg_edid_open,
1418         .read           = seq_read,
1419         .llseek         = seq_lseek,
1420         .write          = dbg_edid_write,
1421         .release        = single_release,
1422 };
1423
1424 static int dbg_hotplug_show(struct seq_file *s, void *unused)
1425 {
1426         struct tegra_dc *dc = s->private;
1427
1428         if (WARN_ON(!dc || !dc->out))
1429                 return -EINVAL;
1430
1431         rmb();
1432         seq_put_decimal_ll(s, '\0', dc->out->hotplug_state);
1433         seq_putc(s, '\n');
1434         return 0;
1435 }
1436
1437 static int dbg_hotplug_open(struct inode *inode, struct file *file)
1438 {
1439         return single_open(file, dbg_hotplug_show, inode->i_private);
1440 }
1441
1442 static ssize_t dbg_hotplug_write(struct file *file, const char __user *addr,
1443         size_t len, loff_t *pos)
1444 {
1445         struct seq_file *m = file->private_data; /* single_open() initialized */
1446         struct tegra_dc *dc = m ? m->private : NULL;
1447         int ret;
1448         long new_state;
1449         int hotplug_state;
1450
1451         if (WARN_ON(!dc || !dc->out))
1452                 return -EINVAL;
1453
1454         ret = kstrtol_from_user(addr, len, 10, &new_state);
1455         if (ret < 0)
1456                 return ret;
1457
1458         mutex_lock(&dc->lock);
1459         rmb();
1460         hotplug_state = dc->out->hotplug_state;
1461         if (hotplug_state == 0 && new_state != 0
1462                         && tegra_dc_hotplug_supported(dc)) {
1463                 /* was 0, now -1 or 1.
1464                  * we are overriding the hpd GPIO, so ignore the interrupt. */
1465                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1466
1467                 disable_irq(gpio_irq);
1468         } else if (hotplug_state != 0 && new_state == 0
1469                         && tegra_dc_hotplug_supported(dc)) {
1470                 /* was -1 or 1, and now 0
1471                  * restore the interrupt for hpd GPIO. */
1472                 int gpio_irq = gpio_to_irq(dc->out->hotplug_gpio);
1473
1474                 enable_irq(gpio_irq);
1475         }
1476
1477         dc->out->hotplug_state = new_state;
1478         wmb();
1479
1480         /* retrigger the hotplug */
1481         if (dc->out_ops->detect)
1482                 dc->connected = dc->out_ops->detect(dc);
1483         mutex_unlock(&dc->lock);
1484
1485         return len;
1486 }
1487
1488 static const struct file_operations dbg_hotplug_fops = {
1489         .open           = dbg_hotplug_open,
1490         .read           = seq_read,
1491         .write          = dbg_hotplug_write,
1492         .llseek         = seq_lseek,
1493         .release        = single_release,
1494 };
1495
1496 static int dbg_vrr_enable_show(struct seq_file *m, void *unused)
1497 {
1498         struct tegra_vrr *vrr = m->private;
1499
1500         if (!vrr) return -EINVAL;
1501
1502         seq_printf(m, "vrr enable state: %d\n", vrr->enable);
1503
1504         return 0;
1505 }
1506
1507 static int dbg_vrr_enable_open(struct inode *inode, struct file *file)
1508 {
1509         return single_open(file, dbg_vrr_enable_show, inode->i_private);
1510 }
1511
1512 static const struct file_operations dbg_vrr_enable_ops = {
1513         .open = dbg_vrr_enable_open,
1514         .read = seq_read,
1515         .llseek = seq_lseek,
1516         .release = single_release,
1517 };
1518
1519 static int dbg_vrr_dcb_show(struct seq_file *m, void *unused)
1520 {
1521         struct tegra_vrr *vrr = m->private;
1522
1523         if (!vrr)
1524                 return -EINVAL;
1525
1526         seq_printf(m, "vrr dc balance: %d\n", vrr->dcb);
1527
1528         return 0;
1529 }
1530
1531 static int dbg_vrr_dcb_open(struct inode *inode, struct file *file)
1532 {
1533         return single_open(file, dbg_vrr_dcb_show, inode->i_private);
1534 }
1535
1536 static const struct file_operations dbg_vrr_dcb_ops = {
1537         .open = dbg_vrr_dcb_open,
1538         .read = seq_read,
1539         .llseek = seq_lseek,
1540         .release = single_release,
1541 };
1542
1543 static int dbg_vrr_db_tolerance_show(struct seq_file *m, void *unused)
1544 {
1545         struct tegra_vrr *vrr = m->private;
1546
1547         if (!vrr)
1548                 return -EINVAL;
1549
1550         seq_printf(m, "vrr db tolerance: %d\n", vrr->db_tolerance);
1551
1552         return 0;
1553 }
1554
1555 static ssize_t dbg_vrr_db_tolerance_write(struct file *file,
1556                 const char __user *addr, size_t len, loff_t *pos)
1557 {
1558         struct seq_file *m = file->private_data;
1559         struct tegra_vrr *vrr = m->private;
1560         long   new_value;
1561         int    ret;
1562
1563         if (!vrr)
1564                 return -EINVAL;
1565
1566         ret = kstrtol_from_user(addr, len, 10, &new_value);
1567         if (ret < 0)
1568                 return ret;
1569
1570         vrr->db_tolerance = new_value;
1571
1572         return len;
1573 }
1574
1575 static int dbg_vrr_db_tolerance_open(struct inode *inode, struct file *file)
1576 {
1577         return single_open(file, dbg_vrr_db_tolerance_show, inode->i_private);
1578 }
1579
1580 static const struct file_operations dbg_vrr_db_tolerance_ops = {
1581         .open = dbg_vrr_db_tolerance_open,
1582         .read = seq_read,
1583         .write = dbg_vrr_db_tolerance_write,
1584         .llseek = seq_lseek,
1585         .release = single_release,
1586 };
1587
1588 static int dbg_vrr_frame_avg_pct_show(struct seq_file *m, void *unused)
1589 {
1590         struct tegra_vrr *vrr = m->private;
1591
1592         if (!vrr)
1593                 return -EINVAL;
1594
1595         seq_printf(m, "vrr frame average percent: %d\n", vrr->frame_avg_pct);
1596
1597         return 0;
1598 }
1599
1600 static ssize_t dbg_vrr_frame_avg_pct_write(struct file *file,
1601                 const char __user *addr, size_t len, loff_t *pos)
1602 {
1603         struct seq_file *m = file->private_data;
1604         struct tegra_vrr *vrr = m->private;
1605         long   new_pct;
1606         int    ret;
1607
1608         if (!vrr)
1609                 return -EINVAL;
1610
1611         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1612         if (ret < 0)
1613                 return ret;
1614
1615         vrr->frame_avg_pct = new_pct;
1616
1617         return len;
1618 }
1619
1620 static int dbg_vrr_frame_avg_pct_open(struct inode *inode, struct file *file)
1621 {
1622         return single_open(file, dbg_vrr_frame_avg_pct_show, inode->i_private);
1623 }
1624
1625 static const struct file_operations dbg_vrr_frame_avg_pct_ops = {
1626         .open = dbg_vrr_frame_avg_pct_open,
1627         .read = seq_read,
1628         .write = dbg_vrr_frame_avg_pct_write,
1629         .llseek = seq_lseek,
1630         .release = single_release,
1631 };
1632
1633 static int dbg_vrr_fluct_avg_pct_show(struct seq_file *m, void *unused)
1634 {
1635         struct tegra_vrr *vrr = m->private;
1636
1637         if (!vrr)
1638                 return -EINVAL;
1639
1640         seq_printf(m, "vrr fluct average percent: %d\n", vrr->fluct_avg_pct);
1641
1642         return 0;
1643 }
1644
1645 static ssize_t dbg_vrr_fluct_avg_pct_write(struct file *file,
1646                 const char __user *addr, size_t len, loff_t *pos)
1647 {
1648         struct seq_file *m = file->private_data;
1649         struct tegra_vrr *vrr = m->private;
1650         long   new_pct;
1651         int    ret;
1652
1653         if (!vrr)
1654                 return -EINVAL;
1655
1656         ret = kstrtol_from_user(addr, len, 10, &new_pct);
1657         if (ret < 0)
1658                 return ret;
1659
1660         vrr->fluct_avg_pct = new_pct;
1661
1662         return len;
1663 }
1664
1665 static int dbg_vrr_fluct_avg_pct_open(struct inode *inode, struct file *file)
1666 {
1667         return single_open(file, dbg_vrr_fluct_avg_pct_show, inode->i_private);
1668 }
1669
1670 static const struct file_operations dbg_vrr_fluct_avg_pct_ops = {
1671         .open = dbg_vrr_fluct_avg_pct_open,
1672         .read = seq_read,
1673         .write = dbg_vrr_fluct_avg_pct_write,
1674         .llseek = seq_lseek,
1675         .release = single_release,
1676 };
1677
1678 static int dbg_tegrahw_type_show(struct seq_file *m, void *unused)
1679 {
1680         struct tegra_dc *dc = m->private;
1681
1682         if (WARN_ON(!dc || !dc->out))
1683                 return -EINVAL;
1684
1685         /* All platforms other than real silicon are taken
1686                 as simulation */
1687         seq_printf(m,
1688                 "real_silicon: %d\n",
1689                 tegra_platform_is_silicon());
1690
1691         return 0;
1692 }
1693
1694 static int dbg_tegrahw_type_open(struct inode *inode, struct file *file)
1695 {
1696         return single_open(file, dbg_tegrahw_type_show, inode->i_private);
1697 }
1698
1699 static const struct file_operations dbg_tegrahw_type_ops = {
1700         .open = dbg_tegrahw_type_open,
1701         .read = seq_read,
1702         .llseek = seq_lseek,
1703         .release = single_release,
1704 };
1705 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
1706 {
1707         if (dc->debugdir)
1708                 debugfs_remove_recursive(dc->debugdir);
1709         dc->debugdir = NULL;
1710 }
1711
1712 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
1713 {
1714         struct dentry *retval, *vrrdir;
1715         char   devname[50];
1716
1717         snprintf(devname, sizeof(devname), "tegradc.%d", dc->ctrl_num);
1718         dc->debugdir = debugfs_create_dir(devname, NULL);
1719         if (!dc->debugdir)
1720                 goto remove_out;
1721
1722         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
1723                 &regs_fops);
1724         if (!retval)
1725                 goto remove_out;
1726
1727         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
1728                 &mode_fops);
1729         if (!retval)
1730                 goto remove_out;
1731
1732         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
1733                 &stats_fops);
1734         if (!retval)
1735                 goto remove_out;
1736
1737         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
1738                 &event_inject_fops);
1739         if (!retval)
1740                 goto remove_out;
1741
1742         retval = debugfs_create_file("out_type", S_IRUGO, dc->debugdir, dc,
1743                 &outtype_fops);
1744         if (!retval)
1745                 goto remove_out;
1746
1747         retval = debugfs_create_file("edid", S_IRUGO, dc->debugdir, dc,
1748                 &edid_fops);
1749         if (!retval)
1750                 goto remove_out;
1751
1752         if (dc->out_ops->detect) {
1753                 /* only create the file if hotplug is supported */
1754                 retval = debugfs_create_file("hotplug", S_IRUGO, dc->debugdir,
1755                         dc, &dbg_hotplug_fops);
1756                 if (!retval)
1757                         goto remove_out;
1758         }
1759
1760         vrrdir = debugfs_create_dir("vrr",  dc->debugdir);
1761         if (!vrrdir)
1762                 goto remove_out;
1763
1764         retval = debugfs_create_file("enable", S_IRUGO, vrrdir,
1765                                 dc->out->vrr, &dbg_vrr_enable_ops);
1766         if (!retval)
1767                 goto remove_out;
1768
1769         retval = debugfs_create_file("dcb", S_IRUGO, vrrdir,
1770                                 dc->out->vrr, &dbg_vrr_dcb_ops);
1771         if (!retval)
1772                 goto remove_out;
1773
1774         retval = debugfs_create_file("frame_avg_pct", S_IRUGO, vrrdir,
1775                                 dc->out->vrr, &dbg_vrr_frame_avg_pct_ops);
1776         if (!retval)
1777                 goto remove_out;
1778
1779         retval = debugfs_create_file("fluct_avg_pct", S_IRUGO, vrrdir,
1780                                 dc->out->vrr, &dbg_vrr_fluct_avg_pct_ops);
1781         if (!retval)
1782                 goto remove_out;
1783
1784         retval = debugfs_create_file("tegrahw_type", S_IRUGO, dc->debugdir,
1785                                 dc, &dbg_tegrahw_type_ops);
1786         if (!retval)
1787                 goto remove_out;
1788
1789         return;
1790 remove_out:
1791         dev_err(&dc->ndev->dev, "could not create debugfs\n");
1792         tegra_dc_remove_debugfs(dc);
1793 }
1794
1795 #else /* !CONFIG_DEBUGFS */
1796 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
1797 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
1798 #endif /* CONFIG_DEBUGFS */
1799
1800 s32 tegra_dc_calc_v_front_porch(struct tegra_dc_mode *mode,
1801                                 int desired_fps)
1802 {
1803         int vfp = 0;
1804
1805         if (desired_fps > 0) {
1806                 int line = mode->h_sync_width + mode->h_back_porch +
1807                         mode->h_active + mode->h_front_porch;
1808                 int lines_per_frame = mode->pclk / line / desired_fps;
1809                 vfp = lines_per_frame - mode->v_sync_width -
1810                         mode->v_active - mode->v_back_porch;
1811         }
1812
1813         return vfp;
1814 }
1815
1816 static void tegra_dc_setup_vrr(struct tegra_dc *dc)
1817 {
1818         int lines_per_frame_max, lines_per_frame_min;
1819
1820         struct tegra_dc_mode *m;
1821         struct tegra_vrr *vrr  = dc->out->vrr;
1822
1823         if (!vrr) return;
1824
1825         m = &dc->out->modes[dc->out->n_modes-1];
1826         vrr->v_front_porch = m->v_front_porch;
1827         vrr->v_back_porch = m->v_back_porch;
1828         vrr->pclk = m->pclk;
1829
1830         if (vrr->vrr_min_fps > 0)
1831                 vrr->v_front_porch_max = tegra_dc_calc_v_front_porch(m,
1832                                 vrr->vrr_min_fps);
1833
1834         vrr->vrr_max_fps =
1835                 (s32)div_s64(NSEC_PER_SEC, dc->frametime_ns);
1836
1837         vrr->v_front_porch_min = m->v_front_porch;
1838
1839         vrr->line_width = m->h_sync_width + m->h_back_porch +
1840                         m->h_active + m->h_front_porch;
1841         vrr->lines_per_frame_common = m->v_sync_width +
1842                         m->v_back_porch + m->v_active;
1843         lines_per_frame_max = vrr->lines_per_frame_common +
1844                         vrr->v_front_porch_max;
1845         lines_per_frame_min = vrr->lines_per_frame_common +
1846                         vrr->v_front_porch_min;
1847
1848         if (lines_per_frame_max < 2*lines_per_frame_min) {
1849                 pr_err("max fps is less than 2 times min fps.\n");
1850                 return;
1851         }
1852
1853         vrr->frame_len_max = vrr->line_width * lines_per_frame_max /
1854                                         (m->pclk / 1000000);
1855         vrr->frame_len_min = vrr->line_width * lines_per_frame_min /
1856                                         (m->pclk / 1000000);
1857         vrr->vfp_extend = vrr->v_front_porch_max;
1858         vrr->vfp_shrink = vrr->v_front_porch_min;
1859
1860         vrr->frame_type = 0;
1861         vrr->frame_delta_us = 0;
1862
1863         vrr->max_adj_pct = 50;
1864         vrr->max_flip_pct = 20;
1865         vrr->max_dcb = 20000;
1866         vrr->max_inc_pct = 5;
1867
1868         vrr->dcb = 0;
1869         vrr->frame_avg_pct = 75;
1870         vrr->fluct_avg_pct = 75;
1871         vrr->db_tolerance = 5000;
1872 }
1873
1874 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
1875                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
1876 {
1877         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
1878         u32 reg_val = 0;
1879
1880         if (tegra_platform_is_linsim())
1881                 return 0;
1882
1883         do {
1884                 usleep_range(poll_interval_us, poll_interval_us << 1);
1885                 reg_val = tegra_dc_readl(dc, reg);
1886         } while (((reg_val & mask) != exp_val) &&
1887                 time_after(timeout_jf, jiffies));
1888
1889         if ((reg_val & mask) == exp_val)
1890                 return 0;       /* success */
1891         dev_err(&dc->ndev->dev,
1892                 "dc_poll_register 0x%x: timeout\n", reg);
1893         return jiffies - timeout_jf + 1;
1894 }
1895
1896
1897 void tegra_dc_enable_general_act(struct tegra_dc *dc)
1898 {
1899         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1900
1901         if (tegra_dc_poll_register(dc, DC_CMD_STATE_CONTROL,
1902                 GENERAL_ACT_REQ, 0, 1,
1903                 TEGRA_DC_POLL_TIMEOUT_MS))
1904                 dev_err(&dc->ndev->dev,
1905                         "dc timeout waiting for DC to stop\n");
1906 }
1907
1908
1909 static int tegra_dc_set_next(struct tegra_dc *dc)
1910 {
1911         int i;
1912         int ret = -EBUSY;
1913
1914         mutex_lock(&tegra_dc_lock);
1915
1916         for (i = 0; i < TEGRA_MAX_DC; i++) {
1917                 if (tegra_dcs[i] == NULL) {
1918                         tegra_dcs[i] = dc;
1919                         ret = i;
1920                         break;
1921                 }
1922         }
1923
1924         mutex_unlock(&tegra_dc_lock);
1925
1926         return ret;
1927 }
1928
1929 static int tegra_dc_set_idx(struct tegra_dc *dc, int index)
1930 {
1931         int ret = 0;
1932
1933         mutex_lock(&tegra_dc_lock);
1934         if (index >= TEGRA_MAX_DC) {
1935                 ret = -EINVAL;
1936                 goto out;
1937         }
1938
1939         if (dc != NULL && tegra_dcs[index] != NULL) {
1940                 ret = -EBUSY;
1941                 goto out;
1942         }
1943
1944         tegra_dcs[index] = dc;
1945
1946 out:
1947         mutex_unlock(&tegra_dc_lock);
1948
1949         return ret;
1950 }
1951
1952 /*
1953  * If index == -1, set dc at next available index. This is to be called only
1954  * when registering dc in DT case. For non DT case & when removing the device
1955  * (dc == NULL), index should be accordingly.
1956  */
1957 static int tegra_dc_set(struct tegra_dc *dc, int index)
1958 {
1959         if ((index == -1) && (dc != NULL)) /* DT register case */
1960                 return tegra_dc_set_next(dc);
1961         else /* non DT, unregister case */
1962                 return tegra_dc_set_idx(dc, index);
1963 }
1964
1965 unsigned int tegra_dc_has_multiple_dc(void)
1966 {
1967         unsigned int idx;
1968         unsigned int cnt = 0;
1969         struct tegra_dc *dc;
1970
1971         mutex_lock(&tegra_dc_lock);
1972         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
1973                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
1974         mutex_unlock(&tegra_dc_lock);
1975
1976         return (cnt > 1);
1977 }
1978
1979 /* get the stride size of a window.
1980  * return: stride size in bytes for window win. or 0 if unavailble. */
1981 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1982 {
1983         u32 stride;
1984
1985         if (!dc->enabled)
1986                 return 0;
1987         BUG_ON(win > DC_N_WINDOWS);
1988         mutex_lock(&dc->lock);
1989         tegra_dc_get(dc);
1990         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1991                 DC_CMD_DISPLAY_WINDOW_HEADER);
1992 #ifdef CONFIG_TEGRA_NVDISPLAY
1993         stride = tegra_nvdisp_get_linestride(dc, win);
1994 #else
1995         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1996 #endif
1997         tegra_dc_put(dc);
1998         mutex_unlock(&dc->lock);
1999         return GET_LINE_STRIDE(stride);
2000 }
2001 EXPORT_SYMBOL(tegra_dc_get_stride);
2002
2003 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
2004 {
2005         if (idx < TEGRA_MAX_DC)
2006                 return tegra_dcs[idx];
2007         else
2008                 return NULL;
2009 }
2010 EXPORT_SYMBOL(tegra_dc_get_dc);
2011
2012 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
2013 {
2014         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
2015                 return NULL;
2016
2017 #ifdef CONFIG_TEGRA_NVDISPLAY
2018         return &tegra_dc_windows[win];
2019 #else
2020         return &dc->windows[win];
2021 #endif
2022 }
2023 EXPORT_SYMBOL(tegra_dc_get_window);
2024
2025 bool tegra_dc_get_connected(struct tegra_dc *dc)
2026 {
2027         return dc->connected;
2028 }
2029 EXPORT_SYMBOL(tegra_dc_get_connected);
2030
2031 bool tegra_dc_hpd(struct tegra_dc *dc)
2032 {
2033         int hpd = false;
2034         int hotplug_state;
2035
2036         if (WARN_ON(!dc || !dc->out))
2037                 return false;
2038
2039         rmb();
2040         hotplug_state = dc->out->hotplug_state;
2041
2042         if (hotplug_state != TEGRA_HPD_STATE_NORMAL) {
2043                 if (hotplug_state == TEGRA_HPD_STATE_FORCE_ASSERT)
2044                         return true;
2045                 if (hotplug_state == TEGRA_HPD_STATE_FORCE_DEASSERT)
2046                         return false;
2047         }
2048
2049         if (!tegra_dc_hotplug_supported(dc))
2050                 return true;
2051
2052         if (dc->out_ops && dc->out_ops->hpd_state)
2053                 hpd = dc->out_ops->hpd_state(dc);
2054
2055         if (dc->out->hotplug_report)
2056                 dc->out->hotplug_report(hpd);
2057
2058         return hpd;
2059 }
2060 EXPORT_SYMBOL(tegra_dc_hpd);
2061
2062 #ifndef CONFIG_TEGRA_NVDISPLAY
2063 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
2064 {
2065         unsigned i;
2066         unsigned v0 = 128;
2067         unsigned v1 = 0;
2068
2069         /* linear horizontal and vertical filters */
2070         for (i = 0; i < 16; i++) {
2071                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
2072                                 DC_WIN_H_FILTER_P(i));
2073
2074                 tegra_dc_writel(dc, v0,
2075                                 DC_WIN_V_FILTER_P(i));
2076                 v0 -= 8;
2077                 v1 += 8;
2078         }
2079 }
2080 #endif
2081
2082 static int _tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
2083 {
2084         tegra_dc_io_start(dc);
2085         if (enable) {
2086                 atomic_inc(&dc->frame_end_ref);
2087                 tegra_dc_unmask_interrupt(dc, FRAME_END_INT);
2088         } else if (!atomic_dec_return(&dc->frame_end_ref))
2089                 tegra_dc_mask_interrupt(dc, FRAME_END_INT);
2090         tegra_dc_io_end(dc);
2091
2092         return 0;
2093 }
2094
2095 #if defined(CONFIG_TEGRA_DC_CMU) || defined(CONFIG_TEGRA_DC_CMU_V2)
2096 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
2097 {
2098         if (dc->out->type == TEGRA_DC_OUT_FAKE_DP ||
2099                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIA ||
2100                 dc->out->type == TEGRA_DC_OUT_FAKE_DSIB ||
2101                 dc->out->type == TEGRA_DC_OUT_FAKE_DSI_GANGED ||
2102                 dc->out->type == TEGRA_DC_OUT_NULL)
2103                 return &default_cmu;
2104         if (dc->pdata->cmu && !dc->pdata->default_clr_space)
2105                 return dc->pdata->cmu;
2106         else if (dc->pdata->cmu_adbRGB && dc->pdata->default_clr_space)
2107                 return dc->pdata->cmu_adbRGB;
2108         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
2109                 return &default_limited_cmu;
2110         else
2111                 return &default_cmu;
2112 }
2113
2114 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
2115 {
2116         dc->cmu_enabled = cmu_enable;
2117 #if defined(CONFIG_TEGRA_NVDISPLAY)
2118         tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
2119         tegra_nvdisp_update_cmu(dc, &dc->cmu);
2120 #else
2121         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2122 #endif
2123 }
2124 EXPORT_SYMBOL(tegra_dc_cmu_enable);
2125 #else
2126 #define tegra_dc_cmu_enable(dc, cmu_enable)
2127 #endif
2128
2129 #ifdef CONFIG_TEGRA_DC_CMU
2130 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
2131                                 struct tegra_dc_cmu *src_cmu)
2132 {
2133         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
2134                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
2135         dc->cmu_dirty = true;
2136 }
2137
2138 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2139 {
2140         u32 val;
2141         u32 i;
2142
2143         for (i = 0; i < 256; i++) {
2144                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
2145                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
2146         }
2147
2148         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
2149         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
2150         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
2151         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
2152         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
2153         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
2154         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
2155         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
2156         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
2157
2158         for (i = 0; i < 960; i++) {
2159                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
2160                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
2161         }
2162
2163         dc->cmu_dirty = false;
2164 }
2165
2166 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2167 {
2168         u32 val;
2169
2170         if (!dc->cmu_enabled)
2171                 return;
2172
2173         tegra_dc_cache_cmu(dc, cmu);
2174
2175         if (dc->cmu_dirty) {
2176                 /* Disable CMU to avoid programming it while it is in use */
2177                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
2178                 if (val & CMU_ENABLE) {
2179                         val &= ~CMU_ENABLE;
2180                         tegra_dc_writel(dc, val,
2181                                         DC_DISP_DISP_COLOR_CONTROL);
2182                         val = GENERAL_ACT_REQ;
2183                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
2184                         /*TODO: Sync up with vsync */
2185                         mdelay(20);
2186                 }
2187                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
2188                         dc->cmu_dirty);
2189
2190                 tegra_dc_set_cmu(dc, &dc->cmu);
2191         }
2192 }
2193
2194 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2195 {
2196         mutex_lock(&dc->lock);
2197         if (!dc->enabled) {
2198                 mutex_unlock(&dc->lock);
2199                 return 0;
2200         }
2201
2202         tegra_dc_get(dc);
2203
2204         _tegra_dc_update_cmu(dc, cmu);
2205         tegra_dc_set_color_control(dc);
2206         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2207
2208         tegra_dc_put(dc);
2209         mutex_unlock(&dc->lock);
2210
2211         return 0;
2212 }
2213 EXPORT_SYMBOL(tegra_dc_update_cmu);
2214
2215 int tegra_dc_set_hdr(struct tegra_dc *dc, struct tegra_dc_hdr *hdr,
2216                                                 bool cache_dirty)
2217 {
2218         int ret;
2219
2220         mutex_lock(&dc->lock);
2221
2222         if (!dc->enabled) {
2223                 mutex_unlock(&dc->lock);
2224                 return 0;
2225         }
2226         if (cache_dirty) {
2227                 dc->hdr.eotf = hdr->eotf;
2228                 dc->hdr.static_metadata_id = hdr->static_metadata_id;
2229                 memcpy(dc->hdr.static_metadata, hdr->static_metadata,
2230                                         sizeof(dc->hdr.static_metadata));
2231         } else if (dc->hdr.enabled == hdr->enabled) {
2232                 mutex_unlock(&dc->lock);
2233                 return 0;
2234         }
2235         dc->hdr.enabled = hdr->enabled;
2236         dc->hdr_cache_dirty = true;
2237         if (!dc->hdr.enabled)
2238                 memset(&dc->hdr, 0, sizeof(dc->hdr));
2239         ret = _tegra_dc_config_frame_end_intr(dc, true);
2240
2241         mutex_unlock(&dc->lock);
2242
2243         return ret;
2244 }
2245 EXPORT_SYMBOL(tegra_dc_set_hdr);
2246
2247 static int _tegra_dc_update_cmu_aligned(struct tegra_dc *dc,
2248                                 struct tegra_dc_cmu *cmu,
2249                                 bool force)
2250 {
2251         memcpy(&dc->cmu_shadow, cmu, sizeof(dc->cmu));
2252         dc->cmu_shadow_dirty = true;
2253         dc->cmu_shadow_force_update = dc->cmu_shadow_force_update || force;
2254         _tegra_dc_config_frame_end_intr(dc, true);
2255
2256         return 0;
2257 }
2258
2259 int tegra_dc_update_cmu_aligned(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
2260 {
2261         int ret;
2262
2263         mutex_lock(&dc->lock);
2264         if (!dc->enabled) {
2265                 mutex_unlock(&dc->lock);
2266                 return 0;
2267         }
2268         ret = _tegra_dc_update_cmu_aligned(dc, cmu, false);
2269         mutex_unlock(&dc->lock);
2270
2271         return ret;
2272 }
2273
2274 EXPORT_SYMBOL(tegra_dc_update_cmu_aligned);
2275 #else
2276 #define tegra_dc_cache_cmu(dc, src_cmu)
2277 #define tegra_dc_set_cmu(dc, cmu)
2278 #define tegra_dc_update_cmu(dc, cmu)
2279 #define tegra_dc_update_cmu_aligned(dc, cmu)
2280 #endif
2281
2282 /* disable_irq() blocks until handler completes, calling this function while
2283  * holding dc->lock can deadlock. */
2284 static inline void disable_dc_irq(const struct tegra_dc *dc)
2285 {
2286         disable_irq(dc->irq);
2287 }
2288
2289 u32 tegra_dc_get_syncpt_id(struct tegra_dc *dc, int i)
2290 {
2291         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2292         BUG_ON(!win);
2293         return win->syncpt.id;
2294 }
2295 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
2296
2297 static u32 tegra_dc_incr_syncpt_max_locked(struct tegra_dc *dc, int i)
2298 {
2299         u32 max;
2300         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2301
2302         BUG_ON(!win);
2303         max = nvhost_syncpt_incr_max_ext(dc->ndev,
2304                 win->syncpt.id, ((dc->enabled) ? 1 : 0));
2305         win->syncpt.max = max;
2306
2307         return max;
2308 }
2309
2310 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
2311 {
2312         u32 max;
2313
2314         mutex_lock(&dc->lock);
2315         tegra_dc_get(dc);
2316         max = tegra_dc_incr_syncpt_max_locked(dc, i);
2317         tegra_dc_put(dc);
2318         mutex_unlock(&dc->lock);
2319
2320         return max;
2321 }
2322
2323 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
2324 {
2325         struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
2326
2327         BUG_ON(!win);
2328         mutex_lock(&dc->lock);
2329
2330         tegra_dc_get(dc);
2331         while (win->syncpt.min < val) {
2332                 win->syncpt.min++;
2333                 nvhost_syncpt_cpu_incr_ext(dc->ndev, win->syncpt.id);
2334                 }
2335         tegra_dc_put(dc);
2336         mutex_unlock(&dc->lock);
2337 }
2338
2339 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
2340 {
2341         struct nvhost_ctrl_sync_fence_info syncpt;
2342         u32 id = tegra_dc_get_syncpt_id(dc, i);
2343
2344         syncpt.id = id;
2345         syncpt.thresh = val;
2346         return nvhost_sync_create_fence(
2347                         to_platform_device(dc->ndev->dev.parent),
2348                         &syncpt, 1, dev_name(&dc->ndev->dev));
2349 }
2350
2351 void
2352 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
2353 {
2354         unsigned int ctrl;
2355         unsigned long out_sel;
2356         unsigned long cmd_state;
2357
2358         mutex_lock(&dc->lock);
2359         if (!dc->enabled) {
2360                 mutex_unlock(&dc->lock);
2361                 return;
2362         }
2363
2364         tegra_dc_get(dc);
2365
2366         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
2367                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
2368                 cfg->clk_select);
2369
2370         /* The new value should be effected immediately */
2371         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
2372         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
2373
2374         switch (cfg->which_pwm) {
2375         case TEGRA_PWM_PM0:
2376                 /* Select the LM0 on PM0 */
2377                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2378                 out_sel &= ~(7 << 0);
2379                 out_sel |= (3 << 0);
2380                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2381                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
2382                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
2383                 break;
2384         case TEGRA_PWM_PM1:
2385                 /* Select the LM1 on PM1 */
2386                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
2387                 out_sel &= ~(7 << 4);
2388                 out_sel |= (3 << 4);
2389                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
2390                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
2391                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
2392                 break;
2393         default:
2394                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
2395                 break;
2396         }
2397         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
2398         tegra_dc_put(dc);
2399         mutex_unlock(&dc->lock);
2400 }
2401 EXPORT_SYMBOL(tegra_dc_config_pwm);
2402
2403 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
2404                                 const struct tegra_dc_out_pin *pins,
2405                                 const unsigned int n_pins)
2406 {
2407         unsigned int i;
2408
2409         int name;
2410         int pol;
2411
2412         u32 pol1, pol3;
2413
2414         u32 set1, unset1;
2415         u32 set3, unset3;
2416
2417         set1 = set3 = unset1 = unset3 = 0;
2418
2419         for (i = 0; i < n_pins; i++) {
2420                 name = (pins + i)->name;
2421                 pol  = (pins + i)->pol;
2422
2423                 /* set polarity by name */
2424                 switch (name) {
2425                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
2426                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2427                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
2428                         else
2429                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
2430                         break;
2431                 case TEGRA_DC_OUT_PIN_H_SYNC:
2432                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2433                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
2434                         else
2435                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
2436                         break;
2437                 case TEGRA_DC_OUT_PIN_V_SYNC:
2438                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2439                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
2440                         else
2441                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
2442                         break;
2443                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
2444                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
2445                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
2446                         else
2447                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
2448                         break;
2449                 default:
2450                         printk("Invalid argument in function %s\n",
2451                                __FUNCTION__);
2452                         break;
2453                 }
2454         }
2455
2456         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
2457         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
2458
2459         pol1 |= set1;
2460         pol1 &= ~unset1;
2461
2462         pol3 |= set3;
2463         pol3 &= ~unset3;
2464
2465         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
2466         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
2467 }
2468
2469 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
2470 {
2471         unsigned long refresh;
2472
2473         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2474                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2475
2476                 /* For seamless HDMI, read mode parameters from bootloader
2477                  * set DC configuration
2478                  */
2479                 u32 val = 0;
2480                 struct tegra_dc_mode *mode = &override_disp_mode[dc->out->type];
2481 #ifdef CONFIG_TEGRA_NVDISPLAY
2482                 struct clk *parent_clk = tegra_disp_clk_get(&dc->ndev->dev,
2483                                 dc->out->parent_clk ? : "plld2");
2484 #else
2485                 struct clk *parent_clk = clk_get_sys(NULL,
2486                                 dc->out->parent_clk ? : "pll_d2");
2487 #endif
2488                 memset(mode, 0, sizeof(struct tegra_dc_mode));
2489                 mode->pclk = clk_get_rate(parent_clk);
2490                 mode->rated_pclk = 0;
2491
2492                 tegra_dc_get(dc);
2493                 val = tegra_dc_readl(dc, DC_DISP_REF_TO_SYNC);
2494                 mode->h_ref_to_sync = val & 0xffff;
2495                 mode->v_ref_to_sync = (val >> 16) & 0xffff;
2496
2497                 val = tegra_dc_readl(dc, DC_DISP_SYNC_WIDTH);
2498                 mode->h_sync_width = val & 0xffff;
2499                 mode->v_sync_width = (val >> 16) & 0xffff;
2500
2501                 val = tegra_dc_readl(dc, DC_DISP_BACK_PORCH);
2502                 mode->h_back_porch = val & 0xffff;
2503                 mode->v_back_porch = (val >> 16) & 0xffff;
2504
2505                 val = tegra_dc_readl(dc, DC_DISP_FRONT_PORCH);
2506                 mode->h_front_porch = val & 0xffff;
2507                 mode->v_front_porch = (val >> 16) & 0xffff;
2508
2509                 val = tegra_dc_readl(dc, DC_DISP_DISP_ACTIVE);
2510                 mode->h_active = val & 0xffff;
2511                 mode->v_active = (val >> 16) & 0xffff;
2512
2513                 /* Check the freq setup by the BL, 59.94 or 60Hz
2514                  * If 59.94, vmode needs to be FB_VMODE_1000DIV1001
2515                  * for seamless
2516                  */
2517                 refresh = tegra_dc_calc_refresh(mode);
2518                 if (refresh % 1000)
2519                         mode->vmode = FB_VMODE_1000DIV1001;
2520
2521                 tegra_dc_put(dc);
2522         }
2523
2524         if (dc->out->type == TEGRA_DC_OUT_RGB  ||
2525                 dc->out->type == TEGRA_DC_OUT_HDMI ||
2526                 dc->out->type == TEGRA_DC_OUT_DSI  ||
2527                 dc->out->type == TEGRA_DC_OUT_NULL)
2528                 return override_disp_mode[dc->out->type].pclk ?
2529                         &override_disp_mode[dc->out->type] : NULL;
2530         else
2531                 return NULL;
2532 }
2533
2534 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
2535 {
2536         struct tegra_dc_mode *mode;
2537         int err = 0;
2538
2539         dc->out = out;
2540
2541         if (dc->out->type == TEGRA_DC_OUT_HDMI &&
2542                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2543                 /*
2544                  * Bootloader enables clk and host1x in seamless
2545                  * usecase. Below extra reference accounts for it
2546                  */
2547                 tegra_dc_get(dc);
2548         }
2549 /*
2550  * This config enables seamless feature only for
2551  * android usecase as a WAR for improper DSI initialization
2552  * in bootloader for L4T usecase.
2553  * Bug 200122858
2554  */
2555 #ifdef CONFIG_ANDROID
2556         /*
2557          * Seamless supporting panels can work in seamless mode
2558          * only if BL initializes DC/DSI. If not, panel should
2559          * go with complete initialization.
2560          */
2561         if (dc->out->type == TEGRA_DC_OUT_DSI &&
2562                         !tegra_is_bl_display_initialized(dc->ndev->id)) {
2563                 dc->initialized = false;
2564         } else if (dc->out->type == TEGRA_DC_OUT_DSI &&
2565                         tegra_is_bl_display_initialized(dc->ndev->id)) {
2566                 dc->initialized = true;
2567         }
2568 #endif
2569         mode = tegra_dc_get_override_mode(dc);
2570
2571         if (mode) {
2572                 tegra_dc_set_mode(dc, mode);
2573
2574                 /*
2575                  * Bootloader should and should only pass disp_params if
2576                  * it has initialized display controller.  Whenever we see
2577                  * override modes, we should skip things cause display resets.
2578                  */
2579                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
2580                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
2581                                 dc->mode.h_active, dc->mode.v_active,
2582                                 dc->out->h_size, dc->out->v_size,
2583                                 dc->mode.pclk);
2584                 dc->initialized = true;
2585         } else if (out->n_modes > 0) {
2586                 /* For VRR panels, default mode is first in the list,
2587                  * and native panel mode is the last.
2588                  * Initialization must occur using the native panel mode. */
2589                 if (dc->out->vrr) {
2590                         tegra_dc_set_mode(dc,
2591                                 &dc->out->modes[dc->out->n_modes-1]);
2592                         tegra_dc_setup_vrr(dc);
2593                 } else
2594                         tegra_dc_set_mode(dc, &dc->out->modes[0]);
2595         }
2596
2597         switch (out->type) {
2598         case TEGRA_DC_OUT_RGB:
2599                 dc->out_ops = &tegra_dc_rgb_ops;
2600                 break;
2601
2602         case TEGRA_DC_OUT_HDMI:
2603 #if     defined(CONFIG_TEGRA_HDMI2_0)
2604                 dc->out_ops = &tegra_dc_hdmi2_0_ops;
2605 #elif defined(CONFIG_TEGRA_HDMI)
2606                 dc->out_ops = &tegra_dc_hdmi_ops;
2607 #endif
2608 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2609                 if (tegra_bonded_out_dev(BOND_OUT_SOR1)) {
2610                         dev_info(&dc->ndev->dev,
2611                                 "SOR1 instance is bonded out\n");
2612                         dc->out_ops = NULL;
2613                         err = -ENODEV;
2614                 }
2615 #endif
2616                 break;
2617
2618         case TEGRA_DC_OUT_DSI:
2619         case TEGRA_DC_OUT_FAKE_DSIA:
2620         case TEGRA_DC_OUT_FAKE_DSIB:
2621         case TEGRA_DC_OUT_FAKE_DSI_GANGED:
2622                 dc->out_ops = &tegra_dc_dsi_ops;
2623 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
2624                 if (tegra_bonded_out_dev(BOND_OUT_DSI) ||
2625                         tegra_bonded_out_dev(BOND_OUT_DSIB)) {
2626                         dev_info(&dc->ndev->dev,
2627                                 "DSI instance is bonded out\n");
2628                         dc->out_ops = NULL;
2629                         err = -ENODEV;
2630                 }
2631 #endif
2632                 break;
2633
2634 #ifdef CONFIG_TEGRA_DP
2635         case TEGRA_DC_OUT_FAKE_DP:
2636         case TEGRA_DC_OUT_DP:
2637                 dc->out_ops = &tegra_dc_dp_ops;
2638                 break;
2639 #ifdef CONFIG_TEGRA_NVSR
2640         case TEGRA_DC_OUT_NVSR_DP:
2641                 dc->out_ops = &tegra_dc_nvsr_ops;
2642                 break;
2643 #endif
2644 #endif
2645 #ifdef CONFIG_TEGRA_LVDS
2646         case TEGRA_DC_OUT_LVDS:
2647                 dc->out_ops = &tegra_dc_lvds_ops;
2648                 break;
2649 #endif
2650 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
2651         case TEGRA_DC_OUT_NULL:
2652                 dc->out_ops = &tegra_dc_null_ops;
2653                 break;
2654 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
2655
2656         default:
2657                 dc->out_ops = NULL;
2658                 break;
2659         }
2660
2661 #ifdef CONFIG_TEGRA_DC_CMU
2662         tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
2663 #endif
2664
2665         if (dc->out_ops && dc->out_ops->init) {
2666                 err = dc->out_ops->init(dc);
2667                 if (err < 0) {
2668                         dc->out = NULL;
2669                         dc->out_ops = NULL;
2670                         dev_err(&dc->ndev->dev,
2671                                 "Error: out->type:%d out_ops->init() failed\n",
2672                                 out->type);
2673                         return err;
2674                 }
2675         }
2676
2677         return err;
2678 }
2679
2680 int tegra_dc_get_head(const struct tegra_dc *dc)
2681 {
2682         if (dc)
2683                 return dc->ctrl_num;
2684         return -EINVAL;
2685 }
2686
2687 /* returns on error: -EINVAL
2688  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, ... */
2689 int tegra_dc_get_out(const struct tegra_dc *dc)
2690 {
2691         if (dc && dc->out)
2692                 return dc->out->type;
2693         return -EINVAL;
2694 }
2695
2696 bool tegra_dc_is_ext_dp_panel(const struct tegra_dc *dc)
2697 {
2698         if (dc && dc->out)
2699                 return dc->out->is_ext_dp_panel;
2700         return false;
2701 }
2702
2703 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
2704 {
2705         unsigned height = 0;
2706
2707         if (dc->out) {
2708                 if (dc->out->height)
2709                         height = dc->out->height;
2710                 else if (dc->out->h_size && dc->out->v_size)
2711                         height = dc->out->v_size;
2712         }
2713
2714         return height;
2715 }
2716 EXPORT_SYMBOL(tegra_dc_get_out_height);
2717
2718 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
2719 {
2720         unsigned width = 0;
2721
2722         if (dc->out) {
2723                 if (dc->out->width)
2724                         width = dc->out->width;
2725                 else if (dc->out->h_size && dc->out->v_size)
2726                         width = dc->out->h_size;
2727         }
2728
2729         return width;
2730 }
2731 EXPORT_SYMBOL(tegra_dc_get_out_width);
2732
2733 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
2734 {
2735         if (dc && dc->out)
2736                 return dc->out->max_pixclock;
2737         else
2738                 return 0;
2739 }
2740 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
2741
2742 void tegra_dc_enable_crc(struct tegra_dc *dc)
2743 {
2744         u32 val;
2745
2746         mutex_lock(&dc->lock);
2747         tegra_dc_get(dc);
2748
2749         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
2750                 CRC_ENABLE_ENABLE;
2751         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
2752         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2753         tegra_dc_put(dc);
2754         mutex_unlock(&dc->lock);
2755
2756         /* Register a client of frame_end interrupt */
2757         tegra_dc_config_frame_end_intr(dc, true);
2758 }
2759
2760 void tegra_dc_disable_crc(struct tegra_dc *dc)
2761 {
2762         /* Unregister a client of frame_end interrupt */
2763         tegra_dc_config_frame_end_intr(dc, false);
2764
2765         mutex_lock(&dc->lock);
2766         tegra_dc_get(dc);
2767         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
2768         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2769
2770         tegra_dc_put(dc);
2771         mutex_unlock(&dc->lock);
2772 }
2773
2774 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
2775 {
2776         int crc = 0;
2777
2778         if (!dc) {
2779                 pr_err("Failed to get dc: NULL parameter.\n");
2780                 goto crc_error;
2781         }
2782
2783         /* If gated quitely return */
2784         if (!tegra_dc_is_powered(dc))
2785                 return 0;
2786
2787         INIT_COMPLETION(dc->crc_complete);
2788         if (dc->crc_pending &&
2789             wait_for_completion_interruptible(&dc->crc_complete)) {
2790                 pr_err("CRC read interrupted.\n");
2791                 goto crc_error;
2792         }
2793
2794         mutex_lock(&dc->lock);
2795         tegra_dc_get(dc);
2796         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
2797         tegra_dc_put(dc);
2798         mutex_unlock(&dc->lock);
2799 crc_error:
2800         return crc;
2801 }
2802 EXPORT_SYMBOL(tegra_dc_read_checksum_latched);
2803
2804 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
2805 {
2806         u32 val;
2807
2808         if (tegra_platform_is_linsim())
2809                 return false;
2810
2811         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
2812         if (val & (win_act_req_mask))
2813                 return true;
2814
2815         return false;
2816 }
2817
2818 static inline void enable_dc_irq(const struct tegra_dc *dc)
2819 {
2820         if (tegra_platform_is_fpga())
2821                 /* Always disable DC interrupts on FPGA. */
2822                 disable_irq(dc->irq);
2823         else
2824                 enable_irq(dc->irq);
2825 }
2826
2827 /* assumes dc->lock is already taken. */
2828 static void _tegra_dc_vsync_enable(struct tegra_dc *dc)
2829 {
2830         int vsync_irq;
2831
2832         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2833                 vsync_irq = MSF_INT;
2834         else
2835                 vsync_irq = V_BLANK_INT;
2836         tegra_dc_hold_dc_out(dc);
2837         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
2838         tegra_dc_unmask_interrupt(dc, vsync_irq);
2839 }
2840
2841 int tegra_dc_vsync_enable(struct tegra_dc *dc)
2842 {
2843         mutex_lock(&dc->lock);
2844         if (dc->enabled) {
2845                 _tegra_dc_vsync_enable(dc);
2846                 mutex_unlock(&dc->lock);
2847                 return 0;
2848         }
2849         mutex_unlock(&dc->lock);
2850         return 1;
2851 }
2852
2853 /* assumes dc->lock is already taken. */
2854 static void _tegra_dc_vsync_disable(struct tegra_dc *dc)
2855 {
2856         int vsync_irq;
2857
2858         if (dc->out->type == TEGRA_DC_OUT_DSI)
2859                 vsync_irq = MSF_INT;
2860         else
2861                 vsync_irq = V_BLANK_INT;
2862         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
2863         if (!dc->vblank_ref_count)
2864                 tegra_dc_mask_interrupt(dc, vsync_irq);
2865         tegra_dc_release_dc_out(dc);
2866 }
2867
2868 void tegra_dc_vsync_disable(struct tegra_dc *dc)
2869 {
2870         mutex_lock(&dc->lock);
2871         _tegra_dc_vsync_disable(dc);
2872         mutex_unlock(&dc->lock);
2873 }
2874
2875 bool tegra_dc_has_vsync(struct tegra_dc *dc)
2876 {
2877         return true;
2878 }
2879
2880 /* assumes dc->lock is already taken. */
2881 static void _tegra_dc_user_vsync_enable(struct tegra_dc *dc, bool enable)
2882 {
2883         if (enable) {
2884                 dc->out->user_needs_vblank++;
2885                 init_completion(&dc->out->user_vblank_comp);
2886                 _tegra_dc_vsync_enable(dc);
2887         } else {
2888                 _tegra_dc_vsync_disable(dc);
2889                 if (dc->out->user_needs_vblank > 0)
2890                         dc->out->user_needs_vblank--;
2891         }
2892 }
2893
2894 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
2895 {
2896         unsigned long timeout_ms;
2897         unsigned long refresh; /* in 1000th Hz */
2898         int ret;
2899
2900         mutex_lock(&dc->lp_lock);
2901         mutex_lock(&dc->lock);
2902         if (!dc->enabled) {
2903                 ret = -ENOTTY;
2904                 goto out;
2905         }
2906         refresh = tegra_dc_calc_refresh(&dc->mode);
2907         /* time out if waiting took more than 2 frames */
2908         timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
2909         _tegra_dc_user_vsync_enable(dc, true);
2910         mutex_unlock(&dc->lock);
2911         ret = wait_for_completion_interruptible_timeout(
2912                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
2913         mutex_lock(&dc->lock);
2914         _tegra_dc_user_vsync_enable(dc, false);
2915 out:
2916         mutex_unlock(&dc->lock);
2917         mutex_unlock(&dc->lp_lock);
2918         return ret;
2919 }
2920
2921 int _tegra_dc_wait_for_frame_end(struct tegra_dc *dc,
2922         u32 timeout_ms)
2923 {
2924         int ret;
2925
2926         INIT_COMPLETION(dc->frame_end_complete);
2927
2928         tegra_dc_get(dc);
2929
2930         tegra_dc_flush_interrupt(dc, FRAME_END_INT);
2931         /* unmask frame end interrupt */
2932         _tegra_dc_config_frame_end_intr(dc, true);
2933
2934         ret = wait_for_completion_interruptible_timeout(
2935                         &dc->frame_end_complete,
2936                         msecs_to_jiffies(timeout_ms));
2937
2938         _tegra_dc_config_frame_end_intr(dc, false);
2939
2940         tegra_dc_put(dc);
2941
2942         return ret;
2943 }
2944
2945 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
2946 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
2947 {
2948         /* Do the actual brightness update outside of the mutex dc->lock */
2949         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
2950                 dc->out->sd_settings->bl_device_name) {
2951                 char *bl_device_name =
2952                         dc->out->sd_settings->bl_device_name;
2953                 dc->out->sd_settings->bl_device =
2954                         get_backlight_device_by_name(bl_device_name);
2955         }
2956
2957         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
2958                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
2959                 backlight_update_status(bl);
2960         }
2961 }
2962 #endif
2963
2964 void tegra_dc_set_act_vfp(struct tegra_dc *dc, int vfp)
2965 {
2966         WARN_ON(!mutex_is_locked(&dc->lock));
2967         WARN_ON(vfp < dc->mode.v_ref_to_sync + 1);
2968
2969         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
2970                         DC_CMD_STATE_ACCESS);
2971         tegra_dc_writel(dc, dc->mode.h_front_porch |
2972                         (vfp << 16), DC_DISP_FRONT_PORCH);
2973         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
2974                         DC_CMD_STATE_ACCESS);
2975 }
2976
2977 static void tegra_dc_vrr_extend_vfp(struct tegra_dc *dc)
2978 {
2979         struct tegra_vrr *vrr  = dc->out->vrr;
2980
2981         if (!vrr || !vrr->enable)
2982                 return;
2983
2984         tegra_dc_set_act_vfp(dc, MAX_VRR_V_FRONT_PORCH);
2985 }
2986
2987 int tegra_dc_get_v_count(struct tegra_dc *dc)
2988 {
2989         u32     value;
2990
2991         value = tegra_dc_readl(dc, DC_DISP_DISPLAY_DBG_TIMING);
2992         return (value & DBG_V_COUNT_MASK) >> DBG_V_COUNT_SHIFT;
2993 }
2994
2995 static void tegra_dc_vrr_get_ts(struct tegra_dc *dc)
2996 {
2997         struct timespec time_now;
2998         struct tegra_vrr *vrr  = dc->out->vrr;
2999
3000         if (!vrr || (!vrr->enable && !vrr->lastenable))
3001                 return;
3002
3003         getnstimeofday(&time_now);
3004         vrr->fe_time_us = (s64)time_now.tv_sec * 1000000 +
3005                                 time_now.tv_nsec / 1000;
3006         vrr->v_count = tegra_dc_get_v_count(dc);
3007 }
3008
3009 static void tegra_dc_vrr_sec(struct tegra_dc *dc)
3010 {
3011         struct tegra_vrr *vrr  = dc->out->vrr;
3012
3013         if (!vrr || (!vrr->enable && !vrr->fe_intr_req))
3014                 return;
3015
3016         /* Decrement frame end interrupt refcount previously
3017            requested by secure library */
3018         if (vrr->fe_intr_req) {
3019                 _tegra_dc_config_frame_end_intr(dc, false);
3020                 vrr->fe_intr_req = 0;
3021         }
3022
3023 #ifdef CONFIG_TRUSTED_LITTLE_KERNEL
3024         te_vrr_sec();
3025 #endif
3026         /* Increment frame end interrupt refcount requested
3027            by secure library */
3028         if (vrr->fe_intr_req)
3029                 _tegra_dc_config_frame_end_intr(dc, true);
3030 }
3031
3032 static void tegra_dc_vblank(struct work_struct *work)
3033 {
3034         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
3035 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
3036         bool nvsd_updated = false;
3037 #endif /* CONFIG_TEGRA_NVSD */
3038
3039         mutex_lock(&dc->lock);
3040
3041         if (!dc->enabled) {
3042                 mutex_unlock(&dc->lock);
3043                 return;
3044         }
3045
3046         tegra_dc_get(dc);
3047
3048         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
3049         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
3050                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
3051
3052 #ifdef CONFIG_TEGRA_NVDISPLAY
3053         if (dc->out->sd_settings) {
3054                 if (dc->out->sd_settings->enable) {
3055                         if ((dc->out->sd_settings->update_sd) ||
3056                                         (dc->out->sd_settings->phase_in_steps)) {
3057                                 tegra_dc_mask_interrupt(dc, SMARTDIM_INT);
3058                                 nvsd_updated = tegra_sd_update_brightness(dc);
3059                                 dc->out->sd_settings->update_sd = false;
3060                                 tegra_dc_unmask_interrupt(dc, SMARTDIM_INT);
3061                         }
3062                 }
3063         }
3064 #endif
3065 #ifdef CONFIG_TEGRA_NVSD
3066         /* Update the SD brightness */
3067         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
3068                 nvsd_updated = nvsd_update_brightness(dc);
3069                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
3070                  * V_BLANK_NVSD bit of vblank ref-count. */
3071                 if (nvsd_updated) {
3072                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
3073                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
3074                 } else {
3075                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
3076                 }
3077         }
3078
3079         /* Mask vblank interrupt if ref-count is zero. */
3080         if (!dc->vblank_ref_count)
3081                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
3082 #endif /* CONFIG_TEGRA_NVSD */
3083
3084         tegra_dc_put(dc);
3085         mutex_unlock(&dc->lock);
3086
3087 #if defined(CONFIG_TEGRA_NVSD) || defined(CONFIG_TEGRA_NVDISPLAY)
3088         /* Do the actual brightness update outside of the mutex dc->lock */
3089         if (nvsd_updated)
3090                 tegra_dc_prism_update_backlight(dc);
3091 #endif /* CONFIG_TEGRA_NVSD */
3092 }
3093
3094 #define CSC_UPDATE_IF_CHANGED(entry, ENTRY) do { \
3095                 if (cmu_active->csc.entry != cmu_shadow->csc.entry || \
3096                         dc->cmu_shadow_force_update) { \
3097                         cmu_active->csc.entry = cmu_shadow->csc.entry; \
3098                         tegra_dc_writel(dc, \
3099                                 cmu_active->csc.entry, \
3100                                 DC_COM_CMU_CSC_##ENTRY); \
3101                 } \
3102         } while (0)
3103
3104 static void _tegra_dc_handle_hdr(struct tegra_dc *dc)
3105 {
3106         mutex_lock(&dc->lock);
3107         if (!dc->enabled) {
3108                 mutex_unlock(&dc->lock);
3109                 return;
3110         }
3111
3112         tegra_dc_get(dc);
3113
3114         if (dc->out_ops->set_hdr)
3115                 dc->out_ops->set_hdr(dc);
3116
3117         tegra_dc_put(dc);
3118         mutex_unlock(&dc->lock);
3119
3120         return;
3121 }
3122
3123 static void tegra_dc_frame_end(struct work_struct *work)
3124 {
3125         struct tegra_dc *dc = container_of(work,
3126                 struct tegra_dc, frame_end_work);
3127 #ifdef CONFIG_TEGRA_DC_CMU
3128         u32 val;
3129         u32 i;
3130
3131         mutex_lock(&dc->lock);
3132
3133         if (!dc->enabled) {
3134                 mutex_unlock(&dc->lock);
3135                 return;
3136         }
3137
3138         tegra_dc_get(dc);
3139
3140         if (dc->cmu_shadow_dirty) {
3141                 struct tegra_dc_cmu *cmu_active = &dc->cmu;
3142                 struct tegra_dc_cmu *cmu_shadow = &dc->cmu_shadow;
3143
3144                 for (i = 0; i < 256; i++) {
3145                         if (cmu_active->lut1[i] != cmu_shadow->lut1[i] ||
3146                                 dc->cmu_shadow_force_update) {
3147                                 cmu_active->lut1[i] = cmu_shadow->lut1[i];
3148                                 val = LUT1_ADDR(i) |
3149                                         LUT1_DATA(cmu_shadow->lut1[i]);
3150                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
3151                         }
3152                 }
3153
3154                 CSC_UPDATE_IF_CHANGED(krr, KRR);
3155                 CSC_UPDATE_IF_CHANGED(kgr, KGR);
3156                 CSC_UPDATE_IF_CHANGED(kbr, KBR);
3157                 CSC_UPDATE_IF_CHANGED(krg, KRG);
3158                 CSC_UPDATE_IF_CHANGED(kgg, KGG);
3159                 CSC_UPDATE_IF_CHANGED(kbg, KBG);
3160                 CSC_UPDATE_IF_CHANGED(krb, KRB);
3161                 CSC_UPDATE_IF_CHANGED(kgb, KGB);
3162                 CSC_UPDATE_IF_CHANGED(kbb, KBB);
3163
3164                 for (i = 0; i < 960; i++)
3165                         if (cmu_active->lut2[i] != cmu_shadow->lut2[i] ||
3166                                 dc->cmu_shadow_force_update) {
3167                                 cmu_active->lut2[i] = cmu_shadow->lut2[i];
3168                                 val = LUT2_ADDR(i) |
3169                                         LUT2_DATA(cmu_active->lut2[i]);
3170                                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
3171                         }
3172
3173                 dc->cmu_shadow_dirty = false;
3174                 dc->cmu_shadow_force_update = false;
3175                 _tegra_dc_config_frame_end_intr(dc, false);
3176         }
3177
3178         tegra_dc_put(dc);
3179         mutex_unlock(&dc->lock);
3180 #endif
3181         if (dc->hdr_cache_dirty) {
3182                 _tegra_dc_handle_hdr(dc);
3183                 _tegra_dc_config_frame_end_intr(dc, false);
3184                 dc->hdr_cache_dirty = false;
3185         }
3186         return;
3187 }
3188
3189 static void tegra_dc_one_shot_worker(struct work_struct *work)
3190 {
3191         struct tegra_dc *dc = container_of(
3192                 to_delayed_work(work), struct tegra_dc, one_shot_work);
3193         mutex_lock(&dc->lock);
3194
3195         /* memory client has gone idle */
3196         tegra_dc_clear_bandwidth(dc);
3197
3198         if (dc->out_ops && dc->out_ops->idle) {
3199                 tegra_dc_io_start(dc);
3200                 dc->out_ops->idle(dc);
3201                 tegra_dc_io_end(dc);
3202         }
3203
3204         mutex_unlock(&dc->lock);
3205 }
3206
3207 #if !defined(CONFIG_TEGRA_NVDISPLAY)
3208 /* return an arbitrarily large number if count overflow occurs.
3209  * make it a nice base-10 number to show up in stats output */
3210 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
3211 {
3212         unsigned count = tegra_dc_readl(dc, reg);
3213
3214         tegra_dc_writel(dc, 0, reg);
3215         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
3216 }
3217 #endif
3218
3219 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
3220 {
3221 #if !defined(CONFIG_TEGRA_NVDISPLAY)
3222
3223         const u32 masks[] = {
3224                 WIN_A_UF_INT,
3225                 WIN_B_UF_INT,
3226                 WIN_C_UF_INT,
3227 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3228         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3229         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3230                 WIN_D_UF_INT,
3231                 HC_UF_INT,
3232                 WIN_T_UF_INT,
3233 #endif
3234         };
3235         int i;
3236
3237         dc->stats.underflows++;
3238         if (dc->underflow_mask & WIN_A_UF_INT)
3239                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
3240                         DC_WINBUF_AD_UFLOW_STATUS);
3241         if (dc->underflow_mask & WIN_B_UF_INT)
3242                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
3243                         DC_WINBUF_BD_UFLOW_STATUS);
3244         if (dc->underflow_mask & WIN_C_UF_INT)
3245                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
3246                         DC_WINBUF_CD_UFLOW_STATUS);
3247 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3248         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3249         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3250         if (dc->underflow_mask & HC_UF_INT)
3251                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
3252                         DC_WINBUF_HD_UFLOW_STATUS);
3253         if (dc->underflow_mask & WIN_D_UF_INT)
3254                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
3255                         DC_WINBUF_DD_UFLOW_STATUS);
3256         if (dc->underflow_mask & WIN_T_UF_INT)
3257                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
3258                         DC_WINBUF_TD_UFLOW_STATUS);
3259 #endif
3260
3261         /* Check for any underflow reset conditions */
3262         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3263                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3264                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
3265                         "underflow stats unsupported"))
3266                         break; /* bail if the table above is missing entries */
3267                 if (!masks[i])
3268                         continue; /* skip empty entries */
3269
3270                 if (dc->underflow_mask & masks[i]) {
3271                         win->underflows++;
3272
3273 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3274                         if (i < 3 && win->underflows > 4) {
3275                                 schedule_work(&dc->reset_work);
3276                                 /* reset counter */
3277                                 win->underflows = 0;
3278                                 trace_display_reset(dc);
3279                         }
3280 #endif
3281 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3282                         if (i < 3 && win->underflows > 4) {
3283                                 trace_display_reset(dc);
3284                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
3285                                                 DC_DISP_DISP_MISC_CONTROL);
3286                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3287                                                 DC_CMD_STATE_CONTROL);
3288
3289                                 tegra_dc_writel(dc, 0,
3290                                                 DC_DISP_DISP_MISC_CONTROL);
3291                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
3292                                                 DC_CMD_STATE_CONTROL);
3293                         }
3294 #endif
3295                 } else {
3296                         win->underflows = 0;
3297                 }
3298         }
3299
3300 #else
3301         tegra_nvdisp_underflow_handler(dc);
3302 #endif /* CONFIG_TEGRA_NVDISPLAY */
3303
3304         /* Clear the underflow mask now that we've checked it. */
3305         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
3306         dc->underflow_mask = 0;
3307         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
3308         trace_underflow(dc);
3309 }
3310
3311 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3312 static void tegra_dc_vpulse2(struct work_struct *work)
3313 {
3314         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
3315 #ifdef CONFIG_TEGRA_NVSD
3316         bool nvsd_updated = false;
3317 #endif /* CONFIG_TEGRA_NVSD */
3318
3319         mutex_lock(&dc->lock);
3320
3321         if (!dc->enabled) {
3322                 mutex_unlock(&dc->lock);
3323                 return;
3324         }
3325
3326         tegra_dc_get(dc);
3327
3328         /* Clear the V_PULSE2_FLIP if no update */
3329         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
3330                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
3331
3332 #ifdef CONFIG_TEGRA_NVSD
3333         /* Update the SD brightness */
3334         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
3335                 nvsd_updated = nvsd_update_brightness(dc);
3336
3337                 if (nvsd_updated) {
3338                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3339                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
3340                 } else {
3341                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
3342                 }
3343         }
3344
3345         /* Mask vpulse2 interrupt if ref-count is zero. */
3346         if (!dc->vpulse2_ref_count)
3347                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3348 #endif /* CONFIG_TEGRA_NVSD */
3349
3350         tegra_dc_put(dc);
3351         mutex_unlock(&dc->lock);
3352
3353 #ifdef CONFIG_TEGRA_NVSD
3354         /* Do the actual brightness update outside of the mutex dc->lock */
3355         if (nvsd_updated)
3356                 tegra_dc_prism_update_backlight(dc);
3357 #endif /* CONFIG_TEGRA_NVSD */
3358 }
3359 #endif
3360
3361 static void tegra_dc_process_vblank(struct tegra_dc *dc, ktime_t timestamp)
3362 {
3363         /* pending user vblank, so wakeup */
3364         if (dc->out->user_needs_vblank) {
3365                 dc->out->user_needs_vblank = false;
3366                 complete(&dc->out->user_vblank_comp);
3367         }
3368         if (test_bit(V_BLANK_USER, &dc->vblank_ref_count)) {
3369 #ifdef CONFIG_ADF_TEGRA
3370                 tegra_adf_process_vblank(dc->adf, timestamp);
3371 #endif
3372 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3373                 tegra_dc_ext_process_vblank(dc->ndev->id, timestamp);
3374 #endif
3375         }
3376 }
3377
3378 int tegra_dc_config_frame_end_intr(struct tegra_dc *dc, bool enable)
3379 {
3380         int ret;
3381
3382         mutex_lock(&dc->lock);
3383         ret = _tegra_dc_config_frame_end_intr(dc, enable);
3384         mutex_unlock(&dc->lock);
3385
3386         return ret;
3387 }
3388
3389 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
3390                 ktime_t timestamp)
3391 {
3392         if (status & MSF_INT)
3393                 tegra_dc_process_vblank(dc, timestamp);
3394
3395         if (status & V_BLANK_INT) {
3396                 /* Sync up windows. */
3397                 tegra_dc_trigger_windows(dc);
3398
3399                 /* Schedule any additional bottom-half vblank actvities. */
3400                 queue_work(system_freezable_wq, &dc->vblank_work);
3401         }
3402
3403         if (status & FRAME_END_INT) {
3404                 /* Mark the frame_end as complete. */
3405                 dc->crc_pending = false;
3406                 if (!completion_done(&dc->frame_end_complete))
3407                         complete(&dc->frame_end_complete);
3408                 if (!completion_done(&dc->crc_complete))
3409                         complete(&dc->crc_complete);
3410
3411                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3412                         tegra_dc_put(dc);
3413
3414                 queue_work(system_freezable_wq, &dc->frame_end_work);
3415         }
3416
3417 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3418         if (status & V_PULSE2_INT)
3419                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3420 #endif
3421 }
3422
3423 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
3424                 ktime_t timestamp)
3425 {
3426         /* Schedule any additional bottom-half vblank actvities. */
3427         if (status & V_BLANK_INT) {
3428 #ifdef CONFIG_TEGRA_NVDISPLAY
3429                 if (status & SMARTDIM_INT) {
3430                         if (dc->out->sd_settings) {
3431                                 dc->out->sd_settings->update_sd = true;
3432                         }
3433                 }
3434 #endif
3435                 queue_work(system_freezable_wq, &dc->vblank_work);
3436         }
3437         if (status & (V_BLANK_INT | MSF_INT)) {
3438                 if (dc->out->user_needs_vblank) {
3439                         dc->out->user_needs_vblank = false;
3440                         complete(&dc->out->user_vblank_comp);
3441                 }
3442                 tegra_dc_process_vblank(dc, timestamp);
3443         }
3444
3445         if (status & FRAME_END_INT) {
3446                 struct timespec tm;
3447                 ktime_get_ts(&tm);
3448                 dc->frame_end_timestamp = timespec_to_ns(&tm);
3449                 wake_up(&dc->timestamp_wq);
3450
3451                 if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ)) {
3452                         if (dc->out->type == TEGRA_DC_OUT_DSI) {
3453                                 tegra_dc_vrr_get_ts(dc);
3454                                 tegra_dc_vrr_sec(dc);
3455                         } else
3456                                 tegra_dc_vrr_extend_vfp(dc);
3457                 }
3458
3459                 /* Mark the frame_end as complete. */
3460                 if (!completion_done(&dc->frame_end_complete))
3461                         complete(&dc->frame_end_complete);
3462                 if (!completion_done(&dc->crc_complete))
3463                         complete(&dc->crc_complete);
3464
3465                 tegra_dc_trigger_windows(dc);
3466
3467                 queue_work(system_freezable_wq, &dc->frame_end_work);
3468         }
3469
3470 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3471         if (status & V_PULSE2_INT)
3472                 queue_work(system_freezable_wq, &dc->vpulse2_work);
3473 #endif
3474 }
3475
3476 /* XXX: Not sure if we limit look ahead to 1 frame */
3477 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
3478 {
3479         BUG_ON(!dc->frametime_ns);
3480         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
3481 }
3482
3483 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
3484 {
3485         BUG_ON(!dc->frametime_ns);
3486         return (((new_ts - old_ts) > dc->frametime_ns)
3487                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
3488                         != div_s64((old_ts - dc->frame_end_timestamp),
3489                                 dc->frametime_ns)));
3490 }
3491
3492 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
3493 {
3494         ktime_t timestamp = ktime_get();
3495         struct tegra_dc *dc = ptr;
3496         unsigned long status;
3497         unsigned long underflow_mask;
3498         u32 val;
3499         int need_disable = 0;
3500
3501         if (tegra_platform_is_fpga())
3502                 return IRQ_NONE;
3503
3504         mutex_lock(&dc->lock);
3505         if (!tegra_dc_is_powered(dc)) {
3506                 mutex_unlock(&dc->lock);
3507                 return IRQ_HANDLED;
3508         }
3509
3510         tegra_dc_get(dc);
3511
3512         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
3513                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
3514                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3515                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
3516                 tegra_dc_put(dc);
3517                 mutex_unlock(&dc->lock);
3518                 return IRQ_HANDLED;
3519         }
3520
3521         /* clear all status flags except underflow, save those for the worker */
3522         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
3523         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
3524         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
3525         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
3526
3527         /*
3528          * Overlays can get thier internal state corrupted during and underflow
3529          * condition.  The only way to fix this state is to reset the DC.
3530          * if we get 4 consecutive frames with underflows, assume we're
3531          * hosed and reset.
3532          */
3533         underflow_mask = status & ALL_UF_INT();
3534
3535         /* Check underflow */
3536         if (underflow_mask) {
3537                 dc->underflow_mask |= underflow_mask;
3538                 schedule_delayed_work(&dc->underflow_work,
3539                         msecs_to_jiffies(1));
3540         }
3541
3542         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE ||
3543                 dc->out->flags & TEGRA_DC_OUT_NVSR_MODE)
3544                 tegra_dc_one_shot_irq(dc, status, timestamp);
3545         else
3546                 tegra_dc_continuous_irq(dc, status, timestamp);
3547
3548         if (dc->nvsr)
3549                 tegra_dc_nvsr_irq(dc->nvsr, status);
3550
3551         /* update video mode if it has changed since the last frame */
3552         if (status & (FRAME_END_INT | V_BLANK_INT))
3553                 if (tegra_dc_update_mode(dc))
3554                         need_disable = 1; /* force display off on error */
3555
3556         if (status & FRAME_END_INT)
3557                 if (dc->disp_active_dirty) {
3558                         tegra_dc_writel(dc, dc->mode.h_active |
3559                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
3560                         tegra_dc_writel(dc,
3561                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3562
3563                         dc->disp_active_dirty = false;
3564                 }
3565
3566         tegra_dc_put(dc);
3567         mutex_unlock(&dc->lock);
3568
3569         if (need_disable)
3570                 tegra_dc_disable_irq_ops(dc, true);
3571         return IRQ_HANDLED;
3572 }
3573
3574 void tegra_dc_set_color_control(struct tegra_dc *dc)
3575 {
3576         u32 color_control;
3577
3578         switch (dc->out->depth) {
3579         case 3:
3580                 color_control = BASE_COLOR_SIZE111;
3581                 break;
3582
3583         case 6:
3584                 color_control = BASE_COLOR_SIZE222;
3585                 break;
3586
3587         case 8:
3588                 color_control = BASE_COLOR_SIZE332;
3589                 break;
3590
3591         case 9:
3592                 color_control = BASE_COLOR_SIZE333;
3593                 break;
3594
3595         case 12:
3596                 color_control = BASE_COLOR_SIZE444;
3597                 break;
3598
3599         case 15:
3600                 color_control = BASE_COLOR_SIZE555;
3601                 break;
3602
3603         case 16:
3604                 color_control = BASE_COLOR_SIZE565;
3605                 break;
3606
3607         case 18:
3608                 color_control = BASE_COLOR_SIZE666;
3609                 break;
3610
3611         default:
3612                 color_control = BASE_COLOR_SIZE888;
3613                 break;
3614         }
3615
3616         switch (dc->out->dither) {
3617         case TEGRA_DC_UNDEFINED_DITHER:
3618         case TEGRA_DC_DISABLE_DITHER:
3619                 color_control |= DITHER_CONTROL_DISABLE;
3620                 break;
3621         case TEGRA_DC_ORDERED_DITHER:
3622                 color_control |= DITHER_CONTROL_ORDERED;
3623                 break;
3624 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
3625         case TEGRA_DC_TEMPORAL_DITHER:
3626                 color_control |= DITHER_CONTROL_TEMPORAL;
3627                 break;
3628 #else
3629         case TEGRA_DC_ERRDIFF_DITHER:
3630                 /* The line buffer for error-diffusion dither is limited
3631                  * to 1280 pixels per line. This limits the maximum
3632                  * horizontal active area size to 1280 pixels when error
3633                  * diffusion is enabled.
3634                  */
3635                 BUG_ON(dc->mode.h_active > 1280);
3636                 color_control |= DITHER_CONTROL_ERRDIFF;
3637                 break;
3638 #endif
3639         default:
3640                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
3641         }
3642
3643 #ifdef CONFIG_TEGRA_DC_CMU
3644         if (dc->cmu_enabled)
3645                 color_control |= CMU_ENABLE;
3646 #endif
3647
3648         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
3649 }
3650
3651 #ifndef CONFIG_TEGRA_NVDISPLAY
3652 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
3653 {
3654 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3655         u32 start, end;
3656         unsigned long val;
3657
3658         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
3659         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
3660
3661         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
3662                 dc->mode.v_back_porch + dc->mode.v_active;
3663         end = start + 1;
3664         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
3665         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
3666
3667         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3668         val |= V_PULSE2_INT;
3669         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
3670
3671         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
3672         val = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0);
3673         val |= V_PULSE_2_ENABLE;
3674         tegra_dc_writel(dc, val, DC_DISP_DISP_SIGNAL_OPTIONS0);
3675 #endif
3676 }
3677
3678 static int tegra_dc_init(struct tegra_dc *dc)
3679 {
3680         int i;
3681         int int_enable;
3682         u32 val;
3683
3684         tegra_dc_io_start(dc);
3685         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
3686         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
3687                         DC_CMD_CONT_SYNCPT_VSYNC);
3688
3689         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
3690 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3691         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3692         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3693         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3694                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
3695                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3696                 DC_CMD_INT_POLARITY);
3697 #else
3698         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
3699                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
3700                 DC_CMD_INT_POLARITY);
3701 #endif
3702         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
3703         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
3704 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
3705         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
3706 #endif
3707         /* enable interrupts for vblank, frame_end and underflows */
3708         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
3709         /* for panels with one-shot mode enable tearing effect interrupt */
3710         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3711                 int_enable |= MSF_INT;
3712
3713         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
3714         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
3715         tegra_dc_init_vpulse2_int(dc);
3716
3717         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
3718                 DC_CMD_STATE_ACCESS);
3719
3720 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
3721         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
3722 #else
3723         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
3724 #endif
3725
3726 #ifdef CONFIG_TEGRA_DC_CMU
3727         if (dc->is_cmu_set_bl)
3728                 _tegra_dc_update_cmu_aligned(dc, &dc->cmu, true);
3729         else
3730                 _tegra_dc_update_cmu(dc, &dc->cmu);
3731         dc->is_cmu_set_bl = false;
3732 #endif
3733         tegra_dc_set_color_control(dc);
3734         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3735                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3736                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
3737                                 DC_CMD_DISPLAY_WINDOW_HEADER);
3738                 tegra_dc_set_csc(dc, &win->csc);
3739                 tegra_dc_set_lut(dc, win);
3740                 tegra_dc_set_scaling_filter(dc);
3741         }
3742
3743 #ifdef CONFIG_TEGRA_DC_WIN_H
3744         /* Window H is set to window mode by default for t14x. */
3745         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
3746                         DC_DISP_BLEND_CURSOR_CONTROL);
3747 #endif
3748
3749         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
3750                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
3751
3752                 BUG_ON(!win);
3753
3754                 /* refuse to operate on invalid syncpts */
3755                 if (WARN_ON(win->syncpt.id == NVSYNCPT_INVALID))
3756                         continue;
3757
3758                 if (!nvhost_syncpt_read_ext_check(dc->ndev, win->syncpt.id, &val))
3759                         win->syncpt.min = win->syncpt.max = val;
3760         }
3761
3762         dc->crc_pending = false;
3763
3764         trace_display_mode(dc, &dc->mode);
3765
3766         if (dc->mode.pclk) {
3767                 if (!dc->initialized) {
3768                         if (tegra_dc_program_mode(dc, &dc->mode)) {
3769                                 tegra_dc_io_end(dc);
3770                                 dev_warn(&dc->ndev->dev,
3771                                         "%s: tegra_dc_program_mode failed\n",
3772                                         __func__);
3773                                 return -EINVAL;
3774                         }
3775                 } else {
3776                         dev_info(&dc->ndev->dev, "DC initialized, "
3777                                         "skipping tegra_dc_program_mode.\n");
3778                 }
3779         }
3780
3781         /* Initialize SD AFTER the modeset.
3782            nvsd_init handles the sd_settings = NULL case. */
3783         nvsd_init(dc, dc->out->sd_settings);
3784
3785         tegra_dc_io_end(dc);
3786
3787         return 0;
3788 }
3789
3790 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
3791 {
3792         int failed_init = 0;
3793         int i;
3794
3795 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
3796         struct device_node *np_dpaux;
3797 #endif
3798
3799         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3800                 return false;
3801
3802         tegra_dc_unpowergate_locked(dc);
3803
3804         if (dc->out->enable)
3805                 dc->out->enable(&dc->ndev->dev);
3806
3807         tegra_dc_setup_clk(dc, dc->clk);
3808
3809         /* dc clk always on for continuous mode */
3810         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3811                 tegra_dc_clk_enable(dc);
3812         else
3813                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
3814
3815         tegra_dc_get(dc);
3816
3817         tegra_dc_power_on(dc);
3818
3819         /* do not accept interrupts during initialization */
3820         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3821
3822         enable_dc_irq(dc);
3823
3824         failed_init = tegra_dc_init(dc);
3825         if (failed_init) {
3826                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
3827                 disable_irq_nosync(dc->irq);
3828                 tegra_dc_clear_bandwidth(dc);
3829                 if (dc->out && dc->out->disable)
3830                         dc->out->disable(&dc->ndev->dev);
3831                 tegra_dc_put(dc);
3832                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
3833                         tegra_dc_clk_disable(dc);
3834                 else
3835                         tegra_dvfs_set_rate(dc->clk, 0);
3836                 dev_warn(&dc->ndev->dev,
3837                         "%s: tegra_dc_init failed\n", __func__);
3838                 return false;
3839         }
3840
3841 #if !defined(CONFIG_ARCH_TEGRA_21x_SOC)
3842         if (dc->out->type != TEGRA_DC_OUT_DP) {
3843                 np_dpaux = of_find_node_by_path(
3844                                 dc->ndev->id ? DPAUX1_NODE : DPAUX_NODE);
3845                 if (np_dpaux || !dc->ndev->dev.of_node)
3846                         tegra_dpaux_pad_power(dc,
3847                         dc->ndev->id ? TEGRA_DPAUX_INSTANCE_1 :
3848                         TEGRA_DPAUX_INSTANCE_0, false);
3849                 of_node_put(np_dpaux);
3850         }
3851 #endif
3852
3853         if (dc->out_ops && dc->out_ops->enable)
3854                 dc->out_ops->enable(dc);
3855
3856         /* force a full blending update */
3857         for (i = 0; i < DC_N_WINDOWS; i++)
3858                 dc->blend.z[i] = -1;
3859
3860 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3861         tegra_dc_ext_enable(dc->ext);
3862 #endif
3863
3864         /* initialize cursor to defaults, as driver depends on HW state */
3865         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
3866         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
3867 #if defined(CONFIG_ARCH_TEGRA_12x_SOC) || defined(CONFIG_ARCH_TEGRA_21x_SOC)
3868         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
3869         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
3870 #endif
3871         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
3872         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
3873         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
3874         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
3875         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
3876
3877         trace_display_enable(dc);
3878
3879 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3880 !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3881 !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
3882 !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3883         tegra_dc_writel(dc, CURSOR_UPDATE, DC_CMD_STATE_CONTROL);
3884         tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
3885 #endif
3886         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
3887
3888         if (dc->out->postpoweron)
3889                 dc->out->postpoweron(&dc->ndev->dev);
3890
3891         if (dc->out_ops && dc->out_ops->postpoweron)
3892                 dc->out_ops->postpoweron(dc);
3893
3894         tegra_log_resume_time();
3895
3896         tegra_dc_put(dc);
3897
3898         tegra_disp_clk_prepare_enable(dc->emc_la_clk);
3899
3900         return true;
3901 }
3902 #endif
3903
3904 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3905 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
3906 {
3907         bool ret = true;
3908
3909         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3910                 return false;
3911
3912         if (dc->out->enable)
3913                 dc->out->enable(&dc->ndev->dev);
3914
3915         tegra_dc_setup_clk(dc, dc->clk);
3916         tegra_dc_clk_enable(dc);
3917
3918         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
3919                 mutex_lock(&tegra_dcs[1]->lock);
3920                 disable_irq_nosync(tegra_dcs[1]->irq);
3921         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
3922                 mutex_lock(&tegra_dcs[0]->lock);
3923                 disable_irq_nosync(tegra_dcs[0]->irq);
3924         }
3925
3926         msleep(5);
3927         tegra_periph_reset_assert(dc->clk);
3928         msleep(2);
3929         if (tegra_platform_is_silicon()) {
3930                 tegra_periph_reset_deassert(dc->clk);
3931                 msleep(1);
3932         }
3933
3934         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
3935                 enable_dc_irq(tegra_dcs[1]);
3936                 mutex_unlock(&tegra_dcs[1]->lock);
3937         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
3938                 enable_dc_irq(tegra_dcs[0]);
3939                 mutex_unlock(&tegra_dcs[0]->lock);
3940         }
3941
3942         enable_dc_irq(dc);
3943
3944         if (tegra_dc_init(dc)) {
3945                 dev_err(&dc->ndev->dev, "cannot initialize\n");
3946                 ret = false;
3947         }
3948
3949         if (dc->out_ops && dc->out_ops->enable)
3950                 dc->out_ops->enable(dc);
3951
3952         if (dc->out->postpoweron)
3953                 dc->out->postpoweron(&dc->ndev->dev);
3954
3955         /* force a full blending update */
3956         dc->blend.z[0] = -1;
3957
3958 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
3959         tegra_dc_ext_enable(dc->ext);
3960 #endif
3961
3962         if (!ret) {
3963                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
3964                 _tegra_dc_controller_disable(dc);
3965         }
3966
3967         trace_display_reset(dc);
3968         return ret;
3969 }
3970 #endif
3971
3972 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
3973 {
3974         if (dc->mode.pclk == 0) {
3975                 switch (dc->out->type) {
3976                 case TEGRA_DC_OUT_HDMI:
3977                         /* No fallback mode. If no mode info available
3978                          * from bootloader or device tree,
3979                          * mode will be set by userspace during unblank.
3980                          */
3981                         break;
3982                 case TEGRA_DC_OUT_DP:
3983                 case TEGRA_DC_OUT_NVSR_DP:
3984                 case TEGRA_DC_OUT_FAKE_DP:
3985                 case TEGRA_DC_OUT_NULL:
3986                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
3987
3988                 /* Do nothing for other outputs for now */
3989                 case TEGRA_DC_OUT_RGB:
3990
3991                 case TEGRA_DC_OUT_DSI:
3992
3993                 default:
3994                         return false;
3995                 }
3996         }
3997
3998         return false;
3999 }
4000
4001 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
4002 {
4003         return _tegra_dc_set_default_videomode(dc);
4004 }
4005
4006 static bool _tegra_dc_enable(struct tegra_dc *dc)
4007 {
4008         if (dc->mode.pclk == 0)
4009                 return false;
4010
4011         if (!dc->out)
4012                 return false;
4013
4014         if (dc->enabled)
4015                 return true;
4016
4017         pm_runtime_get_sync(&dc->ndev->dev);
4018
4019         if ((dc->out->type == TEGRA_DC_OUT_HDMI ||
4020                 dc->out->type == TEGRA_DC_OUT_DP) &&
4021                 !tegra_dc_hpd(dc))
4022                 return false;
4023
4024 #ifdef CONFIG_TEGRA_NVDISPLAY
4025         if (tegra_nvdisp_head_enable(dc)) {
4026 #else
4027         if (!_tegra_dc_controller_enable(dc)) {
4028 #endif
4029                 pm_runtime_put_sync(&dc->ndev->dev);
4030                 return false;
4031         }
4032
4033         return true;
4034 }
4035
4036 void tegra_dc_enable(struct tegra_dc *dc)
4037 {
4038         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4039                 return;
4040
4041         mutex_lock(&dc->lock);
4042
4043         if (!dc->enabled)
4044                 dc->enabled = _tegra_dc_enable(dc);
4045
4046         mutex_unlock(&dc->lock);
4047         trace_display_mode(dc, &dc->mode);
4048 }
4049
4050 static void tegra_dc_flush_syncpts_window(struct tegra_dc *dc, unsigned win)
4051 {
4052         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
4053         u32 max;
4054
4055         /* refuse to operate on invalid syncpts */
4056         if (WARN_ON(w->syncpt.id == NVSYNCPT_INVALID))
4057                 return;
4058
4059         /* flush any pending syncpt waits */
4060         max = tegra_dc_incr_syncpt_max_locked(dc, win);
4061         while (w->syncpt.min < w->syncpt.max) {
4062                 trace_display_syncpt_flush(dc, w->syncpt.id,
4063                         w->syncpt.min, w->syncpt.max);
4064                 w->syncpt.min++;
4065                 nvhost_syncpt_cpu_incr_ext(dc->ndev, w->syncpt.id);
4066         }
4067 }
4068
4069 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
4070 {
4071         struct tegra_dc_win *w = tegra_dc_get_window(dc, win);
4072
4073         /* reset window bandwidth */
4074         w->bandwidth = 0;
4075         w->new_bandwidth = 0;
4076
4077         /* disable windows */
4078         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
4079
4080         /* flush pending syncpts */
4081         tegra_dc_flush_syncpts_window(dc, win);
4082 }
4083
4084 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
4085 {
4086         unsigned i;
4087
4088         tegra_dc_get(dc);
4089
4090         if (atomic_read(&dc->holding)) {
4091                 /* Force release all refs but the last one */
4092                 atomic_set(&dc->holding, 1);
4093                 tegra_dc_release_dc_out(dc);
4094         }
4095
4096         if (dc->out && dc->out->prepoweroff)
4097                 dc->out->prepoweroff();
4098
4099         if (dc->out_ops && dc->out_ops->vrr_enable) {
4100                 dc->out_ops->vrr_enable(dc, 0);
4101                 /* TODO: Fix properly. Bug 1644102. */
4102                 tegra_dc_set_act_vfp(dc, dc->mode.v_front_porch);
4103         }
4104
4105         if (dc->out_ops && dc->out_ops->disable)
4106                 dc->out_ops->disable(dc);
4107
4108         if (tegra_powergate_is_powered(dc->powergate_id))
4109                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
4110
4111         disable_irq_nosync(dc->irq);
4112
4113         tegra_dc_clear_bandwidth(dc);
4114
4115         if (dc->out && dc->out->disable)
4116                 dc->out->disable(&dc->ndev->dev);
4117
4118         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
4119                 tegra_dc_disable_window(dc, i);
4120         }
4121         trace_display_disable(dc);
4122
4123         if (dc->out_ops && dc->out_ops->postpoweroff)
4124                 dc->out_ops->postpoweroff(dc);
4125
4126         tegra_dc_put(dc);
4127
4128         /* disable always on dc clk in continuous mode */
4129         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
4130                 tegra_dc_clk_disable(dc);
4131         else
4132                 tegra_dvfs_set_rate(dc->clk, 0);
4133
4134         tegra_disp_clk_disable_unprepare(dc->emc_la_clk);
4135 }
4136
4137 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
4138 {
4139 #if 0 /* underflow interrupt is already enabled by dc reset worker */
4140         u32 val;
4141         if (dc->enabled)  {
4142                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
4143                 if (enable)
4144                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
4145                 else
4146                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
4147                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
4148         }
4149 #endif
4150 }
4151
4152 bool tegra_dc_stats_get(struct tegra_dc *dc)
4153 {
4154 #if 0 /* right now it is always enabled */
4155         u32 val;
4156         bool res;
4157
4158         if (dc->enabled)  {
4159                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
4160                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
4161         } else {
4162                 res = false;
4163         }
4164
4165         return res;
4166 #endif
4167         return true;
4168 }
4169
4170 /* blank selected windows by disabling them */
4171 int tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
4172 {
4173         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
4174         struct tegra_dc_win blank_win;
4175         unsigned i;
4176         unsigned long int blank_windows;
4177         int nr_win = 0;
4178         int ret = 0;
4179
4180         /* YUV420 10bpc variables */
4181         int yuv_flag = dc->mode.vmode & FB_VMODE_YUV_MASK;
4182         bool yuv_420_10b_path = false;
4183         int fb_win_idx = -1;
4184         int fb_win_pos = -1;
4185
4186         if (dc->yuv_bypass && yuv_flag == (FB_VMODE_Y420 | FB_VMODE_Y30))
4187                 yuv_420_10b_path = true;
4188
4189         if (yuv_420_10b_path) {
4190                 u32 active_width = dc->mode.h_active;
4191                 u32 active_height = dc->mode.v_active;
4192
4193                 blank_win = *tegra_fb_get_blank_win(dc->fb);
4194
4195                 /*
4196                  * 420 10bpc blank frame statically
4197                  * created for this pixel format
4198                  */
4199                 blank_win.h.full = dfixed_const(1);
4200                 blank_win.w.full = dfixed_const(active_width);
4201                 blank_win.fmt = TEGRA_WIN_FMT_B8G8R8A8;
4202                 blank_win.out_w = active_width;
4203                 blank_win.out_h = active_height;
4204
4205                 dcwins[0] = &blank_win;
4206                 fb_win_idx = dcwins[0]->idx;
4207                 nr_win++;
4208         }
4209
4210         blank_windows = windows & dc->valid_windows;
4211
4212         if (!blank_windows)
4213                 return ret;
4214
4215         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4216                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
4217                 if (!dcwins[nr_win])
4218                         continue;
4219                 /*
4220                  * Prevent disabling the YUV410 10bpc window in case
4221                  * it is also in blank_windows, additionally, prevent
4222                  * adding it to the list twice.
4223                  */
4224                 if (fb_win_idx == dcwins[nr_win]->idx) {
4225                         fb_win_pos = i;
4226                         continue;
4227                 }
4228                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
4229         }
4230
4231         /* Skip update for linsim */
4232         if (!tegra_platform_is_linsim()) {
4233                 tegra_dc_update_windows(dcwins, nr_win, NULL, true);
4234                 ret = tegra_dc_sync_windows(dcwins, nr_win);
4235         }
4236         tegra_dc_program_bandwidth(dc, true);
4237
4238         /*
4239          * Disable, reset bandwidth and advance pending syncpoints
4240          * of all windows. In case the statically created 420 10bpc
4241          * is also present in blank_windows, only advance syncpoints.
4242          */
4243         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
4244                 if (fb_win_pos == i) {
4245                         tegra_dc_flush_syncpts_window(dc, i);
4246                         continue;
4247                 }
4248                 tegra_dc_disable_window(dc, i);
4249         }
4250         return ret;
4251 }
4252
4253 int tegra_dc_restore(struct tegra_dc *dc)
4254 {
4255 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4256         return tegra_dc_ext_restore(dc->ext);
4257 #else
4258         return 0;
4259 #endif
4260 }
4261
4262 static void _tegra_dc_disable(struct tegra_dc *dc)
4263 {
4264 #ifdef CONFIG_TEGRA_DC_CMU
4265         /* power down resets the registers, setting to true
4266          * causes CMU to be restored in tegra_dc_init(). */
4267         dc->cmu_dirty = true;
4268 #endif
4269         tegra_dc_io_start(dc);
4270         _tegra_dc_controller_disable(dc);
4271         tegra_dc_io_end(dc);
4272
4273         tegra_dc_powergate_locked(dc);
4274
4275         pm_runtime_put(&dc->ndev->dev);
4276
4277         tegra_log_suspend_time();
4278 }
4279
4280 void tegra_dc_disable(struct tegra_dc *dc)
4281 {
4282         tegra_dc_disable_irq_ops(dc, false);
4283 }
4284
4285 static void tegra_dc_disable_irq_ops(struct tegra_dc *dc, bool from_irq)
4286 {
4287         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
4288                 return;
4289
4290 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4291         if (!tegra_dc_ext_disable(dc->ext))
4292                 tegra_dc_blank(dc, BLANK_ALL);
4293 #else
4294         tegra_dc_blank(dc, BLANK_ALL);
4295 #endif
4296
4297         /* it's important that new underflow work isn't scheduled before the
4298          * lock is acquired. */
4299         cancel_delayed_work_sync(&dc->underflow_work);
4300
4301
4302         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
4303                 mutex_lock(&dc->one_shot_lock);
4304                 cancel_delayed_work_sync(&dc->one_shot_work);
4305         }
4306
4307         mutex_lock(&dc->lp_lock);
4308         mutex_lock(&dc->lock);
4309
4310         if (dc->enabled) {
4311                 dc->enabled = false;
4312                 dc->blanked = false;
4313
4314                 if (!dc->suspended)
4315                         _tegra_dc_disable(dc);
4316         }
4317
4318 #ifdef CONFIG_SWITCH
4319         if (dc->switchdev_registered)
4320                 switch_set_state(&dc->modeset_switch, 0);
4321 #endif
4322         mutex_unlock(&dc->lock);
4323         mutex_unlock(&dc->lp_lock);
4324         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
4325                 mutex_unlock(&dc->one_shot_lock);
4326         if (!from_irq)
4327                 synchronize_irq(dc->irq);
4328         trace_display_mode(dc, &dc->mode);
4329
4330         /* disable pending clks due to uncompleted frames */
4331         while (!tegra_platform_is_linsim() && tegra_is_clk_enabled(dc->clk))
4332                 tegra_dc_put(dc);
4333 }
4334
4335 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4336 static void tegra_dc_reset_worker(struct work_struct *work)
4337 {
4338         struct tegra_dc *dc =
4339                 container_of(work, struct tegra_dc, reset_work);
4340
4341         unsigned long val = 0;
4342
4343         mutex_lock(&shared_lock);
4344
4345         dev_warn(&dc->ndev->dev,
4346                 "overlay stuck in underflow state.  resetting.\n");
4347
4348 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4349         tegra_dc_ext_disable(dc->ext);
4350 #endif
4351
4352         mutex_lock(&dc->lock);
4353
4354         if (dc->enabled == false)
4355                 goto unlock;
4356
4357         dc->enabled = false;
4358
4359         /*
4360          * off host read bus
4361          */
4362         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4363         val &= ~(0x00000100);
4364         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4365
4366         /*
4367          * set DC to STOP mode
4368          */
4369         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
4370
4371         msleep(10);
4372
4373         _tegra_dc_controller_disable(dc);
4374
4375         /* _tegra_dc_controller_reset_enable deasserts reset */
4376         _tegra_dc_controller_reset_enable(dc);
4377
4378         dc->enabled = true;
4379
4380         /* reopen host read bus */
4381         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
4382         val &= ~(0x00000100);
4383         val |= 0x100;
4384         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
4385
4386 unlock:
4387         mutex_unlock(&dc->lock);
4388         mutex_unlock(&shared_lock);
4389         trace_display_reset(dc);
4390 }
4391 #endif
4392
4393 static void tegra_dc_underflow_worker(struct work_struct *work)
4394 {
4395         struct tegra_dc *dc = container_of(
4396                 to_delayed_work(work), struct tegra_dc, underflow_work);
4397
4398         mutex_lock(&dc->lock);
4399         tegra_dc_get(dc);
4400
4401         if (dc->enabled)
4402                 tegra_dc_underflow_handler(dc);
4403
4404         tegra_dc_put(dc);
4405         mutex_unlock(&dc->lock);
4406 }
4407
4408 static void (*flip_callback)(void);
4409 static spinlock_t flip_callback_lock;
4410 static bool init_tegra_dc_flip_callback_called;
4411
4412 static int __init init_tegra_dc_flip_callback(void)
4413 {
4414         spin_lock_init(&flip_callback_lock);
4415         init_tegra_dc_flip_callback_called = true;
4416         return 0;
4417 }
4418
4419 pure_initcall(init_tegra_dc_flip_callback);
4420
4421 int tegra_dc_set_flip_callback(void (*callback)(void))
4422 {
4423         WARN_ON(!init_tegra_dc_flip_callback_called);
4424
4425         spin_lock(&flip_callback_lock);
4426         flip_callback = callback;
4427         spin_unlock(&flip_callback_lock);
4428
4429         return 0;
4430 }
4431 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
4432
4433 int tegra_dc_unset_flip_callback(void)
4434 {
4435         spin_lock(&flip_callback_lock);
4436         flip_callback = NULL;
4437         spin_unlock(&flip_callback_lock);
4438
4439         return 0;
4440 }
4441 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
4442
4443 void tegra_dc_call_flip_callback(void)
4444 {
4445         spin_lock(&flip_callback_lock);
4446         if (flip_callback)
4447                 flip_callback();
4448         spin_unlock(&flip_callback_lock);
4449 }
4450 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
4451
4452 #ifdef CONFIG_SWITCH
4453 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
4454 {
4455         struct tegra_dc *dc =
4456                 container_of(sdev, struct tegra_dc, modeset_switch);
4457
4458         if (!sdev->state)
4459                 return sprintf(buf, "offline\n");
4460
4461         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
4462 }
4463 #endif
4464
4465 /* enables pads and clocks to perform DDC/I2C */
4466 int tegra_dc_ddc_enable(struct tegra_dc *dc, bool enabled)
4467 {
4468         int ret = -ENOSYS;
4469         if (dc->out_ops) {
4470                 if (enabled && dc->out_ops->ddc_enable)
4471                         ret = dc->out_ops->ddc_enable(dc);
4472                 else if (!enabled && dc->out_ops->ddc_disable)
4473                         ret = dc->out_ops->ddc_disable(dc);
4474         }
4475         return ret;
4476 }
4477
4478 int tegra_dc_slgc_disp0(struct notifier_block *nb,
4479         unsigned long unused0, void *unused1)
4480 {
4481 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4482         struct tegra_dc *dc = container_of(nb, struct tegra_dc, slgc_notifier);
4483         u32 val;
4484
4485         tegra_dc_get(dc);
4486
4487         val = tegra_dc_readl(dc, DC_COM_DSC_TOP_CTL);
4488         val |= DSC_SLCG_OVERRIDE;
4489         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* set */
4490         /* flush the previous write */
4491         (void)tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
4492         val &= ~DSC_SLCG_OVERRIDE;
4493         tegra_dc_writel(dc, val, DC_COM_DSC_TOP_CTL); /* restore */
4494
4495         tegra_dc_put(dc);
4496 #endif
4497         return NOTIFY_OK;
4498 }
4499
4500 struct clk *tegra_disp_of_clk_get_by_name(struct device_node *np,
4501                                                 const char *name)
4502 {
4503 #ifdef CONFIG_TEGRA_NVDISPLAY
4504         if (!tegra_platform_is_silicon() && !tegra_bpmp_running())
4505                 return of_clk_get_by_name(np, "clk32k_in");
4506 #endif
4507         return of_clk_get_by_name(np, name);
4508 }
4509
4510 struct clk *tegra_disp_clk_get(struct device *dev, const char *id)
4511 {
4512 #ifdef CONFIG_TEGRA_NVDISPLAY
4513         if (!tegra_platform_is_silicon() && !tegra_bpmp_running())
4514                 return of_clk_get_by_name(dev->of_node, "clk32k_in");
4515         else
4516                 return devm_clk_get(dev, id);
4517
4518 #else
4519         return clk_get(dev, id);
4520 #endif
4521 }
4522
4523 void tegra_disp_clk_put(struct device *dev, struct clk *clk)
4524 {
4525 #ifdef CONFIG_TEGRA_NVDISPLAY
4526         if (tegra_platform_is_silicon() || tegra_bpmp_running())
4527                 devm_clk_put(dev, clk);
4528 #else
4529         return clk_put(clk);
4530 #endif
4531 }
4532
4533 static int tegra_dc_probe(struct platform_device *ndev)
4534 {
4535         struct tegra_dc *dc;
4536         struct tegra_dc_mode *mode;
4537         struct tegra_dc_platform_data *dt_pdata = NULL;
4538         struct clk *clk;
4539 #ifndef CONFIG_TEGRA_ISOMGR
4540         struct clk *emc_clk;
4541 #else
4542         int isomgr_client_id = -1;
4543 #endif
4544         struct clk *emc_la_clk;
4545         struct device_node *np = ndev->dev.of_node;
4546         struct resource *res;
4547         struct resource dt_res;
4548         struct resource *base_res;
4549         struct resource *fb_mem = NULL;
4550         char clk_name[16];
4551         int ret = 0;
4552         void __iomem *base;
4553         int irq;
4554         int i;
4555 #ifndef CONFIG_TEGRA_NVDISPLAY
4556
4557 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4558         int partition_id_disa, partition_id_disb;
4559 #endif
4560 #endif
4561
4562 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
4563         if (tegra_platform_is_linsim()) {
4564                 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
4565                 return -ENODEV;
4566         }
4567 #endif
4568
4569         if (!np && !ndev->dev.platform_data) {
4570                 dev_err(&ndev->dev, "no platform data\n");
4571                 return -ENOENT;
4572         }
4573
4574         /* Specify parameters for the maximum physical segment size. */
4575         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
4576
4577         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
4578         if (!dc) {
4579                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
4580                 return -ENOMEM;
4581         }
4582
4583         if (np) {
4584 #ifdef CONFIG_OF
4585                 irq = of_irq_to_resource(np, 0, NULL);
4586                 if (!irq)
4587                         goto err_free;
4588 #endif
4589
4590                 ret = of_address_to_resource(np, 0, &dt_res);
4591                 if (ret)
4592                         goto err_free;
4593
4594                 ndev->id = tegra_dc_set(dc, -1);
4595                 if (ndev->id < 0) {
4596                         dev_err(&ndev->dev, "can't add dc\n");
4597                         goto err_free;
4598                 }
4599
4600                 dev_info(&ndev->dev, "Display dc.%08x registered with id=%d\n",
4601                                 (unsigned int)dt_res.start, ndev->id);
4602
4603                 res = &dt_res;
4604
4605                 dt_pdata = of_dc_parse_platform_data(ndev);
4606                 if (dt_pdata == NULL)
4607                         goto err_free;
4608
4609 #ifdef CONFIG_TEGRA_NVDISPLAY
4610                 dc->ctrl_num = dt_pdata->ctrl_num;
4611 #else
4612                 if (dt_res.start == TEGRA_DISPLAY_BASE)
4613                         dc->ctrl_num = 0;
4614                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
4615                         dc->ctrl_num = 1;
4616                 else
4617                         goto err_free;
4618 #endif
4619
4620         } else {
4621
4622                 dc->ctrl_num = ndev->id;
4623
4624                 irq = platform_get_irq_byname(ndev, "irq");
4625                 if (irq <= 0) {
4626                         dev_err(&ndev->dev, "no irq\n");
4627                         ret = -ENOENT;
4628                         goto err_free;
4629                 }
4630
4631                 res = platform_get_resource_byname(ndev,
4632                         IORESOURCE_MEM, "regs");
4633                 if (!res) {
4634                         dev_err(&ndev->dev, "no mem resource\n");
4635                         ret = -ENOENT;
4636                         goto err_free;
4637                 }
4638
4639                 if (tegra_dc_set(dc, ndev->id) < 0) {
4640                         dev_err(&ndev->dev, "can't add dc\n");
4641                         goto err_free;
4642                 }
4643
4644         }
4645
4646         base_res = request_mem_region(res->start, resource_size(res),
4647                 ndev->name);
4648         if (!base_res) {
4649                 dev_err(&ndev->dev, "request_mem_region failed\n");
4650                 ret = -EBUSY;
4651                 goto err_free;
4652         }
4653
4654         base = ioremap(res->start, resource_size(res));
4655         if (!base) {
4656                 dev_err(&ndev->dev, "registers can't be mapped\n");
4657                 ret = -EBUSY;
4658                 goto err_release_resource_reg;
4659         }
4660
4661 #ifndef CONFIG_TEGRA_NVDISPLAY
4662         for (i = 0; i < DC_N_WINDOWS; i++)
4663                 dc->windows[i].syncpt.id = NVSYNCPT_INVALID;
4664
4665         if (TEGRA_DISPLAY_BASE == res->start) {
4666                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
4667                 dc->windows[0].syncpt.id =
4668                         nvhost_get_syncpt_client_managed(ndev, "disp0_a");
4669                 dc->windows[1].syncpt.id =
4670                         nvhost_get_syncpt_client_managed(ndev, "disp0_b");
4671                 dc->windows[2].syncpt.id =
4672                         nvhost_get_syncpt_client_managed(ndev, "disp0_c");
4673                 dc->valid_windows = 0x07;
4674 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
4675                 dc->windows[3].syncpt.id =
4676                         nvhost_get_syncpt_client_managed(ndev, "disp0_d");
4677                 dc->windows[4].syncpt.id =
4678                         nvhost_get_syncpt_client_managed(ndev, "disp0_h");
4679                 dc->valid_windows |= 0x18;
4680 #elif !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
4681         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
4682         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
4683                 dc->windows[3].syncpt.id =
4684                         nvhost_get_syncpt_client_managed(ndev, "disp0_d");
4685                 dc->valid_windows |= 0x08;
4686 #endif
4687 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4688                 partition_id_disa = tegra_pd_get_powergate_id(tegra_disa_pd);
4689                 if (partition_id_disa < 0)
4690                         return -EINVAL;
4691
4692                 dc->powergate_id = partition_id_disa;
4693 #else
4694                 dc->powergate_id = TEGRA_POWERGATE_DISA;
4695 #endif
4696 #ifdef CONFIG_TEGRA_ISOMGR
4697                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
4698 #endif
4699                 dc->slgc_notifier.notifier_call = tegra_dc_slgc_disp0;
4700                 slcg_register_notifier(dc->powergate_id,
4701                         &dc->slgc_notifier);
4702         } else if (TEGRA_DISPLAY2_BASE == res->start) {
4703                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
4704                 dc->windows[0].syncpt.id =
4705                         nvhost_get_syncpt_client_managed(ndev, "disp1_a");
4706                 dc->windows[1].syncpt.id =
4707                         nvhost_get_syncpt_client_managed(ndev, "disp1_b");
4708                 dc->windows[2].syncpt.id =
4709                         nvhost_get_syncpt_client_managed(ndev, "disp1_c");
4710                 dc->valid_windows = 0x07;
4711 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
4712                 dc->windows[4].syncpt.id =
4713                         nvhost_get_syncpt_client_managed(ndev, "disp1_h");
4714                 dc->valid_windows |= 0x10;
4715 #endif
4716 #ifdef CONFIG_PM_GENERIC_DOMAINS_OF
4717                 partition_id_disb = tegra_pd_get_powergate_id(tegra_disb_pd);
4718                 if (partition_id_disb < 0)
4719                         return -EINVAL;
4720
4721                 dc->powergate_id = partition_id_disb;
4722 #else
4723                 dc->powergate_id = TEGRA_POWERGATE_DISB;
4724 #endif
4725 #ifdef CONFIG_TEGRA_ISOMGR
4726                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
4727 #endif
4728         } else {
4729                 dev_err(&ndev->dev,
4730                         "Unknown base address %llx: unable to assign syncpt\n",
4731                         (u64)res->start);
4732         }
4733 #endif  /* !CONFIG_TEGRA_NVDISPLAY */
4734
4735         if (np) {
4736                 struct resource of_fb_res;
4737 #ifdef CONFIG_TEGRA_NVDISPLAY
4738                 tegra_get_fb_resource(&of_fb_res);
4739 #else
4740                 if (dc->ctrl_num == 0)
4741                         tegra_get_fb_resource(&of_fb_res);
4742                 else /* dc->ctrl_num == 1*/
4743                         tegra_get_fb2_resource(&of_fb_res);
4744 #endif
4745
4746                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
4747                 if (fb_mem == NULL) {
4748                         ret = -ENOMEM;
4749                         goto err_iounmap_reg;
4750                 }
4751                 fb_mem->name = "fbmem";
4752                 fb_mem->flags = IORESOURCE_MEM;
4753                 fb_mem->start = (resource_size_t)of_fb_res.start;
4754                 fb_mem->end = (resource_size_t)of_fb_res.end;
4755         } else {
4756                 fb_mem = platform_get_resource_byname(ndev,
4757                         IORESOURCE_MEM, "fbmem");
4758                 if (fb_mem == NULL) {
4759                         ret = -ENOMEM;
4760                         goto err_iounmap_reg;
4761                 }
4762         }
4763
4764 #ifdef CONFIG_TEGRA_NVDISPLAY
4765         snprintf(clk_name, sizeof(clk_name), "nvdisplay_p%u", dc->ctrl_num);
4766 #else
4767         memset(clk_name, 0, sizeof(clk_name));
4768 #endif
4769         clk = tegra_disp_clk_get(&ndev->dev, clk_name);
4770         if (IS_ERR_OR_NULL(clk)) {
4771                 dev_err(&ndev->dev, "can't get clock\n");
4772                 ret = -ENOENT;
4773                 goto err_iounmap_reg;
4774         }
4775
4776         dc->clk = clk;
4777         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
4778         /* Initialize one shot work delay, it will be assigned by dsi
4779          * according to refresh rate later. */
4780         dc->one_shot_delay_ms = 40;
4781
4782         dc->base_res = base_res;
4783         dc->base = base;
4784         dc->irq = irq;
4785         dc->ndev = ndev;
4786         dc->fb_mem = fb_mem;
4787
4788         if (!np)
4789                 dc->pdata = ndev->dev.platform_data;
4790         else
4791                 dc->pdata = dt_pdata;
4792
4793         dc->bw_kbps = 0;
4794
4795 #ifdef CONFIG_TEGRA_NVDISPLAY
4796         /* dc variables need to initialized before nvdisp init */
4797         ret = tegra_nvdisp_init(dc);
4798         if (ret)
4799                 goto err_iounmap_reg;
4800 #endif
4801
4802         mutex_init(&dc->lock);
4803         mutex_init(&dc->one_shot_lock);
4804         mutex_init(&dc->lp_lock);
4805         init_completion(&dc->frame_end_complete);
4806         init_completion(&dc->crc_complete);
4807         init_waitqueue_head(&dc->wq);
4808         init_waitqueue_head(&dc->timestamp_wq);
4809 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
4810         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
4811 #endif
4812         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
4813         dc->vblank_ref_count = 0;
4814         INIT_WORK(&dc->frame_end_work, tegra_dc_frame_end);
4815 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
4816         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
4817 #endif
4818         dc->vpulse2_ref_count = 0;
4819         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
4820         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
4821
4822         tegra_dc_init_lut_defaults(&dc->fb_lut);
4823
4824         dc->n_windows = DC_N_WINDOWS;
4825         for (i = 0; i < DC_N_WINDOWS; i++) {
4826                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
4827 #ifdef CONFIG_TEGRA_NVDISPLAY
4828                 struct tegra_dc_win *win = &tegra_dc_windows[i];
4829 #else
4830                 struct tegra_dc_win *win = &dc->windows[i];
4831                 win->dc = dc;
4832 #endif
4833                 if (!test_bit(i, &dc->valid_windows))
4834                         win->flags |= TEGRA_WIN_FLAG_INVALID;
4835                 win->idx = i;
4836                 tmp_win->idx = i;
4837                 tmp_win->dc = dc;
4838 #if defined(CONFIG_TEGRA_CSC)
4839                 tegra_dc_init_csc_defaults(&win->csc);
4840 #endif
4841                 tegra_dc_init_lut_defaults(&win->lut);
4842         }
4843
4844         platform_set_drvdata(ndev, dc);
4845
4846 #ifdef CONFIG_SWITCH
4847         dc->modeset_switch.name = dev_name(&ndev->dev);
4848         dc->modeset_switch.state = 0;
4849         dc->modeset_switch.print_state = switch_modeset_print_mode;
4850         ret = switch_dev_register(&dc->modeset_switch);
4851         if (ret < 0) {
4852                 dev_err(&ndev->dev,
4853                         "failed to register switch driver ret(%d)\n", ret);
4854                 dc->switchdev_registered = false;
4855         } else
4856                 dc->switchdev_registered = true;
4857 #endif
4858
4859         tegra_dc_feature_register(dc);
4860
4861         if (dc->pdata->default_out) {
4862                 if (dc->pdata->default_out->hotplug_init)
4863                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
4864                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
4865                 if (ret < 0) {
4866                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
4867                         goto err_put_clk;
4868                 }
4869         } else {
4870                 dev_err(&ndev->dev,
4871                         "No default output specified.  Leaving output disabled.\n");
4872         }
4873         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
4874
4875         if ((dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) &&
4876                         dc->out && dc->out->type == TEGRA_DC_OUT_LVDS) {
4877                 struct fb_monspecs specs;
4878                 struct tegra_dc_lvds_data *lvds = tegra_dc_get_outdata(dc);
4879                 if (!tegra_edid_get_monspecs(lvds->edid, &specs))
4880                         tegra_dc_set_fb_mode(dc, specs.modedb, false);
4881         }
4882
4883 #ifndef CONFIG_TEGRA_ISOMGR
4884                 /*
4885                  * The emc is a shared clock, it will be set based on
4886                  * the requirements for each user on the bus.
4887                  */
4888                 emc_clk = tegra_disp_clk_get(&ndev->dev, "emc");
4889                 if (IS_ERR_OR_NULL(emc_clk)) {
4890                         dev_err(&ndev->dev, "can't get emc clock\n");
4891                         ret = -ENOENT;
4892                         goto err_put_clk;
4893                 }
4894                 dc->emc_clk = emc_clk;
4895 #endif
4896                 /*
4897                  * The emc_la clock is being added to set the floor value
4898                  * for emc depending on the LA calculaions for each window
4899                  */
4900 #ifdef CONFIG_TEGRA_NVDISPLAY
4901                 emc_la_clk = tegra_disp_clk_get(&ndev->dev, "emc_latency");
4902 #else
4903                 emc_la_clk = tegra_disp_clk_get(&ndev->dev, "emc.la");
4904 #endif
4905                 if (IS_ERR_OR_NULL(emc_la_clk)) {
4906                         dev_err(&ndev->dev, "can't get emc.la clock\n");
4907                         ret = -ENOENT;
4908                         goto err_put_clk;
4909                 }
4910                 dc->emc_la_clk = emc_la_clk;
4911                 clk_set_rate(dc->emc_la_clk, 0);
4912
4913 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
4914         dc->ext = tegra_dc_ext_register(ndev, dc);
4915         if (IS_ERR_OR_NULL(dc->ext)) {
4916                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
4917                 dc->ext = NULL;
4918         }
4919 #endif
4920
4921         /* interrupt handler must be registered before tegra_fb_register() */
4922         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
4923                         dev_name(&ndev->dev), dc)) {
4924                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
4925                 ret = -EBUSY;
4926                 goto err_disable_dc;
4927         }
4928         disable_dc_irq(dc);
4929
4930         tegra_pd_add_device(&ndev->dev);
4931         pm_runtime_use_autosuspend(&ndev->dev);
4932         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
4933         pm_runtime_enable(&ndev->dev);
4934
4935 #if defined(CONFIG_TEGRA_DC_CMU) || defined(CONFIG_TEGRA_DC_CMU_V2)
4936         /* if bootloader leaves this head enabled, then skip CMU programming. */
4937         dc->is_cmu_set_bl = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) != 0;
4938         dc->cmu_enabled = dc->pdata->cmu_enable;
4939 #endif
4940
4941         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
4942                 /* WAR: BL is putting DC in bad state for EDP configuration */
4943                 if (!tegra_platform_is_linsim() &&
4944                         (dc->out->type == TEGRA_DC_OUT_DP ||
4945                                 dc->out->type == TEGRA_DC_OUT_NVSR_DP)) {
4946                         tegra_disp_clk_prepare_enable(dc->clk);
4947                         tegra_periph_reset_assert(dc->clk);
4948                         udelay(10);
4949                         tegra_periph_reset_deassert(dc->clk);
4950                         udelay(10);
4951                         tegra_disp_clk_disable_unprepare(dc->clk);
4952                 }
4953
4954                 if (dc->out_ops && dc->out_ops->hotplug_init)
4955                         dc->out_ops->hotplug_init(dc);
4956
4957                 _tegra_dc_set_default_videomode(dc);
4958                 dc->enabled = _tegra_dc_enable(dc);
4959
4960 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
4961                 /* BL or PG init will keep DISA unpowergated after booting.
4962                  * Adding an extra powergate to balance the refcount
4963                  * since _tegra_dc_enable() increases the refcount.
4964                  */
4965                 if (!tegra_platform_is_fpga())
4966                         if (dc->powergate_id == TEGRA_POWERGATE_DISA)
4967                                 tegra_dc_powergate_locked(dc);
4968 #endif
4969         }
4970
4971 #ifdef CONFIG_TEGRA_ISOMGR
4972         if (isomgr_client_id == -1) {
4973                 dc->isomgr_handle = NULL;
4974         } else {
4975                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
4976                         tegra_dc_calc_min_bandwidth(dc),
4977                         tegra_dc_bandwidth_renegotiate, dc);
4978                 if (IS_ERR(dc->isomgr_handle)) {
4979                         dev_err(&dc->ndev->dev,
4980                                 "could not register isomgr. err=%ld\n",
4981                                 PTR_ERR(dc->isomgr_handle));
4982                         ret = -ENOENT;
4983                         goto err_put_clk;
4984                 }
4985                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
4986                 /*
4987                  * Use maximum value so we can try to reserve as much as
4988                  * needed until we are told by isomgr to backoff.
4989                  */
4990                 dc->available_bw = UINT_MAX;
4991         }
4992 #endif
4993
4994         tegra_dc_create_debugfs(dc);
4995
4996         dev_info(&ndev->dev, "probed\n");
4997
4998         if (dc->pdata->fb) {
4999                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
5000                         unsigned long fmt;
5001                         tegra_dc_writel(dc,
5002                                         WINDOW_A_SELECT << dc->pdata->fb->win,
5003                                         DC_CMD_DISPLAY_WINDOW_HEADER);
5004
5005                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
5006                         dc->pdata->fb->bits_per_pixel =
5007                                 tegra_dc_fmt_bpp(fmt);
5008                 }
5009
5010                 mode = tegra_dc_get_override_mode(dc);
5011                 if (mode) {
5012                         dc->pdata->fb->xres = mode->h_active;
5013                         dc->pdata->fb->yres = mode->v_active;
5014                 }
5015
5016 #ifdef CONFIG_ADF_TEGRA
5017                 tegra_dc_io_start(dc);
5018                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb, fb_mem);
5019                 tegra_dc_io_end(dc);
5020
5021                 if (IS_ERR(dc->adf)) {
5022                         tegra_dc_io_start(dc);
5023                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
5024                                 fb_mem);
5025                         tegra_dc_io_end(dc);
5026                         if (IS_ERR_OR_NULL(dc->fb)) {
5027                                 dc->fb = NULL;
5028                                 dev_err(&ndev->dev, "failed to register fb\n");
5029                                 goto err_remove_debugfs;
5030                         }
5031                 }
5032 #endif
5033 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5034                 tegra_dc_io_start(dc);
5035 #ifdef CONFIG_TEGRA_NVDISPLAY
5036                 dc->fb = tegra_nvdisp_fb_register(ndev, dc, dc->pdata->fb,
5037                         fb_mem);
5038 #else
5039                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem,
5040                         NULL);
5041 #endif
5042                 tegra_dc_io_end(dc);
5043                 if (IS_ERR_OR_NULL(dc->fb)) {
5044                         dc->fb = NULL;
5045                         dev_err(&ndev->dev, "failed to register fb\n");
5046                         goto err_remove_debugfs;
5047                 }
5048 #endif
5049         }
5050
5051         if (dc->out_ops) {
5052                 if (dc->out_ops->detect)
5053                         dc->connected = dc->out_ops->detect(dc);
5054                 else
5055                         dc->connected = true;
5056         } else
5057                 dc->connected = false;
5058
5059         /* Powergate display module when it's unconnected. */
5060         /* detect() function, if presetns, responsible for the powergate */
5061         if (!tegra_dc_get_connected(dc) &&
5062                         !(dc->out_ops && dc->out_ops->detect))
5063                 tegra_dc_powergate_locked(dc);
5064
5065         tegra_dc_create_sysfs(&dc->ndev->dev);
5066
5067         /*
5068          * Overriding the display mode only applies for modes set up during
5069          * boot. It should not apply for e.g. HDMI hotplug.
5070          */
5071         dc->initialized = false;
5072
5073         /*
5074          * Initialize vedid state. This is placed here
5075          * to allow persistence across sw HDMI hotplugs.
5076          */
5077         dc->vedid = false;
5078         dc->vedid_data = NULL;
5079
5080         return 0;
5081
5082 err_remove_debugfs:
5083         tegra_dc_remove_debugfs(dc);
5084         free_irq(irq, dc);
5085 err_disable_dc:
5086 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5087         if (dc->ext) {
5088                 tegra_dc_ext_disable(dc->ext);
5089                 tegra_dc_ext_unregister(dc->ext);
5090         }
5091 #endif
5092         mutex_lock(&dc->lock);
5093         if (dc->enabled)
5094                 _tegra_dc_disable(dc);
5095         dc->enabled = false;
5096         mutex_unlock(&dc->lock);
5097 #ifdef CONFIG_TEGRA_ISOMGR
5098         tegra_isomgr_unregister(dc->isomgr_handle);
5099 #else
5100         tegra_disp_clk_put(&ndev->dev, emc_clk);
5101 #endif
5102         tegra_disp_clk_put(&ndev->dev, dc->emc_la_clk);
5103 err_put_clk:
5104 #ifdef CONFIG_SWITCH
5105         if (dc->switchdev_registered)
5106                 switch_dev_unregister(&dc->modeset_switch);
5107 #endif
5108         tegra_disp_clk_put(&ndev->dev, clk);
5109 err_iounmap_reg:
5110         iounmap(base);
5111         if (fb_mem) {
5112                 if (!np)
5113                         release_resource(fb_mem);
5114                 else
5115                         kfree(fb_mem);
5116         }
5117 err_release_resource_reg:
5118         release_resource(base_res);
5119 err_free:
5120         kfree(dc);
5121         tegra_dc_set(NULL, ndev->id);
5122
5123         return ret;
5124 }
5125
5126 static int tegra_dc_remove(struct platform_device *ndev)
5127 {
5128         struct tegra_dc *dc = platform_get_drvdata(ndev);
5129         struct device_node *np = ndev->dev.of_node;
5130
5131         tegra_dc_remove_sysfs(&dc->ndev->dev);
5132         tegra_dc_remove_debugfs(dc);
5133
5134         if (dc->fb) {
5135                 tegra_fb_unregister(dc->fb);
5136                 if (dc->fb_mem) {
5137                         if (!np)
5138                                 release_resource(dc->fb_mem);
5139                         else
5140                                 kfree(dc->fb_mem);
5141                 }
5142         }
5143
5144 #ifdef CONFIG_ADF_TEGRA
5145         if (dc->adf)
5146                 tegra_adf_unregister(dc->adf);
5147 #endif
5148 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5149         if (dc->ext) {
5150                 tegra_dc_ext_disable(dc->ext);
5151                 tegra_dc_ext_unregister(dc->ext);
5152         }
5153 #endif
5154
5155         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
5156                 mutex_lock(&dc->one_shot_lock);
5157                 cancel_delayed_work_sync(&dc->one_shot_work);
5158         }
5159         mutex_lock(&dc->lock);
5160         if (dc->enabled)
5161                 _tegra_dc_disable(dc);
5162         dc->enabled = false;
5163         mutex_unlock(&dc->lock);
5164         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5165                 mutex_unlock(&dc->one_shot_lock);
5166         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
5167
5168 #ifdef CONFIG_SWITCH
5169         if (dc->switchdev_registered)
5170                 switch_dev_unregister(&dc->modeset_switch);
5171 #endif
5172         free_irq(dc->irq, dc);
5173 #ifdef CONFIG_TEGRA_ISOMGR
5174         if (dc->isomgr_handle) {
5175                 tegra_isomgr_unregister(dc->isomgr_handle);
5176                 dc->isomgr_handle = NULL;
5177         }
5178 #else
5179         tegra_disp_clk_put(&ndev->dev, dc->emc_clk);
5180 #endif
5181         tegra_disp_clk_put(&ndev->dev, dc->emc_la_clk);
5182
5183         tegra_disp_clk_put(&ndev->dev, dc->clk);
5184         iounmap(dc->base);
5185         if (dc->fb_mem)
5186                 release_resource(dc->base_res);
5187         kfree(dc);
5188         tegra_dc_set(NULL, ndev->id);
5189
5190         return 0;
5191 }
5192
5193 #ifdef CONFIG_PM
5194 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
5195 {
5196         struct tegra_dc *dc = platform_get_drvdata(ndev);
5197         int ret = 0;
5198
5199         trace_display_suspend(dc);
5200         dev_info(&ndev->dev, "suspend\n");
5201
5202 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5203         tegra_dc_ext_disable(dc->ext);
5204 #endif
5205
5206         tegra_dc_cursor_suspend(dc);
5207
5208         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
5209                 mutex_lock(&dc->one_shot_lock);
5210                 cancel_delayed_work_sync(&dc->one_shot_work);
5211         }
5212         mutex_lock(&dc->lock);
5213         ret = tegra_dc_io_start(dc);
5214
5215         if (dc->out_ops && dc->out_ops->suspend)
5216                 dc->out_ops->suspend(dc);
5217
5218         if (dc->enabled) {
5219                 _tegra_dc_disable(dc);
5220
5221                 dc->suspended = true;
5222         }
5223
5224         if (dc->out && dc->out->postsuspend) {
5225                 dc->out->postsuspend();
5226                 /* avoid resume event due to voltage falling on interfaces that
5227                  * support hotplug wake. And only do this if a panel is
5228                  * connected, if we are already disconnected, then no phantom
5229                  * hotplug can occur by disabling the voltage.
5230                  */
5231                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
5232                         && tegra_dc_get_connected(dc))
5233                         msleep(100);
5234         }
5235
5236         if (!ret)
5237                 tegra_dc_io_end(dc);
5238
5239         mutex_unlock(&dc->lock);
5240         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
5241                 mutex_unlock(&dc->one_shot_lock);
5242         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
5243
5244         return 0;
5245 }
5246
5247 static int tegra_dc_resume(struct platform_device *ndev)
5248 {
5249         struct tegra_dc *dc = platform_get_drvdata(ndev);
5250
5251         trace_display_resume(dc);
5252         dev_info(&ndev->dev, "resume\n");
5253
5254         mutex_lock(&dc->lock);
5255         dc->suspended = false;
5256
5257         /* To pan the fb on resume */
5258         tegra_fb_pan_display_reset(dc->fb);
5259
5260         if (dc->enabled) {
5261                 dc->enabled = false;
5262                 _tegra_dc_set_default_videomode(dc);
5263                 dc->enabled = _tegra_dc_enable(dc);
5264         }
5265
5266         if (dc->out && dc->out->hotplug_init)
5267                 dc->out->hotplug_init(&ndev->dev);
5268
5269         if (dc->out_ops && dc->out_ops->resume)
5270                 dc->out_ops->resume(dc);
5271
5272         mutex_unlock(&dc->lock);
5273         tegra_dc_cursor_resume(dc);
5274
5275         return 0;
5276 }
5277
5278 #endif /* CONFIG_PM */
5279
5280 static void tegra_dc_shutdown(struct platform_device *ndev)
5281 {
5282         struct tegra_dc *dc = platform_get_drvdata(ndev);
5283
5284         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
5285                 return;
5286
5287         if (!dc->enabled)
5288                 return;
5289
5290         kfree(dc->vedid_data);
5291         dc->vedid_data = NULL;
5292         dc->vedid = false;
5293
5294
5295         /* Let dc clients know about shutdown event before calling disable */
5296         if (dc->out_ops && dc->out_ops->shutdown)
5297                 dc->out_ops->shutdown(dc);
5298
5299         tegra_dc_disable(dc);
5300 }
5301
5302 static int suspend_set(const char *val, struct kernel_param *kp)
5303 {
5304         if (!strcmp(val, "dump"))
5305                 dump_regs(tegra_dcs[0]);
5306 #ifdef CONFIG_PM
5307         else if (!strcmp(val, "suspend"))
5308                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
5309         else if (!strcmp(val, "resume"))
5310                 tegra_dc_resume(tegra_dcs[0]->ndev);
5311 #endif
5312
5313         return 0;
5314 }
5315
5316 static int suspend_get(char *buffer, struct kernel_param *kp)
5317 {
5318         return 0;
5319 }
5320
5321 static int suspend;
5322
5323 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
5324
5325
5326 #ifdef CONFIG_OF
5327 static struct of_device_id tegra_display_of_match[] = {
5328         {.compatible = "nvidia,tegra114-dc", },
5329         {.compatible = "nvidia,tegra124-dc", },
5330         {.compatible = "nvidia,tegra210-dc", },
5331         {.compatible = "nvidia,tegra186-dc", },
5332         { },
5333 };
5334 #endif
5335
5336 static struct platform_driver tegra_dc_driver = {
5337         .driver = {
5338                 .name = "tegradc",
5339                 .owner = THIS_MODULE,
5340 #ifdef CONFIG_OF
5341                 .of_match_table =
5342                         of_match_ptr(tegra_display_of_match),
5343 #endif
5344         },
5345         .probe = tegra_dc_probe,
5346         .remove = tegra_dc_remove,
5347 #ifdef CONFIG_PM
5348         .suspend = tegra_dc_suspend,
5349         .resume = tegra_dc_resume,
5350 #endif
5351         .shutdown = tegra_dc_shutdown,
5352 };
5353
5354 #ifndef MODULE
5355 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
5356 {
5357         int i, params[11];
5358         char *p;
5359
5360         for (i = 0; i < ARRAY_SIZE(params); i++) {
5361                 if ((p = strsep(&options, ",")) != NULL) {
5362                         if (*p)
5363                                 params[i] = simple_strtoul(p, &p, 10);
5364                 } else
5365                         return -EINVAL;
5366         }
5367
5368         if ((mode->pclk = params[0]) == 0)
5369                 return -EINVAL;
5370
5371         mode->h_active      = params[1];
5372         mode->v_active      = params[2];
5373         mode->h_ref_to_sync = params[3];
5374         mode->v_ref_to_sync = params[4];
5375         mode->h_sync_width  = params[5];
5376         mode->v_sync_width  = params[6];
5377         mode->h_back_porch  = params[7];
5378         mode->v_back_porch  = params[8];
5379         mode->h_front_porch = params[9];
5380         mode->v_front_porch = params[10];
5381
5382         return 0;
5383 }
5384
5385 static int __init tegra_dc_mode_override(char *str)
5386 {
5387         char *p = str, *options;
5388
5389         if (!p || !*p)
5390                 return -EINVAL;
5391
5392         p = strstr(str, "hdmi:");
5393         if (p) {
5394                 p += 5;
5395                 options = strsep(&p, ";");
5396                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
5397                         return -EINVAL;
5398         }
5399
5400         p = strstr(str, "rgb:");
5401         if (p) {
5402                 p += 4;
5403                 options = strsep(&p, ";");
5404                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
5405                         return -EINVAL;
5406         }
5407
5408         p = strstr(str, "dsi:");
5409         if (p) {
5410                 p += 4;
5411                 options = strsep(&p, ";");
5412                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
5413                         return -EINVAL;
5414         }
5415
5416         p = strstr(str, "null:");
5417         if (p) {
5418                 p += 5;
5419                 options = strsep(&p, ";");
5420                 if (parse_disp_params(options,
5421                                 &override_disp_mode[TEGRA_DC_OUT_NULL]))
5422                         return -EINVAL;
5423         }
5424
5425         return 0;
5426 }
5427
5428 __setup("disp_params=", tegra_dc_mode_override);
5429 #endif
5430
5431 static int __init tegra_dc_module_init(void)
5432 {
5433 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5434         int ret = tegra_dc_ext_module_init();
5435         if (ret)
5436                 return ret;
5437 #endif
5438         return platform_driver_register(&tegra_dc_driver);
5439 }
5440
5441 static void __exit tegra_dc_module_exit(void)
5442 {
5443         platform_driver_unregister(&tegra_dc_driver);
5444 #ifdef CONFIG_TEGRA_DC_EXTENSIONS
5445         tegra_dc_ext_module_exit();
5446 #endif
5447 }
5448
5449 module_exit(tegra_dc_module_exit);
5450 module_init(tegra_dc_module_init);