260af95d313135f876db2591eb8da922bd097fdf
[linux-3.10.git] / drivers / video / tegra / dc / dc.c
1 /*
2  * drivers/video/tegra/dc/dc.c
3  *
4  * Copyright (C) 2010 Google, Inc.
5  * Author: Erik Gilling <konkers@android.com>
6  *
7  * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
8  *
9  * This software is licensed under the terms of the GNU General Public
10  * License version 2, as published by the Free Software Foundation, and
11  * may be copied, distributed, and modified under those terms.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  */
19
20 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/err.h>
23 #include <linux/errno.h>
24 #include <linux/interrupt.h>
25 #include <linux/slab.h>
26 #include <linux/io.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/clk.h>
30 #include <linux/mutex.h>
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/workqueue.h>
34 #include <linux/ktime.h>
35 #include <linux/debugfs.h>
36 #include <linux/seq_file.h>
37 #include <linux/backlight.h>
38 #include <linux/gpio.h>
39 #include <linux/nvhost.h>
40 #include <linux/clk/tegra.h>
41 #include <video/tegrafb.h>
42 #include <drm/drm_fixed.h>
43 #ifdef CONFIG_SWITCH
44 #include <linux/switch.h>
45 #endif
46 #include <linux/of_irq.h>
47 #include <linux/of_address.h>
48 #include <linux/tegra_pm_domains.h>
49
50 #define CREATE_TRACE_POINTS
51 #include <trace/events/display.h>
52 EXPORT_TRACEPOINT_SYMBOL(display_writel);
53 EXPORT_TRACEPOINT_SYMBOL(display_readl);
54
55 #include <mach/dc.h>
56 #include <mach/fb.h>
57 #include <mach/mc.h>
58 #include <linux/nvhost.h>
59 #include <linux/nvhost_ioctl.h>
60 #include <mach/latency_allowance.h>
61
62 #include "dc_reg.h"
63 #include "dc_config.h"
64 #include "dc_priv.h"
65 #include "dev.h"
66 #include "nvhost_sync.h"
67 #include "nvsd.h"
68 #include "dp.h"
69 #include "nvsr.h"
70
71 #ifdef CONFIG_ADF_TEGRA
72 #include "tegra_adf.h"
73 #endif
74
75 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
76 #include "hdmi.h"
77 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
78
79 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
80 #include "fake_panel.h"
81 #include "null_or.h"
82 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
83
84
85 /* HACK! This needs to come from DT */
86 #include "../../../../arch/arm/mach-tegra/iomap.h"
87
88 #define DPAUX_NODE              "/host1x/dpaux"
89
90 #define TEGRA_CRC_LATCHED_DELAY         34
91
92 #define DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL    0x01000000
93 #define DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL    0x0
94
95 static struct fb_videomode tegra_dc_vga_mode = {
96         .refresh = 60,
97         .xres = 640,
98         .yres = 480,
99         .pixclock = KHZ2PICOS(25200),
100         .hsync_len = 96,        /* h_sync_width */
101         .vsync_len = 2,         /* v_sync_width */
102         .left_margin = 48,      /* h_back_porch */
103         .upper_margin = 33,     /* v_back_porch */
104         .right_margin = 16,     /* h_front_porch */
105         .lower_margin = 10,     /* v_front_porch */
106         .vmode = 0,
107         .sync = 0,
108 };
109
110 /* needs to be big enough to be index by largest supported out->type */
111 static struct tegra_dc_mode override_disp_mode[TEGRA_DC_OUT_NULL + 1];
112
113 static void _tegra_dc_controller_disable(struct tegra_dc *dc);
114
115 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out);
116 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state);
117 static int tegra_dc_resume(struct platform_device *ndev);
118
119 struct tegra_dc *tegra_dcs[TEGRA_MAX_DC];
120
121 DEFINE_MUTEX(tegra_dc_lock);
122 DEFINE_MUTEX(shared_lock);
123
124 static struct device_dma_parameters tegra_dc_dma_parameters = {
125         .max_segment_size = UINT_MAX,
126 };
127
128 static const struct {
129         bool h;
130         bool v;
131 } can_filter[] = {
132         /* Window A has no filtering */
133         { false, false },
134         /* Window B has both H and V filtering */
135         { true,  true  },
136         /* Window C has only H filtering */
137         { false, true  },
138 };
139
140 #ifdef CONFIG_TEGRA_DC_CMU
141 static struct tegra_dc_cmu default_cmu = {
142         /* lut1 maps sRGB to linear space. */
143         {
144                 0,    1,    2,    4,    5,    6,    7,    9,
145                 10,   11,   12,   14,   15,   16,   18,   20,
146                 21,   23,   25,   27,   29,   31,   33,   35,
147                 37,   40,   42,   45,   48,   50,   53,   56,
148                 59,   62,   66,   69,   72,   76,   79,   83,
149                 87,   91,   95,   99,   103,  107,  112,  116,
150                 121,  126,  131,  136,  141,  146,  151,  156,
151                 162,  168,  173,  179,  185,  191,  197,  204,
152                 210,  216,  223,  230,  237,  244,  251,  258,
153                 265,  273,  280,  288,  296,  304,  312,  320,
154                 329,  337,  346,  354,  363,  372,  381,  390,
155                 400,  409,  419,  428,  438,  448,  458,  469,
156                 479,  490,  500,  511,  522,  533,  544,  555,
157                 567,  578,  590,  602,  614,  626,  639,  651,
158                 664,  676,  689,  702,  715,  728,  742,  755,
159                 769,  783,  797,  811,  825,  840,  854,  869,
160                 884,  899,  914,  929,  945,  960,  976,  992,
161                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
162                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
163                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
164                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
165                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
166                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
167                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
168                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
169                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
170                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
171                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
172                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
173                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
174                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
175                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
176         },
177         /* csc */
178         {
179                 0x100, 0x0,   0x0,
180                 0x0,   0x100, 0x0,
181                 0x0,   0x0,   0x100,
182         },
183         /* lut2 maps linear space to sRGB*/
184         {
185                 0,    1,    2,    2,    3,    4,    5,    6,
186                 6,    7,    8,    9,    10,   10,   11,   12,
187                 13,   13,   14,   15,   15,   16,   16,   17,
188                 18,   18,   19,   19,   20,   20,   21,   21,
189                 22,   22,   23,   23,   23,   24,   24,   25,
190                 25,   25,   26,   26,   27,   27,   27,   28,
191                 28,   29,   29,   29,   30,   30,   30,   31,
192                 31,   31,   32,   32,   32,   33,   33,   33,
193                 34,   34,   34,   34,   35,   35,   35,   36,
194                 36,   36,   37,   37,   37,   37,   38,   38,
195                 38,   38,   39,   39,   39,   40,   40,   40,
196                 40,   41,   41,   41,   41,   42,   42,   42,
197                 42,   43,   43,   43,   43,   43,   44,   44,
198                 44,   44,   45,   45,   45,   45,   46,   46,
199                 46,   46,   46,   47,   47,   47,   47,   48,
200                 48,   48,   48,   48,   49,   49,   49,   49,
201                 49,   50,   50,   50,   50,   50,   51,   51,
202                 51,   51,   51,   52,   52,   52,   52,   52,
203                 53,   53,   53,   53,   53,   54,   54,   54,
204                 54,   54,   55,   55,   55,   55,   55,   55,
205                 56,   56,   56,   56,   56,   57,   57,   57,
206                 57,   57,   57,   58,   58,   58,   58,   58,
207                 58,   59,   59,   59,   59,   59,   59,   60,
208                 60,   60,   60,   60,   60,   61,   61,   61,
209                 61,   61,   61,   62,   62,   62,   62,   62,
210                 62,   63,   63,   63,   63,   63,   63,   64,
211                 64,   64,   64,   64,   64,   64,   65,   65,
212                 65,   65,   65,   65,   66,   66,   66,   66,
213                 66,   66,   66,   67,   67,   67,   67,   67,
214                 67,   67,   68,   68,   68,   68,   68,   68,
215                 68,   69,   69,   69,   69,   69,   69,   69,
216                 70,   70,   70,   70,   70,   70,   70,   71,
217                 71,   71,   71,   71,   71,   71,   72,   72,
218                 72,   72,   72,   72,   72,   72,   73,   73,
219                 73,   73,   73,   73,   73,   74,   74,   74,
220                 74,   74,   74,   74,   74,   75,   75,   75,
221                 75,   75,   75,   75,   75,   76,   76,   76,
222                 76,   76,   76,   76,   77,   77,   77,   77,
223                 77,   77,   77,   77,   78,   78,   78,   78,
224                 78,   78,   78,   78,   78,   79,   79,   79,
225                 79,   79,   79,   79,   79,   80,   80,   80,
226                 80,   80,   80,   80,   80,   81,   81,   81,
227                 81,   81,   81,   81,   81,   81,   82,   82,
228                 82,   82,   82,   82,   82,   82,   83,   83,
229                 83,   83,   83,   83,   83,   83,   83,   84,
230                 84,   84,   84,   84,   84,   84,   84,   84,
231                 85,   85,   85,   85,   85,   85,   85,   85,
232                 85,   86,   86,   86,   86,   86,   86,   86,
233                 86,   86,   87,   87,   87,   87,   87,   87,
234                 87,   87,   87,   88,   88,   88,   88,   88,
235                 88,   88,   88,   88,   88,   89,   89,   89,
236                 89,   89,   89,   89,   89,   89,   90,   90,
237                 90,   90,   90,   90,   90,   90,   90,   90,
238                 91,   91,   91,   91,   91,   91,   91,   91,
239                 91,   91,   92,   92,   92,   92,   92,   92,
240                 92,   92,   92,   92,   93,   93,   93,   93,
241                 93,   93,   93,   93,   93,   93,   94,   94,
242                 94,   94,   94,   94,   94,   94,   94,   94,
243                 95,   95,   95,   95,   95,   95,   95,   95,
244                 95,   95,   96,   96,   96,   96,   96,   96,
245                 96,   96,   96,   96,   96,   97,   97,   97,
246                 97,   97,   97,   97,   97,   97,   97,   98,
247                 98,   98,   98,   98,   98,   98,   98,   98,
248                 98,   98,   99,   99,   99,   99,   99,   99,
249                 99,   100,  101,  101,  102,  103,  103,  104,
250                 105,  105,  106,  107,  107,  108,  109,  109,
251                 110,  111,  111,  112,  113,  113,  114,  115,
252                 115,  116,  116,  117,  118,  118,  119,  119,
253                 120,  120,  121,  122,  122,  123,  123,  124,
254                 124,  125,  126,  126,  127,  127,  128,  128,
255                 129,  129,  130,  130,  131,  131,  132,  132,
256                 133,  133,  134,  134,  135,  135,  136,  136,
257                 137,  137,  138,  138,  139,  139,  140,  140,
258                 141,  141,  142,  142,  143,  143,  144,  144,
259                 145,  145,  145,  146,  146,  147,  147,  148,
260                 148,  149,  149,  150,  150,  150,  151,  151,
261                 152,  152,  153,  153,  153,  154,  154,  155,
262                 155,  156,  156,  156,  157,  157,  158,  158,
263                 158,  159,  159,  160,  160,  160,  161,  161,
264                 162,  162,  162,  163,  163,  164,  164,  164,
265                 165,  165,  166,  166,  166,  167,  167,  167,
266                 168,  168,  169,  169,  169,  170,  170,  170,
267                 171,  171,  172,  172,  172,  173,  173,  173,
268                 174,  174,  174,  175,  175,  176,  176,  176,
269                 177,  177,  177,  178,  178,  178,  179,  179,
270                 179,  180,  180,  180,  181,  181,  182,  182,
271                 182,  183,  183,  183,  184,  184,  184,  185,
272                 185,  185,  186,  186,  186,  187,  187,  187,
273                 188,  188,  188,  189,  189,  189,  189,  190,
274                 190,  190,  191,  191,  191,  192,  192,  192,
275                 193,  193,  193,  194,  194,  194,  195,  195,
276                 195,  196,  196,  196,  196,  197,  197,  197,
277                 198,  198,  198,  199,  199,  199,  200,  200,
278                 200,  200,  201,  201,  201,  202,  202,  202,
279                 202,  203,  203,  203,  204,  204,  204,  205,
280                 205,  205,  205,  206,  206,  206,  207,  207,
281                 207,  207,  208,  208,  208,  209,  209,  209,
282                 209,  210,  210,  210,  211,  211,  211,  211,
283                 212,  212,  212,  213,  213,  213,  213,  214,
284                 214,  214,  214,  215,  215,  215,  216,  216,
285                 216,  216,  217,  217,  217,  217,  218,  218,
286                 218,  219,  219,  219,  219,  220,  220,  220,
287                 220,  221,  221,  221,  221,  222,  222,  222,
288                 223,  223,  223,  223,  224,  224,  224,  224,
289                 225,  225,  225,  225,  226,  226,  226,  226,
290                 227,  227,  227,  227,  228,  228,  228,  228,
291                 229,  229,  229,  229,  230,  230,  230,  230,
292                 231,  231,  231,  231,  232,  232,  232,  232,
293                 233,  233,  233,  233,  234,  234,  234,  234,
294                 235,  235,  235,  235,  236,  236,  236,  236,
295                 237,  237,  237,  237,  238,  238,  238,  238,
296                 239,  239,  239,  239,  240,  240,  240,  240,
297                 240,  241,  241,  241,  241,  242,  242,  242,
298                 242,  243,  243,  243,  243,  244,  244,  244,
299                 244,  244,  245,  245,  245,  245,  246,  246,
300                 246,  246,  247,  247,  247,  247,  247,  248,
301                 248,  248,  248,  249,  249,  249,  249,  249,
302                 250,  250,  250,  250,  251,  251,  251,  251,
303                 251,  252,  252,  252,  252,  253,  253,  253,
304                 253,  253,  254,  254,  254,  254,  255,  255,
305         },
306 };
307
308 static struct tegra_dc_cmu default_limited_cmu = {
309         /* lut1 maps sRGB to linear space. */
310         {
311                 0,    1,    2,    4,    5,    6,    7,    9,
312                 10,   11,   12,   14,   15,   16,   18,   20,
313                 21,   23,   25,   27,   29,   31,   33,   35,
314                 37,   40,   42,   45,   48,   50,   53,   56,
315                 59,   62,   66,   69,   72,   76,   79,   83,
316                 87,   91,   95,   99,   103,  107,  112,  116,
317                 121,  126,  131,  136,  141,  146,  151,  156,
318                 162,  168,  173,  179,  185,  191,  197,  204,
319                 210,  216,  223,  230,  237,  244,  251,  258,
320                 265,  273,  280,  288,  296,  304,  312,  320,
321                 329,  337,  346,  354,  363,  372,  381,  390,
322                 400,  409,  419,  428,  438,  448,  458,  469,
323                 479,  490,  500,  511,  522,  533,  544,  555,
324                 567,  578,  590,  602,  614,  626,  639,  651,
325                 664,  676,  689,  702,  715,  728,  742,  755,
326                 769,  783,  797,  811,  825,  840,  854,  869,
327                 884,  899,  914,  929,  945,  960,  976,  992,
328                 1008, 1024, 1041, 1057, 1074, 1091, 1108, 1125,
329                 1142, 1159, 1177, 1195, 1213, 1231, 1249, 1267,
330                 1286, 1304, 1323, 1342, 1361, 1381, 1400, 1420,
331                 1440, 1459, 1480, 1500, 1520, 1541, 1562, 1582,
332                 1603, 1625, 1646, 1668, 1689, 1711, 1733, 1755,
333                 1778, 1800, 1823, 1846, 1869, 1892, 1916, 1939,
334                 1963, 1987, 2011, 2035, 2059, 2084, 2109, 2133,
335                 2159, 2184, 2209, 2235, 2260, 2286, 2312, 2339,
336                 2365, 2392, 2419, 2446, 2473, 2500, 2527, 2555,
337                 2583, 2611, 2639, 2668, 2696, 2725, 2754, 2783,
338                 2812, 2841, 2871, 2901, 2931, 2961, 2991, 3022,
339                 3052, 3083, 3114, 3146, 3177, 3209, 3240, 3272,
340                 3304, 3337, 3369, 3402, 3435, 3468, 3501, 3535,
341                 3568, 3602, 3636, 3670, 3705, 3739, 3774, 3809,
342                 3844, 3879, 3915, 3950, 3986, 4022, 4059, 4095,
343         },
344         /* csc */
345         {
346                 0x100, 0x000, 0x000,
347                 0x000, 0x100, 0x000,
348                 0x000, 0x000, 0x100,
349         },
350         /*
351          * lut2 maps linear space back to sRGB, where
352          * the output range is [16...235] (limited).
353          */
354         {
355                 16,  17,  17,  18,  19,  19,  20,  21,
356                 22,  22,  23,  24,  24,  25,  26,  26,
357                 27,  27,  28,  29,  29,  30,  30,  31,
358                 31,  32,  32,  32,  33,  33,  34,  34,
359                 35,  35,  35,  36,  36,  36,  37,  37,
360                 38,  38,  38,  39,  39,  39,  40,  40,
361                 40,  41,  41,  41,  41,  42,  42,  42,
362                 43,  43,  43,  43,  44,  44,  44,  45,
363                 45,  45,  45,  46,  46,  46,  46,  47,
364                 47,  47,  47,  48,  48,  48,  48,  49,
365                 49,  49,  49,  49,  50,  50,  50,  50,
366                 51,  51,  51,  51,  51,  52,  52,  52,
367                 52,  53,  53,  53,  53,  53,  54,  54,
368                 54,  54,  54,  55,  55,  55,  55,  55,
369                 56,  56,  56,  56,  56,  56,  57,  57,
370                 57,  57,  57,  58,  58,  58,  58,  58,
371                 58,  59,  59,  59,  59,  59,  60,  60,
372                 60,  60,  60,  60,  61,  61,  61,  61,
373                 61,  61,  62,  62,  62,  62,  62,  62,
374                 63,  63,  63,  63,  63,  63,  63,  64,
375                 64,  64,  64,  64,  64,  65,  65,  65,
376                 65,  65,  65,  65,  66,  66,  66,  66,
377                 66,  66,  67,  67,  67,  67,  67,  67,
378                 67,  68,  68,  68,  68,  68,  68,  68,
379                 69,  69,  69,  69,  69,  69,  69,  69,
380                 70,  70,  70,  70,  70,  70,  70,  71,
381                 71,  71,  71,  71,  71,  71,  72,  72,
382                 72,  72,  72,  72,  72,  72,  73,  73,
383                 73,  73,  73,  73,  73,  73,  74,  74,
384                 74,  74,  74,  74,  74,  74,  75,  75,
385                 75,  75,  75,  75,  75,  75,  76,  76,
386                 76,  76,  76,  76,  76,  76,  76,  77,
387                 77,  77,  77,  77,  77,  77,  77,  78,
388                 78,  78,  78,  78,  78,  78,  78,  78,
389                 79,  79,  79,  79,  79,  79,  79,  79,
390                 80,  80,  80,  80,  80,  80,  80,  80,
391                 80,  81,  81,  81,  81,  81,  81,  81,
392                 81,  81,  81,  82,  82,  82,  82,  82,
393                 82,  82,  82,  82,  83,  83,  83,  83,
394                 83,  83,  83,  83,  83,  84,  84,  84,
395                 84,  84,  84,  84,  84,  84,  84,  85,
396                 85,  85,  85,  85,  85,  85,  85,  85,
397                 85,  86,  86,  86,  86,  86,  86,  86,
398                 86,  86,  86,  87,  87,  87,  87,  87,
399                 87,  87,  87,  87,  87,  88,  88,  88,
400                 88,  88,  88,  88,  88,  88,  88,  89,
401                 89,  89,  89,  89,  89,  89,  89,  89,
402                 89,  89,  90,  90,  90,  90,  90,  90,
403                 90,  90,  90,  90,  91,  91,  91,  91,
404                 91,  91,  91,  91,  91,  91,  91,  92,
405                 92,  92,  92,  92,  92,  92,  92,  92,
406                 92,  92,  93,  93,  93,  93,  93,  93,
407                 93,  93,  93,  93,  93,  94,  94,  94,
408                 94,  94,  94,  94,  94,  94,  94,  94,
409                 94,  95,  95,  95,  95,  95,  95,  95,
410                 95,  95,  95,  95,  96,  96,  96,  96,
411                 96,  96,  96,  96,  96,  96,  96,  96,
412                 97,  97,  97,  97,  97,  97,  97,  97,
413                 97,  97,  97,  97,  98,  98,  98,  98,
414                 98,  98,  98,  98,  98,  98,  98,  98,
415                 99,  99,  99,  99,  99,  99,  99,  99,
416                 99,  99,  99,  99, 100, 100, 100, 100,
417                 100, 100, 100, 100, 100, 100, 100, 100,
418                 100, 101, 101, 101, 101, 101, 101, 101,
419                 102, 102, 103, 104, 104, 105, 105, 106,
420                 107, 107, 108, 108, 109, 109, 110, 111,
421                 111, 112, 112, 113, 113, 114, 114, 115,
422                 115, 116, 116, 117, 117, 118, 118, 119,
423                 119, 120, 120, 121, 121, 122, 122, 123,
424                 123, 124, 124, 125, 125, 126, 126, 127,
425                 127, 127, 128, 128, 129, 129, 130, 130,
426                 131, 131, 131, 132, 132, 133, 133, 134,
427                 134, 134, 135, 135, 136, 136, 136, 137,
428                 137, 138, 138, 139, 139, 139, 140, 140,
429                 141, 141, 141, 142, 142, 142, 143, 143,
430                 144, 144, 144, 145, 145, 145, 146, 146,
431                 147, 147, 147, 148, 148, 148, 149, 149,
432                 150, 150, 150, 151, 151, 151, 152, 152,
433                 152, 153, 153, 153, 154, 154, 154, 155,
434                 155, 155, 156, 156, 156, 157, 157, 157,
435                 158, 158, 158, 159, 159, 159, 160, 160,
436                 160, 161, 161, 161, 162, 162, 162, 163,
437                 163, 163, 164, 164, 164, 165, 165, 165,
438                 166, 166, 166, 166, 167, 167, 167, 168,
439                 168, 168, 169, 169, 169, 169, 170, 170,
440                 170, 171, 171, 171, 172, 172, 172, 172,
441                 173, 173, 173, 174, 174, 174, 174, 175,
442                 175, 175, 176, 176, 176, 176, 177, 177,
443                 177, 178, 178, 178, 178, 179, 179, 179,
444                 180, 180, 180, 180, 181, 181, 181, 181,
445                 182, 182, 182, 183, 183, 183, 183, 184,
446                 184, 184, 184, 185, 185, 185, 185, 186,
447                 186, 186, 187, 187, 187, 187, 188, 188,
448                 188, 188, 189, 189, 189, 189, 190, 190,
449                 190, 190, 191, 191, 191, 191, 192, 192,
450                 192, 192, 193, 193, 193, 193, 194, 194,
451                 194, 194, 195, 195, 195, 195, 196, 196,
452                 196, 196, 197, 197, 197, 197, 198, 198,
453                 198, 198, 199, 199, 199, 199, 199, 200,
454                 200, 200, 200, 201, 201, 201, 201, 202,
455                 202, 202, 202, 203, 203, 203, 203, 203,
456                 204, 204, 204, 204, 205, 205, 205, 205,
457                 206, 206, 206, 206, 206, 207, 207, 207,
458                 207, 208, 208, 208, 208, 208, 209, 209,
459                 209, 209, 210, 210, 210, 210, 210, 211,
460                 211, 211, 211, 212, 212, 212, 212, 212,
461                 213, 213, 213, 213, 213, 214, 214, 214,
462                 214, 215, 215, 215, 215, 215, 216, 216,
463                 216, 216, 216, 217, 217, 217, 217, 218,
464                 218, 218, 218, 218, 219, 219, 219, 219,
465                 219, 220, 220, 220, 220, 220, 221, 221,
466                 221, 221, 221, 222, 222, 222, 222, 222,
467                 223, 223, 223, 223, 224, 224, 224, 224,
468                 224, 225, 225, 225, 225, 225, 226, 226,
469                 226, 226, 226, 227, 227, 227, 227, 227,
470                 227, 228, 228, 228, 228, 228, 229, 229,
471                 229, 229, 229, 230, 230, 230, 230, 230,
472                 231, 231, 231, 231, 231, 232, 232, 232,
473                 232, 232, 233, 233, 233, 233, 233, 233,
474                 234, 234, 234, 234, 234, 235, 235, 235,
475         },
476 };
477 #endif
478
479 void tegra_dc_clk_enable(struct tegra_dc *dc)
480 {
481         clk_prepare_enable(dc->clk);
482         tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
483 }
484
485 void tegra_dc_clk_disable(struct tegra_dc *dc)
486 {
487         clk_disable_unprepare(dc->clk);
488         tegra_dvfs_set_rate(dc->clk, 0);
489 }
490
491 void tegra_dc_get(struct tegra_dc *dc)
492 {
493         tegra_dc_io_start(dc);
494
495         /* extra reference to dc clk */
496         clk_prepare_enable(dc->clk);
497 }
498 EXPORT_SYMBOL(tegra_dc_get);
499
500 void tegra_dc_put(struct tegra_dc *dc)
501 {
502         /* balance extra dc clk reference */
503         clk_disable_unprepare(dc->clk);
504
505         tegra_dc_io_end(dc);
506 }
507 EXPORT_SYMBOL(tegra_dc_put);
508
509 void tegra_dc_hold_dc_out(struct tegra_dc *dc)
510 {
511         if (1 == atomic_inc_return(&dc->holding)) {
512                 tegra_dc_get(dc);
513                 if (dc->out_ops && dc->out_ops->hold)
514                         dc->out_ops->hold(dc);
515         }
516 }
517
518 void tegra_dc_release_dc_out(struct tegra_dc *dc)
519 {
520         if (0 == atomic_dec_return(&dc->holding)) {
521                 if (dc->out_ops && dc->out_ops->release)
522                         dc->out_ops->release(dc);
523                 tegra_dc_put(dc);
524         }
525 }
526
527 #define DUMP_REG(a) do {                        \
528         snprintf(buff, sizeof(buff), "%-32s\t%03x\t%08lx\n",  \
529                  #a, a, tegra_dc_readl(dc, a));               \
530         print(data, buff);                                    \
531         } while (0)
532
533 static void _dump_regs(struct tegra_dc *dc, void *data,
534                        void (* print)(void *data, const char *str))
535 {
536         int i;
537         char buff[256];
538         const char winname[] = "ABCDHT";
539         /* for above, see also: DC_CMD_DISPLAY_WINDOW_HEADER and DC_N_WINDOWS */
540
541         /* If gated, quietly return. */
542         if (!tegra_powergate_is_powered(dc->powergate_id))
543                 return;
544
545         mutex_lock(&dc->lock);
546         tegra_dc_get(dc);
547         tegra_dc_writel(dc, WRITE_MUX_ACTIVE | READ_MUX_ACTIVE,
548                 DC_CMD_STATE_ACCESS);
549
550         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
551         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
552         DUMP_REG(DC_CMD_SIGNAL_RAISE);
553         DUMP_REG(DC_CMD_INT_STATUS);
554         DUMP_REG(DC_CMD_INT_MASK);
555         DUMP_REG(DC_CMD_INT_ENABLE);
556         DUMP_REG(DC_CMD_INT_TYPE);
557         DUMP_REG(DC_CMD_INT_POLARITY);
558         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
559         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
560         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
561         DUMP_REG(DC_CMD_STATE_ACCESS);
562         DUMP_REG(DC_CMD_STATE_CONTROL);
563         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
564         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
565
566         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
567         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
568         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
569         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY);
570         DUMP_REG(DC_DISP_MEM_HIGH_PRIORITY_TIMER);
571         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
572         DUMP_REG(DC_DISP_REF_TO_SYNC);
573         DUMP_REG(DC_DISP_SYNC_WIDTH);
574         DUMP_REG(DC_DISP_BACK_PORCH);
575         DUMP_REG(DC_DISP_DISP_ACTIVE);
576         DUMP_REG(DC_DISP_FRONT_PORCH);
577         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
578         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
579         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
580         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
581         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
582         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
583         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
584         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
585         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
586         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
587         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
588         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
589         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
590         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
591         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
592         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
593         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
594         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
595         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
596         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
597         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
598         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
599         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
600         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
601         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
602         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
603         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
604         DUMP_REG(DC_DISP_M0_CONTROL);
605         DUMP_REG(DC_DISP_M1_CONTROL);
606         DUMP_REG(DC_DISP_DI_CONTROL);
607         DUMP_REG(DC_DISP_PP_CONTROL);
608         DUMP_REG(DC_DISP_PP_SELECT_A);
609         DUMP_REG(DC_DISP_PP_SELECT_B);
610         DUMP_REG(DC_DISP_PP_SELECT_C);
611         DUMP_REG(DC_DISP_PP_SELECT_D);
612         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
613         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
614         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
615         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
616         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
617         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
618         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
619 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
620         DUMP_REG(DC_DISP_BORDER_COLOR);
621 #endif
622         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
623         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
624         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
625         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
626         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
627         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
628         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
629         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
630 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
631         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
632         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI_NS);
633 #endif
634         DUMP_REG(DC_DISP_CURSOR_POSITION);
635         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
636         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
637         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
638         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
639         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
640         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
641         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
642         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
643         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
644         DUMP_REG(DC_DISP_MCCIF_DISPLAY0C_HYST);
645 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
646         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
647 #endif
648         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
649         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
650 #if defined(CONFIG_TEGRA_DC_INTERLACE)
651         DUMP_REG(DC_DISP_INTERLACE_CONTROL);
652         DUMP_REG(DC_DISP_INTERLACE_FIELD2_REF_TO_SYNC);
653         DUMP_REG(DC_DISP_INTERLACE_FIELD2_SYNC_WIDTH);
654         DUMP_REG(DC_DISP_INTERLACE_FIELD2_BACK_PORCH);
655         DUMP_REG(DC_DISP_INTERLACE_FIELD2_FRONT_PORCH);
656         DUMP_REG(DC_DISP_INTERLACE_FIELD2_DISP_ACTIVE);
657 #endif
658
659         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
660         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE2);
661         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY2);
662         DUMP_REG(DC_COM_PIN_OUTPUT_DATA2);
663         DUMP_REG(DC_COM_PIN_INPUT_ENABLE2);
664         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT5);
665         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
666         DUMP_REG(DC_DISP_M1_CONTROL);
667         DUMP_REG(DC_COM_PM1_CONTROL);
668         DUMP_REG(DC_COM_PM1_DUTY_CYCLE);
669         DUMP_REG(DC_DISP_SD_CONTROL);
670
671 #ifdef CONFIG_TEGRA_DC_CMU
672         DUMP_REG(DC_COM_CMU_CSC_KRR);
673         DUMP_REG(DC_COM_CMU_CSC_KGR);
674         DUMP_REG(DC_COM_CMU_CSC_KBR);
675         DUMP_REG(DC_COM_CMU_CSC_KRG);
676         DUMP_REG(DC_COM_CMU_CSC_KGG);
677         DUMP_REG(DC_COM_CMU_CSC_KBR);
678         DUMP_REG(DC_COM_CMU_CSC_KRB);
679         DUMP_REG(DC_COM_CMU_CSC_KGB);
680         DUMP_REG(DC_COM_CMU_CSC_KBB);
681 #endif
682
683         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
684                 print(data, "\n");
685                 snprintf(buff, sizeof(buff), "WINDOW %c:\n", winname[i]);
686                 print(data, buff);
687
688                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
689                                 DC_CMD_DISPLAY_WINDOW_HEADER);
690                 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
691                 DUMP_REG(DC_WIN_WIN_OPTIONS);
692                 DUMP_REG(DC_WIN_BYTE_SWAP);
693                 DUMP_REG(DC_WIN_BUFFER_CONTROL);
694                 DUMP_REG(DC_WIN_COLOR_DEPTH);
695                 DUMP_REG(DC_WIN_POSITION);
696                 DUMP_REG(DC_WIN_SIZE);
697                 DUMP_REG(DC_WIN_PRESCALED_SIZE);
698                 DUMP_REG(DC_WIN_H_INITIAL_DDA);
699                 DUMP_REG(DC_WIN_V_INITIAL_DDA);
700                 DUMP_REG(DC_WIN_DDA_INCREMENT);
701                 DUMP_REG(DC_WIN_LINE_STRIDE);
702 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
703                 DUMP_REG(DC_WIN_BUF_STRIDE);
704                 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
705 #endif
706                 DUMP_REG(DC_WIN_BLEND_NOKEY);
707                 DUMP_REG(DC_WIN_BLEND_1WIN);
708                 DUMP_REG(DC_WIN_BLEND_2WIN_X);
709                 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
710                 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
711                 DUMP_REG(DC_WIN_GLOBAL_ALPHA);
712 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
713         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
714         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
715         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
716                 DUMP_REG(DC_WINBUF_BLEND_LAYER_CONTROL);
717 #endif
718                 DUMP_REG(DC_WINBUF_START_ADDR);
719                 DUMP_REG(DC_WINBUF_START_ADDR_U);
720                 DUMP_REG(DC_WINBUF_START_ADDR_V);
721                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
722                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
723 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
724         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
725         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
726         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
727                 DUMP_REG(DC_WINBUF_START_ADDR_HI);
728                 DUMP_REG(DC_WINBUF_START_ADDR_HI_U);
729                 DUMP_REG(DC_WINBUF_START_ADDR_HI_V);
730                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2);
731                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_U);
732                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_V);
733                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI);
734                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_U);
735                 DUMP_REG(DC_WINBUF_START_ADDR_FIELD2_HI_V);
736                 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_FIELD2);
737                 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_FIELD2);
738 #endif
739                 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
740                 DUMP_REG(DC_WIN_CSC_YOF);
741                 DUMP_REG(DC_WIN_CSC_KYRGB);
742                 DUMP_REG(DC_WIN_CSC_KUR);
743                 DUMP_REG(DC_WIN_CSC_KVR);
744                 DUMP_REG(DC_WIN_CSC_KUG);
745                 DUMP_REG(DC_WIN_CSC_KVG);
746                 DUMP_REG(DC_WIN_CSC_KUB);
747                 DUMP_REG(DC_WIN_CSC_KVB);
748
749 #if defined(CONFIG_ARCH_TEGRA_21x_SOC)
750                 DUMP_REG(DC_WINBUF_CDE_CONTROL);
751                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASE_0);
752                 DUMP_REG(DC_WINBUF_CDE_COMPTAG_BASEHI_0);
753                 DUMP_REG(DC_WINBUF_CDE_ZBC_COLOR_0);
754                 DUMP_REG(DC_WINBUF_CDE_SURFACE_OFFSET_0);
755                 DUMP_REG(DC_WINBUF_CDE_CTB_ENTRY_0);
756                 DUMP_REG(DC_WINBUF_CDE_CG_SW_OVR);
757                 DUMP_REG(DC_WINBUF_CDE_PM_CONTROL);
758                 DUMP_REG(DC_WINBUF_CDE_PM_COUNTER);
759 #endif
760         }
761
762         tegra_dc_put(dc);
763         mutex_unlock(&dc->lock);
764 }
765
766 #undef DUMP_REG
767
768 #ifdef DEBUG
769 static void dump_regs_print(void *data, const char *str)
770 {
771         struct tegra_dc *dc = data;
772         dev_dbg(&dc->ndev->dev, "%s", str);
773 }
774
775 static void dump_regs(struct tegra_dc *dc)
776 {
777         _dump_regs(dc, dc, dump_regs_print);
778 }
779 #else /* !DEBUG */
780
781 static void dump_regs(struct tegra_dc *dc) {}
782
783 #endif /* DEBUG */
784
785 #ifdef CONFIG_DEBUG_FS
786
787 static void dbg_regs_print(void *data, const char *str)
788 {
789         struct seq_file *s = data;
790
791         seq_printf(s, "%s", str);
792 }
793
794 #undef DUMP_REG
795
796 static int dbg_dc_show(struct seq_file *s, void *unused)
797 {
798         struct tegra_dc *dc = s->private;
799
800         _dump_regs(dc, s, dbg_regs_print);
801
802         return 0;
803 }
804
805
806 static int dbg_dc_open(struct inode *inode, struct file *file)
807 {
808         return single_open(file, dbg_dc_show, inode->i_private);
809 }
810
811 static const struct file_operations regs_fops = {
812         .open           = dbg_dc_open,
813         .read           = seq_read,
814         .llseek         = seq_lseek,
815         .release        = single_release,
816 };
817
818 static int dbg_dc_mode_show(struct seq_file *s, void *unused)
819 {
820         struct tegra_dc *dc = s->private;
821         struct tegra_dc_mode *m;
822
823         mutex_lock(&dc->lock);
824         m = &dc->mode;
825         seq_printf(s,
826                 "pclk: %d\n"
827                 "h_ref_to_sync: %d\n"
828                 "v_ref_to_sync: %d\n"
829                 "h_sync_width: %d\n"
830                 "v_sync_width: %d\n"
831                 "h_back_porch: %d\n"
832                 "v_back_porch: %d\n"
833                 "h_active: %d\n"
834                 "v_active: %d\n"
835                 "h_front_porch: %d\n"
836                 "v_front_porch: %d\n"
837                 "stereo_mode: %d\n",
838                 m->pclk, m->h_ref_to_sync, m->v_ref_to_sync,
839                 m->h_sync_width, m->v_sync_width,
840                 m->h_back_porch, m->v_back_porch,
841                 m->h_active, m->v_active,
842                 m->h_front_porch, m->v_front_porch,
843                 m->stereo_mode);
844         mutex_unlock(&dc->lock);
845         return 0;
846 }
847
848 static int dbg_dc_mode_open(struct inode *inode, struct file *file)
849 {
850         return single_open(file, dbg_dc_mode_show, inode->i_private);
851 }
852
853 static const struct file_operations mode_fops = {
854         .open           = dbg_dc_mode_open,
855         .read           = seq_read,
856         .llseek         = seq_lseek,
857         .release        = single_release,
858 };
859
860 static int dbg_dc_stats_show(struct seq_file *s, void *unused)
861 {
862         struct tegra_dc *dc = s->private;
863
864         mutex_lock(&dc->lock);
865         seq_printf(s,
866                 "underflows: %llu\n"
867                 "underflows_a: %llu\n"
868                 "underflows_b: %llu\n"
869                 "underflows_c: %llu\n",
870                 dc->stats.underflows,
871                 dc->stats.underflows_a,
872                 dc->stats.underflows_b,
873                 dc->stats.underflows_c);
874 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
875         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
876         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
877         seq_printf(s,
878                 "underflows_d: %llu\n"
879                 "underflows_h: %llu\n"
880                 "underflows_t: %llu\n",
881                 dc->stats.underflows_d,
882                 dc->stats.underflows_h,
883                 dc->stats.underflows_t);
884 #endif
885         mutex_unlock(&dc->lock);
886
887         return 0;
888 }
889
890 static int dbg_dc_stats_open(struct inode *inode, struct file *file)
891 {
892         return single_open(file, dbg_dc_stats_show, inode->i_private);
893 }
894
895 static int dbg_dc_event_inject_show(struct seq_file *s, void *unused)
896 {
897         return 0;
898 }
899
900 static ssize_t dbg_dc_event_inject_write(struct file *file,
901         const char __user *addr, size_t len, loff_t *pos)
902 {
903         struct seq_file *m = file->private_data; /* single_open() initialized */
904         struct tegra_dc *dc = m ? m->private : NULL;
905         long event;
906         int ret;
907
908         if (!dc)
909                 return -EINVAL;
910
911         ret = kstrtol_from_user(addr, len, 10, &event);
912         if (ret < 0)
913                 return ret;
914
915         if (event == 0x1) /* TEGRA_DC_EXT_EVENT_HOTPLUG */
916                 tegra_dc_ext_process_hotplug(dc->ndev->id);
917         else if (event == 0x2) /* TEGRA_DC_EXT_EVENT_BANDWIDTH_DEC */
918                 tegra_dc_ext_process_bandwidth_renegotiate(
919                                 dc->ndev->id, NULL);
920         else {
921                 dev_err(&dc->ndev->dev, "Unknown event 0x%lx\n", event);
922                 return -EINVAL; /* unknown event number */
923         }
924         return len;
925 }
926
927 /* Update the strings as dc.h get updated for new output types*/
928 static const char * const dc_outtype_strings[] = {
929         "TEGRA_DC_OUT_RGB",
930         "TEGRA_DC_OUT_HDMI",
931         "TEGRA_DC_OUT_DSI",
932         "TEGRA_DC_OUT_DP",
933         "TEGRA_DC_OUT_LVDS",
934         "TEGRA_DC_OUT_NVSR_DP",
935         "TEGRA_DC_OUT_FAKE_DP",
936         "TEGRA_DC_OUT_FAKE_DSIA",
937         "TEGRA_DC_OUT_FAKE_DSIB",
938         "TEGRA_DC_OUT_FAKE_DSI_GANGED",
939         "TEGRA_DC_OUT_NULL",
940         "TEGRA_DC_OUT_UNKNOWN"
941 };
942
943 static int dbg_dc_outtype_show(struct seq_file *s, void *unused)
944 {
945         struct tegra_dc *dc = s->private;
946
947         mutex_lock(&dc->lock);
948         seq_puts(s, "\n");
949         seq_printf(s,
950                 "\tDC OUTPUT: \t%s (%d)\n",
951                 dc_outtype_strings[dc->out->type], dc->out->type);
952         seq_puts(s, "\n");
953         mutex_unlock(&dc->lock);
954         return 0;
955 }
956
957 /* Add specific variable related to each output type.
958  * Save and reuse on changing the output type
959  */
960 #if defined(CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT)
961 struct tegra_dc_out_info {
962         struct tegra_dc_out_ops *out_ops;
963         void *out_data;
964         struct tegra_dc_out out;
965         struct tegra_dc_mode mode;
966         int fblistindex;
967 };
968
969 static struct tegra_dc_out_info dbg_dc_out_info[TEGRA_DC_OUT_MAX];
970 /* array for saving the out_type for each head */
971 static int  boot_out_type[] = {-1, -1};
972
973 static int is_invalid_dc_out(struct tegra_dc *dc, long dc_outtype)
974 {
975         if ((dc_outtype != boot_out_type[dc->ndev->id]) &&
976                 (dc_outtype != TEGRA_DC_OUT_FAKE_DP) &&
977                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIA) &&
978                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSIB) &&
979                 (dc_outtype != TEGRA_DC_OUT_FAKE_DSI_GANGED) &&
980                 (dc_outtype != TEGRA_DC_OUT_NULL)) {
981                 dev_err(&dc->ndev->dev,
982                         "Request 0x%lx is unsupported target out_type\n",
983                          dc_outtype);
984                 dev_err(&dc->ndev->dev,
985                         "boot_out_type[%d] is 0x%x\n",
986                          dc->ndev->id, boot_out_type[dc->ndev->id]);
987                 return -EINVAL;
988         }
989
990         return 0;
991 }
992
993 static int is_valid_dsi_out(struct tegra_dc *dc, long dc_outtype)
994 {
995         if (((dc_outtype >= TEGRA_DC_OUT_FAKE_DSIA) &&
996                 (dc_outtype <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) ||
997                 (dc_outtype == TEGRA_DC_OUT_DSI))
998                         return 1;
999
1000         return 0;
1001 }
1002
1003
1004 static int is_valid_fake_support(struct tegra_dc *dc, long dc_outtype)
1005 {
1006         if ((dc_outtype == TEGRA_DC_OUT_FAKE_DP) ||
1007                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIA) ||
1008                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSIB) ||
1009                 (dc_outtype == TEGRA_DC_OUT_FAKE_DSI_GANGED) ||
1010                 (dc_outtype == TEGRA_DC_OUT_NULL))
1011                 return 1;
1012
1013         return 0;
1014 }
1015
1016 static ssize_t dbg_dc_out_type_set(struct file *file,
1017         const char __user *addr, size_t len, loff_t *pos)
1018 {
1019         struct seq_file *m = file->private_data; /* single_open() initialized */
1020         struct tegra_dc *dc = m ? m->private : NULL;
1021         long cur_dc_out;
1022         long out_type;
1023         int ret = 0;
1024         bool  allocate = false;
1025
1026         if (!dc)
1027                 return -EINVAL;
1028
1029         ret = kstrtol_from_user(addr, len, 10, &out_type);
1030         if (ret < 0)
1031                 return ret;
1032
1033         if (!dc->pdata->default_out)
1034                 return -EINVAL;
1035
1036         /* check out type is out of range then skip */
1037         if (out_type < TEGRA_DC_OUT_RGB ||
1038                 out_type >= TEGRA_DC_OUT_MAX) {
1039                 dev_err(&dc->ndev->dev, "Unknown out_type 0x%lx\n", out_type);
1040                 return -EINVAL;
1041         }
1042
1043         if (boot_out_type[dc->ndev->id] == -1)
1044                 boot_out_type[dc->ndev->id] = dc->pdata->default_out->type;
1045
1046         cur_dc_out = dc->pdata->default_out->type;
1047
1048         /* Nothing to do if new outtype is same as old
1049          * Allow to switch between booted out type and fake panel out
1050          */
1051         if ((cur_dc_out == out_type) || is_invalid_dc_out(dc, out_type))
1052                 return -EINVAL;
1053
1054         /* disable the dc and output controllers */
1055         if (dc->enabled)
1056                 tegra_dc_disable(dc);
1057
1058         /* If output is already created - save it */
1059         if (dc->out_data) {
1060                 dbg_dc_out_info[cur_dc_out].out_data = dc->out_data;
1061                 dbg_dc_out_info[cur_dc_out].out_ops  = dc->out_ops;
1062                 memcpy(&dbg_dc_out_info[cur_dc_out].out, dc->out,
1063                                         sizeof(struct tegra_dc_out));
1064                 dbg_dc_out_info[cur_dc_out].mode = dc->mode;
1065
1066                 if (is_valid_dsi_out(dc, cur_dc_out) &&
1067                         dbg_dc_out_info[cur_dc_out].out_data)
1068                         tegra_dc_destroy_dsi_resources(dc, cur_dc_out);
1069
1070                 if (!is_valid_fake_support(dc, cur_dc_out))
1071                         dbg_dc_out_info[cur_dc_out].fblistindex =
1072                                                 tegra_fb_update_modelist(dc, 0);
1073
1074         }
1075
1076         /* If output already created - reuse it */
1077         if (dbg_dc_out_info[out_type].out_data) {
1078                 mutex_lock(&dc->lp_lock);
1079                 mutex_lock(&dc->lock);
1080
1081                 /* Change the out type */
1082                 dc->pdata->default_out->type = out_type;
1083                 dc->out_ops = dbg_dc_out_info[out_type].out_ops;
1084                 dc->out_data = dbg_dc_out_info[out_type].out_data;
1085                 memcpy(dc->out, &dbg_dc_out_info[out_type].out,
1086                                                 sizeof(struct tegra_dc_out));
1087                 dc->mode = dbg_dc_out_info[out_type].mode;
1088
1089                 /* Re-init the resources that are destroyed for dsi */
1090                 if (is_valid_dsi_out(dc, out_type))
1091                         ret = tegra_dc_reinit_dsi_resources(dc, out_type);
1092
1093                 if (!is_valid_fake_support(dc, out_type))
1094                         tegra_fb_update_modelist(dc,
1095                                         dbg_dc_out_info[out_type].fblistindex);
1096
1097                 mutex_unlock(&dc->lock);
1098                 mutex_unlock(&dc->lp_lock);
1099
1100                 if (ret) {
1101                         dev_err(&dc->ndev->dev, "Failed to reinit!!!\n");
1102                         return -EINVAL;
1103                 }
1104
1105         } else {
1106                 /* Change the out type */
1107                 dc->pdata->default_out->type = out_type;
1108
1109                 /* create new - now restricted to fake_dp only */
1110                 if (out_type == TEGRA_DC_OUT_FAKE_DP) {
1111
1112                         /* set to default bpp */
1113                         if (!dc->pdata->default_out->depth)
1114                                 dc->pdata->default_out->depth = 24;
1115
1116                         /* DP and Fake_Dp use same data
1117                         *  Reuse if already created */
1118                         if (!dbg_dc_out_info[TEGRA_DC_OUT_DP].out_data) {
1119                                 allocate = true;
1120                                 tegra_dc_init_fakedp_panel(dc);
1121                         }
1122                 } else if ((out_type >= TEGRA_DC_OUT_FAKE_DSIA) &&
1123                                 (out_type <= TEGRA_DC_OUT_FAKE_DSI_GANGED)) {
1124                         /* DSI and fake DSI use same data
1125                          * create new if not created yet
1126                          */
1127                         if (!dc->pdata->default_out->depth)
1128                                 dc->pdata->default_out->depth = 18;
1129
1130                         allocate = true;
1131                         tegra_dc_init_fakedsi_panel(dc, out_type);
1132
1133                 } else if (out_type == TEGRA_DC_OUT_NULL) {
1134                         if (!dbg_dc_out_info[TEGRA_DC_OUT_NULL].out_data) {
1135                                 allocate = true;
1136                                 tegra_dc_init_null_or(dc);
1137                         }
1138                 } else {
1139                         /* set  back to existing one */
1140                         dc->pdata->default_out->type = cur_dc_out;
1141                         dev_err(&dc->ndev->dev, "Unknown type is asked\n");
1142                         goto by_pass;
1143                 }
1144
1145                 if (allocate) {
1146                         ret = tegra_dc_set_out(dc, dc->pdata->default_out);
1147                                 if (ret < 0) {
1148                                         dev_err(&dc->ndev->dev,
1149                                         "Failed to initialize DC out ops\n");
1150                                         return -EINVAL;
1151                                 }
1152                 }
1153
1154                 dbg_dc_out_info[out_type].out_ops = dc->out_ops;
1155                 dbg_dc_out_info[out_type].out_data = dc->out_data;
1156                 memcpy(&dbg_dc_out_info[out_type].out, dc->out,
1157                                                 sizeof(struct tegra_dc_out));
1158
1159         }
1160
1161 by_pass:
1162         /*enable the dc and output controllers */
1163         if (!dc->enabled)
1164                 tegra_dc_enable(dc);
1165
1166         return len;
1167 }
1168 #else
1169 static ssize_t dbg_dc_out_type_set(struct file *file,
1170         const char __user *addr, size_t len, loff_t *pos)
1171 {
1172         return -EINVAL;
1173 }
1174 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1175
1176 static const struct file_operations stats_fops = {
1177         .open           = dbg_dc_stats_open,
1178         .read           = seq_read,
1179         .llseek         = seq_lseek,
1180         .release        = single_release,
1181 };
1182
1183 static int dbg_dc_event_inject_open(struct inode *inode, struct file *file)
1184 {
1185         return single_open(file, dbg_dc_event_inject_show, inode->i_private);
1186 }
1187
1188 static const struct file_operations event_inject_fops = {
1189         .open           = dbg_dc_event_inject_open,
1190         .read           = seq_read,
1191         .write          = dbg_dc_event_inject_write,
1192         .llseek         = seq_lseek,
1193         .release        = single_release,
1194 };
1195
1196 static int dbg_dc_outtype_open(struct inode *inode, struct file *file)
1197 {
1198         return single_open(file, dbg_dc_outtype_show, inode->i_private);
1199 }
1200
1201 static const struct file_operations outtype_fops = {
1202         .open           = dbg_dc_outtype_open,
1203         .read           = seq_read,
1204         .write          = dbg_dc_out_type_set,
1205         .llseek         = seq_lseek,
1206         .release        = single_release,
1207 };
1208
1209 static void tegra_dc_remove_debugfs(struct tegra_dc *dc)
1210 {
1211         if (dc->debugdir)
1212                 debugfs_remove_recursive(dc->debugdir);
1213         dc->debugdir = NULL;
1214 }
1215
1216 static void tegra_dc_create_debugfs(struct tegra_dc *dc)
1217 {
1218         struct dentry *retval;
1219
1220         dc->debugdir = debugfs_create_dir(dev_name(&dc->ndev->dev), NULL);
1221         if (!dc->debugdir)
1222                 goto remove_out;
1223
1224         retval = debugfs_create_file("regs", S_IRUGO, dc->debugdir, dc,
1225                 &regs_fops);
1226         if (!retval)
1227                 goto remove_out;
1228
1229         retval = debugfs_create_file("mode", S_IRUGO, dc->debugdir, dc,
1230                 &mode_fops);
1231         if (!retval)
1232                 goto remove_out;
1233
1234         retval = debugfs_create_file("stats", S_IRUGO, dc->debugdir, dc,
1235                 &stats_fops);
1236         if (!retval)
1237                 goto remove_out;
1238
1239         retval = debugfs_create_file("event_inject", S_IRUGO, dc->debugdir, dc,
1240                 &event_inject_fops);
1241         if (!retval)
1242                 goto remove_out;
1243
1244         retval = debugfs_create_file("out_type", S_IRUGO, dc->debugdir, dc,
1245                 &outtype_fops);
1246         if (!retval)
1247                 goto remove_out;
1248
1249         return;
1250 remove_out:
1251         dev_err(&dc->ndev->dev, "could not create debugfs\n");
1252         tegra_dc_remove_debugfs(dc);
1253 }
1254
1255 #else /* !CONFIG_DEBUGFS */
1256 static inline void tegra_dc_create_debugfs(struct tegra_dc *dc) { };
1257 static inline void tegra_dc_remove_debugfs(struct tegra_dc *dc) { };
1258 #endif /* CONFIG_DEBUGFS */
1259
1260 unsigned long tegra_dc_poll_register(struct tegra_dc *dc, u32 reg, u32 mask,
1261                 u32 exp_val, u32 poll_interval_us, u32 timeout_ms)
1262 {
1263         unsigned long timeout_jf = jiffies + msecs_to_jiffies(timeout_ms);
1264         u32 reg_val = 0;
1265
1266         do {
1267                 usleep_range(poll_interval_us, poll_interval_us << 1);
1268                 reg_val = tegra_dc_readl(dc, reg);
1269         } while (((reg_val & mask) != exp_val) &&
1270                 time_after(timeout_jf, jiffies));
1271
1272         if ((reg_val & mask) == exp_val)
1273                 return 0;       /* success */
1274         dev_err(&dc->ndev->dev,
1275                 "dc_poll_register 0x%x: timeout\n", reg);
1276         return jiffies - timeout_jf + 1;
1277 }
1278
1279 static int tegra_dc_set_next(struct tegra_dc *dc)
1280 {
1281         int i;
1282         int ret = -EBUSY;
1283
1284         mutex_lock(&tegra_dc_lock);
1285
1286         for (i = 0; i < TEGRA_MAX_DC; i++) {
1287                 if (tegra_dcs[i] == NULL) {
1288                         tegra_dcs[i] = dc;
1289                         ret = i;
1290                         break;
1291                 }
1292         }
1293
1294         mutex_unlock(&tegra_dc_lock);
1295
1296         return ret;
1297 }
1298
1299 static int tegra_dc_set_idx(struct tegra_dc *dc, int index)
1300 {
1301         int ret = 0;
1302
1303         mutex_lock(&tegra_dc_lock);
1304         if (index >= TEGRA_MAX_DC) {
1305                 ret = -EINVAL;
1306                 goto out;
1307         }
1308
1309         if (dc != NULL && tegra_dcs[index] != NULL) {
1310                 ret = -EBUSY;
1311                 goto out;
1312         }
1313
1314         tegra_dcs[index] = dc;
1315
1316 out:
1317         mutex_unlock(&tegra_dc_lock);
1318
1319         return ret;
1320 }
1321
1322 /*
1323  * If index == -1, set dc at next available index. This is to be called only
1324  * when registering dc in DT case. For non DT case & when removing the device
1325  * (dc == NULL), index should be accordingly.
1326  */
1327 static int tegra_dc_set(struct tegra_dc *dc, int index)
1328 {
1329         if ((index == -1) && (dc != NULL)) /* DT register case */
1330                 return tegra_dc_set_next(dc);
1331         else /* non DT, unregister case */
1332                 return tegra_dc_set_idx(dc, index);
1333 }
1334
1335 unsigned int tegra_dc_has_multiple_dc(void)
1336 {
1337         unsigned int idx;
1338         unsigned int cnt = 0;
1339         struct tegra_dc *dc;
1340
1341         mutex_lock(&tegra_dc_lock);
1342         for (idx = 0; idx < TEGRA_MAX_DC; idx++)
1343                 cnt += ((dc = tegra_dcs[idx]) != NULL && dc->enabled) ? 1 : 0;
1344         mutex_unlock(&tegra_dc_lock);
1345
1346         return (cnt > 1);
1347 }
1348
1349 /* get the stride size of a window.
1350  * return: stride size in bytes for window win. or 0 if unavailble. */
1351 int tegra_dc_get_stride(struct tegra_dc *dc, unsigned win)
1352 {
1353         u32 stride;
1354
1355         if (!dc->enabled)
1356                 return 0;
1357         BUG_ON(win > DC_N_WINDOWS);
1358         mutex_lock(&dc->lock);
1359         tegra_dc_get(dc);
1360         tegra_dc_writel(dc, WINDOW_A_SELECT << win,
1361                 DC_CMD_DISPLAY_WINDOW_HEADER);
1362         stride = tegra_dc_readl(dc, DC_WIN_LINE_STRIDE);
1363         tegra_dc_put(dc);
1364         mutex_unlock(&dc->lock);
1365         return GET_LINE_STRIDE(stride);
1366 }
1367 EXPORT_SYMBOL(tegra_dc_get_stride);
1368
1369 struct tegra_dc *tegra_dc_get_dc(unsigned idx)
1370 {
1371         if (idx < TEGRA_MAX_DC)
1372                 return tegra_dcs[idx];
1373         else
1374                 return NULL;
1375 }
1376 EXPORT_SYMBOL(tegra_dc_get_dc);
1377
1378 struct tegra_dc_win *tegra_dc_get_window(struct tegra_dc *dc, unsigned win)
1379 {
1380         if (win >= DC_N_WINDOWS || !test_bit(win, &dc->valid_windows))
1381                 return NULL;
1382
1383         return &dc->windows[win];
1384 }
1385 EXPORT_SYMBOL(tegra_dc_get_window);
1386
1387 bool tegra_dc_get_connected(struct tegra_dc *dc)
1388 {
1389         return dc->connected;
1390 }
1391 EXPORT_SYMBOL(tegra_dc_get_connected);
1392
1393 bool tegra_dc_hpd(struct tegra_dc *dc)
1394 {
1395         int sense;
1396         int level;
1397         int hpd;
1398
1399         if (WARN_ON(!dc || !dc->out))
1400                 return false;
1401
1402         if (dc->out->hotplug_state != 0) {
1403                 if (dc->out->hotplug_state == 1) /* force on */
1404                         return true;
1405                 if (dc->out->hotplug_state == -1) /* force off */
1406                         return false;
1407         }
1408
1409         if (!tegra_dc_hotplug_supported(dc))
1410                 return true;
1411
1412         level = gpio_get_value_cansleep(dc->out->hotplug_gpio);
1413
1414         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
1415
1416         hpd = (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
1417                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
1418
1419         if (dc->out->hotplug_report)
1420                 dc->out->hotplug_report(hpd);
1421
1422         return hpd;
1423 }
1424 EXPORT_SYMBOL(tegra_dc_hpd);
1425
1426 static void tegra_dc_set_scaling_filter(struct tegra_dc *dc)
1427 {
1428         unsigned i;
1429         unsigned v0 = 128;
1430         unsigned v1 = 0;
1431
1432         /* linear horizontal and vertical filters */
1433         for (i = 0; i < 16; i++) {
1434                 tegra_dc_writel(dc, (v1 << 16) | (v0 << 8),
1435                                 DC_WIN_H_FILTER_P(i));
1436
1437                 tegra_dc_writel(dc, v0,
1438                                 DC_WIN_V_FILTER_P(i));
1439                 v0 -= 8;
1440                 v1 += 8;
1441         }
1442 }
1443
1444 #ifdef CONFIG_TEGRA_DC_CMU
1445 static void tegra_dc_cache_cmu(struct tegra_dc *dc,
1446                                         struct tegra_dc_cmu *src_cmu)
1447 {
1448         if (&dc->cmu != src_cmu) /* ignore if it would require memmove() */
1449                 memcpy(&dc->cmu, src_cmu, sizeof(*src_cmu));
1450         dc->cmu_dirty = true;
1451 }
1452
1453 static void tegra_dc_set_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1454 {
1455         u32 val;
1456         u32 i;
1457
1458         for (i = 0; i < 256; i++) {
1459                 val = LUT1_ADDR(i) | LUT1_DATA(cmu->lut1[i]);
1460                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT1);
1461         }
1462
1463         tegra_dc_writel(dc, cmu->csc.krr, DC_COM_CMU_CSC_KRR);
1464         tegra_dc_writel(dc, cmu->csc.kgr, DC_COM_CMU_CSC_KGR);
1465         tegra_dc_writel(dc, cmu->csc.kbr, DC_COM_CMU_CSC_KBR);
1466         tegra_dc_writel(dc, cmu->csc.krg, DC_COM_CMU_CSC_KRG);
1467         tegra_dc_writel(dc, cmu->csc.kgg, DC_COM_CMU_CSC_KGG);
1468         tegra_dc_writel(dc, cmu->csc.kbg, DC_COM_CMU_CSC_KBG);
1469         tegra_dc_writel(dc, cmu->csc.krb, DC_COM_CMU_CSC_KRB);
1470         tegra_dc_writel(dc, cmu->csc.kgb, DC_COM_CMU_CSC_KGB);
1471         tegra_dc_writel(dc, cmu->csc.kbb, DC_COM_CMU_CSC_KBB);
1472
1473         for (i = 0; i < 960; i++) {
1474                 val = LUT2_ADDR(i) | LUT1_DATA(cmu->lut2[i]);
1475                 tegra_dc_writel(dc, val, DC_COM_CMU_LUT2);
1476         }
1477
1478         dc->cmu_dirty = false;
1479 }
1480
1481 static void _tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1482 {
1483         u32 val;
1484
1485         if (!dc->cmu_enabled)
1486                 return;
1487
1488         tegra_dc_cache_cmu(dc, cmu);
1489
1490         if (dc->cmu_dirty) {
1491                 /* Disable CMU to avoid programming it while it is in use */
1492                 val = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL);
1493                 if (val & CMU_ENABLE) {
1494                         val &= ~CMU_ENABLE;
1495                         tegra_dc_writel(dc, val,
1496                                         DC_DISP_DISP_COLOR_CONTROL);
1497                         val = GENERAL_ACT_REQ;
1498                         tegra_dc_writel(dc, val, DC_CMD_STATE_CONTROL);
1499                         /*TODO: Sync up with vsync */
1500                         mdelay(20);
1501                 }
1502                 dev_dbg(&dc->ndev->dev, "updating CMU cmu_dirty=%d\n",
1503                         dc->cmu_dirty);
1504
1505                 tegra_dc_set_cmu(dc, &dc->cmu);
1506         }
1507 }
1508
1509 int tegra_dc_update_cmu(struct tegra_dc *dc, struct tegra_dc_cmu *cmu)
1510 {
1511         mutex_lock(&dc->lock);
1512         if (!dc->enabled) {
1513                 mutex_unlock(&dc->lock);
1514                 return 0;
1515         }
1516
1517         tegra_dc_get(dc);
1518
1519         _tegra_dc_update_cmu(dc, cmu);
1520         tegra_dc_set_color_control(dc);
1521
1522         tegra_dc_put(dc);
1523         mutex_unlock(&dc->lock);
1524
1525         return 0;
1526 }
1527 EXPORT_SYMBOL(tegra_dc_update_cmu);
1528
1529 static struct tegra_dc_cmu *tegra_dc_get_cmu(struct tegra_dc *dc)
1530 {
1531         if (dc->pdata->cmu)
1532                 return dc->pdata->cmu;
1533         else if (dc->out->type == TEGRA_DC_OUT_HDMI)
1534                 return &default_limited_cmu;
1535         else
1536                 return &default_cmu;
1537 }
1538
1539 void tegra_dc_cmu_enable(struct tegra_dc *dc, bool cmu_enable)
1540 {
1541         dc->cmu_enabled = cmu_enable;
1542         tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
1543 }
1544 #else
1545 #define tegra_dc_cache_cmu(dc, src_cmu)
1546 #define tegra_dc_set_cmu(dc, cmu)
1547 #define tegra_dc_update_cmu(dc, cmu)
1548 #endif
1549
1550 /* disable_irq() blocks until handler completes, calling this function while
1551  * holding dc->lock can deadlock. */
1552 static inline void disable_dc_irq(const struct tegra_dc *dc)
1553 {
1554         disable_irq(dc->irq);
1555 }
1556
1557 u32 tegra_dc_get_syncpt_id(const struct tegra_dc *dc, int i)
1558 {
1559         return dc->syncpt[i].id;
1560 }
1561 EXPORT_SYMBOL(tegra_dc_get_syncpt_id);
1562
1563 u32 tegra_dc_incr_syncpt_max(struct tegra_dc *dc, int i)
1564 {
1565         u32 max;
1566
1567         mutex_lock(&dc->lock);
1568         tegra_dc_get(dc);
1569         max = nvhost_syncpt_incr_max_ext(dc->ndev,
1570                 dc->syncpt[i].id, ((dc->enabled) ? 1 : 0));
1571         dc->syncpt[i].max = max;
1572         tegra_dc_put(dc);
1573         mutex_unlock(&dc->lock);
1574
1575         return max;
1576 }
1577
1578 void tegra_dc_incr_syncpt_min(struct tegra_dc *dc, int i, u32 val)
1579 {
1580         mutex_lock(&dc->lock);
1581
1582         tegra_dc_get(dc);
1583         while (dc->syncpt[i].min < val) {
1584                 dc->syncpt[i].min++;
1585                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[i].id);
1586                 }
1587         tegra_dc_put(dc);
1588         mutex_unlock(&dc->lock);
1589 }
1590
1591 struct sync_fence *tegra_dc_create_fence(struct tegra_dc *dc, int i, u32 val)
1592 {
1593         struct nvhost_ctrl_sync_fence_info syncpt;
1594         u32 id = tegra_dc_get_syncpt_id(dc, i);
1595
1596         syncpt.id = id;
1597         syncpt.thresh = val;
1598         return nvhost_sync_create_fence(
1599                         to_platform_device(dc->ndev->dev.parent),
1600                         &syncpt, 1, dev_name(&dc->ndev->dev));
1601 }
1602
1603 void
1604 tegra_dc_config_pwm(struct tegra_dc *dc, struct tegra_dc_pwm_params *cfg)
1605 {
1606         unsigned int ctrl;
1607         unsigned long out_sel;
1608         unsigned long cmd_state;
1609
1610         mutex_lock(&dc->lock);
1611         if (!dc->enabled) {
1612                 mutex_unlock(&dc->lock);
1613                 return;
1614         }
1615
1616         tegra_dc_get(dc);
1617
1618         ctrl = ((cfg->period << PM_PERIOD_SHIFT) |
1619                 (cfg->clk_div << PM_CLK_DIVIDER_SHIFT) |
1620                 cfg->clk_select);
1621
1622         /* The new value should be effected immediately */
1623         cmd_state = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1624         tegra_dc_writel(dc, (cmd_state | (1 << 2)), DC_CMD_STATE_ACCESS);
1625
1626         switch (cfg->which_pwm) {
1627         case TEGRA_PWM_PM0:
1628                 /* Select the LM0 on PM0 */
1629                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1630                 out_sel &= ~(7 << 0);
1631                 out_sel |= (3 << 0);
1632                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1633                 tegra_dc_writel(dc, ctrl, DC_COM_PM0_CONTROL);
1634                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM0_DUTY_CYCLE);
1635                 break;
1636         case TEGRA_PWM_PM1:
1637                 /* Select the LM1 on PM1 */
1638                 out_sel = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_SELECT5);
1639                 out_sel &= ~(7 << 4);
1640                 out_sel |= (3 << 4);
1641                 tegra_dc_writel(dc, out_sel, DC_COM_PIN_OUTPUT_SELECT5);
1642                 tegra_dc_writel(dc, ctrl, DC_COM_PM1_CONTROL);
1643                 tegra_dc_writel(dc, cfg->duty_cycle, DC_COM_PM1_DUTY_CYCLE);
1644                 break;
1645         default:
1646                 dev_err(&dc->ndev->dev, "Error: Need which_pwm\n");
1647                 break;
1648         }
1649         tegra_dc_writel(dc, cmd_state, DC_CMD_STATE_ACCESS);
1650         tegra_dc_put(dc);
1651         mutex_unlock(&dc->lock);
1652 }
1653 EXPORT_SYMBOL(tegra_dc_config_pwm);
1654
1655 void tegra_dc_set_out_pin_polars(struct tegra_dc *dc,
1656                                 const struct tegra_dc_out_pin *pins,
1657                                 const unsigned int n_pins)
1658 {
1659         unsigned int i;
1660
1661         int name;
1662         int pol;
1663
1664         u32 pol1, pol3;
1665
1666         u32 set1, unset1;
1667         u32 set3, unset3;
1668
1669         set1 = set3 = unset1 = unset3 = 0;
1670
1671         for (i = 0; i < n_pins; i++) {
1672                 name = (pins + i)->name;
1673                 pol  = (pins + i)->pol;
1674
1675                 /* set polarity by name */
1676                 switch (name) {
1677                 case TEGRA_DC_OUT_PIN_DATA_ENABLE:
1678                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1679                                 set3 |= LSPI_OUTPUT_POLARITY_LOW;
1680                         else
1681                                 unset3 |= LSPI_OUTPUT_POLARITY_LOW;
1682                         break;
1683                 case TEGRA_DC_OUT_PIN_H_SYNC:
1684                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1685                                 set1 |= LHS_OUTPUT_POLARITY_LOW;
1686                         else
1687                                 unset1 |= LHS_OUTPUT_POLARITY_LOW;
1688                         break;
1689                 case TEGRA_DC_OUT_PIN_V_SYNC:
1690                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1691                                 set1 |= LVS_OUTPUT_POLARITY_LOW;
1692                         else
1693                                 unset1 |= LVS_OUTPUT_POLARITY_LOW;
1694                         break;
1695                 case TEGRA_DC_OUT_PIN_PIXEL_CLOCK:
1696                         if (pol == TEGRA_DC_OUT_PIN_POL_LOW)
1697                                 set1 |= LSC0_OUTPUT_POLARITY_LOW;
1698                         else
1699                                 unset1 |= LSC0_OUTPUT_POLARITY_LOW;
1700                         break;
1701                 default:
1702                         printk("Invalid argument in function %s\n",
1703                                __FUNCTION__);
1704                         break;
1705                 }
1706         }
1707
1708         pol1 = DC_COM_PIN_OUTPUT_POLARITY1_INIT_VAL;
1709         pol3 = DC_COM_PIN_OUTPUT_POLARITY3_INIT_VAL;
1710
1711         pol1 |= set1;
1712         pol1 &= ~unset1;
1713
1714         pol3 |= set3;
1715         pol3 &= ~unset3;
1716
1717         tegra_dc_writel(dc, pol1, DC_COM_PIN_OUTPUT_POLARITY1);
1718         tegra_dc_writel(dc, pol3, DC_COM_PIN_OUTPUT_POLARITY3);
1719 }
1720
1721 static struct tegra_dc_mode *tegra_dc_get_override_mode(struct tegra_dc *dc)
1722 {
1723         if (dc->out->type == TEGRA_DC_OUT_RGB ||
1724                 dc->out->type == TEGRA_DC_OUT_HDMI ||
1725                 dc->out->type == TEGRA_DC_OUT_DSI ||
1726                 dc->out->type == TEGRA_DC_OUT_NULL)
1727                 return override_disp_mode[dc->out->type].pclk ?
1728                         &override_disp_mode[dc->out->type] : NULL;
1729         else
1730                 return NULL;
1731 }
1732
1733 static int tegra_dc_set_out(struct tegra_dc *dc, struct tegra_dc_out *out)
1734 {
1735         struct tegra_dc_mode *mode;
1736         int err = 0;
1737
1738         dc->out = out;
1739         mode = tegra_dc_get_override_mode(dc);
1740
1741         if (mode) {
1742                 tegra_dc_set_mode(dc, mode);
1743
1744                 /*
1745                  * Bootloader should and should only pass disp_params if
1746                  * it has initialized display controller.  Whenever we see
1747                  * override modes, we should skip things cause display resets.
1748                  */
1749                 dev_info(&dc->ndev->dev, "Bootloader disp_param detected. "
1750                                 "Detected mode: %dx%d (on %dx%dmm) pclk=%d\n",
1751                                 dc->mode.h_active, dc->mode.v_active,
1752                                 dc->out->h_size, dc->out->v_size,
1753                                 dc->mode.pclk);
1754                 dc->initialized = true;
1755
1756 #ifdef CONFIG_TEGRA_DC_CMU
1757                 /*
1758                  * If the bootloader already set the mode, assume the CMU
1759                  * parameters are also correctly set. It would be better to
1760                  * read them, but unfortunately there is no reliable and
1761                  * flicker-free way to do this!
1762                  */
1763                 tegra_dc_cache_cmu(dc, tegra_dc_get_cmu(dc));
1764 #endif
1765         } else if (out->n_modes > 0)
1766                 tegra_dc_set_mode(dc, &dc->out->modes[0]);
1767
1768         switch (out->type) {
1769         case TEGRA_DC_OUT_RGB:
1770                 dc->out_ops = &tegra_dc_rgb_ops;
1771                 break;
1772
1773         case TEGRA_DC_OUT_HDMI:
1774 #if     defined(CONFIG_TEGRA_HDMI2_0)
1775                 dc->out_ops = &tegra_dc_hdmi2_0_ops;
1776 #elif defined(CONFIG_TEGRA_HDMI)
1777                 dc->out_ops = &tegra_dc_hdmi_ops;
1778 #endif
1779 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1780                 if (tegra_bonded_out_dev(BOND_OUT_SOR1)) {
1781                         dev_info(&dc->ndev->dev,
1782                                 "SOR1 instance is bonded out\n");
1783                         dc->out_ops = NULL;
1784                         err = -ENODEV;
1785                 }
1786 #endif
1787                 break;
1788
1789         case TEGRA_DC_OUT_DSI:
1790         case TEGRA_DC_OUT_FAKE_DSIA:
1791         case TEGRA_DC_OUT_FAKE_DSIB:
1792         case TEGRA_DC_OUT_FAKE_DSI_GANGED:
1793                 dc->out_ops = &tegra_dc_dsi_ops;
1794 #ifdef CONFIG_ARCH_TEGRA_21x_SOC
1795                 if (tegra_bonded_out_dev(BOND_OUT_DSI) ||
1796                         tegra_bonded_out_dev(BOND_OUT_DSIB)) {
1797                         dev_info(&dc->ndev->dev,
1798                                 "DSI instance is bonded out\n");
1799                         dc->out_ops = NULL;
1800                         err = -ENODEV;
1801                 }
1802 #endif
1803                 break;
1804
1805 #ifdef CONFIG_TEGRA_DP
1806         case TEGRA_DC_OUT_FAKE_DP:
1807         case TEGRA_DC_OUT_DP:
1808                 dc->out_ops = &tegra_dc_dp_ops;
1809                 break;
1810 #ifdef CONFIG_TEGRA_NVSR
1811         case TEGRA_DC_OUT_NVSR_DP:
1812                 dc->out_ops = &tegra_dc_nvsr_ops;
1813                 break;
1814 #endif
1815 #endif
1816 #ifdef CONFIG_TEGRA_LVDS
1817         case TEGRA_DC_OUT_LVDS:
1818                 dc->out_ops = &tegra_dc_lvds_ops;
1819                 break;
1820 #endif
1821 #ifdef CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT
1822         case TEGRA_DC_OUT_NULL:
1823                 dc->out_ops = &tegra_dc_null_ops;
1824                 break;
1825 #endif /*CONFIG_TEGRA_DC_FAKE_PANEL_SUPPORT*/
1826
1827         default:
1828                 dc->out_ops = NULL;
1829                 break;
1830         }
1831         if (dc->out_ops && dc->out_ops->init) {
1832                 err = dc->out_ops->init(dc);
1833                 if (err < 0) {
1834                         dc->out = NULL;
1835                         dc->out_ops = NULL;
1836                         dev_err(&dc->ndev->dev,
1837                                 "Error: out->type:%d out_ops->init() failed\n",
1838                                 out->type);
1839                         return err;
1840                 }
1841         }
1842
1843         return err;
1844 }
1845
1846 /* returns on error: -EINVAL
1847  * on success: TEGRA_DC_OUT_RGB, TEGRA_DC_OUT_HDMI, ... */
1848 int tegra_dc_get_out(const struct tegra_dc *dc)
1849 {
1850         if (dc && dc->out)
1851                 return dc->out->type;
1852         return -EINVAL;
1853 }
1854
1855 unsigned tegra_dc_get_out_height(const struct tegra_dc *dc)
1856 {
1857         if (dc->out)
1858                 return dc->out->height;
1859         else
1860                 return 0;
1861 }
1862 EXPORT_SYMBOL(tegra_dc_get_out_height);
1863
1864 unsigned tegra_dc_get_out_width(const struct tegra_dc *dc)
1865 {
1866         if (dc->out)
1867                 return dc->out->width;
1868         else
1869                 return 0;
1870 }
1871 EXPORT_SYMBOL(tegra_dc_get_out_width);
1872
1873 unsigned tegra_dc_get_out_max_pixclock(const struct tegra_dc *dc)
1874 {
1875         if (dc && dc->out)
1876                 return dc->out->max_pixclock;
1877         else
1878                 return 0;
1879 }
1880 EXPORT_SYMBOL(tegra_dc_get_out_max_pixclock);
1881
1882 void tegra_dc_enable_crc(struct tegra_dc *dc)
1883 {
1884         u32 val;
1885
1886         mutex_lock(&dc->lock);
1887         tegra_dc_get(dc);
1888
1889         val = CRC_ALWAYS_ENABLE | CRC_INPUT_DATA_ACTIVE_DATA |
1890                 CRC_ENABLE_ENABLE;
1891         tegra_dc_writel(dc, val, DC_COM_CRC_CONTROL);
1892         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1893         tegra_dc_put(dc);
1894         mutex_unlock(&dc->lock);
1895
1896         /* Register a client of frame_end interrupt */
1897         tegra_dc_config_frame_end_intr(dc, true);
1898 }
1899
1900 void tegra_dc_disable_crc(struct tegra_dc *dc)
1901 {
1902         /* Unregister a client of frame_end interrupt */
1903         tegra_dc_config_frame_end_intr(dc, false);
1904
1905         mutex_lock(&dc->lock);
1906         tegra_dc_get(dc);
1907         tegra_dc_writel(dc, 0x0, DC_COM_CRC_CONTROL);
1908         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1909
1910         tegra_dc_put(dc);
1911         mutex_unlock(&dc->lock);
1912 }
1913
1914 u32 tegra_dc_read_checksum_latched(struct tegra_dc *dc)
1915 {
1916         int crc = 0;
1917
1918         if (!dc) {
1919                 pr_err("Failed to get dc: NULL parameter.\n");
1920                 goto crc_error;
1921         }
1922
1923         /* If gated quitely return */
1924         if (!tegra_dc_is_powered(dc))
1925                 return 0;
1926
1927         INIT_COMPLETION(dc->crc_complete);
1928         if (dc->crc_pending &&
1929             wait_for_completion_interruptible(&dc->crc_complete)) {
1930                 pr_err("CRC read interrupted.\n");
1931                 goto crc_error;
1932         }
1933
1934         mutex_lock(&dc->lock);
1935         tegra_dc_get(dc);
1936         crc = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM_LATCHED);
1937         tegra_dc_put(dc);
1938         mutex_unlock(&dc->lock);
1939 crc_error:
1940         return crc;
1941 }
1942 EXPORT_SYMBOL(tegra_dc_read_checksum_latched);
1943
1944 bool tegra_dc_windows_are_dirty(struct tegra_dc *dc, u32 win_act_req_mask)
1945 {
1946         u32 val;
1947
1948         if (tegra_platform_is_linsim())
1949                 return false;
1950
1951         val = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL);
1952         if (val & (win_act_req_mask))
1953                 return true;
1954
1955         return false;
1956 }
1957
1958 static inline void enable_dc_irq(const struct tegra_dc *dc)
1959 {
1960         if (tegra_platform_is_fpga())
1961                 /* Always disable DC interrupts on FPGA. */
1962                 disable_irq(dc->irq);
1963         else
1964                 enable_irq(dc->irq);
1965 }
1966
1967 /* assumes dc->lock is already taken. */
1968 static void _tegra_dc_vsync_enable(struct tegra_dc *dc)
1969 {
1970         int vsync_irq;
1971
1972         if (dc->out->type == TEGRA_DC_OUT_DSI)
1973                 vsync_irq = MSF_INT;
1974         else
1975                 vsync_irq = V_BLANK_INT;
1976         tegra_dc_hold_dc_out(dc);
1977         set_bit(V_BLANK_USER, &dc->vblank_ref_count);
1978         tegra_dc_unmask_interrupt(dc, vsync_irq);
1979 }
1980
1981 void tegra_dc_vsync_enable(struct tegra_dc *dc)
1982 {
1983         mutex_lock(&dc->lock);
1984         _tegra_dc_vsync_enable(dc);
1985         mutex_unlock(&dc->lock);
1986 }
1987
1988 /* assumes dc->lock is already taken. */
1989 static void _tegra_dc_vsync_disable(struct tegra_dc *dc)
1990 {
1991         int vsync_irq;
1992
1993         if (dc->out->type == TEGRA_DC_OUT_DSI)
1994                 vsync_irq = MSF_INT;
1995         else
1996                 vsync_irq = V_BLANK_INT;
1997         clear_bit(V_BLANK_USER, &dc->vblank_ref_count);
1998         if (!dc->vblank_ref_count)
1999                 tegra_dc_mask_interrupt(dc, vsync_irq);
2000         tegra_dc_release_dc_out(dc);
2001 }
2002
2003 void tegra_dc_vsync_disable(struct tegra_dc *dc)
2004 {
2005         mutex_lock(&dc->lock);
2006         _tegra_dc_vsync_disable(dc);
2007         mutex_unlock(&dc->lock);
2008 }
2009
2010 bool tegra_dc_has_vsync(struct tegra_dc *dc)
2011 {
2012         return true;
2013 }
2014
2015 /* assumes dc->lock is already taken. */
2016 static void _tegra_dc_user_vsync_enable(struct tegra_dc *dc, bool enable)
2017 {
2018         if (enable) {
2019                 dc->out->user_needs_vblank++;
2020                 init_completion(&dc->out->user_vblank_comp);
2021                 _tegra_dc_vsync_enable(dc);
2022         } else {
2023                 _tegra_dc_vsync_disable(dc);
2024                 dc->out->user_needs_vblank--;
2025         }
2026 }
2027
2028 int tegra_dc_wait_for_vsync(struct tegra_dc *dc)
2029 {
2030         unsigned long timeout_ms;
2031         unsigned long refresh; /* in 1000th Hz */
2032         int ret;
2033
2034         mutex_lock(&dc->lp_lock);
2035         mutex_lock(&dc->lock);
2036         if (!dc->enabled) {
2037                 ret = -ENOTTY;
2038                 goto out;
2039         }
2040         refresh = tegra_dc_calc_refresh(&dc->mode);
2041         /* time out if waiting took more than 2 frames */
2042         timeout_ms = DIV_ROUND_UP(2 * 1000000, refresh);
2043         _tegra_dc_user_vsync_enable(dc, true);
2044         mutex_unlock(&dc->lock);
2045         ret = wait_for_completion_interruptible_timeout(
2046                 &dc->out->user_vblank_comp, msecs_to_jiffies(timeout_ms));
2047         mutex_lock(&dc->lock);
2048         _tegra_dc_user_vsync_enable(dc, false);
2049 out:
2050         mutex_unlock(&dc->lock);
2051         mutex_unlock(&dc->lp_lock);
2052         return ret;
2053 }
2054
2055 static void tegra_dc_prism_update_backlight(struct tegra_dc *dc)
2056 {
2057         /* Do the actual brightness update outside of the mutex dc->lock */
2058         if (dc->out->sd_settings && !dc->out->sd_settings->bl_device &&
2059                 dc->out->sd_settings->bl_device_name) {
2060                 char *bl_device_name =
2061                         dc->out->sd_settings->bl_device_name;
2062                 dc->out->sd_settings->bl_device =
2063                         get_backlight_device_by_name(bl_device_name);
2064         }
2065
2066         if (dc->out->sd_settings && dc->out->sd_settings->bl_device) {
2067                 struct backlight_device *bl = dc->out->sd_settings->bl_device;
2068                 backlight_update_status(bl);
2069         }
2070 }
2071
2072 static void tegra_dc_vblank(struct work_struct *work)
2073 {
2074         struct tegra_dc *dc = container_of(work, struct tegra_dc, vblank_work);
2075         bool nvsd_updated = false;
2076
2077         mutex_lock(&dc->lock);
2078
2079         if (!dc->enabled) {
2080                 mutex_unlock(&dc->lock);
2081                 return;
2082         }
2083
2084         tegra_dc_get(dc);
2085
2086         /* Clear the V_BLANK_FLIP bit of vblank ref-count if update is clean. */
2087         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
2088                 clear_bit(V_BLANK_FLIP, &dc->vblank_ref_count);
2089
2090         /* Update the SD brightness */
2091         if (dc->out->sd_settings && !dc->out->sd_settings->use_vpulse2) {
2092                 nvsd_updated = nvsd_update_brightness(dc);
2093                 /* Ref-count vblank if nvsd is on-going. Otherwise, clean the
2094                  * V_BLANK_NVSD bit of vblank ref-count. */
2095                 if (nvsd_updated) {
2096                         set_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2097                         tegra_dc_unmask_interrupt(dc, V_BLANK_INT);
2098                 } else {
2099                         clear_bit(V_BLANK_NVSD, &dc->vblank_ref_count);
2100                 }
2101         }
2102
2103         /* Mask vblank interrupt if ref-count is zero. */
2104         if (!dc->vblank_ref_count)
2105                 tegra_dc_mask_interrupt(dc, V_BLANK_INT);
2106
2107         tegra_dc_put(dc);
2108         mutex_unlock(&dc->lock);
2109
2110         /* Do the actual brightness update outside of the mutex dc->lock */
2111         if (nvsd_updated)
2112                 tegra_dc_prism_update_backlight(dc);
2113 }
2114
2115 static void tegra_dc_one_shot_worker(struct work_struct *work)
2116 {
2117         struct tegra_dc *dc = container_of(
2118                 to_delayed_work(work), struct tegra_dc, one_shot_work);
2119         mutex_lock(&dc->lock);
2120
2121         /* memory client has gone idle */
2122         tegra_dc_clear_bandwidth(dc);
2123
2124         if (dc->out_ops && dc->out_ops->idle) {
2125                 tegra_dc_io_start(dc);
2126                 dc->out_ops->idle(dc);
2127                 tegra_dc_io_end(dc);
2128         }
2129
2130         mutex_unlock(&dc->lock);
2131 }
2132
2133 /* return an arbitrarily large number if count overflow occurs.
2134  * make it a nice base-10 number to show up in stats output */
2135 static u64 tegra_dc_underflow_count(struct tegra_dc *dc, unsigned reg)
2136 {
2137         unsigned count = tegra_dc_readl(dc, reg);
2138
2139         tegra_dc_writel(dc, 0, reg);
2140         return ((count & 0x80000000) == 0) ? count : 10000000000ll;
2141 }
2142
2143 static void tegra_dc_underflow_handler(struct tegra_dc *dc)
2144 {
2145         const u32 masks[] = {
2146                 WIN_A_UF_INT,
2147                 WIN_B_UF_INT,
2148                 WIN_C_UF_INT,
2149 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2150         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2151         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2152                 WIN_D_UF_INT,
2153                 HC_UF_INT,
2154                 WIN_T_UF_INT,
2155 #endif
2156         };
2157         int i;
2158
2159         dc->stats.underflows++;
2160         if (dc->underflow_mask & WIN_A_UF_INT)
2161                 dc->stats.underflows_a += tegra_dc_underflow_count(dc,
2162                         DC_WINBUF_AD_UFLOW_STATUS);
2163         if (dc->underflow_mask & WIN_B_UF_INT)
2164                 dc->stats.underflows_b += tegra_dc_underflow_count(dc,
2165                         DC_WINBUF_BD_UFLOW_STATUS);
2166         if (dc->underflow_mask & WIN_C_UF_INT)
2167                 dc->stats.underflows_c += tegra_dc_underflow_count(dc,
2168                         DC_WINBUF_CD_UFLOW_STATUS);
2169 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2170         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2171         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2172         if (dc->underflow_mask & HC_UF_INT)
2173                 dc->stats.underflows_h += tegra_dc_underflow_count(dc,
2174                         DC_WINBUF_HD_UFLOW_STATUS);
2175         if (dc->underflow_mask & WIN_D_UF_INT)
2176                 dc->stats.underflows_d += tegra_dc_underflow_count(dc,
2177                         DC_WINBUF_DD_UFLOW_STATUS);
2178         if (dc->underflow_mask & WIN_T_UF_INT)
2179                 dc->stats.underflows_t += tegra_dc_underflow_count(dc,
2180                         DC_WINBUF_TD_UFLOW_STATUS);
2181 #endif
2182
2183         /* Check for any underflow reset conditions */
2184         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2185                 if (WARN_ONCE(i >= ARRAY_SIZE(masks),
2186                         "underflow stats unsupported"))
2187                         break; /* bail if the table above is missing entries */
2188                 if (!masks[i])
2189                         continue; /* skip empty entries */
2190
2191                 if (dc->underflow_mask & masks[i]) {
2192                         dc->windows[i].underflows++;
2193
2194 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2195                         if (i < 3 && dc->windows[i].underflows > 4) {
2196                                 schedule_work(&dc->reset_work);
2197                                 /* reset counter */
2198                                 dc->windows[i].underflows = 0;
2199                                 trace_display_reset(dc);
2200                         }
2201 #endif
2202 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2203                         if (i < 3 && dc->windows[i].underflows > 4) {
2204                                 trace_display_reset(dc);
2205                                 tegra_dc_writel(dc, UF_LINE_FLUSH,
2206                                                 DC_DISP_DISP_MISC_CONTROL);
2207                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2208                                                 DC_CMD_STATE_CONTROL);
2209
2210                                 tegra_dc_writel(dc, 0,
2211                                                 DC_DISP_DISP_MISC_CONTROL);
2212                                 tegra_dc_writel(dc, GENERAL_ACT_REQ,
2213                                                 DC_CMD_STATE_CONTROL);
2214                         }
2215 #endif
2216                 } else {
2217                         dc->windows[i].underflows = 0;
2218                 }
2219         }
2220
2221         /* Clear the underflow mask now that we've checked it. */
2222         tegra_dc_writel(dc, dc->underflow_mask, DC_CMD_INT_STATUS);
2223         dc->underflow_mask = 0;
2224         tegra_dc_unmask_interrupt(dc, ALL_UF_INT());
2225         trace_underflow(dc);
2226 }
2227
2228 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2229 static void tegra_dc_vpulse2(struct work_struct *work)
2230 {
2231         struct tegra_dc *dc = container_of(work, struct tegra_dc, vpulse2_work);
2232         bool nvsd_updated = false;
2233
2234         mutex_lock(&dc->lock);
2235
2236         if (!dc->enabled) {
2237                 mutex_unlock(&dc->lock);
2238                 return;
2239         }
2240
2241         tegra_dc_get(dc);
2242
2243         /* Clear the V_PULSE2_FLIP if no update */
2244         if (!tegra_dc_windows_are_dirty(dc, WIN_ALL_ACT_REQ))
2245                 clear_bit(V_PULSE2_FLIP, &dc->vpulse2_ref_count);
2246
2247         /* Update the SD brightness */
2248         if (dc->out->sd_settings && dc->out->sd_settings->use_vpulse2) {
2249                 nvsd_updated = nvsd_update_brightness(dc);
2250                 if (nvsd_updated) {
2251                         set_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
2252                         tegra_dc_unmask_interrupt(dc, V_PULSE2_INT);
2253                 } else {
2254                         clear_bit(V_PULSE2_NVSD, &dc->vpulse2_ref_count);
2255                 }
2256         }
2257
2258         /* Mask vpulse2 interrupt if ref-count is zero. */
2259         if (!dc->vpulse2_ref_count)
2260                 tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2261
2262         tegra_dc_put(dc);
2263         mutex_unlock(&dc->lock);
2264
2265         /* Do the actual brightness update outside of the mutex dc->lock */
2266         if (nvsd_updated)
2267                 tegra_dc_prism_update_backlight(dc);
2268 }
2269 #endif
2270
2271 static void tegra_dc_process_vblank(struct tegra_dc *dc, ktime_t timestamp)
2272 {
2273         if (test_bit(V_BLANK_USER, &dc->vblank_ref_count))
2274                 tegra_dc_ext_process_vblank(dc->ndev->id, timestamp);
2275 #ifdef CONFIG_ADF_TEGRA
2276         tegra_adf_process_vblank(dc->adf, timestamp);
2277 #endif
2278 }
2279
2280 static void tegra_dc_one_shot_irq(struct tegra_dc *dc, unsigned long status,
2281                 ktime_t timestamp)
2282 {
2283         /* pending user vblank, so wakeup */
2284         if (status & (V_BLANK_INT | MSF_INT)) {
2285                 if (dc->out->user_needs_vblank) {
2286                         dc->out->user_needs_vblank = false;
2287                         complete(&dc->out->user_vblank_comp);
2288                 }
2289                 tegra_dc_process_vblank(dc, timestamp);
2290         }
2291
2292         if (status & V_BLANK_INT) {
2293                 /* Sync up windows. */
2294                 tegra_dc_trigger_windows(dc);
2295
2296                 /* Schedule any additional bottom-half vblank actvities. */
2297                 queue_work(system_freezable_wq, &dc->vblank_work);
2298         }
2299
2300         if (status & FRAME_END_INT) {
2301                 /* Mark the frame_end as complete. */
2302                 dc->crc_pending = false;
2303                 if (!completion_done(&dc->frame_end_complete))
2304                         complete(&dc->frame_end_complete);
2305                 if (!completion_done(&dc->crc_complete))
2306                         complete(&dc->crc_complete);
2307
2308                 if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE && !dc->nvsr)
2309                         tegra_dc_put(dc);
2310         }
2311
2312 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2313         if (status & V_PULSE2_INT)
2314                 queue_work(system_freezable_wq, &dc->vpulse2_work);
2315 #endif
2316 }
2317
2318 static void tegra_dc_continuous_irq(struct tegra_dc *dc, unsigned long status,
2319                 ktime_t timestamp)
2320 {
2321         /* Schedule any additional bottom-half vblank actvities. */
2322         if (status & V_BLANK_INT)
2323                 queue_work(system_freezable_wq, &dc->vblank_work);
2324
2325         if (status & (V_BLANK_INT | MSF_INT))
2326                 tegra_dc_process_vblank(dc, timestamp);
2327
2328         if (status & FRAME_END_INT) {
2329                 struct timespec tm = CURRENT_TIME;
2330                 dc->frame_end_timestamp = timespec_to_ns(&tm);
2331                 wake_up(&dc->timestamp_wq);
2332
2333                 /* Mark the frame_end as complete. */
2334                 if (!completion_done(&dc->frame_end_complete))
2335                         complete(&dc->frame_end_complete);
2336                 if (!completion_done(&dc->crc_complete))
2337                         complete(&dc->crc_complete);
2338
2339                 tegra_dc_trigger_windows(dc);
2340         }
2341
2342 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2343         if (status & V_PULSE2_INT)
2344                 queue_work(system_freezable_wq, &dc->vpulse2_work);
2345 #endif
2346 }
2347
2348 /* XXX: Not sure if we limit look ahead to 1 frame */
2349 bool tegra_dc_is_within_n_vsync(struct tegra_dc *dc, s64 ts)
2350 {
2351         BUG_ON(!dc->frametime_ns);
2352         return ((ts - dc->frame_end_timestamp) < dc->frametime_ns);
2353 }
2354
2355 bool tegra_dc_does_vsync_separate(struct tegra_dc *dc, s64 new_ts, s64 old_ts)
2356 {
2357         BUG_ON(!dc->frametime_ns);
2358         return (((new_ts - old_ts) > dc->frametime_ns)
2359                 || (div_s64((new_ts - dc->frame_end_timestamp), dc->frametime_ns)
2360                         != div_s64((old_ts - dc->frame_end_timestamp),
2361                                 dc->frametime_ns)));
2362 }
2363
2364 static irqreturn_t tegra_dc_irq(int irq, void *ptr)
2365 {
2366         ktime_t timestamp = ktime_get();
2367         struct tegra_dc *dc = ptr;
2368         unsigned long status;
2369         unsigned long underflow_mask;
2370         u32 val;
2371         int need_disable = 0;
2372
2373         if (tegra_platform_is_fpga())
2374                 return IRQ_NONE;
2375
2376         mutex_lock(&dc->lock);
2377         if (!tegra_dc_is_powered(dc)) {
2378                 mutex_unlock(&dc->lock);
2379                 return IRQ_HANDLED;
2380         }
2381
2382         tegra_dc_get(dc);
2383
2384         if (!dc->enabled || !nvhost_module_powered_ext(dc->ndev)) {
2385                 dev_dbg(&dc->ndev->dev, "IRQ when DC not powered!\n");
2386                 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2387                 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
2388                 tegra_dc_put(dc);
2389                 mutex_unlock(&dc->lock);
2390                 return IRQ_HANDLED;
2391         }
2392
2393         /* clear all status flags except underflow, save those for the worker */
2394         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
2395         tegra_dc_writel(dc, status & ~ALL_UF_INT(), DC_CMD_INT_STATUS);
2396         val = tegra_dc_readl(dc, DC_CMD_INT_MASK);
2397         tegra_dc_writel(dc, val & ~ALL_UF_INT(), DC_CMD_INT_MASK);
2398
2399         /*
2400          * Overlays can get thier internal state corrupted during and underflow
2401          * condition.  The only way to fix this state is to reset the DC.
2402          * if we get 4 consecutive frames with underflows, assume we're
2403          * hosed and reset.
2404          */
2405         underflow_mask = status & ALL_UF_INT();
2406
2407         /* Check underflow */
2408         if (underflow_mask) {
2409                 dc->underflow_mask |= underflow_mask;
2410                 schedule_delayed_work(&dc->underflow_work,
2411                         msecs_to_jiffies(1));
2412         }
2413
2414         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2415                 tegra_dc_one_shot_irq(dc, status, timestamp);
2416         else
2417                 tegra_dc_continuous_irq(dc, status, timestamp);
2418
2419         if (dc->nvsr)
2420                 tegra_dc_nvsr_irq(dc->nvsr, status);
2421
2422         /* update video mode if it has changed since the last frame */
2423         if (status & (FRAME_END_INT | V_BLANK_INT))
2424                 if (tegra_dc_update_mode(dc))
2425                         need_disable = 1; /* force display off on error */
2426
2427         if (status & FRAME_END_INT)
2428                 if (dc->disp_active_dirty) {
2429                         tegra_dc_writel(dc, dc->mode.h_active |
2430                                 (dc->mode.v_active << 16), DC_DISP_DISP_ACTIVE);
2431                         tegra_dc_writel(dc,
2432                                 GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2433
2434                         dc->disp_active_dirty = false;
2435                 }
2436
2437         tegra_dc_put(dc);
2438         mutex_unlock(&dc->lock);
2439
2440         if (need_disable)
2441                 tegra_dc_disable(dc);
2442         return IRQ_HANDLED;
2443 }
2444
2445 void tegra_dc_set_color_control(struct tegra_dc *dc)
2446 {
2447         u32 color_control;
2448
2449         switch (dc->out->depth) {
2450         case 3:
2451                 color_control = BASE_COLOR_SIZE111;
2452                 break;
2453
2454         case 6:
2455                 color_control = BASE_COLOR_SIZE222;
2456                 break;
2457
2458         case 8:
2459                 color_control = BASE_COLOR_SIZE332;
2460                 break;
2461
2462         case 9:
2463                 color_control = BASE_COLOR_SIZE333;
2464                 break;
2465
2466         case 12:
2467                 color_control = BASE_COLOR_SIZE444;
2468                 break;
2469
2470         case 15:
2471                 color_control = BASE_COLOR_SIZE555;
2472                 break;
2473
2474         case 16:
2475                 color_control = BASE_COLOR_SIZE565;
2476                 break;
2477
2478         case 18:
2479                 color_control = BASE_COLOR_SIZE666;
2480                 break;
2481
2482         default:
2483                 color_control = BASE_COLOR_SIZE888;
2484                 break;
2485         }
2486
2487         switch (dc->out->dither) {
2488         case TEGRA_DC_UNDEFINED_DITHER:
2489         case TEGRA_DC_DISABLE_DITHER:
2490                 color_control |= DITHER_CONTROL_DISABLE;
2491                 break;
2492         case TEGRA_DC_ORDERED_DITHER:
2493                 color_control |= DITHER_CONTROL_ORDERED;
2494                 break;
2495 #ifdef CONFIG_TEGRA_DC_TEMPORAL_DITHER
2496         case TEGRA_DC_TEMPORAL_DITHER:
2497                 color_control |= DITHER_CONTROL_TEMPORAL;
2498                 break;
2499 #else
2500         case TEGRA_DC_ERRDIFF_DITHER:
2501                 /* The line buffer for error-diffusion dither is limited
2502                  * to 1280 pixels per line. This limits the maximum
2503                  * horizontal active area size to 1280 pixels when error
2504                  * diffusion is enabled.
2505                  */
2506                 BUG_ON(dc->mode.h_active > 1280);
2507                 color_control |= DITHER_CONTROL_ERRDIFF;
2508                 break;
2509 #endif
2510         default:
2511                 dev_err(&dc->ndev->dev, "Error: Unsupported dithering mode\n");
2512         }
2513
2514 #ifdef CONFIG_TEGRA_DC_CMU
2515         if (dc->cmu_enabled)
2516                 color_control |= CMU_ENABLE;
2517 #endif
2518
2519         tegra_dc_writel(dc, color_control, DC_DISP_DISP_COLOR_CONTROL);
2520 }
2521
2522 static u32 get_syncpt(struct tegra_dc *dc, int idx)
2523 {
2524         if (idx >= 0 && idx < ARRAY_SIZE(dc->win_syncpt))
2525                 return dc->win_syncpt[idx];
2526         BUG();
2527 }
2528
2529 static void tegra_dc_init_vpulse2_int(struct tegra_dc *dc)
2530 {
2531 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
2532         u32 start, end;
2533         unsigned long val;
2534
2535         val = V_PULSE2_H_POSITION(0) | V_PULSE2_LAST(0x1);
2536         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_CONTROL);
2537
2538         start = dc->mode.v_ref_to_sync + dc->mode.v_sync_width +
2539                 dc->mode.v_back_porch + dc->mode.v_active;
2540         end = start + 1;
2541         val = V_PULSE2_START_A(start) + V_PULSE2_END_A(end);
2542         tegra_dc_writel(dc, val, DC_DISP_V_PULSE2_POSITION_A);
2543
2544         val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
2545         val |= V_PULSE2_INT;
2546         tegra_dc_writel(dc, val , DC_CMD_INT_ENABLE);
2547
2548         tegra_dc_mask_interrupt(dc, V_PULSE2_INT);
2549         tegra_dc_writel(dc, V_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
2550 #endif
2551 }
2552
2553 static int tegra_dc_init(struct tegra_dc *dc)
2554 {
2555         int i;
2556         int int_enable;
2557         u32 val;
2558
2559         tegra_dc_io_start(dc);
2560         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
2561         if (dc->ctrl_num == 0) {
2562                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0A,
2563                                       TEGRA_MC_PRIO_MED);
2564                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0B,
2565                                       TEGRA_MC_PRIO_MED);
2566                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0C,
2567                                       TEGRA_MC_PRIO_MED);
2568 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2569                 /* only present on Tegra2 and 3 */
2570                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1B,
2571                                       TEGRA_MC_PRIO_MED);
2572 #endif
2573                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHC,
2574                                       TEGRA_MC_PRIO_HIGH);
2575         } else if (dc->ctrl_num == 1) {
2576                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0AB,
2577                                       TEGRA_MC_PRIO_MED);
2578                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0BB,
2579                                       TEGRA_MC_PRIO_MED);
2580                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY0CB,
2581                                       TEGRA_MC_PRIO_MED);
2582 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
2583                 /* only present on Tegra2 and 3 */
2584                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAY1BB,
2585                                       TEGRA_MC_PRIO_MED);
2586 #endif
2587                 tegra_mc_set_priority(TEGRA_MC_CLIENT_DISPLAYHCB,
2588                                       TEGRA_MC_PRIO_HIGH);
2589         }
2590         tegra_dc_writel(dc, 0x00000100 | dc->vblank_syncpt,
2591                         DC_CMD_CONT_SYNCPT_VSYNC);
2592
2593         tegra_dc_writel(dc, 0x00004700, DC_CMD_INT_TYPE);
2594 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
2595         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
2596         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
2597         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2598                 WIN_T_UF_INT | WIN_D_UF_INT | HC_UF_INT |
2599                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2600                 DC_CMD_INT_POLARITY);
2601 #else
2602         tegra_dc_writel(dc, WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT |
2603                 WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT,
2604                 DC_CMD_INT_POLARITY);
2605 #endif
2606         tegra_dc_writel(dc, 0x00202020, DC_DISP_MEM_HIGH_PRIORITY);
2607         tegra_dc_writel(dc, 0x00010101, DC_DISP_MEM_HIGH_PRIORITY_TIMER);
2608 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
2609         tegra_dc_writel(dc, 0x00000000, DC_DISP_DISP_MISC_CONTROL);
2610 #endif
2611         /* enable interrupts for vblank, frame_end and underflows */
2612         int_enable = (FRAME_END_INT | V_BLANK_INT | ALL_UF_INT());
2613         /* for panels with one-shot mode enable tearing effect interrupt */
2614         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
2615                 int_enable |= MSF_INT;
2616
2617         tegra_dc_writel(dc, int_enable, DC_CMD_INT_ENABLE);
2618         tegra_dc_writel(dc, ALL_UF_INT(), DC_CMD_INT_MASK);
2619         tegra_dc_init_vpulse2_int(dc);
2620
2621         tegra_dc_writel(dc, WRITE_MUX_ASSEMBLY | READ_MUX_ASSEMBLY,
2622                 DC_CMD_STATE_ACCESS);
2623
2624 #if !defined(CONFIG_TEGRA_DC_BLENDER_GEN2)
2625         tegra_dc_writel(dc, 0x00000000, DC_DISP_BORDER_COLOR);
2626 #else
2627         tegra_dc_writel(dc, 0x00000000, DC_DISP_BLEND_BACKGROUND_COLOR);
2628 #endif
2629
2630 #ifdef CONFIG_TEGRA_DC_CMU
2631         _tegra_dc_update_cmu(dc, tegra_dc_get_cmu(dc));
2632 #endif
2633         tegra_dc_set_color_control(dc);
2634         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2635                 struct tegra_dc_win *win = &dc->windows[i];
2636                 tegra_dc_writel(dc, WINDOW_A_SELECT << i,
2637                                 DC_CMD_DISPLAY_WINDOW_HEADER);
2638                 tegra_dc_set_csc(dc, &win->csc);
2639                 tegra_dc_set_lut(dc, win);
2640                 tegra_dc_set_scaling_filter(dc);
2641         }
2642
2643 #ifdef CONFIG_TEGRA_DC_WIN_H
2644         /* Window H is set to window mode by default for t14x. */
2645         tegra_dc_writel(dc, WINH_CURS_SELECT(1),
2646                         DC_DISP_BLEND_CURSOR_CONTROL);
2647 #endif
2648
2649         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2650                 u32 syncpt = get_syncpt(dc, i);
2651
2652                 /* refuse to operate on invalid syncpts */
2653                 if (WARN_ON(syncpt == NVSYNCPT_INVALID))
2654                         continue;
2655
2656                 dc->syncpt[i].id = syncpt;
2657
2658                 if (!nvhost_syncpt_read_ext_check(dc->ndev, syncpt, &val))
2659                         dc->syncpt[i].min = dc->syncpt[i].max = val;
2660         }
2661
2662         dc->crc_pending = false;
2663
2664         trace_display_mode(dc, &dc->mode);
2665
2666         if (dc->mode.pclk) {
2667                 if (!dc->initialized) {
2668                         if (tegra_dc_program_mode(dc, &dc->mode)) {
2669                                 tegra_dc_io_end(dc);
2670                                 dev_warn(&dc->ndev->dev,
2671                                         "%s: tegra_dc_program_mode failed\n",
2672                                         __func__);
2673                                 return -EINVAL;
2674                         }
2675                 } else {
2676                         dev_info(&dc->ndev->dev, "DC initialized, "
2677                                         "skipping tegra_dc_program_mode.\n");
2678                 }
2679         }
2680
2681         /* Initialize SD AFTER the modeset.
2682            nvsd_init handles the sd_settings = NULL case. */
2683         nvsd_init(dc, dc->out->sd_settings);
2684
2685         tegra_dc_io_end(dc);
2686
2687         return 0;
2688 }
2689
2690 static bool _tegra_dc_controller_enable(struct tegra_dc *dc)
2691 {
2692         int failed_init = 0;
2693         int i;
2694         struct device_node *np_dpaux;
2695
2696         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2697                 return false;
2698
2699         tegra_dc_unpowergate_locked(dc);
2700
2701         if (dc->out->enable)
2702                 dc->out->enable(&dc->ndev->dev);
2703
2704         tegra_dc_setup_clk(dc, dc->clk);
2705
2706         /* dc clk always on for continuous mode */
2707         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2708                 tegra_dc_clk_enable(dc);
2709         else
2710                 tegra_dvfs_set_rate(dc->clk, dc->mode.pclk);
2711
2712         tegra_dc_get(dc);
2713
2714         tegra_dc_power_on(dc);
2715
2716         /* do not accept interrupts during initialization */
2717         tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2718
2719         enable_dc_irq(dc);
2720
2721         failed_init = tegra_dc_init(dc);
2722         if (failed_init) {
2723                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2724                 disable_irq_nosync(dc->irq);
2725                 tegra_dc_clear_bandwidth(dc);
2726                 if (dc->out && dc->out->disable)
2727                         dc->out->disable();
2728                 tegra_dc_put(dc);
2729                 if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2730                         tegra_dc_clk_disable(dc);
2731                 else
2732                         tegra_dvfs_set_rate(dc->clk, 0);
2733                 dev_warn(&dc->ndev->dev,
2734                         "%s: tegra_dc_init failed\n", __func__);
2735                 return false;
2736         }
2737
2738         np_dpaux = of_find_node_by_path(DPAUX_NODE);
2739         if (np_dpaux || !dc->ndev->dev.of_node)
2740                 tegra_dpaux_pad_power(dc, false);
2741
2742         if (dc->out_ops && dc->out_ops->enable)
2743                 dc->out_ops->enable(dc);
2744
2745         /* force a full blending update */
2746         for (i = 0; i < DC_N_WINDOWS; i++)
2747                 dc->blend.z[i] = -1;
2748
2749         tegra_dc_ext_enable(dc->ext);
2750
2751         /* initialize cursor to defaults, as driver depends on HW state */
2752         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR);
2753         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_NS);
2754 #if defined(CONFIG_ARCH_TEGRA_12x_SOC)
2755         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI);
2756         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_START_ADDR_HI_NS);
2757 #endif
2758         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION);
2759         tegra_dc_writel(dc, 0, DC_DISP_CURSOR_POSITION_NS);
2760         tegra_dc_writel(dc, 0xffffff, DC_DISP_CURSOR_FOREGROUND); /* white */
2761         tegra_dc_writel(dc, 0x000000, DC_DISP_CURSOR_BACKGROUND); /* black */
2762         tegra_dc_writel(dc, 0, DC_DISP_BLEND_CURSOR_CONTROL);
2763
2764         trace_display_enable(dc);
2765
2766         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
2767
2768         if (dc->out->postpoweron)
2769                 dc->out->postpoweron(&dc->ndev->dev);
2770
2771         if (dc->out_ops && dc->out_ops->postpoweron)
2772                 dc->out_ops->postpoweron(dc);
2773
2774         tegra_log_resume_time();
2775         /*
2776          * We will need to reinitialize the display the next time panel
2777          * is enabled.
2778          */
2779         dc->out->flags &= ~TEGRA_DC_OUT_INITIALIZED_MODE;
2780
2781         tegra_dc_put(dc);
2782
2783         return true;
2784 }
2785
2786 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
2787 static bool _tegra_dc_controller_reset_enable(struct tegra_dc *dc)
2788 {
2789         bool ret = true;
2790
2791         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2792                 return false;
2793
2794         if (dc->out->enable)
2795                 dc->out->enable(&dc->ndev->dev);
2796
2797         tegra_dc_setup_clk(dc, dc->clk);
2798         tegra_dc_clk_enable(dc);
2799
2800         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2801                 mutex_lock(&tegra_dcs[1]->lock);
2802                 disable_irq_nosync(tegra_dcs[1]->irq);
2803         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2804                 mutex_lock(&tegra_dcs[0]->lock);
2805                 disable_irq_nosync(tegra_dcs[0]->irq);
2806         }
2807
2808         msleep(5);
2809         tegra_periph_reset_assert(dc->clk);
2810         msleep(2);
2811         if (tegra_platform_is_silicon()) {
2812                 tegra_periph_reset_deassert(dc->clk);
2813                 msleep(1);
2814         }
2815
2816         if (dc->ndev->id == 0 && tegra_dcs[1] != NULL) {
2817                 enable_dc_irq(tegra_dcs[1]);
2818                 mutex_unlock(&tegra_dcs[1]->lock);
2819         } else if (dc->ndev->id == 1 && tegra_dcs[0] != NULL) {
2820                 enable_dc_irq(tegra_dcs[0]);
2821                 mutex_unlock(&tegra_dcs[0]->lock);
2822         }
2823
2824         enable_dc_irq(dc);
2825
2826         if (tegra_dc_init(dc)) {
2827                 dev_err(&dc->ndev->dev, "cannot initialize\n");
2828                 ret = false;
2829         }
2830
2831         if (dc->out_ops && dc->out_ops->enable)
2832                 dc->out_ops->enable(dc);
2833
2834         if (dc->out->postpoweron)
2835                 dc->out->postpoweron(&dc->ndev->dev);
2836
2837         /* force a full blending update */
2838         dc->blend.z[0] = -1;
2839
2840         tegra_dc_ext_enable(dc->ext);
2841
2842         if (!ret) {
2843                 dev_err(&dc->ndev->dev, "initialization failed,disabling");
2844                 _tegra_dc_controller_disable(dc);
2845         }
2846
2847         trace_display_reset(dc);
2848         return ret;
2849 }
2850 #endif
2851
2852 static int _tegra_dc_set_default_videomode(struct tegra_dc *dc)
2853 {
2854         if (dc->mode.pclk == 0) {
2855                 switch (dc->out->type) {
2856                 case TEGRA_DC_OUT_HDMI:
2857                 /* If DC is enable called, and HDMI is connected,
2858                  * but DC is not initialized by bootloader and no
2859                  * mode is set up, then set a fallback mode.
2860                  */
2861                 if (tegra_dc_hpd(dc) && (!dc->initialized)) {
2862                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2863                 } else
2864                         return false;
2865
2866                 break;
2867
2868                 case TEGRA_DC_OUT_DP:
2869                 case TEGRA_DC_OUT_NVSR_DP:
2870                 case TEGRA_DC_OUT_FAKE_DP:
2871                 case TEGRA_DC_OUT_NULL:
2872                         return tegra_dc_set_fb_mode(dc, &tegra_dc_vga_mode, 0);
2873
2874                 /* Do nothing for other outputs for now */
2875                 case TEGRA_DC_OUT_RGB:
2876
2877                 case TEGRA_DC_OUT_DSI:
2878
2879                 default:
2880                         return false;
2881                 }
2882         }
2883
2884         return false;
2885 }
2886
2887 int tegra_dc_set_default_videomode(struct tegra_dc *dc)
2888 {
2889         return _tegra_dc_set_default_videomode(dc);
2890 }
2891
2892 static bool _tegra_dc_enable(struct tegra_dc *dc)
2893 {
2894         if (dc->mode.pclk == 0)
2895                 return false;
2896
2897         if (!dc->out)
2898                 return false;
2899
2900         if (dc->enabled)
2901                 return true;
2902
2903         pm_runtime_get_sync(&dc->ndev->dev);
2904
2905         if (dc->out->type == TEGRA_DC_OUT_HDMI && !tegra_dc_hpd(dc))
2906                 return false;
2907
2908         if (!_tegra_dc_controller_enable(dc)) {
2909                 pm_runtime_put_sync(&dc->ndev->dev);
2910                 return false;
2911         }
2912
2913         return true;
2914 }
2915
2916 void tegra_dc_enable(struct tegra_dc *dc)
2917 {
2918         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
2919                 return;
2920
2921         mutex_lock(&dc->lock);
2922
2923         if (!dc->enabled)
2924                 dc->enabled = _tegra_dc_enable(dc);
2925
2926         mutex_unlock(&dc->lock);
2927         trace_display_mode(dc, &dc->mode);
2928 }
2929
2930 void tegra_dc_disable_window(struct tegra_dc *dc, unsigned win)
2931 {
2932         struct tegra_dc_win *w = &dc->windows[win];
2933
2934         /* reset window bandwidth */
2935         w->bandwidth = 0;
2936         w->new_bandwidth = 0;
2937
2938         /* disable windows */
2939         w->flags &= ~TEGRA_WIN_FLAG_ENABLED;
2940
2941         /* refuse to operate on invalid syncpts */
2942         if (WARN_ON(dc->syncpt[win].id == NVSYNCPT_INVALID))
2943                 return;
2944
2945         /* flush any pending syncpt waits */
2946         dc->syncpt[win].max += 1;
2947         while (dc->syncpt[win].min < dc->syncpt[win].max) {
2948                 trace_display_syncpt_flush(dc, dc->syncpt[win].id,
2949                         dc->syncpt[win].min, dc->syncpt[win].max);
2950                 dc->syncpt[win].min++;
2951                 nvhost_syncpt_cpu_incr_ext(dc->ndev, dc->syncpt[win].id);
2952         }
2953 }
2954
2955 static void _tegra_dc_controller_disable(struct tegra_dc *dc)
2956 {
2957         unsigned i;
2958
2959         tegra_dc_get(dc);
2960
2961         if (atomic_read(&dc->holding)) {
2962                 /* Force release all refs but the last one */
2963                 atomic_set(&dc->holding, 1);
2964                 tegra_dc_release_dc_out(dc);
2965         }
2966
2967         if (dc->out && dc->out->prepoweroff)
2968                 dc->out->prepoweroff();
2969
2970         if (dc->out_ops && dc->out_ops->disable)
2971                 dc->out_ops->disable(dc);
2972
2973         if (tegra_powergate_is_powered(dc->powergate_id))
2974                 tegra_dc_writel(dc, 0, DC_CMD_INT_MASK);
2975
2976         disable_irq_nosync(dc->irq);
2977
2978         tegra_dc_clear_bandwidth(dc);
2979
2980         if (dc->out && dc->out->disable)
2981                 dc->out->disable();
2982
2983         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
2984                 tegra_dc_disable_window(dc, i);
2985         }
2986         trace_display_disable(dc);
2987
2988         if (dc->out_ops && dc->out_ops->postpoweroff)
2989                 dc->out_ops->postpoweroff(dc);
2990
2991         tegra_dc_put(dc);
2992
2993         /* disable always on dc clk in continuous mode */
2994         if (!(dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE))
2995                 tegra_dc_clk_disable(dc);
2996         else
2997                 tegra_dvfs_set_rate(dc->clk, 0);
2998 }
2999
3000 void tegra_dc_stats_enable(struct tegra_dc *dc, bool enable)
3001 {
3002 #if 0 /* underflow interrupt is already enabled by dc reset worker */
3003         u32 val;
3004         if (dc->enabled)  {
3005                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3006                 if (enable)
3007                         val |= (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3008                 else
3009                         val &= ~(WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT);
3010                 tegra_dc_writel(dc, val, DC_CMD_INT_ENABLE);
3011         }
3012 #endif
3013 }
3014
3015 bool tegra_dc_stats_get(struct tegra_dc *dc)
3016 {
3017 #if 0 /* right now it is always enabled */
3018         u32 val;
3019         bool res;
3020
3021         if (dc->enabled)  {
3022                 val = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
3023                 res = !!(val & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT));
3024         } else {
3025                 res = false;
3026         }
3027
3028         return res;
3029 #endif
3030         return true;
3031 }
3032
3033 /* blank selected windows by disabling them */
3034 void tegra_dc_blank(struct tegra_dc *dc, unsigned windows)
3035 {
3036         struct tegra_dc_win *dcwins[DC_N_WINDOWS];
3037         unsigned i;
3038         unsigned long int blank_windows;
3039         int nr_win = 0;
3040
3041         blank_windows = windows & dc->valid_windows;
3042
3043         if (!blank_windows)
3044                 return;
3045
3046         for_each_set_bit(i, &blank_windows, DC_N_WINDOWS) {
3047                 dcwins[nr_win] = tegra_dc_get_window(dc, i);
3048                 if (!dcwins[nr_win])
3049                         continue;
3050                 dcwins[nr_win++]->flags &= ~TEGRA_WIN_FLAG_ENABLED;
3051         }
3052
3053         tegra_dc_update_windows(dcwins, nr_win, NULL, true);
3054         tegra_dc_sync_windows(dcwins, nr_win);
3055         tegra_dc_program_bandwidth(dc, true);
3056 }
3057
3058 int tegra_dc_restore(struct tegra_dc *dc)
3059 {
3060         return tegra_dc_ext_restore(dc->ext);
3061 }
3062
3063 static void _tegra_dc_disable(struct tegra_dc *dc)
3064 {
3065 #ifdef CONFIG_TEGRA_DC_CMU
3066         /* power down resets the registers, setting to true
3067          * causes CMU to be restored in tegra_dc_init(). */
3068         dc->cmu_dirty = true;
3069 #endif
3070
3071         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE) {
3072                 mutex_lock(&dc->one_shot_lock);
3073                 cancel_delayed_work_sync(&dc->one_shot_work);
3074         }
3075
3076         tegra_dc_io_start(dc);
3077         _tegra_dc_controller_disable(dc);
3078         tegra_dc_io_end(dc);
3079
3080         tegra_dc_powergate_locked(dc);
3081
3082         if (dc->out->flags & TEGRA_DC_OUT_ONE_SHOT_MODE)
3083                 mutex_unlock(&dc->one_shot_lock);
3084         pm_runtime_put(&dc->ndev->dev);
3085
3086         tegra_log_suspend_time();
3087 }
3088
3089 void tegra_dc_disable(struct tegra_dc *dc)
3090 {
3091         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3092                 return;
3093
3094         tegra_dc_ext_disable(dc->ext);
3095
3096         /* it's important that new underflow work isn't scheduled before the
3097          * lock is acquired. */
3098         cancel_delayed_work_sync(&dc->underflow_work);
3099
3100         mutex_lock(&dc->lp_lock);
3101         mutex_lock(&dc->lock);
3102
3103         if (dc->enabled) {
3104                 dc->enabled = false;
3105                 dc->blanked = false;
3106
3107                 if (!dc->suspended)
3108                         _tegra_dc_disable(dc);
3109         }
3110
3111 #ifdef CONFIG_SWITCH
3112         switch_set_state(&dc->modeset_switch, 0);
3113 #endif
3114         mutex_unlock(&dc->lock);
3115         mutex_unlock(&dc->lp_lock);
3116         synchronize_irq(dc->irq);
3117         trace_display_mode(dc, &dc->mode);
3118
3119         /* disable pending clks due to uncompleted frames */
3120         while (tegra_is_clk_enabled(dc->clk))
3121                 tegra_dc_put(dc);
3122 }
3123
3124 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3125 static void tegra_dc_reset_worker(struct work_struct *work)
3126 {
3127         struct tegra_dc *dc =
3128                 container_of(work, struct tegra_dc, reset_work);
3129
3130         unsigned long val = 0;
3131
3132         mutex_lock(&shared_lock);
3133
3134         dev_warn(&dc->ndev->dev,
3135                 "overlay stuck in underflow state.  resetting.\n");
3136
3137         tegra_dc_ext_disable(dc->ext);
3138
3139         mutex_lock(&dc->lock);
3140
3141         if (dc->enabled == false)
3142                 goto unlock;
3143
3144         dc->enabled = false;
3145
3146         /*
3147          * off host read bus
3148          */
3149         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
3150         val &= ~(0x00000100);
3151         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
3152
3153         /*
3154          * set DC to STOP mode
3155          */
3156         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
3157
3158         msleep(10);
3159
3160         _tegra_dc_controller_disable(dc);
3161
3162         /* _tegra_dc_controller_reset_enable deasserts reset */
3163         _tegra_dc_controller_reset_enable(dc);
3164
3165         dc->enabled = true;
3166
3167         /* reopen host read bus */
3168         val = tegra_dc_readl(dc, DC_CMD_CONT_SYNCPT_VSYNC);
3169         val &= ~(0x00000100);
3170         val |= 0x100;
3171         tegra_dc_writel(dc, val, DC_CMD_CONT_SYNCPT_VSYNC);
3172
3173 unlock:
3174         mutex_unlock(&dc->lock);
3175         mutex_unlock(&shared_lock);
3176         trace_display_reset(dc);
3177 }
3178 #endif
3179
3180 static void tegra_dc_underflow_worker(struct work_struct *work)
3181 {
3182         struct tegra_dc *dc = container_of(
3183                 to_delayed_work(work), struct tegra_dc, underflow_work);
3184
3185         mutex_lock(&dc->lock);
3186         tegra_dc_get(dc);
3187
3188         if (dc->enabled) {
3189                 tegra_dc_underflow_handler(dc);
3190         }
3191         tegra_dc_put(dc);
3192         mutex_unlock(&dc->lock);
3193 }
3194
3195 static void (*flip_callback)(void);
3196 static spinlock_t flip_callback_lock;
3197 static bool init_tegra_dc_flip_callback_called;
3198
3199 static int __init init_tegra_dc_flip_callback(void)
3200 {
3201         spin_lock_init(&flip_callback_lock);
3202         init_tegra_dc_flip_callback_called = true;
3203         return 0;
3204 }
3205
3206 pure_initcall(init_tegra_dc_flip_callback);
3207
3208 int tegra_dc_set_flip_callback(void (*callback)(void))
3209 {
3210         WARN_ON(!init_tegra_dc_flip_callback_called);
3211
3212         spin_lock(&flip_callback_lock);
3213         flip_callback = callback;
3214         spin_unlock(&flip_callback_lock);
3215
3216         return 0;
3217 }
3218 EXPORT_SYMBOL(tegra_dc_set_flip_callback);
3219
3220 int tegra_dc_unset_flip_callback()
3221 {
3222         spin_lock(&flip_callback_lock);
3223         flip_callback = NULL;
3224         spin_unlock(&flip_callback_lock);
3225
3226         return 0;
3227 }
3228 EXPORT_SYMBOL(tegra_dc_unset_flip_callback);
3229
3230 void tegra_dc_call_flip_callback()
3231 {
3232         spin_lock(&flip_callback_lock);
3233         if (flip_callback)
3234                 flip_callback();
3235         spin_unlock(&flip_callback_lock);
3236 }
3237 EXPORT_SYMBOL(tegra_dc_call_flip_callback);
3238
3239 #ifdef CONFIG_SWITCH
3240 static ssize_t switch_modeset_print_mode(struct switch_dev *sdev, char *buf)
3241 {
3242         struct tegra_dc *dc =
3243                 container_of(sdev, struct tegra_dc, modeset_switch);
3244
3245         if (!sdev->state)
3246                 return sprintf(buf, "offline\n");
3247
3248         return sprintf(buf, "%dx%d\n", dc->mode.h_active, dc->mode.v_active);
3249 }
3250 #endif
3251
3252 static int tegra_dc_probe(struct platform_device *ndev)
3253 {
3254         struct tegra_dc *dc;
3255         struct tegra_dc_mode *mode;
3256         struct tegra_dc_platform_data *dt_pdata = NULL;
3257         struct clk *clk;
3258 #ifndef CONFIG_TEGRA_ISOMGR
3259         struct clk *emc_clk;
3260 #else
3261         int isomgr_client_id = -1;
3262 #endif
3263         struct device_node *np = ndev->dev.of_node;
3264         struct resource *res;
3265         struct resource dt_res;
3266         struct resource *base_res;
3267         struct resource *fb_mem = NULL;
3268         int ret = 0;
3269         void __iomem *base;
3270         int irq;
3271         int i;
3272
3273         if (tegra_platform_is_linsim()) {
3274                 dev_info(&ndev->dev, "DC instances are not present on linsim\n");
3275                 return -ENODEV;
3276         }
3277
3278         if (!np && !ndev->dev.platform_data) {
3279                 dev_err(&ndev->dev, "no platform data\n");
3280                 return -ENOENT;
3281         }
3282
3283         /* Specify parameters for the maximum physical segment size. */
3284         ndev->dev.dma_parms = &tegra_dc_dma_parameters;
3285
3286         dc = kzalloc(sizeof(struct tegra_dc), GFP_KERNEL);
3287         if (!dc) {
3288                 dev_err(&ndev->dev, "can't allocate memory for tegra_dc\n");
3289                 return -ENOMEM;
3290         }
3291
3292         if (np) {
3293 #ifdef CONFIG_OF
3294                 irq = of_irq_to_resource(np, 0, NULL);
3295                 if (!irq)
3296                         goto err_free;
3297 #endif
3298
3299                 ret = of_address_to_resource(np, 0, &dt_res);
3300                 if (ret)
3301                         goto err_free;
3302
3303                 ndev->id = tegra_dc_set(dc, -1);
3304                 if (ndev->id < 0) {
3305                         dev_err(&ndev->dev, "can't add dc\n");
3306                         goto err_free;
3307                 }
3308
3309                 dev_info(&ndev->dev, "Display dc.%08x registered with id=%d\n",
3310                                 (unsigned int)dt_res.start, ndev->id);
3311
3312                 if (dt_res.start == TEGRA_DISPLAY_BASE)
3313                         dc->ctrl_num = 0;
3314                 else if (dt_res.start == TEGRA_DISPLAY2_BASE)
3315                         dc->ctrl_num = 1;
3316                 else
3317                         goto err_free;
3318
3319                 res = &dt_res;
3320
3321                 dt_pdata = of_dc_parse_platform_data(ndev);
3322                 if (dt_pdata == NULL)
3323                         goto err_free;
3324         } else {
3325
3326                 dc->ctrl_num = ndev->id;
3327
3328                 irq = platform_get_irq_byname(ndev, "irq");
3329                 if (irq <= 0) {
3330                         dev_err(&ndev->dev, "no irq\n");
3331                         ret = -ENOENT;
3332                         goto err_free;
3333                 }
3334
3335                 res = platform_get_resource_byname(ndev,
3336                         IORESOURCE_MEM, "regs");
3337                 if (!res) {
3338                         dev_err(&ndev->dev, "no mem resource\n");
3339                         ret = -ENOENT;
3340                         goto err_free;
3341                 }
3342
3343                 if (tegra_dc_set(dc, ndev->id) < 0) {
3344                         dev_err(&ndev->dev, "can't add dc\n");
3345                         goto err_free;
3346                 }
3347
3348         }
3349
3350         base_res = request_mem_region(res->start, resource_size(res),
3351                 ndev->name);
3352         if (!base_res) {
3353                 dev_err(&ndev->dev, "request_mem_region failed\n");
3354                 ret = -EBUSY;
3355                 goto err_free;
3356         }
3357
3358         base = ioremap(res->start, resource_size(res));
3359         if (!base) {
3360                 dev_err(&ndev->dev, "registers can't be mapped\n");
3361                 ret = -EBUSY;
3362                 goto err_release_resource_reg;
3363         }
3364
3365         for (i = 0; i < DC_N_WINDOWS; i++)
3366                 dc->win_syncpt[i] = NVSYNCPT_INVALID;
3367
3368         if (TEGRA_DISPLAY_BASE == res->start) {
3369                 dc->vblank_syncpt = NVSYNCPT_VBLANK0;
3370                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp0_a");
3371                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp0_b");
3372                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp0_c");
3373                 dc->valid_windows = 0x07;
3374 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
3375                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3376                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp0_h");
3377                 dc->valid_windows |= 0x18;
3378 #elif !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
3379         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
3380         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
3381                 dc->win_syncpt[3] = nvhost_get_syncpt_client_managed("disp0_d");
3382                 dc->valid_windows |= 0x08;
3383 #endif
3384                 dc->powergate_id = TEGRA_POWERGATE_DISA;
3385 #ifdef CONFIG_TEGRA_ISOMGR
3386                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_0;
3387 #endif
3388         } else if (TEGRA_DISPLAY2_BASE == res->start) {
3389                 dc->vblank_syncpt = NVSYNCPT_VBLANK1;
3390                 dc->win_syncpt[0] = nvhost_get_syncpt_client_managed("disp1_a");
3391                 dc->win_syncpt[1] = nvhost_get_syncpt_client_managed("disp1_b");
3392                 dc->win_syncpt[2] = nvhost_get_syncpt_client_managed("disp1_c");
3393                 dc->valid_windows = 0x07;
3394 #ifdef CONFIG_ARCH_TEGRA_14x_SOC
3395                 dc->win_syncpt[4] = nvhost_get_syncpt_client_managed("disp1_h");
3396                 dc->valid_windows |= 0x10;
3397 #endif
3398                 dc->powergate_id = TEGRA_POWERGATE_DISB;
3399 #ifdef CONFIG_TEGRA_ISOMGR
3400                 isomgr_client_id = TEGRA_ISO_CLIENT_DISP_1;
3401 #endif
3402         } else {
3403                 dev_err(&ndev->dev,
3404                         "Unknown base address %llx: unable to assign syncpt\n",
3405                         (u64)res->start);
3406         }
3407
3408         if (np) {
3409                 struct resource of_fb_res;
3410                 if (dc->ctrl_num == 0)
3411                         tegra_get_fb_resource(&of_fb_res);
3412                 else /* dc->ctrl_num == 1*/
3413                         tegra_get_fb2_resource(&of_fb_res);
3414
3415                 fb_mem = kzalloc(sizeof(struct resource), GFP_KERNEL);
3416                 if (fb_mem == NULL) {
3417                         ret = -ENOMEM;
3418                         goto err_iounmap_reg;
3419                 }
3420                 fb_mem->name = "fbmem";
3421                 fb_mem->flags = IORESOURCE_MEM;
3422                 fb_mem->start = (resource_size_t)of_fb_res.start;
3423                 fb_mem->end = (resource_size_t)of_fb_res.end;
3424         } else {
3425                 fb_mem = platform_get_resource_byname(ndev,
3426                         IORESOURCE_MEM, "fbmem");
3427         }
3428
3429         clk = clk_get(&ndev->dev, NULL);
3430         if (IS_ERR_OR_NULL(clk)) {
3431                 dev_err(&ndev->dev, "can't get clock\n");
3432                 ret = -ENOENT;
3433                 goto err_iounmap_reg;
3434         }
3435
3436         dc->clk = clk;
3437         dc->shift_clk_div.mul = dc->shift_clk_div.div = 1;
3438         /* Initialize one shot work delay, it will be assigned by dsi
3439          * according to refresh rate later. */
3440         dc->one_shot_delay_ms = 40;
3441
3442         dc->base_res = base_res;
3443         dc->base = base;
3444         dc->irq = irq;
3445         dc->ndev = ndev;
3446         dc->fb_mem = fb_mem;
3447
3448         if (!np)
3449                 dc->pdata = ndev->dev.platform_data;
3450         else
3451                 dc->pdata = dt_pdata;
3452
3453         dc->bw_kbps = 0;
3454
3455         mutex_init(&dc->lock);
3456         mutex_init(&dc->one_shot_lock);
3457         mutex_init(&dc->lp_lock);
3458         init_completion(&dc->frame_end_complete);
3459         init_completion(&dc->crc_complete);
3460         init_waitqueue_head(&dc->wq);
3461         init_waitqueue_head(&dc->timestamp_wq);
3462 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
3463         INIT_WORK(&dc->reset_work, tegra_dc_reset_worker);
3464 #endif
3465         INIT_WORK(&dc->vblank_work, tegra_dc_vblank);
3466         dc->vblank_ref_count = 0;
3467 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && !defined(CONFIG_ARCH_TEGRA_3x_SOC)
3468         INIT_WORK(&dc->vpulse2_work, tegra_dc_vpulse2);
3469 #endif
3470         dc->vpulse2_ref_count = 0;
3471         INIT_DELAYED_WORK(&dc->underflow_work, tegra_dc_underflow_worker);
3472         INIT_DELAYED_WORK(&dc->one_shot_work, tegra_dc_one_shot_worker);
3473
3474         tegra_dc_init_lut_defaults(&dc->fb_lut);
3475
3476         dc->n_windows = DC_N_WINDOWS;
3477         for (i = 0; i < DC_N_WINDOWS; i++) {
3478                 struct tegra_dc_win *win = &dc->windows[i];
3479                 struct tegra_dc_win *tmp_win = &dc->tmp_wins[i];
3480                 if (!test_bit(i, &dc->valid_windows))
3481                         win->flags |= TEGRA_WIN_FLAG_INVALID;
3482                 win->idx = i;
3483                 win->dc = dc;
3484                 tmp_win->idx = i;
3485                 tmp_win->dc = dc;
3486                 tegra_dc_init_csc_defaults(&win->csc);
3487                 tegra_dc_init_lut_defaults(&win->lut);
3488         }
3489
3490         platform_set_drvdata(ndev, dc);
3491
3492 #ifdef CONFIG_SWITCH
3493         dc->modeset_switch.name = dev_name(&ndev->dev);
3494         dc->modeset_switch.state = 0;
3495         dc->modeset_switch.print_state = switch_modeset_print_mode;
3496         ret = switch_dev_register(&dc->modeset_switch);
3497         if (ret < 0)
3498                 dev_err(&ndev->dev, "failed to register switch driver\n");
3499 #endif
3500
3501         tegra_dc_feature_register(dc);
3502
3503         if (dc->pdata->default_out) {
3504 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3505                 if (dc->pdata->default_out->hotplug_init)
3506                         dc->pdata->default_out->hotplug_init(&dc->ndev->dev);
3507 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3508                 ret = tegra_dc_set_out(dc, dc->pdata->default_out);
3509                 if (ret < 0) {
3510                         dev_err(&dc->ndev->dev, "failed to initialize DC out ops\n");
3511                         goto err_put_clk;
3512                 }
3513         } else {
3514                 dev_err(&ndev->dev,
3515                         "No default output specified.  Leaving output disabled.\n");
3516         }
3517         dc->mode_dirty = false; /* ignore changes tegra_dc_set_out has done */
3518
3519 #ifdef CONFIG_FRAMEBUFFER_CONSOLE
3520         if (dc->out && dc->out->n_modes &&
3521             (dc->out->type == TEGRA_DC_OUT_HDMI)) {
3522                 struct fb_monspecs specs;
3523                 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
3524                 if (!tegra_edid_get_monspecs(hdmi->edid, &specs)) {
3525                         struct tegra_dc_mode *dcmode = &dc->out->modes[0];
3526                         dcmode->pclk          = specs.modedb->pixclock;
3527                         dcmode->pclk          = PICOS2KHZ(dcmode->pclk);
3528                         dcmode->pclk         *= 1000;
3529                         dcmode->h_ref_to_sync = 1;
3530                         dcmode->v_ref_to_sync = 1;
3531                         dcmode->h_sync_width  = specs.modedb->hsync_len;
3532                         dcmode->v_sync_width  = specs.modedb->vsync_len;
3533                         dcmode->h_back_porch  = specs.modedb->left_margin;
3534                         dcmode->v_back_porch  = specs.modedb->upper_margin;
3535                         dcmode->h_active      = specs.modedb->xres;
3536                         dcmode->v_active      = specs.modedb->yres;
3537                         dcmode->h_front_porch = specs.modedb->right_margin;
3538                         dcmode->v_front_porch = specs.modedb->lower_margin;
3539                         tegra_dc_set_mode(dc, dcmode);
3540                         dc->pdata->fb->xres = dcmode->h_active;
3541                         dc->pdata->fb->yres = dcmode->v_active;
3542                 }
3543         }
3544 #endif /* CONFIG_FRAMEBUFFER_CONSOLE */
3545
3546 #ifndef CONFIG_TEGRA_ISOMGR
3547                 /*
3548                  * The emc is a shared clock, it will be set based on
3549                  * the requirements for each user on the bus.
3550                  */
3551                 emc_clk = clk_get(&ndev->dev, "emc");
3552                 if (IS_ERR_OR_NULL(emc_clk)) {
3553                         dev_err(&ndev->dev, "can't get emc clock\n");
3554                         ret = -ENOENT;
3555                         goto err_put_clk;
3556                 }
3557                 dc->emc_clk = emc_clk;
3558 #endif
3559
3560         dc->ext = tegra_dc_ext_register(ndev, dc);
3561         if (IS_ERR_OR_NULL(dc->ext)) {
3562                 dev_warn(&ndev->dev, "Failed to enable Tegra DC extensions.\n");
3563                 dc->ext = NULL;
3564         }
3565
3566         /* interrupt handler must be registered before tegra_fb_register() */
3567         if (request_threaded_irq(irq, NULL, tegra_dc_irq, IRQF_ONESHOT,
3568                         dev_name(&ndev->dev), dc)) {
3569                 dev_err(&ndev->dev, "request_irq %d failed\n", irq);
3570                 ret = -EBUSY;
3571                 goto err_disable_dc;
3572         }
3573         disable_dc_irq(dc);
3574
3575         tegra_pd_add_device(&ndev->dev);
3576         pm_runtime_use_autosuspend(&ndev->dev);
3577         pm_runtime_set_autosuspend_delay(&ndev->dev, 100);
3578         pm_runtime_enable(&ndev->dev);
3579
3580 #ifdef CONFIG_TEGRA_DC_CMU
3581         /* if bootloader leaves this head enabled, then skip CMU programming. */
3582         dc->cmu_dirty = (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) == 0;
3583         dc->cmu_enabled = dc->pdata->cmu_enable;
3584 #endif
3585
3586         if (dc->pdata->flags & TEGRA_DC_FLAG_ENABLED) {
3587                 /* WAR: BL is putting DC in bad state for EDP configuration */
3588                 if (dc->out->type == TEGRA_DC_OUT_DP ||
3589                         dc->out->type == TEGRA_DC_OUT_NVSR_DP) {
3590                         clk_prepare_enable(dc->clk);
3591                         tegra_periph_reset_assert(dc->clk);
3592                         udelay(10);
3593                         tegra_periph_reset_deassert(dc->clk);
3594                         udelay(10);
3595                         clk_disable_unprepare(dc->clk);
3596                 }
3597                 _tegra_dc_set_default_videomode(dc);
3598                 dc->enabled = _tegra_dc_enable(dc);
3599
3600 #if !defined(CONFIG_ARCH_TEGRA_11x_SOC) && !defined(CONFIG_ARCH_TEGRA_14x_SOC)
3601                 /* BL or PG init will keep DISA unpowergated after booting.
3602                  * Adding an extra powergate to balance the refcount
3603                  * since _tegra_dc_enable() increases the refcount.
3604                  */
3605                 if (!tegra_platform_is_fpga())
3606                         if (dc->powergate_id == TEGRA_POWERGATE_DISA)
3607                                 tegra_dc_powergate_locked(dc);
3608 #endif
3609         }
3610
3611 #ifdef CONFIG_TEGRA_ISOMGR
3612         if (isomgr_client_id == -1) {
3613                 dc->isomgr_handle = NULL;
3614         } else {
3615                 dc->isomgr_handle = tegra_isomgr_register(isomgr_client_id,
3616                         tegra_dc_calc_min_bandwidth(dc),
3617                         tegra_dc_bandwidth_renegotiate, dc);
3618                 if (IS_ERR(dc->isomgr_handle)) {
3619                         dev_err(&dc->ndev->dev,
3620                                 "could not register isomgr. err=%ld\n",
3621                                 PTR_ERR(dc->isomgr_handle));
3622                         ret = -ENOENT;
3623                         goto err_put_clk;
3624                 }
3625                 dc->reserved_bw = tegra_dc_calc_min_bandwidth(dc);
3626                 /*
3627                  * Use maximum value so we can try to reserve as much as
3628                  * needed until we are told by isomgr to backoff.
3629                  */
3630                 dc->available_bw = UINT_MAX;
3631         }
3632 #endif
3633
3634         tegra_dc_create_debugfs(dc);
3635
3636         dev_info(&ndev->dev, "probed\n");
3637
3638         if (dc->pdata->fb) {
3639                 if (dc->enabled && dc->pdata->fb->bits_per_pixel == -1) {
3640                         unsigned long fmt;
3641                         tegra_dc_writel(dc,
3642                                         WINDOW_A_SELECT << dc->pdata->fb->win,
3643                                         DC_CMD_DISPLAY_WINDOW_HEADER);
3644
3645                         fmt = tegra_dc_readl(dc, DC_WIN_COLOR_DEPTH);
3646                         dc->pdata->fb->bits_per_pixel =
3647                                 tegra_dc_fmt_bpp(fmt);
3648                 }
3649
3650                 mode = tegra_dc_get_override_mode(dc);
3651                 if (mode) {
3652                         dc->pdata->fb->xres = mode->h_active;
3653                         dc->pdata->fb->yres = mode->v_active;
3654                 }
3655
3656 #ifdef CONFIG_ADF_TEGRA
3657                 tegra_dc_io_start(dc);
3658                 dc->adf = tegra_adf_init(ndev, dc, dc->pdata->fb);
3659                 tegra_dc_io_end(dc);
3660
3661                 if (IS_ERR(dc->adf)) {
3662                         tegra_dc_io_start(dc);
3663                         dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb,
3664                                         fb_mem);
3665                         tegra_dc_io_end(dc);
3666                         if (IS_ERR_OR_NULL(dc->fb)) {
3667                                 dc->fb = NULL;
3668                                 dev_err(&ndev->dev, "failed to register fb\n");
3669                                 goto err_remove_debugfs;
3670                         }
3671                 }
3672 #else
3673                 tegra_dc_io_start(dc);
3674                 dc->fb = tegra_fb_register(ndev, dc, dc->pdata->fb, fb_mem);
3675                 tegra_dc_io_end(dc);
3676                 if (IS_ERR_OR_NULL(dc->fb)) {
3677                         dc->fb = NULL;
3678                         dev_err(&ndev->dev, "failed to register fb\n");
3679                         goto err_remove_debugfs;
3680                 }
3681 #endif
3682         }
3683
3684 #ifndef CONFIG_FRAMEBUFFER_CONSOLE
3685         if (dc->out && dc->out->hotplug_init)
3686                 dc->out->hotplug_init(&ndev->dev);
3687 #endif /* !CONFIG_FRAMEBUFFER_CONSOLE */
3688
3689         if (dc->out_ops) {
3690                 if (dc->out_ops->detect)
3691                         dc->connected = dc->out_ops->detect(dc);
3692                 else
3693                         dc->connected = true;
3694         }
3695         else
3696                 dc->connected = false;
3697
3698         /* Powergate display module when it's unconnected. */
3699         /* detect() function, if presetns, responsible for the powergate */
3700         if (!tegra_dc_get_connected(dc) &&
3701                         !(dc->out_ops && dc->out_ops->detect))
3702                 tegra_dc_powergate_locked(dc);
3703
3704         tegra_dc_create_sysfs(&dc->ndev->dev);
3705
3706         /*
3707          * Overriding the display mode only applies for modes set up during
3708          * boot. It should not apply for e.g. HDMI hotplug.
3709          */
3710         dc->initialized = false;
3711
3712         return 0;
3713
3714 err_remove_debugfs:
3715         tegra_dc_remove_debugfs(dc);
3716         free_irq(irq, dc);
3717 err_disable_dc:
3718         if (dc->ext) {
3719                 tegra_dc_ext_disable(dc->ext);
3720                 tegra_dc_ext_unregister(dc->ext);
3721         }
3722         mutex_lock(&dc->lock);
3723         if (dc->enabled)
3724                 _tegra_dc_disable(dc);
3725         dc->enabled = false;
3726         mutex_unlock(&dc->lock);
3727 #ifdef CONFIG_SWITCH
3728         switch_dev_unregister(&dc->modeset_switch);
3729 #endif
3730 #ifdef CONFIG_TEGRA_ISOMGR
3731         tegra_isomgr_unregister(dc->isomgr_handle);
3732 #else
3733         clk_put(emc_clk);
3734 #endif
3735 err_put_clk:
3736         clk_put(clk);
3737 err_iounmap_reg:
3738         iounmap(base);
3739         if (fb_mem) {
3740                 if (!np)
3741                         release_resource(fb_mem);
3742                 else
3743                         kfree(fb_mem);
3744         }
3745 err_release_resource_reg:
3746         release_resource(base_res);
3747 err_free:
3748         kfree(dc);
3749
3750         return ret;
3751 }
3752
3753 static int tegra_dc_remove(struct platform_device *ndev)
3754 {
3755         struct tegra_dc *dc = platform_get_drvdata(ndev);
3756         struct device_node *np = ndev->dev.of_node;
3757
3758         tegra_dc_remove_sysfs(&dc->ndev->dev);
3759         tegra_dc_remove_debugfs(dc);
3760
3761         if (dc->fb) {
3762                 tegra_fb_unregister(dc->fb);
3763                 if (dc->fb_mem) {
3764                         if (!np)
3765                                 release_resource(dc->fb_mem);
3766                         else
3767                                 kfree(dc->fb_mem);
3768                 }
3769         }
3770
3771 #ifdef CONFIG_ADF_TEGRA
3772         if (dc->adf)
3773                 tegra_adf_unregister(dc->adf);
3774 #endif
3775
3776         tegra_dc_ext_disable(dc->ext);
3777
3778         if (dc->ext)
3779                 tegra_dc_ext_unregister(dc->ext);
3780
3781         mutex_lock(&dc->lock);
3782         if (dc->enabled)
3783                 _tegra_dc_disable(dc);
3784         dc->enabled = false;
3785         mutex_unlock(&dc->lock);
3786         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3787
3788 #ifdef CONFIG_SWITCH
3789         switch_dev_unregister(&dc->modeset_switch);
3790 #endif
3791         free_irq(dc->irq, dc);
3792 #ifdef CONFIG_TEGRA_ISOMGR
3793         if (dc->isomgr_handle) {
3794                 tegra_isomgr_unregister(dc->isomgr_handle);
3795                 dc->isomgr_handle = NULL;
3796         }
3797 #else
3798         clk_put(dc->emc_clk);
3799 #endif
3800         clk_put(dc->clk);
3801         iounmap(dc->base);
3802         if (dc->fb_mem)
3803                 release_resource(dc->base_res);
3804         kfree(dc);
3805         tegra_dc_set(NULL, ndev->id);
3806
3807         return 0;
3808 }
3809
3810 #ifdef CONFIG_PM
3811 static int tegra_dc_suspend(struct platform_device *ndev, pm_message_t state)
3812 {
3813         struct tegra_dc *dc = platform_get_drvdata(ndev);
3814         int ret = 0;
3815
3816         trace_display_suspend(dc);
3817         dev_info(&ndev->dev, "suspend\n");
3818
3819         tegra_dc_ext_disable(dc->ext);
3820
3821         tegra_dc_cursor_suspend(dc);
3822         mutex_lock(&dc->lock);
3823         ret = tegra_dc_io_start(dc);
3824
3825         if (dc->out_ops && dc->out_ops->suspend)
3826                 dc->out_ops->suspend(dc);
3827
3828         if (dc->enabled) {
3829                 _tegra_dc_disable(dc);
3830
3831                 dc->suspended = true;
3832         }
3833
3834         if (dc->out && dc->out->postsuspend) {
3835                 dc->out->postsuspend();
3836                 /* avoid resume event due to voltage falling on interfaces that
3837                  * support hotplug wake. And only do this if a panel is
3838                  * connected, if we are already disconnected, then no phantom
3839                  * hotplug can occur by disabling the voltage.
3840                  */
3841                 if ((dc->out->flags & TEGRA_DC_OUT_HOTPLUG_WAKE_LP0)
3842                         && tegra_dc_get_connected(dc))
3843                         msleep(100);
3844         }
3845
3846         if (!ret)
3847                 tegra_dc_io_end(dc);
3848
3849         mutex_unlock(&dc->lock);
3850         synchronize_irq(dc->irq); /* wait for IRQ handlers to finish */
3851
3852         return 0;
3853 }
3854
3855 static int tegra_dc_resume(struct platform_device *ndev)
3856 {
3857         struct tegra_dc *dc = platform_get_drvdata(ndev);
3858
3859         trace_display_resume(dc);
3860         dev_info(&ndev->dev, "resume\n");
3861
3862         mutex_lock(&dc->lock);
3863         dc->suspended = false;
3864
3865         /* To pan the fb on resume */
3866         tegra_fb_pan_display_reset(dc->fb);
3867
3868         if (dc->enabled) {
3869                 dc->enabled = false;
3870                 _tegra_dc_set_default_videomode(dc);
3871                 dc->enabled = _tegra_dc_enable(dc);
3872         }
3873
3874         if (dc->out && dc->out->hotplug_init)
3875                 dc->out->hotplug_init(&ndev->dev);
3876
3877         if (dc->out_ops && dc->out_ops->resume)
3878                 dc->out_ops->resume(dc);
3879
3880         mutex_unlock(&dc->lock);
3881         tegra_dc_cursor_resume(dc);
3882
3883         return 0;
3884 }
3885
3886 #endif /* CONFIG_PM */
3887
3888 static void tegra_dc_shutdown(struct platform_device *ndev)
3889 {
3890         struct tegra_dc *dc = platform_get_drvdata(ndev);
3891
3892         if (WARN_ON(!dc || !dc->out || !dc->out_ops))
3893                 return;
3894
3895         if (!dc->enabled)
3896                 return;
3897
3898         tegra_dc_disable(dc);
3899 }
3900
3901 extern int suspend_set(const char *val, struct kernel_param *kp)
3902 {
3903         if (!strcmp(val, "dump"))
3904                 dump_regs(tegra_dcs[0]);
3905 #ifdef CONFIG_PM
3906         else if (!strcmp(val, "suspend"))
3907                 tegra_dc_suspend(tegra_dcs[0]->ndev, PMSG_SUSPEND);
3908         else if (!strcmp(val, "resume"))
3909                 tegra_dc_resume(tegra_dcs[0]->ndev);
3910 #endif
3911
3912         return 0;
3913 }
3914
3915 extern int suspend_get(char *buffer, struct kernel_param *kp)
3916 {
3917         return 0;
3918 }
3919
3920 int suspend;
3921
3922 module_param_call(suspend, suspend_set, suspend_get, &suspend, 0644);
3923
3924
3925 #ifdef CONFIG_OF
3926 static struct of_device_id tegra_display_of_match[] = {
3927         {.compatible = "nvidia,tegra114-dc", },
3928         {.compatible = "nvidia,tegra124-dc", },
3929         { },
3930 };
3931 #endif
3932
3933 struct platform_driver tegra_dc_driver = {
3934         .driver = {
3935                 .name = "tegradc",
3936                 .owner = THIS_MODULE,
3937 #ifdef CONFIG_OF
3938                 .of_match_table =
3939                         of_match_ptr(tegra_display_of_match),
3940 #endif
3941         },
3942         .probe = tegra_dc_probe,
3943         .remove = tegra_dc_remove,
3944 #ifdef CONFIG_PM
3945         .suspend = tegra_dc_suspend,
3946         .resume = tegra_dc_resume,
3947 #endif
3948         .shutdown = tegra_dc_shutdown,
3949 };
3950
3951 #ifndef MODULE
3952 static int __init parse_disp_params(char *options, struct tegra_dc_mode *mode)
3953 {
3954         int i, params[11];
3955         char *p;
3956
3957         for (i = 0; i < ARRAY_SIZE(params); i++) {
3958                 if ((p = strsep(&options, ",")) != NULL) {
3959                         if (*p)
3960                                 params[i] = simple_strtoul(p, &p, 10);
3961                 } else
3962                         return -EINVAL;
3963         }
3964
3965         if ((mode->pclk = params[0]) == 0)
3966                 return -EINVAL;
3967
3968         mode->h_active      = params[1];
3969         mode->v_active      = params[2];
3970         mode->h_ref_to_sync = params[3];
3971         mode->v_ref_to_sync = params[4];
3972         mode->h_sync_width  = params[5];
3973         mode->v_sync_width  = params[6];
3974         mode->h_back_porch  = params[7];
3975         mode->v_back_porch  = params[8];
3976         mode->h_front_porch = params[9];
3977         mode->v_front_porch = params[10];
3978
3979         return 0;
3980 }
3981
3982 static int __init tegra_dc_mode_override(char *str)
3983 {
3984         char *p = str, *options;
3985
3986         if (!p || !*p)
3987                 return -EINVAL;
3988
3989         p = strstr(str, "hdmi:");
3990         if (p) {
3991                 p += 5;
3992                 options = strsep(&p, ";");
3993                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_HDMI]))
3994                         return -EINVAL;
3995         }
3996
3997         p = strstr(str, "rgb:");
3998         if (p) {
3999                 p += 4;
4000                 options = strsep(&p, ";");
4001                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_RGB]))
4002                         return -EINVAL;
4003         }
4004
4005         p = strstr(str, "dsi:");
4006         if (p) {
4007                 p += 4;
4008                 options = strsep(&p, ";");
4009                 if (parse_disp_params(options, &override_disp_mode[TEGRA_DC_OUT_DSI]))
4010                         return -EINVAL;
4011         }
4012
4013         p = strstr(str, "null:");
4014         if (p) {
4015                 p += 5;
4016                 options = strsep(&p, ";");
4017                 if (parse_disp_params(options,
4018                                 &override_disp_mode[TEGRA_DC_OUT_NULL]))
4019                         return -EINVAL;
4020         }
4021
4022         return 0;
4023 }
4024
4025 __setup("disp_params=", tegra_dc_mode_override);
4026 #endif
4027
4028 static int __init tegra_dc_module_init(void)
4029 {
4030         int ret = tegra_dc_ext_module_init();
4031         if (ret)
4032                 return ret;
4033         return platform_driver_register(&tegra_dc_driver);
4034 }
4035
4036 static void __exit tegra_dc_module_exit(void)
4037 {
4038         platform_driver_unregister(&tegra_dc_driver);
4039         tegra_dc_ext_module_exit();
4040 }
4041
4042 module_exit(tegra_dc_module_exit);
4043 module_init(tegra_dc_module_init);