32a20034dab5855662b23ee34e071603252e37cb
[linux-3.10.git] / drivers / video / tegra / dc / bandwidth.c
1 /*
2  * drivers/video/tegra/dc/bandwidth.c
3  *
4  * Copyright (c) 2010-2014, NVIDIA CORPORATION, All rights reserved.
5  *
6  * Author: Jon Mayo <jmayo@nvidia.com>
7  *
8  * This software is licensed under the terms of the GNU General Public
9  * License version 2, as published by the Free Software Foundation, and
10  * may be copied, distributed, and modified under those terms.
11  *
12  * This program is distributed in the hope that it will be useful,
13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15  * GNU General Public License for more details.
16  *
17  */
18
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/clk.h>
22 #include <linux/clk/tegra.h>
23 #include <linux/math64.h>
24
25 #include <mach/dc.h>
26 #include <mach/fb.h>
27 #include <mach/mc.h>
28 #include <linux/nvhost.h>
29 #include <mach/latency_allowance.h>
30 #include <mach/tegra_emc.h>
31 #include <trace/events/display.h>
32
33 #include "dc_reg.h"
34 #include "dc_config.h"
35 #include "dc_priv.h"
36 #ifdef CONFIG_ADF_TEGRA
37 #include "tegra_adf.h"
38 #endif
39
40 static int use_dynamic_emc = 1;
41
42 module_param_named(use_dynamic_emc, use_dynamic_emc, int, S_IRUGO | S_IWUSR);
43
44 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
45         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
46         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
47         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
48 static unsigned int tegra_dcs_total_bw[TEGRA_MAX_DC] = {0};
49 DEFINE_MUTEX(tegra_dcs_total_bw_lock);
50 #endif
51
52 /* windows A, B, C for first and second display */
53 static const enum tegra_la_id la_id_tab[2][DC_N_WINDOWS] = {
54         /* first display */
55         {
56                 TEGRA_LA_DISPLAY_0A,
57                 TEGRA_LA_DISPLAY_0B,
58                 TEGRA_LA_DISPLAY_0C,
59 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
60         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
61         !defined(CONFIG_ARCH_TEGRA_11x_SOC)
62                 TEGRA_LA_DISPLAYD,
63 #endif
64 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
65                 TEGRA_LA_DISPLAY_HC,
66 #endif
67 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
68         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
69         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
70         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
71                 TEGRA_LA_DISPLAY_T,
72 #endif
73         },
74         /* second display */
75         {
76                 TEGRA_LA_DISPLAY_0AB,
77                 TEGRA_LA_DISPLAY_0BB,
78                 TEGRA_LA_DISPLAY_0CB,
79 #if defined(CONFIG_ARCH_TEGRA_14x_SOC)
80                 0,
81                 TEGRA_LA_DISPLAY_HCB,
82 #endif
83         },
84 };
85
86 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
87         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
88         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
89         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
90 static bool is_internal_win(enum tegra_la_id id)
91 {
92         return ((id == TEGRA_LA_DISPLAY_0A) || (id == TEGRA_LA_DISPLAY_0B) ||
93                 (id == TEGRA_LA_DISPLAY_0C) || (id == TEGRA_LA_DISPLAYD) ||
94                 (id == TEGRA_LA_DISPLAY_HC) || (id == TEGRA_LA_DISPLAY_T));
95 }
96
97 static unsigned int num_active_internal_wins(struct tegra_dc *dc)
98 {
99         unsigned int num_active_internal_wins = 0;
100         int i = 0;
101
102         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
103                 struct tegra_dc_win *curr_win = &dc->windows[i];
104                 enum tegra_la_id curr_win_la_id =
105                                 la_id_tab[dc->ctrl_num][curr_win->idx];
106
107                 if (!is_internal_win(curr_win_la_id))
108                         continue;
109
110                 if (WIN_IS_ENABLED(curr_win))
111                         num_active_internal_wins++;
112         }
113
114         return num_active_internal_wins;
115 }
116
117 static unsigned int num_active_external_wins(struct tegra_dc *dc)
118 {
119         unsigned int num_active_external_wins = 0;
120         int i = 0;
121
122         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
123                 struct tegra_dc_win *curr_win = &dc->windows[i];
124                 enum tegra_la_id curr_win_la_id =
125                                 la_id_tab[dc->ctrl_num][curr_win->idx];
126
127                 if (is_internal_win(curr_win_la_id))
128                         continue;
129
130                 if (WIN_IS_ENABLED(curr_win))
131                         num_active_external_wins++;
132         }
133
134         return num_active_external_wins;
135 }
136
137 /*
138  * Note about fixed point arithmetic:
139  * ----------------------------------
140  * calc_disp_params(...) contains fixed point values and arithmetic due to the
141  * need to use floating point values. All fixed point values have the "_fp" or
142  * "_FP" suffix in their name. Functions/values used to convert between real and
143  * fixed point values are listed below:
144  *    - la_params.fp_factor
145  *    - la_params.la_real_to_fp(real_val)
146  *    - la_params.la_fp_to_real(fp_val)
147  */
148
149 #define T12X_LA_BW_DISRUPTION_TIME_EMCCLKS_FP                   1342000
150 #define T12X_LA_STATIC_LA_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP        54000
151 #define T12X_LA_CONS_MEM_EFFICIENCY_FP                          500
152 #define T12X_LA_ROW_SRT_SZ_BYTES        (64 * (T12X_LA_MC_EMEM_NUM_SLOTS + 1))
153 #define T12X_LA_MC_EMEM_NUM_SLOTS                               63
154 #define T12X_LA_MAX_DRAIN_TIME_USEC                             10
155
156 /*
157  * Function outputs:
158  *    - disp_params->thresh_lwm_bytes
159  *    - disp_params->spool_up_buffering_adj_bytes
160  *    - disp_params->total_dc0_bw
161  *    - disp_params->total_dc1_bw
162  */
163 static void calc_disp_params(struct tegra_dc *dc,
164                                 struct tegra_dc_win *w,
165                                 enum tegra_la_id la_id,
166                                 unsigned long emc_freq_hz,
167                                 unsigned int bw_mbps,
168                                 struct dc_to_la_params *disp_params) {
169         const struct disp_client *disp_clients_info =
170                                                 tegra_la_disp_clients_info;
171         struct la_to_dc_params la_params = tegra_get_la_to_dc_params();
172         unsigned int bw_mbps_fp = la_params.la_real_to_fp(bw_mbps);
173         bool active = WIN_IS_ENABLED(w);
174         bool win_rotated = false;
175         unsigned int surface_width = 0;
176         bool vertical_scaling_enabled = false;
177         bool pitch = !WIN_IS_BLOCKLINEAR(w) && !WIN_IS_TILED(w);
178         bool planar = tegra_dc_is_yuv_planar(w->fmt);
179         bool packed_yuv422 =
180                         ((tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCbCr422) ||
181                         (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YUV422));
182         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
183          * but the size reported by tegra_dc_fmt_bpp for the planar version
184          * is of the luma plane's size only. */
185         unsigned int bytes_per_pixel = tegra_dc_is_yuv_planar(w->fmt) ?
186                                 2 * tegra_dc_fmt_bpp(w->fmt) / 8 :
187                                 tegra_dc_fmt_bpp(w->fmt) / 8;
188         struct tegra_dc_mode mode = dc->mode;
189         unsigned int total_h = mode.h_active +
190                                 mode.h_front_porch +
191                                 mode.h_back_porch +
192                                 mode.h_sync_width;
193         unsigned int total_v = mode.v_active +
194                                 mode.v_front_porch +
195                                 mode.v_back_porch +
196                                 mode.v_sync_width;
197         unsigned int total_screen_area = total_h * total_v;
198         unsigned int total_active_area = mode.h_active * mode.v_active;
199         unsigned int total_blank_area = total_screen_area - total_active_area;
200         unsigned int c1_fp = 0;
201         unsigned int c2 = 0;
202         unsigned int c3 = 0;
203         unsigned int bpp_for_line_buffer_storage_fp = 0;
204         unsigned int reqd_buffering_thresh_disp_bytes_fp = 0;
205         unsigned int latency_buffering_available_in_reqd_buffering_fp = 0;
206         unsigned long emc_freq_khz = emc_freq_hz / 1000;
207         unsigned long emc_freq_mhz = emc_freq_khz / 1000;
208         unsigned int bw_disruption_time_usec_fp =
209                                         T12X_LA_BW_DISRUPTION_TIME_EMCCLKS_FP /
210                                         emc_freq_mhz;
211         unsigned int effective_row_srt_sz_bytes_fp =
212                 min((unsigned long)la_params.la_real_to_fp(min(
213                                         (unsigned long)T12X_LA_ROW_SRT_SZ_BYTES,
214                                         16 * min(emc_freq_mhz + 50,
215                                                 400ul))),
216                         (T12X_LA_MAX_DRAIN_TIME_USEC *
217                         emc_freq_mhz -
218                         la_params.la_fp_to_real(
219                         T12X_LA_STATIC_LA_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP)) *
220                         2 *
221                         la_params.dram_width_bits /
222                         8 *
223                         T12X_LA_CONS_MEM_EFFICIENCY_FP);
224         unsigned int drain_time_usec_fp =
225                         effective_row_srt_sz_bytes_fp *
226                         la_params.fp_factor /
227                         (emc_freq_mhz *
228                                 la_params.dram_width_bits /
229                                 4 *
230                                 T12X_LA_CONS_MEM_EFFICIENCY_FP) +
231                         T12X_LA_STATIC_LA_SNAP_ARB_TO_ROW_SRT_EMCCLKS_FP /
232                         emc_freq_mhz;
233         unsigned int total_latency_usec_fp =
234                 drain_time_usec_fp +
235                 la_params.static_la_minus_snap_arb_to_row_srt_emcclks_fp /
236                 emc_freq_mhz;
237         unsigned int bw_disruption_buffering_bytes_fp =
238                                         bw_mbps *
239                                         max(bw_disruption_time_usec_fp,
240                                                 total_latency_usec_fp) +
241                                         la_params.la_real_to_fp(1)/2;
242         unsigned int reqd_lines = 0;
243         unsigned int lines_of_latency = 0;
244         unsigned int thresh_lwm_bytes = 0;
245         unsigned int total_buf_sz_bytes =
246         disp_clients_info[DISP_CLIENT_LA_ID(la_id)].line_buf_sz_bytes +
247         disp_clients_info[DISP_CLIENT_LA_ID(la_id)].mccif_size_bytes;
248         unsigned int num_active_wins_to_use = is_internal_win(la_id) ?
249                                                 num_active_internal_wins(dc) :
250                                                 num_active_external_wins(dc);
251         unsigned int total_active_space_bw = 0;
252         unsigned int total_vblank_bw = 0;
253         unsigned int bw_other_wins = 0;
254         unsigned int bw_display_fp = 0;
255         unsigned int bw_delta_fp = 0;
256         unsigned int fill_rate_other_wins_fp = 0;
257         unsigned int dvfs_time_nsec =
258                         tegra_get_dvfs_clk_change_latency_nsec(emc_freq_khz);
259         unsigned int data_shortfall_other_wins_fp = 0;
260         unsigned int duration_usec_fp = 0;
261         unsigned int spool_up_buffering_adj_bytes = 0;
262         unsigned int curr_dc_head_bw = 0;
263
264         disp_params->drain_time_usec_fp = drain_time_usec_fp;
265
266         if (w->flags & TEGRA_WIN_FLAG_SCAN_COLUMN) {
267                 win_rotated = true;
268                 surface_width = dfixed_trunc(w->h);
269                 vertical_scaling_enabled = (dfixed_trunc(w->w) == w->out_w) ?
270                                         false : true;
271         } else {
272                 win_rotated = false;
273                 surface_width = dfixed_trunc(w->w);
274                 vertical_scaling_enabled = (dfixed_trunc(w->h) == w->out_h) ?
275                                         false : true;
276         }
277
278         if ((disp_clients_info[DISP_CLIENT_LA_ID(la_id)].line_buf_sz_bytes
279                                                                         == 0) ||
280                 (pitch == true)) {
281                 reqd_lines = 0;
282         } else if (win_rotated && planar) {
283                 if (vertical_scaling_enabled)
284                         reqd_lines = 17;
285                 else
286                         reqd_lines = 16;
287         } else {
288                 if (win_rotated) {
289                         if (vertical_scaling_enabled)
290                                 reqd_lines = 16 / bytes_per_pixel + 1;
291                         else
292                                 reqd_lines = 16 / bytes_per_pixel;
293                 } else {
294                         if (vertical_scaling_enabled)
295                                 reqd_lines = 3;
296                         else
297                                 reqd_lines = 1;
298                 }
299         }
300
301         if (reqd_lines > 0 && !vertical_scaling_enabled && win_rotated)
302                 lines_of_latency = 1;
303         else
304                 lines_of_latency = 0;
305
306
307         if (((tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCbCr422R) ||
308                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YUV422R) ||
309                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCbCr422RA) ||
310                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YUV422RA)) &&
311                 !win_rotated) {
312                 c1_fp = la_params.la_real_to_fp(5) / 2;
313         } else {
314                 c1_fp = la_params.la_real_to_fp(1);
315         }
316
317         if ((((tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCbCr420P) ||
318                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YUV420P) ||
319                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCrCb420SP) ||
320                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YCbCr420SP) ||
321                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YVU420SP) ||
322                 (tegra_dc_fmt(w->fmt) == TEGRA_WIN_FMT_YUV420SP)) &&
323                 !win_rotated) ||
324                 (tegra_dc_is_yuv(w->fmt) && win_rotated)) {
325                 c2 = 3;
326         } else {
327                 c2 = bytes_per_pixel;
328         }
329
330         c3 = (packed_yuv422 && win_rotated) ? 2 : 1;
331         latency_buffering_available_in_reqd_buffering_fp = active *
332                                                         surface_width *
333                                                         lines_of_latency *
334                                                         c1_fp *
335                                                         c2 *
336                                                         c3;
337
338         switch (tegra_dc_fmt(w->fmt)) {
339         /* YUV 420 case*/
340         case TEGRA_WIN_FMT_YCbCr420P:
341         case TEGRA_WIN_FMT_YUV420P:
342         case TEGRA_WIN_FMT_YCrCb420SP:
343         case TEGRA_WIN_FMT_YCbCr420SP:
344         case TEGRA_WIN_FMT_YVU420SP:
345         case TEGRA_WIN_FMT_YUV420SP:
346                 c1_fp = (win_rotated) ?
347                         la_params.la_real_to_fp(2) :
348                         la_params.la_real_to_fp(3);
349                 break;
350
351         /* YUV 422 case */
352         case TEGRA_WIN_FMT_YCbCr422:
353         case TEGRA_WIN_FMT_YUV422:
354         case TEGRA_WIN_FMT_YCbCr422P:
355         case TEGRA_WIN_FMT_YUV422P:
356         case TEGRA_WIN_FMT_YCrCb422SP:
357         case TEGRA_WIN_FMT_YCbCr422SP:
358         case TEGRA_WIN_FMT_YVU422SP:
359         case TEGRA_WIN_FMT_YUV422SP:
360                 c1_fp = (win_rotated) ?
361                         la_params.la_real_to_fp(3) :
362                         la_params.la_real_to_fp(2);
363                 break;
364
365         /* YUV 422R case */
366         case TEGRA_WIN_FMT_YCbCr422R:
367         case TEGRA_WIN_FMT_YUV422R:
368         case TEGRA_WIN_FMT_YCbCr422RA:
369         case TEGRA_WIN_FMT_YUV422RA:
370                 c1_fp = (win_rotated) ?
371                         la_params.la_real_to_fp(2) :
372                         la_params.la_real_to_fp(5);
373                 break;
374
375         /* YUV 444 case */
376         case TEGRA_WIN_FMT_YCbCr444P:
377         case TEGRA_WIN_FMT_YUV444P:
378         case TEGRA_WIN_FMT_YVU444SP:
379         case TEGRA_WIN_FMT_YUV444SP:
380                 c1_fp = la_params.la_real_to_fp(3);
381                 break;
382
383         default:
384                 c1_fp = la_params.la_real_to_fp(bytes_per_pixel);
385                 break;
386         }
387
388         c2 = (packed_yuv422 && win_rotated) ? 2 : 1;
389         bpp_for_line_buffer_storage_fp = c1_fp * c2;
390         reqd_buffering_thresh_disp_bytes_fp = active *
391                                                 surface_width *
392                                                 reqd_lines *
393                                                 bpp_for_line_buffer_storage_fp;
394         thresh_lwm_bytes =
395                 la_params.la_fp_to_real(reqd_buffering_thresh_disp_bytes_fp);
396         thresh_lwm_bytes +=
397                 la_params.la_fp_to_real(
398                         (bw_disruption_buffering_bytes_fp >=
399                         latency_buffering_available_in_reqd_buffering_fp) ?
400                         (bw_disruption_buffering_bytes_fp -
401                         latency_buffering_available_in_reqd_buffering_fp) : 0);
402         disp_params->thresh_lwm_bytes = thresh_lwm_bytes;
403
404
405         if (is_internal_win(la_id)) {
406                 int i = 0;
407
408                 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
409                         struct tegra_dc_win *curr_win = &dc->windows[i];
410                         enum tegra_la_id curr_win_la_id =
411                                         la_id_tab[dc->ctrl_num][curr_win->idx];
412                         unsigned int curr_win_bw = 0;
413
414                         if (!is_internal_win(curr_win_la_id))
415                                 continue;
416
417                         curr_win_bw = max(curr_win->bandwidth,
418                                                 curr_win->new_bandwidth);
419                         /* our bandwidth is in kbytes/sec, but LA takes MBps.
420                          * round up bandwidth to next 1MBps */
421                         if (curr_win_bw != UINT_MAX)
422                                 curr_win_bw = curr_win_bw / 1000 + 1;
423
424                         total_active_space_bw += curr_win_bw;
425                 }
426         } else {
427                 int i = 0;
428
429                 for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
430                         struct tegra_dc_win *curr_win = &dc->windows[i];
431                         enum tegra_la_id curr_win_la_id =
432                                         la_id_tab[dc->ctrl_num][curr_win->idx];
433                         unsigned int curr_win_bw = 0;
434
435                         if (is_internal_win(curr_win_la_id))
436                                 continue;
437
438                         curr_win_bw = max(curr_win->bandwidth,
439                                                 curr_win->new_bandwidth);
440                         /* our bandwidth is in kbytes/sec, but LA takes MBps.
441                          * round up bandwidth to next 1MBps */
442                         if (curr_win_bw != UINT_MAX)
443                                 curr_win_bw = curr_win_bw / 1000 + 1;
444
445                         total_active_space_bw += curr_win_bw;
446                 }
447         }
448
449
450         if ((disp_clients_info[DISP_CLIENT_LA_ID(la_id)].win_type  ==
451                                                 TEGRA_LA_DISP_WIN_TYPE_FULL) ||
452                 (disp_clients_info[DISP_CLIENT_LA_ID(la_id)].win_type  ==
453                                                 TEGRA_LA_DISP_WIN_TYPE_FULLA) ||
454                 (disp_clients_info[DISP_CLIENT_LA_ID(la_id)].win_type  ==
455                                                 TEGRA_LA_DISP_WIN_TYPE_FULLB)) {
456                 total_vblank_bw = total_buf_sz_bytes / total_blank_area;
457         } else {
458                 total_vblank_bw = 0;
459         }
460
461
462         bw_display_fp = la_params.disp_catchup_factor_fp *
463                         max(total_active_space_bw,
464                                 total_vblank_bw);
465         if (active)
466                 bw_delta_fp = bw_mbps_fp -
467                                 (bw_display_fp /
468                                 num_active_wins_to_use);
469
470
471         bw_other_wins = total_active_space_bw - bw_mbps;
472
473         if (num_active_wins_to_use > 0) {
474                 fill_rate_other_wins_fp =
475                                 bw_display_fp *
476                                 (num_active_wins_to_use - active) /
477                                 num_active_wins_to_use -
478                                 la_params.la_real_to_fp(bw_other_wins);
479         } else {
480                 fill_rate_other_wins_fp = 0;
481         }
482
483         data_shortfall_other_wins_fp = dvfs_time_nsec *
484                                         bw_other_wins *
485                                         la_params.fp_factor /
486                                         1000;
487
488         duration_usec_fp = (fill_rate_other_wins_fp == 0) ? 0 :
489                                 data_shortfall_other_wins_fp *
490                                 la_params.fp_factor /
491                                 fill_rate_other_wins_fp;
492
493
494         spool_up_buffering_adj_bytes = (bw_delta_fp > 0) ?
495                                         (bw_delta_fp *
496                                         duration_usec_fp /
497                                         (la_params.fp_factor *
498                                         la_params.fp_factor)) :
499                                         0;
500         disp_params->spool_up_buffering_adj_bytes =
501                                                 spool_up_buffering_adj_bytes;
502
503         mutex_lock(&tegra_dcs_total_bw_lock);
504         curr_dc_head_bw = max(dc->new_bw_kbps, dc->bw_kbps);
505         /* our bandwidth is in kbytes/sec, but LA takes MBps.
506          * round up bandwidth to next 1MBps */
507         if (curr_dc_head_bw != ULONG_MAX)
508                 curr_dc_head_bw = curr_dc_head_bw / 1000 + 1;
509         tegra_dcs_total_bw[dc->ctrl_num] = curr_dc_head_bw;
510         disp_params->total_dc0_bw = tegra_dcs_total_bw[0];
511         disp_params->total_dc1_bw = tegra_dcs_total_bw[1];
512         mutex_unlock(&tegra_dcs_total_bw_lock);
513 }
514 #endif
515
516 /*
517  * tegra_dc_process_bandwidth_renegotiate() is only called in code
518  * sections wrapped by CONFIG_TEGRA_ISOMGR.  Thus it is also wrapped
519  * to avoid "defined but not used" compiler error.
520  */
521 #ifdef CONFIG_TEGRA_ISOMGR
522 static void tegra_dc_process_bandwidth_renegotiate(struct tegra_dc *dc,
523                                                 struct tegra_dc_bw_data *bw)
524 {
525 #ifdef CONFIG_ADF_TEGRA
526         tegra_adf_process_bandwidth_renegotiate(dc->adf, bw);
527 #endif
528         tegra_dc_ext_process_bandwidth_renegotiate(dc->ctrl_num, bw);
529 }
530 #endif
531
532 /* uses the larger of w->bandwidth or w->new_bandwidth */
533 static void tegra_dc_set_latency_allowance(struct tegra_dc *dc,
534         struct tegra_dc_win *w)
535 {
536         unsigned long bw;
537         struct dc_to_la_params disp_params;
538 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
539         /* window B V-filter tap for first and second display. */
540         static const enum tegra_la_id vfilter_tab[2] = {
541                 TEGRA_LA_DISPLAY_1B, TEGRA_LA_DISPLAY_1BB,
542         };
543 #endif
544 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
545         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
546         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
547         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
548         struct clk *emc_clk = NULL;
549         unsigned long emc_freq_hz = 0;
550 #endif
551
552
553         BUG_ON(dc->ctrl_num >= ARRAY_SIZE(la_id_tab));
554 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
555         BUG_ON(dc->ctrl_num >= ARRAY_SIZE(vfilter_tab));
556 #endif
557         BUG_ON(w->idx >= ARRAY_SIZE(*la_id_tab));
558
559         bw = max(w->bandwidth, w->new_bandwidth);
560
561 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
562         /* tegra_dc_get_bandwidth() treats V filter windows as double
563          * bandwidth, but LA has a seperate client for V filter */
564         if (w->idx == 1 && win_use_v_filter(dc, w))
565                 bw /= 2;
566 #endif
567
568         /* our bandwidth is in kbytes/sec, but LA takes MBps.
569          * round up bandwidth to next 1MBps */
570         if (bw != ULONG_MAX)
571                 bw = bw / 1000 + 1;
572
573 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
574         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
575         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
576         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
577         /* use clk_round_rate on root emc clock instead to get correct rate */
578         emc_clk = clk_get(NULL, "emc");
579         emc_freq_hz = tegra_emc_bw_to_freq_req(bw);
580         emc_freq_hz = clk_round_rate(emc_clk, emc_freq_hz);
581
582         while (1) {
583                 int err;
584                 unsigned long next_freq = 0;
585
586                 calc_disp_params(dc,
587                                 w,
588                         la_id_tab[dc->ctrl_num][w->idx],
589                                 emc_freq_hz,
590                                 bw,
591                                 &disp_params);
592
593                 err = tegra_set_disp_latency_allowance(
594                                 la_id_tab[dc->ndev->id][w->idx],
595                                 emc_freq_hz,
596                                 bw,
597                                 disp_params);
598                 if (!err) {
599                         struct clk *emc_la_clk = clk_get(&dc->ndev->dev, "emc.la");
600                         clk_set_rate(emc_la_clk, emc_freq_hz);
601                         break;
602                 }
603
604                 next_freq = clk_round_rate(emc_clk, emc_freq_hz + 1);
605
606                 if (emc_freq_hz != next_freq)
607                         emc_freq_hz = next_freq;
608                 else
609                         break;
610         }
611 #else
612         tegra_set_disp_latency_allowance(la_id_tab[dc->ctrl_num][w->idx],
613                                                 emc_freq_hz,
614                                                 bw,
615                                                 disp_params);
616 #endif
617 #if defined(CONFIG_ARCH_TEGRA_2x_SOC) || defined(CONFIG_ARCH_TEGRA_3x_SOC)
618         /* if window B, also set the 1B client for the 2-tap V filter. */
619         if (w->idx == 1)
620                 tegra_set_latency_allowance(vfilter_tab[dc->ctrl_num], bw);
621 #endif
622 }
623
624 /* determine if a row is within a window */
625 static int tegra_dc_line_in_window(int line, struct tegra_dc_win *win)
626 {
627         int win_first = win->out_y;
628         int win_last = win_first + win->out_h - 1;
629
630         return (line >= win_first && line <= win_last);
631 }
632
633 /* check overlapping window combinations to find the max bandwidth. */
634 static unsigned long tegra_dc_find_max_bandwidth(struct tegra_dc_win *wins[],
635                                                  unsigned n)
636 {
637         unsigned i;
638         unsigned j;
639         long max = 0;
640
641         for (i = 0; i < n; i++) {
642                 struct tegra_dc_win *a = wins[i];
643                 long bw = 0;
644                 int a_first = a->out_y;
645
646                 if (!WIN_IS_ENABLED(a))
647                         continue;
648                 for (j = 0; j < n; j++) {
649                         struct tegra_dc_win *b = wins[j];
650
651                         if (!WIN_IS_ENABLED(b))
652                                 continue;
653                         if (tegra_dc_line_in_window(a_first, b))
654                                 bw += b->new_bandwidth;
655                 }
656                 if (max < bw)
657                         max = bw;
658         }
659         return max;
660 }
661
662 static inline int tegra_dc_is_yuv420(int fmt)
663 {
664         switch (fmt) {
665         case TEGRA_WIN_FMT_YCbCr420P:
666         case TEGRA_WIN_FMT_YUV420P:
667         case TEGRA_WIN_FMT_YCrCb420SP:
668         case TEGRA_WIN_FMT_YCbCr420SP:
669         case TEGRA_WIN_FMT_YVU420SP:
670         case TEGRA_WIN_FMT_YUV420SP:
671                 return 1;
672         default:
673                 return 0;
674         }
675 }
676
677 /*
678  * Calculate peak EMC bandwidth for each enabled window =
679  * pixel_clock * win_bpp * (use_v_filter ? 2 : 1)) * H_scale_factor *
680  * (windows_tiling ? 2 : 1)
681  *
682  * note:
683  * (*) We use 2 tap V filter on T2x/T3x, so need double BW if use V filter
684  * (*) Tiling mode on T30 and DDR3 requires double BW
685  *
686  * return:
687  * bandwidth in kBps
688  */
689 static unsigned long tegra_dc_calc_win_bandwidth(struct tegra_dc *dc,
690         struct tegra_dc_win *w)
691 {
692         u64 ret;
693         int tiled_windows_bw_multiplier;
694         unsigned long bpp;
695         unsigned in_w;
696         unsigned out_w;
697         unsigned in_h;
698         unsigned out_h;
699
700         if (!WIN_IS_ENABLED(w))
701                 return 0;
702
703         if (dfixed_trunc(w->w) == 0 || dfixed_trunc(w->h) == 0 ||
704             w->out_w == 0 || w->out_h == 0)
705                 return 0;
706         if (w->flags & TEGRA_WIN_FLAG_SCAN_COLUMN) {
707                 /* rotated: PRESCALE_SIZE swapped, but WIN_SIZE is unchanged */
708                 in_w = dfixed_trunc(w->h);
709                 out_w = w->out_h;
710                 in_h = dfixed_trunc(w->w);
711                 out_h = w->out_w;
712         } else {
713                 in_w = dfixed_trunc(w->w); /* normal output, not rotated */
714                 out_w = w->out_w;
715                 in_h = dfixed_trunc(w->h);
716                 out_h = w->out_h;
717         }
718
719         tiled_windows_bw_multiplier =
720                 tegra_mc_get_tiled_memory_bandwidth_multiplier();
721
722         /* all of tegra's YUV formats(420 and 422) fetch 2 bytes per pixel,
723          * but the size reported by tegra_dc_fmt_bpp for the planar version
724          * is of the luma plane's size only. */
725         bpp = tegra_dc_is_yuv_planar(w->fmt) ?
726                 2 * tegra_dc_fmt_bpp(w->fmt) : tegra_dc_fmt_bpp(w->fmt);
727 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
728         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
729         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
730         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
731         if (tegra_dc_is_yuv420(w->fmt))
732                 bpp = 16;
733 #endif
734
735         ret = (dc->mode.pclk / 1000UL) * (bpp / 8);
736 #if !defined(CONFIG_ARCH_TEGRA_2x_SOC) && \
737         !defined(CONFIG_ARCH_TEGRA_3x_SOC) && \
738         !defined(CONFIG_ARCH_TEGRA_11x_SOC) && \
739         !defined(CONFIG_ARCH_TEGRA_14x_SOC)
740         ret *= (win_use_v_filter(dc, w) ? 2 : 1);
741 #endif
742         ret *= in_w;
743         ret = div_u64(ret, out_w * (WIN_IS_TILED(w) ?
744                       tiled_windows_bw_multiplier : 1));
745         if (in_h > out_h) {
746                 /* vertical downscaling enabled  */
747                 ret *= in_h;
748                 ret = div_u64(ret, out_h);
749         }
750 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
751         /*
752          * Assuming 60% efficiency: i.e. if we calculate we need 70MBps, we
753          * will request 117MBps from EMC.
754          */
755         ret = ret + (17 * div_u64(ret, 25));
756 #endif
757         return ret;
758 }
759
760 static unsigned long tegra_dc_get_bandwidth(
761         struct tegra_dc_win *windows[], int n)
762 {
763         int i;
764
765         BUG_ON(n > DC_N_WINDOWS);
766
767         /* emc rate and latency allowance both need to know per window
768          * bandwidths */
769         for (i = 0; i < n; i++) {
770                 struct tegra_dc_win *w = windows[i];
771
772                 if (w)
773                         w->new_bandwidth =
774                                 tegra_dc_calc_win_bandwidth(w->dc, w);
775         }
776
777         return tegra_dc_find_max_bandwidth(windows, n);
778 }
779
780 #ifdef CONFIG_TEGRA_ISOMGR
781 /* to save power, call when display memory clients would be idle */
782 void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
783 {
784         int latency;
785
786         trace_clear_bandwidth(dc);
787         latency = tegra_isomgr_reserve(dc->isomgr_handle, 0, 1000);
788         if (latency) {
789                 dc->reserved_bw = 0;
790                 latency = tegra_isomgr_realize(dc->isomgr_handle);
791                 WARN_ONCE(!latency, "tegra_isomgr_realize failed\n");
792         } else {
793                 dev_dbg(&dc->ndev->dev, "Failed to clear bw.\n");
794                 tegra_dc_process_bandwidth_renegotiate(dc, NULL);
795         }
796         dc->bw_kbps = 0;
797 }
798 #else
799 /* to save power, call when display memory clients would be idle */
800 void tegra_dc_clear_bandwidth(struct tegra_dc *dc)
801 {
802         trace_clear_bandwidth(dc);
803         if (tegra_is_clk_enabled(dc->emc_clk))
804                 clk_disable_unprepare(dc->emc_clk);
805         dc->bw_kbps = 0;
806 }
807
808 /* bw in kByte/second. returns Hz for EMC frequency */
809 static inline unsigned long tegra_dc_kbps_to_emc(unsigned long bw)
810 {
811         unsigned long freq;
812
813         if (bw == ULONG_MAX)
814                 return ULONG_MAX;
815
816         freq = tegra_emc_bw_to_freq_req(bw);
817         if (freq >= (ULONG_MAX / 1000))
818                 return ULONG_MAX; /* freq too big - clamp at max */
819
820         if (WARN_ONCE((freq * 1000) < freq, "Bandwidth Overflow"))
821                 return ULONG_MAX; /* should never occur because of above. */
822         return freq * 1000;
823 }
824 #endif
825
826 /* use the larger of dc->bw_kbps or dc->new_bw_kbps, and copies
827  * dc->new_bw_kbps into dc->bw_kbps.
828  * calling this function both before and after a flip is sufficient to select
829  * the best possible frequency and latency allowance.
830  * set use_new to true to force dc->new_bw_kbps programming.
831  */
832 void tegra_dc_program_bandwidth(struct tegra_dc *dc, bool use_new)
833 {
834         unsigned i;
835
836         if (!dc->enabled)
837                 return;
838
839         if (!tegra_platform_is_silicon())
840                 return;
841
842         if (use_new || dc->bw_kbps != dc->new_bw_kbps) {
843                 long bw = max(dc->bw_kbps, dc->new_bw_kbps);
844
845 #ifdef CONFIG_TEGRA_ISOMGR
846                 int latency;
847
848                 if (!dc->isomgr_handle)
849                         return;
850
851                 /* reserve atleast the minimum bandwidth. */
852                 bw = max(bw, tegra_dc_calc_min_bandwidth(dc));
853                 latency = tegra_isomgr_reserve(dc->isomgr_handle, bw, 1000);
854                 if (latency) {
855                         dc->reserved_bw = bw;
856                         latency = tegra_isomgr_realize(dc->isomgr_handle);
857                         WARN_ONCE(!latency, "tegra_isomgr_realize failed\n");
858                 } else {
859                         dev_dbg(&dc->ndev->dev, "Failed to reserve bw %ld.\n",
860                                                                         bw);
861                         tegra_dc_process_bandwidth_renegotiate(dc, NULL);
862                 }
863 #else /* EMC version */
864                 int emc_freq;
865
866                 /* going from 0 to non-zero */
867                 if (!dc->bw_kbps && dc->new_bw_kbps &&
868                         !tegra_is_clk_enabled(dc->emc_clk))
869                         clk_prepare_enable(dc->emc_clk);
870
871                 emc_freq = tegra_dc_kbps_to_emc(bw);
872                 clk_set_rate(dc->emc_clk, emc_freq);
873
874                 /* going from non-zero to 0 */
875                 if (dc->bw_kbps && !dc->new_bw_kbps &&
876                         tegra_is_clk_enabled(dc->emc_clk))
877                         clk_disable_unprepare(dc->emc_clk);
878 #endif
879                 dc->bw_kbps = dc->new_bw_kbps;
880         }
881
882         for_each_set_bit(i, &dc->valid_windows, DC_N_WINDOWS) {
883                 struct tegra_dc_win *w = &dc->windows[i];
884
885                 if ((use_new || w->bandwidth != w->new_bandwidth) &&
886                         w->new_bandwidth != 0)
887                         tegra_dc_set_latency_allowance(dc, w);
888                 trace_program_bandwidth(dc);
889                 w->bandwidth = w->new_bandwidth;
890         }
891 }
892
893 int tegra_dc_set_dynamic_emc(struct tegra_dc *dc)
894 {
895         unsigned long new_rate;
896         struct tegra_dc_win *windows[DC_N_WINDOWS];
897         unsigned i;
898         unsigned len;
899         unsigned win_status = 0;
900
901         if (!use_dynamic_emc)
902                 return 0;
903
904         for (i = 0, len = 0; i < DC_N_WINDOWS; i++) {
905                 struct tegra_dc_win *win = tegra_dc_get_window(dc, i);
906                 if (win) {
907                         windows[len++] = win;
908                         if (win->flags & TEGRA_WIN_FLAG_ENABLED)
909                                 win_status |= 1 << i;
910                 }
911         }
912 #ifdef CONFIG_TEGRA_ISOMGR
913         new_rate = tegra_dc_get_bandwidth(windows, len);
914 #else
915         if (tegra_dc_has_multiple_dc())
916                 new_rate = ULONG_MAX;
917         else
918                 new_rate = tegra_dc_get_bandwidth(windows, len);
919 #endif
920
921         dc->new_bw_kbps = new_rate;
922         trace_set_dynamic_emc(dc);
923
924         /* if low_v_win is set, we can lower vdd_core when
925                 that windows is the only one active */
926         if (dc->pdata->low_v_win != 0) {
927                 if (win_status == dc->pdata->low_v_win &&
928                         dc->win_status != dc->pdata->low_v_win) {
929                         tegra_dvfs_use_alt_freqs_on_clk(dc->clk, true);
930                         dc->win_status = dc->pdata->low_v_win;
931                 } else if (win_status != dc->pdata->low_v_win &&
932                         dc->win_status == dc->pdata->low_v_win) {
933                         tegra_dvfs_use_alt_freqs_on_clk(dc->clk, false);
934                         dc->win_status = win_status;
935                 }
936         }
937         return 0;
938 }
939
940 /* return the minimum bandwidth in kbps for display to function */
941 long tegra_dc_calc_min_bandwidth(struct tegra_dc *dc)
942 {
943         unsigned  pclk;
944
945         if (WARN_ONCE(!dc, "dc is NULL") ||
946                 WARN_ONCE(!dc->out, "dc->out is NULL!"))
947                 return 0;
948
949         pclk = tegra_dc_get_out_max_pixclock(dc);
950         if (!pclk) {
951                  if (dc->out->type == TEGRA_DC_OUT_HDMI) {
952 #if defined(CONFIG_ARCH_TEGRA_11x_SOC) || defined(CONFIG_ARCH_TEGRA_12x_SOC)
953                         pclk = KHZ2PICOS(300000); /* 300MHz max */
954 #elif defined(CONFIG_ARCH_TEGRA_21x_SOC)
955                         pclk = KHZ2PICOS(600000); /* 600MHz max */
956 #else
957                         pclk = KHZ2PICOS(150000); /* 150MHz max */
958 #endif
959                 } else if ((dc->out->type == TEGRA_DC_OUT_DP) ||
960                         (dc->out->type == TEGRA_DC_OUT_FAKE_DP) ||
961                         (dc->out->type == TEGRA_DC_OUT_NULL) ||
962                         (dc->out->type == TEGRA_DC_OUT_NVSR_DP)) {
963                         if (dc->mode.pclk)
964                                 pclk = KHZ2PICOS(dc->mode.pclk / 1000);
965                         else
966                                 pclk = KHZ2PICOS(25200); /* vga */
967                 } else {
968                         if (!WARN_ONCE(!dc->mode.pclk,
969                                 "pclk is not set, bandwidth calc cannot work"))
970                                 pclk = KHZ2PICOS(dc->mode.pclk / 1000);
971                 }
972         }
973
974         return PICOS2KHZ(pclk) * 4; /* support a single 32bpp window */
975 }
976
977 #ifdef CONFIG_TEGRA_ISOMGR
978 int tegra_dc_bandwidth_negotiate_bw(struct tegra_dc *dc,
979                         struct tegra_dc_win *windows[], int n)
980 {
981         int latency;
982         u32 bw;
983
984         mutex_lock(&dc->lock);
985         /*
986          * isomgr will update available bandwidth through a callback.
987          * If available bandwidth is less than proposed bw fail the ioctl.
988          * If proposed bw is larger than reserved bw, make it in effect
989          * immediately. Otherwise, bandwidth will be adjusted in flips.
990          */
991         bw = tegra_dc_get_bandwidth(windows, n);
992         if (bw > dc->available_bw) {
993                 mutex_unlock(&dc->lock);
994                 return -1;
995         } else if (bw <= dc->reserved_bw) {
996                 mutex_unlock(&dc->lock);
997                 return 0;
998         }
999
1000         latency = tegra_isomgr_reserve(dc->isomgr_handle, bw, 1000);
1001         if (!latency) {
1002                 dev_dbg(&dc->ndev->dev, "Failed to reserve proposed bw %d.\n",
1003                                                                         bw);
1004                 mutex_unlock(&dc->lock);
1005                 return -1;
1006         }
1007
1008         /*
1009          * Only realize if bw required > reserved bw
1010          * If realized, update dc->bw_kbps
1011          */
1012         if (dc->reserved_bw < bw) {
1013                 dc->reserved_bw = bw;
1014                 latency = tegra_isomgr_realize(dc->isomgr_handle);
1015                 if (!latency) {
1016                         WARN_ONCE(!latency, "tegra_isomgr_realize failed\n");
1017                         mutex_unlock(&dc->lock);
1018                         return -1;
1019                 }
1020                 dc->bw_kbps = bw;
1021         }
1022
1023         mutex_unlock(&dc->lock);
1024
1025         return 0;
1026 }
1027 EXPORT_SYMBOL(tegra_dc_bandwidth_negotiate_bw);
1028
1029 void tegra_dc_bandwidth_renegotiate(void *p, u32 avail_bw)
1030 {
1031         struct tegra_dc_bw_data data;
1032         struct tegra_dc *dc = p;
1033
1034         if (WARN_ONCE(!dc, "dc is NULL!"))
1035                 return;
1036
1037         if (dc->available_bw == avail_bw)
1038                 return;
1039
1040         data.total_bw = tegra_isomgr_get_total_iso_bw();
1041         data.avail_bw = avail_bw;
1042         data.resvd_bw = dc->reserved_bw;
1043
1044         tegra_dc_process_bandwidth_renegotiate(dc, &data);
1045
1046         mutex_lock(&dc->lock);
1047         dc->available_bw = avail_bw;
1048         mutex_unlock(&dc->lock);
1049 }
1050 #endif