drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37
  38 #include <plat/sram.h>
  39 #include <plat/clock.h>
  40
  41 #include <video/omapdss.h>
  42
  43 #include "dss.h"
  44 #include "dss_features.h"
  45 #include "dispc.h"
  46
  47 /* DISPC */
  48 #define DISPC_SZ_REGS                   SZ_4K
  49
  50 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  51                                          DISPC_IRQ_OCP_ERR | \
  52                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  53                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_SYNC_LOST | \
  55                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  56
  57 #define DISPC_MAX_NR_ISRS               8
  58
  59 struct omap_dispc_isr_data {
  60         omap_dispc_isr_t        isr;
  61         void                    *arg;
  62         u32                     mask;
  63 };
  64
  65 struct dispc_h_coef {
  66         s8 hc4;
  67         s8 hc3;
  68         u8 hc2;
  69         s8 hc1;
  70         s8 hc0;
  71 };
  72
  73 struct dispc_v_coef {
  74         s8 vc22;
  75         s8 vc2;
  76         u8 vc1;
  77         s8 vc0;
  78         s8 vc00;
  79 };
  80
  81 #define REG_GET(idx, start, end) \
  82         FLD_GET(dispc_read_reg(idx), start, end)
  83
  84 #define REG_FLD_MOD(idx, val, start, end)                               \
  85         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  86
  87 struct dispc_irq_stats {
  88         unsigned long last_reset;
  89         unsigned irq_count;
  90         unsigned irqs[32];
  91 };
  92
  93 static struct {
  94         struct platform_device *pdev;
  95         void __iomem    *base;
  96         int irq;
  97
  98         u32     fifo_size[3];
  99
 100         spinlock_t irq_lock;
 101         u32 irq_error_mask;
 102         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 103         u32 error_irqs;
 104         struct work_struct error_work;
 105
 106         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 107
 108 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 109         spinlock_t irq_stats_lock;
 110         struct dispc_irq_stats irq_stats;
 111 #endif
 112 } dispc;
 113
 114 enum omap_color_component {
 115         /* used for all color formats for OMAP3 and earlier
 116          * and for RGB and Y color component on OMAP4
 117          */
 118         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 119         /* used for UV component for
 120          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 121          * color formats on OMAP4
 122          */
 123         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 124 };
 125
 126 static void _omap_dispc_set_irqs(void);
 127
 128 static inline void dispc_write_reg(const u16 idx, u32 val)
 129 {
 130         __raw_writel(val, dispc.base + idx);
 131 }
 132
 133 static inline u32 dispc_read_reg(const u16 idx)
 134 {
 135         return __raw_readl(dispc.base + idx);
 136 }
 137
 138 #define SR(reg) \
 139         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 140 #define RR(reg) \
 141         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 142
 143 void dispc_save_context(void)
 144 {
 145         int i;
 146         if (cpu_is_omap24xx())
 147                 return;
 148
 149         SR(SYSCONFIG);
 150         SR(IRQENABLE);
 151         SR(CONTROL);
 152         SR(CONFIG);
 153         SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
 154         SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
 155         SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
 156         SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
 157         SR(LINE_NUMBER);
 158         SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
 159         SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
 160         SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
 161         SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
 162         SR(GLOBAL_ALPHA);
 163         SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
 164         SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
 165         if (dss_has_feature(FEAT_MGR_LCD2)) {
 166                 SR(CONTROL2);
 167                 SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
 168                 SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
 169                 SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
 170                 SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
 171                 SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
 172                 SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
 173                 SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
 174                 SR(CONFIG2);
 175         }
 176
 177         SR(OVL_BA0(OMAP_DSS_GFX));
 178         SR(OVL_BA1(OMAP_DSS_GFX));
 179         SR(OVL_POSITION(OMAP_DSS_GFX));
 180         SR(OVL_SIZE(OMAP_DSS_GFX));
 181         SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
 182         SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
 183         SR(OVL_ROW_INC(OMAP_DSS_GFX));
 184         SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
 185         SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
 186         SR(OVL_TABLE_BA(OMAP_DSS_GFX));
 187
 188         SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
 189         SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
 190         SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
 191
 192         SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
 193         SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
 194         SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
 195         if (dss_has_feature(FEAT_MGR_LCD2)) {
 196                 SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
 197                 SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
 198                 SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
 199
 200                 SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
 201                 SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
 202                 SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
 203         }
 204
 205         SR(OVL_PRELOAD(OMAP_DSS_GFX));
 206
 207         /* VID1 */
 208         SR(OVL_BA0(OMAP_DSS_VIDEO1));
 209         SR(OVL_BA1(OMAP_DSS_VIDEO1));
 210         SR(OVL_POSITION(OMAP_DSS_VIDEO1));
 211         SR(OVL_SIZE(OMAP_DSS_VIDEO1));
 212         SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
 213         SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
 214         SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
 215         SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
 216         SR(OVL_FIR(OMAP_DSS_VIDEO1));
 217         SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
 218         SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
 219         SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
 220
 221         for (i = 0; i < 8; i++)
 222                 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
 223
 224         for (i = 0; i < 8; i++)
 225                 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
 226
 227         for (i = 0; i < 5; i++)
 228                 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
 229
 230         for (i = 0; i < 8; i++)
 231                 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 232
 233         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 234                 SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
 235                 SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
 236                 SR(OVL_FIR2(OMAP_DSS_VIDEO1));
 237                 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
 238                 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
 239
 240                 for (i = 0; i < 8; i++)
 241                         SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
 242
 243                 for (i = 0; i < 8; i++)
 244                         SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
 245
 246                 for (i = 0; i < 8; i++)
 247                         SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
 248         }
 249         if (dss_has_feature(FEAT_ATTR2))
 250                 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
 251
 252         SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 253
 254         /* VID2 */
 255         SR(OVL_BA0(OMAP_DSS_VIDEO2));
 256         SR(OVL_BA1(OMAP_DSS_VIDEO2));
 257         SR(OVL_POSITION(OMAP_DSS_VIDEO2));
 258         SR(OVL_SIZE(OMAP_DSS_VIDEO2));
 259         SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
 260         SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
 261         SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
 262         SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
 263         SR(OVL_FIR(OMAP_DSS_VIDEO2));
 264         SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
 265         SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
 266         SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
 267
 268         for (i = 0; i < 8; i++)
 269                 SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
 270
 271         for (i = 0; i < 8; i++)
 272                 SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
 273
 274         for (i = 0; i < 5; i++)
 275                 SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
 276
 277         for (i = 0; i < 8; i++)
 278                 SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 279
 280         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 281                 SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
 282                 SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
 283                 SR(OVL_FIR2(OMAP_DSS_VIDEO2));
 284                 SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
 285                 SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
 286
 287                 for (i = 0; i < 8; i++)
 288                         SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
 289
 290                 for (i = 0; i < 8; i++)
 291                         SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
 292
 293                 for (i = 0; i < 8; i++)
 294                         SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
 295         }
 296         if (dss_has_feature(FEAT_ATTR2))
 297                 SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
 298
 299         SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 300
 301         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 302                 SR(DIVISOR);
 303 }
 304
 305 void dispc_restore_context(void)
 306 {
 307         int i;
 308         RR(SYSCONFIG);
 309         /*RR(IRQENABLE);*/
 310         /*RR(CONTROL);*/
 311         RR(CONFIG);
 312         RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
 313         RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
 314         RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
 315         RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
 316         RR(LINE_NUMBER);
 317         RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
 318         RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
 319         RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
 320         RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
 321         RR(GLOBAL_ALPHA);
 322         RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
 323         RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
 324         if (dss_has_feature(FEAT_MGR_LCD2)) {
 325                 RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
 326                 RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
 327                 RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
 328                 RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
 329                 RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
 330                 RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
 331                 RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
 332                 RR(CONFIG2);
 333         }
 334
 335         RR(OVL_BA0(OMAP_DSS_GFX));
 336         RR(OVL_BA1(OMAP_DSS_GFX));
 337         RR(OVL_POSITION(OMAP_DSS_GFX));
 338         RR(OVL_SIZE(OMAP_DSS_GFX));
 339         RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
 340         RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
 341         RR(OVL_ROW_INC(OMAP_DSS_GFX));
 342         RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
 343         RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
 344         RR(OVL_TABLE_BA(OMAP_DSS_GFX));
 345
 346
 347         RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
 348         RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
 349         RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
 350
 351         RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
 352         RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
 353         RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
 354         if (dss_has_feature(FEAT_MGR_LCD2)) {
 355                 RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
 356                 RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
 357                 RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
 358
 359                 RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
 360                 RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
 361                 RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
 362         }
 363
 364         RR(OVL_PRELOAD(OMAP_DSS_GFX));
 365
 366         /* VID1 */
 367         RR(OVL_BA0(OMAP_DSS_VIDEO1));
 368         RR(OVL_BA1(OMAP_DSS_VIDEO1));
 369         RR(OVL_POSITION(OMAP_DSS_VIDEO1));
 370         RR(OVL_SIZE(OMAP_DSS_VIDEO1));
 371         RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
 372         RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
 373         RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
 374         RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
 375         RR(OVL_FIR(OMAP_DSS_VIDEO1));
 376         RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
 377         RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
 378         RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
 379
 380         for (i = 0; i < 8; i++)
 381                 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
 382
 383         for (i = 0; i < 8; i++)
 384                 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
 385
 386         for (i = 0; i < 5; i++)
 387                 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
 388
 389         for (i = 0; i < 8; i++)
 390                 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
 391
 392         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 393                 RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
 394                 RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
 395                 RR(OVL_FIR2(OMAP_DSS_VIDEO1));
 396                 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
 397                 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
 398
 399                 for (i = 0; i < 8; i++)
 400                         RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
 401
 402                 for (i = 0; i < 8; i++)
 403                         RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
 404
 405                 for (i = 0; i < 8; i++)
 406                         RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
 407         }
 408         if (dss_has_feature(FEAT_ATTR2))
 409                 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
 410
 411         RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
 412
 413         /* VID2 */
 414         RR(OVL_BA0(OMAP_DSS_VIDEO2));
 415         RR(OVL_BA1(OMAP_DSS_VIDEO2));
 416         RR(OVL_POSITION(OMAP_DSS_VIDEO2));
 417         RR(OVL_SIZE(OMAP_DSS_VIDEO2));
 418         RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
 419         RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
 420         RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
 421         RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
 422         RR(OVL_FIR(OMAP_DSS_VIDEO2));
 423         RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
 424         RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
 425         RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
 426
 427         for (i = 0; i < 8; i++)
 428                 RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
 429
 430         for (i = 0; i < 8; i++)
 431                 RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
 432
 433         for (i = 0; i < 5; i++)
 434                 RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
 435
 436         for (i = 0; i < 8; i++)
 437                 RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
 438
 439         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 440                 RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
 441                 RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
 442                 RR(OVL_FIR2(OMAP_DSS_VIDEO2));
 443                 RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
 444                 RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
 445
 446                 for (i = 0; i < 8; i++)
 447                         RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
 448
 449                 for (i = 0; i < 8; i++)
 450                         RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
 451
 452                 for (i = 0; i < 8; i++)
 453                         RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
 454         }
 455         if (dss_has_feature(FEAT_ATTR2))
 456                 RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
 457
 458         RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
 459
 460         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 461                 RR(DIVISOR);
 462
 463         /* enable last, because LCD & DIGIT enable are here */
 464         RR(CONTROL);
 465         if (dss_has_feature(FEAT_MGR_LCD2))
 466                 RR(CONTROL2);
 467         /* clear spurious SYNC_LOST_DIGIT interrupts */
 468         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 469
 470         /*
 471          * enable last so IRQs won't trigger before
 472          * the context is fully restored
 473          */
 474         RR(IRQENABLE);
 475 }
 476
 477 #undef SR
 478 #undef RR
 479
 480 static inline void enable_clocks(bool enable)
 481 {
 482         if (enable)
 483                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
 484         else
 485                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
 486 }
 487
 488 bool dispc_go_busy(enum omap_channel channel)
 489 {
 490         int bit;
 491
 492         if (channel == OMAP_DSS_CHANNEL_LCD ||
 493                         channel == OMAP_DSS_CHANNEL_LCD2)
 494                 bit = 5; /* GOLCD */
 495         else
 496                 bit = 6; /* GODIGIT */
 497
 498         if (channel == OMAP_DSS_CHANNEL_LCD2)
 499                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 500         else
 501                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 502 }
 503
 504 void dispc_go(enum omap_channel channel)
 505 {
 506         int bit;
 507         bool enable_bit, go_bit;
 508
 509         enable_clocks(1);
 510
 511         if (channel == OMAP_DSS_CHANNEL_LCD ||
 512                         channel == OMAP_DSS_CHANNEL_LCD2)
 513                 bit = 0; /* LCDENABLE */
 514         else
 515                 bit = 1; /* DIGITALENABLE */
 516
 517         /* if the channel is not enabled, we don't need GO */
 518         if (channel == OMAP_DSS_CHANNEL_LCD2)
 519                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 520         else
 521                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 522
 523         if (!enable_bit)
 524                 goto end;
 525
 526         if (channel == OMAP_DSS_CHANNEL_LCD ||
 527                         channel == OMAP_DSS_CHANNEL_LCD2)
 528                 bit = 5; /* GOLCD */
 529         else
 530                 bit = 6; /* GODIGIT */
 531
 532         if (channel == OMAP_DSS_CHANNEL_LCD2)
 533                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 534         else
 535                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 536
 537         if (go_bit) {
 538                 DSSERR("GO bit not down for channel %d\n", channel);
 539                 goto end;
 540         }
 541
 542         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 543                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 544
 545         if (channel == OMAP_DSS_CHANNEL_LCD2)
 546                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 547         else
 548                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 549 end:
 550         enable_clocks(0);
 551 }
 552
 553 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 554 {
 555         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 556 }
 557
 558 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 559 {
 560         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 561 }
 562
 563 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 564 {
 565         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 566 }
 567
 568 static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 569 {
 570         BUG_ON(plane == OMAP_DSS_GFX);
 571
 572         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 573 }
 574
 575 static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
 576 {
 577         BUG_ON(plane == OMAP_DSS_GFX);
 578
 579         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 580 }
 581
 582 static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 583 {
 584         BUG_ON(plane == OMAP_DSS_GFX);
 585
 586         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 587 }
 588
 589 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 590                                   int vscaleup, int five_taps,
 591                                   enum omap_color_component color_comp)
 592 {
 593         /* Coefficients for horizontal up-sampling */
 594         static const struct dispc_h_coef coef_hup[8] = {
 595                 {  0,   0, 128,   0,  0 },
 596                 { -1,  13, 124,  -8,  0 },
 597                 { -2,  30, 112, -11, -1 },
 598                 { -5,  51,  95, -11, -2 },
 599                 {  0,  -9,  73,  73, -9 },
 600                 { -2, -11,  95,  51, -5 },
 601                 { -1, -11, 112,  30, -2 },
 602                 {  0,  -8, 124,  13, -1 },
 603         };
 604
 605         /* Coefficients for vertical up-sampling */
 606         static const struct dispc_v_coef coef_vup_3tap[8] = {
 607                 { 0,  0, 128,  0, 0 },
 608                 { 0,  3, 123,  2, 0 },
 609                 { 0, 12, 111,  5, 0 },
 610                 { 0, 32,  89,  7, 0 },
 611                 { 0,  0,  64, 64, 0 },
 612                 { 0,  7,  89, 32, 0 },
 613                 { 0,  5, 111, 12, 0 },
 614                 { 0,  2, 123,  3, 0 },
 615         };
 616
 617         static const struct dispc_v_coef coef_vup_5tap[8] = {
 618                 {  0,   0, 128,   0,  0 },
 619                 { -1,  13, 124,  -8,  0 },
 620                 { -2,  30, 112, -11, -1 },
 621                 { -5,  51,  95, -11, -2 },
 622                 {  0,  -9,  73,  73, -9 },
 623                 { -2, -11,  95,  51, -5 },
 624                 { -1, -11, 112,  30, -2 },
 625                 {  0,  -8, 124,  13, -1 },
 626         };
 627
 628         /* Coefficients for horizontal down-sampling */
 629         static const struct dispc_h_coef coef_hdown[8] = {
 630                 {   0, 36, 56, 36,  0 },
 631                 {   4, 40, 55, 31, -2 },
 632                 {   8, 44, 54, 27, -5 },
 633                 {  12, 48, 53, 22, -7 },
 634                 {  -9, 17, 52, 51, 17 },
 635                 {  -7, 22, 53, 48, 12 },
 636                 {  -5, 27, 54, 44,  8 },
 637                 {  -2, 31, 55, 40,  4 },
 638         };
 639
 640         /* Coefficients for vertical down-sampling */
 641         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 642                 { 0, 36, 56, 36, 0 },
 643                 { 0, 40, 57, 31, 0 },
 644                 { 0, 45, 56, 27, 0 },
 645                 { 0, 50, 55, 23, 0 },
 646                 { 0, 18, 55, 55, 0 },
 647                 { 0, 23, 55, 50, 0 },
 648                 { 0, 27, 56, 45, 0 },
 649                 { 0, 31, 57, 40, 0 },
 650         };
 651
 652         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 653                 {   0, 36, 56, 36,  0 },
 654                 {   4, 40, 55, 31, -2 },
 655                 {   8, 44, 54, 27, -5 },
 656                 {  12, 48, 53, 22, -7 },
 657                 {  -9, 17, 52, 51, 17 },
 658                 {  -7, 22, 53, 48, 12 },
 659                 {  -5, 27, 54, 44,  8 },
 660                 {  -2, 31, 55, 40,  4 },
 661         };
 662
 663         const struct dispc_h_coef *h_coef;
 664         const struct dispc_v_coef *v_coef;
 665         int i;
 666
 667         if (hscaleup)
 668                 h_coef = coef_hup;
 669         else
 670                 h_coef = coef_hdown;
 671
 672         if (vscaleup)
 673                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 674         else
 675                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 676
 677         for (i = 0; i < 8; i++) {
 678                 u32 h, hv;
 679
 680                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 681                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 682                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 683                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 684                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 685                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 686                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 687                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 688
 689                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 690                         _dispc_write_firh_reg(plane, i, h);
 691                         _dispc_write_firhv_reg(plane, i, hv);
 692                 } else {
 693                         _dispc_write_firh2_reg(plane, i, h);
 694                         _dispc_write_firhv2_reg(plane, i, hv);
 695                 }
 696
 697         }
 698
 699         if (five_taps) {
 700                 for (i = 0; i < 8; i++) {
 701                         u32 v;
 702                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 703                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 704                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 705                                 _dispc_write_firv_reg(plane, i, v);
 706                         else
 707                                 _dispc_write_firv2_reg(plane, i, v);
 708                 }
 709         }
 710 }
 711
 712 static void _dispc_setup_color_conv_coef(void)
 713 {
 714         const struct color_conv_coef {
 715                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 716                 int  full_range;
 717         }  ctbl_bt601_5 = {
 718                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 719         };
 720
 721         const struct color_conv_coef *ct;
 722
 723 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 724
 725         ct = &ctbl_bt601_5;
 726
 727         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
 728                 CVAL(ct->rcr, ct->ry));
 729         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
 730                 CVAL(ct->gy,  ct->rcb));
 731         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
 732                 CVAL(ct->gcb, ct->gcr));
 733         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
 734                 CVAL(ct->bcr, ct->by));
 735         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
 736                 CVAL(0, ct->bcb));
 737
 738         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
 739                 CVAL(ct->rcr, ct->ry));
 740         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
 741                 CVAL(ct->gy, ct->rcb));
 742         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
 743                 CVAL(ct->gcb, ct->gcr));
 744         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
 745                 CVAL(ct->bcr, ct->by));
 746         dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
 747                 CVAL(0, ct->bcb));
 748
 749 #undef CVAL
 750
 751         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
 752                 ct->full_range, 11, 11);
 753         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
 754                 ct->full_range, 11, 11);
 755 }
 756
 757
 758 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 759 {
 760         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 761 }
 762
 763 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 764 {
 765         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 766 }
 767
 768 static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
 769 {
 770         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 771 }
 772
 773 static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
 774 {
 775         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 776 }
 777
 778 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 779 {
 780         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 781
 782         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 783 }
 784
 785 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 786 {
 787         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 788
 789         if (plane == OMAP_DSS_GFX)
 790                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 791         else
 792                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 793 }
 794
 795 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 796 {
 797         u32 val;
 798
 799         BUG_ON(plane == OMAP_DSS_GFX);
 800
 801         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 802
 803         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 804 }
 805
 806 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 807 {
 808         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 809                 return;
 810
 811         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 812                 plane == OMAP_DSS_VIDEO1)
 813                 return;
 814
 815         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 816 }
 817
 818 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 819 {
 820         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 821                 return;
 822
 823         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 824                 plane == OMAP_DSS_VIDEO1)
 825                 return;
 826
 827         if (plane == OMAP_DSS_GFX)
 828                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 829         else if (plane == OMAP_DSS_VIDEO2)
 830                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 831 }
 832
 833 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 834 {
 835         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 836 }
 837
 838 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 839 {
 840         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 841 }
 842
 843 static void _dispc_set_color_mode(enum omap_plane plane,
 844                 enum omap_color_mode color_mode)
 845 {
 846         u32 m = 0;
 847         if (plane != OMAP_DSS_GFX) {
 848                 switch (color_mode) {
 849                 case OMAP_DSS_COLOR_NV12:
 850                         m = 0x0; break;
 851                 case OMAP_DSS_COLOR_RGB12U:
 852                         m = 0x1; break;
 853                 case OMAP_DSS_COLOR_RGBA16:
 854                         m = 0x2; break;
 855                 case OMAP_DSS_COLOR_RGBX16:
 856                         m = 0x4; break;
 857                 case OMAP_DSS_COLOR_ARGB16:
 858                         m = 0x5; break;
 859                 case OMAP_DSS_COLOR_RGB16:
 860                         m = 0x6; break;
 861                 case OMAP_DSS_COLOR_ARGB16_1555:
 862                         m = 0x7; break;
 863                 case OMAP_DSS_COLOR_RGB24U:
 864                         m = 0x8; break;
 865                 case OMAP_DSS_COLOR_RGB24P:
 866                         m = 0x9; break;
 867                 case OMAP_DSS_COLOR_YUV2:
 868                         m = 0xa; break;
 869                 case OMAP_DSS_COLOR_UYVY:
 870                         m = 0xb; break;
 871                 case OMAP_DSS_COLOR_ARGB32:
 872                         m = 0xc; break;
 873                 case OMAP_DSS_COLOR_RGBA32:
 874                         m = 0xd; break;
 875                 case OMAP_DSS_COLOR_RGBX32:
 876                         m = 0xe; break;
 877                 case OMAP_DSS_COLOR_XRGB16_1555:
 878                         m = 0xf; break;
 879                 default:
 880                         BUG(); break;
 881                 }
 882         } else {
 883                 switch (color_mode) {
 884                 case OMAP_DSS_COLOR_CLUT1:
 885                         m = 0x0; break;
 886                 case OMAP_DSS_COLOR_CLUT2:
 887                         m = 0x1; break;
 888                 case OMAP_DSS_COLOR_CLUT4:
 889                         m = 0x2; break;
 890                 case OMAP_DSS_COLOR_CLUT8:
 891                         m = 0x3; break;
 892                 case OMAP_DSS_COLOR_RGB12U:
 893                         m = 0x4; break;
 894                 case OMAP_DSS_COLOR_ARGB16:
 895                         m = 0x5; break;
 896                 case OMAP_DSS_COLOR_RGB16:
 897                         m = 0x6; break;
 898                 case OMAP_DSS_COLOR_ARGB16_1555:
 899                         m = 0x7; break;
 900                 case OMAP_DSS_COLOR_RGB24U:
 901                         m = 0x8; break;
 902                 case OMAP_DSS_COLOR_RGB24P:
 903                         m = 0x9; break;
 904                 case OMAP_DSS_COLOR_YUV2:
 905                         m = 0xa; break;
 906                 case OMAP_DSS_COLOR_UYVY:
 907                         m = 0xb; break;
 908                 case OMAP_DSS_COLOR_ARGB32:
 909                         m = 0xc; break;
 910                 case OMAP_DSS_COLOR_RGBA32:
 911                         m = 0xd; break;
 912                 case OMAP_DSS_COLOR_RGBX32:
 913                         m = 0xe; break;
 914                 case OMAP_DSS_COLOR_XRGB16_1555:
 915                         m = 0xf; break;
 916                 default:
 917                         BUG(); break;
 918                 }
 919         }
 920
 921         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 922 }
 923
 924 static void _dispc_set_channel_out(enum omap_plane plane,
 925                 enum omap_channel channel)
 926 {
 927         int shift;
 928         u32 val;
 929         int chan = 0, chan2 = 0;
 930
 931         switch (plane) {
 932         case OMAP_DSS_GFX:
 933                 shift = 8;
 934                 break;
 935         case OMAP_DSS_VIDEO1:
 936         case OMAP_DSS_VIDEO2:
 937                 shift = 16;
 938                 break;
 939         default:
 940                 BUG();
 941                 return;
 942         }
 943
 944         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 945         if (dss_has_feature(FEAT_MGR_LCD2)) {
 946                 switch (channel) {
 947                 case OMAP_DSS_CHANNEL_LCD:
 948                         chan = 0;
 949                         chan2 = 0;
 950                         break;
 951                 case OMAP_DSS_CHANNEL_DIGIT:
 952                         chan = 1;
 953                         chan2 = 0;
 954                         break;
 955                 case OMAP_DSS_CHANNEL_LCD2:
 956                         chan = 0;
 957                         chan2 = 1;
 958                         break;
 959                 default:
 960                         BUG();
 961                 }
 962
 963                 val = FLD_MOD(val, chan, shift, shift);
 964                 val = FLD_MOD(val, chan2, 31, 30);
 965         } else {
 966                 val = FLD_MOD(val, channel, shift, shift);
 967         }
 968         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 969 }
 970
 971 void dispc_set_burst_size(enum omap_plane plane,
 972                 enum omap_burst_size burst_size)
 973 {
 974         int shift;
 975         u32 val;
 976
 977         enable_clocks(1);
 978
 979         switch (plane) {
 980         case OMAP_DSS_GFX:
 981                 shift = 6;
 982                 break;
 983         case OMAP_DSS_VIDEO1:
 984         case OMAP_DSS_VIDEO2:
 985                 shift = 14;
 986                 break;
 987         default:
 988                 BUG();
 989                 return;
 990         }
 991
 992         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 993         val = FLD_MOD(val, burst_size, shift+1, shift);
 994         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 995
 996         enable_clocks(0);
 997 }
 998
 999 void dispc_enable_gamma_table(bool enable)
1000 {
1001         /*
1002          * This is partially implemented to support only disabling of
1003          * the gamma table.
1004          */
1005         if (enable) {
1006                 DSSWARN("Gamma table enabling for TV not yet supported");
1007                 return;
1008         }
1009
1010         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
1011 }
1012
1013 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
1014 {
1015         u32 val;
1016
1017         BUG_ON(plane == OMAP_DSS_GFX);
1018
1019         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1020         val = FLD_MOD(val, enable, 9, 9);
1021         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1022 }
1023
1024 void dispc_enable_replication(enum omap_plane plane, bool enable)
1025 {
1026         int bit;
1027
1028         if (plane == OMAP_DSS_GFX)
1029                 bit = 5;
1030         else
1031                 bit = 10;
1032
1033         enable_clocks(1);
1034         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
1035         enable_clocks(0);
1036 }
1037
1038 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1039 {
1040         u32 val;
1041         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1042         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1043         enable_clocks(1);
1044         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1045         enable_clocks(0);
1046 }
1047
1048 void dispc_set_digit_size(u16 width, u16 height)
1049 {
1050         u32 val;
1051         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1052         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1053         enable_clocks(1);
1054         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1055         enable_clocks(0);
1056 }
1057
1058 static void dispc_read_plane_fifo_sizes(void)
1059 {
1060         u32 size;
1061         int plane;
1062         u8 start, end;
1063
1064         enable_clocks(1);
1065
1066         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1067
1068         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
1069                 size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
1070                         start, end);
1071                 dispc.fifo_size[plane] = size;
1072         }
1073
1074         enable_clocks(0);
1075 }
1076
1077 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
1078 {
1079         return dispc.fifo_size[plane];
1080 }
1081
1082 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1083 {
1084         u8 hi_start, hi_end, lo_start, lo_end;
1085
1086         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1087         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1088
1089         enable_clocks(1);
1090
1091         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1092                         plane,
1093                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1094                                 lo_start, lo_end),
1095                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1096                                 hi_start, hi_end),
1097                         low, high);
1098
1099         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1100                         FLD_VAL(high, hi_start, hi_end) |
1101                         FLD_VAL(low, lo_start, lo_end));
1102
1103         enable_clocks(0);
1104 }
1105
1106 void dispc_enable_fifomerge(bool enable)
1107 {
1108         enable_clocks(1);
1109
1110         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1111         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1112
1113         enable_clocks(0);
1114 }
1115
1116 static void _dispc_set_fir(enum omap_plane plane,
1117                                 int hinc, int vinc,
1118                                 enum omap_color_component color_comp)
1119 {
1120         u32 val;
1121
1122         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1123                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1124
1125                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1126                                         &hinc_start, &hinc_end);
1127                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1128                                         &vinc_start, &vinc_end);
1129                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1130                                 FLD_VAL(hinc, hinc_start, hinc_end);
1131
1132                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1133         } else {
1134                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1135                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1136         }
1137 }
1138
1139 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1140 {
1141         u32 val;
1142         u8 hor_start, hor_end, vert_start, vert_end;
1143
1144         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1145         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1146
1147         val = FLD_VAL(vaccu, vert_start, vert_end) |
1148                         FLD_VAL(haccu, hor_start, hor_end);
1149
1150         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1151 }
1152
1153 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1154 {
1155         u32 val;
1156         u8 hor_start, hor_end, vert_start, vert_end;
1157
1158         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1159         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1160
1161         val = FLD_VAL(vaccu, vert_start, vert_end) |
1162                         FLD_VAL(haccu, hor_start, hor_end);
1163
1164         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1165 }
1166
1167 static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
1168 {
1169         u32 val;
1170
1171         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1172         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1173 }
1174
1175 static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
1176 {
1177         u32 val;
1178
1179         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1180         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1181 }
1182
1183 static void _dispc_set_scale_param(enum omap_plane plane,
1184                 u16 orig_width, u16 orig_height,
1185                 u16 out_width, u16 out_height,
1186                 bool five_taps, u8 rotation,
1187                 enum omap_color_component color_comp)
1188 {
1189         int fir_hinc, fir_vinc;
1190         int hscaleup, vscaleup;
1191
1192         hscaleup = orig_width <= out_width;
1193         vscaleup = orig_height <= out_height;
1194
1195         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
1196
1197         fir_hinc = 1024 * orig_width / out_width;
1198         fir_vinc = 1024 * orig_height / out_height;
1199
1200         _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1201 }
1202
1203 static void _dispc_set_scaling_common(enum omap_plane plane,
1204                 u16 orig_width, u16 orig_height,
1205                 u16 out_width, u16 out_height,
1206                 bool ilace, bool five_taps,
1207                 bool fieldmode, enum omap_color_mode color_mode,
1208                 u8 rotation)
1209 {
1210         int accu0 = 0;
1211         int accu1 = 0;
1212         u32 l;
1213
1214         _dispc_set_scale_param(plane, orig_width, orig_height,
1215                                 out_width, out_height, five_taps,
1216                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1217         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1218
1219         /* RESIZEENABLE and VERTICALTAPS */
1220         l &= ~((0x3 << 5) | (0x1 << 21));
1221         l |= (orig_width != out_width) ? (1 << 5) : 0;
1222         l |= (orig_height != out_height) ? (1 << 6) : 0;
1223         l |= five_taps ? (1 << 21) : 0;
1224
1225         /* VRESIZECONF and HRESIZECONF */
1226         if (dss_has_feature(FEAT_RESIZECONF)) {
1227                 l &= ~(0x3 << 7);
1228                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1229                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1230         }
1231
1232         /* LINEBUFFERSPLIT */
1233         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1234                 l &= ~(0x1 << 22);
1235                 l |= five_taps ? (1 << 22) : 0;
1236         }
1237
1238         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1239
1240         /*
1241          * field 0 = even field = bottom field
1242          * field 1 = odd field = top field
1243          */
1244         if (ilace && !fieldmode) {
1245                 accu1 = 0;
1246                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1247                 if (accu0 >= 1024/2) {
1248                         accu1 = 1024/2;
1249                         accu0 -= accu1;
1250                 }
1251         }
1252
1253         _dispc_set_vid_accu0(plane, 0, accu0);
1254         _dispc_set_vid_accu1(plane, 0, accu1);
1255 }
1256
1257 static void _dispc_set_scaling_uv(enum omap_plane plane,
1258                 u16 orig_width, u16 orig_height,
1259                 u16 out_width, u16 out_height,
1260                 bool ilace, bool five_taps,
1261                 bool fieldmode, enum omap_color_mode color_mode,
1262                 u8 rotation)
1263 {
1264         int scale_x = out_width != orig_width;
1265         int scale_y = out_height != orig_height;
1266
1267         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1268                 return;
1269         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1270                         color_mode != OMAP_DSS_COLOR_UYVY &&
1271                         color_mode != OMAP_DSS_COLOR_NV12)) {
1272                 /* reset chroma resampling for RGB formats  */
1273                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1274                 return;
1275         }
1276         switch (color_mode) {
1277         case OMAP_DSS_COLOR_NV12:
1278                 /* UV is subsampled by 2 vertically*/
1279                 orig_height >>= 1;
1280                 /* UV is subsampled by 2 horz.*/
1281                 orig_width >>= 1;
1282                 break;
1283         case OMAP_DSS_COLOR_YUV2:
1284         case OMAP_DSS_COLOR_UYVY:
1285                 /*For YUV422 with 90/270 rotation,
1286                  *we don't upsample chroma
1287                  */
1288                 if (rotation == OMAP_DSS_ROT_0 ||
1289                         rotation == OMAP_DSS_ROT_180)
1290                         /* UV is subsampled by 2 hrz*/
1291                         orig_width >>= 1;
1292                 /* must use FIR for YUV422 if rotated */
1293                 if (rotation != OMAP_DSS_ROT_0)
1294                         scale_x = scale_y = true;
1295                 break;
1296         default:
1297                 BUG();
1298         }
1299
1300         if (out_width != orig_width)
1301                 scale_x = true;
1302         if (out_height != orig_height)
1303                 scale_y = true;
1304
1305         _dispc_set_scale_param(plane, orig_width, orig_height,
1306                         out_width, out_height, five_taps,
1307                                 rotation, DISPC_COLOR_COMPONENT_UV);
1308
1309         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1310                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1311         /* set H scaling */
1312         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1313         /* set V scaling */
1314         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1315
1316         _dispc_set_vid_accu2_0(plane, 0x80, 0);
1317         _dispc_set_vid_accu2_1(plane, 0x80, 0);
1318 }
1319
1320 static void _dispc_set_scaling(enum omap_plane plane,
1321                 u16 orig_width, u16 orig_height,
1322                 u16 out_width, u16 out_height,
1323                 bool ilace, bool five_taps,
1324                 bool fieldmode, enum omap_color_mode color_mode,
1325                 u8 rotation)
1326 {
1327         BUG_ON(plane == OMAP_DSS_GFX);
1328
1329         _dispc_set_scaling_common(plane,
1330                         orig_width, orig_height,
1331                         out_width, out_height,
1332                         ilace, five_taps,
1333                         fieldmode, color_mode,
1334                         rotation);
1335
1336         _dispc_set_scaling_uv(plane,
1337                 orig_width, orig_height,
1338                 out_width, out_height,
1339                 ilace, five_taps,
1340                 fieldmode, color_mode,
1341                 rotation);
1342 }
1343
1344 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1345                 bool mirroring, enum omap_color_mode color_mode)
1346 {
1347         bool row_repeat = false;
1348         int vidrot = 0;
1349
1350         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1351                         color_mode == OMAP_DSS_COLOR_UYVY) {
1352
1353                 if (mirroring) {
1354                         switch (rotation) {
1355                         case OMAP_DSS_ROT_0:
1356                                 vidrot = 2;
1357                                 break;
1358                         case OMAP_DSS_ROT_90:
1359                                 vidrot = 1;
1360                                 break;
1361                         case OMAP_DSS_ROT_180:
1362                                 vidrot = 0;
1363                                 break;
1364                         case OMAP_DSS_ROT_270:
1365                                 vidrot = 3;
1366                                 break;
1367                         }
1368                 } else {
1369                         switch (rotation) {
1370                         case OMAP_DSS_ROT_0:
1371                                 vidrot = 0;
1372                                 break;
1373                         case OMAP_DSS_ROT_90:
1374                                 vidrot = 1;
1375                                 break;
1376                         case OMAP_DSS_ROT_180:
1377                                 vidrot = 2;
1378                                 break;
1379                         case OMAP_DSS_ROT_270:
1380                                 vidrot = 3;
1381                                 break;
1382                         }
1383                 }
1384
1385                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1386                         row_repeat = true;
1387                 else
1388                         row_repeat = false;
1389         }
1390
1391         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1392         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1393                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1394                         row_repeat ? 1 : 0, 18, 18);
1395 }
1396
1397 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1398 {
1399         switch (color_mode) {
1400         case OMAP_DSS_COLOR_CLUT1:
1401                 return 1;
1402         case OMAP_DSS_COLOR_CLUT2:
1403                 return 2;
1404         case OMAP_DSS_COLOR_CLUT4:
1405                 return 4;
1406         case OMAP_DSS_COLOR_CLUT8:
1407         case OMAP_DSS_COLOR_NV12:
1408                 return 8;
1409         case OMAP_DSS_COLOR_RGB12U:
1410         case OMAP_DSS_COLOR_RGB16:
1411         case OMAP_DSS_COLOR_ARGB16:
1412         case OMAP_DSS_COLOR_YUV2:
1413         case OMAP_DSS_COLOR_UYVY:
1414         case OMAP_DSS_COLOR_RGBA16:
1415         case OMAP_DSS_COLOR_RGBX16:
1416         case OMAP_DSS_COLOR_ARGB16_1555:
1417         case OMAP_DSS_COLOR_XRGB16_1555:
1418                 return 16;
1419         case OMAP_DSS_COLOR_RGB24P:
1420                 return 24;
1421         case OMAP_DSS_COLOR_RGB24U:
1422         case OMAP_DSS_COLOR_ARGB32:
1423         case OMAP_DSS_COLOR_RGBA32:
1424         case OMAP_DSS_COLOR_RGBX32:
1425                 return 32;
1426         default:
1427                 BUG();
1428         }
1429 }
1430
1431 static s32 pixinc(int pixels, u8 ps)
1432 {
1433         if (pixels == 1)
1434                 return 1;
1435         else if (pixels > 1)
1436                 return 1 + (pixels - 1) * ps;
1437         else if (pixels < 0)
1438                 return 1 - (-pixels + 1) * ps;
1439         else
1440                 BUG();
1441 }
1442
1443 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1444                 u16 screen_width,
1445                 u16 width, u16 height,
1446                 enum omap_color_mode color_mode, bool fieldmode,
1447                 unsigned int field_offset,
1448                 unsigned *offset0, unsigned *offset1,
1449                 s32 *row_inc, s32 *pix_inc)
1450 {
1451         u8 ps;
1452
1453         /* FIXME CLUT formats */
1454         switch (color_mode) {
1455         case OMAP_DSS_COLOR_CLUT1:
1456         case OMAP_DSS_COLOR_CLUT2:
1457         case OMAP_DSS_COLOR_CLUT4:
1458         case OMAP_DSS_COLOR_CLUT8:
1459                 BUG();
1460                 return;
1461         case OMAP_DSS_COLOR_YUV2:
1462         case OMAP_DSS_COLOR_UYVY:
1463                 ps = 4;
1464                 break;
1465         default:
1466                 ps = color_mode_to_bpp(color_mode) / 8;
1467                 break;
1468         }
1469
1470         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1471                         width, height);
1472
1473         /*
1474          * field 0 = even field = bottom field
1475          * field 1 = odd field = top field
1476          */
1477         switch (rotation + mirror * 4) {
1478         case OMAP_DSS_ROT_0:
1479         case OMAP_DSS_ROT_180:
1480                 /*
1481                  * If the pixel format is YUV or UYVY divide the width
1482                  * of the image by 2 for 0 and 180 degree rotation.
1483                  */
1484                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1485                         color_mode == OMAP_DSS_COLOR_UYVY)
1486                         width = width >> 1;
1487         case OMAP_DSS_ROT_90:
1488         case OMAP_DSS_ROT_270:
1489                 *offset1 = 0;
1490                 if (field_offset)
1491                         *offset0 = field_offset * screen_width * ps;
1492                 else
1493                         *offset0 = 0;
1494
1495                 *row_inc = pixinc(1 + (screen_width - width) +
1496                                 (fieldmode ? screen_width : 0),
1497                                 ps);
1498                 *pix_inc = pixinc(1, ps);
1499                 break;
1500
1501         case OMAP_DSS_ROT_0 + 4:
1502         case OMAP_DSS_ROT_180 + 4:
1503                 /* If the pixel format is YUV or UYVY divide the width
1504                  * of the image by 2  for 0 degree and 180 degree
1505                  */
1506                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1507                         color_mode == OMAP_DSS_COLOR_UYVY)
1508                         width = width >> 1;
1509         case OMAP_DSS_ROT_90 + 4:
1510         case OMAP_DSS_ROT_270 + 4:
1511                 *offset1 = 0;
1512                 if (field_offset)
1513                         *offset0 = field_offset * screen_width * ps;
1514                 else
1515                         *offset0 = 0;
1516                 *row_inc = pixinc(1 - (screen_width + width) -
1517                                 (fieldmode ? screen_width : 0),
1518                                 ps);
1519                 *pix_inc = pixinc(1, ps);
1520                 break;
1521
1522         default:
1523                 BUG();
1524         }
1525 }
1526
1527 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1528                 u16 screen_width,
1529                 u16 width, u16 height,
1530                 enum omap_color_mode color_mode, bool fieldmode,
1531                 unsigned int field_offset,
1532                 unsigned *offset0, unsigned *offset1,
1533                 s32 *row_inc, s32 *pix_inc)
1534 {
1535         u8 ps;
1536         u16 fbw, fbh;
1537
1538         /* FIXME CLUT formats */
1539         switch (color_mode) {
1540         case OMAP_DSS_COLOR_CLUT1:
1541         case OMAP_DSS_COLOR_CLUT2:
1542         case OMAP_DSS_COLOR_CLUT4:
1543         case OMAP_DSS_COLOR_CLUT8:
1544                 BUG();
1545                 return;
1546         default:
1547                 ps = color_mode_to_bpp(color_mode) / 8;
1548                 break;
1549         }
1550
1551         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1552                         width, height);
1553
1554         /* width & height are overlay sizes, convert to fb sizes */
1555
1556         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1557                 fbw = width;
1558                 fbh = height;
1559         } else {
1560                 fbw = height;
1561                 fbh = width;
1562         }
1563
1564         /*
1565          * field 0 = even field = bottom field
1566          * field 1 = odd field = top field
1567          */
1568         switch (rotation + mirror * 4) {
1569         case OMAP_DSS_ROT_0:
1570                 *offset1 = 0;
1571                 if (field_offset)
1572                         *offset0 = *offset1 + field_offset * screen_width * ps;
1573                 else
1574                         *offset0 = *offset1;
1575                 *row_inc = pixinc(1 + (screen_width - fbw) +
1576                                 (fieldmode ? screen_width : 0),
1577                                 ps);
1578                 *pix_inc = pixinc(1, ps);
1579                 break;
1580         case OMAP_DSS_ROT_90:
1581                 *offset1 = screen_width * (fbh - 1) * ps;
1582                 if (field_offset)
1583                         *offset0 = *offset1 + field_offset * ps;
1584                 else
1585                         *offset0 = *offset1;
1586                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1587                                 (fieldmode ? 1 : 0), ps);
1588                 *pix_inc = pixinc(-screen_width, ps);
1589                 break;
1590         case OMAP_DSS_ROT_180:
1591                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1592                 if (field_offset)
1593                         *offset0 = *offset1 - field_offset * screen_width * ps;
1594                 else
1595                         *offset0 = *offset1;
1596                 *row_inc = pixinc(-1 -
1597                                 (screen_width - fbw) -
1598                                 (fieldmode ? screen_width : 0),
1599                                 ps);
1600                 *pix_inc = pixinc(-1, ps);
1601                 break;
1602         case OMAP_DSS_ROT_270:
1603                 *offset1 = (fbw - 1) * ps;
1604                 if (field_offset)
1605                         *offset0 = *offset1 - field_offset * ps;
1606                 else
1607                         *offset0 = *offset1;
1608                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1609                                 (fieldmode ? 1 : 0), ps);
1610                 *pix_inc = pixinc(screen_width, ps);
1611                 break;
1612
1613         /* mirroring */
1614         case OMAP_DSS_ROT_0 + 4:
1615                 *offset1 = (fbw - 1) * ps;
1616                 if (field_offset)
1617                         *offset0 = *offset1 + field_offset * screen_width * ps;
1618                 else
1619                         *offset0 = *offset1;
1620                 *row_inc = pixinc(screen_width * 2 - 1 +
1621                                 (fieldmode ? screen_width : 0),
1622                                 ps);
1623                 *pix_inc = pixinc(-1, ps);
1624                 break;
1625
1626         case OMAP_DSS_ROT_90 + 4:
1627                 *offset1 = 0;
1628                 if (field_offset)
1629                         *offset0 = *offset1 + field_offset * ps;
1630                 else
1631                         *offset0 = *offset1;
1632                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1633                                 (fieldmode ? 1 : 0),
1634                                 ps);
1635                 *pix_inc = pixinc(screen_width, ps);
1636                 break;
1637
1638         case OMAP_DSS_ROT_180 + 4:
1639                 *offset1 = screen_width * (fbh - 1) * ps;
1640                 if (field_offset)
1641                         *offset0 = *offset1 - field_offset * screen_width * ps;
1642                 else
1643                         *offset0 = *offset1;
1644                 *row_inc = pixinc(1 - screen_width * 2 -
1645                                 (fieldmode ? screen_width : 0),
1646                                 ps);
1647                 *pix_inc = pixinc(1, ps);
1648                 break;
1649
1650         case OMAP_DSS_ROT_270 + 4:
1651                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1652                 if (field_offset)
1653                         *offset0 = *offset1 - field_offset * ps;
1654                 else
1655                         *offset0 = *offset1;
1656                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1657                                 (fieldmode ? 1 : 0),
1658                                 ps);
1659                 *pix_inc = pixinc(-screen_width, ps);
1660                 break;
1661
1662         default:
1663                 BUG();
1664         }
1665 }
1666
1667 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1668                 u16 height, u16 out_width, u16 out_height,
1669                 enum omap_color_mode color_mode)
1670 {
1671         u32 fclk = 0;
1672         /* FIXME venc pclk? */
1673         u64 tmp, pclk = dispc_pclk_rate(channel);
1674
1675         if (height > out_height) {
1676                 /* FIXME get real display PPL */
1677                 unsigned int ppl = 800;
1678
1679                 tmp = pclk * height * out_width;
1680                 do_div(tmp, 2 * out_height * ppl);
1681                 fclk = tmp;
1682
1683                 if (height > 2 * out_height) {
1684                         if (ppl == out_width)
1685                                 return 0;
1686
1687                         tmp = pclk * (height - 2 * out_height) * out_width;
1688                         do_div(tmp, 2 * out_height * (ppl - out_width));
1689                         fclk = max(fclk, (u32) tmp);
1690                 }
1691         }
1692
1693         if (width > out_width) {
1694                 tmp = pclk * width;
1695                 do_div(tmp, out_width);
1696                 fclk = max(fclk, (u32) tmp);
1697
1698                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1699                         fclk <<= 1;
1700         }
1701
1702         return fclk;
1703 }
1704
1705 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1706                 u16 height, u16 out_width, u16 out_height)
1707 {
1708         unsigned int hf, vf;
1709
1710         /*
1711          * FIXME how to determine the 'A' factor
1712          * for the no downscaling case ?
1713          */
1714
1715         if (width > 3 * out_width)
1716                 hf = 4;
1717         else if (width > 2 * out_width)
1718                 hf = 3;
1719         else if (width > out_width)
1720                 hf = 2;
1721         else
1722                 hf = 1;
1723
1724         if (height > out_height)
1725                 vf = 2;
1726         else
1727                 vf = 1;
1728
1729         /* FIXME venc pclk? */
1730         return dispc_pclk_rate(channel) * vf * hf;
1731 }
1732
1733 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1734 {
1735         enable_clocks(1);
1736         _dispc_set_channel_out(plane, channel_out);
1737         enable_clocks(0);
1738 }
1739
1740 static int _dispc_setup_plane(enum omap_plane plane,
1741                 u32 paddr, u16 screen_width,
1742                 u16 pos_x, u16 pos_y,
1743                 u16 width, u16 height,
1744                 u16 out_width, u16 out_height,
1745                 enum omap_color_mode color_mode,
1746                 bool ilace,
1747                 enum omap_dss_rotation_type rotation_type,
1748                 u8 rotation, int mirror,
1749                 u8 global_alpha, u8 pre_mult_alpha,
1750                 enum omap_channel channel, u32 puv_addr)
1751 {
1752         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1753         bool five_taps = 0;
1754         bool fieldmode = 0;
1755         int cconv = 0;
1756         unsigned offset0, offset1;
1757         s32 row_inc;
1758         s32 pix_inc;
1759         u16 frame_height = height;
1760         unsigned int field_offset = 0;
1761
1762         if (paddr == 0)
1763                 return -EINVAL;
1764
1765         if (ilace && height == out_height)
1766                 fieldmode = 1;
1767
1768         if (ilace) {
1769                 if (fieldmode)
1770                         height /= 2;
1771                 pos_y /= 2;
1772                 out_height /= 2;
1773
1774                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1775                                 "out_height %d\n",
1776                                 height, pos_y, out_height);
1777         }
1778
1779         if (!dss_feat_color_mode_supported(plane, color_mode))
1780                 return -EINVAL;
1781
1782         if (plane == OMAP_DSS_GFX) {
1783                 if (width != out_width || height != out_height)
1784                         return -EINVAL;
1785         } else {
1786                 /* video plane */
1787
1788                 unsigned long fclk = 0;
1789
1790                 if (out_width < width / maxdownscale ||
1791                    out_width > width * 8)
1792                         return -EINVAL;
1793
1794                 if (out_height < height / maxdownscale ||
1795                    out_height > height * 8)
1796                         return -EINVAL;
1797
1798                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1799                         color_mode == OMAP_DSS_COLOR_UYVY ||
1800                         color_mode == OMAP_DSS_COLOR_NV12)
1801                         cconv = 1;
1802
1803                 /* Must use 5-tap filter? */
1804                 five_taps = height > out_height * 2;
1805
1806                 if (!five_taps) {
1807                         fclk = calc_fclk(channel, width, height, out_width,
1808                                         out_height);
1809
1810                         /* Try 5-tap filter if 3-tap fclk is too high */
1811                         if (cpu_is_omap34xx() && height > out_height &&
1812                                         fclk > dispc_fclk_rate())
1813                                 five_taps = true;
1814                 }
1815
1816                 if (width > (2048 >> five_taps)) {
1817                         DSSERR("failed to set up scaling, fclk too low\n");
1818                         return -EINVAL;
1819                 }
1820
1821                 if (five_taps)
1822                         fclk = calc_fclk_five_taps(channel, width, height,
1823                                         out_width, out_height, color_mode);
1824
1825                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1826                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1827
1828                 if (!fclk || fclk > dispc_fclk_rate()) {
1829                         DSSERR("failed to set up scaling, "
1830                                         "required fclk rate = %lu Hz, "
1831                                         "current fclk rate = %lu Hz\n",
1832                                         fclk, dispc_fclk_rate());
1833                         return -EINVAL;
1834                 }
1835         }
1836
1837         if (ilace && !fieldmode) {
1838                 /*
1839                  * when downscaling the bottom field may have to start several
1840                  * source lines below the top field. Unfortunately ACCUI
1841                  * registers will only hold the fractional part of the offset
1842                  * so the integer part must be added to the base address of the
1843                  * bottom field.
1844                  */
1845                 if (!height || height == out_height)
1846                         field_offset = 0;
1847                 else
1848                         field_offset = height / out_height / 2;
1849         }
1850
1851         /* Fields are independent but interleaved in memory. */
1852         if (fieldmode)
1853                 field_offset = 1;
1854
1855         if (rotation_type == OMAP_DSS_ROT_DMA)
1856                 calc_dma_rotation_offset(rotation, mirror,
1857                                 screen_width, width, frame_height, color_mode,
1858                                 fieldmode, field_offset,
1859                                 &offset0, &offset1, &row_inc, &pix_inc);
1860         else
1861                 calc_vrfb_rotation_offset(rotation, mirror,
1862                                 screen_width, width, frame_height, color_mode,
1863                                 fieldmode, field_offset,
1864                                 &offset0, &offset1, &row_inc, &pix_inc);
1865
1866         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1867                         offset0, offset1, row_inc, pix_inc);
1868
1869         _dispc_set_color_mode(plane, color_mode);
1870
1871         _dispc_set_plane_ba0(plane, paddr + offset0);
1872         _dispc_set_plane_ba1(plane, paddr + offset1);
1873
1874         if (OMAP_DSS_COLOR_NV12 == color_mode) {
1875                 _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
1876                 _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
1877         }
1878
1879
1880         _dispc_set_row_inc(plane, row_inc);
1881         _dispc_set_pix_inc(plane, pix_inc);
1882
1883         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1884                         out_width, out_height);
1885
1886         _dispc_set_plane_pos(plane, pos_x, pos_y);
1887
1888         _dispc_set_pic_size(plane, width, height);
1889
1890         if (plane != OMAP_DSS_GFX) {
1891                 _dispc_set_scaling(plane, width, height,
1892                                    out_width, out_height,
1893                                    ilace, five_taps, fieldmode,
1894                                    color_mode, rotation);
1895                 _dispc_set_vid_size(plane, out_width, out_height);
1896                 _dispc_set_vid_color_conv(plane, cconv);
1897         }
1898
1899         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1900
1901         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1902         _dispc_setup_global_alpha(plane, global_alpha);
1903
1904         return 0;
1905 }
1906
1907 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1908 {
1909         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1910 }
1911
1912 static void dispc_disable_isr(void *data, u32 mask)
1913 {
1914         struct completion *compl = data;
1915         complete(compl);
1916 }
1917
1918 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1919 {
1920         if (channel == OMAP_DSS_CHANNEL_LCD2)
1921                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1922         else
1923                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1924 }
1925
1926 static void dispc_enable_lcd_out(enum omap_channel channel, bool enable)
1927 {
1928         struct completion frame_done_completion;
1929         bool is_on;
1930         int r;
1931         u32 irq;
1932
1933         enable_clocks(1);
1934
1935         /* When we disable LCD output, we need to wait until frame is done.
1936          * Otherwise the DSS is still working, and turning off the clocks
1937          * prevents DSS from going to OFF mode */
1938         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1939                         REG_GET(DISPC_CONTROL2, 0, 0) :
1940                         REG_GET(DISPC_CONTROL, 0, 0);
1941
1942         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1943                         DISPC_IRQ_FRAMEDONE;
1944
1945         if (!enable && is_on) {
1946                 init_completion(&frame_done_completion);
1947
1948                 r = omap_dispc_register_isr(dispc_disable_isr,
1949                                 &frame_done_completion, irq);
1950
1951                 if (r)
1952                         DSSERR("failed to register FRAMEDONE isr\n");
1953         }
1954
1955         _enable_lcd_out(channel, enable);
1956
1957         if (!enable && is_on) {
1958                 if (!wait_for_completion_timeout(&frame_done_completion,
1959                                         msecs_to_jiffies(100)))
1960                         DSSERR("timeout waiting for FRAME DONE\n");
1961
1962                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1963                                 &frame_done_completion, irq);
1964
1965                 if (r)
1966                         DSSERR("failed to unregister FRAMEDONE isr\n");
1967         }
1968
1969         enable_clocks(0);
1970 }
1971
1972 static void _enable_digit_out(bool enable)
1973 {
1974         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1975 }
1976
1977 static void dispc_enable_digit_out(bool enable)
1978 {
1979         struct completion frame_done_completion;
1980         int r;
1981
1982         enable_clocks(1);
1983
1984         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1985                 enable_clocks(0);
1986                 return;
1987         }
1988
1989         if (enable) {
1990                 unsigned long flags;
1991                 /* When we enable digit output, we'll get an extra digit
1992                  * sync lost interrupt, that we need to ignore */
1993                 spin_lock_irqsave(&dispc.irq_lock, flags);
1994                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1995                 _omap_dispc_set_irqs();
1996                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1997         }
1998
1999         /* When we disable digit output, we need to wait until fields are done.
2000          * Otherwise the DSS is still working, and turning off the clocks
2001          * prevents DSS from going to OFF mode. And when enabling, we need to
2002          * wait for the extra sync losts */
2003         init_completion(&frame_done_completion);
2004
2005         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2006                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2007         if (r)
2008                 DSSERR("failed to register EVSYNC isr\n");
2009
2010         _enable_digit_out(enable);
2011
2012         /* XXX I understand from TRM that we should only wait for the
2013          * current field to complete. But it seems we have to wait
2014          * for both fields */
2015         if (!wait_for_completion_timeout(&frame_done_completion,
2016                                 msecs_to_jiffies(100)))
2017                 DSSERR("timeout waiting for EVSYNC\n");
2018
2019         if (!wait_for_completion_timeout(&frame_done_completion,
2020                                 msecs_to_jiffies(100)))
2021                 DSSERR("timeout waiting for EVSYNC\n");
2022
2023         r = omap_dispc_unregister_isr(dispc_disable_isr,
2024                         &frame_done_completion,
2025                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
2026         if (r)
2027                 DSSERR("failed to unregister EVSYNC isr\n");
2028
2029         if (enable) {
2030                 unsigned long flags;
2031                 spin_lock_irqsave(&dispc.irq_lock, flags);
2032                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
2033                 if (dss_has_feature(FEAT_MGR_LCD2))
2034                         dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
2035                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2036                 _omap_dispc_set_irqs();
2037                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2038         }
2039
2040         enable_clocks(0);
2041 }
2042
2043 bool dispc_is_channel_enabled(enum omap_channel channel)
2044 {
2045         if (channel == OMAP_DSS_CHANNEL_LCD)
2046                 return !!REG_GET(DISPC_CONTROL, 0, 0);
2047         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2048                 return !!REG_GET(DISPC_CONTROL, 1, 1);
2049         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2050                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2051         else
2052                 BUG();
2053 }
2054
2055 void dispc_enable_channel(enum omap_channel channel, bool enable)
2056 {
2057         if (channel == OMAP_DSS_CHANNEL_LCD ||
2058                         channel == OMAP_DSS_CHANNEL_LCD2)
2059                 dispc_enable_lcd_out(channel, enable);
2060         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2061                 dispc_enable_digit_out(enable);
2062         else
2063                 BUG();
2064 }
2065
2066 void dispc_lcd_enable_signal_polarity(bool act_high)
2067 {
2068         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2069                 return;
2070
2071         enable_clocks(1);
2072         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2073         enable_clocks(0);
2074 }
2075
2076 void dispc_lcd_enable_signal(bool enable)
2077 {
2078         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2079                 return;
2080
2081         enable_clocks(1);
2082         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2083         enable_clocks(0);
2084 }
2085
2086 void dispc_pck_free_enable(bool enable)
2087 {
2088         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2089                 return;
2090
2091         enable_clocks(1);
2092         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2093         enable_clocks(0);
2094 }
2095
2096 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
2097 {
2098         enable_clocks(1);
2099         if (channel == OMAP_DSS_CHANNEL_LCD2)
2100                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2101         else
2102                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2103         enable_clocks(0);
2104 }
2105
2106
2107 void dispc_set_lcd_display_type(enum omap_channel channel,
2108                 enum omap_lcd_display_type type)
2109 {
2110         int mode;
2111
2112         switch (type) {
2113         case OMAP_DSS_LCD_DISPLAY_STN:
2114                 mode = 0;
2115                 break;
2116
2117         case OMAP_DSS_LCD_DISPLAY_TFT:
2118                 mode = 1;
2119                 break;
2120
2121         default:
2122                 BUG();
2123                 return;
2124         }
2125
2126         enable_clocks(1);
2127         if (channel == OMAP_DSS_CHANNEL_LCD2)
2128                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2129         else
2130                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2131         enable_clocks(0);
2132 }
2133
2134 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2135 {
2136         enable_clocks(1);
2137         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2138         enable_clocks(0);
2139 }
2140
2141
2142 void dispc_set_default_color(enum omap_channel channel, u32 color)
2143 {
2144         enable_clocks(1);
2145         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2146         enable_clocks(0);
2147 }
2148
2149 u32 dispc_get_default_color(enum omap_channel channel)
2150 {
2151         u32 l;
2152
2153         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2154                 channel != OMAP_DSS_CHANNEL_LCD &&
2155                 channel != OMAP_DSS_CHANNEL_LCD2);
2156
2157         enable_clocks(1);
2158         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2159         enable_clocks(0);
2160
2161         return l;
2162 }
2163
2164 void dispc_set_trans_key(enum omap_channel ch,
2165                 enum omap_dss_trans_key_type type,
2166                 u32 trans_key)
2167 {
2168         enable_clocks(1);
2169         if (ch == OMAP_DSS_CHANNEL_LCD)
2170                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2171         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2172                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2173         else /* OMAP_DSS_CHANNEL_LCD2 */
2174                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2175
2176         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2177         enable_clocks(0);
2178 }
2179
2180 void dispc_get_trans_key(enum omap_channel ch,
2181                 enum omap_dss_trans_key_type *type,
2182                 u32 *trans_key)
2183 {
2184         enable_clocks(1);
2185         if (type) {
2186                 if (ch == OMAP_DSS_CHANNEL_LCD)
2187                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2188                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2189                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2190                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2191                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2192                 else
2193                         BUG();
2194         }
2195
2196         if (trans_key)
2197                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2198         enable_clocks(0);
2199 }
2200
2201 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
2202 {
2203         enable_clocks(1);
2204         if (ch == OMAP_DSS_CHANNEL_LCD)
2205                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2206         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2207                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2208         else /* OMAP_DSS_CHANNEL_LCD2 */
2209                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2210         enable_clocks(0);
2211 }
2212 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2213 {
2214         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2215                 return;
2216
2217         enable_clocks(1);
2218         if (ch == OMAP_DSS_CHANNEL_LCD)
2219                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2220         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2221                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2222         else /* OMAP_DSS_CHANNEL_LCD2 */
2223                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2224         enable_clocks(0);
2225 }
2226 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2227 {
2228         bool enabled;
2229
2230         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2231                 return false;
2232
2233         enable_clocks(1);
2234         if (ch == OMAP_DSS_CHANNEL_LCD)
2235                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2236         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2237                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2238         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2239                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2240         else
2241                 BUG();
2242         enable_clocks(0);
2243
2244         return enabled;
2245 }
2246
2247
2248 bool dispc_trans_key_enabled(enum omap_channel ch)
2249 {
2250         bool enabled;
2251
2252         enable_clocks(1);
2253         if (ch == OMAP_DSS_CHANNEL_LCD)
2254                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2255         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2256                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2257         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2258                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2259         else
2260                 BUG();
2261         enable_clocks(0);
2262
2263         return enabled;
2264 }
2265
2266
2267 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2268 {
2269         int code;
2270
2271         switch (data_lines) {
2272         case 12:
2273                 code = 0;
2274                 break;
2275         case 16:
2276                 code = 1;
2277                 break;
2278         case 18:
2279                 code = 2;
2280                 break;
2281         case 24:
2282                 code = 3;
2283                 break;
2284         default:
2285                 BUG();
2286                 return;
2287         }
2288
2289         enable_clocks(1);
2290         if (channel == OMAP_DSS_CHANNEL_LCD2)
2291                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2292         else
2293                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2294         enable_clocks(0);
2295 }
2296
2297 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2298                 enum omap_parallel_interface_mode mode)
2299 {
2300         u32 l;
2301         int stallmode;
2302         int gpout0 = 1;
2303         int gpout1;
2304
2305         switch (mode) {
2306         case OMAP_DSS_PARALLELMODE_BYPASS:
2307                 stallmode = 0;
2308                 gpout1 = 1;
2309                 break;
2310
2311         case OMAP_DSS_PARALLELMODE_RFBI:
2312                 stallmode = 1;
2313                 gpout1 = 0;
2314                 break;
2315
2316         case OMAP_DSS_PARALLELMODE_DSI:
2317                 stallmode = 1;
2318                 gpout1 = 1;
2319                 break;
2320
2321         default:
2322                 BUG();
2323                 return;
2324         }
2325
2326         enable_clocks(1);
2327
2328         if (channel == OMAP_DSS_CHANNEL_LCD2) {
2329                 l = dispc_read_reg(DISPC_CONTROL2);
2330                 l = FLD_MOD(l, stallmode, 11, 11);
2331                 dispc_write_reg(DISPC_CONTROL2, l);
2332         } else {
2333                 l = dispc_read_reg(DISPC_CONTROL);
2334                 l = FLD_MOD(l, stallmode, 11, 11);
2335                 l = FLD_MOD(l, gpout0, 15, 15);
2336                 l = FLD_MOD(l, gpout1, 16, 16);
2337                 dispc_write_reg(DISPC_CONTROL, l);
2338         }
2339
2340         enable_clocks(0);
2341 }
2342
2343 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2344                 int vsw, int vfp, int vbp)
2345 {
2346         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2347                 if (hsw < 1 || hsw > 64 ||
2348                                 hfp < 1 || hfp > 256 ||
2349                                 hbp < 1 || hbp > 256 ||
2350                                 vsw < 1 || vsw > 64 ||
2351                                 vfp < 0 || vfp > 255 ||
2352                                 vbp < 0 || vbp > 255)
2353                         return false;
2354         } else {
2355                 if (hsw < 1 || hsw > 256 ||
2356                                 hfp < 1 || hfp > 4096 ||
2357                                 hbp < 1 || hbp > 4096 ||
2358                                 vsw < 1 || vsw > 256 ||
2359                                 vfp < 0 || vfp > 4095 ||
2360                                 vbp < 0 || vbp > 4095)
2361                         return false;
2362         }
2363
2364         return true;
2365 }
2366
2367 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2368 {
2369         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2370                         timings->hbp, timings->vsw,
2371                         timings->vfp, timings->vbp);
2372 }
2373
2374 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2375                 int hfp, int hbp, int vsw, int vfp, int vbp)
2376 {
2377         u32 timing_h, timing_v;
2378
2379         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2380                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2381                         FLD_VAL(hbp-1, 27, 20);
2382
2383                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2384                         FLD_VAL(vbp, 27, 20);
2385         } else {
2386                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2387                         FLD_VAL(hbp-1, 31, 20);
2388
2389                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2390                         FLD_VAL(vbp, 31, 20);
2391         }
2392
2393         enable_clocks(1);
2394         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2395         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2396         enable_clocks(0);
2397 }
2398
2399 /* change name to mode? */
2400 void dispc_set_lcd_timings(enum omap_channel channel,
2401                 struct omap_video_timings *timings)
2402 {
2403         unsigned xtot, ytot;
2404         unsigned long ht, vt;
2405
2406         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2407                                 timings->hbp, timings->vsw,
2408                                 timings->vfp, timings->vbp))
2409                 BUG();
2410
2411         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2412                         timings->hbp, timings->vsw, timings->vfp,
2413                         timings->vbp);
2414
2415         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2416
2417         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2418         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2419
2420         ht = (timings->pixel_clock * 1000) / xtot;
2421         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2422
2423         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2424                         timings->y_res);
2425         DSSDBG("pck %u\n", timings->pixel_clock);
2426         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2427                         timings->hsw, timings->hfp, timings->hbp,
2428                         timings->vsw, timings->vfp, timings->vbp);
2429
2430         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2431 }
2432
2433 static void dispc_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2434                 u16 pck_div)
2435 {
2436         BUG_ON(lck_div < 1);
2437         BUG_ON(pck_div < 2);
2438
2439         enable_clocks(1);
2440         dispc_write_reg(DISPC_DIVISORo(channel),
2441                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2442         enable_clocks(0);
2443 }
2444
2445 static void dispc_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2446                 int *pck_div)
2447 {
2448         u32 l;
2449         l = dispc_read_reg(DISPC_DIVISORo(channel));
2450         *lck_div = FLD_GET(l, 23, 16);
2451         *pck_div = FLD_GET(l, 7, 0);
2452 }
2453
2454 unsigned long dispc_fclk_rate(void)
2455 {
2456         struct platform_device *dsidev;
2457         unsigned long r = 0;
2458
2459         switch (dss_get_dispc_clk_source()) {
2460         case OMAP_DSS_CLK_SRC_FCK:
2461                 r = dss_clk_get_rate(DSS_CLK_FCK);
2462                 break;
2463         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2464                 dsidev = dsi_get_dsidev_from_id(0);
2465                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2466                 break;
2467         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2468                 dsidev = dsi_get_dsidev_from_id(1);
2469                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2470                 break;
2471         default:
2472                 BUG();
2473         }
2474
2475         return r;
2476 }
2477
2478 unsigned long dispc_lclk_rate(enum omap_channel channel)
2479 {
2480         struct platform_device *dsidev;
2481         int lcd;
2482         unsigned long r;
2483         u32 l;
2484
2485         l = dispc_read_reg(DISPC_DIVISORo(channel));
2486
2487         lcd = FLD_GET(l, 23, 16);
2488
2489         switch (dss_get_lcd_clk_source(channel)) {
2490         case OMAP_DSS_CLK_SRC_FCK:
2491                 r = dss_clk_get_rate(DSS_CLK_FCK);
2492                 break;
2493         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2494                 dsidev = dsi_get_dsidev_from_id(0);
2495                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2496                 break;
2497         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2498                 dsidev = dsi_get_dsidev_from_id(1);
2499                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2500                 break;
2501         default:
2502                 BUG();
2503         }
2504
2505         return r / lcd;
2506 }
2507
2508 unsigned long dispc_pclk_rate(enum omap_channel channel)
2509 {
2510         int pcd;
2511         unsigned long r;
2512         u32 l;
2513
2514         l = dispc_read_reg(DISPC_DIVISORo(channel));
2515
2516         pcd = FLD_GET(l, 7, 0);
2517
2518         r = dispc_lclk_rate(channel);
2519
2520         return r / pcd;
2521 }
2522
2523 void dispc_dump_clocks(struct seq_file *s)
2524 {
2525         int lcd, pcd;
2526         u32 l;
2527         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2528         enum omap_dss_clk_source lcd_clk_src;
2529
2530         enable_clocks(1);
2531
2532         seq_printf(s, "- DISPC -\n");
2533
2534         seq_printf(s, "dispc fclk source = %s (%s)\n",
2535                         dss_get_generic_clk_source_name(dispc_clk_src),
2536                         dss_feat_get_clk_source_name(dispc_clk_src));
2537
2538         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2539
2540         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2541                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2542                 l = dispc_read_reg(DISPC_DIVISOR);
2543                 lcd = FLD_GET(l, 23, 16);
2544
2545                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2546                                 (dispc_fclk_rate()/lcd), lcd);
2547         }
2548         seq_printf(s, "- LCD1 -\n");
2549
2550         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2551
2552         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2553                 dss_get_generic_clk_source_name(lcd_clk_src),
2554                 dss_feat_get_clk_source_name(lcd_clk_src));
2555
2556         dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2557
2558         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2559                         dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2560         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2561                         dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2562         if (dss_has_feature(FEAT_MGR_LCD2)) {
2563                 seq_printf(s, "- LCD2 -\n");
2564
2565                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2566
2567                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2568                         dss_get_generic_clk_source_name(lcd_clk_src),
2569                         dss_feat_get_clk_source_name(lcd_clk_src));
2570
2571                 dispc_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2572
2573                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2574                                 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2575                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2576                                 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2577         }
2578         enable_clocks(0);
2579 }
2580
2581 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2582 void dispc_dump_irqs(struct seq_file *s)
2583 {
2584         unsigned long flags;
2585         struct dispc_irq_stats stats;
2586
2587         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2588
2589         stats = dispc.irq_stats;
2590         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2591         dispc.irq_stats.last_reset = jiffies;
2592
2593         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2594
2595         seq_printf(s, "period %u ms\n",
2596                         jiffies_to_msecs(jiffies - stats.last_reset));
2597
2598         seq_printf(s, "irqs %d\n", stats.irq_count);
2599 #define PIS(x) \
2600         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2601
2602         PIS(FRAMEDONE);
2603         PIS(VSYNC);
2604         PIS(EVSYNC_EVEN);
2605         PIS(EVSYNC_ODD);
2606         PIS(ACBIAS_COUNT_STAT);
2607         PIS(PROG_LINE_NUM);
2608         PIS(GFX_FIFO_UNDERFLOW);
2609         PIS(GFX_END_WIN);
2610         PIS(PAL_GAMMA_MASK);
2611         PIS(OCP_ERR);
2612         PIS(VID1_FIFO_UNDERFLOW);
2613         PIS(VID1_END_WIN);
2614         PIS(VID2_FIFO_UNDERFLOW);
2615         PIS(VID2_END_WIN);
2616         PIS(SYNC_LOST);
2617         PIS(SYNC_LOST_DIGIT);
2618         PIS(WAKEUP);
2619         if (dss_has_feature(FEAT_MGR_LCD2)) {
2620                 PIS(FRAMEDONE2);
2621                 PIS(VSYNC2);
2622                 PIS(ACBIAS_COUNT_STAT2);
2623                 PIS(SYNC_LOST2);
2624         }
2625 #undef PIS
2626 }
2627 #endif
2628
2629 void dispc_dump_regs(struct seq_file *s)
2630 {
2631 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2632
2633         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
2634
2635         DUMPREG(DISPC_REVISION);
2636         DUMPREG(DISPC_SYSCONFIG);
2637         DUMPREG(DISPC_SYSSTATUS);
2638         DUMPREG(DISPC_IRQSTATUS);
2639         DUMPREG(DISPC_IRQENABLE);
2640         DUMPREG(DISPC_CONTROL);
2641         DUMPREG(DISPC_CONFIG);
2642         DUMPREG(DISPC_CAPABLE);
2643         DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
2644         DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2645         DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
2646         DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
2647         DUMPREG(DISPC_LINE_STATUS);
2648         DUMPREG(DISPC_LINE_NUMBER);
2649         DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
2650         DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
2651         DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
2652         DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
2653         DUMPREG(DISPC_GLOBAL_ALPHA);
2654         DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
2655         DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
2656         if (dss_has_feature(FEAT_MGR_LCD2)) {
2657                 DUMPREG(DISPC_CONTROL2);
2658                 DUMPREG(DISPC_CONFIG2);
2659                 DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
2660                 DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
2661                 DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
2662                 DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
2663                 DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
2664                 DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
2665                 DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
2666         }
2667
2668         DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
2669         DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
2670         DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
2671         DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
2672         DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
2673         DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
2674         DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
2675         DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
2676         DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
2677         DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
2678         DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
2679
2680         DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
2681         DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
2682         DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
2683
2684         DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
2685         DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
2686         DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
2687         if (dss_has_feature(FEAT_MGR_LCD2)) {
2688                 DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
2689                 DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
2690                 DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
2691
2692                 DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
2693                 DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
2694                 DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
2695         }
2696
2697         DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
2698
2699         DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
2700         DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
2701         DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
2702         DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
2703         DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
2704         DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
2705         DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
2706         DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
2707         DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
2708         DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
2709         DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
2710         DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
2711         DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
2712
2713         DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
2714         DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
2715         DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
2716         DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
2717         DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
2718         DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
2719         DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
2720         DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
2721         DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
2722         DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
2723         DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
2724         DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
2725         DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
2726
2727         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
2728         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
2729         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
2730         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
2731         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
2732         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
2733         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
2734         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
2735         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
2736         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
2737         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
2738         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
2739         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
2740         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
2741         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
2742         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
2743         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
2744         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
2745         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
2746         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
2747         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
2748         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
2749         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
2750         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
2751         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
2752         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
2753         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
2754         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
2755         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
2756
2757         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2758                 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
2759                 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
2760                 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
2761                 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
2762                 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
2763
2764                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
2765                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
2766                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
2767                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
2768                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
2769                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
2770                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
2771                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
2772
2773                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
2774                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
2775                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
2776                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
2777                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
2778                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
2779                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
2780                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
2781
2782                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
2783                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
2784                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
2785                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
2786                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
2787                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
2788                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
2789                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
2790         }
2791         if (dss_has_feature(FEAT_ATTR2))
2792                 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
2793
2794
2795         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
2796         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
2797         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
2798         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
2799         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
2800         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
2801         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
2802         DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
2803         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
2804         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
2805         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
2806         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
2807         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
2808         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
2809         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
2810         DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
2811         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
2812         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
2813         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
2814         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
2815         DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
2816         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
2817         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
2818         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
2819         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
2820         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
2821         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
2822         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
2823         DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
2824
2825         if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2826                 DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
2827                 DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
2828                 DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
2829                 DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
2830                 DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
2831
2832                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
2833                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
2834                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
2835                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
2836                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
2837                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
2838                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
2839                 DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
2840
2841                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
2842                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
2843                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
2844                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
2845                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
2846                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
2847                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
2848                 DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
2849
2850                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
2851                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
2852                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
2853                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
2854                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
2855                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
2856                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
2857                 DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
2858         }
2859         if (dss_has_feature(FEAT_ATTR2))
2860                 DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
2861
2862         DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
2863         DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
2864
2865         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
2866 #undef DUMPREG
2867 }
2868
2869 static void _dispc_set_pol_freq(enum omap_channel channel, bool onoff, bool rf,
2870                 bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi, u8 acb)
2871 {
2872         u32 l = 0;
2873
2874         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2875                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2876
2877         l |= FLD_VAL(onoff, 17, 17);
2878         l |= FLD_VAL(rf, 16, 16);
2879         l |= FLD_VAL(ieo, 15, 15);
2880         l |= FLD_VAL(ipc, 14, 14);
2881         l |= FLD_VAL(ihs, 13, 13);
2882         l |= FLD_VAL(ivs, 12, 12);
2883         l |= FLD_VAL(acbi, 11, 8);
2884         l |= FLD_VAL(acb, 7, 0);
2885
2886         enable_clocks(1);
2887         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2888         enable_clocks(0);
2889 }
2890
2891 void dispc_set_pol_freq(enum omap_channel channel,
2892                 enum omap_panel_config config, u8 acbi, u8 acb)
2893 {
2894         _dispc_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2895                         (config & OMAP_DSS_LCD_RF) != 0,
2896                         (config & OMAP_DSS_LCD_IEO) != 0,
2897                         (config & OMAP_DSS_LCD_IPC) != 0,
2898                         (config & OMAP_DSS_LCD_IHS) != 0,
2899                         (config & OMAP_DSS_LCD_IVS) != 0,
2900                         acbi, acb);
2901 }
2902
2903 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2904 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2905                 struct dispc_clock_info *cinfo)
2906 {
2907         u16 pcd_min = is_tft ? 2 : 3;
2908         unsigned long best_pck;
2909         u16 best_ld, cur_ld;
2910         u16 best_pd, cur_pd;
2911
2912         best_pck = 0;
2913         best_ld = 0;
2914         best_pd = 0;
2915
2916         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2917                 unsigned long lck = fck / cur_ld;
2918
2919                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2920                         unsigned long pck = lck / cur_pd;
2921                         long old_delta = abs(best_pck - req_pck);
2922                         long new_delta = abs(pck - req_pck);
2923
2924                         if (best_pck == 0 || new_delta < old_delta) {
2925                                 best_pck = pck;
2926                                 best_ld = cur_ld;
2927                                 best_pd = cur_pd;
2928
2929                                 if (pck == req_pck)
2930                                         goto found;
2931                         }
2932
2933                         if (pck < req_pck)
2934                                 break;
2935                 }
2936
2937                 if (lck / pcd_min < req_pck)
2938                         break;
2939         }
2940
2941 found:
2942         cinfo->lck_div = best_ld;
2943         cinfo->pck_div = best_pd;
2944         cinfo->lck = fck / cinfo->lck_div;
2945         cinfo->pck = cinfo->lck / cinfo->pck_div;
2946 }
2947
2948 /* calculate clock rates using dividers in cinfo */
2949 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2950                 struct dispc_clock_info *cinfo)
2951 {
2952         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2953                 return -EINVAL;
2954         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2955                 return -EINVAL;
2956
2957         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2958         cinfo->pck = cinfo->lck / cinfo->pck_div;
2959
2960         return 0;
2961 }
2962
2963 int dispc_set_clock_div(enum omap_channel channel,
2964                 struct dispc_clock_info *cinfo)
2965 {
2966         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2967         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2968
2969         dispc_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2970
2971         return 0;
2972 }
2973
2974 int dispc_get_clock_div(enum omap_channel channel,
2975                 struct dispc_clock_info *cinfo)
2976 {
2977         unsigned long fck;
2978
2979         fck = dispc_fclk_rate();
2980
2981         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2982         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2983
2984         cinfo->lck = fck / cinfo->lck_div;
2985         cinfo->pck = cinfo->lck / cinfo->pck_div;
2986
2987         return 0;
2988 }
2989
2990 /* dispc.irq_lock has to be locked by the caller */
2991 static void _omap_dispc_set_irqs(void)
2992 {
2993         u32 mask;
2994         u32 old_mask;
2995         int i;
2996         struct omap_dispc_isr_data *isr_data;
2997
2998         mask = dispc.irq_error_mask;
2999
3000         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3001                 isr_data = &dispc.registered_isr[i];
3002
3003                 if (isr_data->isr == NULL)
3004                         continue;
3005
3006                 mask |= isr_data->mask;
3007         }
3008
3009         enable_clocks(1);
3010
3011         old_mask = dispc_read_reg(DISPC_IRQENABLE);
3012         /* clear the irqstatus for newly enabled irqs */
3013         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3014
3015         dispc_write_reg(DISPC_IRQENABLE, mask);
3016
3017         enable_clocks(0);
3018 }
3019
3020 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3021 {
3022         int i;
3023         int ret;
3024         unsigned long flags;
3025         struct omap_dispc_isr_data *isr_data;
3026
3027         if (isr == NULL)
3028                 return -EINVAL;
3029
3030         spin_lock_irqsave(&dispc.irq_lock, flags);
3031
3032         /* check for duplicate entry */
3033         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3034                 isr_data = &dispc.registered_isr[i];
3035                 if (isr_data->isr == isr && isr_data->arg == arg &&
3036                                 isr_data->mask == mask) {
3037                         ret = -EINVAL;
3038                         goto err;
3039                 }
3040         }
3041
3042         isr_data = NULL;
3043         ret = -EBUSY;
3044
3045         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3046                 isr_data = &dispc.registered_isr[i];
3047
3048                 if (isr_data->isr != NULL)
3049                         continue;
3050
3051                 isr_data->isr = isr;
3052                 isr_data->arg = arg;
3053                 isr_data->mask = mask;
3054                 ret = 0;
3055
3056                 break;
3057         }
3058
3059         if (ret)
3060                 goto err;
3061
3062         _omap_dispc_set_irqs();
3063
3064         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3065
3066         return 0;
3067 err:
3068         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3069
3070         return ret;
3071 }
3072 EXPORT_SYMBOL(omap_dispc_register_isr);
3073
3074 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3075 {
3076         int i;
3077         unsigned long flags;
3078         int ret = -EINVAL;
3079         struct omap_dispc_isr_data *isr_data;
3080
3081         spin_lock_irqsave(&dispc.irq_lock, flags);
3082
3083         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3084                 isr_data = &dispc.registered_isr[i];
3085                 if (isr_data->isr != isr || isr_data->arg != arg ||
3086                                 isr_data->mask != mask)
3087                         continue;
3088
3089                 /* found the correct isr */
3090
3091                 isr_data->isr = NULL;
3092                 isr_data->arg = NULL;
3093                 isr_data->mask = 0;
3094
3095                 ret = 0;
3096                 break;
3097         }
3098
3099         if (ret == 0)
3100                 _omap_dispc_set_irqs();
3101
3102         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3103
3104         return ret;
3105 }
3106 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3107
3108 #ifdef DEBUG
3109 static void print_irq_status(u32 status)
3110 {
3111         if ((status & dispc.irq_error_mask) == 0)
3112                 return;
3113
3114         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3115
3116 #define PIS(x) \
3117         if (status & DISPC_IRQ_##x) \
3118                 printk(#x " ");
3119         PIS(GFX_FIFO_UNDERFLOW);
3120         PIS(OCP_ERR);
3121         PIS(VID1_FIFO_UNDERFLOW);
3122         PIS(VID2_FIFO_UNDERFLOW);
3123         PIS(SYNC_LOST);
3124         PIS(SYNC_LOST_DIGIT);
3125         if (dss_has_feature(FEAT_MGR_LCD2))
3126                 PIS(SYNC_LOST2);
3127 #undef PIS
3128
3129         printk("\n");
3130 }
3131 #endif
3132
3133 /* Called from dss.c. Note that we don't touch clocks here,
3134  * but we presume they are on because we got an IRQ. However,
3135  * an irq handler may turn the clocks off, so we may not have
3136  * clock later in the function. */
3137 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3138 {
3139         int i;
3140         u32 irqstatus, irqenable;
3141         u32 handledirqs = 0;
3142         u32 unhandled_errors;
3143         struct omap_dispc_isr_data *isr_data;
3144         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3145
3146         spin_lock(&dispc.irq_lock);
3147
3148         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3149         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3150
3151         /* IRQ is not for us */
3152         if (!(irqstatus & irqenable)) {
3153                 spin_unlock(&dispc.irq_lock);
3154                 return IRQ_NONE;
3155         }
3156
3157 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3158         spin_lock(&dispc.irq_stats_lock);
3159         dispc.irq_stats.irq_count++;
3160         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3161         spin_unlock(&dispc.irq_stats_lock);
3162 #endif
3163
3164 #ifdef DEBUG
3165         if (dss_debug)
3166                 print_irq_status(irqstatus);
3167 #endif
3168         /* Ack the interrupt. Do it here before clocks are possibly turned
3169          * off */
3170         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3171         /* flush posted write */
3172         dispc_read_reg(DISPC_IRQSTATUS);
3173
3174         /* make a copy and unlock, so that isrs can unregister
3175          * themselves */
3176         memcpy(registered_isr, dispc.registered_isr,
3177                         sizeof(registered_isr));
3178
3179         spin_unlock(&dispc.irq_lock);
3180
3181         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3182                 isr_data = &registered_isr[i];
3183
3184                 if (!isr_data->isr)
3185                         continue;
3186
3187                 if (isr_data->mask & irqstatus) {
3188                         isr_data->isr(isr_data->arg, irqstatus);
3189                         handledirqs |= isr_data->mask;
3190                 }
3191         }
3192
3193         spin_lock(&dispc.irq_lock);
3194
3195         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3196
3197         if (unhandled_errors) {
3198                 dispc.error_irqs |= unhandled_errors;
3199
3200                 dispc.irq_error_mask &= ~unhandled_errors;
3201                 _omap_dispc_set_irqs();
3202
3203                 schedule_work(&dispc.error_work);
3204         }
3205
3206         spin_unlock(&dispc.irq_lock);
3207
3208         return IRQ_HANDLED;
3209 }
3210
3211 static void dispc_error_worker(struct work_struct *work)
3212 {
3213         int i;
3214         u32 errors;
3215         unsigned long flags;
3216
3217         spin_lock_irqsave(&dispc.irq_lock, flags);
3218         errors = dispc.error_irqs;
3219         dispc.error_irqs = 0;
3220         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3221
3222         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
3223                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
3224                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3225                         struct omap_overlay *ovl;
3226                         ovl = omap_dss_get_overlay(i);
3227
3228                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3229                                 continue;
3230
3231                         if (ovl->id == 0) {
3232                                 dispc_enable_plane(ovl->id, 0);
3233                                 dispc_go(ovl->manager->id);
3234                                 mdelay(50);
3235                                 break;
3236                         }
3237                 }
3238         }
3239
3240         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
3241                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
3242                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3243                         struct omap_overlay *ovl;
3244                         ovl = omap_dss_get_overlay(i);
3245
3246                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3247                                 continue;
3248
3249                         if (ovl->id == 1) {
3250                                 dispc_enable_plane(ovl->id, 0);
3251                                 dispc_go(ovl->manager->id);
3252                                 mdelay(50);
3253                                 break;
3254                         }
3255                 }
3256         }
3257
3258         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
3259                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
3260                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3261                         struct omap_overlay *ovl;
3262                         ovl = omap_dss_get_overlay(i);
3263
3264                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3265                                 continue;
3266
3267                         if (ovl->id == 2) {
3268                                 dispc_enable_plane(ovl->id, 0);
3269                                 dispc_go(ovl->manager->id);
3270                                 mdelay(50);
3271                                 break;
3272                         }
3273                 }
3274         }
3275
3276         if (errors & DISPC_IRQ_SYNC_LOST) {
3277                 struct omap_overlay_manager *manager = NULL;
3278                 bool enable = false;
3279
3280                 DSSERR("SYNC_LOST, disabling LCD\n");
3281
3282                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3283                         struct omap_overlay_manager *mgr;
3284                         mgr = omap_dss_get_overlay_manager(i);
3285
3286                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
3287                                 manager = mgr;
3288                                 enable = mgr->device->state ==
3289                                                 OMAP_DSS_DISPLAY_ACTIVE;
3290                                 mgr->device->driver->disable(mgr->device);
3291                                 break;
3292                         }
3293                 }
3294
3295                 if (manager) {
3296                         struct omap_dss_device *dssdev = manager->device;
3297                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3298                                 struct omap_overlay *ovl;
3299                                 ovl = omap_dss_get_overlay(i);
3300
3301                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3302                                         continue;
3303
3304                                 if (ovl->id != 0 && ovl->manager == manager)
3305                                         dispc_enable_plane(ovl->id, 0);
3306                         }
3307
3308                         dispc_go(manager->id);
3309                         mdelay(50);
3310                         if (enable)
3311                                 dssdev->driver->enable(dssdev);
3312                 }
3313         }
3314
3315         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
3316                 struct omap_overlay_manager *manager = NULL;
3317                 bool enable = false;
3318
3319                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
3320
3321                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3322                         struct omap_overlay_manager *mgr;
3323                         mgr = omap_dss_get_overlay_manager(i);
3324
3325                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
3326                                 manager = mgr;
3327                                 enable = mgr->device->state ==
3328                                                 OMAP_DSS_DISPLAY_ACTIVE;
3329                                 mgr->device->driver->disable(mgr->device);
3330                                 break;
3331                         }
3332                 }
3333
3334                 if (manager) {
3335                         struct omap_dss_device *dssdev = manager->device;
3336                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3337                                 struct omap_overlay *ovl;
3338                                 ovl = omap_dss_get_overlay(i);
3339
3340                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3341                                         continue;
3342
3343                                 if (ovl->id != 0 && ovl->manager == manager)
3344                                         dispc_enable_plane(ovl->id, 0);
3345                         }
3346
3347                         dispc_go(manager->id);
3348                         mdelay(50);
3349                         if (enable)
3350                                 dssdev->driver->enable(dssdev);
3351                 }
3352         }
3353
3354         if (errors & DISPC_IRQ_SYNC_LOST2) {
3355                 struct omap_overlay_manager *manager = NULL;
3356                 bool enable = false;
3357
3358                 DSSERR("SYNC_LOST for LCD2, disabling LCD2\n");
3359
3360                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3361                         struct omap_overlay_manager *mgr;
3362                         mgr = omap_dss_get_overlay_manager(i);
3363
3364                         if (mgr->id == OMAP_DSS_CHANNEL_LCD2) {
3365                                 manager = mgr;
3366                                 enable = mgr->device->state ==
3367                                                 OMAP_DSS_DISPLAY_ACTIVE;
3368                                 mgr->device->driver->disable(mgr->device);
3369                                 break;
3370                         }
3371                 }
3372
3373                 if (manager) {
3374                         struct omap_dss_device *dssdev = manager->device;
3375                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3376                                 struct omap_overlay *ovl;
3377                                 ovl = omap_dss_get_overlay(i);
3378
3379                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
3380                                         continue;
3381
3382                                 if (ovl->id != 0 && ovl->manager == manager)
3383                                         dispc_enable_plane(ovl->id, 0);
3384                         }
3385
3386                         dispc_go(manager->id);
3387                         mdelay(50);
3388                         if (enable)
3389                                 dssdev->driver->enable(dssdev);
3390                 }
3391         }
3392
3393         if (errors & DISPC_IRQ_OCP_ERR) {
3394                 DSSERR("OCP_ERR\n");
3395                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3396                         struct omap_overlay_manager *mgr;
3397                         mgr = omap_dss_get_overlay_manager(i);
3398
3399                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
3400                                 mgr->device->driver->disable(mgr->device);
3401                 }
3402         }
3403
3404         spin_lock_irqsave(&dispc.irq_lock, flags);
3405         dispc.irq_error_mask |= errors;
3406         _omap_dispc_set_irqs();
3407         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3408 }
3409
3410 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3411 {
3412         void dispc_irq_wait_handler(void *data, u32 mask)
3413         {
3414                 complete((struct completion *)data);
3415         }
3416
3417         int r;
3418         DECLARE_COMPLETION_ONSTACK(completion);
3419
3420         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3421                         irqmask);
3422
3423         if (r)
3424                 return r;
3425
3426         timeout = wait_for_completion_timeout(&completion, timeout);
3427
3428         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3429
3430         if (timeout == 0)
3431                 return -ETIMEDOUT;
3432
3433         if (timeout == -ERESTARTSYS)
3434                 return -ERESTARTSYS;
3435
3436         return 0;
3437 }
3438
3439 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3440                 unsigned long timeout)
3441 {
3442         void dispc_irq_wait_handler(void *data, u32 mask)
3443         {
3444                 complete((struct completion *)data);
3445         }
3446
3447         int r;
3448         DECLARE_COMPLETION_ONSTACK(completion);
3449
3450         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3451                         irqmask);
3452
3453         if (r)
3454                 return r;
3455
3456         timeout = wait_for_completion_interruptible_timeout(&completion,
3457                         timeout);
3458
3459         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3460
3461         if (timeout == 0)
3462                 return -ETIMEDOUT;
3463
3464         if (timeout == -ERESTARTSYS)
3465                 return -ERESTARTSYS;
3466
3467         return 0;
3468 }
3469
3470 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3471 void dispc_fake_vsync_irq(void)
3472 {
3473         u32 irqstatus = DISPC_IRQ_VSYNC;
3474         int i;
3475
3476         WARN_ON(!in_interrupt());
3477
3478         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3479                 struct omap_dispc_isr_data *isr_data;
3480                 isr_data = &dispc.registered_isr[i];
3481
3482                 if (!isr_data->isr)
3483                         continue;
3484
3485                 if (isr_data->mask & irqstatus)
3486                         isr_data->isr(isr_data->arg, irqstatus);
3487         }
3488 }
3489 #endif
3490
3491 static void _omap_dispc_initialize_irq(void)
3492 {
3493         unsigned long flags;
3494
3495         spin_lock_irqsave(&dispc.irq_lock, flags);
3496
3497         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3498
3499         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3500         if (dss_has_feature(FEAT_MGR_LCD2))
3501                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3502
3503         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3504          * so clear it */
3505         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3506
3507         _omap_dispc_set_irqs();
3508
3509         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3510 }
3511
3512 void dispc_enable_sidle(void)
3513 {
3514         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3515 }
3516
3517 void dispc_disable_sidle(void)
3518 {
3519         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3520 }
3521
3522 static void _omap_dispc_initial_config(void)
3523 {
3524         u32 l;
3525
3526         l = dispc_read_reg(DISPC_SYSCONFIG);
3527         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3528         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3529         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3530         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3531         dispc_write_reg(DISPC_SYSCONFIG, l);
3532
3533         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3534         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3535                 l = dispc_read_reg(DISPC_DIVISOR);
3536                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3537                 l = FLD_MOD(l, 1, 0, 0);
3538                 l = FLD_MOD(l, 1, 23, 16);
3539                 dispc_write_reg(DISPC_DIVISOR, l);
3540         }
3541
3542         /* FUNCGATED */
3543         if (dss_has_feature(FEAT_FUNCGATED))
3544                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3545
3546         /* L3 firewall setting: enable access to OCM RAM */
3547         /* XXX this should be somewhere in plat-omap */
3548         if (cpu_is_omap24xx())
3549                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3550
3551         _dispc_setup_color_conv_coef();
3552
3553         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3554
3555         dispc_read_plane_fifo_sizes();
3556 }
3557
3558 int dispc_enable_plane(enum omap_plane plane, bool enable)
3559 {
3560         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3561
3562         enable_clocks(1);
3563         _dispc_enable_plane(plane, enable);
3564         enable_clocks(0);
3565
3566         return 0;
3567 }
3568
3569 int dispc_setup_plane(enum omap_plane plane,
3570                        u32 paddr, u16 screen_width,
3571                        u16 pos_x, u16 pos_y,
3572                        u16 width, u16 height,
3573                        u16 out_width, u16 out_height,
3574                        enum omap_color_mode color_mode,
3575                        bool ilace,
3576                        enum omap_dss_rotation_type rotation_type,
3577                        u8 rotation, bool mirror, u8 global_alpha,
3578                        u8 pre_mult_alpha, enum omap_channel channel,
3579                        u32 puv_addr)
3580 {
3581         int r = 0;
3582
3583         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
3584                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
3585                plane, paddr, screen_width, pos_x, pos_y,
3586                width, height,
3587                out_width, out_height,
3588                ilace, color_mode,
3589                rotation, mirror, channel);
3590
3591         enable_clocks(1);
3592
3593         r = _dispc_setup_plane(plane,
3594                            paddr, screen_width,
3595                            pos_x, pos_y,
3596                            width, height,
3597                            out_width, out_height,
3598                            color_mode, ilace,
3599                            rotation_type,
3600                            rotation, mirror,
3601                            global_alpha,
3602                            pre_mult_alpha,
3603                            channel, puv_addr);
3604
3605         enable_clocks(0);
3606
3607         return r;
3608 }
3609
3610 /* DISPC HW IP initialisation */
3611 static int omap_dispchw_probe(struct platform_device *pdev)
3612 {
3613         u32 rev;
3614         int r = 0;
3615         struct resource *dispc_mem;
3616
3617         dispc.pdev = pdev;
3618
3619         spin_lock_init(&dispc.irq_lock);
3620
3621 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3622         spin_lock_init(&dispc.irq_stats_lock);
3623         dispc.irq_stats.last_reset = jiffies;
3624 #endif
3625
3626         INIT_WORK(&dispc.error_work, dispc_error_worker);
3627
3628         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3629         if (!dispc_mem) {
3630                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3631                 r = -EINVAL;
3632                 goto fail0;
3633         }
3634         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3635         if (!dispc.base) {
3636                 DSSERR("can't ioremap DISPC\n");
3637                 r = -ENOMEM;
3638                 goto fail0;
3639         }
3640         dispc.irq = platform_get_irq(dispc.pdev, 0);
3641         if (dispc.irq < 0) {
3642                 DSSERR("platform_get_irq failed\n");
3643                 r = -ENODEV;
3644                 goto fail1;
3645         }
3646
3647         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3648                 "OMAP DISPC", dispc.pdev);
3649         if (r < 0) {
3650                 DSSERR("request_irq failed\n");
3651                 goto fail1;
3652         }
3653
3654         enable_clocks(1);
3655
3656         _omap_dispc_initial_config();
3657
3658         _omap_dispc_initialize_irq();
3659
3660         dispc_save_context();
3661
3662         rev = dispc_read_reg(DISPC_REVISION);
3663         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3664                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3665
3666         enable_clocks(0);
3667
3668         return 0;
3669 fail1:
3670         iounmap(dispc.base);
3671 fail0:
3672         return r;
3673 }
3674
3675 static int omap_dispchw_remove(struct platform_device *pdev)
3676 {
3677         free_irq(dispc.irq, dispc.pdev);
3678         iounmap(dispc.base);
3679         return 0;
3680 }
3681
3682 static struct platform_driver omap_dispchw_driver = {
3683         .probe          = omap_dispchw_probe,
3684         .remove         = omap_dispchw_remove,
3685         .driver         = {
3686                 .name   = "omapdss_dispc",
3687                 .owner  = THIS_MODULE,
3688         },
3689 };
3690
3691 int dispc_init_platform_driver(void)
3692 {
3693         return platform_driver_register(&omap_dispchw_driver);
3694 }
3695
3696 void dispc_uninit_platform_driver(void)
3697 {
3698         return platform_driver_unregister(&omap_dispchw_driver);
3699 }