OMAPDSS: Remove passive matrix LCD support (part 4)
[linux-3.10.git] / drivers / video / omap2 / dss / dispc.c
1 /*
2  * linux/drivers/video/omap2/dss/dispc.c
3  *
4  * Copyright (C) 2009 Nokia Corporation
5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6  *
7  * Some code and ideas taken from drivers/video/omap/ driver
8  * by Imre Deak.
9  *
10  * This program is free software; you can redistribute it and/or modify it
11  * under the terms of the GNU General Public License version 2 as published by
12  * the Free Software Foundation.
13  *
14  * This program is distributed in the hope that it will be useful, but WITHOUT
15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
17  * more details.
18  *
19  * You should have received a copy of the GNU General Public License along with
20  * this program.  If not, see <http://www.gnu.org/licenses/>.
21  */
22
23 #define DSS_SUBSYS_NAME "DISPC"
24
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
30 #include <linux/io.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
39
40 #include <plat/clock.h>
41
42 #include <video/omapdss.h>
43
44 #include "dss.h"
45 #include "dss_features.h"
46 #include "dispc.h"
47
48 /* DISPC */
49 #define DISPC_SZ_REGS                   SZ_4K
50
51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52                                          DISPC_IRQ_OCP_ERR | \
53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55                                          DISPC_IRQ_SYNC_LOST | \
56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
57
58 #define DISPC_MAX_NR_ISRS               8
59
60 struct omap_dispc_isr_data {
61         omap_dispc_isr_t        isr;
62         void                    *arg;
63         u32                     mask;
64 };
65
66 enum omap_burst_size {
67         BURST_SIZE_X2 = 0,
68         BURST_SIZE_X4 = 1,
69         BURST_SIZE_X8 = 2,
70 };
71
72 #define REG_GET(idx, start, end) \
73         FLD_GET(dispc_read_reg(idx), start, end)
74
75 #define REG_FLD_MOD(idx, val, start, end)                               \
76         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
78 struct dispc_irq_stats {
79         unsigned long last_reset;
80         unsigned irq_count;
81         unsigned irqs[32];
82 };
83
84 static struct {
85         struct platform_device *pdev;
86         void __iomem    *base;
87
88         int             ctx_loss_cnt;
89
90         int irq;
91         struct clk *dss_clk;
92
93         u32     fifo_size[MAX_DSS_OVERLAYS];
94
95         spinlock_t irq_lock;
96         u32 irq_error_mask;
97         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98         u32 error_irqs;
99         struct work_struct error_work;
100
101         bool            ctx_valid;
102         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
103
104 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105         spinlock_t irq_stats_lock;
106         struct dispc_irq_stats irq_stats;
107 #endif
108 } dispc;
109
110 enum omap_color_component {
111         /* used for all color formats for OMAP3 and earlier
112          * and for RGB and Y color component on OMAP4
113          */
114         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
115         /* used for UV component for
116          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117          * color formats on OMAP4
118          */
119         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
120 };
121
122 enum mgr_reg_fields {
123         DISPC_MGR_FLD_ENABLE,
124         DISPC_MGR_FLD_STNTFT,
125         DISPC_MGR_FLD_GO,
126         DISPC_MGR_FLD_TFTDATALINES,
127         DISPC_MGR_FLD_STALLMODE,
128         DISPC_MGR_FLD_TCKENABLE,
129         DISPC_MGR_FLD_TCKSELECTION,
130         DISPC_MGR_FLD_CPR,
131         DISPC_MGR_FLD_FIFOHANDCHECK,
132         /* used to maintain a count of the above fields */
133         DISPC_MGR_FLD_NUM,
134 };
135
136 static const struct {
137         const char *name;
138         u32 vsync_irq;
139         u32 framedone_irq;
140         u32 sync_lost_irq;
141         struct reg_field reg_desc[DISPC_MGR_FLD_NUM];
142 } mgr_desc[] = {
143         [OMAP_DSS_CHANNEL_LCD] = {
144                 .name           = "LCD",
145                 .vsync_irq      = DISPC_IRQ_VSYNC,
146                 .framedone_irq  = DISPC_IRQ_FRAMEDONE,
147                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST,
148                 .reg_desc       = {
149                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  0,  0 },
150                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL,  3,  3 },
151                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  5,  5 },
152                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL,  9,  8 },
153                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL, 11, 11 },
154                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  10, 10 },
155                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  11, 11 },
156                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG,  15, 15 },
157                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
158                 },
159         },
160         [OMAP_DSS_CHANNEL_DIGIT] = {
161                 .name           = "DIGIT",
162                 .vsync_irq      = DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN,
163                 .framedone_irq  = 0,
164                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST_DIGIT,
165                 .reg_desc       = {
166                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL,  1,  1 },
167                         [DISPC_MGR_FLD_STNTFT]          = { },
168                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL,  6,  6 },
169                         [DISPC_MGR_FLD_TFTDATALINES]    = { },
170                         [DISPC_MGR_FLD_STALLMODE]       = { },
171                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG,  12, 12 },
172                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG,  13, 13 },
173                         [DISPC_MGR_FLD_CPR]             = { },
174                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG,  16, 16 },
175                 },
176         },
177         [OMAP_DSS_CHANNEL_LCD2] = {
178                 .name           = "LCD2",
179                 .vsync_irq      = DISPC_IRQ_VSYNC2,
180                 .framedone_irq  = DISPC_IRQ_FRAMEDONE2,
181                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST2,
182                 .reg_desc       = {
183                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL2,  0,  0 },
184                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL2,  3,  3 },
185                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL2,  5,  5 },
186                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL2,  9,  8 },
187                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL2, 11, 11 },
188                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG2,  10, 10 },
189                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG2,  11, 11 },
190                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG2,  15, 15 },
191                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG2,  16, 16 },
192                 },
193         },
194         [OMAP_DSS_CHANNEL_LCD3] = {
195                 .name           = "LCD3",
196                 .vsync_irq      = DISPC_IRQ_VSYNC3,
197                 .framedone_irq  = DISPC_IRQ_FRAMEDONE3,
198                 .sync_lost_irq  = DISPC_IRQ_SYNC_LOST3,
199                 .reg_desc       = {
200                         [DISPC_MGR_FLD_ENABLE]          = { DISPC_CONTROL3,  0,  0 },
201                         [DISPC_MGR_FLD_STNTFT]          = { DISPC_CONTROL3,  3,  3 },
202                         [DISPC_MGR_FLD_GO]              = { DISPC_CONTROL3,  5,  5 },
203                         [DISPC_MGR_FLD_TFTDATALINES]    = { DISPC_CONTROL3,  9,  8 },
204                         [DISPC_MGR_FLD_STALLMODE]       = { DISPC_CONTROL3, 11, 11 },
205                         [DISPC_MGR_FLD_TCKENABLE]       = { DISPC_CONFIG3,  10, 10 },
206                         [DISPC_MGR_FLD_TCKSELECTION]    = { DISPC_CONFIG3,  11, 11 },
207                         [DISPC_MGR_FLD_CPR]             = { DISPC_CONFIG3,  15, 15 },
208                         [DISPC_MGR_FLD_FIFOHANDCHECK]   = { DISPC_CONFIG3,  16, 16 },
209                 },
210         },
211 };
212
213 static void _omap_dispc_set_irqs(void);
214
215 static inline void dispc_write_reg(const u16 idx, u32 val)
216 {
217         __raw_writel(val, dispc.base + idx);
218 }
219
220 static inline u32 dispc_read_reg(const u16 idx)
221 {
222         return __raw_readl(dispc.base + idx);
223 }
224
225 static u32 mgr_fld_read(enum omap_channel channel, enum mgr_reg_fields regfld)
226 {
227         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
228         return REG_GET(rfld.reg, rfld.high, rfld.low);
229 }
230
231 static void mgr_fld_write(enum omap_channel channel,
232                                         enum mgr_reg_fields regfld, int val) {
233         const struct reg_field rfld = mgr_desc[channel].reg_desc[regfld];
234         REG_FLD_MOD(rfld.reg, val, rfld.high, rfld.low);
235 }
236
237 #define SR(reg) \
238         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
239 #define RR(reg) \
240         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
241
242 static void dispc_save_context(void)
243 {
244         int i, j;
245
246         DSSDBG("dispc_save_context\n");
247
248         SR(IRQENABLE);
249         SR(CONTROL);
250         SR(CONFIG);
251         SR(LINE_NUMBER);
252         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
253                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
254                 SR(GLOBAL_ALPHA);
255         if (dss_has_feature(FEAT_MGR_LCD2)) {
256                 SR(CONTROL2);
257                 SR(CONFIG2);
258         }
259         if (dss_has_feature(FEAT_MGR_LCD3)) {
260                 SR(CONTROL3);
261                 SR(CONFIG3);
262         }
263
264         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
265                 SR(DEFAULT_COLOR(i));
266                 SR(TRANS_COLOR(i));
267                 SR(SIZE_MGR(i));
268                 if (i == OMAP_DSS_CHANNEL_DIGIT)
269                         continue;
270                 SR(TIMING_H(i));
271                 SR(TIMING_V(i));
272                 SR(POL_FREQ(i));
273                 SR(DIVISORo(i));
274
275                 SR(DATA_CYCLE1(i));
276                 SR(DATA_CYCLE2(i));
277                 SR(DATA_CYCLE3(i));
278
279                 if (dss_has_feature(FEAT_CPR)) {
280                         SR(CPR_COEF_R(i));
281                         SR(CPR_COEF_G(i));
282                         SR(CPR_COEF_B(i));
283                 }
284         }
285
286         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
287                 SR(OVL_BA0(i));
288                 SR(OVL_BA1(i));
289                 SR(OVL_POSITION(i));
290                 SR(OVL_SIZE(i));
291                 SR(OVL_ATTRIBUTES(i));
292                 SR(OVL_FIFO_THRESHOLD(i));
293                 SR(OVL_ROW_INC(i));
294                 SR(OVL_PIXEL_INC(i));
295                 if (dss_has_feature(FEAT_PRELOAD))
296                         SR(OVL_PRELOAD(i));
297                 if (i == OMAP_DSS_GFX) {
298                         SR(OVL_WINDOW_SKIP(i));
299                         SR(OVL_TABLE_BA(i));
300                         continue;
301                 }
302                 SR(OVL_FIR(i));
303                 SR(OVL_PICTURE_SIZE(i));
304                 SR(OVL_ACCU0(i));
305                 SR(OVL_ACCU1(i));
306
307                 for (j = 0; j < 8; j++)
308                         SR(OVL_FIR_COEF_H(i, j));
309
310                 for (j = 0; j < 8; j++)
311                         SR(OVL_FIR_COEF_HV(i, j));
312
313                 for (j = 0; j < 5; j++)
314                         SR(OVL_CONV_COEF(i, j));
315
316                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
317                         for (j = 0; j < 8; j++)
318                                 SR(OVL_FIR_COEF_V(i, j));
319                 }
320
321                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
322                         SR(OVL_BA0_UV(i));
323                         SR(OVL_BA1_UV(i));
324                         SR(OVL_FIR2(i));
325                         SR(OVL_ACCU2_0(i));
326                         SR(OVL_ACCU2_1(i));
327
328                         for (j = 0; j < 8; j++)
329                                 SR(OVL_FIR_COEF_H2(i, j));
330
331                         for (j = 0; j < 8; j++)
332                                 SR(OVL_FIR_COEF_HV2(i, j));
333
334                         for (j = 0; j < 8; j++)
335                                 SR(OVL_FIR_COEF_V2(i, j));
336                 }
337                 if (dss_has_feature(FEAT_ATTR2))
338                         SR(OVL_ATTRIBUTES2(i));
339         }
340
341         if (dss_has_feature(FEAT_CORE_CLK_DIV))
342                 SR(DIVISOR);
343
344         dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
345         dispc.ctx_valid = true;
346
347         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
348 }
349
350 static void dispc_restore_context(void)
351 {
352         int i, j, ctx;
353
354         DSSDBG("dispc_restore_context\n");
355
356         if (!dispc.ctx_valid)
357                 return;
358
359         ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
360
361         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
362                 return;
363
364         DSSDBG("ctx_loss_count: saved %d, current %d\n",
365                         dispc.ctx_loss_cnt, ctx);
366
367         /*RR(IRQENABLE);*/
368         /*RR(CONTROL);*/
369         RR(CONFIG);
370         RR(LINE_NUMBER);
371         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
372                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
373                 RR(GLOBAL_ALPHA);
374         if (dss_has_feature(FEAT_MGR_LCD2))
375                 RR(CONFIG2);
376         if (dss_has_feature(FEAT_MGR_LCD3))
377                 RR(CONFIG3);
378
379         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
380                 RR(DEFAULT_COLOR(i));
381                 RR(TRANS_COLOR(i));
382                 RR(SIZE_MGR(i));
383                 if (i == OMAP_DSS_CHANNEL_DIGIT)
384                         continue;
385                 RR(TIMING_H(i));
386                 RR(TIMING_V(i));
387                 RR(POL_FREQ(i));
388                 RR(DIVISORo(i));
389
390                 RR(DATA_CYCLE1(i));
391                 RR(DATA_CYCLE2(i));
392                 RR(DATA_CYCLE3(i));
393
394                 if (dss_has_feature(FEAT_CPR)) {
395                         RR(CPR_COEF_R(i));
396                         RR(CPR_COEF_G(i));
397                         RR(CPR_COEF_B(i));
398                 }
399         }
400
401         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
402                 RR(OVL_BA0(i));
403                 RR(OVL_BA1(i));
404                 RR(OVL_POSITION(i));
405                 RR(OVL_SIZE(i));
406                 RR(OVL_ATTRIBUTES(i));
407                 RR(OVL_FIFO_THRESHOLD(i));
408                 RR(OVL_ROW_INC(i));
409                 RR(OVL_PIXEL_INC(i));
410                 if (dss_has_feature(FEAT_PRELOAD))
411                         RR(OVL_PRELOAD(i));
412                 if (i == OMAP_DSS_GFX) {
413                         RR(OVL_WINDOW_SKIP(i));
414                         RR(OVL_TABLE_BA(i));
415                         continue;
416                 }
417                 RR(OVL_FIR(i));
418                 RR(OVL_PICTURE_SIZE(i));
419                 RR(OVL_ACCU0(i));
420                 RR(OVL_ACCU1(i));
421
422                 for (j = 0; j < 8; j++)
423                         RR(OVL_FIR_COEF_H(i, j));
424
425                 for (j = 0; j < 8; j++)
426                         RR(OVL_FIR_COEF_HV(i, j));
427
428                 for (j = 0; j < 5; j++)
429                         RR(OVL_CONV_COEF(i, j));
430
431                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
432                         for (j = 0; j < 8; j++)
433                                 RR(OVL_FIR_COEF_V(i, j));
434                 }
435
436                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
437                         RR(OVL_BA0_UV(i));
438                         RR(OVL_BA1_UV(i));
439                         RR(OVL_FIR2(i));
440                         RR(OVL_ACCU2_0(i));
441                         RR(OVL_ACCU2_1(i));
442
443                         for (j = 0; j < 8; j++)
444                                 RR(OVL_FIR_COEF_H2(i, j));
445
446                         for (j = 0; j < 8; j++)
447                                 RR(OVL_FIR_COEF_HV2(i, j));
448
449                         for (j = 0; j < 8; j++)
450                                 RR(OVL_FIR_COEF_V2(i, j));
451                 }
452                 if (dss_has_feature(FEAT_ATTR2))
453                         RR(OVL_ATTRIBUTES2(i));
454         }
455
456         if (dss_has_feature(FEAT_CORE_CLK_DIV))
457                 RR(DIVISOR);
458
459         /* enable last, because LCD & DIGIT enable are here */
460         RR(CONTROL);
461         if (dss_has_feature(FEAT_MGR_LCD2))
462                 RR(CONTROL2);
463         if (dss_has_feature(FEAT_MGR_LCD3))
464                 RR(CONTROL3);
465         /* clear spurious SYNC_LOST_DIGIT interrupts */
466         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
467
468         /*
469          * enable last so IRQs won't trigger before
470          * the context is fully restored
471          */
472         RR(IRQENABLE);
473
474         DSSDBG("context restored\n");
475 }
476
477 #undef SR
478 #undef RR
479
480 int dispc_runtime_get(void)
481 {
482         int r;
483
484         DSSDBG("dispc_runtime_get\n");
485
486         r = pm_runtime_get_sync(&dispc.pdev->dev);
487         WARN_ON(r < 0);
488         return r < 0 ? r : 0;
489 }
490
491 void dispc_runtime_put(void)
492 {
493         int r;
494
495         DSSDBG("dispc_runtime_put\n");
496
497         r = pm_runtime_put_sync(&dispc.pdev->dev);
498         WARN_ON(r < 0 && r != -ENOSYS);
499 }
500
501 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
502 {
503         if (channel == OMAP_DSS_CHANNEL_LCD ||
504                         channel == OMAP_DSS_CHANNEL_LCD2 ||
505                         channel == OMAP_DSS_CHANNEL_LCD3)
506                 return true;
507         else
508                 return false;
509 }
510
511 u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
512 {
513         return mgr_desc[channel].vsync_irq;
514 }
515
516 u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
517 {
518         return mgr_desc[channel].framedone_irq;
519 }
520
521 bool dispc_mgr_go_busy(enum omap_channel channel)
522 {
523         return mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
524 }
525
526 void dispc_mgr_go(enum omap_channel channel)
527 {
528         bool enable_bit, go_bit;
529
530         /* if the channel is not enabled, we don't need GO */
531         enable_bit = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE) == 1;
532
533         if (!enable_bit)
534                 return;
535
536         go_bit = mgr_fld_read(channel, DISPC_MGR_FLD_GO) == 1;
537
538         if (go_bit) {
539                 DSSERR("GO bit not down for channel %d\n", channel);
540                 return;
541         }
542
543         DSSDBG("GO %s\n", mgr_desc[channel].name);
544
545         mgr_fld_write(channel, DISPC_MGR_FLD_GO, 1);
546 }
547
548 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
549 {
550         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
551 }
552
553 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
554 {
555         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
556 }
557
558 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
559 {
560         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
561 }
562
563 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
564 {
565         BUG_ON(plane == OMAP_DSS_GFX);
566
567         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
568 }
569
570 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
571                 u32 value)
572 {
573         BUG_ON(plane == OMAP_DSS_GFX);
574
575         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
576 }
577
578 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
579 {
580         BUG_ON(plane == OMAP_DSS_GFX);
581
582         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
583 }
584
585 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
586                                 int fir_vinc, int five_taps,
587                                 enum omap_color_component color_comp)
588 {
589         const struct dispc_coef *h_coef, *v_coef;
590         int i;
591
592         h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
593         v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
594
595         for (i = 0; i < 8; i++) {
596                 u32 h, hv;
597
598                 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
599                         | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
600                         | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
601                         | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
602                 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
603                         | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
604                         | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
605                         | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
606
607                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
608                         dispc_ovl_write_firh_reg(plane, i, h);
609                         dispc_ovl_write_firhv_reg(plane, i, hv);
610                 } else {
611                         dispc_ovl_write_firh2_reg(plane, i, h);
612                         dispc_ovl_write_firhv2_reg(plane, i, hv);
613                 }
614
615         }
616
617         if (five_taps) {
618                 for (i = 0; i < 8; i++) {
619                         u32 v;
620                         v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
621                                 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
622                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
623                                 dispc_ovl_write_firv_reg(plane, i, v);
624                         else
625                                 dispc_ovl_write_firv2_reg(plane, i, v);
626                 }
627         }
628 }
629
630 static void _dispc_setup_color_conv_coef(void)
631 {
632         int i;
633         const struct color_conv_coef {
634                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
635                 int  full_range;
636         }  ctbl_bt601_5 = {
637                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
638         };
639
640         const struct color_conv_coef *ct;
641
642 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
643
644         ct = &ctbl_bt601_5;
645
646         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
647                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
648                         CVAL(ct->rcr, ct->ry));
649                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
650                         CVAL(ct->gy,  ct->rcb));
651                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
652                         CVAL(ct->gcb, ct->gcr));
653                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
654                         CVAL(ct->bcr, ct->by));
655                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
656                         CVAL(0, ct->bcb));
657
658                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
659                         11, 11);
660         }
661
662 #undef CVAL
663 }
664
665
666 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
667 {
668         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
669 }
670
671 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
672 {
673         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
674 }
675
676 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
677 {
678         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
679 }
680
681 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
682 {
683         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
684 }
685
686 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
687 {
688         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
689
690         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
691 }
692
693 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
694 {
695         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
696
697         if (plane == OMAP_DSS_GFX)
698                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
699         else
700                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
701 }
702
703 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
704 {
705         u32 val;
706
707         BUG_ON(plane == OMAP_DSS_GFX);
708
709         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
710
711         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
712 }
713
714 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
715 {
716         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
717
718         if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
719                 return;
720
721         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
722 }
723
724 static void dispc_ovl_enable_zorder_planes(void)
725 {
726         int i;
727
728         if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
729                 return;
730
731         for (i = 0; i < dss_feat_get_num_ovls(); i++)
732                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
733 }
734
735 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
736 {
737         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
738
739         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
740                 return;
741
742         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
743 }
744
745 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
746 {
747         static const unsigned shifts[] = { 0, 8, 16, 24, };
748         int shift;
749         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
750
751         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
752                 return;
753
754         shift = shifts[plane];
755         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
756 }
757
758 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
759 {
760         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
761 }
762
763 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
764 {
765         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
766 }
767
768 static void dispc_ovl_set_color_mode(enum omap_plane plane,
769                 enum omap_color_mode color_mode)
770 {
771         u32 m = 0;
772         if (plane != OMAP_DSS_GFX) {
773                 switch (color_mode) {
774                 case OMAP_DSS_COLOR_NV12:
775                         m = 0x0; break;
776                 case OMAP_DSS_COLOR_RGBX16:
777                         m = 0x1; break;
778                 case OMAP_DSS_COLOR_RGBA16:
779                         m = 0x2; break;
780                 case OMAP_DSS_COLOR_RGB12U:
781                         m = 0x4; break;
782                 case OMAP_DSS_COLOR_ARGB16:
783                         m = 0x5; break;
784                 case OMAP_DSS_COLOR_RGB16:
785                         m = 0x6; break;
786                 case OMAP_DSS_COLOR_ARGB16_1555:
787                         m = 0x7; break;
788                 case OMAP_DSS_COLOR_RGB24U:
789                         m = 0x8; break;
790                 case OMAP_DSS_COLOR_RGB24P:
791                         m = 0x9; break;
792                 case OMAP_DSS_COLOR_YUV2:
793                         m = 0xa; break;
794                 case OMAP_DSS_COLOR_UYVY:
795                         m = 0xb; break;
796                 case OMAP_DSS_COLOR_ARGB32:
797                         m = 0xc; break;
798                 case OMAP_DSS_COLOR_RGBA32:
799                         m = 0xd; break;
800                 case OMAP_DSS_COLOR_RGBX32:
801                         m = 0xe; break;
802                 case OMAP_DSS_COLOR_XRGB16_1555:
803                         m = 0xf; break;
804                 default:
805                         BUG(); return;
806                 }
807         } else {
808                 switch (color_mode) {
809                 case OMAP_DSS_COLOR_CLUT1:
810                         m = 0x0; break;
811                 case OMAP_DSS_COLOR_CLUT2:
812                         m = 0x1; break;
813                 case OMAP_DSS_COLOR_CLUT4:
814                         m = 0x2; break;
815                 case OMAP_DSS_COLOR_CLUT8:
816                         m = 0x3; break;
817                 case OMAP_DSS_COLOR_RGB12U:
818                         m = 0x4; break;
819                 case OMAP_DSS_COLOR_ARGB16:
820                         m = 0x5; break;
821                 case OMAP_DSS_COLOR_RGB16:
822                         m = 0x6; break;
823                 case OMAP_DSS_COLOR_ARGB16_1555:
824                         m = 0x7; break;
825                 case OMAP_DSS_COLOR_RGB24U:
826                         m = 0x8; break;
827                 case OMAP_DSS_COLOR_RGB24P:
828                         m = 0x9; break;
829                 case OMAP_DSS_COLOR_RGBX16:
830                         m = 0xa; break;
831                 case OMAP_DSS_COLOR_RGBA16:
832                         m = 0xb; break;
833                 case OMAP_DSS_COLOR_ARGB32:
834                         m = 0xc; break;
835                 case OMAP_DSS_COLOR_RGBA32:
836                         m = 0xd; break;
837                 case OMAP_DSS_COLOR_RGBX32:
838                         m = 0xe; break;
839                 case OMAP_DSS_COLOR_XRGB16_1555:
840                         m = 0xf; break;
841                 default:
842                         BUG(); return;
843                 }
844         }
845
846         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
847 }
848
849 static void dispc_ovl_configure_burst_type(enum omap_plane plane,
850                 enum omap_dss_rotation_type rotation_type)
851 {
852         if (dss_has_feature(FEAT_BURST_2D) == 0)
853                 return;
854
855         if (rotation_type == OMAP_DSS_ROT_TILER)
856                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29);
857         else
858                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29);
859 }
860
861 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
862 {
863         int shift;
864         u32 val;
865         int chan = 0, chan2 = 0;
866
867         switch (plane) {
868         case OMAP_DSS_GFX:
869                 shift = 8;
870                 break;
871         case OMAP_DSS_VIDEO1:
872         case OMAP_DSS_VIDEO2:
873         case OMAP_DSS_VIDEO3:
874                 shift = 16;
875                 break;
876         default:
877                 BUG();
878                 return;
879         }
880
881         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
882         if (dss_has_feature(FEAT_MGR_LCD2)) {
883                 switch (channel) {
884                 case OMAP_DSS_CHANNEL_LCD:
885                         chan = 0;
886                         chan2 = 0;
887                         break;
888                 case OMAP_DSS_CHANNEL_DIGIT:
889                         chan = 1;
890                         chan2 = 0;
891                         break;
892                 case OMAP_DSS_CHANNEL_LCD2:
893                         chan = 0;
894                         chan2 = 1;
895                         break;
896                 case OMAP_DSS_CHANNEL_LCD3:
897                         if (dss_has_feature(FEAT_MGR_LCD3)) {
898                                 chan = 0;
899                                 chan2 = 2;
900                         } else {
901                                 BUG();
902                                 return;
903                         }
904                         break;
905                 default:
906                         BUG();
907                         return;
908                 }
909
910                 val = FLD_MOD(val, chan, shift, shift);
911                 val = FLD_MOD(val, chan2, 31, 30);
912         } else {
913                 val = FLD_MOD(val, channel, shift, shift);
914         }
915         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
916 }
917
918 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
919 {
920         int shift;
921         u32 val;
922         enum omap_channel channel;
923
924         switch (plane) {
925         case OMAP_DSS_GFX:
926                 shift = 8;
927                 break;
928         case OMAP_DSS_VIDEO1:
929         case OMAP_DSS_VIDEO2:
930         case OMAP_DSS_VIDEO3:
931                 shift = 16;
932                 break;
933         default:
934                 BUG();
935                 return 0;
936         }
937
938         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
939
940         if (dss_has_feature(FEAT_MGR_LCD3)) {
941                 if (FLD_GET(val, 31, 30) == 0)
942                         channel = FLD_GET(val, shift, shift);
943                 else if (FLD_GET(val, 31, 30) == 1)
944                         channel = OMAP_DSS_CHANNEL_LCD2;
945                 else
946                         channel = OMAP_DSS_CHANNEL_LCD3;
947         } else if (dss_has_feature(FEAT_MGR_LCD2)) {
948                 if (FLD_GET(val, 31, 30) == 0)
949                         channel = FLD_GET(val, shift, shift);
950                 else
951                         channel = OMAP_DSS_CHANNEL_LCD2;
952         } else {
953                 channel = FLD_GET(val, shift, shift);
954         }
955
956         return channel;
957 }
958
959 static void dispc_ovl_set_burst_size(enum omap_plane plane,
960                 enum omap_burst_size burst_size)
961 {
962         static const unsigned shifts[] = { 6, 14, 14, 14, };
963         int shift;
964
965         shift = shifts[plane];
966         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
967 }
968
969 static void dispc_configure_burst_sizes(void)
970 {
971         int i;
972         const int burst_size = BURST_SIZE_X8;
973
974         /* Configure burst size always to maximum size */
975         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
976                 dispc_ovl_set_burst_size(i, burst_size);
977 }
978
979 static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
980 {
981         unsigned unit = dss_feat_get_burst_size_unit();
982         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
983         return unit * 8;
984 }
985
986 void dispc_enable_gamma_table(bool enable)
987 {
988         /*
989          * This is partially implemented to support only disabling of
990          * the gamma table.
991          */
992         if (enable) {
993                 DSSWARN("Gamma table enabling for TV not yet supported");
994                 return;
995         }
996
997         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
998 }
999
1000 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1001 {
1002         if (channel == OMAP_DSS_CHANNEL_DIGIT)
1003                 return;
1004
1005         mgr_fld_write(channel, DISPC_MGR_FLD_CPR, enable);
1006 }
1007
1008 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1009                 struct omap_dss_cpr_coefs *coefs)
1010 {
1011         u32 coef_r, coef_g, coef_b;
1012
1013         if (!dispc_mgr_is_lcd(channel))
1014                 return;
1015
1016         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1017                 FLD_VAL(coefs->rb, 9, 0);
1018         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1019                 FLD_VAL(coefs->gb, 9, 0);
1020         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1021                 FLD_VAL(coefs->bb, 9, 0);
1022
1023         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1024         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1025         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1026 }
1027
1028 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1029 {
1030         u32 val;
1031
1032         BUG_ON(plane == OMAP_DSS_GFX);
1033
1034         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1035         val = FLD_MOD(val, enable, 9, 9);
1036         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1037 }
1038
1039 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1040 {
1041         static const unsigned shifts[] = { 5, 10, 10, 10 };
1042         int shift;
1043
1044         shift = shifts[plane];
1045         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1046 }
1047
1048 static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
1049                 u16 height)
1050 {
1051         u32 val;
1052
1053         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1054         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1055 }
1056
1057 static void dispc_read_plane_fifo_sizes(void)
1058 {
1059         u32 size;
1060         int plane;
1061         u8 start, end;
1062         u32 unit;
1063
1064         unit = dss_feat_get_buffer_size_unit();
1065
1066         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1067
1068         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1069                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1070                 size *= unit;
1071                 dispc.fifo_size[plane] = size;
1072         }
1073 }
1074
1075 static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1076 {
1077         return dispc.fifo_size[plane];
1078 }
1079
1080 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1081 {
1082         u8 hi_start, hi_end, lo_start, lo_end;
1083         u32 unit;
1084
1085         unit = dss_feat_get_buffer_size_unit();
1086
1087         WARN_ON(low % unit != 0);
1088         WARN_ON(high % unit != 0);
1089
1090         low /= unit;
1091         high /= unit;
1092
1093         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1094         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1095
1096         DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
1097                         plane,
1098                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1099                                 lo_start, lo_end) * unit,
1100                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1101                                 hi_start, hi_end) * unit,
1102                         low * unit, high * unit);
1103
1104         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1105                         FLD_VAL(high, hi_start, hi_end) |
1106                         FLD_VAL(low, lo_start, lo_end));
1107 }
1108
1109 void dispc_enable_fifomerge(bool enable)
1110 {
1111         if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1112                 WARN_ON(enable);
1113                 return;
1114         }
1115
1116         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1117         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1118 }
1119
1120 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
1121                 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1122                 bool manual_update)
1123 {
1124         /*
1125          * All sizes are in bytes. Both the buffer and burst are made of
1126          * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1127          */
1128
1129         unsigned buf_unit = dss_feat_get_buffer_size_unit();
1130         unsigned ovl_fifo_size, total_fifo_size, burst_size;
1131         int i;
1132
1133         burst_size = dispc_ovl_get_burst_size(plane);
1134         ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
1135
1136         if (use_fifomerge) {
1137                 total_fifo_size = 0;
1138                 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1139                         total_fifo_size += dispc_ovl_get_fifo_size(i);
1140         } else {
1141                 total_fifo_size = ovl_fifo_size;
1142         }
1143
1144         /*
1145          * We use the same low threshold for both fifomerge and non-fifomerge
1146          * cases, but for fifomerge we calculate the high threshold using the
1147          * combined fifo size
1148          */
1149
1150         if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
1151                 *fifo_low = ovl_fifo_size - burst_size * 2;
1152                 *fifo_high = total_fifo_size - burst_size;
1153         } else {
1154                 *fifo_low = ovl_fifo_size - burst_size;
1155                 *fifo_high = total_fifo_size - buf_unit;
1156         }
1157 }
1158
1159 static void dispc_ovl_set_fir(enum omap_plane plane,
1160                                 int hinc, int vinc,
1161                                 enum omap_color_component color_comp)
1162 {
1163         u32 val;
1164
1165         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1166                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1167
1168                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1169                                         &hinc_start, &hinc_end);
1170                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1171                                         &vinc_start, &vinc_end);
1172                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1173                                 FLD_VAL(hinc, hinc_start, hinc_end);
1174
1175                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1176         } else {
1177                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1178                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1179         }
1180 }
1181
1182 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1183 {
1184         u32 val;
1185         u8 hor_start, hor_end, vert_start, vert_end;
1186
1187         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1188         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1189
1190         val = FLD_VAL(vaccu, vert_start, vert_end) |
1191                         FLD_VAL(haccu, hor_start, hor_end);
1192
1193         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1194 }
1195
1196 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1197 {
1198         u32 val;
1199         u8 hor_start, hor_end, vert_start, vert_end;
1200
1201         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1202         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1203
1204         val = FLD_VAL(vaccu, vert_start, vert_end) |
1205                         FLD_VAL(haccu, hor_start, hor_end);
1206
1207         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1208 }
1209
1210 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1211                 int vaccu)
1212 {
1213         u32 val;
1214
1215         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1216         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1217 }
1218
1219 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1220                 int vaccu)
1221 {
1222         u32 val;
1223
1224         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1225         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1226 }
1227
1228 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1229                 u16 orig_width, u16 orig_height,
1230                 u16 out_width, u16 out_height,
1231                 bool five_taps, u8 rotation,
1232                 enum omap_color_component color_comp)
1233 {
1234         int fir_hinc, fir_vinc;
1235
1236         fir_hinc = 1024 * orig_width / out_width;
1237         fir_vinc = 1024 * orig_height / out_height;
1238
1239         dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1240                                 color_comp);
1241         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1242 }
1243
1244 static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1245                 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1246                 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1247 {
1248         int h_accu2_0, h_accu2_1;
1249         int v_accu2_0, v_accu2_1;
1250         int chroma_hinc, chroma_vinc;
1251         int idx;
1252
1253         struct accu {
1254                 s8 h0_m, h0_n;
1255                 s8 h1_m, h1_n;
1256                 s8 v0_m, v0_n;
1257                 s8 v1_m, v1_n;
1258         };
1259
1260         const struct accu *accu_table;
1261         const struct accu *accu_val;
1262
1263         static const struct accu accu_nv12[4] = {
1264                 {  0, 1,  0, 1 , -1, 2, 0, 1 },
1265                 {  1, 2, -3, 4 ,  0, 1, 0, 1 },
1266                 { -1, 1,  0, 1 , -1, 2, 0, 1 },
1267                 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1268         };
1269
1270         static const struct accu accu_nv12_ilace[4] = {
1271                 {  0, 1,  0, 1 , -3, 4, -1, 4 },
1272                 { -1, 4, -3, 4 ,  0, 1,  0, 1 },
1273                 { -1, 1,  0, 1 , -1, 4, -3, 4 },
1274                 { -3, 4, -3, 4 , -1, 1,  0, 1 },
1275         };
1276
1277         static const struct accu accu_yuv[4] = {
1278                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1279                 {  0, 1, 0, 1,  0, 1, 0, 1 },
1280                 { -1, 1, 0, 1,  0, 1, 0, 1 },
1281                 {  0, 1, 0, 1, -1, 1, 0, 1 },
1282         };
1283
1284         switch (rotation) {
1285         case OMAP_DSS_ROT_0:
1286                 idx = 0;
1287                 break;
1288         case OMAP_DSS_ROT_90:
1289                 idx = 1;
1290                 break;
1291         case OMAP_DSS_ROT_180:
1292                 idx = 2;
1293                 break;
1294         case OMAP_DSS_ROT_270:
1295                 idx = 3;
1296                 break;
1297         default:
1298                 BUG();
1299                 return;
1300         }
1301
1302         switch (color_mode) {
1303         case OMAP_DSS_COLOR_NV12:
1304                 if (ilace)
1305                         accu_table = accu_nv12_ilace;
1306                 else
1307                         accu_table = accu_nv12;
1308                 break;
1309         case OMAP_DSS_COLOR_YUV2:
1310         case OMAP_DSS_COLOR_UYVY:
1311                 accu_table = accu_yuv;
1312                 break;
1313         default:
1314                 BUG();
1315                 return;
1316         }
1317
1318         accu_val = &accu_table[idx];
1319
1320         chroma_hinc = 1024 * orig_width / out_width;
1321         chroma_vinc = 1024 * orig_height / out_height;
1322
1323         h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1324         h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1325         v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1326         v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1327
1328         dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1329         dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1330 }
1331
1332 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1333                 u16 orig_width, u16 orig_height,
1334                 u16 out_width, u16 out_height,
1335                 bool ilace, bool five_taps,
1336                 bool fieldmode, enum omap_color_mode color_mode,
1337                 u8 rotation)
1338 {
1339         int accu0 = 0;
1340         int accu1 = 0;
1341         u32 l;
1342
1343         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1344                                 out_width, out_height, five_taps,
1345                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1346         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1347
1348         /* RESIZEENABLE and VERTICALTAPS */
1349         l &= ~((0x3 << 5) | (0x1 << 21));
1350         l |= (orig_width != out_width) ? (1 << 5) : 0;
1351         l |= (orig_height != out_height) ? (1 << 6) : 0;
1352         l |= five_taps ? (1 << 21) : 0;
1353
1354         /* VRESIZECONF and HRESIZECONF */
1355         if (dss_has_feature(FEAT_RESIZECONF)) {
1356                 l &= ~(0x3 << 7);
1357                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1358                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1359         }
1360
1361         /* LINEBUFFERSPLIT */
1362         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1363                 l &= ~(0x1 << 22);
1364                 l |= five_taps ? (1 << 22) : 0;
1365         }
1366
1367         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1368
1369         /*
1370          * field 0 = even field = bottom field
1371          * field 1 = odd field = top field
1372          */
1373         if (ilace && !fieldmode) {
1374                 accu1 = 0;
1375                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1376                 if (accu0 >= 1024/2) {
1377                         accu1 = 1024/2;
1378                         accu0 -= accu1;
1379                 }
1380         }
1381
1382         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1383         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1384 }
1385
1386 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1387                 u16 orig_width, u16 orig_height,
1388                 u16 out_width, u16 out_height,
1389                 bool ilace, bool five_taps,
1390                 bool fieldmode, enum omap_color_mode color_mode,
1391                 u8 rotation)
1392 {
1393         int scale_x = out_width != orig_width;
1394         int scale_y = out_height != orig_height;
1395
1396         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1397                 return;
1398         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1399                         color_mode != OMAP_DSS_COLOR_UYVY &&
1400                         color_mode != OMAP_DSS_COLOR_NV12)) {
1401                 /* reset chroma resampling for RGB formats  */
1402                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1403                 return;
1404         }
1405
1406         dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1407                         out_height, ilace, color_mode, rotation);
1408
1409         switch (color_mode) {
1410         case OMAP_DSS_COLOR_NV12:
1411                 /* UV is subsampled by 2 vertically*/
1412                 orig_height >>= 1;
1413                 /* UV is subsampled by 2 horz.*/
1414                 orig_width >>= 1;
1415                 break;
1416         case OMAP_DSS_COLOR_YUV2:
1417         case OMAP_DSS_COLOR_UYVY:
1418                 /*For YUV422 with 90/270 rotation,
1419                  *we don't upsample chroma
1420                  */
1421                 if (rotation == OMAP_DSS_ROT_0 ||
1422                         rotation == OMAP_DSS_ROT_180)
1423                         /* UV is subsampled by 2 hrz*/
1424                         orig_width >>= 1;
1425                 /* must use FIR for YUV422 if rotated */
1426                 if (rotation != OMAP_DSS_ROT_0)
1427                         scale_x = scale_y = true;
1428                 break;
1429         default:
1430                 BUG();
1431                 return;
1432         }
1433
1434         if (out_width != orig_width)
1435                 scale_x = true;
1436         if (out_height != orig_height)
1437                 scale_y = true;
1438
1439         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1440                         out_width, out_height, five_taps,
1441                                 rotation, DISPC_COLOR_COMPONENT_UV);
1442
1443         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1444                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1445         /* set H scaling */
1446         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1447         /* set V scaling */
1448         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1449 }
1450
1451 static void dispc_ovl_set_scaling(enum omap_plane plane,
1452                 u16 orig_width, u16 orig_height,
1453                 u16 out_width, u16 out_height,
1454                 bool ilace, bool five_taps,
1455                 bool fieldmode, enum omap_color_mode color_mode,
1456                 u8 rotation)
1457 {
1458         BUG_ON(plane == OMAP_DSS_GFX);
1459
1460         dispc_ovl_set_scaling_common(plane,
1461                         orig_width, orig_height,
1462                         out_width, out_height,
1463                         ilace, five_taps,
1464                         fieldmode, color_mode,
1465                         rotation);
1466
1467         dispc_ovl_set_scaling_uv(plane,
1468                 orig_width, orig_height,
1469                 out_width, out_height,
1470                 ilace, five_taps,
1471                 fieldmode, color_mode,
1472                 rotation);
1473 }
1474
1475 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1476                 bool mirroring, enum omap_color_mode color_mode)
1477 {
1478         bool row_repeat = false;
1479         int vidrot = 0;
1480
1481         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1482                         color_mode == OMAP_DSS_COLOR_UYVY) {
1483
1484                 if (mirroring) {
1485                         switch (rotation) {
1486                         case OMAP_DSS_ROT_0:
1487                                 vidrot = 2;
1488                                 break;
1489                         case OMAP_DSS_ROT_90:
1490                                 vidrot = 1;
1491                                 break;
1492                         case OMAP_DSS_ROT_180:
1493                                 vidrot = 0;
1494                                 break;
1495                         case OMAP_DSS_ROT_270:
1496                                 vidrot = 3;
1497                                 break;
1498                         }
1499                 } else {
1500                         switch (rotation) {
1501                         case OMAP_DSS_ROT_0:
1502                                 vidrot = 0;
1503                                 break;
1504                         case OMAP_DSS_ROT_90:
1505                                 vidrot = 1;
1506                                 break;
1507                         case OMAP_DSS_ROT_180:
1508                                 vidrot = 2;
1509                                 break;
1510                         case OMAP_DSS_ROT_270:
1511                                 vidrot = 3;
1512                                 break;
1513                         }
1514                 }
1515
1516                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1517                         row_repeat = true;
1518                 else
1519                         row_repeat = false;
1520         }
1521
1522         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1523         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1524                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1525                         row_repeat ? 1 : 0, 18, 18);
1526 }
1527
1528 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1529 {
1530         switch (color_mode) {
1531         case OMAP_DSS_COLOR_CLUT1:
1532                 return 1;
1533         case OMAP_DSS_COLOR_CLUT2:
1534                 return 2;
1535         case OMAP_DSS_COLOR_CLUT4:
1536                 return 4;
1537         case OMAP_DSS_COLOR_CLUT8:
1538         case OMAP_DSS_COLOR_NV12:
1539                 return 8;
1540         case OMAP_DSS_COLOR_RGB12U:
1541         case OMAP_DSS_COLOR_RGB16:
1542         case OMAP_DSS_COLOR_ARGB16:
1543         case OMAP_DSS_COLOR_YUV2:
1544         case OMAP_DSS_COLOR_UYVY:
1545         case OMAP_DSS_COLOR_RGBA16:
1546         case OMAP_DSS_COLOR_RGBX16:
1547         case OMAP_DSS_COLOR_ARGB16_1555:
1548         case OMAP_DSS_COLOR_XRGB16_1555:
1549                 return 16;
1550         case OMAP_DSS_COLOR_RGB24P:
1551                 return 24;
1552         case OMAP_DSS_COLOR_RGB24U:
1553         case OMAP_DSS_COLOR_ARGB32:
1554         case OMAP_DSS_COLOR_RGBA32:
1555         case OMAP_DSS_COLOR_RGBX32:
1556                 return 32;
1557         default:
1558                 BUG();
1559                 return 0;
1560         }
1561 }
1562
1563 static s32 pixinc(int pixels, u8 ps)
1564 {
1565         if (pixels == 1)
1566                 return 1;
1567         else if (pixels > 1)
1568                 return 1 + (pixels - 1) * ps;
1569         else if (pixels < 0)
1570                 return 1 - (-pixels + 1) * ps;
1571         else
1572                 BUG();
1573                 return 0;
1574 }
1575
1576 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1577                 u16 screen_width,
1578                 u16 width, u16 height,
1579                 enum omap_color_mode color_mode, bool fieldmode,
1580                 unsigned int field_offset,
1581                 unsigned *offset0, unsigned *offset1,
1582                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1583 {
1584         u8 ps;
1585
1586         /* FIXME CLUT formats */
1587         switch (color_mode) {
1588         case OMAP_DSS_COLOR_CLUT1:
1589         case OMAP_DSS_COLOR_CLUT2:
1590         case OMAP_DSS_COLOR_CLUT4:
1591         case OMAP_DSS_COLOR_CLUT8:
1592                 BUG();
1593                 return;
1594         case OMAP_DSS_COLOR_YUV2:
1595         case OMAP_DSS_COLOR_UYVY:
1596                 ps = 4;
1597                 break;
1598         default:
1599                 ps = color_mode_to_bpp(color_mode) / 8;
1600                 break;
1601         }
1602
1603         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1604                         width, height);
1605
1606         /*
1607          * field 0 = even field = bottom field
1608          * field 1 = odd field = top field
1609          */
1610         switch (rotation + mirror * 4) {
1611         case OMAP_DSS_ROT_0:
1612         case OMAP_DSS_ROT_180:
1613                 /*
1614                  * If the pixel format is YUV or UYVY divide the width
1615                  * of the image by 2 for 0 and 180 degree rotation.
1616                  */
1617                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1618                         color_mode == OMAP_DSS_COLOR_UYVY)
1619                         width = width >> 1;
1620         case OMAP_DSS_ROT_90:
1621         case OMAP_DSS_ROT_270:
1622                 *offset1 = 0;
1623                 if (field_offset)
1624                         *offset0 = field_offset * screen_width * ps;
1625                 else
1626                         *offset0 = 0;
1627
1628                 *row_inc = pixinc(1 +
1629                         (y_predecim * screen_width - x_predecim * width) +
1630                         (fieldmode ? screen_width : 0), ps);
1631                 *pix_inc = pixinc(x_predecim, ps);
1632                 break;
1633
1634         case OMAP_DSS_ROT_0 + 4:
1635         case OMAP_DSS_ROT_180 + 4:
1636                 /* If the pixel format is YUV or UYVY divide the width
1637                  * of the image by 2  for 0 degree and 180 degree
1638                  */
1639                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1640                         color_mode == OMAP_DSS_COLOR_UYVY)
1641                         width = width >> 1;
1642         case OMAP_DSS_ROT_90 + 4:
1643         case OMAP_DSS_ROT_270 + 4:
1644                 *offset1 = 0;
1645                 if (field_offset)
1646                         *offset0 = field_offset * screen_width * ps;
1647                 else
1648                         *offset0 = 0;
1649                 *row_inc = pixinc(1 -
1650                         (y_predecim * screen_width + x_predecim * width) -
1651                         (fieldmode ? screen_width : 0), ps);
1652                 *pix_inc = pixinc(x_predecim, ps);
1653                 break;
1654
1655         default:
1656                 BUG();
1657                 return;
1658         }
1659 }
1660
1661 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1662                 u16 screen_width,
1663                 u16 width, u16 height,
1664                 enum omap_color_mode color_mode, bool fieldmode,
1665                 unsigned int field_offset,
1666                 unsigned *offset0, unsigned *offset1,
1667                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1668 {
1669         u8 ps;
1670         u16 fbw, fbh;
1671
1672         /* FIXME CLUT formats */
1673         switch (color_mode) {
1674         case OMAP_DSS_COLOR_CLUT1:
1675         case OMAP_DSS_COLOR_CLUT2:
1676         case OMAP_DSS_COLOR_CLUT4:
1677         case OMAP_DSS_COLOR_CLUT8:
1678                 BUG();
1679                 return;
1680         default:
1681                 ps = color_mode_to_bpp(color_mode) / 8;
1682                 break;
1683         }
1684
1685         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1686                         width, height);
1687
1688         /* width & height are overlay sizes, convert to fb sizes */
1689
1690         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1691                 fbw = width;
1692                 fbh = height;
1693         } else {
1694                 fbw = height;
1695                 fbh = width;
1696         }
1697
1698         /*
1699          * field 0 = even field = bottom field
1700          * field 1 = odd field = top field
1701          */
1702         switch (rotation + mirror * 4) {
1703         case OMAP_DSS_ROT_0:
1704                 *offset1 = 0;
1705                 if (field_offset)
1706                         *offset0 = *offset1 + field_offset * screen_width * ps;
1707                 else
1708                         *offset0 = *offset1;
1709                 *row_inc = pixinc(1 +
1710                         (y_predecim * screen_width - fbw * x_predecim) +
1711                         (fieldmode ? screen_width : 0), ps);
1712                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1713                         color_mode == OMAP_DSS_COLOR_UYVY)
1714                         *pix_inc = pixinc(x_predecim, 2 * ps);
1715                 else
1716                         *pix_inc = pixinc(x_predecim, ps);
1717                 break;
1718         case OMAP_DSS_ROT_90:
1719                 *offset1 = screen_width * (fbh - 1) * ps;
1720                 if (field_offset)
1721                         *offset0 = *offset1 + field_offset * ps;
1722                 else
1723                         *offset0 = *offset1;
1724                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1725                                 y_predecim + (fieldmode ? 1 : 0), ps);
1726                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1727                 break;
1728         case OMAP_DSS_ROT_180:
1729                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1730                 if (field_offset)
1731                         *offset0 = *offset1 - field_offset * screen_width * ps;
1732                 else
1733                         *offset0 = *offset1;
1734                 *row_inc = pixinc(-1 -
1735                         (y_predecim * screen_width - fbw * x_predecim) -
1736                         (fieldmode ? screen_width : 0), ps);
1737                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1738                         color_mode == OMAP_DSS_COLOR_UYVY)
1739                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1740                 else
1741                         *pix_inc = pixinc(-x_predecim, ps);
1742                 break;
1743         case OMAP_DSS_ROT_270:
1744                 *offset1 = (fbw - 1) * ps;
1745                 if (field_offset)
1746                         *offset0 = *offset1 - field_offset * ps;
1747                 else
1748                         *offset0 = *offset1;
1749                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1750                                 y_predecim - (fieldmode ? 1 : 0), ps);
1751                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1752                 break;
1753
1754         /* mirroring */
1755         case OMAP_DSS_ROT_0 + 4:
1756                 *offset1 = (fbw - 1) * ps;
1757                 if (field_offset)
1758                         *offset0 = *offset1 + field_offset * screen_width * ps;
1759                 else
1760                         *offset0 = *offset1;
1761                 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
1762                                 (fieldmode ? screen_width : 0),
1763                                 ps);
1764                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1765                         color_mode == OMAP_DSS_COLOR_UYVY)
1766                         *pix_inc = pixinc(-x_predecim, 2 * ps);
1767                 else
1768                         *pix_inc = pixinc(-x_predecim, ps);
1769                 break;
1770
1771         case OMAP_DSS_ROT_90 + 4:
1772                 *offset1 = 0;
1773                 if (field_offset)
1774                         *offset0 = *offset1 + field_offset * ps;
1775                 else
1776                         *offset0 = *offset1;
1777                 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1778                                 y_predecim + (fieldmode ? 1 : 0),
1779                                 ps);
1780                 *pix_inc = pixinc(x_predecim * screen_width, ps);
1781                 break;
1782
1783         case OMAP_DSS_ROT_180 + 4:
1784                 *offset1 = screen_width * (fbh - 1) * ps;
1785                 if (field_offset)
1786                         *offset0 = *offset1 - field_offset * screen_width * ps;
1787                 else
1788                         *offset0 = *offset1;
1789                 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
1790                                 (fieldmode ? screen_width : 0),
1791                                 ps);
1792                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1793                         color_mode == OMAP_DSS_COLOR_UYVY)
1794                         *pix_inc = pixinc(x_predecim, 2 * ps);
1795                 else
1796                         *pix_inc = pixinc(x_predecim, ps);
1797                 break;
1798
1799         case OMAP_DSS_ROT_270 + 4:
1800                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1801                 if (field_offset)
1802                         *offset0 = *offset1 - field_offset * ps;
1803                 else
1804                         *offset0 = *offset1;
1805                 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1806                                 y_predecim - (fieldmode ? 1 : 0),
1807                                 ps);
1808                 *pix_inc = pixinc(-x_predecim * screen_width, ps);
1809                 break;
1810
1811         default:
1812                 BUG();
1813                 return;
1814         }
1815 }
1816
1817 static void calc_tiler_rotation_offset(u16 screen_width, u16 width,
1818                 enum omap_color_mode color_mode, bool fieldmode,
1819                 unsigned int field_offset, unsigned *offset0, unsigned *offset1,
1820                 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
1821 {
1822         u8 ps;
1823
1824         switch (color_mode) {
1825         case OMAP_DSS_COLOR_CLUT1:
1826         case OMAP_DSS_COLOR_CLUT2:
1827         case OMAP_DSS_COLOR_CLUT4:
1828         case OMAP_DSS_COLOR_CLUT8:
1829                 BUG();
1830                 return;
1831         default:
1832                 ps = color_mode_to_bpp(color_mode) / 8;
1833                 break;
1834         }
1835
1836         DSSDBG("scrw %d, width %d\n", screen_width, width);
1837
1838         /*
1839          * field 0 = even field = bottom field
1840          * field 1 = odd field = top field
1841          */
1842         *offset1 = 0;
1843         if (field_offset)
1844                 *offset0 = *offset1 + field_offset * screen_width * ps;
1845         else
1846                 *offset0 = *offset1;
1847         *row_inc = pixinc(1 + (y_predecim * screen_width - width * x_predecim) +
1848                         (fieldmode ? screen_width : 0), ps);
1849         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1850                 color_mode == OMAP_DSS_COLOR_UYVY)
1851                 *pix_inc = pixinc(x_predecim, 2 * ps);
1852         else
1853                 *pix_inc = pixinc(x_predecim, ps);
1854 }
1855
1856 /*
1857  * This function is used to avoid synclosts in OMAP3, because of some
1858  * undocumented horizontal position and timing related limitations.
1859  */
1860 static int check_horiz_timing_omap3(enum omap_channel channel,
1861                 const struct omap_video_timings *t, u16 pos_x,
1862                 u16 width, u16 height, u16 out_width, u16 out_height)
1863 {
1864         int DS = DIV_ROUND_UP(height, out_height);
1865         unsigned long nonactive, lclk, pclk;
1866         static const u8 limits[3] = { 8, 10, 20 };
1867         u64 val, blank;
1868         int i;
1869
1870         nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
1871         pclk = dispc_mgr_pclk_rate(channel);
1872         if (dispc_mgr_is_lcd(channel))
1873                 lclk = dispc_mgr_lclk_rate(channel);
1874         else
1875                 lclk = dispc_fclk_rate();
1876
1877         i = 0;
1878         if (out_height < height)
1879                 i++;
1880         if (out_width < width)
1881                 i++;
1882         blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
1883         DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1884         if (blank <= limits[i])
1885                 return -EINVAL;
1886
1887         /*
1888          * Pixel data should be prepared before visible display point starts.
1889          * So, atleast DS-2 lines must have already been fetched by DISPC
1890          * during nonactive - pos_x period.
1891          */
1892         val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1893         DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1894                 val, max(0, DS - 2) * width);
1895         if (val < max(0, DS - 2) * width)
1896                 return -EINVAL;
1897
1898         /*
1899          * All lines need to be refilled during the nonactive period of which
1900          * only one line can be loaded during the active period. So, atleast
1901          * DS - 1 lines should be loaded during nonactive period.
1902          */
1903         val =  div_u64((u64)nonactive * lclk, pclk);
1904         DSSDBG("nonactive * pcd  = %llu, max(0, DS - 1) * width = %d\n",
1905                 val, max(0, DS - 1) * width);
1906         if (val < max(0, DS - 1) * width)
1907                 return -EINVAL;
1908
1909         return 0;
1910 }
1911
1912 static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
1913                 const struct omap_video_timings *mgr_timings, u16 width,
1914                 u16 height, u16 out_width, u16 out_height,
1915                 enum omap_color_mode color_mode)
1916 {
1917         u32 core_clk = 0;
1918         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1919
1920         if (height <= out_height && width <= out_width)
1921                 return (unsigned long) pclk;
1922
1923         if (height > out_height) {
1924                 unsigned int ppl = mgr_timings->x_res;
1925
1926                 tmp = pclk * height * out_width;
1927                 do_div(tmp, 2 * out_height * ppl);
1928                 core_clk = tmp;
1929
1930                 if (height > 2 * out_height) {
1931                         if (ppl == out_width)
1932                                 return 0;
1933
1934                         tmp = pclk * (height - 2 * out_height) * out_width;
1935                         do_div(tmp, 2 * out_height * (ppl - out_width));
1936                         core_clk = max_t(u32, core_clk, tmp);
1937                 }
1938         }
1939
1940         if (width > out_width) {
1941                 tmp = pclk * width;
1942                 do_div(tmp, out_width);
1943                 core_clk = max_t(u32, core_clk, tmp);
1944
1945                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1946                         core_clk <<= 1;
1947         }
1948
1949         return core_clk;
1950 }
1951
1952 static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
1953                 u16 height, u16 out_width, u16 out_height)
1954 {
1955         unsigned int hf, vf;
1956         unsigned long pclk = dispc_mgr_pclk_rate(channel);
1957
1958         /*
1959          * FIXME how to determine the 'A' factor
1960          * for the no downscaling case ?
1961          */
1962
1963         if (width > 3 * out_width)
1964                 hf = 4;
1965         else if (width > 2 * out_width)
1966                 hf = 3;
1967         else if (width > out_width)
1968                 hf = 2;
1969         else
1970                 hf = 1;
1971
1972         if (height > out_height)
1973                 vf = 2;
1974         else
1975                 vf = 1;
1976
1977         if (cpu_is_omap24xx()) {
1978                 if (vf > 1 && hf > 1)
1979                         return pclk * 4;
1980                 else
1981                         return pclk * 2;
1982         } else if (cpu_is_omap34xx()) {
1983                 return pclk * vf * hf;
1984         } else {
1985                 if (hf > 1)
1986                         return DIV_ROUND_UP(pclk, out_width) * width;
1987                 else
1988                         return pclk;
1989         }
1990 }
1991
1992 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1993                 enum omap_channel channel,
1994                 const struct omap_video_timings *mgr_timings,
1995                 u16 width, u16 height, u16 out_width, u16 out_height,
1996                 enum omap_color_mode color_mode, bool *five_taps,
1997                 int *x_predecim, int *y_predecim, u16 pos_x)
1998 {
1999         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2000         const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
2001         const int maxsinglelinewidth =
2002                                 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
2003         const int max_decim_limit = 16;
2004         unsigned long core_clk = 0;
2005         int decim_x, decim_y, error, min_factor;
2006         u16 in_width, in_height, in_width_max = 0;
2007
2008         if (width == out_width && height == out_height)
2009                 return 0;
2010
2011         if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
2012                 return -EINVAL;
2013
2014         *x_predecim = max_decim_limit;
2015         *y_predecim = max_decim_limit;
2016
2017         if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
2018             color_mode == OMAP_DSS_COLOR_CLUT2 ||
2019             color_mode == OMAP_DSS_COLOR_CLUT4 ||
2020             color_mode == OMAP_DSS_COLOR_CLUT8) {
2021                 *x_predecim = 1;
2022                 *y_predecim = 1;
2023                 *five_taps = false;
2024                 return 0;
2025         }
2026
2027         decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
2028         decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
2029
2030         min_factor = min(decim_x, decim_y);
2031
2032         if (decim_x > *x_predecim || out_width > width * 8)
2033                 return -EINVAL;
2034
2035         if (decim_y > *y_predecim || out_height > height * 8)
2036                 return -EINVAL;
2037
2038         if (cpu_is_omap24xx()) {
2039                 *five_taps = false;
2040
2041                 do {
2042                         in_height = DIV_ROUND_UP(height, decim_y);
2043                         in_width = DIV_ROUND_UP(width, decim_x);
2044                         core_clk = calc_core_clk(channel, in_width, in_height,
2045                                         out_width, out_height);
2046                         error = (in_width > maxsinglelinewidth || !core_clk ||
2047                                 core_clk > dispc_core_clk_rate());
2048                         if (error) {
2049                                 if (decim_x == decim_y) {
2050                                         decim_x = min_factor;
2051                                         decim_y++;
2052                                 } else {
2053                                         swap(decim_x, decim_y);
2054                                         if (decim_x < decim_y)
2055                                                 decim_x++;
2056                                 }
2057                         }
2058                 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
2059                                 error);
2060
2061                 if (in_width > maxsinglelinewidth) {
2062                         DSSERR("Cannot scale max input width exceeded");
2063                         return -EINVAL;
2064                 }
2065         } else if (cpu_is_omap34xx()) {
2066
2067                 do {
2068                         in_height = DIV_ROUND_UP(height, decim_y);
2069                         in_width = DIV_ROUND_UP(width, decim_x);
2070                         core_clk = calc_core_clk_five_taps(channel, mgr_timings,
2071                                 in_width, in_height, out_width, out_height,
2072                                 color_mode);
2073
2074                         error = check_horiz_timing_omap3(channel, mgr_timings,
2075                                 pos_x, in_width, in_height, out_width,
2076                                 out_height);
2077
2078                         if (in_width > maxsinglelinewidth)
2079                                 if (in_height > out_height &&
2080                                         in_height < out_height * 2)
2081                                         *five_taps = false;
2082                         if (!*five_taps)
2083                                 core_clk = calc_core_clk(channel, in_width,
2084                                         in_height, out_width, out_height);
2085                         error = (error || in_width > maxsinglelinewidth * 2 ||
2086                                 (in_width > maxsinglelinewidth && *five_taps) ||
2087                                 !core_clk || core_clk > dispc_core_clk_rate());
2088                         if (error) {
2089                                 if (decim_x == decim_y) {
2090                                         decim_x = min_factor;
2091                                         decim_y++;
2092                                 } else {
2093                                         swap(decim_x, decim_y);
2094                                         if (decim_x < decim_y)
2095                                                 decim_x++;
2096                                 }
2097                         }
2098                 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
2099                         && error);
2100
2101                 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
2102                         height, out_width, out_height)){
2103                                 DSSERR("horizontal timing too tight\n");
2104                                 return -EINVAL;
2105                 }
2106
2107                 if (in_width > (maxsinglelinewidth * 2)) {
2108                         DSSERR("Cannot setup scaling");
2109                         DSSERR("width exceeds maximum width possible");
2110                         return -EINVAL;
2111                 }
2112
2113                 if (in_width > maxsinglelinewidth && *five_taps) {
2114                         DSSERR("cannot setup scaling with five taps");
2115                         return -EINVAL;
2116                 }
2117         } else {
2118                 int decim_x_min = decim_x;
2119                 in_height = DIV_ROUND_UP(height, decim_y);
2120                 in_width_max = dispc_core_clk_rate() /
2121                                 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
2122                                                 out_width);
2123                 decim_x = DIV_ROUND_UP(width, in_width_max);
2124
2125                 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
2126                 if (decim_x > *x_predecim)
2127                         return -EINVAL;
2128
2129                 do {
2130                         in_width = DIV_ROUND_UP(width, decim_x);
2131                 } while (decim_x <= *x_predecim &&
2132                                 in_width > maxsinglelinewidth && decim_x++);
2133
2134                 if (in_width > maxsinglelinewidth) {
2135                         DSSERR("Cannot scale width exceeds max line width");
2136                         return -EINVAL;
2137                 }
2138
2139                 core_clk = calc_core_clk(channel, in_width, in_height,
2140                                 out_width, out_height);
2141         }
2142
2143         DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2144         DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
2145
2146         if (!core_clk || core_clk > dispc_core_clk_rate()) {
2147                 DSSERR("failed to set up scaling, "
2148                         "required core clk rate = %lu Hz, "
2149                         "current core clk rate = %lu Hz\n",
2150                         core_clk, dispc_core_clk_rate());
2151                 return -EINVAL;
2152         }
2153
2154         *x_predecim = decim_x;
2155         *y_predecim = decim_y;
2156         return 0;
2157 }
2158
2159 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
2160                 bool ilace, bool replication,
2161                 const struct omap_video_timings *mgr_timings)
2162 {
2163         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
2164         bool five_taps = true;
2165         bool fieldmode = 0;
2166         int r, cconv = 0;
2167         unsigned offset0, offset1;
2168         s32 row_inc;
2169         s32 pix_inc;
2170         u16 frame_height = oi->height;
2171         unsigned int field_offset = 0;
2172         u16 in_height = oi->height;
2173         u16 in_width = oi->width;
2174         u16 out_width, out_height;
2175         enum omap_channel channel;
2176         int x_predecim = 1, y_predecim = 1;
2177
2178         channel = dispc_ovl_get_channel_out(plane);
2179
2180         DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
2181                 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2182                 plane, oi->paddr, oi->p_uv_addr,
2183                 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2184                 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
2185                 oi->mirror, ilace, channel, replication);
2186
2187         if (oi->paddr == 0)
2188                 return -EINVAL;
2189
2190         out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2191         out_height = oi->out_height == 0 ? oi->height : oi->out_height;
2192
2193         if (ilace && oi->height == out_height)
2194                 fieldmode = 1;
2195
2196         if (ilace) {
2197                 if (fieldmode)
2198                         in_height /= 2;
2199                 oi->pos_y /= 2;
2200                 out_height /= 2;
2201
2202                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2203                                 "out_height %d\n",
2204                                 in_height, oi->pos_y, out_height);
2205         }
2206
2207         if (!dss_feat_color_mode_supported(plane, oi->color_mode))
2208                 return -EINVAL;
2209
2210         r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2211                         in_height, out_width, out_height, oi->color_mode,
2212                         &five_taps, &x_predecim, &y_predecim, oi->pos_x);
2213         if (r)
2214                 return r;
2215
2216         in_width = DIV_ROUND_UP(in_width, x_predecim);
2217         in_height = DIV_ROUND_UP(in_height, y_predecim);
2218
2219         if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2220                         oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2221                         oi->color_mode == OMAP_DSS_COLOR_NV12)
2222                 cconv = 1;
2223
2224         if (ilace && !fieldmode) {
2225                 /*
2226                  * when downscaling the bottom field may have to start several
2227                  * source lines below the top field. Unfortunately ACCUI
2228                  * registers will only hold the fractional part of the offset
2229                  * so the integer part must be added to the base address of the
2230                  * bottom field.
2231                  */
2232                 if (!in_height || in_height == out_height)
2233                         field_offset = 0;
2234                 else
2235                         field_offset = in_height / out_height / 2;
2236         }
2237
2238         /* Fields are independent but interleaved in memory. */
2239         if (fieldmode)
2240                 field_offset = 1;
2241
2242         offset0 = 0;
2243         offset1 = 0;
2244         row_inc = 0;
2245         pix_inc = 0;
2246
2247         if (oi->rotation_type == OMAP_DSS_ROT_TILER)
2248                 calc_tiler_rotation_offset(oi->screen_width, in_width,
2249                                 oi->color_mode, fieldmode, field_offset,
2250                                 &offset0, &offset1, &row_inc, &pix_inc,
2251                                 x_predecim, y_predecim);
2252         else if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2253                 calc_dma_rotation_offset(oi->rotation, oi->mirror,
2254                                 oi->screen_width, in_width, frame_height,
2255                                 oi->color_mode, fieldmode, field_offset,
2256                                 &offset0, &offset1, &row_inc, &pix_inc,
2257                                 x_predecim, y_predecim);
2258         else
2259                 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
2260                                 oi->screen_width, in_width, frame_height,
2261                                 oi->color_mode, fieldmode, field_offset,
2262                                 &offset0, &offset1, &row_inc, &pix_inc,
2263                                 x_predecim, y_predecim);
2264
2265         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2266                         offset0, offset1, row_inc, pix_inc);
2267
2268         dispc_ovl_set_color_mode(plane, oi->color_mode);
2269
2270         dispc_ovl_configure_burst_type(plane, oi->rotation_type);
2271
2272         dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2273         dispc_ovl_set_ba1(plane, oi->paddr + offset1);
2274
2275         if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2276                 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2277                 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
2278         }
2279
2280
2281         dispc_ovl_set_row_inc(plane, row_inc);
2282         dispc_ovl_set_pix_inc(plane, pix_inc);
2283
2284         DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2285                         in_height, out_width, out_height);
2286
2287         dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
2288
2289         dispc_ovl_set_pic_size(plane, in_width, in_height);
2290
2291         if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
2292                 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2293                                    out_height, ilace, five_taps, fieldmode,
2294                                    oi->color_mode, oi->rotation);
2295                 dispc_ovl_set_vid_size(plane, out_width, out_height);
2296                 dispc_ovl_set_vid_color_conv(plane, cconv);
2297         }
2298
2299         dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2300                         oi->color_mode);
2301
2302         dispc_ovl_set_zorder(plane, oi->zorder);
2303         dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2304         dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
2305
2306         dispc_ovl_enable_replication(plane, replication);
2307
2308         return 0;
2309 }
2310
2311 int dispc_ovl_enable(enum omap_plane plane, bool enable)
2312 {
2313         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2314
2315         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
2316
2317         return 0;
2318 }
2319
2320 static void dispc_disable_isr(void *data, u32 mask)
2321 {
2322         struct completion *compl = data;
2323         complete(compl);
2324 }
2325
2326 static void _enable_lcd_out(enum omap_channel channel, bool enable)
2327 {
2328         mgr_fld_write(channel, DISPC_MGR_FLD_ENABLE, enable);
2329         /* flush posted write */
2330         mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2331 }
2332
2333 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
2334 {
2335         struct completion frame_done_completion;
2336         bool is_on;
2337         int r;
2338         u32 irq;
2339
2340         /* When we disable LCD output, we need to wait until frame is done.
2341          * Otherwise the DSS is still working, and turning off the clocks
2342          * prevents DSS from going to OFF mode */
2343         is_on = mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2344
2345         irq = mgr_desc[channel].framedone_irq;
2346
2347         if (!enable && is_on) {
2348                 init_completion(&frame_done_completion);
2349
2350                 r = omap_dispc_register_isr(dispc_disable_isr,
2351                                 &frame_done_completion, irq);
2352
2353                 if (r)
2354                         DSSERR("failed to register FRAMEDONE isr\n");
2355         }
2356
2357         _enable_lcd_out(channel, enable);
2358
2359         if (!enable && is_on) {
2360                 if (!wait_for_completion_timeout(&frame_done_completion,
2361                                         msecs_to_jiffies(100)))
2362                         DSSERR("timeout waiting for FRAME DONE\n");
2363
2364                 r = omap_dispc_unregister_isr(dispc_disable_isr,
2365                                 &frame_done_completion, irq);
2366
2367                 if (r)
2368                         DSSERR("failed to unregister FRAMEDONE isr\n");
2369         }
2370 }
2371
2372 static void _enable_digit_out(bool enable)
2373 {
2374         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2375         /* flush posted write */
2376         dispc_read_reg(DISPC_CONTROL);
2377 }
2378
2379 static void dispc_mgr_enable_digit_out(bool enable)
2380 {
2381         struct completion frame_done_completion;
2382         enum dss_hdmi_venc_clk_source_select src;
2383         int r, i;
2384         u32 irq_mask;
2385         int num_irqs;
2386
2387         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2388                 return;
2389
2390         src = dss_get_hdmi_venc_clk_source();
2391
2392         if (enable) {
2393                 unsigned long flags;
2394                 /* When we enable digit output, we'll get an extra digit
2395                  * sync lost interrupt, that we need to ignore */
2396                 spin_lock_irqsave(&dispc.irq_lock, flags);
2397                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2398                 _omap_dispc_set_irqs();
2399                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2400         }
2401
2402         /* When we disable digit output, we need to wait until fields are done.
2403          * Otherwise the DSS is still working, and turning off the clocks
2404          * prevents DSS from going to OFF mode. And when enabling, we need to
2405          * wait for the extra sync losts */
2406         init_completion(&frame_done_completion);
2407
2408         if (src == DSS_HDMI_M_PCLK && enable == false) {
2409                 irq_mask = DISPC_IRQ_FRAMEDONETV;
2410                 num_irqs = 1;
2411         } else {
2412                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2413                 /* XXX I understand from TRM that we should only wait for the
2414                  * current field to complete. But it seems we have to wait for
2415                  * both fields */
2416                 num_irqs = 2;
2417         }
2418
2419         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2420                         irq_mask);
2421         if (r)
2422                 DSSERR("failed to register %x isr\n", irq_mask);
2423
2424         _enable_digit_out(enable);
2425
2426         for (i = 0; i < num_irqs; ++i) {
2427                 if (!wait_for_completion_timeout(&frame_done_completion,
2428                                         msecs_to_jiffies(100)))
2429                         DSSERR("timeout waiting for digit out to %s\n",
2430                                         enable ? "start" : "stop");
2431         }
2432
2433         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2434                         irq_mask);
2435         if (r)
2436                 DSSERR("failed to unregister %x isr\n", irq_mask);
2437
2438         if (enable) {
2439                 unsigned long flags;
2440                 spin_lock_irqsave(&dispc.irq_lock, flags);
2441                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2442                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2443                 _omap_dispc_set_irqs();
2444                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2445         }
2446 }
2447
2448 bool dispc_mgr_is_enabled(enum omap_channel channel)
2449 {
2450         return !!mgr_fld_read(channel, DISPC_MGR_FLD_ENABLE);
2451 }
2452
2453 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2454 {
2455         if (dispc_mgr_is_lcd(channel))
2456                 dispc_mgr_enable_lcd_out(channel, enable);
2457         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2458                 dispc_mgr_enable_digit_out(enable);
2459         else
2460                 BUG();
2461 }
2462
2463 void dispc_lcd_enable_signal_polarity(bool act_high)
2464 {
2465         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2466                 return;
2467
2468         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2469 }
2470
2471 void dispc_lcd_enable_signal(bool enable)
2472 {
2473         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2474                 return;
2475
2476         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2477 }
2478
2479 void dispc_pck_free_enable(bool enable)
2480 {
2481         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2482                 return;
2483
2484         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2485 }
2486
2487 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2488 {
2489         mgr_fld_write(channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable);
2490 }
2491
2492
2493 void dispc_mgr_set_lcd_type_tft(enum omap_channel channel)
2494 {
2495         mgr_fld_write(channel, DISPC_MGR_FLD_STNTFT, 1);
2496 }
2497
2498 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2499 {
2500         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2501 }
2502
2503
2504 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2505 {
2506         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2507 }
2508
2509 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2510                 enum omap_dss_trans_key_type type,
2511                 u32 trans_key)
2512 {
2513         mgr_fld_write(ch, DISPC_MGR_FLD_TCKSELECTION, type);
2514
2515         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2516 }
2517
2518 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2519 {
2520         mgr_fld_write(ch, DISPC_MGR_FLD_TCKENABLE, enable);
2521 }
2522
2523 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2524                 bool enable)
2525 {
2526         if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2527                 return;
2528
2529         if (ch == OMAP_DSS_CHANNEL_LCD)
2530                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2531         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2532                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2533 }
2534
2535 void dispc_mgr_setup(enum omap_channel channel,
2536                 struct omap_overlay_manager_info *info)
2537 {
2538         dispc_mgr_set_default_color(channel, info->default_color);
2539         dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2540         dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2541         dispc_mgr_enable_alpha_fixed_zorder(channel,
2542                         info->partial_alpha_enabled);
2543         if (dss_has_feature(FEAT_CPR)) {
2544                 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2545                 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2546         }
2547 }
2548
2549 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2550 {
2551         int code;
2552
2553         switch (data_lines) {
2554         case 12:
2555                 code = 0;
2556                 break;
2557         case 16:
2558                 code = 1;
2559                 break;
2560         case 18:
2561                 code = 2;
2562                 break;
2563         case 24:
2564                 code = 3;
2565                 break;
2566         default:
2567                 BUG();
2568                 return;
2569         }
2570
2571         mgr_fld_write(channel, DISPC_MGR_FLD_TFTDATALINES, code);
2572 }
2573
2574 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2575 {
2576         u32 l;
2577         int gpout0, gpout1;
2578
2579         switch (mode) {
2580         case DSS_IO_PAD_MODE_RESET:
2581                 gpout0 = 0;
2582                 gpout1 = 0;
2583                 break;
2584         case DSS_IO_PAD_MODE_RFBI:
2585                 gpout0 = 1;
2586                 gpout1 = 0;
2587                 break;
2588         case DSS_IO_PAD_MODE_BYPASS:
2589                 gpout0 = 1;
2590                 gpout1 = 1;
2591                 break;
2592         default:
2593                 BUG();
2594                 return;
2595         }
2596
2597         l = dispc_read_reg(DISPC_CONTROL);
2598         l = FLD_MOD(l, gpout0, 15, 15);
2599         l = FLD_MOD(l, gpout1, 16, 16);
2600         dispc_write_reg(DISPC_CONTROL, l);
2601 }
2602
2603 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2604 {
2605         mgr_fld_write(channel, DISPC_MGR_FLD_STALLMODE, enable);
2606 }
2607
2608 static bool _dispc_mgr_size_ok(u16 width, u16 height)
2609 {
2610         return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2611                 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2612 }
2613
2614 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2615                 int vsw, int vfp, int vbp)
2616 {
2617         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2618                 if (hsw < 1 || hsw > 64 ||
2619                                 hfp < 1 || hfp > 256 ||
2620                                 hbp < 1 || hbp > 256 ||
2621                                 vsw < 1 || vsw > 64 ||
2622                                 vfp < 0 || vfp > 255 ||
2623                                 vbp < 0 || vbp > 255)
2624                         return false;
2625         } else {
2626                 if (hsw < 1 || hsw > 256 ||
2627                                 hfp < 1 || hfp > 4096 ||
2628                                 hbp < 1 || hbp > 4096 ||
2629                                 vsw < 1 || vsw > 256 ||
2630                                 vfp < 0 || vfp > 4095 ||
2631                                 vbp < 0 || vbp > 4095)
2632                         return false;
2633         }
2634
2635         return true;
2636 }
2637
2638 bool dispc_mgr_timings_ok(enum omap_channel channel,
2639                 const struct omap_video_timings *timings)
2640 {
2641         bool timings_ok;
2642
2643         timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2644
2645         if (dispc_mgr_is_lcd(channel))
2646                 timings_ok =  timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2647                                                 timings->hfp, timings->hbp,
2648                                                 timings->vsw, timings->vfp,
2649                                                 timings->vbp);
2650
2651         return timings_ok;
2652 }
2653
2654 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2655                 int hfp, int hbp, int vsw, int vfp, int vbp)
2656 {
2657         u32 timing_h, timing_v;
2658
2659         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2660                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2661                         FLD_VAL(hbp-1, 27, 20);
2662
2663                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2664                         FLD_VAL(vbp, 27, 20);
2665         } else {
2666                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2667                         FLD_VAL(hbp-1, 31, 20);
2668
2669                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2670                         FLD_VAL(vbp, 31, 20);
2671         }
2672
2673         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2674         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2675 }
2676
2677 /* change name to mode? */
2678 void dispc_mgr_set_timings(enum omap_channel channel,
2679                 struct omap_video_timings *timings)
2680 {
2681         unsigned xtot, ytot;
2682         unsigned long ht, vt;
2683         struct omap_video_timings t = *timings;
2684
2685         DSSDBG("channel %d xres %u yres %u\n", channel, t.x_res, t.y_res);
2686
2687         if (!dispc_mgr_timings_ok(channel, &t)) {
2688                 BUG();
2689                 return;
2690         }
2691
2692         if (dispc_mgr_is_lcd(channel)) {
2693                 _dispc_mgr_set_lcd_timings(channel, t.hsw, t.hfp, t.hbp, t.vsw,
2694                                 t.vfp, t.vbp);
2695
2696                 xtot = t.x_res + t.hfp + t.hsw + t.hbp;
2697                 ytot = t.y_res + t.vfp + t.vsw + t.vbp;
2698
2699                 ht = (timings->pixel_clock * 1000) / xtot;
2700                 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2701
2702                 DSSDBG("pck %u\n", timings->pixel_clock);
2703                 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2704                         t.hsw, t.hfp, t.hbp, t.vsw, t.vfp, t.vbp);
2705
2706                 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2707         } else {
2708                 enum dss_hdmi_venc_clk_source_select source;
2709
2710                 source = dss_get_hdmi_venc_clk_source();
2711
2712                 if (source == DSS_VENC_TV_CLK)
2713                         t.y_res /= 2;
2714         }
2715
2716         dispc_mgr_set_size(channel, t.x_res, t.y_res);
2717 }
2718
2719 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2720                 u16 pck_div)
2721 {
2722         BUG_ON(lck_div < 1);
2723         BUG_ON(pck_div < 1);
2724
2725         dispc_write_reg(DISPC_DIVISORo(channel),
2726                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2727 }
2728
2729 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2730                 int *pck_div)
2731 {
2732         u32 l;
2733         l = dispc_read_reg(DISPC_DIVISORo(channel));
2734         *lck_div = FLD_GET(l, 23, 16);
2735         *pck_div = FLD_GET(l, 7, 0);
2736 }
2737
2738 unsigned long dispc_fclk_rate(void)
2739 {
2740         struct platform_device *dsidev;
2741         unsigned long r = 0;
2742
2743         switch (dss_get_dispc_clk_source()) {
2744         case OMAP_DSS_CLK_SRC_FCK:
2745                 r = clk_get_rate(dispc.dss_clk);
2746                 break;
2747         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2748                 dsidev = dsi_get_dsidev_from_id(0);
2749                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2750                 break;
2751         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2752                 dsidev = dsi_get_dsidev_from_id(1);
2753                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2754                 break;
2755         default:
2756                 BUG();
2757                 return 0;
2758         }
2759
2760         return r;
2761 }
2762
2763 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2764 {
2765         struct platform_device *dsidev;
2766         int lcd;
2767         unsigned long r;
2768         u32 l;
2769
2770         l = dispc_read_reg(DISPC_DIVISORo(channel));
2771
2772         lcd = FLD_GET(l, 23, 16);
2773
2774         switch (dss_get_lcd_clk_source(channel)) {
2775         case OMAP_DSS_CLK_SRC_FCK:
2776                 r = clk_get_rate(dispc.dss_clk);
2777                 break;
2778         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2779                 dsidev = dsi_get_dsidev_from_id(0);
2780                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2781                 break;
2782         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2783                 dsidev = dsi_get_dsidev_from_id(1);
2784                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2785                 break;
2786         default:
2787                 BUG();
2788                 return 0;
2789         }
2790
2791         return r / lcd;
2792 }
2793
2794 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2795 {
2796         unsigned long r;
2797
2798         if (dispc_mgr_is_lcd(channel)) {
2799                 int pcd;
2800                 u32 l;
2801
2802                 l = dispc_read_reg(DISPC_DIVISORo(channel));
2803
2804                 pcd = FLD_GET(l, 7, 0);
2805
2806                 r = dispc_mgr_lclk_rate(channel);
2807
2808                 return r / pcd;
2809         } else {
2810                 enum dss_hdmi_venc_clk_source_select source;
2811
2812                 source = dss_get_hdmi_venc_clk_source();
2813
2814                 switch (source) {
2815                 case DSS_VENC_TV_CLK:
2816                         return venc_get_pixel_clock();
2817                 case DSS_HDMI_M_PCLK:
2818                         return hdmi_get_pixel_clock();
2819                 default:
2820                         BUG();
2821                         return 0;
2822                 }
2823         }
2824 }
2825
2826 unsigned long dispc_core_clk_rate(void)
2827 {
2828         int lcd;
2829         unsigned long fclk = dispc_fclk_rate();
2830
2831         if (dss_has_feature(FEAT_CORE_CLK_DIV))
2832                 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2833         else
2834                 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2835
2836         return fclk / lcd;
2837 }
2838
2839 static void dispc_dump_clocks_channel(struct seq_file *s, enum omap_channel channel)
2840 {
2841         int lcd, pcd;
2842         enum omap_dss_clk_source lcd_clk_src;
2843
2844         seq_printf(s, "- %s -\n", mgr_desc[channel].name);
2845
2846         lcd_clk_src = dss_get_lcd_clk_source(channel);
2847
2848         seq_printf(s, "%s clk source = %s (%s)\n", mgr_desc[channel].name,
2849                 dss_get_generic_clk_source_name(lcd_clk_src),
2850                 dss_feat_get_clk_source_name(lcd_clk_src));
2851
2852         dispc_mgr_get_lcd_divisor(channel, &lcd, &pcd);
2853
2854         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2855                 dispc_mgr_lclk_rate(channel), lcd);
2856         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2857                 dispc_mgr_pclk_rate(channel), pcd);
2858 }
2859
2860 void dispc_dump_clocks(struct seq_file *s)
2861 {
2862         int lcd;
2863         u32 l;
2864         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2865
2866         if (dispc_runtime_get())
2867                 return;
2868
2869         seq_printf(s, "- DISPC -\n");
2870
2871         seq_printf(s, "dispc fclk source = %s (%s)\n",
2872                         dss_get_generic_clk_source_name(dispc_clk_src),
2873                         dss_feat_get_clk_source_name(dispc_clk_src));
2874
2875         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2876
2877         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2878                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2879                 l = dispc_read_reg(DISPC_DIVISOR);
2880                 lcd = FLD_GET(l, 23, 16);
2881
2882                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2883                                 (dispc_fclk_rate()/lcd), lcd);
2884         }
2885
2886         dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD);
2887
2888         if (dss_has_feature(FEAT_MGR_LCD2))
2889                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD2);
2890         if (dss_has_feature(FEAT_MGR_LCD3))
2891                 dispc_dump_clocks_channel(s, OMAP_DSS_CHANNEL_LCD3);
2892
2893         dispc_runtime_put();
2894 }
2895
2896 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2897 void dispc_dump_irqs(struct seq_file *s)
2898 {
2899         unsigned long flags;
2900         struct dispc_irq_stats stats;
2901
2902         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2903
2904         stats = dispc.irq_stats;
2905         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2906         dispc.irq_stats.last_reset = jiffies;
2907
2908         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2909
2910         seq_printf(s, "period %u ms\n",
2911                         jiffies_to_msecs(jiffies - stats.last_reset));
2912
2913         seq_printf(s, "irqs %d\n", stats.irq_count);
2914 #define PIS(x) \
2915         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2916
2917         PIS(FRAMEDONE);
2918         PIS(VSYNC);
2919         PIS(EVSYNC_EVEN);
2920         PIS(EVSYNC_ODD);
2921         PIS(ACBIAS_COUNT_STAT);
2922         PIS(PROG_LINE_NUM);
2923         PIS(GFX_FIFO_UNDERFLOW);
2924         PIS(GFX_END_WIN);
2925         PIS(PAL_GAMMA_MASK);
2926         PIS(OCP_ERR);
2927         PIS(VID1_FIFO_UNDERFLOW);
2928         PIS(VID1_END_WIN);
2929         PIS(VID2_FIFO_UNDERFLOW);
2930         PIS(VID2_END_WIN);
2931         if (dss_feat_get_num_ovls() > 3) {
2932                 PIS(VID3_FIFO_UNDERFLOW);
2933                 PIS(VID3_END_WIN);
2934         }
2935         PIS(SYNC_LOST);
2936         PIS(SYNC_LOST_DIGIT);
2937         PIS(WAKEUP);
2938         if (dss_has_feature(FEAT_MGR_LCD2)) {
2939                 PIS(FRAMEDONE2);
2940                 PIS(VSYNC2);
2941                 PIS(ACBIAS_COUNT_STAT2);
2942                 PIS(SYNC_LOST2);
2943         }
2944         if (dss_has_feature(FEAT_MGR_LCD3)) {
2945                 PIS(FRAMEDONE3);
2946                 PIS(VSYNC3);
2947                 PIS(ACBIAS_COUNT_STAT3);
2948                 PIS(SYNC_LOST3);
2949         }
2950 #undef PIS
2951 }
2952 #endif
2953
2954 static void dispc_dump_regs(struct seq_file *s)
2955 {
2956         int i, j;
2957         const char *mgr_names[] = {
2958                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2959                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2960                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2961                 [OMAP_DSS_CHANNEL_LCD3]         = "LCD3",
2962         };
2963         const char *ovl_names[] = {
2964                 [OMAP_DSS_GFX]          = "GFX",
2965                 [OMAP_DSS_VIDEO1]       = "VID1",
2966                 [OMAP_DSS_VIDEO2]       = "VID2",
2967                 [OMAP_DSS_VIDEO3]       = "VID3",
2968         };
2969         const char **p_names;
2970
2971 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2972
2973         if (dispc_runtime_get())
2974                 return;
2975
2976         /* DISPC common registers */
2977         DUMPREG(DISPC_REVISION);
2978         DUMPREG(DISPC_SYSCONFIG);
2979         DUMPREG(DISPC_SYSSTATUS);
2980         DUMPREG(DISPC_IRQSTATUS);
2981         DUMPREG(DISPC_IRQENABLE);
2982         DUMPREG(DISPC_CONTROL);
2983         DUMPREG(DISPC_CONFIG);
2984         DUMPREG(DISPC_CAPABLE);
2985         DUMPREG(DISPC_LINE_STATUS);
2986         DUMPREG(DISPC_LINE_NUMBER);
2987         if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2988                         dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2989                 DUMPREG(DISPC_GLOBAL_ALPHA);
2990         if (dss_has_feature(FEAT_MGR_LCD2)) {
2991                 DUMPREG(DISPC_CONTROL2);
2992                 DUMPREG(DISPC_CONFIG2);
2993         }
2994         if (dss_has_feature(FEAT_MGR_LCD3)) {
2995                 DUMPREG(DISPC_CONTROL3);
2996                 DUMPREG(DISPC_CONFIG3);
2997         }
2998
2999 #undef DUMPREG
3000
3001 #define DISPC_REG(i, name) name(i)
3002 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
3003         48 - strlen(#r) - strlen(p_names[i]), " ", \
3004         dispc_read_reg(DISPC_REG(i, r)))
3005
3006         p_names = mgr_names;
3007
3008         /* DISPC channel specific registers */
3009         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
3010                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3011                 DUMPREG(i, DISPC_TRANS_COLOR);
3012                 DUMPREG(i, DISPC_SIZE_MGR);
3013
3014                 if (i == OMAP_DSS_CHANNEL_DIGIT)
3015                         continue;
3016
3017                 DUMPREG(i, DISPC_DEFAULT_COLOR);
3018                 DUMPREG(i, DISPC_TRANS_COLOR);
3019                 DUMPREG(i, DISPC_TIMING_H);
3020                 DUMPREG(i, DISPC_TIMING_V);
3021                 DUMPREG(i, DISPC_POL_FREQ);
3022                 DUMPREG(i, DISPC_DIVISORo);
3023                 DUMPREG(i, DISPC_SIZE_MGR);
3024
3025                 DUMPREG(i, DISPC_DATA_CYCLE1);
3026                 DUMPREG(i, DISPC_DATA_CYCLE2);
3027                 DUMPREG(i, DISPC_DATA_CYCLE3);
3028
3029                 if (dss_has_feature(FEAT_CPR)) {
3030                         DUMPREG(i, DISPC_CPR_COEF_R);
3031                         DUMPREG(i, DISPC_CPR_COEF_G);
3032                         DUMPREG(i, DISPC_CPR_COEF_B);
3033                 }
3034         }
3035
3036         p_names = ovl_names;
3037
3038         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
3039                 DUMPREG(i, DISPC_OVL_BA0);
3040                 DUMPREG(i, DISPC_OVL_BA1);
3041                 DUMPREG(i, DISPC_OVL_POSITION);
3042                 DUMPREG(i, DISPC_OVL_SIZE);
3043                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
3044                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
3045                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
3046                 DUMPREG(i, DISPC_OVL_ROW_INC);
3047                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
3048                 if (dss_has_feature(FEAT_PRELOAD))
3049                         DUMPREG(i, DISPC_OVL_PRELOAD);
3050
3051                 if (i == OMAP_DSS_GFX) {
3052                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
3053                         DUMPREG(i, DISPC_OVL_TABLE_BA);
3054                         continue;
3055                 }
3056
3057                 DUMPREG(i, DISPC_OVL_FIR);
3058                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
3059                 DUMPREG(i, DISPC_OVL_ACCU0);
3060                 DUMPREG(i, DISPC_OVL_ACCU1);
3061                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3062                         DUMPREG(i, DISPC_OVL_BA0_UV);
3063                         DUMPREG(i, DISPC_OVL_BA1_UV);
3064                         DUMPREG(i, DISPC_OVL_FIR2);
3065                         DUMPREG(i, DISPC_OVL_ACCU2_0);
3066                         DUMPREG(i, DISPC_OVL_ACCU2_1);
3067                 }
3068                 if (dss_has_feature(FEAT_ATTR2))
3069                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
3070                 if (dss_has_feature(FEAT_PRELOAD))
3071                         DUMPREG(i, DISPC_OVL_PRELOAD);
3072         }
3073
3074 #undef DISPC_REG
3075 #undef DUMPREG
3076
3077 #define DISPC_REG(plane, name, i) name(plane, i)
3078 #define DUMPREG(plane, name, i) \
3079         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
3080         46 - strlen(#name) - strlen(p_names[plane]), " ", \
3081         dispc_read_reg(DISPC_REG(plane, name, i)))
3082
3083         /* Video pipeline coefficient registers */
3084
3085         /* start from OMAP_DSS_VIDEO1 */
3086         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
3087                 for (j = 0; j < 8; j++)
3088                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
3089
3090                 for (j = 0; j < 8; j++)
3091                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
3092
3093                 for (j = 0; j < 5; j++)
3094                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
3095
3096                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
3097                         for (j = 0; j < 8; j++)
3098                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
3099                 }
3100
3101                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
3102                         for (j = 0; j < 8; j++)
3103                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
3104
3105                         for (j = 0; j < 8; j++)
3106                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
3107
3108                         for (j = 0; j < 8; j++)
3109                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3110                 }
3111         }
3112
3113         dispc_runtime_put();
3114
3115 #undef DISPC_REG
3116 #undef DUMPREG
3117 }
3118
3119 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3120                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs)
3121 {
3122         u32 l = 0;
3123
3124         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d\n",
3125                         onoff, rf, ieo, ipc, ihs, ivs);
3126
3127         l |= FLD_VAL(onoff, 17, 17);
3128         l |= FLD_VAL(rf, 16, 16);
3129         l |= FLD_VAL(ieo, 15, 15);
3130         l |= FLD_VAL(ipc, 14, 14);
3131         l |= FLD_VAL(ihs, 13, 13);
3132         l |= FLD_VAL(ivs, 12, 12);
3133
3134         dispc_write_reg(DISPC_POL_FREQ(channel), l);
3135 }
3136
3137 void dispc_mgr_set_pol_freq(enum omap_channel channel,
3138                 enum omap_panel_config config)
3139 {
3140         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
3141                         (config & OMAP_DSS_LCD_RF) != 0,
3142                         (config & OMAP_DSS_LCD_IEO) != 0,
3143                         (config & OMAP_DSS_LCD_IPC) != 0,
3144                         (config & OMAP_DSS_LCD_IHS) != 0,
3145                         (config & OMAP_DSS_LCD_IVS) != 0);
3146 }
3147
3148 /* with fck as input clock rate, find dispc dividers that produce req_pck */
3149 void dispc_find_clk_divs(unsigned long req_pck, unsigned long fck,
3150                 struct dispc_clock_info *cinfo)
3151 {
3152         u16 pcd_min, pcd_max;
3153         unsigned long best_pck;
3154         u16 best_ld, cur_ld;
3155         u16 best_pd, cur_pd;
3156
3157         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3158         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3159
3160         best_pck = 0;
3161         best_ld = 0;
3162         best_pd = 0;
3163
3164         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3165                 unsigned long lck = fck / cur_ld;
3166
3167                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
3168                         unsigned long pck = lck / cur_pd;
3169                         long old_delta = abs(best_pck - req_pck);
3170                         long new_delta = abs(pck - req_pck);
3171
3172                         if (best_pck == 0 || new_delta < old_delta) {
3173                                 best_pck = pck;
3174                                 best_ld = cur_ld;
3175                                 best_pd = cur_pd;
3176
3177                                 if (pck == req_pck)
3178                                         goto found;
3179                         }
3180
3181                         if (pck < req_pck)
3182                                 break;
3183                 }
3184
3185                 if (lck / pcd_min < req_pck)
3186                         break;
3187         }
3188
3189 found:
3190         cinfo->lck_div = best_ld;
3191         cinfo->pck_div = best_pd;
3192         cinfo->lck = fck / cinfo->lck_div;
3193         cinfo->pck = cinfo->lck / cinfo->pck_div;
3194 }
3195
3196 /* calculate clock rates using dividers in cinfo */
3197 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3198                 struct dispc_clock_info *cinfo)
3199 {
3200         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3201                 return -EINVAL;
3202         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
3203                 return -EINVAL;
3204
3205         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3206         cinfo->pck = cinfo->lck / cinfo->pck_div;
3207
3208         return 0;
3209 }
3210
3211 int dispc_mgr_set_clock_div(enum omap_channel channel,
3212                 struct dispc_clock_info *cinfo)
3213 {
3214         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3215         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3216
3217         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
3218
3219         return 0;
3220 }
3221
3222 int dispc_mgr_get_clock_div(enum omap_channel channel,
3223                 struct dispc_clock_info *cinfo)
3224 {
3225         unsigned long fck;
3226
3227         fck = dispc_fclk_rate();
3228
3229         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3230         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
3231
3232         cinfo->lck = fck / cinfo->lck_div;
3233         cinfo->pck = cinfo->lck / cinfo->pck_div;
3234
3235         return 0;
3236 }
3237
3238 /* dispc.irq_lock has to be locked by the caller */
3239 static void _omap_dispc_set_irqs(void)
3240 {
3241         u32 mask;
3242         u32 old_mask;
3243         int i;
3244         struct omap_dispc_isr_data *isr_data;
3245
3246         mask = dispc.irq_error_mask;
3247
3248         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3249                 isr_data = &dispc.registered_isr[i];
3250
3251                 if (isr_data->isr == NULL)
3252                         continue;
3253
3254                 mask |= isr_data->mask;
3255         }
3256
3257         old_mask = dispc_read_reg(DISPC_IRQENABLE);
3258         /* clear the irqstatus for newly enabled irqs */
3259         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3260
3261         dispc_write_reg(DISPC_IRQENABLE, mask);
3262 }
3263
3264 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3265 {
3266         int i;
3267         int ret;
3268         unsigned long flags;
3269         struct omap_dispc_isr_data *isr_data;
3270
3271         if (isr == NULL)
3272                 return -EINVAL;
3273
3274         spin_lock_irqsave(&dispc.irq_lock, flags);
3275
3276         /* check for duplicate entry */
3277         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3278                 isr_data = &dispc.registered_isr[i];
3279                 if (isr_data->isr == isr && isr_data->arg == arg &&
3280                                 isr_data->mask == mask) {
3281                         ret = -EINVAL;
3282                         goto err;
3283                 }
3284         }
3285
3286         isr_data = NULL;
3287         ret = -EBUSY;
3288
3289         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3290                 isr_data = &dispc.registered_isr[i];
3291
3292                 if (isr_data->isr != NULL)
3293                         continue;
3294
3295                 isr_data->isr = isr;
3296                 isr_data->arg = arg;
3297                 isr_data->mask = mask;
3298                 ret = 0;
3299
3300                 break;
3301         }
3302
3303         if (ret)
3304                 goto err;
3305
3306         _omap_dispc_set_irqs();
3307
3308         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3309
3310         return 0;
3311 err:
3312         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3313
3314         return ret;
3315 }
3316 EXPORT_SYMBOL(omap_dispc_register_isr);
3317
3318 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3319 {
3320         int i;
3321         unsigned long flags;
3322         int ret = -EINVAL;
3323         struct omap_dispc_isr_data *isr_data;
3324
3325         spin_lock_irqsave(&dispc.irq_lock, flags);
3326
3327         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3328                 isr_data = &dispc.registered_isr[i];
3329                 if (isr_data->isr != isr || isr_data->arg != arg ||
3330                                 isr_data->mask != mask)
3331                         continue;
3332
3333                 /* found the correct isr */
3334
3335                 isr_data->isr = NULL;
3336                 isr_data->arg = NULL;
3337                 isr_data->mask = 0;
3338
3339                 ret = 0;
3340                 break;
3341         }
3342
3343         if (ret == 0)
3344                 _omap_dispc_set_irqs();
3345
3346         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3347
3348         return ret;
3349 }
3350 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3351
3352 #ifdef DEBUG
3353 static void print_irq_status(u32 status)
3354 {
3355         if ((status & dispc.irq_error_mask) == 0)
3356                 return;
3357
3358         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3359
3360 #define PIS(x) \
3361         if (status & DISPC_IRQ_##x) \
3362                 printk(#x " ");
3363         PIS(GFX_FIFO_UNDERFLOW);
3364         PIS(OCP_ERR);
3365         PIS(VID1_FIFO_UNDERFLOW);
3366         PIS(VID2_FIFO_UNDERFLOW);
3367         if (dss_feat_get_num_ovls() > 3)
3368                 PIS(VID3_FIFO_UNDERFLOW);
3369         PIS(SYNC_LOST);
3370         PIS(SYNC_LOST_DIGIT);
3371         if (dss_has_feature(FEAT_MGR_LCD2))
3372                 PIS(SYNC_LOST2);
3373         if (dss_has_feature(FEAT_MGR_LCD3))
3374                 PIS(SYNC_LOST3);
3375 #undef PIS
3376
3377         printk("\n");
3378 }
3379 #endif
3380
3381 /* Called from dss.c. Note that we don't touch clocks here,
3382  * but we presume they are on because we got an IRQ. However,
3383  * an irq handler may turn the clocks off, so we may not have
3384  * clock later in the function. */
3385 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3386 {
3387         int i;
3388         u32 irqstatus, irqenable;
3389         u32 handledirqs = 0;
3390         u32 unhandled_errors;
3391         struct omap_dispc_isr_data *isr_data;
3392         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3393
3394         spin_lock(&dispc.irq_lock);
3395
3396         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3397         irqenable = dispc_read_reg(DISPC_IRQENABLE);
3398
3399         /* IRQ is not for us */
3400         if (!(irqstatus & irqenable)) {
3401                 spin_unlock(&dispc.irq_lock);
3402                 return IRQ_NONE;
3403         }
3404
3405 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3406         spin_lock(&dispc.irq_stats_lock);
3407         dispc.irq_stats.irq_count++;
3408         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3409         spin_unlock(&dispc.irq_stats_lock);
3410 #endif
3411
3412 #ifdef DEBUG
3413         if (dss_debug)
3414                 print_irq_status(irqstatus);
3415 #endif
3416         /* Ack the interrupt. Do it here before clocks are possibly turned
3417          * off */
3418         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3419         /* flush posted write */
3420         dispc_read_reg(DISPC_IRQSTATUS);
3421
3422         /* make a copy and unlock, so that isrs can unregister
3423          * themselves */
3424         memcpy(registered_isr, dispc.registered_isr,
3425                         sizeof(registered_isr));
3426
3427         spin_unlock(&dispc.irq_lock);
3428
3429         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3430                 isr_data = &registered_isr[i];
3431
3432                 if (!isr_data->isr)
3433                         continue;
3434
3435                 if (isr_data->mask & irqstatus) {
3436                         isr_data->isr(isr_data->arg, irqstatus);
3437                         handledirqs |= isr_data->mask;
3438                 }
3439         }
3440
3441         spin_lock(&dispc.irq_lock);
3442
3443         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3444
3445         if (unhandled_errors) {
3446                 dispc.error_irqs |= unhandled_errors;
3447
3448                 dispc.irq_error_mask &= ~unhandled_errors;
3449                 _omap_dispc_set_irqs();
3450
3451                 schedule_work(&dispc.error_work);
3452         }
3453
3454         spin_unlock(&dispc.irq_lock);
3455
3456         return IRQ_HANDLED;
3457 }
3458
3459 static void dispc_error_worker(struct work_struct *work)
3460 {
3461         int i;
3462         u32 errors;
3463         unsigned long flags;
3464         static const unsigned fifo_underflow_bits[] = {
3465                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3466                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3467                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3468                 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3469         };
3470
3471         spin_lock_irqsave(&dispc.irq_lock, flags);
3472         errors = dispc.error_irqs;
3473         dispc.error_irqs = 0;
3474         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3475
3476         dispc_runtime_get();
3477
3478         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3479                 struct omap_overlay *ovl;
3480                 unsigned bit;
3481
3482                 ovl = omap_dss_get_overlay(i);
3483                 bit = fifo_underflow_bits[i];
3484
3485                 if (bit & errors) {
3486                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3487                                         ovl->name);
3488                         dispc_ovl_enable(ovl->id, false);
3489                         dispc_mgr_go(ovl->manager->id);
3490                         mdelay(50);
3491                 }
3492         }
3493
3494         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3495                 struct omap_overlay_manager *mgr;
3496                 unsigned bit;
3497
3498                 mgr = omap_dss_get_overlay_manager(i);
3499                 bit = mgr_desc[i].sync_lost_irq;
3500
3501                 if (bit & errors) {
3502                         struct omap_dss_device *dssdev = mgr->device;
3503                         bool enable;
3504
3505                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3506                                         "with video overlays disabled\n",
3507                                         mgr->name);
3508
3509                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3510                         dssdev->driver->disable(dssdev);
3511
3512                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3513                                 struct omap_overlay *ovl;
3514                                 ovl = omap_dss_get_overlay(i);
3515
3516                                 if (ovl->id != OMAP_DSS_GFX &&
3517                                                 ovl->manager == mgr)
3518                                         dispc_ovl_enable(ovl->id, false);
3519                         }
3520
3521                         dispc_mgr_go(mgr->id);
3522                         mdelay(50);
3523
3524                         if (enable)
3525                                 dssdev->driver->enable(dssdev);
3526                 }
3527         }
3528
3529         if (errors & DISPC_IRQ_OCP_ERR) {
3530                 DSSERR("OCP_ERR\n");
3531                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3532                         struct omap_overlay_manager *mgr;
3533                         mgr = omap_dss_get_overlay_manager(i);
3534                         if (mgr->device && mgr->device->driver)
3535                                 mgr->device->driver->disable(mgr->device);
3536                 }
3537         }
3538
3539         spin_lock_irqsave(&dispc.irq_lock, flags);
3540         dispc.irq_error_mask |= errors;
3541         _omap_dispc_set_irqs();
3542         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3543
3544         dispc_runtime_put();
3545 }
3546
3547 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3548 {
3549         void dispc_irq_wait_handler(void *data, u32 mask)
3550         {
3551                 complete((struct completion *)data);
3552         }
3553
3554         int r;
3555         DECLARE_COMPLETION_ONSTACK(completion);
3556
3557         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3558                         irqmask);
3559
3560         if (r)
3561                 return r;
3562
3563         timeout = wait_for_completion_timeout(&completion, timeout);
3564
3565         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3566
3567         if (timeout == 0)
3568                 return -ETIMEDOUT;
3569
3570         if (timeout == -ERESTARTSYS)
3571                 return -ERESTARTSYS;
3572
3573         return 0;
3574 }
3575
3576 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3577                 unsigned long timeout)
3578 {
3579         void dispc_irq_wait_handler(void *data, u32 mask)
3580         {
3581                 complete((struct completion *)data);
3582         }
3583
3584         int r;
3585         DECLARE_COMPLETION_ONSTACK(completion);
3586
3587         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3588                         irqmask);
3589
3590         if (r)
3591                 return r;
3592
3593         timeout = wait_for_completion_interruptible_timeout(&completion,
3594                         timeout);
3595
3596         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3597
3598         if (timeout == 0)
3599                 return -ETIMEDOUT;
3600
3601         if (timeout == -ERESTARTSYS)
3602                 return -ERESTARTSYS;
3603
3604         return 0;
3605 }
3606
3607 static void _omap_dispc_initialize_irq(void)
3608 {
3609         unsigned long flags;
3610
3611         spin_lock_irqsave(&dispc.irq_lock, flags);
3612
3613         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3614
3615         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3616         if (dss_has_feature(FEAT_MGR_LCD2))
3617                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3618         if (dss_has_feature(FEAT_MGR_LCD3))
3619                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST3;
3620         if (dss_feat_get_num_ovls() > 3)
3621                 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3622
3623         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3624          * so clear it */
3625         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3626
3627         _omap_dispc_set_irqs();
3628
3629         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3630 }
3631
3632 void dispc_enable_sidle(void)
3633 {
3634         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3635 }
3636
3637 void dispc_disable_sidle(void)
3638 {
3639         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3640 }
3641
3642 static void _omap_dispc_initial_config(void)
3643 {
3644         u32 l;
3645
3646         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3647         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3648                 l = dispc_read_reg(DISPC_DIVISOR);
3649                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3650                 l = FLD_MOD(l, 1, 0, 0);
3651                 l = FLD_MOD(l, 1, 23, 16);
3652                 dispc_write_reg(DISPC_DIVISOR, l);
3653         }
3654
3655         /* FUNCGATED */
3656         if (dss_has_feature(FEAT_FUNCGATED))
3657                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3658
3659         _dispc_setup_color_conv_coef();
3660
3661         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3662
3663         dispc_read_plane_fifo_sizes();
3664
3665         dispc_configure_burst_sizes();
3666
3667         dispc_ovl_enable_zorder_planes();
3668 }
3669
3670 /* DISPC HW IP initialisation */
3671 static int __init omap_dispchw_probe(struct platform_device *pdev)
3672 {
3673         u32 rev;
3674         int r = 0;
3675         struct resource *dispc_mem;
3676         struct clk *clk;
3677
3678         dispc.pdev = pdev;
3679
3680         spin_lock_init(&dispc.irq_lock);
3681
3682 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3683         spin_lock_init(&dispc.irq_stats_lock);
3684         dispc.irq_stats.last_reset = jiffies;
3685 #endif
3686
3687         INIT_WORK(&dispc.error_work, dispc_error_worker);
3688
3689         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3690         if (!dispc_mem) {
3691                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3692                 return -EINVAL;
3693         }
3694
3695         dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3696                                   resource_size(dispc_mem));
3697         if (!dispc.base) {
3698                 DSSERR("can't ioremap DISPC\n");
3699                 return -ENOMEM;
3700         }
3701
3702         dispc.irq = platform_get_irq(dispc.pdev, 0);
3703         if (dispc.irq < 0) {
3704                 DSSERR("platform_get_irq failed\n");
3705                 return -ENODEV;
3706         }
3707
3708         r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3709                              IRQF_SHARED, "OMAP DISPC", dispc.pdev);
3710         if (r < 0) {
3711                 DSSERR("request_irq failed\n");
3712                 return r;
3713         }
3714
3715         clk = clk_get(&pdev->dev, "fck");
3716         if (IS_ERR(clk)) {
3717                 DSSERR("can't get fck\n");
3718                 r = PTR_ERR(clk);
3719                 return r;
3720         }
3721
3722         dispc.dss_clk = clk;
3723
3724         pm_runtime_enable(&pdev->dev);
3725
3726         r = dispc_runtime_get();
3727         if (r)
3728                 goto err_runtime_get;
3729
3730         _omap_dispc_initial_config();
3731
3732         _omap_dispc_initialize_irq();
3733
3734         rev = dispc_read_reg(DISPC_REVISION);
3735         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3736                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3737
3738         dispc_runtime_put();
3739
3740         dss_debugfs_create_file("dispc", dispc_dump_regs);
3741
3742 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3743         dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3744 #endif
3745         return 0;
3746
3747 err_runtime_get:
3748         pm_runtime_disable(&pdev->dev);
3749         clk_put(dispc.dss_clk);
3750         return r;
3751 }
3752
3753 static int __exit omap_dispchw_remove(struct platform_device *pdev)
3754 {
3755         pm_runtime_disable(&pdev->dev);
3756
3757         clk_put(dispc.dss_clk);
3758
3759         return 0;
3760 }
3761
3762 static int dispc_runtime_suspend(struct device *dev)
3763 {
3764         dispc_save_context();
3765
3766         return 0;
3767 }
3768
3769 static int dispc_runtime_resume(struct device *dev)
3770 {
3771         dispc_restore_context();
3772
3773         return 0;
3774 }
3775
3776 static const struct dev_pm_ops dispc_pm_ops = {
3777         .runtime_suspend = dispc_runtime_suspend,
3778         .runtime_resume = dispc_runtime_resume,
3779 };
3780
3781 static struct platform_driver omap_dispchw_driver = {
3782         .remove         = __exit_p(omap_dispchw_remove),
3783         .driver         = {
3784                 .name   = "omapdss_dispc",
3785                 .owner  = THIS_MODULE,
3786                 .pm     = &dispc_pm_ops,
3787         },
3788 };
3789
3790 int __init dispc_init_platform_driver(void)
3791 {
3792         return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
3793 }
3794
3795 void __exit dispc_uninit_platform_driver(void)
3796 {
3797         platform_driver_unregister(&omap_dispchw_driver);
3798 }