eb6aa42be60eb8cf6413c9106e4c270f4ec4f4f2
[linux-3.10.git] / drivers / video / aty / atyfb_base.c
1 /*
2  *  ATI Frame Buffer Device Driver Core
3  *
4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
6  *      Copyright (C) 1998  Bernd Harries
7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
8  *
9  *  This driver supports the following ATI graphics chips:
10  *    - ATI Mach64
11  *
12  *  To do: add support for
13  *    - ATI Rage128 (from aty128fb.c)
14  *    - ATI Radeon (from radeonfb.c)
15  *
16  *  This driver is partly based on the PowerMac console driver:
17  *
18  *      Copyright (C) 1996 Paul Mackerras
19  *
20  *  and on the PowerMac ATI/mach64 display driver:
21  *
22  *      Copyright (C) 1997 Michael AK Tesch
23  *
24  *            with work by Jon Howell
25  *                         Harry AC Eaton
26  *                         Anthony Tong <atong@uiuc.edu>
27  *
28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
30  *
31  *  This file is subject to the terms and conditions of the GNU General Public
32  *  License. See the file COPYING in the main directory of this archive for
33  *  more details.
34  *
35  *  Many thanks to Nitya from ATI devrel for support and patience !
36  */
37
38 /******************************************************************************
39
40   TODO:
41
42     - cursor support on all cards and all ramdacs.
43     - cursor parameters controlable via ioctl()s.
44     - guess PLL and MCLK based on the original PLL register values initialized
45       by Open Firmware (if they are initialized). BIOS is done
46
47     (Anyone with Mac to help with this?)
48
49 ******************************************************************************/
50
51
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
58 #include <linux/mm.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
63 #include <linux/fb.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
69
70 #include <asm/io.h>
71 #include <asm/uaccess.h>
72
73 #include <video/mach64.h>
74 #include "atyfb.h"
75 #include "ati_ids.h"
76
77 #ifdef __powerpc__
78 #include <asm/machdep.h>
79 #include <asm/prom.h>
80 #include "../macmodes.h"
81 #endif
82 #ifdef __sparc__
83 #include <asm/pbm.h>
84 #include <asm/fbio.h>
85 #endif
86
87 #ifdef CONFIG_ADB_PMU
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
90 #endif
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
93 #endif
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
96 #endif
97 #ifdef CONFIG_MTRR
98 #include <asm/mtrr.h>
99 #endif
100
101 /*
102  * Debug flags.
103  */
104 #undef DEBUG
105 /*#define DEBUG*/
106
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /*  - must be large enough to catch all GUI-Regs   */
109 /*  - must be aligned to a PAGE boundary           */
110 #define GUI_RESERVE     (1 * PAGE_SIZE)
111
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114         if (!(var->activate & FB_ACTIVATE_TEST)) \
115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
116         return -EINVAL; \
117 } while (0)
118 #define FAIL_MAX(msg, x, _max_) do { \
119         if (x > _max_) { \
120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
122                 return -EINVAL; \
123         } \
124 } while (0)
125 #ifdef DEBUG
126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
127 #else
128 #define DPRINTK(fmt, args...)
129 #endif
130
131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
133
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
135 static const u32 lt_lcd_regs[] = {
136         CONFIG_PANEL_LG,
137         LCD_GEN_CNTL_LG,
138         DSTN_CONTROL_LG,
139         HFB_PITCH_ADDR_LG,
140         HORZ_STRETCHING_LG,
141         VERT_STRETCHING_LG,
142         0, /* EXT_VERT_STRETCH */
143         LT_GIO_LG,
144         POWER_MANAGEMENT_LG
145 };
146
147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
148 {
149         if (M64_HAS(LT_LCD_REGS)) {
150                 aty_st_le32(lt_lcd_regs[index], val, par);
151         } else {
152                 unsigned long temp;
153
154                 /* write addr byte */
155                 temp = aty_ld_le32(LCD_INDEX, par);
156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
157                 /* write the register value */
158                 aty_st_le32(LCD_DATA, val, par);
159         }
160 }
161
162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
163 {
164         if (M64_HAS(LT_LCD_REGS)) {
165                 return aty_ld_le32(lt_lcd_regs[index], par);
166         } else {
167                 unsigned long temp;
168
169                 /* write addr byte */
170                 temp = aty_ld_le32(LCD_INDEX, par);
171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
172                 /* read the register value */
173                 return aty_ld_le32(LCD_DATA, par);
174         }
175 }
176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
177
178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
179 /*
180  * ATIReduceRatio --
181  *
182  * Reduce a fraction by factoring out the largest common divider of the
183  * fraction's numerator and denominator.
184  */
185 static void ATIReduceRatio(int *Numerator, int *Denominator)
186 {
187     int Multiplier, Divider, Remainder;
188
189     Multiplier = *Numerator;
190     Divider = *Denominator;
191
192     while ((Remainder = Multiplier % Divider))
193     {
194         Multiplier = Divider;
195         Divider = Remainder;
196     }
197
198     *Numerator /= Divider;
199     *Denominator /= Divider;
200 }
201 #endif
202     /*
203      *  The Hardware parameters for each card
204      */
205
206 struct aty_cmap_regs {
207         u8 windex;
208         u8 lut;
209         u8 mask;
210         u8 rindex;
211         u8 cntl;
212 };
213
214 struct pci_mmap_map {
215         unsigned long voff;
216         unsigned long poff;
217         unsigned long size;
218         unsigned long prot_flag;
219         unsigned long prot_mask;
220 };
221
222 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
223         .id             = "ATY Mach64",
224         .type           = FB_TYPE_PACKED_PIXELS,
225         .visual         = FB_VISUAL_PSEUDOCOLOR,
226         .xpanstep       = 8,
227         .ypanstep       = 1,
228 };
229
230     /*
231      *  Frame buffer device API
232      */
233
234 static int atyfb_open(struct fb_info *info, int user);
235 static int atyfb_release(struct fb_info *info, int user);
236 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
237 static int atyfb_set_par(struct fb_info *info);
238 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
239         u_int transp, struct fb_info *info);
240 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
241 static int atyfb_blank(int blank, struct fb_info *info);
242 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
246 #ifdef __sparc__
247 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
248 #endif
249 static int atyfb_sync(struct fb_info *info);
250
251     /*
252      *  Internal routines
253      */
254
255 static int aty_init(struct fb_info *info, const char *name);
256 #ifdef CONFIG_ATARI
257 static int store_video_par(char *videopar, unsigned char m64_num);
258 #endif
259
260 static struct crtc saved_crtc;
261 static union aty_pll saved_pll;
262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
263
264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
268 #ifdef CONFIG_PPC
269 static int read_aty_sense(const struct atyfb_par *par);
270 #endif
271
272
273     /*
274      *  Interface used by the world
275      */
276
277 static struct fb_var_screeninfo default_var = {
278         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
279         640, 480, 640, 480, 0, 0, 8, 0,
280         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
281         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
282         0, FB_VMODE_NONINTERLACED
283 };
284
285 static struct fb_videomode defmode = {
286         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
287         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
288         0, FB_VMODE_NONINTERLACED
289 };
290
291 static struct fb_ops atyfb_ops = {
292         .owner          = THIS_MODULE,
293         .fb_open        = atyfb_open,
294         .fb_release     = atyfb_release,
295         .fb_check_var   = atyfb_check_var,
296         .fb_set_par     = atyfb_set_par,
297         .fb_setcolreg   = atyfb_setcolreg,
298         .fb_pan_display = atyfb_pan_display,
299         .fb_blank       = atyfb_blank,
300         .fb_ioctl       = atyfb_ioctl,
301         .fb_fillrect    = atyfb_fillrect,
302         .fb_copyarea    = atyfb_copyarea,
303         .fb_imageblit   = atyfb_imageblit,
304 #ifdef __sparc__
305         .fb_mmap        = atyfb_mmap,
306 #endif
307         .fb_sync        = atyfb_sync,
308 };
309
310 static int noaccel;
311 #ifdef CONFIG_MTRR
312 static int nomtrr;
313 #endif
314 static int vram;
315 static int pll;
316 static int mclk;
317 static int xclk;
318 static int comp_sync __initdata = -1;
319 static char *mode;
320
321 #ifdef CONFIG_PPC
322 static int default_vmode __initdata = VMODE_CHOOSE;
323 static int default_cmode __initdata = CMODE_CHOOSE;
324
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
329 #endif
330
331 #ifdef CONFIG_ATARI
332 static unsigned int mach64_count __initdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
336 #endif
337
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX   (M64F_GX)
340 #define ATI_CHIP_88800CX   (M64F_GX)
341
342 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
344
345 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
347
348 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
351
352 /* FIXME what is this chip? */
353 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
354
355 /* make sets shorter */
356 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
357
358 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359 /*#define ATI_CHIP_264GTDVD  ?*/
360 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
361
362 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
363 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
364 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
365
366 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
367 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
368
369 static struct {
370         u16 pci_id;
371         const char *name;
372         int pll, mclk, xclk, ecp_max;
373         u32 features;
374 } aty_chips[] __devinitdata = {
375 #ifdef CONFIG_FB_ATY_GX
376         /* Mach64 GX */
377         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
378         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
379 #endif /* CONFIG_FB_ATY_GX */
380
381 #ifdef CONFIG_FB_ATY_CT
382         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
383         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
384
385         /* FIXME what is this chip? */
386         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
387
388         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
389         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
390
391         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
392         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
393
394         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
395
396         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
397
398         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
402
403         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
406         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
407         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
408
409         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
410         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
412         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
413         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
414
415         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
416         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
418         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
420         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
421
422         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 #endif /* CONFIG_FB_ATY_CT */
427 };
428
429 /* can not fail */
430 static int __devinit correct_chipset(struct atyfb_par *par)
431 {
432         u8 rev;
433         u16 type;
434         u32 chip_id;
435         const char *name;
436         int i;
437
438         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
439                 if (par->pci_id == aty_chips[i].pci_id)
440                         break;
441
442         name = aty_chips[i].name;
443         par->pll_limits.pll_max = aty_chips[i].pll;
444         par->pll_limits.mclk = aty_chips[i].mclk;
445         par->pll_limits.xclk = aty_chips[i].xclk;
446         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
447         par->features = aty_chips[i].features;
448
449         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
450         type = chip_id & CFG_CHIP_TYPE;
451         rev = (chip_id & CFG_CHIP_REV) >> 24;
452
453         switch(par->pci_id) {
454 #ifdef CONFIG_FB_ATY_GX
455         case PCI_CHIP_MACH64GX:
456                 if(type != 0x00d7)
457                         return -ENODEV;
458                 break;
459         case PCI_CHIP_MACH64CX:
460                 if(type != 0x0057)
461                         return -ENODEV;
462                 break;
463 #endif
464 #ifdef CONFIG_FB_ATY_CT
465         case PCI_CHIP_MACH64VT:
466                 switch (rev & 0x07) {
467                 case 0x00:
468                         switch (rev & 0xc0) {
469                         case 0x00:
470                                 name = "ATI264VT (A3) (Mach64 VT)";
471                                 par->pll_limits.pll_max = 170;
472                                 par->pll_limits.mclk = 67;
473                                 par->pll_limits.xclk = 67;
474                                 par->pll_limits.ecp_max = 80;
475                                 par->features = ATI_CHIP_264VT;
476                                 break;
477                         case 0x40:
478                                 name = "ATI264VT2 (A4) (Mach64 VT)";
479                                 par->pll_limits.pll_max = 200;
480                                 par->pll_limits.mclk = 67;
481                                 par->pll_limits.xclk = 67;
482                                 par->pll_limits.ecp_max = 80;
483                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
484                                 break;
485                         }
486                         break;
487                 case 0x01:
488                         name = "ATI264VT3 (B1) (Mach64 VT)";
489                         par->pll_limits.pll_max = 200;
490                         par->pll_limits.mclk = 67;
491                         par->pll_limits.xclk = 67;
492                         par->pll_limits.ecp_max = 80;
493                         par->features = ATI_CHIP_264VTB;
494                         break;
495                 case 0x02:
496                         name = "ATI264VT3 (B2) (Mach64 VT)";
497                         par->pll_limits.pll_max = 200;
498                         par->pll_limits.mclk = 67;
499                         par->pll_limits.xclk = 67;
500                         par->pll_limits.ecp_max = 80;
501                         par->features = ATI_CHIP_264VT3;
502                         break;
503                 }
504                 break;
505         case PCI_CHIP_MACH64GT:
506                 switch (rev & 0x07) {
507                 case 0x01:
508                         name = "3D RAGE II (Mach64 GT)";
509                         par->pll_limits.pll_max = 170;
510                         par->pll_limits.mclk = 67;
511                         par->pll_limits.xclk = 67;
512                         par->pll_limits.ecp_max = 80;
513                         par->features = ATI_CHIP_264GTB;
514                         break;
515                 case 0x02:
516                         name = "3D RAGE II+ (Mach64 GT)";
517                         par->pll_limits.pll_max = 200;
518                         par->pll_limits.mclk = 67;
519                         par->pll_limits.xclk = 67;
520                         par->pll_limits.ecp_max = 100;
521                         par->features = ATI_CHIP_264GTB;
522                         break;
523                 }
524                 break;
525 #endif
526         }
527
528         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
529         return 0;
530 }
531
532 static char ram_dram[] __devinitdata = "DRAM";
533 static char ram_resv[] __devinitdata = "RESV";
534 #ifdef CONFIG_FB_ATY_GX
535 static char ram_vram[] __devinitdata = "VRAM";
536 #endif /* CONFIG_FB_ATY_GX */
537 #ifdef CONFIG_FB_ATY_CT
538 static char ram_edo[] __devinitdata = "EDO";
539 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
540 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
541 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
542 static char ram_off[] __devinitdata = "OFF";
543 #endif /* CONFIG_FB_ATY_CT */
544
545
546 static u32 pseudo_palette[17];
547
548 #ifdef CONFIG_FB_ATY_GX
549 static char *aty_gx_ram[8] __devinitdata = {
550         ram_dram, ram_vram, ram_vram, ram_dram,
551         ram_dram, ram_vram, ram_vram, ram_resv
552 };
553 #endif /* CONFIG_FB_ATY_GX */
554
555 #ifdef CONFIG_FB_ATY_CT
556 static char *aty_ct_ram[8] __devinitdata = {
557         ram_off, ram_dram, ram_edo, ram_edo,
558         ram_sdram, ram_sgram, ram_sdram32, ram_resv
559 };
560 #endif /* CONFIG_FB_ATY_CT */
561
562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
563 {
564         u32 pixclock = var->pixclock;
565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
566         u32 lcd_on_off;
567         par->pll.ct.xres = 0;
568         if (par->lcd_table != 0) {
569                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
570                 if(lcd_on_off & LCD_ON) {
571                         par->pll.ct.xres = var->xres;
572                         pixclock = par->lcd_pixclock;
573                 }
574         }
575 #endif
576         return pixclock;
577 }
578
579 #if defined(CONFIG_PPC)
580
581 /*
582  *  Apple monitor sense
583  */
584
585 static int __init read_aty_sense(const struct atyfb_par *par)
586 {
587         int sense, i;
588
589         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
590         __delay(200);
591         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
592         __delay(2000);
593         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
594         sense = ((i & 0x3000) >> 3) | (i & 0x100);
595
596         /* drive each sense line low in turn and collect the other 2 */
597         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
598         __delay(2000);
599         i = aty_ld_le32(GP_IO, par);
600         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
601         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
602         __delay(200);
603
604         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
605         __delay(2000);
606         i = aty_ld_le32(GP_IO, par);
607         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
608         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
609         __delay(200);
610
611         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
612         __delay(2000);
613         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
614         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
615         return sense;
616 }
617
618 #endif /* defined(CONFIG_PPC) */
619
620 /* ------------------------------------------------------------------------- */
621
622 /*
623  *  CRTC programming
624  */
625
626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
627 {
628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
629         if (par->lcd_table != 0) {
630                 if(!M64_HAS(LT_LCD_REGS)) {
631                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
632                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
633                 }
634                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
635                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
636
637
638                 /* switch to non shadow registers */
639                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
640                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
641
642                 /* save stretching */
643                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
644                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
645                 if (!M64_HAS(LT_LCD_REGS))
646                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
647         }
648 #endif
649         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
650         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
651         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
652         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
653         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
654         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
655         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
656
657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
658         if (par->lcd_table != 0) {
659                 /* switch to shadow registers */
660                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
661                         SHADOW_EN | SHADOW_RW_EN, par);
662
663                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
664                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
665                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
666                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
667
668                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
669         }
670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
671 }
672
673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
674 {
675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
676         if (par->lcd_table != 0) {
677                 /* stop CRTC */
678                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
679
680                 /* update non-shadow registers first */
681                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
682                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
683                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
684
685                 /* temporarily disable stretching */
686                 aty_st_lcd(HORZ_STRETCHING,
687                         crtc->horz_stretching &
688                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
689                 aty_st_lcd(VERT_STRETCHING,
690                         crtc->vert_stretching &
691                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
692                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
693         }
694 #endif
695         /* turn off CRT */
696         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
697
698         DPRINTK("setting up CRTC\n");
699         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
700             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
701             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
702             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
703
704         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
705         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
706         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
707         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
708         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
709         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
710         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
711
712         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
713         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
714         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
715         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
716         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
717         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
718
719         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
720 #if 0
721         FIXME
722         if (par->accel_flags & FB_ACCELF_TEXT)
723                 aty_init_engine(par, info);
724 #endif
725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
726         /* after setting the CRTC registers we should set the LCD registers. */
727         if (par->lcd_table != 0) {
728                 /* switch to shadow registers */
729                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
730                         (SHADOW_EN | SHADOW_RW_EN), par);
731
732                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
733                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
734                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
735
736                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
737                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
738                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
739                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
740
741                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
742                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
743                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
744                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
745
746                 /* restore CRTC selection & shadow state and enable stretching */
747                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
748                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
749                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
750                 if(!M64_HAS(LT_LCD_REGS))
751                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
752
753                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
754                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
755                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
756                 if(!M64_HAS(LT_LCD_REGS)) {
757                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
758                     aty_ld_le32(LCD_INDEX, par);
759                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
760                 }
761         }
762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
763 }
764
765 static int aty_var_to_crtc(const struct fb_info *info,
766         const struct fb_var_screeninfo *var, struct crtc *crtc)
767 {
768         struct atyfb_par *par = (struct atyfb_par *) info->par;
769         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
770         u32 sync, vmode, vdisplay;
771         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
772         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
773         u32 pix_width, dp_pix_width, dp_chain_mask;
774
775         /* input */
776         xres = var->xres;
777         yres = var->yres;
778         vxres = var->xres_virtual;
779         vyres = var->yres_virtual;
780         xoffset = var->xoffset;
781         yoffset = var->yoffset;
782         bpp = var->bits_per_pixel;
783         if (bpp == 16)
784                 bpp = (var->green.length == 5) ? 15 : 16;
785         sync = var->sync;
786         vmode = var->vmode;
787
788         /* convert (and round up) and validate */
789         if (vxres < xres + xoffset)
790                 vxres = xres + xoffset;
791         h_disp = xres;
792
793         if (vyres < yres + yoffset)
794                 vyres = yres + yoffset;
795         v_disp = yres;
796
797         if (bpp <= 8) {
798                 bpp = 8;
799                 pix_width = CRTC_PIX_WIDTH_8BPP;
800                 dp_pix_width =
801                     HOST_8BPP | SRC_8BPP | DST_8BPP |
802                     BYTE_ORDER_LSB_TO_MSB;
803                 dp_chain_mask = DP_CHAIN_8BPP;
804         } else if (bpp <= 15) {
805                 bpp = 16;
806                 pix_width = CRTC_PIX_WIDTH_15BPP;
807                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
808                     BYTE_ORDER_LSB_TO_MSB;
809                 dp_chain_mask = DP_CHAIN_15BPP;
810         } else if (bpp <= 16) {
811                 bpp = 16;
812                 pix_width = CRTC_PIX_WIDTH_16BPP;
813                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
814                     BYTE_ORDER_LSB_TO_MSB;
815                 dp_chain_mask = DP_CHAIN_16BPP;
816         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
817                 bpp = 24;
818                 pix_width = CRTC_PIX_WIDTH_24BPP;
819                 dp_pix_width =
820                     HOST_8BPP | SRC_8BPP | DST_8BPP |
821                     BYTE_ORDER_LSB_TO_MSB;
822                 dp_chain_mask = DP_CHAIN_24BPP;
823         } else if (bpp <= 32) {
824                 bpp = 32;
825                 pix_width = CRTC_PIX_WIDTH_32BPP;
826                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
827                     BYTE_ORDER_LSB_TO_MSB;
828                 dp_chain_mask = DP_CHAIN_32BPP;
829         } else
830                 FAIL("invalid bpp");
831
832         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
833                 FAIL("not enough video RAM");
834
835         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
836         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
837
838         if((xres > 1600) || (yres > 1200)) {
839                 FAIL("MACH64 chips are designed for max 1600x1200\n"
840                 "select anoter resolution.");
841         }
842         h_sync_strt = h_disp + var->right_margin;
843         h_sync_end = h_sync_strt + var->hsync_len;
844         h_sync_dly  = var->right_margin & 7;
845         h_total = h_sync_end + h_sync_dly + var->left_margin;
846
847         v_sync_strt = v_disp + var->lower_margin;
848         v_sync_end = v_sync_strt + var->vsync_len;
849         v_total = v_sync_end + var->upper_margin;
850
851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
852         if (par->lcd_table != 0) {
853                 if(!M64_HAS(LT_LCD_REGS)) {
854                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
855                     crtc->lcd_index = lcd_index &
856                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
857                     aty_st_le32(LCD_INDEX, lcd_index, par);
858                 }
859
860                 if (!M64_HAS(MOBIL_BUS))
861                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
862
863                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
864                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
865
866                 crtc->lcd_gen_cntl &=
867                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
868                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
869                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
870                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
871
872                 if((crtc->lcd_gen_cntl & LCD_ON) &&
873                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
874                         /* We cannot display the mode on the LCD. If the CRT is enabled
875                            we can turn off the LCD.
876                            If the CRT is off, it isn't a good idea to switch it on; we don't
877                            know if one is connected. So it's better to fail then.
878                          */
879                         if (crtc->lcd_gen_cntl & CRT_ON) {
880                                 if (!(var->activate & FB_ACTIVATE_TEST))
881                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
882                                 crtc->lcd_gen_cntl &= ~LCD_ON;
883                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
884                         } else {
885                                 if (!(var->activate & FB_ACTIVATE_TEST))
886                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
887                                 return -EINVAL;
888                         }
889                 }
890         }
891
892         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
893                 int VScan = 1;
894                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
895                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
896                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
897
898                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
899
900                 /* This is horror! When we simulate, say 640x480 on an 800x600
901                    LCD monitor, the CRTC should be programmed 800x600 values for
902                    the non visible part, but 640x480 for the visible part.
903                    This code has been tested on a laptop with it's 1400x1050 LCD
904                    monitor and a conventional monitor both switched on.
905                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
906                     works with little glitches also with DOUBLESCAN modes
907                  */
908                 if (yres < par->lcd_height) {
909                         VScan = par->lcd_height / yres;
910                         if(VScan > 1) {
911                                 VScan = 2;
912                                 vmode |= FB_VMODE_DOUBLE;
913                         }
914                 }
915
916                 h_sync_strt = h_disp + par->lcd_right_margin;
917                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
918                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
919                 h_total = h_disp + par->lcd_hblank_len;
920
921                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
922                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
923                 v_total = v_disp + par->lcd_vblank_len / VScan;
924         }
925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
926
927         h_disp = (h_disp >> 3) - 1;
928         h_sync_strt = (h_sync_strt >> 3) - 1;
929         h_sync_end = (h_sync_end >> 3) - 1;
930         h_total = (h_total >> 3) - 1;
931         h_sync_wid = h_sync_end - h_sync_strt;
932
933         FAIL_MAX("h_disp too large", h_disp, 0xff);
934         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
935         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
936         if(h_sync_wid > 0x1f)
937                 h_sync_wid = 0x1f;
938         FAIL_MAX("h_total too large", h_total, 0x1ff);
939
940         if (vmode & FB_VMODE_DOUBLE) {
941                 v_disp <<= 1;
942                 v_sync_strt <<= 1;
943                 v_sync_end <<= 1;
944                 v_total <<= 1;
945         }
946
947         vdisplay = yres;
948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
949         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
950                 vdisplay  = par->lcd_height;
951 #endif
952
953         v_disp--;
954         v_sync_strt--;
955         v_sync_end--;
956         v_total--;
957         v_sync_wid = v_sync_end - v_sync_strt;
958
959         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
960         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
961         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
962         if(v_sync_wid > 0x1f)
963                 v_sync_wid = 0x1f;
964         FAIL_MAX("v_total too large", v_total, 0x7ff);
965
966         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
967
968         /* output */
969         crtc->vxres = vxres;
970         crtc->vyres = vyres;
971         crtc->xoffset = xoffset;
972         crtc->yoffset = yoffset;
973         crtc->bpp = bpp;
974         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
975         crtc->vline_crnt_vline = 0;
976
977         crtc->h_tot_disp = h_total | (h_disp<<16);
978         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
979                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
980         crtc->v_tot_disp = v_total | (v_disp<<16);
981         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
982
983         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
984         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
985         crtc->gen_cntl |= CRTC_VGA_LINEAR;
986
987         /* Enable doublescan mode if requested */
988         if (vmode & FB_VMODE_DOUBLE)
989                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
990         /* Enable interlaced mode if requested */
991         if (vmode & FB_VMODE_INTERLACED)
992                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
994         if (par->lcd_table != 0) {
995                 vdisplay = yres;
996                 if(vmode & FB_VMODE_DOUBLE)
997                         vdisplay <<= 1;
998                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
999                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1003
1004                 /* MOBILITY M1 tested, FIXME: LT */
1005                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006                 if (!M64_HAS(LT_LCD_REGS))
1007                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1009
1010                 crtc->horz_stretching &=
1011                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1014                         do {
1015                                 /*
1016                                 * The horizontal blender misbehaves when HDisplay is less than a
1017                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1018                                 * stretch such modes enough.  Use pixel replication instead of
1019                                 * blending to stretch modes that can be made to exactly fit the
1020                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1021                                 * pixel-replicated mode to be slightly wider or narrower than the
1022                                 * panel width.  It also causes a mode that is exactly half as wide
1023                                 * as the panel to be pixel-replicated, rather than blended.
1024                                 */
1025                                 int HDisplay  = xres & ~7;
1026                                 int nStretch  = par->lcd_width / HDisplay;
1027                                 int Remainder = par->lcd_width % HDisplay;
1028
1029                                 if ((!Remainder && ((nStretch > 2))) ||
1030                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1031                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032                                         int horz_stretch_loop = -1, BestRemainder;
1033                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1034                                         int Index = 5;
1035                                         ATIReduceRatio(&Numerator, &Denominator);
1036
1037                                         BestRemainder = (Numerator * 16) / Denominator;
1038                                         while (--Index >= 0) {
1039                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1040                                                         Denominator;
1041                                                 if (Remainder < BestRemainder) {
1042                                                         horz_stretch_loop = Index;
1043                                                         if (!(BestRemainder = Remainder))
1044                                                                 break;
1045                                                 }
1046                                         }
1047
1048                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1050                                                 int reuse_previous = 1;
1051
1052                                                 Index = StretchLoops[horz_stretch_loop];
1053
1054                                                 while (--Index >= 0) {
1055                                                         if (Accumulator > 0)
1056                                                                 horz_stretch_ratio |= reuse_previous;
1057                                                         else
1058                                                                 Accumulator += Denominator;
1059                                                         Accumulator -= Numerator;
1060                                                         reuse_previous <<= 1;
1061                                                 }
1062
1063                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066                                                 break;      /* Out of the do { ... } while (0) */
1067                                         }
1068                                 }
1069
1070                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1072                         } while (0);
1073                 }
1074
1075                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1078
1079                         if (!M64_HAS(LT_LCD_REGS) &&
1080                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1082                 } else {
1083                         /*
1084                          * Don't use vertical blending if the mode is too wide or not
1085                          * vertically stretched.
1086                          */
1087                         crtc->vert_stretching = 0;
1088                 }
1089                 /* copy to shadow crtc */
1090                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1094         }
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1096
1097         if (M64_HAS(MAGIC_FIFO)) {
1098                 /* FIXME: display FIFO low watermark values */
1099                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1100         }
1101         crtc->dp_pix_width = dp_pix_width;
1102         crtc->dp_chain_mask = dp_chain_mask;
1103
1104         return 0;
1105 }
1106
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1108 {
1109         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1111             h_sync_pol;
1112         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1113         u32 pix_width;
1114         u32 double_scan, interlace;
1115
1116         /* input */
1117         h_total = crtc->h_tot_disp & 0x1ff;
1118         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123         v_total = crtc->v_tot_disp & 0x7ff;
1124         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1132
1133         /* convert */
1134         xres = (h_disp + 1) * 8;
1135         yres = v_disp + 1;
1136         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138         hslen = h_sync_wid * 8;
1139         upper = v_total - v_sync_strt - v_sync_wid;
1140         lower = v_sync_strt - v_disp;
1141         vslen = v_sync_wid;
1142         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1145
1146         switch (pix_width) {
1147 #if 0
1148         case CRTC_PIX_WIDTH_4BPP:
1149                 bpp = 4;
1150                 var->red.offset = 0;
1151                 var->red.length = 8;
1152                 var->green.offset = 0;
1153                 var->green.length = 8;
1154                 var->blue.offset = 0;
1155                 var->blue.length = 8;
1156                 var->transp.offset = 0;
1157                 var->transp.length = 0;
1158                 break;
1159 #endif
1160         case CRTC_PIX_WIDTH_8BPP:
1161                 bpp = 8;
1162                 var->red.offset = 0;
1163                 var->red.length = 8;
1164                 var->green.offset = 0;
1165                 var->green.length = 8;
1166                 var->blue.offset = 0;
1167                 var->blue.length = 8;
1168                 var->transp.offset = 0;
1169                 var->transp.length = 0;
1170                 break;
1171         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1172                 bpp = 16;
1173                 var->red.offset = 10;
1174                 var->red.length = 5;
1175                 var->green.offset = 5;
1176                 var->green.length = 5;
1177                 var->blue.offset = 0;
1178                 var->blue.length = 5;
1179                 var->transp.offset = 0;
1180                 var->transp.length = 0;
1181                 break;
1182         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1183                 bpp = 16;
1184                 var->red.offset = 11;
1185                 var->red.length = 5;
1186                 var->green.offset = 5;
1187                 var->green.length = 6;
1188                 var->blue.offset = 0;
1189                 var->blue.length = 5;
1190                 var->transp.offset = 0;
1191                 var->transp.length = 0;
1192                 break;
1193         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1194                 bpp = 24;
1195                 var->red.offset = 16;
1196                 var->red.length = 8;
1197                 var->green.offset = 8;
1198                 var->green.length = 8;
1199                 var->blue.offset = 0;
1200                 var->blue.length = 8;
1201                 var->transp.offset = 0;
1202                 var->transp.length = 0;
1203                 break;
1204         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1205                 bpp = 32;
1206                 var->red.offset = 16;
1207                 var->red.length = 8;
1208                 var->green.offset = 8;
1209                 var->green.length = 8;
1210                 var->blue.offset = 0;
1211                 var->blue.length = 8;
1212                 var->transp.offset = 24;
1213                 var->transp.length = 8;
1214                 break;
1215         default:
1216                 PRINTKE("Invalid pixel width\n");
1217                 return -EINVAL;
1218         }
1219
1220         /* output */
1221         var->xres = xres;
1222         var->yres = yres;
1223         var->xres_virtual = crtc->vxres;
1224         var->yres_virtual = crtc->vyres;
1225         var->bits_per_pixel = bpp;
1226         var->left_margin = left;
1227         var->right_margin = right;
1228         var->upper_margin = upper;
1229         var->lower_margin = lower;
1230         var->hsync_len = hslen;
1231         var->vsync_len = vslen;
1232         var->sync = sync;
1233         var->vmode = FB_VMODE_NONINTERLACED;
1234         /* In double scan mode, the vertical parameters are doubled, so we need to
1235            half them to get the right values.
1236            In interlaced mode the values are already correct, so no correction is
1237            necessary.
1238          */
1239         if (interlace)
1240                 var->vmode = FB_VMODE_INTERLACED;
1241
1242         if (double_scan) {
1243                 var->vmode = FB_VMODE_DOUBLE;
1244                 var->yres>>=1;
1245                 var->upper_margin>>=1;
1246                 var->lower_margin>>=1;
1247                 var->vsync_len>>=1;
1248         }
1249
1250         return 0;
1251 }
1252
1253 /* ------------------------------------------------------------------------- */
1254
1255 static int atyfb_set_par(struct fb_info *info)
1256 {
1257         struct atyfb_par *par = (struct atyfb_par *) info->par;
1258         struct fb_var_screeninfo *var = &info->var;
1259         u32 tmp, pixclock;
1260         int err;
1261 #ifdef DEBUG
1262         struct fb_var_screeninfo debug;
1263         u32 pixclock_in_ps;
1264 #endif
1265         if (par->asleep)
1266                 return 0;
1267
1268         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1269                 return err;
1270
1271         pixclock = atyfb_get_pixclock(var, par);
1272
1273         if (pixclock == 0) {
1274                 PRINTKE("Invalid pixclock\n");
1275                 return -EINVAL;
1276         } else {
1277                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1278                         return err;
1279         }
1280
1281         par->accel_flags = var->accel_flags; /* hack */
1282
1283         if (par->blitter_may_be_busy)
1284                 wait_for_idle(par);
1285
1286         aty_set_crtc(par, &par->crtc);
1287         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1288         par->pll_ops->set_pll(info, &par->pll);
1289
1290 #ifdef DEBUG
1291         if(par->pll_ops && par->pll_ops->pll_to_var)
1292                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1293         else
1294                 pixclock_in_ps = 0;
1295
1296         if(0 == pixclock_in_ps) {
1297                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1298                 pixclock_in_ps = pixclock;
1299         }
1300
1301         memset(&debug, 0, sizeof(debug));
1302         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1303                 u32 hSync, vRefresh;
1304                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1305                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1306
1307                 h_disp = debug.xres;
1308                 h_sync_strt = h_disp + debug.right_margin;
1309                 h_sync_end = h_sync_strt + debug.hsync_len;
1310                 h_total = h_sync_end + debug.left_margin;
1311                 v_disp = debug.yres;
1312                 v_sync_strt = v_disp + debug.lower_margin;
1313                 v_sync_end = v_sync_strt + debug.vsync_len;
1314                 v_total = v_sync_end + debug.upper_margin;
1315
1316                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1317                 vRefresh = (hSync * 1000) / v_total;
1318                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1319                 vRefresh *= 2;
1320                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1321                 vRefresh /= 2;
1322
1323                 DPRINTK("atyfb_set_par\n");
1324                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1325                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1326                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1327                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1328                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1329                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1330                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1331                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1332                         h_disp, h_sync_strt, h_sync_end, h_total,
1333                         v_disp, v_sync_strt, v_sync_end, v_total);
1334                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1335                         pixclock_in_ps,
1336                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1337                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1338         }
1339 #endif /* DEBUG */
1340
1341         if (!M64_HAS(INTEGRATED)) {
1342                 /* Don't forget MEM_CNTL */
1343                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1344                 switch (var->bits_per_pixel) {
1345                 case 8:
1346                         tmp |= 0x02000000;
1347                         break;
1348                 case 16:
1349                         tmp |= 0x03000000;
1350                         break;
1351                 case 32:
1352                         tmp |= 0x06000000;
1353                         break;
1354                 }
1355                 aty_st_le32(MEM_CNTL, tmp, par);
1356         } else {
1357                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1358                 if (!M64_HAS(MAGIC_POSTDIV))
1359                         tmp |= par->mem_refresh_rate << 20;
1360                 switch (var->bits_per_pixel) {
1361                 case 8:
1362                 case 24:
1363                         tmp |= 0x00000000;
1364                         break;
1365                 case 16:
1366                         tmp |= 0x04000000;
1367                         break;
1368                 case 32:
1369                         tmp |= 0x08000000;
1370                         break;
1371                 }
1372                 if (M64_HAS(CT_BUS)) {
1373                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1374                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1375                 } else if (M64_HAS(VT_BUS)) {
1376                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1377                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1378                 } else if (M64_HAS(MOBIL_BUS)) {
1379                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1380                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1381                 } else {
1382                         /* GT */
1383                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1384                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1385                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1386                 }
1387                 aty_st_le32(MEM_CNTL, tmp, par);
1388         }
1389         aty_st_8(DAC_MASK, 0xff, par);
1390
1391         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1392         info->fix.visual = var->bits_per_pixel <= 8 ?
1393                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1394
1395         /* Initialize the graphics engine */
1396         if (par->accel_flags & FB_ACCELF_TEXT)
1397                 aty_init_engine(par, info);
1398
1399 #ifdef CONFIG_BOOTX_TEXT
1400         btext_update_display(info->fix.smem_start,
1401                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1402                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1403                 var->bits_per_pixel,
1404                 par->crtc.vxres * var->bits_per_pixel / 8);
1405 #endif /* CONFIG_BOOTX_TEXT */
1406 #if 0
1407         /* switch to accelerator mode */
1408         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1409                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1410 #endif
1411 #ifdef DEBUG
1412 {
1413         /* dump non shadow CRTC, pll, LCD registers */
1414         int i; u32 base;
1415
1416         /* CRTC registers */
1417         base = 0x2000;
1418         printk("debug atyfb: Mach64 non-shadow register values:");
1419         for (i = 0; i < 256; i = i+4) {
1420                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1421                 printk(" %08X", aty_ld_le32(i, par));
1422         }
1423         printk("\n\n");
1424
1425 #ifdef CONFIG_FB_ATY_CT
1426         /* PLL registers */
1427         base = 0x00;
1428         printk("debug atyfb: Mach64 PLL register values:");
1429         for (i = 0; i < 64; i++) {
1430                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1431                 if(i%4 == 0)  printk(" ");
1432                 printk("%02X", aty_ld_pll_ct(i, par));
1433         }
1434         printk("\n\n");
1435 #endif  /* CONFIG_FB_ATY_CT */
1436
1437 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1438         if (par->lcd_table != 0) {
1439                 /* LCD registers */
1440                 base = 0x00;
1441                 printk("debug atyfb: LCD register values:");
1442                 if(M64_HAS(LT_LCD_REGS)) {
1443                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1444                         if(i == EXT_VERT_STRETCH)
1445                             continue;
1446                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1447                         printk(" %08X", aty_ld_lcd(i, par));
1448                     }
1449
1450                 } else {
1451                     for (i = 0; i < 64; i++) {
1452                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1453                         printk(" %08X", aty_ld_lcd(i, par));
1454                     }
1455                 }
1456                 printk("\n\n");
1457         }
1458 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1459 }
1460 #endif /* DEBUG */
1461         return 0;
1462 }
1463
1464 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1465 {
1466         struct atyfb_par *par = (struct atyfb_par *) info->par;
1467         int err;
1468         struct crtc crtc;
1469         union aty_pll pll;
1470         u32 pixclock;
1471
1472         memcpy(&pll, &(par->pll), sizeof(pll));
1473
1474         if((err = aty_var_to_crtc(info, var, &crtc)))
1475                 return err;
1476
1477         pixclock = atyfb_get_pixclock(var, par);
1478
1479         if (pixclock == 0) {
1480                 if (!(var->activate & FB_ACTIVATE_TEST))
1481                         PRINTKE("Invalid pixclock\n");
1482                 return -EINVAL;
1483         } else {
1484                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1485                         return err;
1486         }
1487
1488         if (var->accel_flags & FB_ACCELF_TEXT)
1489                 info->var.accel_flags = FB_ACCELF_TEXT;
1490         else
1491                 info->var.accel_flags = 0;
1492
1493 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1494         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1495                 return -EINVAL;
1496 #endif
1497         aty_crtc_to_var(&crtc, var);
1498         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1499         return 0;
1500 }
1501
1502 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1503 {
1504         u32 xoffset = info->var.xoffset;
1505         u32 yoffset = info->var.yoffset;
1506         u32 vxres = par->crtc.vxres;
1507         u32 bpp = info->var.bits_per_pixel;
1508
1509         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1510 }
1511
1512
1513     /*
1514      *  Open/Release the frame buffer device
1515      */
1516
1517 static int atyfb_open(struct fb_info *info, int user)
1518 {
1519         struct atyfb_par *par = (struct atyfb_par *) info->par;
1520
1521         if (user) {
1522                 par->open++;
1523 #ifdef __sparc__
1524                 par->mmaped = 0;
1525 #endif
1526         }
1527         return (0);
1528 }
1529
1530 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1531 {
1532         struct atyfb_par *par = dev_id;
1533         int handled = 0;
1534         u32 int_cntl;
1535
1536         spin_lock(&par->int_lock);
1537
1538         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1539
1540         if (int_cntl & CRTC_VBLANK_INT) {
1541                 /* clear interrupt */
1542                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1543                 par->vblank.count++;
1544                 if (par->vblank.pan_display) {
1545                         par->vblank.pan_display = 0;
1546                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1547                 }
1548                 wake_up_interruptible(&par->vblank.wait);
1549                 handled = 1;
1550         }
1551
1552         spin_unlock(&par->int_lock);
1553
1554         return IRQ_RETVAL(handled);
1555 }
1556
1557 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1558 {
1559         u32 int_cntl;
1560
1561         if (!test_and_set_bit(0, &par->irq_flags)) {
1562                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1563                         clear_bit(0, &par->irq_flags);
1564                         return -EINVAL;
1565                 }
1566                 spin_lock_irq(&par->int_lock);
1567                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1568                 /* clear interrupt */
1569                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1570                 /* enable interrupt */
1571                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1572                 spin_unlock_irq(&par->int_lock);
1573         } else if (reenable) {
1574                 spin_lock_irq(&par->int_lock);
1575                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1577                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1578                         /* re-enable interrupt */
1579                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1580                 }
1581                 spin_unlock_irq(&par->int_lock);
1582         }
1583
1584         return 0;
1585 }
1586
1587 static int aty_disable_irq(struct atyfb_par *par)
1588 {
1589         u32 int_cntl;
1590
1591         if (test_and_clear_bit(0, &par->irq_flags)) {
1592                 if (par->vblank.pan_display) {
1593                         par->vblank.pan_display = 0;
1594                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1595                 }
1596                 spin_lock_irq(&par->int_lock);
1597                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1598                 /* disable interrupt */
1599                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1600                 spin_unlock_irq(&par->int_lock);
1601                 free_irq(par->irq, par);
1602         }
1603
1604         return 0;
1605 }
1606
1607 static int atyfb_release(struct fb_info *info, int user)
1608 {
1609         struct atyfb_par *par = (struct atyfb_par *) info->par;
1610         if (user) {
1611                 par->open--;
1612                 mdelay(1);
1613                 wait_for_idle(par);
1614                 if (!par->open) {
1615 #ifdef __sparc__
1616                         int was_mmaped = par->mmaped;
1617
1618                         par->mmaped = 0;
1619
1620                         if (was_mmaped) {
1621                                 struct fb_var_screeninfo var;
1622
1623                                 /* Now reset the default display config, we have no
1624                                  * idea what the program(s) which mmap'd the chip did
1625                                  * to the configuration, nor whether it restored it
1626                                  * correctly.
1627                                  */
1628                                 var = default_var;
1629                                 if (noaccel)
1630                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1631                                 else
1632                                         var.accel_flags |= FB_ACCELF_TEXT;
1633                                 if (var.yres == var.yres_virtual) {
1634                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1635                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1636                                         if (var.yres_virtual < var.yres)
1637                                                 var.yres_virtual = var.yres;
1638                                 }
1639                         }
1640 #endif
1641                         aty_disable_irq(par);
1642                 }
1643         }
1644         return (0);
1645 }
1646
1647     /*
1648      *  Pan or Wrap the Display
1649      *
1650      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651      */
1652
1653 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1654 {
1655         struct atyfb_par *par = (struct atyfb_par *) info->par;
1656         u32 xres, yres, xoffset, yoffset;
1657
1658         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1659         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1660         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1661                 yres >>= 1;
1662         xoffset = (var->xoffset + 7) & ~7;
1663         yoffset = var->yoffset;
1664         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1665                 return -EINVAL;
1666         info->var.xoffset = xoffset;
1667         info->var.yoffset = yoffset;
1668         if (par->asleep)
1669                 return 0;
1670
1671         set_off_pitch(par, info);
1672         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1673                 par->vblank.pan_display = 1;
1674         } else {
1675                 par->vblank.pan_display = 0;
1676                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1677         }
1678
1679         return 0;
1680 }
1681
1682 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1683 {
1684         struct aty_interrupt *vbl;
1685         unsigned int count;
1686         int ret;
1687
1688         switch (crtc) {
1689         case 0:
1690                 vbl = &par->vblank;
1691                 break;
1692         default:
1693                 return -ENODEV;
1694         }
1695
1696         ret = aty_enable_irq(par, 0);
1697         if (ret)
1698                 return ret;
1699
1700         count = vbl->count;
1701         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1702         if (ret < 0) {
1703                 return ret;
1704         }
1705         if (ret == 0) {
1706                 aty_enable_irq(par, 1);
1707                 return -ETIMEDOUT;
1708         }
1709
1710         return 0;
1711 }
1712
1713
1714 #ifdef DEBUG
1715 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1716 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1717
1718 struct atyclk {
1719         u32 ref_clk_per;
1720         u8 pll_ref_div;
1721         u8 mclk_fb_div;
1722         u8 mclk_post_div;       /* 1,2,3,4,8 */
1723         u8 mclk_fb_mult;        /* 2 or 4 */
1724         u8 xclk_post_div;       /* 1,2,3,4,8 */
1725         u8 vclk_fb_div;
1726         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1727         u32 dsp_xclks_per_row;  /* 0-16383 */
1728         u32 dsp_loop_latency;   /* 0-15 */
1729         u32 dsp_precision;      /* 0-7 */
1730         u32 dsp_on;             /* 0-2047 */
1731         u32 dsp_off;            /* 0-2047 */
1732 };
1733
1734 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1735 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1736 #endif
1737
1738 #ifndef FBIO_WAITFORVSYNC
1739 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 #endif
1741
1742 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1743 {
1744         struct atyfb_par *par = (struct atyfb_par *) info->par;
1745 #ifdef __sparc__
1746         struct fbtype fbtyp;
1747 #endif
1748
1749         switch (cmd) {
1750 #ifdef __sparc__
1751         case FBIOGTYPE:
1752                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1753                 fbtyp.fb_width = par->crtc.vxres;
1754                 fbtyp.fb_height = par->crtc.vyres;
1755                 fbtyp.fb_depth = info->var.bits_per_pixel;
1756                 fbtyp.fb_cmsize = info->cmap.len;
1757                 fbtyp.fb_size = info->fix.smem_len;
1758                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1759                         return -EFAULT;
1760                 break;
1761 #endif /* __sparc__ */
1762
1763         case FBIO_WAITFORVSYNC:
1764                 {
1765                         u32 crtc;
1766
1767                         if (get_user(crtc, (__u32 __user *) arg))
1768                                 return -EFAULT;
1769
1770                         return aty_waitforvblank(par, crtc);
1771                 }
1772                 break;
1773
1774 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1775         case ATYIO_CLKR:
1776                 if (M64_HAS(INTEGRATED)) {
1777                         struct atyclk clk;
1778                         union aty_pll *pll = &(par->pll);
1779                         u32 dsp_config = pll->ct.dsp_config;
1780                         u32 dsp_on_off = pll->ct.dsp_on_off;
1781                         clk.ref_clk_per = par->ref_clk_per;
1782                         clk.pll_ref_div = pll->ct.pll_ref_div;
1783                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1784                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1785                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1786                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1787                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1788                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1789                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1790                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1791                         clk.dsp_precision = (dsp_config >> 20) & 7;
1792                         clk.dsp_off = dsp_on_off & 0x7ff;
1793                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1794                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1795                                          sizeof(clk)))
1796                                 return -EFAULT;
1797                 } else
1798                         return -EINVAL;
1799                 break;
1800         case ATYIO_CLKW:
1801                 if (M64_HAS(INTEGRATED)) {
1802                         struct atyclk clk;
1803                         union aty_pll *pll = &(par->pll);
1804                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1805                                 return -EFAULT;
1806                         par->ref_clk_per = clk.ref_clk_per;
1807                         pll->ct.pll_ref_div = clk.pll_ref_div;
1808                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1809                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1810                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1811                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1812                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1813                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1814                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1815                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1816                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1817                         /*aty_calc_pll_ct(info, &pll->ct);*/
1818                         aty_set_pll_ct(info, pll);
1819                 } else
1820                         return -EINVAL;
1821                 break;
1822         case ATYIO_FEATR:
1823                 if (get_user(par->features, (u32 __user *) arg))
1824                         return -EFAULT;
1825                 break;
1826         case ATYIO_FEATW:
1827                 if (put_user(par->features, (u32 __user *) arg))
1828                         return -EFAULT;
1829                 break;
1830 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1831         default:
1832                 return -EINVAL;
1833         }
1834         return 0;
1835 }
1836
1837 static int atyfb_sync(struct fb_info *info)
1838 {
1839         struct atyfb_par *par = (struct atyfb_par *) info->par;
1840
1841         if (par->blitter_may_be_busy)
1842                 wait_for_idle(par);
1843         return 0;
1844 }
1845
1846 #ifdef __sparc__
1847 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1848 {
1849         struct atyfb_par *par = (struct atyfb_par *) info->par;
1850         unsigned int size, page, map_size = 0;
1851         unsigned long map_offset = 0;
1852         unsigned long off;
1853         int i;
1854
1855         if (!par->mmap_map)
1856                 return -ENXIO;
1857
1858         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1859                 return -EINVAL;
1860
1861         off = vma->vm_pgoff << PAGE_SHIFT;
1862         size = vma->vm_end - vma->vm_start;
1863
1864         /* To stop the swapper from even considering these pages. */
1865         vma->vm_flags |= (VM_IO | VM_RESERVED);
1866
1867         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1868             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1869                 off += 0x8000000000000000UL;
1870
1871         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1872
1873         /* Each page, see which map applies */
1874         for (page = 0; page < size;) {
1875                 map_size = 0;
1876                 for (i = 0; par->mmap_map[i].size; i++) {
1877                         unsigned long start = par->mmap_map[i].voff;
1878                         unsigned long end = start + par->mmap_map[i].size;
1879                         unsigned long offset = off + page;
1880
1881                         if (start > offset)
1882                                 continue;
1883                         if (offset >= end)
1884                                 continue;
1885
1886                         map_size = par->mmap_map[i].size - (offset - start);
1887                         map_offset =
1888                             par->mmap_map[i].poff + (offset - start);
1889                         break;
1890                 }
1891                 if (!map_size) {
1892                         page += PAGE_SIZE;
1893                         continue;
1894                 }
1895                 if (page + map_size > size)
1896                         map_size = size - page;
1897
1898                 pgprot_val(vma->vm_page_prot) &=
1899                     ~(par->mmap_map[i].prot_mask);
1900                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1901
1902                 if (remap_pfn_range(vma, vma->vm_start + page,
1903                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1904                         return -EAGAIN;
1905
1906                 page += map_size;
1907         }
1908
1909         if (!map_size)
1910                 return -EINVAL;
1911
1912         if (!par->mmaped)
1913                 par->mmaped = 1;
1914         return 0;
1915 }
1916
1917 static struct {
1918         u32 yoffset;
1919         u8 r[2][256];
1920         u8 g[2][256];
1921         u8 b[2][256];
1922 } atyfb_save;
1923
1924 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1925 {
1926         int i, tmp;
1927
1928         for (i = 0; i < 256; i++) {
1929                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1930                 if (M64_HAS(EXTRA_BRIGHT))
1931                         tmp |= 0x2;
1932                 aty_st_8(DAC_CNTL, tmp, par);
1933                 aty_st_8(DAC_MASK, 0xff, par);
1934
1935                 writeb(i, &par->aty_cmap_regs->rindex);
1936                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1937                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1938                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1939                 writeb(i, &par->aty_cmap_regs->windex);
1940                 writeb(atyfb_save.r[1 - enter][i],
1941                        &par->aty_cmap_regs->lut);
1942                 writeb(atyfb_save.g[1 - enter][i],
1943                        &par->aty_cmap_regs->lut);
1944                 writeb(atyfb_save.b[1 - enter][i],
1945                        &par->aty_cmap_regs->lut);
1946         }
1947 }
1948
1949 static void atyfb_palette(int enter)
1950 {
1951         struct atyfb_par *par;
1952         struct fb_info *info;
1953         int i;
1954
1955         for (i = 0; i < FB_MAX; i++) {
1956                 info = registered_fb[i];
1957                 if (info && info->fbops == &atyfb_ops) {
1958                         par = (struct atyfb_par *) info->par;
1959                         
1960                         atyfb_save_palette(par, enter);
1961                         if (enter) {
1962                                 atyfb_save.yoffset = info->var.yoffset;
1963                                 info->var.yoffset = 0;
1964                                 set_off_pitch(par, info);
1965                         } else {
1966                                 info->var.yoffset = atyfb_save.yoffset;
1967                                 set_off_pitch(par, info);
1968                         }
1969                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1970                         break;
1971                 }
1972         }
1973 }
1974 #endif /* __sparc__ */
1975
1976
1977
1978 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1979
1980 /* Power management routines. Those are used for PowerBook sleep.
1981  */
1982 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1983 {
1984         u32 pm;
1985         int timeout;
1986
1987         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1988         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1989         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1990         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1991
1992         timeout = 2000;
1993         if (sleep) {
1994                 /* Sleep */
1995                 pm &= ~PWR_MGT_ON;
1996                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1997                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1998                 udelay(10);
1999                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2000                 pm |= SUSPEND_NOW;
2001                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2002                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2003                 udelay(10);
2004                 pm |= PWR_MGT_ON;
2005                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2006                 do {
2007                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2008                         mdelay(1);
2009                         if ((--timeout) == 0)
2010                                 break;
2011                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2012         } else {
2013                 /* Wakeup */
2014                 pm &= ~PWR_MGT_ON;
2015                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2016                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2017                 udelay(10);
2018                 pm &= ~SUSPEND_NOW;
2019                 pm |= (PWR_BLON | AUTO_PWR_UP);
2020                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2021                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2022                 udelay(10);
2023                 pm |= PWR_MGT_ON;
2024                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025                 do {
2026                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2027                         mdelay(1);
2028                         if ((--timeout) == 0)
2029                                 break;
2030                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2031         }
2032         mdelay(500);
2033
2034         return timeout ? 0 : -EIO;
2035 }
2036
2037 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2038 {
2039         struct fb_info *info = pci_get_drvdata(pdev);
2040         struct atyfb_par *par = (struct atyfb_par *) info->par;
2041
2042 #ifndef CONFIG_PPC_PMAC
2043         /* HACK ALERT ! Once I find a proper way to say to each driver
2044          * individually what will happen with it's PCI slot, I'll change
2045          * that. On laptops, the AGP slot is just unclocked, so D2 is
2046          * expected, while on desktops, the card is powered off
2047          */
2048         return 0;
2049 #endif /* CONFIG_PPC_PMAC */
2050
2051         if (state.event == pdev->dev.power.power_state.event)
2052                 return 0;
2053
2054         acquire_console_sem();
2055
2056         fb_set_suspend(info, 1);
2057
2058         /* Idle & reset engine */
2059         wait_for_idle(par);
2060         aty_reset_engine(par);
2061
2062         /* Blank display and LCD */
2063         atyfb_blank(FB_BLANK_POWERDOWN, info);
2064
2065         par->asleep = 1;
2066         par->lock_blank = 1;
2067
2068         /* Set chip to "suspend" mode */
2069         if (aty_power_mgmt(1, par)) {
2070                 par->asleep = 0;
2071                 par->lock_blank = 0;
2072                 atyfb_blank(FB_BLANK_UNBLANK, info);
2073                 fb_set_suspend(info, 0);
2074                 release_console_sem();
2075                 return -EIO;
2076         }
2077
2078         release_console_sem();
2079
2080         pdev->dev.power.power_state = state;
2081
2082         return 0;
2083 }
2084
2085 static int atyfb_pci_resume(struct pci_dev *pdev)
2086 {
2087         struct fb_info *info = pci_get_drvdata(pdev);
2088         struct atyfb_par *par = (struct atyfb_par *) info->par;
2089
2090         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2091                 return 0;
2092
2093         acquire_console_sem();
2094
2095         if (pdev->dev.power.power_state.event == 2)
2096                 aty_power_mgmt(0, par);
2097         par->asleep = 0;
2098
2099         /* Restore display */
2100         atyfb_set_par(info);
2101
2102         /* Refresh */
2103         fb_set_suspend(info, 0);
2104
2105         /* Unblank */
2106         par->lock_blank = 0;
2107         atyfb_blank(FB_BLANK_UNBLANK, info);
2108
2109         release_console_sem();
2110
2111         pdev->dev.power.power_state = PMSG_ON;
2112
2113         return 0;
2114 }
2115
2116 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2117
2118 #ifdef CONFIG_PMAC_BACKLIGHT
2119
2120     /*
2121      *   LCD backlight control
2122      */
2123
2124 static int backlight_conv[] = {
2125         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2126         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2127 };
2128
2129 static int aty_set_backlight_enable(int on, int level, void *data)
2130 {
2131         struct fb_info *info = (struct fb_info *) data;
2132         struct atyfb_par *par = (struct atyfb_par *) info->par;
2133         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2134
2135         reg |= (BLMOD_EN | BIASMOD_EN);
2136         if (on && level > BACKLIGHT_OFF) {
2137                 reg &= ~BIAS_MOD_LEVEL_MASK;
2138                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2139         } else {
2140                 reg &= ~BIAS_MOD_LEVEL_MASK;
2141                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2142         }
2143         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2144         return 0;
2145 }
2146
2147 static int aty_set_backlight_level(int level, void *data)
2148 {
2149         return aty_set_backlight_enable(1, level, data);
2150 }
2151
2152 static struct backlight_controller aty_backlight_controller = {
2153         aty_set_backlight_enable,
2154         aty_set_backlight_level
2155 };
2156 #endif /* CONFIG_PMAC_BACKLIGHT */
2157
2158 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2159 {
2160         const int ragepro_tbl[] = {
2161                 44, 50, 55, 66, 75, 80, 100
2162         };
2163         const int ragexl_tbl[] = {
2164                 50, 66, 75, 83, 90, 95, 100, 105,
2165                 110, 115, 120, 125, 133, 143, 166
2166         };
2167         const int *refresh_tbl;
2168         int i, size;
2169
2170         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2171                 refresh_tbl = ragexl_tbl;
2172                 size = ARRAY_SIZE(ragexl_tbl);
2173         } else {
2174                 refresh_tbl = ragepro_tbl;
2175                 size = ARRAY_SIZE(ragepro_tbl);
2176         }
2177
2178         for (i=0; i < size; i++) {
2179                 if (xclk < refresh_tbl[i])
2180                 break;
2181         }
2182         par->mem_refresh_rate = i;
2183 }
2184
2185     /*
2186      *  Initialisation
2187      */
2188
2189 static struct fb_info *fb_list = NULL;
2190
2191 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2192 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2193                                                 struct fb_var_screeninfo *var)
2194 {
2195         int ret = -EINVAL;
2196
2197         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2198                 *var = default_var;
2199                 var->xres = var->xres_virtual = par->lcd_hdisp;
2200                 var->right_margin = par->lcd_right_margin;
2201                 var->left_margin = par->lcd_hblank_len -
2202                         (par->lcd_right_margin + par->lcd_hsync_dly +
2203                          par->lcd_hsync_len);
2204                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2205                 var->yres = var->yres_virtual = par->lcd_vdisp;
2206                 var->lower_margin = par->lcd_lower_margin;
2207                 var->upper_margin = par->lcd_vblank_len -
2208                         (par->lcd_lower_margin + par->lcd_vsync_len);
2209                 var->vsync_len = par->lcd_vsync_len;
2210                 var->pixclock = par->lcd_pixclock;
2211                 ret = 0;
2212         }
2213
2214         return ret;
2215 }
2216 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2217
2218 static int __init aty_init(struct fb_info *info, const char *name)
2219 {
2220         struct atyfb_par *par = (struct atyfb_par *) info->par;
2221         const char *ramname = NULL, *xtal;
2222         int gtb_memsize, has_var = 0;
2223         struct fb_var_screeninfo var;
2224         u8 pll_ref_div;
2225         u32 i;
2226 #if defined(CONFIG_PPC)
2227         int sense;
2228 #endif
2229
2230         init_waitqueue_head(&par->vblank.wait);
2231         spin_lock_init(&par->int_lock);
2232
2233         par->aty_cmap_regs =
2234             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2235
2236 #ifdef CONFIG_PPC_PMAC
2237         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2238          * and set the frequency manually. */
2239         if (machine_is_compatible("PowerBook2,1")) {
2240                 par->pll_limits.mclk = 70;
2241                 par->pll_limits.xclk = 53;
2242         }
2243 #endif
2244         if (pll)
2245                 par->pll_limits.pll_max = pll;
2246         if (mclk)
2247                 par->pll_limits.mclk = mclk;
2248         if (xclk)
2249                 par->pll_limits.xclk = xclk;
2250
2251         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2252         par->pll_per = 1000000/par->pll_limits.pll_max;
2253         par->mclk_per = 1000000/par->pll_limits.mclk;
2254         par->xclk_per = 1000000/par->pll_limits.xclk;
2255
2256         par->ref_clk_per = 1000000000000ULL / 14318180;
2257         xtal = "14.31818";
2258
2259 #ifdef CONFIG_FB_ATY_GX
2260         if (!M64_HAS(INTEGRATED)) {
2261                 u32 stat0;
2262                 u8 dac_type, dac_subtype, clk_type;
2263                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2264                 par->bus_type = (stat0 >> 0) & 0x07;
2265                 par->ram_type = (stat0 >> 3) & 0x07;
2266                 ramname = aty_gx_ram[par->ram_type];
2267                 /* FIXME: clockchip/RAMDAC probing? */
2268                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2269 #ifdef CONFIG_ATARI
2270                 clk_type = CLK_ATI18818_1;
2271                 dac_type = (stat0 >> 9) & 0x07;
2272                 if (dac_type == 0x07)
2273                         dac_subtype = DAC_ATT20C408;
2274                 else
2275                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2276 #else
2277                 dac_type = DAC_IBMRGB514;
2278                 dac_subtype = DAC_IBMRGB514;
2279                 clk_type = CLK_IBMRGB514;
2280 #endif
2281                 switch (dac_subtype) {
2282                 case DAC_IBMRGB514:
2283                         par->dac_ops = &aty_dac_ibm514;
2284                         break;
2285                 case DAC_ATI68860_B:
2286                 case DAC_ATI68860_C:
2287                         par->dac_ops = &aty_dac_ati68860b;
2288                         break;
2289                 case DAC_ATT20C408:
2290                 case DAC_ATT21C498:
2291                         par->dac_ops = &aty_dac_att21c498;
2292                         break;
2293                 default:
2294                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2295                         par->dac_ops = &aty_dac_unsupported;
2296                         break;
2297                 }
2298                 switch (clk_type) {
2299                 case CLK_ATI18818_1:
2300                         par->pll_ops = &aty_pll_ati18818_1;
2301                         break;
2302                 case CLK_IBMRGB514:
2303                         par->pll_ops = &aty_pll_ibm514;
2304                         break;
2305 #if 0 /* dead code */
2306                 case CLK_STG1703:
2307                         par->pll_ops = &aty_pll_stg1703;
2308                         break;
2309                 case CLK_CH8398:
2310                         par->pll_ops = &aty_pll_ch8398;
2311                         break;
2312                 case CLK_ATT20C408:
2313                         par->pll_ops = &aty_pll_att20c408;
2314                         break;
2315 #endif
2316                 default:
2317                         PRINTKI("aty_init: CLK type not implemented yet!");
2318                         par->pll_ops = &aty_pll_unsupported;
2319                         break;
2320                 }
2321         }
2322 #endif /* CONFIG_FB_ATY_GX */
2323 #ifdef CONFIG_FB_ATY_CT
2324         if (M64_HAS(INTEGRATED)) {
2325                 par->dac_ops = &aty_dac_ct;
2326                 par->pll_ops = &aty_pll_ct;
2327                 par->bus_type = PCI;
2328                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2329                 ramname = aty_ct_ram[par->ram_type];
2330                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2331                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2332                         par->pll_limits.mclk = 63;
2333         }
2334
2335         if (M64_HAS(GTB_DSP)
2336             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2337                 int diff1, diff2;
2338                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2339                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2340                 if (diff1 < 0)
2341                         diff1 = -diff1;
2342                 if (diff2 < 0)
2343                         diff2 = -diff2;
2344                 if (diff2 < diff1) {
2345                         par->ref_clk_per = 1000000000000ULL / 29498928;
2346                         xtal = "29.498928";
2347                 }
2348         }
2349 #endif /* CONFIG_FB_ATY_CT */
2350
2351         /* save previous video mode */
2352         aty_get_crtc(par, &saved_crtc);
2353         if(par->pll_ops->get_pll)
2354                 par->pll_ops->get_pll(info, &saved_pll);
2355
2356         i = aty_ld_le32(MEM_CNTL, par);
2357         gtb_memsize = M64_HAS(GTB_DSP);
2358         if (gtb_memsize)
2359                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2360                 case MEM_SIZE_512K:
2361                         info->fix.smem_len = 0x80000;
2362                         break;
2363                 case MEM_SIZE_1M:
2364                         info->fix.smem_len = 0x100000;
2365                         break;
2366                 case MEM_SIZE_2M_GTB:
2367                         info->fix.smem_len = 0x200000;
2368                         break;
2369                 case MEM_SIZE_4M_GTB:
2370                         info->fix.smem_len = 0x400000;
2371                         break;
2372                 case MEM_SIZE_6M_GTB:
2373                         info->fix.smem_len = 0x600000;
2374                         break;
2375                 case MEM_SIZE_8M_GTB:
2376                         info->fix.smem_len = 0x800000;
2377                         break;
2378                 default:
2379                         info->fix.smem_len = 0x80000;
2380         } else
2381                 switch (i & MEM_SIZE_ALIAS) {
2382                 case MEM_SIZE_512K:
2383                         info->fix.smem_len = 0x80000;
2384                         break;
2385                 case MEM_SIZE_1M:
2386                         info->fix.smem_len = 0x100000;
2387                         break;
2388                 case MEM_SIZE_2M:
2389                         info->fix.smem_len = 0x200000;
2390                         break;
2391                 case MEM_SIZE_4M:
2392                         info->fix.smem_len = 0x400000;
2393                         break;
2394                 case MEM_SIZE_6M:
2395                         info->fix.smem_len = 0x600000;
2396                         break;
2397                 case MEM_SIZE_8M:
2398                         info->fix.smem_len = 0x800000;
2399                         break;
2400                 default:
2401                         info->fix.smem_len = 0x80000;
2402                 }
2403
2404         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2405                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2406                         info->fix.smem_len += 0x400000;
2407         }
2408
2409         if (vram) {
2410                 info->fix.smem_len = vram * 1024;
2411                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2412                 if (info->fix.smem_len <= 0x80000)
2413                         i |= MEM_SIZE_512K;
2414                 else if (info->fix.smem_len <= 0x100000)
2415                         i |= MEM_SIZE_1M;
2416                 else if (info->fix.smem_len <= 0x200000)
2417                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2418                 else if (info->fix.smem_len <= 0x400000)
2419                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2420                 else if (info->fix.smem_len <= 0x600000)
2421                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2422                 else
2423                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2424                 aty_st_le32(MEM_CNTL, i, par);
2425         }
2426
2427         /*
2428          *  Reg Block 0 (CT-compatible block) is at mmio_start
2429          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2430          */
2431         if (M64_HAS(GX)) {
2432                 info->fix.mmio_len = 0x400;
2433                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2434         } else if (M64_HAS(CT)) {
2435                 info->fix.mmio_len = 0x400;
2436                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2437         } else if (M64_HAS(VT)) {
2438                 info->fix.mmio_start -= 0x400;
2439                 info->fix.mmio_len = 0x800;
2440                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2441         } else {/* GT */
2442                 info->fix.mmio_start -= 0x400;
2443                 info->fix.mmio_len = 0x800;
2444                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2445         }
2446
2447         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2448                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2449                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2450                par->pll_limits.mclk, par->pll_limits.xclk);
2451
2452 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2453         if (M64_HAS(INTEGRATED)) {
2454                 int i;
2455                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2456                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2457                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2458                        "debug atyfb: PLL",
2459                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2460                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2461                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2462                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2463                 for (i = 0; i < 40; i++)
2464                         printk(" %02x", aty_ld_pll_ct(i, par));
2465                 printk("\n");
2466         }
2467 #endif
2468         if(par->pll_ops->init_pll)
2469                 par->pll_ops->init_pll(info, &par->pll);
2470
2471         /*
2472          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2473          *  FIXME: we should use the auxiliary aperture instead so we can access
2474          *  the full 8 MB of video RAM on 8 MB boards
2475          */
2476
2477         if (!par->aux_start &&
2478                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2479                 info->fix.smem_len -= GUI_RESERVE;
2480
2481         /*
2482          *  Disable register access through the linear aperture
2483          *  if the auxiliary aperture is used so we can access
2484          *  the full 8 MB of video RAM on 8 MB boards.
2485          */
2486         if (par->aux_start)
2487                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2488
2489 #ifdef CONFIG_MTRR
2490         par->mtrr_aper = -1;
2491         par->mtrr_reg = -1;
2492         if (!nomtrr) {
2493                 /* Cover the whole resource. */
2494                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2495                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2496                         /* Make a hole for mmio. */
2497                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2498                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2499                         if (par->mtrr_reg < 0) {
2500                                 mtrr_del(par->mtrr_aper, 0, 0);
2501                                 par->mtrr_aper = -1;
2502                         }
2503                  }
2504         }
2505 #endif
2506
2507         info->fbops = &atyfb_ops;
2508         info->pseudo_palette = pseudo_palette;
2509         info->flags = FBINFO_FLAG_DEFAULT;
2510
2511 #ifdef CONFIG_PMAC_BACKLIGHT
2512         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2513                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2514                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2515                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2516         } else if (M64_HAS(MOBIL_BUS))
2517                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2518 #endif /* CONFIG_PMAC_BACKLIGHT */
2519
2520         memset(&var, 0, sizeof(var));
2521 #ifdef CONFIG_PPC
2522         if (machine_is(powermac)) {
2523                 /*
2524                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2525                  *         applies to all Mac video cards
2526                  */
2527                 if (mode) {
2528                         if (mac_find_mode(&var, info, mode, 8))
2529                                 has_var = 1;
2530                 } else {
2531                         if (default_vmode == VMODE_CHOOSE) {
2532                                 if (M64_HAS(G3_PB_1024x768))
2533                                         /* G3 PowerBook with 1024x768 LCD */
2534                                         default_vmode = VMODE_1024_768_60;
2535                                 else if (machine_is_compatible("iMac"))
2536                                         default_vmode = VMODE_1024_768_75;
2537                                 else if (machine_is_compatible
2538                                          ("PowerBook2,1"))
2539                                         /* iBook with 800x600 LCD */
2540                                         default_vmode = VMODE_800_600_60;
2541                                 else
2542                                         default_vmode = VMODE_640_480_67;
2543                                 sense = read_aty_sense(par);
2544                                 PRINTKI("monitor sense=%x, mode %d\n",
2545                                         sense,  mac_map_monitor_sense(sense));
2546                         }
2547                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2548                                 default_vmode = VMODE_640_480_60;
2549                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2550                                 default_cmode = CMODE_8;
2551                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2552                                                &var))
2553                                 has_var = 1;
2554                 }
2555         }
2556
2557 #endif /* !CONFIG_PPC */
2558
2559 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2560         if (!atyfb_get_timings_from_lcd(par, &var))
2561                 has_var = 1;
2562 #endif
2563
2564         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2565                 has_var = 1;
2566
2567         if (!has_var)
2568                 var = default_var;
2569
2570         if (noaccel)
2571                 var.accel_flags &= ~FB_ACCELF_TEXT;
2572         else
2573                 var.accel_flags |= FB_ACCELF_TEXT;
2574
2575         if (comp_sync != -1) {
2576                 if (!comp_sync)
2577                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2578                 else
2579                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2580         }
2581
2582         if (var.yres == var.yres_virtual) {
2583                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2584                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2585                 if (var.yres_virtual < var.yres)
2586                         var.yres_virtual = var.yres;
2587         }
2588
2589         if (atyfb_check_var(&var, info)) {
2590                 PRINTKE("can't set default video mode\n");
2591                 goto aty_init_exit;
2592         }
2593
2594 #ifdef __sparc__
2595         atyfb_save_palette(par, 0);
2596 #endif
2597
2598 #ifdef CONFIG_FB_ATY_CT
2599         if (!noaccel && M64_HAS(INTEGRATED))
2600                 aty_init_cursor(info);
2601 #endif /* CONFIG_FB_ATY_CT */
2602         info->var = var;
2603
2604         fb_alloc_cmap(&info->cmap, 256, 0);
2605
2606         if (register_framebuffer(info) < 0)
2607                 goto aty_init_exit;
2608
2609         fb_list = info;
2610
2611         PRINTKI("fb%d: %s frame buffer device on %s\n",
2612                info->node, info->fix.id, name);
2613         return 0;
2614
2615 aty_init_exit:
2616         /* restore video mode */
2617         aty_set_crtc(par, &saved_crtc);
2618         par->pll_ops->set_pll(info, &saved_pll);
2619
2620 #ifdef CONFIG_MTRR
2621         if (par->mtrr_reg >= 0) {
2622             mtrr_del(par->mtrr_reg, 0, 0);
2623             par->mtrr_reg = -1;
2624         }
2625         if (par->mtrr_aper >= 0) {
2626             mtrr_del(par->mtrr_aper, 0, 0);
2627             par->mtrr_aper = -1;
2628         }
2629 #endif
2630         return -1;
2631 }
2632
2633 #ifdef CONFIG_ATARI
2634 static int __init store_video_par(char *video_str, unsigned char m64_num)
2635 {
2636         char *p;
2637         unsigned long vmembase, size, guiregbase;
2638
2639         PRINTKI("store_video_par() '%s' \n", video_str);
2640
2641         if (!(p = strsep(&video_str, ";")) || !*p)
2642                 goto mach64_invalid;
2643         vmembase = simple_strtoul(p, NULL, 0);
2644         if (!(p = strsep(&video_str, ";")) || !*p)
2645                 goto mach64_invalid;
2646         size = simple_strtoul(p, NULL, 0);
2647         if (!(p = strsep(&video_str, ";")) || !*p)
2648                 goto mach64_invalid;
2649         guiregbase = simple_strtoul(p, NULL, 0);
2650
2651         phys_vmembase[m64_num] = vmembase;
2652         phys_size[m64_num] = size;
2653         phys_guiregbase[m64_num] = guiregbase;
2654         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2655                guiregbase);
2656         return 0;
2657
2658       mach64_invalid:
2659         phys_vmembase[m64_num] = 0;
2660         return -1;
2661 }
2662 #endif /* CONFIG_ATARI */
2663
2664     /*
2665      *  Blank the display.
2666      */
2667
2668 static int atyfb_blank(int blank, struct fb_info *info)
2669 {
2670         struct atyfb_par *par = (struct atyfb_par *) info->par;
2671         u32 gen_cntl;
2672
2673         if (par->lock_blank || par->asleep)
2674                 return 0;
2675
2676 #ifdef CONFIG_PMAC_BACKLIGHT
2677         if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2678                 set_backlight_enable(0);
2679 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2680         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2681             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2682                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2683                 pm &= ~PWR_BLON;
2684                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2685         }
2686 #endif
2687
2688         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2689         switch (blank) {
2690                 case FB_BLANK_UNBLANK:
2691                         gen_cntl &= ~0x400004c;
2692                         break;
2693                 case FB_BLANK_NORMAL:
2694                         gen_cntl |= 0x4000040;
2695                         break;
2696                 case FB_BLANK_VSYNC_SUSPEND:
2697                         gen_cntl |= 0x4000048;
2698                         break;
2699                 case FB_BLANK_HSYNC_SUSPEND:
2700                         gen_cntl |= 0x4000044;
2701                         break;
2702                 case FB_BLANK_POWERDOWN:
2703                         gen_cntl |= 0x400004c;
2704                         break;
2705         }
2706         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2707
2708 #ifdef CONFIG_PMAC_BACKLIGHT
2709         if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2710                 set_backlight_enable(1);
2711 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2712         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2713             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2714                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2715                 pm |= PWR_BLON;
2716                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2717         }
2718 #endif
2719
2720         return 0;
2721 }
2722
2723 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2724                        const struct atyfb_par *par)
2725 {
2726 #ifdef CONFIG_ATARI
2727         out_8(&par->aty_cmap_regs->windex, regno);
2728         out_8(&par->aty_cmap_regs->lut, red);
2729         out_8(&par->aty_cmap_regs->lut, green);
2730         out_8(&par->aty_cmap_regs->lut, blue);
2731 #else
2732         writeb(regno, &par->aty_cmap_regs->windex);
2733         writeb(red, &par->aty_cmap_regs->lut);
2734         writeb(green, &par->aty_cmap_regs->lut);
2735         writeb(blue, &par->aty_cmap_regs->lut);
2736 #endif
2737 }
2738
2739     /*
2740      *  Set a single color register. The values supplied are already
2741      *  rounded down to the hardware's capabilities (according to the
2742      *  entries in the var structure). Return != 0 for invalid regno.
2743      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2744      */
2745
2746 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2747         u_int transp, struct fb_info *info)
2748 {
2749         struct atyfb_par *par = (struct atyfb_par *) info->par;
2750         int i, depth;
2751         u32 *pal = info->pseudo_palette;
2752
2753         depth = info->var.bits_per_pixel;
2754         if (depth == 16)
2755                 depth = (info->var.green.length == 5) ? 15 : 16;
2756
2757         if (par->asleep)
2758                 return 0;
2759
2760         if (regno > 255 ||
2761             (depth == 16 && regno > 63) ||
2762             (depth == 15 && regno > 31))
2763                 return 1;
2764
2765         red >>= 8;
2766         green >>= 8;
2767         blue >>= 8;
2768
2769         par->palette[regno].red = red;
2770         par->palette[regno].green = green;
2771         par->palette[regno].blue = blue;
2772
2773         if (regno < 16) {
2774                 switch (depth) {
2775                 case 15:
2776                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2777                         break;
2778                 case 16:
2779                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2780                         break;
2781                 case 24:
2782                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2783                         break;
2784                 case 32:
2785                         i = (regno << 8) | regno;
2786                         pal[regno] = (i << 16) | i;
2787                         break;
2788                 }
2789         }
2790
2791         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2792         if (M64_HAS(EXTRA_BRIGHT))
2793                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2794         aty_st_8(DAC_CNTL, i, par);
2795         aty_st_8(DAC_MASK, 0xff, par);
2796
2797         if (M64_HAS(INTEGRATED)) {
2798                 if (depth == 16) {
2799                         if (regno < 32)
2800                                 aty_st_pal(regno << 3, red,
2801                                            par->palette[regno<<1].green,
2802                                            blue, par);
2803                         red = par->palette[regno>>1].red;
2804                         blue = par->palette[regno>>1].blue;
2805                         regno <<= 2;
2806                 } else if (depth == 15) {
2807                         regno <<= 3;
2808                         for(i = 0; i < 8; i++) {
2809                             aty_st_pal(regno + i, red, green, blue, par);
2810                         }
2811                 }
2812         }
2813         aty_st_pal(regno, red, green, blue, par);
2814
2815         return 0;
2816 }
2817
2818 #ifdef CONFIG_PCI
2819
2820 #ifdef __sparc__
2821
2822 extern void (*prom_palette) (int);
2823
2824 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2825                         struct fb_info *info, unsigned long addr)
2826 {
2827         extern int con_is_present(void);
2828
2829         struct atyfb_par *par = info->par;
2830         struct pcidev_cookie *pcp;
2831         char prop[128];
2832         int node, len, i, j, ret;
2833         u32 mem, chip_id;
2834
2835         /* Do not attach when we have a serial console. */
2836         if (!con_is_present())
2837                 return -ENXIO;
2838
2839         /*
2840          * Map memory-mapped registers.
2841          */
2842         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2843         info->fix.mmio_start = addr + 0x7ffc00UL;
2844
2845         /*
2846          * Map in big-endian aperture.
2847          */
2848         info->screen_base = (char *) (addr + 0x800000UL);
2849         info->fix.smem_start = addr + 0x800000UL;
2850
2851         /*
2852          * Figure mmap addresses from PCI config space.
2853          * Split Framebuffer in big- and little-endian halfs.
2854          */
2855         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2856                 /* nothing */ ;
2857         j = i + 4;
2858
2859         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2860         if (!par->mmap_map) {
2861                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2862                 return -ENOMEM;
2863         }
2864         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2865
2866         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2867                 struct resource *rp = &pdev->resource[i];
2868                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2869                 unsigned long base;
2870                 u32 size, pbase;
2871
2872                 base = rp->start;
2873
2874                 io = (rp->flags & IORESOURCE_IO);
2875
2876                 size = rp->end - base + 1;
2877
2878                 pci_read_config_dword(pdev, breg, &pbase);
2879
2880                 if (io)
2881                         size &= ~1;
2882
2883                 /*
2884                  * Map the framebuffer a second time, this time without
2885                  * the braindead _PAGE_IE setting. This is used by the
2886                  * fixed Xserver, but we need to maintain the old mapping
2887                  * to stay compatible with older ones...
2888                  */
2889                 if (base == addr) {
2890                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2891                         par->mmap_map[j].poff = base & PAGE_MASK;
2892                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2893                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2894                         par->mmap_map[j].prot_flag = _PAGE_E;
2895                         j++;
2896                 }
2897
2898                 /*
2899                  * Here comes the old framebuffer mapping with _PAGE_IE
2900                  * set for the big endian half of the framebuffer...
2901                  */
2902                 if (base == addr) {
2903                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2904                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2905                         par->mmap_map[j].size = 0x800000;
2906                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2907                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2908                         size -= 0x800000;
2909                         j++;
2910                 }
2911
2912                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2913                 par->mmap_map[j].poff = base & PAGE_MASK;
2914                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2915                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2916                 par->mmap_map[j].prot_flag = _PAGE_E;
2917                 j++;
2918         }
2919
2920         if((ret = correct_chipset(par)))
2921                 return ret;
2922
2923         if (IS_XL(pdev->device)) {
2924                 /*
2925                  * Fix PROMs idea of MEM_CNTL settings...
2926                  */
2927                 mem = aty_ld_le32(MEM_CNTL, par);
2928                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2929                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2930                         switch (mem & 0x0f) {
2931                         case 3:
2932                                 mem = (mem & ~(0x0f)) | 2;
2933                                 break;
2934                         case 7:
2935                                 mem = (mem & ~(0x0f)) | 3;
2936                                 break;
2937                         case 9:
2938                                 mem = (mem & ~(0x0f)) | 4;
2939                                 break;
2940                         case 11:
2941                                 mem = (mem & ~(0x0f)) | 5;
2942                                 break;
2943                         default:
2944                                 break;
2945                         }
2946                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2947                                 mem &= ~(0x00700000);
2948                 }
2949                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2950                 aty_st_le32(MEM_CNTL, mem, par);
2951         }
2952
2953         /*
2954          * If this is the console device, we will set default video
2955          * settings to what the PROM left us with.
2956          */
2957         node = prom_getchild(prom_root_node);
2958         node = prom_searchsiblings(node, "aliases");
2959         if (node) {
2960                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2961                 if (len > 0) {
2962                         prop[len] = '\0';
2963                         node = prom_finddevice(prop);
2964                 } else
2965                         node = 0;
2966         }
2967
2968         pcp = pdev->sysdata;
2969         if (node == pcp->prom_node) {
2970                 struct fb_var_screeninfo *var = &default_var;
2971                 unsigned int N, P, Q, M, T, R;
2972                 u32 v_total, h_total;
2973                 struct crtc crtc;
2974                 u8 pll_regs[16];
2975                 u8 clock_cntl;
2976
2977                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2978                 crtc.vyres = prom_getintdefault(node, "height", 768);
2979                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2980                 var->xoffset = var->yoffset = 0;
2981                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2982                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2983                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2984                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2985                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2986                 aty_crtc_to_var(&crtc, var);
2987
2988                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2989                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2990
2991                 /*
2992                  * Read the PLL to figure actual Refresh Rate.
2993                  */
2994                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2995                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2996                 for (i = 0; i < 16; i++)
2997                         pll_regs[i] = aty_ld_pll_ct(i, par);
2998
2999                 /*
3000                  * PLL Reference Divider M:
3001                  */
3002                 M = pll_regs[2];
3003
3004                 /*
3005                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3006                  */
3007                 N = pll_regs[7 + (clock_cntl & 3)];
3008
3009                 /*
3010                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3011                  */
3012                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3013
3014                 /*
3015                  * PLL Divider Q:
3016                  */
3017                 Q = N / P;
3018
3019                 /*
3020                  * Target Frequency:
3021                  *
3022                  *      T * M
3023                  * Q = -------
3024                  *      2 * R
3025                  *
3026                  * where R is XTALIN (= 14318 or 29498 kHz).
3027                  */
3028                 if (IS_XL(pdev->device))
3029                         R = 29498;
3030                 else
3031                         R = 14318;
3032
3033                 T = 2 * Q * R / M;
3034
3035                 default_var.pixclock = 1000000000 / T;
3036         }
3037
3038         return 0;
3039 }
3040
3041 #else /* __sparc__ */
3042
3043 #ifdef __i386__
3044 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3045 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3046 {
3047         u32 driv_inf_tab, sig;
3048         u16 lcd_ofs;
3049
3050         /* To support an LCD panel, we should know it's dimensions and
3051          *  it's desired pixel clock.
3052          * There are two ways to do it:
3053          *  - Check the startup video mode and calculate the panel
3054          *    size from it. This is unreliable.
3055          *  - Read it from the driver information table in the video BIOS.
3056         */
3057         /* Address of driver information table is at offset 0x78. */
3058         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3059
3060         /* Check for the driver information table signature. */
3061         sig = (*(u32 *)driv_inf_tab);
3062         if ((sig == 0x54504c24) || /* Rage LT pro */
3063                 (sig == 0x544d5224) || /* Rage mobility */
3064                 (sig == 0x54435824) || /* Rage XC */
3065                 (sig == 0x544c5824)) { /* Rage XL */
3066                 PRINTKI("BIOS contains driver information table.\n");
3067                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3068                 par->lcd_table = 0;
3069                 if (lcd_ofs != 0) {
3070                         par->lcd_table = bios_base + lcd_ofs;
3071                 }
3072         }
3073
3074         if (par->lcd_table != 0) {
3075                 char model[24];
3076                 char strbuf[16];
3077                 char refresh_rates_buf[100];
3078                 int id, tech, f, i, m, default_refresh_rate;
3079                 char *txtcolour;
3080                 char *txtmonitor;
3081                 char *txtdual;
3082                 char *txtformat;
3083                 u16 width, height, panel_type, refresh_rates;
3084                 u16 *lcdmodeptr;
3085                 u32 format;
3086                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3087                 /* The most important information is the panel size at
3088                  * offset 25 and 27, but there's some other nice information
3089                  * which we print to the screen.
3090                  */
3091                 id = *(u8 *)par->lcd_table;
3092                 strncpy(model,(char *)par->lcd_table+1,24);
3093                 model[23]=0;
3094
3095                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3096                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3097                 panel_type = *(u16 *)(par->lcd_table+29);
3098                 if (panel_type & 1)
3099                         txtcolour = "colour";
3100                 else
3101                         txtcolour = "monochrome";
3102                 if (panel_type & 2)
3103                         txtdual = "dual (split) ";
3104                 else
3105                         txtdual = "";
3106                 tech = (panel_type>>2) & 63;
3107                 switch (tech) {
3108                 case 0:
3109                         txtmonitor = "passive matrix";
3110                         break;
3111                 case 1:
3112                         txtmonitor = "active matrix";
3113                         break;
3114                 case 2:
3115                         txtmonitor = "active addressed STN";
3116                         break;
3117                 case 3:
3118                         txtmonitor = "EL";
3119                         break;
3120                 case 4:
3121                         txtmonitor = "plasma";
3122                         break;
3123                 default:
3124                         txtmonitor = "unknown";
3125                 }
3126                 format = *(u32 *)(par->lcd_table+57);
3127                 if (tech == 0 || tech == 2) {
3128                         switch (format & 7) {
3129                         case 0:
3130                                 txtformat = "12 bit interface";
3131                                 break;
3132                         case 1:
3133                                 txtformat = "16 bit interface";
3134                                 break;
3135                         case 2:
3136                                 txtformat = "24 bit interface";
3137                                 break;
3138                         default:
3139                                 txtformat = "unkown format";
3140                         }
3141                 } else {
3142                         switch (format & 7) {
3143                         case 0:
3144                                 txtformat = "8 colours";
3145                                 break;
3146                         case 1:
3147                                 txtformat = "512 colours";
3148                                 break;
3149                         case 2:
3150                                 txtformat = "4096 colours";
3151                                 break;
3152                         case 4:
3153                                 txtformat = "262144 colours (LT mode)";
3154                                 break;
3155                         case 5:
3156                                 txtformat = "16777216 colours";
3157                                 break;
3158                         case 6:
3159                                 txtformat = "262144 colours (FDPI-2 mode)";
3160                                 break;
3161                         default:
3162                                 txtformat = "unkown format";
3163                         }
3164                 }
3165                 PRINTKI("%s%s %s monitor detected: %s\n",
3166                         txtdual ,txtcolour, txtmonitor, model);
3167                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3168                         id, width, height, txtformat);
3169                 refresh_rates_buf[0] = 0;
3170                 refresh_rates = *(u16 *)(par->lcd_table+62);
3171                 m = 1;
3172                 f = 0;
3173                 for (i=0;i<16;i++) {
3174                         if (refresh_rates & m) {
3175                                 if (f == 0) {
3176                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3177                                         f++;
3178                                 } else {
3179                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3180                                 }
3181                                 strcat(refresh_rates_buf,strbuf);
3182                         }
3183                         m = m << 1;
3184                 }
3185                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3186                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3187                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3188                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3189                 /* We now need to determine the crtc parameters for the
3190                  * LCD monitor. This is tricky, because they are not stored
3191                  * individually in the BIOS. Instead, the BIOS contains a
3192                  * table of display modes that work for this monitor.
3193                  *
3194                  * The idea is that we search for a mode of the same dimensions
3195                  * as the dimensions of the LCD monitor. Say our LCD monitor
3196                  * is 800x600 pixels, we search for a 800x600 monitor.
3197                  * The CRTC parameters we find here are the ones that we need
3198                  * to use to simulate other resolutions on the LCD screen.
3199                  */
3200                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3201                 while (*lcdmodeptr != 0) {
3202                         u32 modeptr;
3203                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3204                         modeptr = bios_base + *lcdmodeptr;
3205
3206                         mwidth = *((u16 *)(modeptr+0));
3207                         mheight = *((u16 *)(modeptr+2));
3208
3209                         if (mwidth == width && mheight == height) {
3210                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3211                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3212                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3213                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3214                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3215                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3216
3217                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3218                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3219                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3220                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3221
3222                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3223                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3224                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3225                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3226
3227                                 par->lcd_vtotal++;
3228                                 par->lcd_vdisp++;
3229                                 lcd_vsync_start++;
3230
3231                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3232                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3233                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3234                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3235                                 break;
3236                         }
3237
3238                         lcdmodeptr++;
3239                 }
3240                 if (*lcdmodeptr == 0) {
3241                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3242                         /* To do: Switch to CRT if possible. */
3243                 } else {
3244                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3245                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3246                                 par->lcd_hdisp,
3247                                 par->lcd_hdisp + par->lcd_right_margin,
3248                                 par->lcd_hdisp + par->lcd_right_margin
3249                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3250                                 par->lcd_htotal,
3251                                 par->lcd_vdisp,
3252                                 par->lcd_vdisp + par->lcd_lower_margin,
3253                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3254                                 par->lcd_vtotal);
3255                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3256                                 par->lcd_pixclock,
3257                                 par->lcd_hblank_len - (par->lcd_right_margin +
3258                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3259                                 par->lcd_hdisp,
3260                                 par->lcd_right_margin,
3261                                 par->lcd_hsync_len,
3262                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3263                                 par->lcd_vdisp,
3264                                 par->lcd_lower_margin,
3265                                 par->lcd_vsync_len);
3266                 }
3267         }
3268 }
3269 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3270
3271 static int __devinit init_from_bios(struct atyfb_par *par)
3272 {
3273         u32 bios_base, rom_addr;
3274         int ret;
3275
3276         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3277         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3278
3279         /* The BIOS starts with 0xaa55. */
3280         if (*((u16 *)bios_base) == 0xaa55) {
3281
3282                 u8 *bios_ptr;
3283                 u16 rom_table_offset, freq_table_offset;
3284                 PLL_BLOCK_MACH64 pll_block;
3285
3286                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3287
3288                 /* check for frequncy table */
3289                 bios_ptr = (u8*)bios_base;
3290                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3291                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3292                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3293
3294                 PRINTKI("BIOS frequency table:\n");
3295                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3296                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3297                         pll_block.ref_freq, pll_block.ref_divider);
3298                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3299                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3300                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3301
3302                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3303                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3304                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3305                 par->pll_limits.ref_div = pll_block.ref_divider;
3306                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3307                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3308                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3309                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3310 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3311                 aty_init_lcd(par, bios_base);
3312 #endif
3313                 ret = 0;
3314         } else {
3315                 PRINTKE("no BIOS frequency table found, use parameters\n");
3316                 ret = -ENXIO;
3317         }
3318         iounmap((void* __iomem )bios_base);
3319
3320         return ret;
3321 }
3322 #endif /* __i386__ */
3323
3324 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3325 {
3326         struct atyfb_par *par = info->par;
3327         u16 tmp;
3328         unsigned long raddr;
3329         struct resource *rrp;
3330         int ret = 0;
3331
3332         raddr = addr + 0x7ff000UL;
3333         rrp = &pdev->resource[2];
3334         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3335                 par->aux_start = rrp->start;
3336                 par->aux_size = rrp->end - rrp->start + 1;
3337                 raddr = rrp->start;
3338                 PRINTKI("using auxiliary register aperture\n");
3339         }
3340
3341         info->fix.mmio_start = raddr;
3342         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3343         if (par->ati_regbase == 0)
3344                 return -ENOMEM;
3345
3346         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3347         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3348
3349         /*
3350          * Enable memory-space accesses using config-space
3351          * command register.
3352          */
3353         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3354         if (!(tmp & PCI_COMMAND_MEMORY)) {
3355                 tmp |= PCI_COMMAND_MEMORY;
3356                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3357         }
3358 #ifdef __BIG_ENDIAN
3359         /* Use the big-endian aperture */
3360         addr += 0x800000;
3361 #endif
3362
3363         /* Map in frame buffer */
3364         info->fix.smem_start = addr;
3365         info->screen_base = ioremap(addr, 0x800000);
3366         if (info->screen_base == NULL) {
3367                 ret = -ENOMEM;
3368                 goto atyfb_setup_generic_fail;
3369         }
3370
3371         if((ret = correct_chipset(par)))
3372                 goto atyfb_setup_generic_fail;
3373 #ifdef __i386__
3374         if((ret = init_from_bios(par)))
3375                 goto atyfb_setup_generic_fail;
3376 #endif
3377         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3378                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3379         else
3380                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3381
3382         /* according to ATI, we should use clock 3 for acelerated mode */
3383         par->clk_wr_offset = 3;
3384
3385         return 0;
3386
3387 atyfb_setup_generic_fail:
3388         iounmap(par->ati_regbase);
3389         par->ati_regbase = NULL;
3390         return ret;
3391 }
3392
3393 #endif /* !__sparc__ */
3394
3395 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3396 {
3397         unsigned long addr, res_start, res_size;
3398         struct fb_info *info;
3399         struct resource *rp;
3400         struct atyfb_par *par;
3401         int i, rc = -ENOMEM;
3402
3403         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3404                 if (pdev->device == aty_chips[i].pci_id)
3405                         break;
3406
3407         if (i < 0)
3408                 return -ENODEV;
3409
3410         /* Enable device in PCI config */
3411         if (pci_enable_device(pdev)) {
3412                 PRINTKE("Cannot enable PCI device\n");
3413                 return -ENXIO;
3414         }
3415
3416         /* Find which resource to use */
3417         rp = &pdev->resource[0];
3418         if (rp->flags & IORESOURCE_IO)
3419                 rp = &pdev->resource[1];
3420         addr = rp->start;
3421         if (!addr)
3422                 return -ENXIO;
3423
3424         /* Reserve space */
3425         res_start = rp->start;
3426         res_size = rp->end - rp->start + 1;
3427         if (!request_mem_region (res_start, res_size, "atyfb"))
3428                 return -EBUSY;
3429
3430         /* Allocate framebuffer */
3431         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3432         if (!info) {
3433                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3434                 return -ENOMEM;
3435         }
3436         par = info->par;
3437         info->fix = atyfb_fix;
3438         info->device = &pdev->dev;
3439         par->pci_id = aty_chips[i].pci_id;
3440         par->res_start = res_start;
3441         par->res_size = res_size;
3442         par->irq = pdev->irq;
3443
3444         /* Setup "info" structure */
3445 #ifdef __sparc__
3446         rc = atyfb_setup_sparc(pdev, info, addr);
3447 #else
3448         rc = atyfb_setup_generic(pdev, info, addr);
3449 #endif
3450         if (rc)
3451                 goto err_release_mem;
3452
3453         pci_set_drvdata(pdev, info);
3454
3455         /* Init chip & register framebuffer */
3456         if (aty_init(info, "PCI"))
3457                 goto err_release_io;
3458
3459 #ifdef __sparc__
3460         if (!prom_palette)
3461                 prom_palette = atyfb_palette;
3462
3463         /*
3464          * Add /dev/fb mmap values.
3465          */
3466         par->mmap_map[0].voff = 0x8000000000000000UL;
3467         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3468         par->mmap_map[0].size = info->fix.smem_len;
3469         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3470         par->mmap_map[0].prot_flag = _PAGE_E;
3471         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3472         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3473         par->mmap_map[1].size = PAGE_SIZE;
3474         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3475         par->mmap_map[1].prot_flag = _PAGE_E;
3476 #endif /* __sparc__ */
3477
3478         return 0;
3479
3480 err_release_io:
3481 #ifdef __sparc__
3482         kfree(par->mmap_map);
3483 #else
3484         if (par->ati_regbase)
3485                 iounmap(par->ati_regbase);
3486         if (info->screen_base)
3487                 iounmap(info->screen_base);
3488 #endif
3489 err_release_mem:
3490         if (par->aux_start)
3491                 release_mem_region(par->aux_start, par->aux_size);
3492
3493         release_mem_region(par->res_start, par->res_size);
3494         framebuffer_release(info);
3495
3496         return rc;
3497 }
3498
3499 #endif /* CONFIG_PCI */
3500
3501 #ifdef CONFIG_ATARI
3502
3503 static int __devinit atyfb_atari_probe(void)
3504 {
3505         struct atyfb_par *par;
3506         struct fb_info *info;
3507         int m64_num;
3508         u32 clock_r;
3509
3510         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3511                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3512                     !phys_guiregbase[m64_num]) {
3513                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3514                         continue;
3515                 }
3516
3517                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3518                 if (!info) {
3519                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3520                         return -ENOMEM;
3521                 }
3522                 par = info->par;
3523
3524                 info->fix = atyfb_fix;
3525
3526                 par->irq = (unsigned int) -1; /* something invalid */
3527
3528                 /*
3529                  *  Map the video memory (physical address given) to somewhere in the
3530                  *  kernel address space.
3531                  */
3532                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3533                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3534                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3535                                                 0xFC00ul;
3536                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3537
3538                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3539                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3540
3541                 switch (clock_r & 0x003F) {
3542                 case 0x12:
3543                         par->clk_wr_offset = 3; /*  */
3544                         break;
3545                 case 0x34:
3546                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3547                         break;
3548                 case 0x16:
3549                         par->clk_wr_offset = 1; /*  */
3550                         break;
3551                 case 0x38:
3552                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3553                         break;
3554                 }
3555
3556                 if (aty_init(info, "ISA bus")) {
3557                         framebuffer_release(info);
3558                         /* This is insufficient! kernel_map has added two large chunks!! */
3559                         return -ENXIO;
3560                 }
3561         }
3562 }
3563
3564 #endif /* CONFIG_ATARI */
3565
3566 static void __devexit atyfb_remove(struct fb_info *info)
3567 {
3568         struct atyfb_par *par = (struct atyfb_par *) info->par;
3569
3570         /* restore video mode */
3571         aty_set_crtc(par, &saved_crtc);
3572         par->pll_ops->set_pll(info, &saved_pll);
3573
3574         unregister_framebuffer(info);
3575
3576 #ifdef CONFIG_MTRR
3577         if (par->mtrr_reg >= 0) {
3578             mtrr_del(par->mtrr_reg, 0, 0);
3579             par->mtrr_reg = -1;
3580         }
3581         if (par->mtrr_aper >= 0) {
3582             mtrr_del(par->mtrr_aper, 0, 0);
3583             par->mtrr_aper = -1;
3584         }
3585 #endif
3586 #ifndef __sparc__
3587         if (par->ati_regbase)
3588                 iounmap(par->ati_regbase);
3589         if (info->screen_base)
3590                 iounmap(info->screen_base);
3591 #ifdef __BIG_ENDIAN
3592         if (info->sprite.addr)
3593                 iounmap(info->sprite.addr);
3594 #endif
3595 #endif
3596 #ifdef __sparc__
3597         kfree(par->mmap_map);
3598 #endif
3599         if (par->aux_start)
3600                 release_mem_region(par->aux_start, par->aux_size);
3601
3602         if (par->res_start)
3603                 release_mem_region(par->res_start, par->res_size);
3604
3605         framebuffer_release(info);
3606 }
3607
3608 #ifdef CONFIG_PCI
3609
3610 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3611 {
3612         struct fb_info *info = pci_get_drvdata(pdev);
3613
3614         atyfb_remove(info);
3615 }
3616
3617 /*
3618  * This driver uses its own matching table. That will be more difficult
3619  * to fix, so for now, we just match against any ATI ID and let the
3620  * probe() function find out what's up. That also mean we don't have
3621  * a module ID table though.
3622  */
3623 static struct pci_device_id atyfb_pci_tbl[] = {
3624         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3625           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3626         { 0, }
3627 };
3628
3629 static struct pci_driver atyfb_driver = {
3630         .name           = "atyfb",
3631         .id_table       = atyfb_pci_tbl,
3632         .probe          = atyfb_pci_probe,
3633         .remove         = __devexit_p(atyfb_pci_remove),
3634 #ifdef CONFIG_PM
3635         .suspend        = atyfb_pci_suspend,
3636         .resume         = atyfb_pci_resume,
3637 #endif /* CONFIG_PM */
3638 };
3639
3640 #endif /* CONFIG_PCI */
3641
3642 #ifndef MODULE
3643 static int __init atyfb_setup(char *options)
3644 {
3645         char *this_opt;
3646
3647         if (!options || !*options)
3648                 return 0;
3649
3650         while ((this_opt = strsep(&options, ",")) != NULL) {
3651                 if (!strncmp(this_opt, "noaccel", 7)) {
3652                         noaccel = 1;
3653 #ifdef CONFIG_MTRR
3654                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3655                         nomtrr = 1;
3656 #endif
3657                 } else if (!strncmp(this_opt, "vram:", 5))
3658                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3659                 else if (!strncmp(this_opt, "pll:", 4))
3660                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3661                 else if (!strncmp(this_opt, "mclk:", 5))
3662                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3663                 else if (!strncmp(this_opt, "xclk:", 5))
3664                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3665                 else if (!strncmp(this_opt, "comp_sync:", 10))
3666                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3667 #ifdef CONFIG_PPC
3668                 else if (!strncmp(this_opt, "vmode:", 6)) {
3669                         unsigned int vmode =
3670                             simple_strtoul(this_opt + 6, NULL, 0);
3671                         if (vmode > 0 && vmode <= VMODE_MAX)
3672                                 default_vmode = vmode;
3673                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3674                         unsigned int cmode =
3675                             simple_strtoul(this_opt + 6, NULL, 0);
3676                         switch (cmode) {
3677                         case 0:
3678                         case 8:
3679                                 default_cmode = CMODE_8;
3680                                 break;
3681                         case 15:
3682                         case 16:
3683                                 default_cmode = CMODE_16;
3684                                 break;
3685                         case 24:
3686                         case 32:
3687                                 default_cmode = CMODE_32;
3688                                 break;
3689                         }
3690                 }
3691 #endif
3692 #ifdef CONFIG_ATARI
3693                 /*
3694                  * Why do we need this silly Mach64 argument?
3695                  * We are already here because of mach64= so its redundant.
3696                  */
3697                 else if (MACH_IS_ATARI
3698                          && (!strncmp(this_opt, "Mach64:", 7))) {
3699                         static unsigned char m64_num;
3700                         static char mach64_str[80];
3701                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3702                         if (!store_video_par(mach64_str, m64_num)) {
3703                                 m64_num++;
3704                                 mach64_count = m64_num;
3705                         }
3706                 }
3707 #endif
3708                 else
3709                         mode = this_opt;
3710         }
3711         return 0;
3712 }
3713 #endif  /*  MODULE  */
3714
3715 static int __init atyfb_init(void)
3716 {
3717 #ifndef MODULE
3718     char *option = NULL;
3719
3720     if (fb_get_options("atyfb", &option))
3721         return -ENODEV;
3722     atyfb_setup(option);
3723 #endif
3724
3725 #ifdef CONFIG_PCI
3726     pci_register_driver(&atyfb_driver);
3727 #endif
3728 #ifdef CONFIG_ATARI
3729     atyfb_atari_probe();
3730 #endif
3731     return 0;
3732 }
3733
3734 static void __exit atyfb_exit(void)
3735 {
3736 #ifdef CONFIG_PCI
3737         pci_unregister_driver(&atyfb_driver);
3738 #endif
3739 }
3740
3741 module_init(atyfb_init);
3742 module_exit(atyfb_exit);
3743
3744 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3745 MODULE_LICENSE("GPL");
3746 module_param(noaccel, bool, 0);
3747 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3748 module_param(vram, int, 0);
3749 MODULE_PARM_DESC(vram, "int: override size of video ram");
3750 module_param(pll, int, 0);
3751 MODULE_PARM_DESC(pll, "int: override video clock");
3752 module_param(mclk, int, 0);
3753 MODULE_PARM_DESC(mclk, "int: override memory clock");
3754 module_param(xclk, int, 0);
3755 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3756 module_param(comp_sync, int, 0);
3757 MODULE_PARM_DESC(comp_sync,
3758                  "Set composite sync signal to low (0) or high (1)");
3759 module_param(mode, charp, 0);
3760 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3761 #ifdef CONFIG_MTRR
3762 module_param(nomtrr, bool, 0);
3763 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3764 #endif